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ASoC: rt5645: use polling to support HS button
[linux-2.6-block.git] / sound / soc / codecs / rt5645.c
CommitLineData
1319b2f6
OC		 1/*
2 * rt5645.c -- RT5645 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/platform_device.h>
19#include <linux/spi/spi.h>
f3fa1bbd 20#include <linux/gpio.h>
baf2a0e1 21#include <linux/gpio/consumer.h>
3168c201 22#include <linux/acpi.h>
78c34fd4 23#include <linux/dmi.h>
9fc114c5 24#include <linux/regulator/consumer.h>
1319b2f6
OC		 25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/jack.h>
29#include <sound/soc.h>
30#include <sound/soc-dapm.h>
31#include <sound/initval.h>
32#include <sound/tlv.h>
33
49ef7925 34#include "rl6231.h"
1319b2f6
OC		 35#include "rt5645.h"
36
37#define RT5645_DEVICE_ID 0x6308
5c4ca99d 38#define RT5650_DEVICE_ID 0x6419
1319b2f6
OC		 39
40#define RT5645_PR_RANGE_BASE (0xff + 1)
41#define RT5645_PR_SPACING 0x100
42
43#define RT5645_PR_BASE (RT5645_PR_RANGE_BASE + (0 * RT5645_PR_SPACING))
44
be77b38a
OC		 45#define RT5645_HWEQ_NUM 57
46
1319b2f6
OC		 47static const struct regmap_range_cfg rt5645_ranges[] = {
48 {
49 .name = "PR",
50 .range_min = RT5645_PR_BASE,
51 .range_max = RT5645_PR_BASE + 0xf8,
52 .selector_reg = RT5645_PRIV_INDEX,
53 .selector_mask = 0xff,
54 .selector_shift = 0x0,
55 .window_start = RT5645_PRIV_DATA,
56 .window_len = 0x1,
57 },
58};
59
8019ff6c 60static const struct reg_sequence init_list[] = {
1319b2f6 61 {RT5645_PR_BASE + 0x3d, 0x3600},
4809b96e
OC		 62 {RT5645_PR_BASE + 0x1c, 0xfd20},
63 {RT5645_PR_BASE + 0x20, 0x611f},
64 {RT5645_PR_BASE + 0x21, 0x4040},
65 {RT5645_PR_BASE + 0x23, 0x0004},
1319b2f6
OC		 66};
67#define RT5645_INIT_REG_LEN ARRAY_SIZE(init_list)
68
8019ff6c 69static const struct reg_sequence rt5650_init_list[] = {
5c4ca99d
BL		 70 {0xf6, 0x0100},
71};
72
1319b2f6
OC		 73static const struct reg_default rt5645_reg[] = {
74 { 0x00, 0x0000 },
75 { 0x01, 0xc8c8 },
76 { 0x02, 0xc8c8 },
77 { 0x03, 0xc8c8 },
78 { 0x0a, 0x0002 },
79 { 0x0b, 0x2827 },
80 { 0x0c, 0xe000 },
81 { 0x0d, 0x0000 },
82 { 0x0e, 0x0000 },
83 { 0x0f, 0x0808 },
84 { 0x14, 0x3333 },
85 { 0x16, 0x4b00 },
86 { 0x18, 0x018b },
87 { 0x19, 0xafaf },
88 { 0x1a, 0xafaf },
89 { 0x1b, 0x0001 },
90 { 0x1c, 0x2f2f },
91 { 0x1d, 0x2f2f },
92 { 0x1e, 0x0000 },
93 { 0x20, 0x0000 },
94 { 0x27, 0x7060 },
95 { 0x28, 0x7070 },
96 { 0x29, 0x8080 },
97 { 0x2a, 0x5656 },
98 { 0x2b, 0x5454 },
99 { 0x2c, 0xaaa0 },
5c4ca99d 100 { 0x2d, 0x0000 },
1319b2f6
OC		 101 { 0x2f, 0x1002 },
102 { 0x31, 0x5000 },
103 { 0x32, 0x0000 },
104 { 0x33, 0x0000 },
105 { 0x34, 0x0000 },
106 { 0x35, 0x0000 },
107 { 0x3b, 0x0000 },
108 { 0x3c, 0x007f },
109 { 0x3d, 0x0000 },
110 { 0x3e, 0x007f },
111 { 0x3f, 0x0000 },
112 { 0x40, 0x001f },
113 { 0x41, 0x0000 },
114 { 0x42, 0x001f },
115 { 0x45, 0x6000 },
116 { 0x46, 0x003e },
117 { 0x47, 0x003e },
118 { 0x48, 0xf807 },
119 { 0x4a, 0x0004 },
120 { 0x4d, 0x0000 },
121 { 0x4e, 0x0000 },
122 { 0x4f, 0x01ff },
123 { 0x50, 0x0000 },
124 { 0x51, 0x0000 },
125 { 0x52, 0x01ff },
126 { 0x53, 0xf000 },
127 { 0x56, 0x0111 },
128 { 0x57, 0x0064 },
129 { 0x58, 0xef0e },
130 { 0x59, 0xf0f0 },
131 { 0x5a, 0xef0e },
132 { 0x5b, 0xf0f0 },
133 { 0x5c, 0xef0e },
134 { 0x5d, 0xf0f0 },
135 { 0x5e, 0xf000 },
136 { 0x5f, 0x0000 },
137 { 0x61, 0x0300 },
138 { 0x62, 0x0000 },
139 { 0x63, 0x00c2 },
140 { 0x64, 0x0000 },
141 { 0x65, 0x0000 },
142 { 0x66, 0x0000 },
143 { 0x6a, 0x0000 },
144 { 0x6c, 0x0aaa },
145 { 0x70, 0x8000 },
146 { 0x71, 0x8000 },
147 { 0x72, 0x8000 },
148 { 0x73, 0x7770 },
149 { 0x74, 0x3e00 },
150 { 0x75, 0x2409 },
151 { 0x76, 0x000a },
152 { 0x77, 0x0c00 },
153 { 0x78, 0x0000 },
df078d29 154 { 0x79, 0x0123 },
1319b2f6
OC		 155 { 0x80, 0x0000 },
156 { 0x81, 0x0000 },
157 { 0x82, 0x0000 },
158 { 0x83, 0x0000 },
159 { 0x84, 0x0000 },
160 { 0x85, 0x0000 },
161 { 0x8a, 0x0000 },
162 { 0x8e, 0x0004 },
163 { 0x8f, 0x1100 },
164 { 0x90, 0x0646 },
165 { 0x91, 0x0c06 },
166 { 0x93, 0x0000 },
167 { 0x94, 0x0200 },
168 { 0x95, 0x0000 },
169 { 0x9a, 0x2184 },
170 { 0x9b, 0x010a },
171 { 0x9c, 0x0aea },
172 { 0x9d, 0x000c },
173 { 0x9e, 0x0400 },
174 { 0xa0, 0xa0a8 },
175 { 0xa1, 0x0059 },
176 { 0xa2, 0x0001 },
177 { 0xae, 0x6000 },
178 { 0xaf, 0x0000 },
179 { 0xb0, 0x6000 },
180 { 0xb1, 0x0000 },
181 { 0xb2, 0x0000 },
182 { 0xb3, 0x001f },
183 { 0xb4, 0x020c },
184 { 0xb5, 0x1f00 },
185 { 0xb6, 0x0000 },
186 { 0xbb, 0x0000 },
187 { 0xbc, 0x0000 },
188 { 0xbd, 0x0000 },
189 { 0xbe, 0x0000 },
190 { 0xbf, 0x3100 },
191 { 0xc0, 0x0000 },
192 { 0xc1, 0x0000 },
193 { 0xc2, 0x0000 },
194 { 0xc3, 0x2000 },
195 { 0xcd, 0x0000 },
196 { 0xce, 0x0000 },
197 { 0xcf, 0x1813 },
198 { 0xd0, 0x0690 },
199 { 0xd1, 0x1c17 },
200 { 0xd3, 0xb320 },
201 { 0xd4, 0x0000 },
202 { 0xd6, 0x0400 },
203 { 0xd9, 0x0809 },
204 { 0xda, 0x0000 },
205 { 0xdb, 0x0003 },
206 { 0xdc, 0x0049 },
207 { 0xdd, 0x001b },
5c4ca99d
BL		 208 { 0xdf, 0x0008 },
209 { 0xe0, 0x4000 },
1319b2f6
OC		 210 { 0xe6, 0x8000 },
211 { 0xe7, 0x0200 },
212 { 0xec, 0xb300 },
213 { 0xed, 0x0000 },
214 { 0xf0, 0x001f },
215 { 0xf1, 0x020c },
216 { 0xf2, 0x1f00 },
217 { 0xf3, 0x0000 },
218 { 0xf4, 0x4000 },
219 { 0xf8, 0x0000 },
220 { 0xf9, 0x0000 },
221 { 0xfa, 0x2060 },
222 { 0xfb, 0x4040 },
223 { 0xfc, 0x0000 },
224 { 0xfd, 0x0002 },
225 { 0xfe, 0x10ec },
226 { 0xff, 0x6308 },
227};
228
49abc6cd
BL		 229static const struct reg_default rt5650_reg[] = {
230 { 0x00, 0x0000 },
231 { 0x01, 0xc8c8 },
232 { 0x02, 0xc8c8 },
233 { 0x03, 0xc8c8 },
234 { 0x0a, 0x0002 },
235 { 0x0b, 0x2827 },
236 { 0x0c, 0xe000 },
237 { 0x0d, 0x0000 },
238 { 0x0e, 0x0000 },
239 { 0x0f, 0x0808 },
240 { 0x14, 0x3333 },
241 { 0x16, 0x4b00 },
242 { 0x18, 0x018b },
243 { 0x19, 0xafaf },
244 { 0x1a, 0xafaf },
245 { 0x1b, 0x0001 },
246 { 0x1c, 0x2f2f },
247 { 0x1d, 0x2f2f },
248 { 0x1e, 0x0000 },
249 { 0x20, 0x0000 },
250 { 0x27, 0x7060 },
251 { 0x28, 0x7070 },
252 { 0x29, 0x8080 },
253 { 0x2a, 0x5656 },
254 { 0x2b, 0x5454 },
255 { 0x2c, 0xaaa0 },
256 { 0x2d, 0x0000 },
257 { 0x2f, 0x1002 },
258 { 0x31, 0x5000 },
259 { 0x32, 0x0000 },
260 { 0x33, 0x0000 },
261 { 0x34, 0x0000 },
262 { 0x35, 0x0000 },
263 { 0x3b, 0x0000 },
264 { 0x3c, 0x007f },
265 { 0x3d, 0x0000 },
266 { 0x3e, 0x007f },
267 { 0x3f, 0x0000 },
268 { 0x40, 0x001f },
269 { 0x41, 0x0000 },
270 { 0x42, 0x001f },
271 { 0x45, 0x6000 },
272 { 0x46, 0x003e },
273 { 0x47, 0x003e },
274 { 0x48, 0xf807 },
275 { 0x4a, 0x0004 },
276 { 0x4d, 0x0000 },
277 { 0x4e, 0x0000 },
278 { 0x4f, 0x01ff },
279 { 0x50, 0x0000 },
280 { 0x51, 0x0000 },
281 { 0x52, 0x01ff },
282 { 0x53, 0xf000 },
283 { 0x56, 0x0111 },
284 { 0x57, 0x0064 },
285 { 0x58, 0xef0e },
286 { 0x59, 0xf0f0 },
287 { 0x5a, 0xef0e },
288 { 0x5b, 0xf0f0 },
289 { 0x5c, 0xef0e },
290 { 0x5d, 0xf0f0 },
291 { 0x5e, 0xf000 },
292 { 0x5f, 0x0000 },
293 { 0x61, 0x0300 },
294 { 0x62, 0x0000 },
295 { 0x63, 0x00c2 },
296 { 0x64, 0x0000 },
297 { 0x65, 0x0000 },
298 { 0x66, 0x0000 },
299 { 0x6a, 0x0000 },
300 { 0x6c, 0x0aaa },
301 { 0x70, 0x8000 },
302 { 0x71, 0x8000 },
303 { 0x72, 0x8000 },
304 { 0x73, 0x7770 },
305 { 0x74, 0x3e00 },
306 { 0x75, 0x2409 },
307 { 0x76, 0x000a },
308 { 0x77, 0x0c00 },
309 { 0x78, 0x0000 },
310 { 0x79, 0x0123 },
311 { 0x7a, 0x0123 },
312 { 0x80, 0x0000 },
313 { 0x81, 0x0000 },
314 { 0x82, 0x0000 },
315 { 0x83, 0x0000 },
316 { 0x84, 0x0000 },
317 { 0x85, 0x0000 },
318 { 0x8a, 0x0000 },
319 { 0x8e, 0x0004 },
320 { 0x8f, 0x1100 },
321 { 0x90, 0x0646 },
322 { 0x91, 0x0c06 },
323 { 0x93, 0x0000 },
324 { 0x94, 0x0200 },
325 { 0x95, 0x0000 },
326 { 0x9a, 0x2184 },
327 { 0x9b, 0x010a },
328 { 0x9c, 0x0aea },
329 { 0x9d, 0x000c },
330 { 0x9e, 0x0400 },
331 { 0xa0, 0xa0a8 },
332 { 0xa1, 0x0059 },
333 { 0xa2, 0x0001 },
334 { 0xae, 0x6000 },
335 { 0xaf, 0x0000 },
336 { 0xb0, 0x6000 },
337 { 0xb1, 0x0000 },
338 { 0xb2, 0x0000 },
339 { 0xb3, 0x001f },
340 { 0xb4, 0x020c },
341 { 0xb5, 0x1f00 },
342 { 0xb6, 0x0000 },
343 { 0xbb, 0x0000 },
344 { 0xbc, 0x0000 },
345 { 0xbd, 0x0000 },
346 { 0xbe, 0x0000 },
347 { 0xbf, 0x3100 },
348 { 0xc0, 0x0000 },
349 { 0xc1, 0x0000 },
350 { 0xc2, 0x0000 },
351 { 0xc3, 0x2000 },
352 { 0xcd, 0x0000 },
353 { 0xce, 0x0000 },
354 { 0xcf, 0x1813 },
355 { 0xd0, 0x0690 },
356 { 0xd1, 0x1c17 },
357 { 0xd3, 0xb320 },
358 { 0xd4, 0x0000 },
359 { 0xd6, 0x0400 },
360 { 0xd9, 0x0809 },
361 { 0xda, 0x0000 },
362 { 0xdb, 0x0003 },
363 { 0xdc, 0x0049 },
364 { 0xdd, 0x001b },
365 { 0xdf, 0x0008 },
366 { 0xe0, 0x4000 },
367 { 0xe6, 0x8000 },
368 { 0xe7, 0x0200 },
369 { 0xec, 0xb300 },
370 { 0xed, 0x0000 },
371 { 0xf0, 0x001f },
372 { 0xf1, 0x020c },
373 { 0xf2, 0x1f00 },
374 { 0xf3, 0x0000 },
375 { 0xf4, 0x4000 },
376 { 0xf8, 0x0000 },
377 { 0xf9, 0x0000 },
378 { 0xfa, 0x2060 },
379 { 0xfb, 0x4040 },
380 { 0xfc, 0x0000 },
381 { 0xfd, 0x0002 },
382 { 0xfe, 0x10ec },
383 { 0xff, 0x6308 },
384};
385
be77b38a
OC		 386struct rt5645_eq_param_s {
387 unsigned short reg;
388 unsigned short val;
389};
390
9fc114c5
KC		 391static const char *const rt5645_supply_names[] = {
392 "avdd",
393 "cpvdd",
394};
395
396struct rt5645_priv {
397 struct snd_soc_codec *codec;
398 struct rt5645_platform_data pdata;
399 struct regmap *regmap;
400 struct i2c_client *i2c;
401 struct gpio_desc *gpiod_hp_det;
402 struct snd_soc_jack *hp_jack;
403 struct snd_soc_jack *mic_jack;
404 struct snd_soc_jack *btn_jack;
7099ee85 405 struct delayed_work jack_detect_work, rcclock_work;
9fc114c5 406 struct regulator_bulk_data supplies[ARRAY_SIZE(rt5645_supply_names)];
be77b38a 407 struct rt5645_eq_param_s *eq_param;
7ff6319e 408 struct timer_list btn_check_timer;
9fc114c5
KC		 409
410 int codec_type;
411 int sysclk;
412 int sysclk_src;
413 int lrck[RT5645_AIFS];
414 int bclk[RT5645_AIFS];
415 int master[RT5645_AIFS];
416
417 int pll_src;
418 int pll_in;
419 int pll_out;
420
421 int jack_type;
422 bool en_button_func;
588cd850 423 bool hp_on;
9fc114c5
KC		 424};
425
1319b2f6
OC		 426static int rt5645_reset(struct snd_soc_codec *codec)
427{
428 return snd_soc_write(codec, RT5645_RESET, 0);
429}
430
431static bool rt5645_volatile_register(struct device *dev, unsigned int reg)
432{
433 int i;
434
435 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
436 if (reg >= rt5645_ranges[i].range_min &&
437 reg <= rt5645_ranges[i].range_max) {
438 return true;
439 }
440 }
441
442 switch (reg) {
443 case RT5645_RESET:
444 case RT5645_PRIV_DATA:
445 case RT5645_IN1_CTRL1:
446 case RT5645_IN1_CTRL2:
447 case RT5645_IN1_CTRL3:
448 case RT5645_A_JD_CTRL1:
449 case RT5645_ADC_EQ_CTRL1:
450 case RT5645_EQ_CTRL1:
451 case RT5645_ALC_CTRL_1:
452 case RT5645_IRQ_CTRL2:
453 case RT5645_IRQ_CTRL3:
454 case RT5645_INT_IRQ_ST:
455 case RT5645_IL_CMD:
5c4ca99d 456 case RT5650_4BTN_IL_CMD1:
1319b2f6
OC		 457 case RT5645_VENDOR_ID:
458 case RT5645_VENDOR_ID1:
459 case RT5645_VENDOR_ID2:
71bfa9b4 460 return true;
1319b2f6 461 default:
71bfa9b4 462 return false;
1319b2f6
OC		 463 }
464}
465
466static bool rt5645_readable_register(struct device *dev, unsigned int reg)
467{
468 int i;
469
470 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
471 if (reg >= rt5645_ranges[i].range_min &&
472 reg <= rt5645_ranges[i].range_max) {
473 return true;
474 }
475 }
476
477 switch (reg) {
478 case RT5645_RESET:
479 case RT5645_SPK_VOL:
480 case RT5645_HP_VOL:
481 case RT5645_LOUT1:
482 case RT5645_IN1_CTRL1:
483 case RT5645_IN1_CTRL2:
484 case RT5645_IN1_CTRL3:
485 case RT5645_IN2_CTRL:
486 case RT5645_INL1_INR1_VOL:
487 case RT5645_SPK_FUNC_LIM:
488 case RT5645_ADJ_HPF_CTRL:
489 case RT5645_DAC1_DIG_VOL:
490 case RT5645_DAC2_DIG_VOL:
491 case RT5645_DAC_CTRL:
492 case RT5645_STO1_ADC_DIG_VOL:
493 case RT5645_MONO_ADC_DIG_VOL:
494 case RT5645_ADC_BST_VOL1:
495 case RT5645_ADC_BST_VOL2:
496 case RT5645_STO1_ADC_MIXER:
497 case RT5645_MONO_ADC_MIXER:
498 case RT5645_AD_DA_MIXER:
499 case RT5645_STO_DAC_MIXER:
500 case RT5645_MONO_DAC_MIXER:
501 case RT5645_DIG_MIXER:
5c4ca99d 502 case RT5650_A_DAC_SOUR:
1319b2f6
OC		 503 case RT5645_DIG_INF1_DATA:
504 case RT5645_PDM_OUT_CTRL:
505 case RT5645_REC_L1_MIXER:
506 case RT5645_REC_L2_MIXER:
507 case RT5645_REC_R1_MIXER:
508 case RT5645_REC_R2_MIXER:
509 case RT5645_HPMIXL_CTRL:
510 case RT5645_HPOMIXL_CTRL:
511 case RT5645_HPMIXR_CTRL:
512 case RT5645_HPOMIXR_CTRL:
513 case RT5645_HPO_MIXER:
514 case RT5645_SPK_L_MIXER:
515 case RT5645_SPK_R_MIXER:
516 case RT5645_SPO_MIXER:
517 case RT5645_SPO_CLSD_RATIO:
518 case RT5645_OUT_L1_MIXER:
519 case RT5645_OUT_R1_MIXER:
520 case RT5645_OUT_L_GAIN1:
521 case RT5645_OUT_L_GAIN2:
522 case RT5645_OUT_R_GAIN1:
523 case RT5645_OUT_R_GAIN2:
524 case RT5645_LOUT_MIXER:
525 case RT5645_HAPTIC_CTRL1:
526 case RT5645_HAPTIC_CTRL2:
527 case RT5645_HAPTIC_CTRL3:
528 case RT5645_HAPTIC_CTRL4:
529 case RT5645_HAPTIC_CTRL5:
530 case RT5645_HAPTIC_CTRL6:
531 case RT5645_HAPTIC_CTRL7:
532 case RT5645_HAPTIC_CTRL8:
533 case RT5645_HAPTIC_CTRL9:
534 case RT5645_HAPTIC_CTRL10:
535 case RT5645_PWR_DIG1:
536 case RT5645_PWR_DIG2:
537 case RT5645_PWR_ANLG1:
538 case RT5645_PWR_ANLG2:
539 case RT5645_PWR_MIXER:
540 case RT5645_PWR_VOL:
541 case RT5645_PRIV_INDEX:
542 case RT5645_PRIV_DATA:
543 case RT5645_I2S1_SDP:
544 case RT5645_I2S2_SDP:
545 case RT5645_ADDA_CLK1:
546 case RT5645_ADDA_CLK2:
547 case RT5645_DMIC_CTRL1:
548 case RT5645_DMIC_CTRL2:
549 case RT5645_TDM_CTRL_1:
550 case RT5645_TDM_CTRL_2:
df078d29 551 case RT5645_TDM_CTRL_3:
1fcb76db 552 case RT5650_TDM_CTRL_4:
1319b2f6
OC		 553 case RT5645_GLB_CLK:
554 case RT5645_PLL_CTRL1:
555 case RT5645_PLL_CTRL2:
556 case RT5645_ASRC_1:
557 case RT5645_ASRC_2:
558 case RT5645_ASRC_3:
559 case RT5645_ASRC_4:
560 case RT5645_DEPOP_M1:
561 case RT5645_DEPOP_M2:
562 case RT5645_DEPOP_M3:
b1d42598 563 case RT5645_CHARGE_PUMP:
1319b2f6
OC		 564 case RT5645_MICBIAS:
565 case RT5645_A_JD_CTRL1:
566 case RT5645_VAD_CTRL4:
567 case RT5645_CLSD_OUT_CTRL:
568 case RT5645_ADC_EQ_CTRL1:
569 case RT5645_ADC_EQ_CTRL2:
570 case RT5645_EQ_CTRL1:
571 case RT5645_EQ_CTRL2:
572 case RT5645_ALC_CTRL_1:
573 case RT5645_ALC_CTRL_2:
574 case RT5645_ALC_CTRL_3:
575 case RT5645_ALC_CTRL_4:
576 case RT5645_ALC_CTRL_5:
577 case RT5645_JD_CTRL:
578 case RT5645_IRQ_CTRL1:
579 case RT5645_IRQ_CTRL2:
580 case RT5645_IRQ_CTRL3:
581 case RT5645_INT_IRQ_ST:
582 case RT5645_GPIO_CTRL1:
583 case RT5645_GPIO_CTRL2:
584 case RT5645_GPIO_CTRL3:
585 case RT5645_BASS_BACK:
586 case RT5645_MP3_PLUS1:
587 case RT5645_MP3_PLUS2:
588 case RT5645_ADJ_HPF1:
589 case RT5645_ADJ_HPF2:
590 case RT5645_HP_CALIB_AMP_DET:
591 case RT5645_SV_ZCD1:
592 case RT5645_SV_ZCD2:
593 case RT5645_IL_CMD:
594 case RT5645_IL_CMD2:
595 case RT5645_IL_CMD3:
5c4ca99d
BL		 596 case RT5650_4BTN_IL_CMD1:
597 case RT5650_4BTN_IL_CMD2:
1319b2f6
OC		 598 case RT5645_DRC1_HL_CTRL1:
599 case RT5645_DRC2_HL_CTRL1:
600 case RT5645_ADC_MONO_HP_CTRL1:
601 case RT5645_ADC_MONO_HP_CTRL2:
602 case RT5645_DRC2_CTRL1:
603 case RT5645_DRC2_CTRL2:
604 case RT5645_DRC2_CTRL3:
605 case RT5645_DRC2_CTRL4:
606 case RT5645_DRC2_CTRL5:
607 case RT5645_JD_CTRL3:
608 case RT5645_JD_CTRL4:
609 case RT5645_GEN_CTRL1:
610 case RT5645_GEN_CTRL2:
611 case RT5645_GEN_CTRL3:
612 case RT5645_VENDOR_ID:
613 case RT5645_VENDOR_ID1:
614 case RT5645_VENDOR_ID2:
71bfa9b4 615 return true;
1319b2f6 616 default:
71bfa9b4 617 return false;
1319b2f6
OC		 618 }
619}
620
621static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
177e1e1f 622static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
1319b2f6 623static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
177e1e1f 624static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
1319b2f6
OC		 625static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
626
627/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
6d698a83 628static const DECLARE_TLV_DB_RANGE(bst_tlv,
1319b2f6
OC		 629 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
630 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
631 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
632 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
633 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
634 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
6d698a83
LPC		 635 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
636);
1319b2f6 637
e29fd55d
OC		 638/* {-6, -4.5, -3, -1.5, 0, 0.82, 1.58, 2.28} dB */
639static const DECLARE_TLV_DB_RANGE(spk_clsd_tlv,
640 0, 4, TLV_DB_SCALE_ITEM(-600, 150, 0),
641 5, 5, TLV_DB_SCALE_ITEM(82, 0, 0),
642 6, 6, TLV_DB_SCALE_ITEM(158, 0, 0),
643 7, 7, TLV_DB_SCALE_ITEM(228, 0, 0)
644);
645
be77b38a
OC		 646static int rt5645_hweq_info(struct snd_kcontrol *kcontrol,
647 struct snd_ctl_elem_info *uinfo)
648{
649 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
650 uinfo->count = RT5645_HWEQ_NUM * sizeof(struct rt5645_eq_param_s);
651
652 return 0;
653}
654
655static int rt5645_hweq_get(struct snd_kcontrol *kcontrol,
656 struct snd_ctl_elem_value *ucontrol)
657{
658 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
659 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
660 struct rt5645_eq_param_s *eq_param =
661 (struct rt5645_eq_param_s *)ucontrol->value.bytes.data;
662 int i;
663
664 for (i = 0; i < RT5645_HWEQ_NUM; i++) {
665 eq_param[i].reg = cpu_to_be16(rt5645->eq_param[i].reg);
666 eq_param[i].val = cpu_to_be16(rt5645->eq_param[i].val);
667 }
668
669 return 0;
670}
671
672static bool rt5645_validate_hweq(unsigned short reg)
673{
674 if ((reg >= 0x1a4 && reg <= 0x1cd) | (reg >= 0x1e5 && reg <= 0x1f8) |
675 (reg == RT5645_EQ_CTRL2))
676 return true;
677
678 return false;
679}
680
681static int rt5645_hweq_put(struct snd_kcontrol *kcontrol,
682 struct snd_ctl_elem_value *ucontrol)
683{
684 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
685 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
686 struct rt5645_eq_param_s *eq_param =
687 (struct rt5645_eq_param_s *)ucontrol->value.bytes.data;
688 int i;
689
690 for (i = 0; i < RT5645_HWEQ_NUM; i++) {
691 eq_param[i].reg = be16_to_cpu(eq_param[i].reg);
692 eq_param[i].val = be16_to_cpu(eq_param[i].val);
693 }
694
695 /* The final setting of the table should be RT5645_EQ_CTRL2 */
696 for (i = RT5645_HWEQ_NUM - 1; i >= 0; i--) {
697 if (eq_param[i].reg == 0)
698 continue;
699 else if (eq_param[i].reg != RT5645_EQ_CTRL2)
700 return 0;
701 else
702 break;
703 }
704
705 for (i = 0; i < RT5645_HWEQ_NUM; i++) {
706 if (!rt5645_validate_hweq(eq_param[i].reg) &&
707 eq_param[i].reg != 0)
708 return 0;
709 else if (eq_param[i].reg == 0)
710 break;
711 }
712
713 memcpy(rt5645->eq_param, eq_param,
714 RT5645_HWEQ_NUM * sizeof(struct rt5645_eq_param_s));
715
716 return 0;
717}
718
719#define RT5645_HWEQ(xname) \
720{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
721 .info = rt5645_hweq_info, \
722 .get = rt5645_hweq_get, \
723 .put = rt5645_hweq_put \
724}
725
7099ee85
OC		 726static int rt5645_spk_put_volsw(struct snd_kcontrol *kcontrol,
727 struct snd_ctl_elem_value *ucontrol)
728{
729 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
730 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
731 int ret;
732
7099ee85
OC		 733 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
734 RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PU);
735
736 ret = snd_soc_put_volsw(kcontrol, ucontrol);
737
6e5b143c 738 mod_delayed_work(system_power_efficient_wq, &rt5645->rcclock_work,
7099ee85
OC		 739 msecs_to_jiffies(200));
740
741 return ret;
742}
743
1319b2f6
OC		 744static const struct snd_kcontrol_new rt5645_snd_controls[] = {
745 /* Speaker Output Volume */
746 SOC_DOUBLE("Speaker Channel Switch", RT5645_SPK_VOL,
747 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
7099ee85
OC		 748 SOC_DOUBLE_EXT_TLV("Speaker Playback Volume", RT5645_SPK_VOL,
749 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, snd_soc_get_volsw,
750 rt5645_spk_put_volsw, out_vol_tlv),
1319b2f6 751
e29fd55d
OC		 752 /* ClassD modulator Speaker Gain Ratio */
753 SOC_SINGLE_TLV("Speaker ClassD Playback Volume", RT5645_SPO_CLSD_RATIO,
754 RT5645_SPK_G_CLSD_SFT, 7, 0, spk_clsd_tlv),
755
1319b2f6 756 /* Headphone Output Volume */
692768c4 757 SOC_DOUBLE("Headphone Channel Switch", RT5645_HP_VOL,
1319b2f6 758 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
692768c4 759 SOC_DOUBLE_TLV("Headphone Playback Volume", RT5645_HP_VOL,
1319b2f6
OC		 760 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
761
762 /* OUTPUT Control */
763 SOC_DOUBLE("OUT Playback Switch", RT5645_LOUT1,
764 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
765 SOC_DOUBLE("OUT Channel Switch", RT5645_LOUT1,
766 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
767 SOC_DOUBLE_TLV("OUT Playback Volume", RT5645_LOUT1,
768 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
769
770 /* DAC Digital Volume */
771 SOC_DOUBLE("DAC2 Playback Switch", RT5645_DAC_CTRL,
772 RT5645_M_DAC_L2_VOL_SFT, RT5645_M_DAC_R2_VOL_SFT, 1, 1),
773 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5645_DAC1_DIG_VOL,
177e1e1f 774 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
1319b2f6 775 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5645_DAC2_DIG_VOL,
177e1e1f 776 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
1319b2f6
OC		 777
778 /* IN1/IN2 Control */
779 SOC_SINGLE_TLV("IN1 Boost", RT5645_IN1_CTRL1,
780 RT5645_BST_SFT1, 8, 0, bst_tlv),
781 SOC_SINGLE_TLV("IN2 Boost", RT5645_IN2_CTRL,
782 RT5645_BST_SFT2, 8, 0, bst_tlv),
783
784 /* INL/INR Volume Control */
785 SOC_DOUBLE_TLV("IN Capture Volume", RT5645_INL1_INR1_VOL,
786 RT5645_INL_VOL_SFT, RT5645_INR_VOL_SFT, 31, 1, in_vol_tlv),
787
788 /* ADC Digital Volume Control */
789 SOC_DOUBLE("ADC Capture Switch", RT5645_STO1_ADC_DIG_VOL,
790 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
791 SOC_DOUBLE_TLV("ADC Capture Volume", RT5645_STO1_ADC_DIG_VOL,
177e1e1f 792 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
1319b2f6
OC		 793 SOC_DOUBLE("Mono ADC Capture Switch", RT5645_MONO_ADC_DIG_VOL,
794 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
795 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5645_MONO_ADC_DIG_VOL,
177e1e1f 796 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
1319b2f6
OC		 797
798 /* ADC Boost Volume Control */
8c1a9d63 799 SOC_DOUBLE_TLV("ADC Boost Capture Volume", RT5645_ADC_BST_VOL1,
1319b2f6
OC		 800 RT5645_STO1_ADC_L_BST_SFT, RT5645_STO1_ADC_R_BST_SFT, 3, 0,
801 adc_bst_tlv),
8c1a9d63
OC		 802 SOC_DOUBLE_TLV("Mono ADC Boost Capture Volume", RT5645_ADC_BST_VOL2,
803 RT5645_MONO_ADC_L_BST_SFT, RT5645_MONO_ADC_R_BST_SFT, 3, 0,
1319b2f6
OC		 804 adc_bst_tlv),
805
806 /* I2S2 function select */
807 SOC_SINGLE("I2S2 Func Switch", RT5645_GPIO_CTRL1, RT5645_I2S2_SEL_SFT,
808 1, 1),
be77b38a 809 RT5645_HWEQ("Speaker HWEQ"),
1319b2f6
OC		 810};
811
812/**
813 * set_dmic_clk - Set parameter of dmic.
814 *
815 * @w: DAPM widget.
816 * @kcontrol: The kcontrol of this widget.
817 * @event: Event id.
818 *
1319b2f6
OC		 819 */
820static int set_dmic_clk(struct snd_soc_dapm_widget *w,
821 struct snd_kcontrol *kcontrol, int event)
822{
c5f596cb 823 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1319b2f6 824 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
00a6d6e5 825 int idx, rate;
1319b2f6 826
00a6d6e5
OC		 827 rate = rt5645->sysclk / rl6231_get_pre_div(rt5645->regmap,
828 RT5645_ADDA_CLK1, RT5645_I2S_PD1_SFT);
829 idx = rl6231_calc_dmic_clk(rate);
1319b2f6
OC		 830 if (idx < 0)
831 dev_err(codec->dev, "Failed to set DMIC clock\n");
832 else
833 snd_soc_update_bits(codec, RT5645_DMIC_CTRL1,
834 RT5645_DMIC_CLK_MASK, idx << RT5645_DMIC_CLK_SFT);
835 return idx;
836}
837
838static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
839 struct snd_soc_dapm_widget *sink)
840{
c5f596cb 841 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
1319b2f6
OC		 842 unsigned int val;
843
c5f596cb 844 val = snd_soc_read(codec, RT5645_GLB_CLK);
1319b2f6
OC		 845 val &= RT5645_SCLK_SRC_MASK;
846 if (val == RT5645_SCLK_SRC_PLL1)
847 return 1;
848 else
849 return 0;
850}
851
9e268353
BL		 852static int is_using_asrc(struct snd_soc_dapm_widget *source,
853 struct snd_soc_dapm_widget *sink)
854{
c5f596cb 855 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
9e268353
BL		 856 unsigned int reg, shift, val;
857
858 switch (source->shift) {
859 case 0:
860 reg = RT5645_ASRC_3;
861 shift = 0;
862 break;
863 case 1:
864 reg = RT5645_ASRC_3;
865 shift = 4;
866 break;
867 case 3:
868 reg = RT5645_ASRC_2;
869 shift = 0;
870 break;
871 case 8:
872 reg = RT5645_ASRC_2;
873 shift = 4;
874 break;
875 case 9:
876 reg = RT5645_ASRC_2;
877 shift = 8;
878 break;
879 case 10:
880 reg = RT5645_ASRC_2;
881 shift = 12;
882 break;
883 default:
884 return 0;
885 }
886
c5f596cb 887 val = (snd_soc_read(codec, reg) >> shift) & 0xf;
9e268353
BL		 888 switch (val) {
889 case 1:
890 case 2:
891 case 3:
892 case 4:
893 return 1;
894 default:
895 return 0;
896 }
897
898}
899
be77b38a
OC		 900static int rt5645_enable_hweq(struct snd_soc_codec *codec)
901{
902 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
903 int i;
904
905 for (i = 0; i < RT5645_HWEQ_NUM; i++) {
906 if (rt5645_validate_hweq(rt5645->eq_param[i].reg))
907 regmap_write(rt5645->regmap, rt5645->eq_param[i].reg,
908 rt5645->eq_param[i].val);
909 else
910 break;
911 }
912
913 return 0;
914}
915
79080a8b
FY		 916/**
917 * rt5645_sel_asrc_clk_src - select ASRC clock source for a set of filters
918 * @codec: SoC audio codec device.
919 * @filter_mask: mask of filters.
920 * @clk_src: clock source
921 *
922 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5645 can
923 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
924 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
925 * ASRC function will track i2s clock and generate a corresponding system clock
926 * for codec. This function provides an API to select the clock source for a
927 * set of filters specified by the mask. And the codec driver will turn on ASRC
928 * for these filters if ASRC is selected as their clock source.
929 */
930int rt5645_sel_asrc_clk_src(struct snd_soc_codec *codec,
931 unsigned int filter_mask, unsigned int clk_src)
932{
933 unsigned int asrc2_mask = 0;
934 unsigned int asrc2_value = 0;
935 unsigned int asrc3_mask = 0;
936 unsigned int asrc3_value = 0;
937
938 switch (clk_src) {
939 case RT5645_CLK_SEL_SYS:
940 case RT5645_CLK_SEL_I2S1_ASRC:
941 case RT5645_CLK_SEL_I2S2_ASRC:
942 case RT5645_CLK_SEL_SYS2:
943 break;
944
945 default:
946 return -EINVAL;
947 }
948
949 if (filter_mask & RT5645_DA_STEREO_FILTER) {
950 asrc2_mask |= RT5645_DA_STO_CLK_SEL_MASK;
951 asrc2_value = (asrc2_value & ~RT5645_DA_STO_CLK_SEL_MASK)
952 | (clk_src << RT5645_DA_STO_CLK_SEL_SFT);
953 }
954
955 if (filter_mask & RT5645_DA_MONO_L_FILTER) {
956 asrc2_mask |= RT5645_DA_MONOL_CLK_SEL_MASK;
957 asrc2_value = (asrc2_value & ~RT5645_DA_MONOL_CLK_SEL_MASK)
958 | (clk_src << RT5645_DA_MONOL_CLK_SEL_SFT);
959 }
960
961 if (filter_mask & RT5645_DA_MONO_R_FILTER) {
962 asrc2_mask |= RT5645_DA_MONOR_CLK_SEL_MASK;
963 asrc2_value = (asrc2_value & ~RT5645_DA_MONOR_CLK_SEL_MASK)
964 | (clk_src << RT5645_DA_MONOR_CLK_SEL_SFT);
965 }
966
967 if (filter_mask & RT5645_AD_STEREO_FILTER) {
968 asrc2_mask |= RT5645_AD_STO1_CLK_SEL_MASK;
969 asrc2_value = (asrc2_value & ~RT5645_AD_STO1_CLK_SEL_MASK)
970 | (clk_src << RT5645_AD_STO1_CLK_SEL_SFT);
971 }
972
973 if (filter_mask & RT5645_AD_MONO_L_FILTER) {
974 asrc3_mask |= RT5645_AD_MONOL_CLK_SEL_MASK;
975 asrc3_value = (asrc3_value & ~RT5645_AD_MONOL_CLK_SEL_MASK)
976 | (clk_src << RT5645_AD_MONOL_CLK_SEL_SFT);
977 }
978
979 if (filter_mask & RT5645_AD_MONO_R_FILTER) {
980 asrc3_mask |= RT5645_AD_MONOR_CLK_SEL_MASK;
981 asrc3_value = (asrc3_value & ~RT5645_AD_MONOR_CLK_SEL_MASK)
982 | (clk_src << RT5645_AD_MONOR_CLK_SEL_SFT);
983 }
984
985 if (asrc2_mask)
986 snd_soc_update_bits(codec, RT5645_ASRC_2,
987 asrc2_mask, asrc2_value);
988
989 if (asrc3_mask)
990 snd_soc_update_bits(codec, RT5645_ASRC_3,
991 asrc3_mask, asrc3_value);
992
993 return 0;
994}
995EXPORT_SYMBOL_GPL(rt5645_sel_asrc_clk_src);
996
1319b2f6
OC		 997/* Digital Mixer */
998static const struct snd_kcontrol_new rt5645_sto1_adc_l_mix[] = {
999 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
1000 RT5645_M_ADC_L1_SFT, 1, 1),
1001 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
1002 RT5645_M_ADC_L2_SFT, 1, 1),
1003};
1004
1005static const struct snd_kcontrol_new rt5645_sto1_adc_r_mix[] = {
1006 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
1007 RT5645_M_ADC_R1_SFT, 1, 1),
1008 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
1009 RT5645_M_ADC_R2_SFT, 1, 1),
1010};
1011
1012static const struct snd_kcontrol_new rt5645_mono_adc_l_mix[] = {
1013 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
1014 RT5645_M_MONO_ADC_L1_SFT, 1, 1),
1015 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
1016 RT5645_M_MONO_ADC_L2_SFT, 1, 1),
1017};
1018
1019static const struct snd_kcontrol_new rt5645_mono_adc_r_mix[] = {
1020 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
1021 RT5645_M_MONO_ADC_R1_SFT, 1, 1),
1022 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
1023 RT5645_M_MONO_ADC_R2_SFT, 1, 1),
1024};
1025
1026static const struct snd_kcontrol_new rt5645_dac_l_mix[] = {
1027 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
1028 RT5645_M_ADCMIX_L_SFT, 1, 1),
21cb13e7 1029 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER,
1319b2f6
OC		 1030 RT5645_M_DAC1_L_SFT, 1, 1),
1031};
1032
1033static const struct snd_kcontrol_new rt5645_dac_r_mix[] = {
1034 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
1035 RT5645_M_ADCMIX_R_SFT, 1, 1),
21cb13e7 1036 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER,
1319b2f6
OC		 1037 RT5645_M_DAC1_R_SFT, 1, 1),
1038};
1039
1040static const struct snd_kcontrol_new rt5645_sto_dac_l_mix[] = {
1041 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
1042 RT5645_M_DAC_L1_SFT, 1, 1),
1043 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_STO_DAC_MIXER,
1044 RT5645_M_DAC_L2_SFT, 1, 1),
1045 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
1046 RT5645_M_DAC_R1_STO_L_SFT, 1, 1),
1047};
1048
1049static const struct snd_kcontrol_new rt5645_sto_dac_r_mix[] = {
1050 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
1051 RT5645_M_DAC_R1_SFT, 1, 1),
1052 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_STO_DAC_MIXER,
1053 RT5645_M_DAC_R2_SFT, 1, 1),
1054 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
1055 RT5645_M_DAC_L1_STO_R_SFT, 1, 1),
1056};
1057
1058static const struct snd_kcontrol_new rt5645_mono_dac_l_mix[] = {
1059 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_MONO_DAC_MIXER,
1060 RT5645_M_DAC_L1_MONO_L_SFT, 1, 1),
1061 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
1062 RT5645_M_DAC_L2_MONO_L_SFT, 1, 1),
1063 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
1064 RT5645_M_DAC_R2_MONO_L_SFT, 1, 1),
1065};
1066
1067static const struct snd_kcontrol_new rt5645_mono_dac_r_mix[] = {
1068 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_MONO_DAC_MIXER,
1069 RT5645_M_DAC_R1_MONO_R_SFT, 1, 1),
1070 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
1071 RT5645_M_DAC_R2_MONO_R_SFT, 1, 1),
1072 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
1073 RT5645_M_DAC_L2_MONO_R_SFT, 1, 1),
1074};
1075
1076static const struct snd_kcontrol_new rt5645_dig_l_mix[] = {
1077 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5645_DIG_MIXER,
1078 RT5645_M_STO_L_DAC_L_SFT, 1, 1),
1079 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
1080 RT5645_M_DAC_L2_DAC_L_SFT, 1, 1),
1081 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
1082 RT5645_M_DAC_R2_DAC_L_SFT, 1, 1),
1083};
1084
1085static const struct snd_kcontrol_new rt5645_dig_r_mix[] = {
1086 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5645_DIG_MIXER,
1087 RT5645_M_STO_R_DAC_R_SFT, 1, 1),
1088 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
1089 RT5645_M_DAC_R2_DAC_R_SFT, 1, 1),
1090 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
1091 RT5645_M_DAC_L2_DAC_R_SFT, 1, 1),
1092};
1093
1094/* Analog Input Mixer */
1095static const struct snd_kcontrol_new rt5645_rec_l_mix[] = {
1096 SOC_DAPM_SINGLE("HPOL Switch", RT5645_REC_L2_MIXER,
1097 RT5645_M_HP_L_RM_L_SFT, 1, 1),
1098 SOC_DAPM_SINGLE("INL Switch", RT5645_REC_L2_MIXER,
1099 RT5645_M_IN_L_RM_L_SFT, 1, 1),
1100 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_L2_MIXER,
1101 RT5645_M_BST2_RM_L_SFT, 1, 1),
1102 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_L2_MIXER,
1103 RT5645_M_BST1_RM_L_SFT, 1, 1),
1104 SOC_DAPM_SINGLE("OUT MIXL Switch", RT5645_REC_L2_MIXER,
1105 RT5645_M_OM_L_RM_L_SFT, 1, 1),
1106};
1107
1108static const struct snd_kcontrol_new rt5645_rec_r_mix[] = {
1109 SOC_DAPM_SINGLE("HPOR Switch", RT5645_REC_R2_MIXER,
1110 RT5645_M_HP_R_RM_R_SFT, 1, 1),
1111 SOC_DAPM_SINGLE("INR Switch", RT5645_REC_R2_MIXER,
1112 RT5645_M_IN_R_RM_R_SFT, 1, 1),
1113 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_R2_MIXER,
1114 RT5645_M_BST2_RM_R_SFT, 1, 1),
1115 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_R2_MIXER,
1116 RT5645_M_BST1_RM_R_SFT, 1, 1),
1117 SOC_DAPM_SINGLE("OUT MIXR Switch", RT5645_REC_R2_MIXER,
1118 RT5645_M_OM_R_RM_R_SFT, 1, 1),
1119};
1120
1121static const struct snd_kcontrol_new rt5645_spk_l_mix[] = {
1122 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPK_L_MIXER,
1123 RT5645_M_DAC_L1_SM_L_SFT, 1, 1),
1124 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_SPK_L_MIXER,
1125 RT5645_M_DAC_L2_SM_L_SFT, 1, 1),
1126 SOC_DAPM_SINGLE("INL Switch", RT5645_SPK_L_MIXER,
1127 RT5645_M_IN_L_SM_L_SFT, 1, 1),
1128 SOC_DAPM_SINGLE("BST1 Switch", RT5645_SPK_L_MIXER,
1129 RT5645_M_BST1_L_SM_L_SFT, 1, 1),
1130};
1131
1132static const struct snd_kcontrol_new rt5645_spk_r_mix[] = {
1133 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPK_R_MIXER,
1134 RT5645_M_DAC_R1_SM_R_SFT, 1, 1),
1135 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_SPK_R_MIXER,
1136 RT5645_M_DAC_R2_SM_R_SFT, 1, 1),
1137 SOC_DAPM_SINGLE("INR Switch", RT5645_SPK_R_MIXER,
1138 RT5645_M_IN_R_SM_R_SFT, 1, 1),
1139 SOC_DAPM_SINGLE("BST2 Switch", RT5645_SPK_R_MIXER,
1140 RT5645_M_BST2_R_SM_R_SFT, 1, 1),
1141};
1142
1143static const struct snd_kcontrol_new rt5645_out_l_mix[] = {
1144 SOC_DAPM_SINGLE("BST1 Switch", RT5645_OUT_L1_MIXER,
1145 RT5645_M_BST1_OM_L_SFT, 1, 1),
1146 SOC_DAPM_SINGLE("INL Switch", RT5645_OUT_L1_MIXER,
1147 RT5645_M_IN_L_OM_L_SFT, 1, 1),
1148 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_OUT_L1_MIXER,
1149 RT5645_M_DAC_L2_OM_L_SFT, 1, 1),
1150 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_OUT_L1_MIXER,
1151 RT5645_M_DAC_L1_OM_L_SFT, 1, 1),
1152};
1153
1154static const struct snd_kcontrol_new rt5645_out_r_mix[] = {
1155 SOC_DAPM_SINGLE("BST2 Switch", RT5645_OUT_R1_MIXER,
1156 RT5645_M_BST2_OM_R_SFT, 1, 1),
1157 SOC_DAPM_SINGLE("INR Switch", RT5645_OUT_R1_MIXER,
1158 RT5645_M_IN_R_OM_R_SFT, 1, 1),
1159 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_OUT_R1_MIXER,
1160 RT5645_M_DAC_R2_OM_R_SFT, 1, 1),
1161 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_OUT_R1_MIXER,
1162 RT5645_M_DAC_R1_OM_R_SFT, 1, 1),
1163};
1164
1165static const struct snd_kcontrol_new rt5645_spo_l_mix[] = {
1166 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
1167 RT5645_M_DAC_R1_SPM_L_SFT, 1, 1),
1168 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPO_MIXER,
1169 RT5645_M_DAC_L1_SPM_L_SFT, 1, 1),
1170 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
1171 RT5645_M_SV_R_SPM_L_SFT, 1, 1),
1172 SOC_DAPM_SINGLE("SPKVOL L Switch", RT5645_SPO_MIXER,
1173 RT5645_M_SV_L_SPM_L_SFT, 1, 1),
1174};
1175
1176static const struct snd_kcontrol_new rt5645_spo_r_mix[] = {
1177 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
1178 RT5645_M_DAC_R1_SPM_R_SFT, 1, 1),
1179 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
1180 RT5645_M_SV_R_SPM_R_SFT, 1, 1),
1181};
1182
1183static const struct snd_kcontrol_new rt5645_hpo_mix[] = {
1184 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPO_MIXER,
1185 RT5645_M_DAC1_HM_SFT, 1, 1),
1186 SOC_DAPM_SINGLE("HPVOL Switch", RT5645_HPO_MIXER,
1187 RT5645_M_HPVOL_HM_SFT, 1, 1),
1188};
1189
1190static const struct snd_kcontrol_new rt5645_hpvoll_mix[] = {
1191 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXL_CTRL,
1192 RT5645_M_DAC1_HV_SFT, 1, 1),
1193 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXL_CTRL,
1194 RT5645_M_DAC2_HV_SFT, 1, 1),
1195 SOC_DAPM_SINGLE("INL Switch", RT5645_HPOMIXL_CTRL,
1196 RT5645_M_IN_HV_SFT, 1, 1),
1197 SOC_DAPM_SINGLE("BST1 Switch", RT5645_HPOMIXL_CTRL,
1198 RT5645_M_BST1_HV_SFT, 1, 1),
1199};
1200
1201static const struct snd_kcontrol_new rt5645_hpvolr_mix[] = {
1202 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXR_CTRL,
1203 RT5645_M_DAC1_HV_SFT, 1, 1),
1204 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXR_CTRL,
1205 RT5645_M_DAC2_HV_SFT, 1, 1),
1206 SOC_DAPM_SINGLE("INR Switch", RT5645_HPOMIXR_CTRL,
1207 RT5645_M_IN_HV_SFT, 1, 1),
1208 SOC_DAPM_SINGLE("BST2 Switch", RT5645_HPOMIXR_CTRL,
1209 RT5645_M_BST2_HV_SFT, 1, 1),
1210};
1211
1212static const struct snd_kcontrol_new rt5645_lout_mix[] = {
1213 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_LOUT_MIXER,
1214 RT5645_M_DAC_L1_LM_SFT, 1, 1),
1215 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_LOUT_MIXER,
1216 RT5645_M_DAC_R1_LM_SFT, 1, 1),
1217 SOC_DAPM_SINGLE("OUTMIX L Switch", RT5645_LOUT_MIXER,
1218 RT5645_M_OV_L_LM_SFT, 1, 1),
1219 SOC_DAPM_SINGLE("OUTMIX R Switch", RT5645_LOUT_MIXER,
1220 RT5645_M_OV_R_LM_SFT, 1, 1),
1221};
1222
1223/*DAC1 L/R source*/ /* MX-29 [9:8] [11:10] */
1224static const char * const rt5645_dac1_src[] = {
1225 "IF1 DAC", "IF2 DAC", "IF3 DAC"
1226};
1227
1228static SOC_ENUM_SINGLE_DECL(
1229 rt5645_dac1l_enum, RT5645_AD_DA_MIXER,
1230 RT5645_DAC1_L_SEL_SFT, rt5645_dac1_src);
1231
1232static const struct snd_kcontrol_new rt5645_dac1l_mux =
1233 SOC_DAPM_ENUM("DAC1 L source", rt5645_dac1l_enum);
1234
1235static SOC_ENUM_SINGLE_DECL(
1236 rt5645_dac1r_enum, RT5645_AD_DA_MIXER,
1237 RT5645_DAC1_R_SEL_SFT, rt5645_dac1_src);
1238
1239static const struct snd_kcontrol_new rt5645_dac1r_mux =
1240 SOC_DAPM_ENUM("DAC1 R source", rt5645_dac1r_enum);
1241
1242/*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */
1243static const char * const rt5645_dac12_src[] = {
1244 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "VAD_ADC"
1245};
1246
1247static SOC_ENUM_SINGLE_DECL(
1248 rt5645_dac2l_enum, RT5645_DAC_CTRL,
1249 RT5645_DAC2_L_SEL_SFT, rt5645_dac12_src);
1250
1251static const struct snd_kcontrol_new rt5645_dac_l2_mux =
1252 SOC_DAPM_ENUM("DAC2 L source", rt5645_dac2l_enum);
1253
1254static const char * const rt5645_dacr2_src[] = {
1255 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "Haptic"
1256};
1257
1258static SOC_ENUM_SINGLE_DECL(
1259 rt5645_dac2r_enum, RT5645_DAC_CTRL,
1260 RT5645_DAC2_R_SEL_SFT, rt5645_dacr2_src);
1261
1262static const struct snd_kcontrol_new rt5645_dac_r2_mux =
1263 SOC_DAPM_ENUM("DAC2 R source", rt5645_dac2r_enum);
1264
1265
1266/* INL/R source */
1267static const char * const rt5645_inl_src[] = {
1268 "IN2P", "MonoP"
1269};
1270
1271static SOC_ENUM_SINGLE_DECL(
1272 rt5645_inl_enum, RT5645_INL1_INR1_VOL,
1273 RT5645_INL_SEL_SFT, rt5645_inl_src);
1274
1275static const struct snd_kcontrol_new rt5645_inl_mux =
1276 SOC_DAPM_ENUM("INL source", rt5645_inl_enum);
1277
1278static const char * const rt5645_inr_src[] = {
1279 "IN2N", "MonoN"
1280};
1281
1282static SOC_ENUM_SINGLE_DECL(
1283 rt5645_inr_enum, RT5645_INL1_INR1_VOL,
1284 RT5645_INR_SEL_SFT, rt5645_inr_src);
1285
1286static const struct snd_kcontrol_new rt5645_inr_mux =
1287 SOC_DAPM_ENUM("INR source", rt5645_inr_enum);
1288
1289/* Stereo1 ADC source */
1290/* MX-27 [12] */
1291static const char * const rt5645_stereo_adc1_src[] = {
1292 "DAC MIX", "ADC"
1293};
1294
1295static SOC_ENUM_SINGLE_DECL(
1296 rt5645_stereo1_adc1_enum, RT5645_STO1_ADC_MIXER,
1297 RT5645_ADC_1_SRC_SFT, rt5645_stereo_adc1_src);
1298
1299static const struct snd_kcontrol_new rt5645_sto_adc1_mux =
1300 SOC_DAPM_ENUM("Stereo1 ADC1 Mux", rt5645_stereo1_adc1_enum);
1301
1302/* MX-27 [11] */
1303static const char * const rt5645_stereo_adc2_src[] = {
1304 "DAC MIX", "DMIC"
1305};
1306
1307static SOC_ENUM_SINGLE_DECL(
1308 rt5645_stereo1_adc2_enum, RT5645_STO1_ADC_MIXER,
1309 RT5645_ADC_2_SRC_SFT, rt5645_stereo_adc2_src);
1310
1311static const struct snd_kcontrol_new rt5645_sto_adc2_mux =
1312 SOC_DAPM_ENUM("Stereo1 ADC2 Mux", rt5645_stereo1_adc2_enum);
1313
1314/* MX-27 [8] */
1315static const char * const rt5645_stereo_dmic_src[] = {
1316 "DMIC1", "DMIC2"
1317};
1318
1319static SOC_ENUM_SINGLE_DECL(
1320 rt5645_stereo1_dmic_enum, RT5645_STO1_ADC_MIXER,
1321 RT5645_DMIC_SRC_SFT, rt5645_stereo_dmic_src);
1322
1323static const struct snd_kcontrol_new rt5645_sto1_dmic_mux =
1324 SOC_DAPM_ENUM("Stereo1 DMIC source", rt5645_stereo1_dmic_enum);
1325
1326/* Mono ADC source */
1327/* MX-28 [12] */
1328static const char * const rt5645_mono_adc_l1_src[] = {
1329 "Mono DAC MIXL", "ADC"
1330};
1331
1332static SOC_ENUM_SINGLE_DECL(
1333 rt5645_mono_adc_l1_enum, RT5645_MONO_ADC_MIXER,
1334 RT5645_MONO_ADC_L1_SRC_SFT, rt5645_mono_adc_l1_src);
1335
1336static const struct snd_kcontrol_new rt5645_mono_adc_l1_mux =
1337 SOC_DAPM_ENUM("Mono ADC1 left source", rt5645_mono_adc_l1_enum);
1338/* MX-28 [11] */
1339static const char * const rt5645_mono_adc_l2_src[] = {
1340 "Mono DAC MIXL", "DMIC"
1341};
1342
1343static SOC_ENUM_SINGLE_DECL(
1344 rt5645_mono_adc_l2_enum, RT5645_MONO_ADC_MIXER,
1345 RT5645_MONO_ADC_L2_SRC_SFT, rt5645_mono_adc_l2_src);
1346
1347static const struct snd_kcontrol_new rt5645_mono_adc_l2_mux =
1348 SOC_DAPM_ENUM("Mono ADC2 left source", rt5645_mono_adc_l2_enum);
1349
1350/* MX-28 [8] */
1351static const char * const rt5645_mono_dmic_src[] = {
1352 "DMIC1", "DMIC2"
1353};
1354
1355static SOC_ENUM_SINGLE_DECL(
1356 rt5645_mono_dmic_l_enum, RT5645_MONO_ADC_MIXER,
1357 RT5645_MONO_DMIC_L_SRC_SFT, rt5645_mono_dmic_src);
1358
1359static const struct snd_kcontrol_new rt5645_mono_dmic_l_mux =
1360 SOC_DAPM_ENUM("Mono DMIC left source", rt5645_mono_dmic_l_enum);
1361/* MX-28 [1:0] */
1362static SOC_ENUM_SINGLE_DECL(
1363 rt5645_mono_dmic_r_enum, RT5645_MONO_ADC_MIXER,
1364 RT5645_MONO_DMIC_R_SRC_SFT, rt5645_mono_dmic_src);
1365
1366static const struct snd_kcontrol_new rt5645_mono_dmic_r_mux =
1367 SOC_DAPM_ENUM("Mono DMIC Right source", rt5645_mono_dmic_r_enum);
1368/* MX-28 [4] */
1369static const char * const rt5645_mono_adc_r1_src[] = {
1370 "Mono DAC MIXR", "ADC"
1371};
1372
1373static SOC_ENUM_SINGLE_DECL(
1374 rt5645_mono_adc_r1_enum, RT5645_MONO_ADC_MIXER,
1375 RT5645_MONO_ADC_R1_SRC_SFT, rt5645_mono_adc_r1_src);
1376
1377static const struct snd_kcontrol_new rt5645_mono_adc_r1_mux =
1378 SOC_DAPM_ENUM("Mono ADC1 right source", rt5645_mono_adc_r1_enum);
1379/* MX-28 [3] */
1380static const char * const rt5645_mono_adc_r2_src[] = {
1381 "Mono DAC MIXR", "DMIC"
1382};
1383
1384static SOC_ENUM_SINGLE_DECL(
1385 rt5645_mono_adc_r2_enum, RT5645_MONO_ADC_MIXER,
1386 RT5645_MONO_ADC_R2_SRC_SFT, rt5645_mono_adc_r2_src);
1387
1388static const struct snd_kcontrol_new rt5645_mono_adc_r2_mux =
1389 SOC_DAPM_ENUM("Mono ADC2 right source", rt5645_mono_adc_r2_enum);
1390
1391/* MX-77 [9:8] */
1392static const char * const rt5645_if1_adc_in_src[] = {
21ab3f2b
BL		 1393 "IF_ADC1/IF_ADC2/VAD_ADC", "IF_ADC2/IF_ADC1/VAD_ADC",
1394 "VAD_ADC/IF_ADC1/IF_ADC2", "VAD_ADC/IF_ADC2/IF_ADC1"
1319b2f6
OC		 1395};
1396
1397static SOC_ENUM_SINGLE_DECL(
1398 rt5645_if1_adc_in_enum, RT5645_TDM_CTRL_1,
1399 RT5645_IF1_ADC_IN_SFT, rt5645_if1_adc_in_src);
1400
1401static const struct snd_kcontrol_new rt5645_if1_adc_in_mux =
1402 SOC_DAPM_ENUM("IF1 ADC IN source", rt5645_if1_adc_in_enum);
1403
21ab3f2b
BL		 1404/* MX-78 [4:0] */
1405static const char * const rt5650_if1_adc_in_src[] = {
1406 "IF_ADC1/IF_ADC2/DAC_REF/Null",
1407 "IF_ADC1/IF_ADC2/Null/DAC_REF",
1408 "IF_ADC1/DAC_REF/IF_ADC2/Null",
1409 "IF_ADC1/DAC_REF/Null/IF_ADC2",
1410 "IF_ADC1/Null/DAC_REF/IF_ADC2",
1411 "IF_ADC1/Null/IF_ADC2/DAC_REF",
1412
1413 "IF_ADC2/IF_ADC1/DAC_REF/Null",
1414 "IF_ADC2/IF_ADC1/Null/DAC_REF",
1415 "IF_ADC2/DAC_REF/IF_ADC1/Null",
1416 "IF_ADC2/DAC_REF/Null/IF_ADC1",
1417 "IF_ADC2/Null/DAC_REF/IF_ADC1",
1418 "IF_ADC2/Null/IF_ADC1/DAC_REF",
1419
1420 "DAC_REF/IF_ADC1/IF_ADC2/Null",
1421 "DAC_REF/IF_ADC1/Null/IF_ADC2",
1422 "DAC_REF/IF_ADC2/IF_ADC1/Null",
1423 "DAC_REF/IF_ADC2/Null/IF_ADC1",
1424 "DAC_REF/Null/IF_ADC1/IF_ADC2",
1425 "DAC_REF/Null/IF_ADC2/IF_ADC1",
1426
1427 "Null/IF_ADC1/IF_ADC2/DAC_REF",
1428 "Null/IF_ADC1/DAC_REF/IF_ADC2",
1429 "Null/IF_ADC2/IF_ADC1/DAC_REF",
1430 "Null/IF_ADC2/DAC_REF/IF_ADC1",
1431 "Null/DAC_REF/IF_ADC1/IF_ADC2",
1432 "Null/DAC_REF/IF_ADC2/IF_ADC1",
1433};
1434
1435static SOC_ENUM_SINGLE_DECL(
1436 rt5650_if1_adc_in_enum, RT5645_TDM_CTRL_2,
1437 0, rt5650_if1_adc_in_src);
1438
1439static const struct snd_kcontrol_new rt5650_if1_adc_in_mux =
1440 SOC_DAPM_ENUM("IF1 ADC IN source", rt5650_if1_adc_in_enum);
1441
1442/* MX-78 [15:14][13:12][11:10] */
1443static const char * const rt5645_tdm_adc_swap_select[] = {
1444 "L/R", "R/L", "L/L", "R/R"
1445};
1446
1447static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot0_1_enum,
1448 RT5645_TDM_CTRL_2, 14, rt5645_tdm_adc_swap_select);
1449
1450static const struct snd_kcontrol_new rt5650_if1_adc1_in_mux =
1451 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5650_tdm_adc_slot0_1_enum);
1452
1453static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot2_3_enum,
1454 RT5645_TDM_CTRL_2, 12, rt5645_tdm_adc_swap_select);
1455
1456static const struct snd_kcontrol_new rt5650_if1_adc2_in_mux =
1457 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5650_tdm_adc_slot2_3_enum);
1458
1459static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot4_5_enum,
1460 RT5645_TDM_CTRL_2, 10, rt5645_tdm_adc_swap_select);
1461
1462static const struct snd_kcontrol_new rt5650_if1_adc3_in_mux =
1463 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5650_tdm_adc_slot4_5_enum);
1464
1465/* MX-77 [7:6][5:4][3:2] */
1466static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot0_1_enum,
1467 RT5645_TDM_CTRL_1, 6, rt5645_tdm_adc_swap_select);
1468
1469static const struct snd_kcontrol_new rt5645_if1_adc1_in_mux =
1470 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5645_tdm_adc_slot0_1_enum);
1471
1472static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot2_3_enum,
1473 RT5645_TDM_CTRL_1, 4, rt5645_tdm_adc_swap_select);
1474
1475static const struct snd_kcontrol_new rt5645_if1_adc2_in_mux =
1476 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5645_tdm_adc_slot2_3_enum);
1477
1478static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot4_5_enum,
1479 RT5645_TDM_CTRL_1, 2, rt5645_tdm_adc_swap_select);
1480
1481static const struct snd_kcontrol_new rt5645_if1_adc3_in_mux =
1482 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5645_tdm_adc_slot4_5_enum);
1483
1484/* MX-79 [14:12][10:8][6:4][2:0] */
1485static const char * const rt5645_tdm_dac_swap_select[] = {
1486 "Slot0", "Slot1", "Slot2", "Slot3"
1487};
1488
1489static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac0_enum,
1490 RT5645_TDM_CTRL_3, 12, rt5645_tdm_dac_swap_select);
1491
1492static const struct snd_kcontrol_new rt5645_if1_dac0_tdm_sel_mux =
1493 SOC_DAPM_ENUM("IF1 DAC0 source", rt5645_tdm_dac0_enum);
1494
1495static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac1_enum,
1496 RT5645_TDM_CTRL_3, 8, rt5645_tdm_dac_swap_select);
1497
1498static const struct snd_kcontrol_new rt5645_if1_dac1_tdm_sel_mux =
1499 SOC_DAPM_ENUM("IF1 DAC1 source", rt5645_tdm_dac1_enum);
1500
1501static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac2_enum,
1502 RT5645_TDM_CTRL_3, 4, rt5645_tdm_dac_swap_select);
1503
1504static const struct snd_kcontrol_new rt5645_if1_dac2_tdm_sel_mux =
1505 SOC_DAPM_ENUM("IF1 DAC2 source", rt5645_tdm_dac2_enum);
1506
1507static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac3_enum,
1508 RT5645_TDM_CTRL_3, 0, rt5645_tdm_dac_swap_select);
1509
1510static const struct snd_kcontrol_new rt5645_if1_dac3_tdm_sel_mux =
1511 SOC_DAPM_ENUM("IF1 DAC3 source", rt5645_tdm_dac3_enum);
1512
1513/* MX-7a [14:12][10:8][6:4][2:0] */
1514static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac0_enum,
1515 RT5650_TDM_CTRL_4, 12, rt5645_tdm_dac_swap_select);
1516
1517static const struct snd_kcontrol_new rt5650_if1_dac0_tdm_sel_mux =
1518 SOC_DAPM_ENUM("IF1 DAC0 source", rt5650_tdm_dac0_enum);
1519
1520static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac1_enum,
1521 RT5650_TDM_CTRL_4, 8, rt5645_tdm_dac_swap_select);
1522
1523static const struct snd_kcontrol_new rt5650_if1_dac1_tdm_sel_mux =
1524 SOC_DAPM_ENUM("IF1 DAC1 source", rt5650_tdm_dac1_enum);
1525
1526static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac2_enum,
1527 RT5650_TDM_CTRL_4, 4, rt5645_tdm_dac_swap_select);
1528
1529static const struct snd_kcontrol_new rt5650_if1_dac2_tdm_sel_mux =
1530 SOC_DAPM_ENUM("IF1 DAC2 source", rt5650_tdm_dac2_enum);
1531
1532static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac3_enum,
1533 RT5650_TDM_CTRL_4, 0, rt5645_tdm_dac_swap_select);
1534
1535static const struct snd_kcontrol_new rt5650_if1_dac3_tdm_sel_mux =
1536 SOC_DAPM_ENUM("IF1 DAC3 source", rt5650_tdm_dac3_enum);
1537
5c4ca99d
BL		 1538/* MX-2d [3] [2] */
1539static const char * const rt5650_a_dac1_src[] = {
1540 "DAC1", "Stereo DAC Mixer"
1541};
1542
1543static SOC_ENUM_SINGLE_DECL(
1544 rt5650_a_dac1_l_enum, RT5650_A_DAC_SOUR,
1545 RT5650_A_DAC1_L_IN_SFT, rt5650_a_dac1_src);
1546
1547static const struct snd_kcontrol_new rt5650_a_dac1_l_mux =
1548 SOC_DAPM_ENUM("A DAC1 L source", rt5650_a_dac1_l_enum);
1549
1550static SOC_ENUM_SINGLE_DECL(
1551 rt5650_a_dac1_r_enum, RT5650_A_DAC_SOUR,
1552 RT5650_A_DAC1_R_IN_SFT, rt5650_a_dac1_src);
1553
1554static const struct snd_kcontrol_new rt5650_a_dac1_r_mux =
1555 SOC_DAPM_ENUM("A DAC1 R source", rt5650_a_dac1_r_enum);
1556
1557/* MX-2d [1] [0] */
1558static const char * const rt5650_a_dac2_src[] = {
1559 "Stereo DAC Mixer", "Mono DAC Mixer"
1560};
1561
1562static SOC_ENUM_SINGLE_DECL(
1563 rt5650_a_dac2_l_enum, RT5650_A_DAC_SOUR,
1564 RT5650_A_DAC2_L_IN_SFT, rt5650_a_dac2_src);
1565
1566static const struct snd_kcontrol_new rt5650_a_dac2_l_mux =
1567 SOC_DAPM_ENUM("A DAC2 L source", rt5650_a_dac2_l_enum);
1568
1569static SOC_ENUM_SINGLE_DECL(
1570 rt5650_a_dac2_r_enum, RT5650_A_DAC_SOUR,
1571 RT5650_A_DAC2_R_IN_SFT, rt5650_a_dac2_src);
1572
1573static const struct snd_kcontrol_new rt5650_a_dac2_r_mux =
1574 SOC_DAPM_ENUM("A DAC2 R source", rt5650_a_dac2_r_enum);
1575
1319b2f6
OC		 1576/* MX-2F [13:12] */
1577static const char * const rt5645_if2_adc_in_src[] = {
1578 "IF_ADC1", "IF_ADC2", "VAD_ADC"
1579};
1580
1581static SOC_ENUM_SINGLE_DECL(
1582 rt5645_if2_adc_in_enum, RT5645_DIG_INF1_DATA,
1583 RT5645_IF2_ADC_IN_SFT, rt5645_if2_adc_in_src);
1584
1585static const struct snd_kcontrol_new rt5645_if2_adc_in_mux =
1586 SOC_DAPM_ENUM("IF2 ADC IN source", rt5645_if2_adc_in_enum);
1587
1588/* MX-2F [1:0] */
1589static const char * const rt5645_if3_adc_in_src[] = {
1590 "IF_ADC1", "IF_ADC2", "VAD_ADC"
1591};
1592
1593static SOC_ENUM_SINGLE_DECL(
1594 rt5645_if3_adc_in_enum, RT5645_DIG_INF1_DATA,
1595 RT5645_IF3_ADC_IN_SFT, rt5645_if3_adc_in_src);
1596
1597static const struct snd_kcontrol_new rt5645_if3_adc_in_mux =
1598 SOC_DAPM_ENUM("IF3 ADC IN source", rt5645_if3_adc_in_enum);
1599
1600/* MX-31 [15] [13] [11] [9] */
1601static const char * const rt5645_pdm_src[] = {
1602 "Mono DAC", "Stereo DAC"
1603};
1604
1605static SOC_ENUM_SINGLE_DECL(
1606 rt5645_pdm1_l_enum, RT5645_PDM_OUT_CTRL,
1607 RT5645_PDM1_L_SFT, rt5645_pdm_src);
1608
1609static const struct snd_kcontrol_new rt5645_pdm1_l_mux =
1610 SOC_DAPM_ENUM("PDM1 L source", rt5645_pdm1_l_enum);
1611
1612static SOC_ENUM_SINGLE_DECL(
1613 rt5645_pdm1_r_enum, RT5645_PDM_OUT_CTRL,
1614 RT5645_PDM1_R_SFT, rt5645_pdm_src);
1615
1616static const struct snd_kcontrol_new rt5645_pdm1_r_mux =
1617 SOC_DAPM_ENUM("PDM1 R source", rt5645_pdm1_r_enum);
1618
1619/* MX-9D [9:8] */
1620static const char * const rt5645_vad_adc_src[] = {
1621 "Sto1 ADC L", "Mono ADC L", "Mono ADC R"
1622};
1623
1624static SOC_ENUM_SINGLE_DECL(
1625 rt5645_vad_adc_enum, RT5645_VAD_CTRL4,
1626 RT5645_VAD_SEL_SFT, rt5645_vad_adc_src);
1627
1628static const struct snd_kcontrol_new rt5645_vad_adc_mux =
1629 SOC_DAPM_ENUM("VAD ADC source", rt5645_vad_adc_enum);
1630
1631static const struct snd_kcontrol_new spk_l_vol_control =
1632 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1633 RT5645_L_MUTE_SFT, 1, 1);
1634
1635static const struct snd_kcontrol_new spk_r_vol_control =
1636 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1637 RT5645_R_MUTE_SFT, 1, 1);
1638
1639static const struct snd_kcontrol_new hp_l_vol_control =
1640 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1641 RT5645_L_MUTE_SFT, 1, 1);
1642
1643static const struct snd_kcontrol_new hp_r_vol_control =
1644 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1645 RT5645_R_MUTE_SFT, 1, 1);
1646
1647static const struct snd_kcontrol_new pdm1_l_vol_control =
1648 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1649 RT5645_M_PDM1_L, 1, 1);
1650
1651static const struct snd_kcontrol_new pdm1_r_vol_control =
1652 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1653 RT5645_M_PDM1_R, 1, 1);
1654
1655static void hp_amp_power(struct snd_soc_codec *codec, int on)
1656{
1657 static int hp_amp_power_count;
1658 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1659
1660 if (on) {
1661 if (hp_amp_power_count <= 0) {
d12d6c4e 1662 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
588cd850 1663 snd_soc_write(codec, RT5645_DEPOP_M2, 0x3100);
d12d6c4e
JL		 1664 snd_soc_write(codec, RT5645_CHARGE_PUMP,
1665 0x0e06);
588cd850
OC		 1666 snd_soc_write(codec, RT5645_DEPOP_M1, 0x000d);
1667 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1668 RT5645_HP_DCC_INT1, 0x9f01);
1669 msleep(20);
1670 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1671 RT5645_HP_CO_MASK, RT5645_HP_CO_EN);
d12d6c4e
JL		 1672 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1673 0x3e, 0x7400);
1674 snd_soc_write(codec, RT5645_DEPOP_M3, 0x0737);
1675 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1676 RT5645_MAMP_INT_REG2, 0xfc00);
1677 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1140);
91ed37e4 1678 msleep(70);
588cd850 1679 rt5645->hp_on = true;
d12d6c4e
JL		 1680 } else {
1681 /* depop parameters */
1682 snd_soc_update_bits(codec, RT5645_DEPOP_M2,
1683 RT5645_DEPOP_MASK, RT5645_DEPOP_MAN);
1684 snd_soc_write(codec, RT5645_DEPOP_M1, 0x000d);
1685 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1686 RT5645_HP_DCC_INT1, 0x9f01);
1687 mdelay(150);
1688 /* headphone amp power on */
1689 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1690 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0);
1691 snd_soc_update_bits(codec, RT5645_PWR_VOL,
1692 RT5645_PWR_HV_L | RT5645_PWR_HV_R,
1693 RT5645_PWR_HV_L | RT5645_PWR_HV_R);
1694 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1695 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1696 RT5645_PWR_HA,
1697 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1698 RT5645_PWR_HA);
1699 mdelay(5);
1700 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1701 RT5645_PWR_FV1 | RT5645_PWR_FV2,
1702 RT5645_PWR_FV1 | RT5645_PWR_FV2);
1703
1704 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1705 RT5645_HP_CO_MASK | RT5645_HP_SG_MASK,
1706 RT5645_HP_CO_EN | RT5645_HP_SG_EN);
1707 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1708 0x14, 0x1aaa);
1709 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1710 0x24, 0x0430);
1711 }
1319b2f6
OC		 1712 }
1713 hp_amp_power_count++;
1714 } else {
1715 hp_amp_power_count--;
1716 if (hp_amp_power_count <= 0) {
d12d6c4e
JL		 1717 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
1718 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1719 0x3e, 0x7400);
1720 snd_soc_write(codec, RT5645_DEPOP_M3, 0x0737);
1721 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1722 RT5645_MAMP_INT_REG2, 0xfc00);
1723 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1140);
1724 msleep(100);
1725 snd_soc_write(codec, RT5645_DEPOP_M1, 0x0001);
1726
1727 } else {
1728 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1729 RT5645_HP_SG_MASK |
1730 RT5645_HP_L_SMT_MASK |
1731 RT5645_HP_R_SMT_MASK,
1732 RT5645_HP_SG_DIS |
1733 RT5645_HP_L_SMT_DIS |
1734 RT5645_HP_R_SMT_DIS);
1735 /* headphone amp power down */
1736 snd_soc_write(codec, RT5645_DEPOP_M1, 0x0000);
1737 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1738 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1739 RT5645_PWR_HA, 0);
1740 snd_soc_update_bits(codec, RT5645_DEPOP_M2,
1741 RT5645_DEPOP_MASK, 0);
1742 }
1319b2f6
OC		 1743 }
1744 }
1745}
1746
1747static int rt5645_hp_event(struct snd_soc_dapm_widget *w,
1748 struct snd_kcontrol *kcontrol, int event)
1749{
c5f596cb 1750 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1319b2f6
OC		 1751 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1752
1753 switch (event) {
1754 case SND_SOC_DAPM_POST_PMU:
1755 hp_amp_power(codec, 1);
1756 /* headphone unmute sequence */
d12d6c4e 1757 if (rt5645->codec_type == CODEC_TYPE_RT5645) {
5c4ca99d
BL		 1758 snd_soc_update_bits(codec, RT5645_DEPOP_M3,
1759 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1760 RT5645_CP_FQ3_MASK,
1761 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ1_SFT) |
1762 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1763 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ3_SFT));
d12d6c4e
JL		 1764 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1765 RT5645_MAMP_INT_REG2, 0xfc00);
1766 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1767 RT5645_SMT_TRIG_MASK, RT5645_SMT_TRIG_EN);
1768 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1769 RT5645_RSTN_MASK, RT5645_RSTN_EN);
1770 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1771 RT5645_RSTN_MASK | RT5645_HP_L_SMT_MASK |
1772 RT5645_HP_R_SMT_MASK, RT5645_RSTN_DIS |
1773 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1774 msleep(40);
1775 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1776 RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK |
1777 RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS |
1778 RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS);
5c4ca99d 1779 }
1319b2f6
OC		 1780 break;
1781
1782 case SND_SOC_DAPM_PRE_PMD:
1783 /* headphone mute sequence */
d12d6c4e 1784 if (rt5645->codec_type == CODEC_TYPE_RT5645) {
5c4ca99d
BL		 1785 snd_soc_update_bits(codec, RT5645_DEPOP_M3,
1786 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1787 RT5645_CP_FQ3_MASK,
1788 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ1_SFT) |
1789 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1790 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ3_SFT));
d12d6c4e
JL		 1791 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1792 RT5645_MAMP_INT_REG2, 0xfc00);
1793 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1794 RT5645_HP_SG_MASK, RT5645_HP_SG_EN);
1795 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1796 RT5645_RSTP_MASK, RT5645_RSTP_EN);
1797 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1798 RT5645_RSTP_MASK | RT5645_HP_L_SMT_MASK |
1799 RT5645_HP_R_SMT_MASK, RT5645_RSTP_DIS |
1800 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1801 msleep(30);
5c4ca99d 1802 }
1319b2f6
OC		 1803 hp_amp_power(codec, 0);
1804 break;
1805
1806 default:
1807 return 0;
1808 }
1809
1810 return 0;
1811}
1812
1813static int rt5645_spk_event(struct snd_soc_dapm_widget *w,
1814 struct snd_kcontrol *kcontrol, int event)
1815{
c5f596cb 1816 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1319b2f6
OC		 1817
1818 switch (event) {
1819 case SND_SOC_DAPM_POST_PMU:
be77b38a 1820 rt5645_enable_hweq(codec);
1319b2f6
OC		 1821 snd_soc_update_bits(codec, RT5645_PWR_DIG1,
1822 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1823 RT5645_PWR_CLS_D_L,
1824 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1825 RT5645_PWR_CLS_D_L);
1826 break;
1827
1828 case SND_SOC_DAPM_PRE_PMD:
be77b38a 1829 snd_soc_write(codec, RT5645_EQ_CTRL2, 0);
1319b2f6
OC		 1830 snd_soc_update_bits(codec, RT5645_PWR_DIG1,
1831 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1832 RT5645_PWR_CLS_D_L, 0);
1833 break;
1834
1835 default:
1836 return 0;
1837 }
1838
1839 return 0;
1840}
1841
1842static int rt5645_lout_event(struct snd_soc_dapm_widget *w,
1843 struct snd_kcontrol *kcontrol, int event)
1844{
c5f596cb 1845 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1319b2f6
OC		 1846
1847 switch (event) {
1848 case SND_SOC_DAPM_POST_PMU:
1849 hp_amp_power(codec, 1);
1850 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1851 RT5645_PWR_LM, RT5645_PWR_LM);
1852 snd_soc_update_bits(codec, RT5645_LOUT1,
1853 RT5645_L_MUTE | RT5645_R_MUTE, 0);
1854 break;
1855
1856 case SND_SOC_DAPM_PRE_PMD:
1857 snd_soc_update_bits(codec, RT5645_LOUT1,
1858 RT5645_L_MUTE | RT5645_R_MUTE,
1859 RT5645_L_MUTE | RT5645_R_MUTE);
1860 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1861 RT5645_PWR_LM, 0);
1862 hp_amp_power(codec, 0);
1863 break;
1864
1865 default:
1866 return 0;
1867 }
1868
1869 return 0;
1870}
1871
1872static int rt5645_bst2_event(struct snd_soc_dapm_widget *w,
1873 struct snd_kcontrol *kcontrol, int event)
1874{
c5f596cb 1875 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1319b2f6
OC		 1876
1877 switch (event) {
1878 case SND_SOC_DAPM_POST_PMU:
1879 snd_soc_update_bits(codec, RT5645_PWR_ANLG2,
1880 RT5645_PWR_BST2_P, RT5645_PWR_BST2_P);
1881 break;
1882
1883 case SND_SOC_DAPM_PRE_PMD:
1884 snd_soc_update_bits(codec, RT5645_PWR_ANLG2,
1885 RT5645_PWR_BST2_P, 0);
1886 break;
1887
1888 default:
1889 return 0;
1890 }
1891
1892 return 0;
1893}
1894
588cd850
OC		 1895static int rt5650_hp_event(struct snd_soc_dapm_widget *w,
1896 struct snd_kcontrol *k, int event)
1897{
1898 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1899 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1900
1901 switch (event) {
1902 case SND_SOC_DAPM_POST_PMU:
1903 if (rt5645->hp_on) {
1904 msleep(100);
1905 rt5645->hp_on = false;
1906 }
1907 break;
1908
1909 default:
1910 return 0;
1911 }
1912
1913 return 0;
1914}
1915
1319b2f6
OC		 1916static const struct snd_soc_dapm_widget rt5645_dapm_widgets[] = {
1917 SND_SOC_DAPM_SUPPLY("LDO2", RT5645_PWR_MIXER,
1918 RT5645_PWR_LDO2_BIT, 0, NULL, 0),
1919 SND_SOC_DAPM_SUPPLY("PLL1", RT5645_PWR_ANLG2,
1920 RT5645_PWR_PLL_BIT, 0, NULL, 0),
1921
1922 SND_SOC_DAPM_SUPPLY("JD Power", RT5645_PWR_ANLG2,
1923 RT5645_PWR_JD1_BIT, 0, NULL, 0),
1924 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5645_PWR_VOL,
1925 RT5645_PWR_MIC_DET_BIT, 0, NULL, 0),
1926
9e268353
BL		 1927 /* ASRC */
1928 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5645_ASRC_1,
1929 11, 0, NULL, 0),
1930 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5645_ASRC_1,
1931 12, 0, NULL, 0),
1932 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5645_ASRC_1,
1933 10, 0, NULL, 0),
1934 SND_SOC_DAPM_SUPPLY_S("DAC MONO L ASRC", 1, RT5645_ASRC_1,
1935 9, 0, NULL, 0),
1936 SND_SOC_DAPM_SUPPLY_S("DAC MONO R ASRC", 1, RT5645_ASRC_1,
1937 8, 0, NULL, 0),
1938 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5645_ASRC_1,
1939 7, 0, NULL, 0),
1940 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5645_ASRC_1,
1941 5, 0, NULL, 0),
1942 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5645_ASRC_1,
1943 4, 0, NULL, 0),
1944 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5645_ASRC_1,
1945 3, 0, NULL, 0),
1946 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5645_ASRC_1,
1947 1, 0, NULL, 0),
1948 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5645_ASRC_1,
1949 0, 0, NULL, 0),
1950
1319b2f6
OC		 1951 /* Input Side */
1952 /* micbias */
1953 SND_SOC_DAPM_MICBIAS("micbias1", RT5645_PWR_ANLG2,
1954 RT5645_PWR_MB1_BIT, 0),
1955 SND_SOC_DAPM_MICBIAS("micbias2", RT5645_PWR_ANLG2,
1956 RT5645_PWR_MB2_BIT, 0),
1957 /* Input Lines */
1958 SND_SOC_DAPM_INPUT("DMIC L1"),
1959 SND_SOC_DAPM_INPUT("DMIC R1"),
1960 SND_SOC_DAPM_INPUT("DMIC L2"),
1961 SND_SOC_DAPM_INPUT("DMIC R2"),
1962
1963 SND_SOC_DAPM_INPUT("IN1P"),
1964 SND_SOC_DAPM_INPUT("IN1N"),
1965 SND_SOC_DAPM_INPUT("IN2P"),
1966 SND_SOC_DAPM_INPUT("IN2N"),
1967
1968 SND_SOC_DAPM_INPUT("Haptic Generator"),
1969
1970 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1971 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1972 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1973 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1974 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5645_DMIC_CTRL1,
1975 RT5645_DMIC_1_EN_SFT, 0, NULL, 0),
1976 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5645_DMIC_CTRL1,
1977 RT5645_DMIC_2_EN_SFT, 0, NULL, 0),
1978 /* Boost */
1979 SND_SOC_DAPM_PGA("BST1", RT5645_PWR_ANLG2,
1980 RT5645_PWR_BST1_BIT, 0, NULL, 0),
1981 SND_SOC_DAPM_PGA_E("BST2", RT5645_PWR_ANLG2,
1982 RT5645_PWR_BST2_BIT, 0, NULL, 0, rt5645_bst2_event,
1983 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1984 /* Input Volume */
1985 SND_SOC_DAPM_PGA("INL VOL", RT5645_PWR_VOL,
1986 RT5645_PWR_IN_L_BIT, 0, NULL, 0),
1987 SND_SOC_DAPM_PGA("INR VOL", RT5645_PWR_VOL,
1988 RT5645_PWR_IN_R_BIT, 0, NULL, 0),
1989 /* REC Mixer */
1990 SND_SOC_DAPM_MIXER("RECMIXL", RT5645_PWR_MIXER, RT5645_PWR_RM_L_BIT,
1991 0, rt5645_rec_l_mix, ARRAY_SIZE(rt5645_rec_l_mix)),
1992 SND_SOC_DAPM_MIXER("RECMIXR", RT5645_PWR_MIXER, RT5645_PWR_RM_R_BIT,
1993 0, rt5645_rec_r_mix, ARRAY_SIZE(rt5645_rec_r_mix)),
1994 /* ADCs */
1995 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
1996 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
1997
1998 SND_SOC_DAPM_SUPPLY("ADC L power", RT5645_PWR_DIG1,
1999 RT5645_PWR_ADC_L_BIT, 0, NULL, 0),
2000 SND_SOC_DAPM_SUPPLY("ADC R power", RT5645_PWR_DIG1,
2001 RT5645_PWR_ADC_R_BIT, 0, NULL, 0),
2002
2003 /* ADC Mux */
2004 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
2005 &rt5645_sto1_dmic_mux),
2006 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2007 &rt5645_sto_adc2_mux),
2008 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2009 &rt5645_sto_adc2_mux),
2010 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2011 &rt5645_sto_adc1_mux),
2012 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2013 &rt5645_sto_adc1_mux),
2014 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2015 &rt5645_mono_dmic_l_mux),
2016 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2017 &rt5645_mono_dmic_r_mux),
2018 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2019 &rt5645_mono_adc_l2_mux),
2020 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2021 &rt5645_mono_adc_l1_mux),
2022 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2023 &rt5645_mono_adc_r1_mux),
2024 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2025 &rt5645_mono_adc_r2_mux),
2026 /* ADC Mixer */
2027
2028 SND_SOC_DAPM_SUPPLY_S("adc stereo1 filter", 1, RT5645_PWR_DIG2,
2029 RT5645_PWR_ADC_S1F_BIT, 0, NULL, 0),
1319b2f6
OC		 2030 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
2031 rt5645_sto1_adc_l_mix, ARRAY_SIZE(rt5645_sto1_adc_l_mix),
2032 NULL, 0),
2033 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2034 rt5645_sto1_adc_r_mix, ARRAY_SIZE(rt5645_sto1_adc_r_mix),
2035 NULL, 0),
2036 SND_SOC_DAPM_SUPPLY_S("adc mono left filter", 1, RT5645_PWR_DIG2,
2037 RT5645_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2038 SND_SOC_DAPM_MIXER_E("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
2039 rt5645_mono_adc_l_mix, ARRAY_SIZE(rt5645_mono_adc_l_mix),
2040 NULL, 0),
2041 SND_SOC_DAPM_SUPPLY_S("adc mono right filter", 1, RT5645_PWR_DIG2,
2042 RT5645_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2043 SND_SOC_DAPM_MIXER_E("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
2044 rt5645_mono_adc_r_mix, ARRAY_SIZE(rt5645_mono_adc_r_mix),
2045 NULL, 0),
2046
2047 /* ADC PGA */
2048 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2049 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2050 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2051 SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2052 SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2053 SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2054 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2055 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2056 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2057 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2058
2059 /* IF1 2 Mux */
1319b2f6
OC		 2060 SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM,
2061 0, 0, &rt5645_if2_adc_in_mux),
2062
2063 /* Digital Interface */
2064 SND_SOC_DAPM_SUPPLY("I2S1", RT5645_PWR_DIG1,
2065 RT5645_PWR_I2S1_BIT, 0, NULL, 0),
786aa09b 2066 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
1319b2f6
OC		 2067 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2068 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
786aa09b 2069 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1319b2f6
OC		 2070 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2071 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2072 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2073 SND_SOC_DAPM_SUPPLY("I2S2", RT5645_PWR_DIG1,
2074 RT5645_PWR_I2S2_BIT, 0, NULL, 0),
2075 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2076 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2077 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2078 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2079
2080 /* Digital Interface Select */
2081 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM,
2082 0, 0, &rt5645_vad_adc_mux),
2083
2084 /* Audio Interface */
2085 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
2086 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
2087 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
2088 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
2089
2090 /* Output Side */
2091 /* DAC mixer before sound effect */
2092 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
2093 rt5645_dac_l_mix, ARRAY_SIZE(rt5645_dac_l_mix)),
2094 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
2095 rt5645_dac_r_mix, ARRAY_SIZE(rt5645_dac_r_mix)),
2096
2097 /* DAC2 channel Mux */
2098 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_l2_mux),
2099 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_r2_mux),
2100 SND_SOC_DAPM_PGA("DAC L2 Volume", RT5645_PWR_DIG1,
2101 RT5645_PWR_DAC_L2_BIT, 0, NULL, 0),
2102 SND_SOC_DAPM_PGA("DAC R2 Volume", RT5645_PWR_DIG1,
2103 RT5645_PWR_DAC_R2_BIT, 0, NULL, 0),
2104
2105 SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1l_mux),
2106 SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1r_mux),
2107
2108 /* DAC Mixer */
2109 SND_SOC_DAPM_SUPPLY_S("dac stereo1 filter", 1, RT5645_PWR_DIG2,
2110 RT5645_PWR_DAC_S1F_BIT, 0, NULL, 0),
2111 SND_SOC_DAPM_SUPPLY_S("dac mono left filter", 1, RT5645_PWR_DIG2,
2112 RT5645_PWR_DAC_MF_L_BIT, 0, NULL, 0),
2113 SND_SOC_DAPM_SUPPLY_S("dac mono right filter", 1, RT5645_PWR_DIG2,
2114 RT5645_PWR_DAC_MF_R_BIT, 0, NULL, 0),
2115 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
2116 rt5645_sto_dac_l_mix, ARRAY_SIZE(rt5645_sto_dac_l_mix)),
2117 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
2118 rt5645_sto_dac_r_mix, ARRAY_SIZE(rt5645_sto_dac_r_mix)),
2119 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
2120 rt5645_mono_dac_l_mix, ARRAY_SIZE(rt5645_mono_dac_l_mix)),
2121 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
2122 rt5645_mono_dac_r_mix, ARRAY_SIZE(rt5645_mono_dac_r_mix)),
2123 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
2124 rt5645_dig_l_mix, ARRAY_SIZE(rt5645_dig_l_mix)),
2125 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
2126 rt5645_dig_r_mix, ARRAY_SIZE(rt5645_dig_r_mix)),
2127
2128 /* DACs */
2129 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L1_BIT,
2130 0),
2131 SND_SOC_DAPM_DAC("DAC L2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L2_BIT,
2132 0),
2133 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R1_BIT,
2134 0),
2135 SND_SOC_DAPM_DAC("DAC R2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R2_BIT,
2136 0),
2137 /* OUT Mixer */
2138 SND_SOC_DAPM_MIXER("SPK MIXL", RT5645_PWR_MIXER, RT5645_PWR_SM_L_BIT,
2139 0, rt5645_spk_l_mix, ARRAY_SIZE(rt5645_spk_l_mix)),
2140 SND_SOC_DAPM_MIXER("SPK MIXR", RT5645_PWR_MIXER, RT5645_PWR_SM_R_BIT,
2141 0, rt5645_spk_r_mix, ARRAY_SIZE(rt5645_spk_r_mix)),
2142 SND_SOC_DAPM_MIXER("OUT MIXL", RT5645_PWR_MIXER, RT5645_PWR_OM_L_BIT,
2143 0, rt5645_out_l_mix, ARRAY_SIZE(rt5645_out_l_mix)),
2144 SND_SOC_DAPM_MIXER("OUT MIXR", RT5645_PWR_MIXER, RT5645_PWR_OM_R_BIT,
2145 0, rt5645_out_r_mix, ARRAY_SIZE(rt5645_out_r_mix)),
2146 /* Ouput Volume */
2147 SND_SOC_DAPM_SWITCH("SPKVOL L", RT5645_PWR_VOL, RT5645_PWR_SV_L_BIT, 0,
2148 &spk_l_vol_control),
2149 SND_SOC_DAPM_SWITCH("SPKVOL R", RT5645_PWR_VOL, RT5645_PWR_SV_R_BIT, 0,
2150 &spk_r_vol_control),
2151 SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5645_PWR_VOL, RT5645_PWR_HV_L_BIT,
2152 0, rt5645_hpvoll_mix, ARRAY_SIZE(rt5645_hpvoll_mix)),
2153 SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5645_PWR_VOL, RT5645_PWR_HV_R_BIT,
2154 0, rt5645_hpvolr_mix, ARRAY_SIZE(rt5645_hpvolr_mix)),
2155 SND_SOC_DAPM_SUPPLY("HPOVOL MIXL Power", RT5645_PWR_MIXER,
2156 RT5645_PWR_HM_L_BIT, 0, NULL, 0),
2157 SND_SOC_DAPM_SUPPLY("HPOVOL MIXR Power", RT5645_PWR_MIXER,
2158 RT5645_PWR_HM_R_BIT, 0, NULL, 0),
2159 SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 0, 0, NULL, 0),
2160 SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM, 0, 0, NULL, 0),
2161 SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM, 0, 0, NULL, 0),
2162 SND_SOC_DAPM_SWITCH("HPOVOL L", SND_SOC_NOPM, 0, 0, &hp_l_vol_control),
2163 SND_SOC_DAPM_SWITCH("HPOVOL R", SND_SOC_NOPM, 0, 0, &hp_r_vol_control),
2164
2165 /* HPO/LOUT/Mono Mixer */
2166 SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_l_mix,
2167 ARRAY_SIZE(rt5645_spo_l_mix)),
2168 SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_r_mix,
2169 ARRAY_SIZE(rt5645_spo_r_mix)),
2170 SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0, rt5645_hpo_mix,
2171 ARRAY_SIZE(rt5645_hpo_mix)),
2172 SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0, rt5645_lout_mix,
2173 ARRAY_SIZE(rt5645_lout_mix)),
2174
2175 SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0, rt5645_hp_event,
2176 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2177 SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0, rt5645_lout_event,
2178 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2179 SND_SOC_DAPM_PGA_S("SPK amp", 2, SND_SOC_NOPM, 0, 0, rt5645_spk_event,
2180 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2181
2182 /* PDM */
2183 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5645_PWR_DIG2, RT5645_PWR_PDM1_BIT,
2184 0, NULL, 0),
2185 SND_SOC_DAPM_MUX("PDM1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_l_mux),
2186 SND_SOC_DAPM_MUX("PDM1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_r_mux),
2187
2188 SND_SOC_DAPM_SWITCH("PDM1 L", SND_SOC_NOPM, 0, 0, &pdm1_l_vol_control),
2189 SND_SOC_DAPM_SWITCH("PDM1 R", SND_SOC_NOPM, 0, 0, &pdm1_r_vol_control),
2190
2191 /* Output Lines */
2192 SND_SOC_DAPM_OUTPUT("HPOL"),
2193 SND_SOC_DAPM_OUTPUT("HPOR"),
2194 SND_SOC_DAPM_OUTPUT("LOUTL"),
2195 SND_SOC_DAPM_OUTPUT("LOUTR"),
2196 SND_SOC_DAPM_OUTPUT("PDM1L"),
2197 SND_SOC_DAPM_OUTPUT("PDM1R"),
2198 SND_SOC_DAPM_OUTPUT("SPOL"),
2199 SND_SOC_DAPM_OUTPUT("SPOR"),
588cd850 2200 SND_SOC_DAPM_POST("DAPM_POST", rt5650_hp_event),
1319b2f6
OC		 2201};
2202
83c09290
BL		 2203static const struct snd_soc_dapm_widget rt5645_specific_dapm_widgets[] = {
2204 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0,
2205 &rt5645_if1_dac0_tdm_sel_mux),
2206 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0,
2207 &rt5645_if1_dac1_tdm_sel_mux),
2208 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0,
2209 &rt5645_if1_dac2_tdm_sel_mux),
2210 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0,
2211 &rt5645_if1_dac3_tdm_sel_mux),
2212 SND_SOC_DAPM_MUX("RT5645 IF1 ADC Mux", SND_SOC_NOPM,
2213 0, 0, &rt5645_if1_adc_in_mux),
2214 SND_SOC_DAPM_MUX("RT5645 IF1 ADC1 Swap Mux", SND_SOC_NOPM,
2215 0, 0, &rt5645_if1_adc1_in_mux),
2216 SND_SOC_DAPM_MUX("RT5645 IF1 ADC2 Swap Mux", SND_SOC_NOPM,
2217 0, 0, &rt5645_if1_adc2_in_mux),
2218 SND_SOC_DAPM_MUX("RT5645 IF1 ADC3 Swap Mux", SND_SOC_NOPM,
2219 0, 0, &rt5645_if1_adc3_in_mux),
1319b2f6
OC		 2220};
2221
5c4ca99d
BL		 2222static const struct snd_soc_dapm_widget rt5650_specific_dapm_widgets[] = {
2223 SND_SOC_DAPM_MUX("A DAC1 L Mux", SND_SOC_NOPM,
2224 0, 0, &rt5650_a_dac1_l_mux),
2225 SND_SOC_DAPM_MUX("A DAC1 R Mux", SND_SOC_NOPM,
2226 0, 0, &rt5650_a_dac1_r_mux),
2227 SND_SOC_DAPM_MUX("A DAC2 L Mux", SND_SOC_NOPM,
2228 0, 0, &rt5650_a_dac2_l_mux),
2229 SND_SOC_DAPM_MUX("A DAC2 R Mux", SND_SOC_NOPM,
2230 0, 0, &rt5650_a_dac2_r_mux),
851b81e8
MC		 2231
2232 SND_SOC_DAPM_MUX("RT5650 IF1 ADC1 Swap Mux", SND_SOC_NOPM,
2233 0, 0, &rt5650_if1_adc1_in_mux),
2234 SND_SOC_DAPM_MUX("RT5650 IF1 ADC2 Swap Mux", SND_SOC_NOPM,
2235 0, 0, &rt5650_if1_adc2_in_mux),
2236 SND_SOC_DAPM_MUX("RT5650 IF1 ADC3 Swap Mux", SND_SOC_NOPM,
2237 0, 0, &rt5650_if1_adc3_in_mux),
2238 SND_SOC_DAPM_MUX("RT5650 IF1 ADC Mux", SND_SOC_NOPM,
2239 0, 0, &rt5650_if1_adc_in_mux),
2240
2241 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0,
2242 &rt5650_if1_dac0_tdm_sel_mux),
2243 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0,
2244 &rt5650_if1_dac1_tdm_sel_mux),
2245 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0,
2246 &rt5650_if1_dac2_tdm_sel_mux),
2247 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0,
2248 &rt5650_if1_dac3_tdm_sel_mux),
5c4ca99d
BL		 2249};
2250
1319b2f6 2251static const struct snd_soc_dapm_route rt5645_dapm_routes[] = {
9e268353 2252 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
9e268353
BL		 2253 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
2254 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
2255 { "dac mono left filter", NULL, "DAC MONO L ASRC", is_using_asrc },
2256 { "dac mono right filter", NULL, "DAC MONO R ASRC", is_using_asrc },
2257 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
2258
2259 { "I2S1", NULL, "I2S1 ASRC" },
2260 { "I2S2", NULL, "I2S2 ASRC" },
2261
1319b2f6
OC		 2262 { "IN1P", NULL, "LDO2" },
2263 { "IN2P", NULL, "LDO2" },
2264
2265 { "DMIC1", NULL, "DMIC L1" },
2266 { "DMIC1", NULL, "DMIC R1" },
2267 { "DMIC2", NULL, "DMIC L2" },
2268 { "DMIC2", NULL, "DMIC R2" },
2269
2270 { "BST1", NULL, "IN1P" },
2271 { "BST1", NULL, "IN1N" },
2272 { "BST1", NULL, "JD Power" },
2273 { "BST1", NULL, "Mic Det Power" },
2274 { "BST2", NULL, "IN2P" },
2275 { "BST2", NULL, "IN2N" },
2276
2277 { "INL VOL", NULL, "IN2P" },
2278 { "INR VOL", NULL, "IN2N" },
2279
2280 { "RECMIXL", "HPOL Switch", "HPOL" },
2281 { "RECMIXL", "INL Switch", "INL VOL" },
2282 { "RECMIXL", "BST2 Switch", "BST2" },
2283 { "RECMIXL", "BST1 Switch", "BST1" },
2284 { "RECMIXL", "OUT MIXL Switch", "OUT MIXL" },
2285
2286 { "RECMIXR", "HPOR Switch", "HPOR" },
2287 { "RECMIXR", "INR Switch", "INR VOL" },
2288 { "RECMIXR", "BST2 Switch", "BST2" },
2289 { "RECMIXR", "BST1 Switch", "BST1" },
2290 { "RECMIXR", "OUT MIXR Switch", "OUT MIXR" },
2291
2292 { "ADC L", NULL, "RECMIXL" },
2293 { "ADC L", NULL, "ADC L power" },
2294 { "ADC R", NULL, "RECMIXR" },
2295 { "ADC R", NULL, "ADC R power" },
2296
2297 {"DMIC L1", NULL, "DMIC CLK"},
2298 {"DMIC L1", NULL, "DMIC1 Power"},
2299 {"DMIC R1", NULL, "DMIC CLK"},
2300 {"DMIC R1", NULL, "DMIC1 Power"},
2301 {"DMIC L2", NULL, "DMIC CLK"},
2302 {"DMIC L2", NULL, "DMIC2 Power"},
2303 {"DMIC R2", NULL, "DMIC CLK"},
2304 {"DMIC R2", NULL, "DMIC2 Power"},
2305
2306 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
2307 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
9e268353 2308 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC" },
1319b2f6
OC		 2309
2310 { "Mono DMIC L Mux", "DMIC1", "DMIC L1" },
2311 { "Mono DMIC L Mux", "DMIC2", "DMIC L2" },
9e268353 2312 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC" },
1319b2f6
OC		 2313
2314 { "Mono DMIC R Mux", "DMIC1", "DMIC R1" },
2315 { "Mono DMIC R Mux", "DMIC2", "DMIC R2" },
9e268353 2316 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC" },
1319b2f6
OC		 2317
2318 { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2319 { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
2320 { "Stereo1 ADC L1 Mux", "ADC", "ADC L" },
2321 { "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
2322
2323 { "Stereo1 ADC R1 Mux", "ADC", "ADC R" },
2324 { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
2325 { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2326 { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
2327
2328 { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },
2329 { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
2330 { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
2331 { "Mono ADC L1 Mux", "ADC", "ADC L" },
2332
2333 { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
2334 { "Mono ADC R1 Mux", "ADC", "ADC R" },
2335 { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },
2336 { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
2337
2338 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" },
2339 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" },
2340 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" },
2341 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" },
2342
2343 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
2344 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
2345 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2346
2347 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
2348 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
2349 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2350
2351 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" },
2352 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },
2353 { "Mono ADC MIXL", NULL, "adc mono left filter" },
2354 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
2355
2356 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },
2357 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },
2358 { "Mono ADC MIXR", NULL, "adc mono right filter" },
2359 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
2360
2361 { "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" },
2362 { "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" },
2363 { "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" },
2364
2365 { "IF_ADC1", NULL, "Stereo1 ADC MIXL" },
2366 { "IF_ADC1", NULL, "Stereo1 ADC MIXR" },
2367 { "IF_ADC2", NULL, "Mono ADC MIXL" },
2368 { "IF_ADC2", NULL, "Mono ADC MIXR" },
2369 { "VAD_ADC", NULL, "VAD ADC Mux" },
2370
1319b2f6
OC		 2371 { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" },
2372 { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" },
2373 { "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" },
2374
2375 { "IF1 ADC", NULL, "I2S1" },
1319b2f6
OC		 2376 { "IF2 ADC", NULL, "I2S2" },
2377 { "IF2 ADC", NULL, "IF2 ADC Mux" },
2378
1319b2f6
OC		 2379 { "AIF2TX", NULL, "IF2 ADC" },
2380
21ab3f2b 2381 { "IF1 DAC0", NULL, "AIF1RX" },
1319b2f6
OC		 2382 { "IF1 DAC1", NULL, "AIF1RX" },
2383 { "IF1 DAC2", NULL, "AIF1RX" },
21ab3f2b 2384 { "IF1 DAC3", NULL, "AIF1RX" },
1319b2f6
OC		 2385 { "IF2 DAC", NULL, "AIF2RX" },
2386
21ab3f2b 2387 { "IF1 DAC0", NULL, "I2S1" },
1319b2f6
OC		 2388 { "IF1 DAC1", NULL, "I2S1" },
2389 { "IF1 DAC2", NULL, "I2S1" },
21ab3f2b 2390 { "IF1 DAC3", NULL, "I2S1" },
1319b2f6
OC		 2391 { "IF2 DAC", NULL, "I2S2" },
2392
1319b2f6
OC		 2393 { "IF2 DAC L", NULL, "IF2 DAC" },
2394 { "IF2 DAC R", NULL, "IF2 DAC" },
2395
1319b2f6 2396 { "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" },
1319b2f6
OC		 2397 { "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" },
2398
2399 { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" },
2400 { "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" },
2401 { "DAC1 MIXL", NULL, "dac stereo1 filter" },
2402 { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" },
2403 { "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" },
2404 { "DAC1 MIXR", NULL, "dac stereo1 filter" },
2405
1319b2f6
OC		 2406 { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },
2407 { "DAC L2 Mux", "Mono ADC", "Mono ADC MIXL" },
2408 { "DAC L2 Mux", "VAD_ADC", "VAD_ADC" },
2409 { "DAC L2 Volume", NULL, "DAC L2 Mux" },
2410 { "DAC L2 Volume", NULL, "dac mono left filter" },
2411
1319b2f6
OC		 2412 { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },
2413 { "DAC R2 Mux", "Mono ADC", "Mono ADC MIXR" },
2414 { "DAC R2 Mux", "Haptic", "Haptic Generator" },
2415 { "DAC R2 Volume", NULL, "DAC R2 Mux" },
2416 { "DAC R2 Volume", NULL, "dac mono right filter" },
2417
2418 { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
2419 { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
2420 { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2421 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
2422 { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
2423 { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
2424 { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2425 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
2426
2427 { "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
2428 { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2429 { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
2430 { "Mono DAC MIXL", NULL, "dac mono left filter" },
2431 { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
2432 { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2433 { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
2434 { "Mono DAC MIXR", NULL, "dac mono right filter" },
2435
2436 { "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
2437 { "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2438 { "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
2439 { "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
2440 { "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2441 { "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
2442
1319b2f6 2443 { "DAC L1", NULL, "PLL1", is_sys_clk_from_pll },
1319b2f6 2444 { "DAC R1", NULL, "PLL1", is_sys_clk_from_pll },
1319b2f6 2445 { "DAC L2", NULL, "PLL1", is_sys_clk_from_pll },
1319b2f6
OC		 2446 { "DAC R2", NULL, "PLL1", is_sys_clk_from_pll },
2447
2448 { "SPK MIXL", "BST1 Switch", "BST1" },
2449 { "SPK MIXL", "INL Switch", "INL VOL" },
2450 { "SPK MIXL", "DAC L1 Switch", "DAC L1" },
2451 { "SPK MIXL", "DAC L2 Switch", "DAC L2" },
2452 { "SPK MIXR", "BST2 Switch", "BST2" },
2453 { "SPK MIXR", "INR Switch", "INR VOL" },
2454 { "SPK MIXR", "DAC R1 Switch", "DAC R1" },
2455 { "SPK MIXR", "DAC R2 Switch", "DAC R2" },
2456
2457 { "OUT MIXL", "BST1 Switch", "BST1" },
2458 { "OUT MIXL", "INL Switch", "INL VOL" },
2459 { "OUT MIXL", "DAC L2 Switch", "DAC L2" },
2460 { "OUT MIXL", "DAC L1 Switch", "DAC L1" },
2461
2462 { "OUT MIXR", "BST2 Switch", "BST2" },
2463 { "OUT MIXR", "INR Switch", "INR VOL" },
2464 { "OUT MIXR", "DAC R2 Switch", "DAC R2" },
2465 { "OUT MIXR", "DAC R1 Switch", "DAC R1" },
2466
2467 { "HPOVOL MIXL", "DAC1 Switch", "DAC L1" },
2468 { "HPOVOL MIXL", "DAC2 Switch", "DAC L2" },
2469 { "HPOVOL MIXL", "INL Switch", "INL VOL" },
2470 { "HPOVOL MIXL", "BST1 Switch", "BST1" },
2471 { "HPOVOL MIXL", NULL, "HPOVOL MIXL Power" },
2472 { "HPOVOL MIXR", "DAC1 Switch", "DAC R1" },
2473 { "HPOVOL MIXR", "DAC2 Switch", "DAC R2" },
2474 { "HPOVOL MIXR", "INR Switch", "INR VOL" },
2475 { "HPOVOL MIXR", "BST2 Switch", "BST2" },
2476 { "HPOVOL MIXR", NULL, "HPOVOL MIXR Power" },
2477
2478 { "DAC 2", NULL, "DAC L2" },
2479 { "DAC 2", NULL, "DAC R2" },
2480 { "DAC 1", NULL, "DAC L1" },
2481 { "DAC 1", NULL, "DAC R1" },
2482 { "HPOVOL L", "Switch", "HPOVOL MIXL" },
2483 { "HPOVOL R", "Switch", "HPOVOL MIXR" },
2484 { "HPOVOL", NULL, "HPOVOL L" },
2485 { "HPOVOL", NULL, "HPOVOL R" },
2486 { "HPO MIX", "DAC1 Switch", "DAC 1" },
2487 { "HPO MIX", "HPVOL Switch", "HPOVOL" },
2488
2489 { "SPKVOL L", "Switch", "SPK MIXL" },
2490 { "SPKVOL R", "Switch", "SPK MIXR" },
2491
2492 { "SPOL MIX", "DAC R1 Switch", "DAC R1" },
2493 { "SPOL MIX", "DAC L1 Switch", "DAC L1" },
2494 { "SPOL MIX", "SPKVOL R Switch", "SPKVOL R" },
2495 { "SPOL MIX", "SPKVOL L Switch", "SPKVOL L" },
2496 { "SPOR MIX", "DAC R1 Switch", "DAC R1" },
2497 { "SPOR MIX", "SPKVOL R Switch", "SPKVOL R" },
2498
2499 { "LOUT MIX", "DAC L1 Switch", "DAC L1" },
2500 { "LOUT MIX", "DAC R1 Switch", "DAC R1" },
2501 { "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" },
2502 { "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" },
2503
2504 { "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" },
2505 { "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" },
2506 { "PDM1 L Mux", NULL, "PDM1 Power" },
2507 { "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" },
2508 { "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" },
2509 { "PDM1 R Mux", NULL, "PDM1 Power" },
2510
2511 { "HP amp", NULL, "HPO MIX" },
2512 { "HP amp", NULL, "JD Power" },
2513 { "HP amp", NULL, "Mic Det Power" },
2514 { "HP amp", NULL, "LDO2" },
2515 { "HPOL", NULL, "HP amp" },
2516 { "HPOR", NULL, "HP amp" },
2517
2518 { "LOUT amp", NULL, "LOUT MIX" },
2519 { "LOUTL", NULL, "LOUT amp" },
2520 { "LOUTR", NULL, "LOUT amp" },
2521
2522 { "PDM1 L", "Switch", "PDM1 L Mux" },
2523 { "PDM1 R", "Switch", "PDM1 R Mux" },
2524
2525 { "PDM1L", NULL, "PDM1 L" },
2526 { "PDM1R", NULL, "PDM1 R" },
2527
2528 { "SPK amp", NULL, "SPOL MIX" },
2529 { "SPK amp", NULL, "SPOR MIX" },
2530 { "SPOL", NULL, "SPK amp" },
2531 { "SPOR", NULL, "SPK amp" },
2532};
2533
5c4ca99d
BL		 2534static const struct snd_soc_dapm_route rt5650_specific_dapm_routes[] = {
2535 { "A DAC1 L Mux", "DAC1", "DAC1 MIXL"},
2536 { "A DAC1 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
2537 { "A DAC1 R Mux", "DAC1", "DAC1 MIXR"},
2538 { "A DAC1 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
2539
2540 { "A DAC2 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
2541 { "A DAC2 L Mux", "Mono DAC Mixer", "Mono DAC MIXL"},
2542 { "A DAC2 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
2543 { "A DAC2 R Mux", "Mono DAC Mixer", "Mono DAC MIXR"},
2544
2545 { "DAC L1", NULL, "A DAC1 L Mux" },
2546 { "DAC R1", NULL, "A DAC1 R Mux" },
2547 { "DAC L2", NULL, "A DAC2 L Mux" },
2548 { "DAC R2", NULL, "A DAC2 R Mux" },
21ab3f2b
BL		 2549
2550 { "RT5650 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" },
2551 { "RT5650 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" },
2552 { "RT5650 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" },
2553 { "RT5650 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" },
2554
2555 { "RT5650 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" },
2556 { "RT5650 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" },
2557 { "RT5650 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" },
2558 { "RT5650 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" },
2559
2560 { "RT5650 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" },
2561 { "RT5650 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" },
2562 { "RT5650 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" },
2563 { "RT5650 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" },
2564
2565 { "IF1 ADC", NULL, "RT5650 IF1 ADC1 Swap Mux" },
2566 { "IF1 ADC", NULL, "RT5650 IF1 ADC2 Swap Mux" },
2567 { "IF1 ADC", NULL, "RT5650 IF1 ADC3 Swap Mux" },
2568
2569 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/DAC_REF/Null", "IF1 ADC" },
2570 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/Null/DAC_REF", "IF1 ADC" },
2571 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/IF_ADC2/Null", "IF1 ADC" },
2572 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/Null/IF_ADC2", "IF1 ADC" },
2573 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/DAC_REF/IF_ADC2", "IF1 ADC" },
2574 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/IF_ADC2/DAC_REF", "IF1 ADC" },
2575
2576 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/DAC_REF/Null", "IF1 ADC" },
2577 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/Null/DAC_REF", "IF1 ADC" },
2578 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/IF_ADC1/Null", "IF1 ADC" },
2579 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/Null/IF_ADC1", "IF1 ADC" },
2580 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/DAC_REF/IF_ADC1", "IF1 ADC" },
2581 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/IF_ADC1/DAC_REF", "IF1 ADC" },
2582
2583 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/IF_ADC2/Null", "IF1 ADC" },
2584 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/Null/IF_ADC2", "IF1 ADC" },
2585 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/IF_ADC1/Null", "IF1 ADC" },
2586 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/Null/IF_ADC1", "IF1 ADC" },
2587 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC1/IF_ADC2", "IF1 ADC" },
2588 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC2/IF_ADC1", "IF1 ADC" },
2589
2590 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/IF_ADC2/DAC_REF", "IF1 ADC" },
2591 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/DAC_REF/IF_ADC2", "IF1 ADC" },
2592 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/IF_ADC1/DAC_REF", "IF1 ADC" },
2593 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/DAC_REF/IF_ADC1", "IF1 ADC" },
2594 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC1/IF_ADC2", "IF1 ADC" },
2595 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC2/IF_ADC1", "IF1 ADC" },
2596 { "AIF1TX", NULL, "RT5650 IF1 ADC Mux" },
2597
2598 { "RT5650 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" },
2599 { "RT5650 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" },
2600 { "RT5650 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" },
2601 { "RT5650 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" },
2602
2603 { "RT5650 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" },
2604 { "RT5650 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" },
2605 { "RT5650 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" },
2606 { "RT5650 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" },
2607
2608 { "RT5650 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" },
2609 { "RT5650 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" },
2610 { "RT5650 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" },
2611 { "RT5650 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" },
2612
2613 { "RT5650 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" },
2614 { "RT5650 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" },
2615 { "RT5650 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" },
2616 { "RT5650 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" },
2617
2618 { "DAC1 L Mux", "IF1 DAC", "RT5650 IF1 DAC1 L Mux" },
2619 { "DAC1 R Mux", "IF1 DAC", "RT5650 IF1 DAC1 R Mux" },
2620
2621 { "DAC L2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 L Mux" },
2622 { "DAC R2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 R Mux" },
5c4ca99d
BL		 2623};
2624
2625static const struct snd_soc_dapm_route rt5645_specific_dapm_routes[] = {
2626 { "DAC L1", NULL, "Stereo DAC MIXL" },
2627 { "DAC R1", NULL, "Stereo DAC MIXR" },
2628 { "DAC L2", NULL, "Mono DAC MIXL" },
2629 { "DAC R2", NULL, "Mono DAC MIXR" },
21ab3f2b
BL		 2630
2631 { "RT5645 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" },
2632 { "RT5645 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" },
2633 { "RT5645 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" },
2634 { "RT5645 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" },
2635
2636 { "RT5645 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" },
2637 { "RT5645 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" },
2638 { "RT5645 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" },
2639 { "RT5645 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" },
2640
2641 { "RT5645 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" },
2642 { "RT5645 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" },
2643 { "RT5645 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" },
2644 { "RT5645 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" },
2645
2646 { "IF1 ADC", NULL, "RT5645 IF1 ADC1 Swap Mux" },
2647 { "IF1 ADC", NULL, "RT5645 IF1 ADC2 Swap Mux" },
2648 { "IF1 ADC", NULL, "RT5645 IF1 ADC3 Swap Mux" },
2649
2650 { "RT5645 IF1 ADC Mux", "IF_ADC1/IF_ADC2/VAD_ADC", "IF1 ADC" },
2651 { "RT5645 IF1 ADC Mux", "IF_ADC2/IF_ADC1/VAD_ADC", "IF1 ADC" },
2652 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC1/IF_ADC2", "IF1 ADC" },
2653 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC2/IF_ADC1", "IF1 ADC" },
2654 { "AIF1TX", NULL, "RT5645 IF1 ADC Mux" },
2655
2656 { "RT5645 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" },
2657 { "RT5645 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" },
2658 { "RT5645 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" },
2659 { "RT5645 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" },
2660
2661 { "RT5645 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" },
2662 { "RT5645 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" },
2663 { "RT5645 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" },
2664 { "RT5645 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" },
2665
2666 { "RT5645 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" },
2667 { "RT5645 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" },
2668 { "RT5645 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" },
2669 { "RT5645 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" },
2670
2671 { "RT5645 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" },
2672 { "RT5645 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" },
2673 { "RT5645 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" },
2674 { "RT5645 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" },
2675
2676 { "DAC1 L Mux", "IF1 DAC", "RT5645 IF1 DAC1 L Mux" },
2677 { "DAC1 R Mux", "IF1 DAC", "RT5645 IF1 DAC1 R Mux" },
2678
2679 { "DAC L2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 L Mux" },
2680 { "DAC R2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 R Mux" },
5c4ca99d
BL		 2681};
2682
1319b2f6
OC		 2683static int rt5645_hw_params(struct snd_pcm_substream *substream,
2684 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2685{
2686 struct snd_soc_codec *codec = dai->codec;
2687 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
57bf2736 2688 unsigned int val_len = 0, val_clk, mask_clk, dl_sft;
1319b2f6
OC		 2689 int pre_div, bclk_ms, frame_size;
2690
2691 rt5645->lrck[dai->id] = params_rate(params);
d92950e7 2692 pre_div = rl6231_get_clk_info(rt5645->sysclk, rt5645->lrck[dai->id]);
1319b2f6
OC		 2693 if (pre_div < 0) {
2694 dev_err(codec->dev, "Unsupported clock setting\n");
2695 return -EINVAL;
2696 }
2697 frame_size = snd_soc_params_to_frame_size(params);
2698 if (frame_size < 0) {
2699 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
2700 return -EINVAL;
2701 }
57bf2736
BL		 2702
2703 switch (rt5645->codec_type) {
2704 case CODEC_TYPE_RT5650:
2705 dl_sft = 4;
2706 break;
2707 default:
2708 dl_sft = 2;
2709 break;
2710 }
2711
1319b2f6
OC		 2712 bclk_ms = frame_size > 32;
2713 rt5645->bclk[dai->id] = rt5645->lrck[dai->id] * (32 << bclk_ms);
2714
2715 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
2716 rt5645->bclk[dai->id], rt5645->lrck[dai->id]);
2717 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
2718 bclk_ms, pre_div, dai->id);
2719
2720 switch (params_width(params)) {
2721 case 16:
2722 break;
2723 case 20:
57bf2736 2724 val_len = 0x1;
1319b2f6
OC		 2725 break;
2726 case 24:
57bf2736 2727 val_len = 0x2;
1319b2f6
OC		 2728 break;
2729 case 8:
57bf2736 2730 val_len = 0x3;
1319b2f6
OC		 2731 break;
2732 default:
2733 return -EINVAL;
2734 }
2735
2736 switch (dai->id) {
2737 case RT5645_AIF1:
33de3d54
BL		 2738 mask_clk = RT5645_I2S_PD1_MASK;
2739 val_clk = pre_div << RT5645_I2S_PD1_SFT;
1319b2f6 2740 snd_soc_update_bits(codec, RT5645_I2S1_SDP,
57bf2736 2741 (0x3 << dl_sft), (val_len << dl_sft));
1319b2f6
OC		 2742 snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk);
2743 break;
2744 case RT5645_AIF2:
2745 mask_clk = RT5645_I2S_BCLK_MS2_MASK | RT5645_I2S_PD2_MASK;
2746 val_clk = bclk_ms << RT5645_I2S_BCLK_MS2_SFT |
2747 pre_div << RT5645_I2S_PD2_SFT;
2748 snd_soc_update_bits(codec, RT5645_I2S2_SDP,
57bf2736 2749 (0x3 << dl_sft), (val_len << dl_sft));
1319b2f6
OC		 2750 snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk);
2751 break;
2752 default:
2753 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2754 return -EINVAL;
2755 }
2756
2757 return 0;
2758}
2759
2760static int rt5645_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2761{
2762 struct snd_soc_codec *codec = dai->codec;
2763 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
57bf2736
BL		 2764 unsigned int reg_val = 0, pol_sft;
2765
2766 switch (rt5645->codec_type) {
2767 case CODEC_TYPE_RT5650:
2768 pol_sft = 8;
2769 break;
2770 default:
2771 pol_sft = 7;
2772 break;
2773 }
1319b2f6
OC		 2774
2775 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2776 case SND_SOC_DAIFMT_CBM_CFM:
2777 rt5645->master[dai->id] = 1;
2778 break;
2779 case SND_SOC_DAIFMT_CBS_CFS:
2780 reg_val |= RT5645_I2S_MS_S;
2781 rt5645->master[dai->id] = 0;
2782 break;
2783 default:
2784 return -EINVAL;
2785 }
2786
2787 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2788 case SND_SOC_DAIFMT_NB_NF:
2789 break;
2790 case SND_SOC_DAIFMT_IB_NF:
57bf2736 2791 reg_val |= (1 << pol_sft);
1319b2f6
OC		 2792 break;
2793 default:
2794 return -EINVAL;
2795 }
2796
2797 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2798 case SND_SOC_DAIFMT_I2S:
2799 break;
2800 case SND_SOC_DAIFMT_LEFT_J:
2801 reg_val |= RT5645_I2S_DF_LEFT;
2802 break;
2803 case SND_SOC_DAIFMT_DSP_A:
2804 reg_val |= RT5645_I2S_DF_PCM_A;
2805 break;
2806 case SND_SOC_DAIFMT_DSP_B:
2807 reg_val |= RT5645_I2S_DF_PCM_B;
2808 break;
2809 default:
2810 return -EINVAL;
2811 }
2812 switch (dai->id) {
2813 case RT5645_AIF1:
2814 snd_soc_update_bits(codec, RT5645_I2S1_SDP,
57bf2736 2815 RT5645_I2S_MS_MASK | (1 << pol_sft) |
1319b2f6
OC		 2816 RT5645_I2S_DF_MASK, reg_val);
2817 break;
8c325704
AL		 2818 case RT5645_AIF2:
2819 snd_soc_update_bits(codec, RT5645_I2S2_SDP,
57bf2736 2820 RT5645_I2S_MS_MASK | (1 << pol_sft) |
1319b2f6
OC		 2821 RT5645_I2S_DF_MASK, reg_val);
2822 break;
2823 default:
2824 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2825 return -EINVAL;
2826 }
2827 return 0;
2828}
2829
2830static int rt5645_set_dai_sysclk(struct snd_soc_dai *dai,
2831 int clk_id, unsigned int freq, int dir)
2832{
2833 struct snd_soc_codec *codec = dai->codec;
2834 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2835 unsigned int reg_val = 0;
2836
2837 if (freq == rt5645->sysclk && clk_id == rt5645->sysclk_src)
2838 return 0;
2839
2840 switch (clk_id) {
2841 case RT5645_SCLK_S_MCLK:
2842 reg_val |= RT5645_SCLK_SRC_MCLK;
2843 break;
2844 case RT5645_SCLK_S_PLL1:
2845 reg_val |= RT5645_SCLK_SRC_PLL1;
2846 break;
2847 case RT5645_SCLK_S_RCCLK:
2848 reg_val |= RT5645_SCLK_SRC_RCCLK;
2849 break;
2850 default:
2851 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
2852 return -EINVAL;
2853 }
2854 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2855 RT5645_SCLK_SRC_MASK, reg_val);
2856 rt5645->sysclk = freq;
2857 rt5645->sysclk_src = clk_id;
2858
2859 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
2860
2861 return 0;
2862}
2863
1319b2f6
OC		 2864static int rt5645_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2865 unsigned int freq_in, unsigned int freq_out)
2866{
2867 struct snd_soc_codec *codec = dai->codec;
2868 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
71c7a2d6 2869 struct rl6231_pll_code pll_code;
1319b2f6
OC		 2870 int ret;
2871
2872 if (source == rt5645->pll_src && freq_in == rt5645->pll_in &&
2873 freq_out == rt5645->pll_out)
2874 return 0;
2875
2876 if (!freq_in || !freq_out) {
2877 dev_dbg(codec->dev, "PLL disabled\n");
2878
2879 rt5645->pll_in = 0;
2880 rt5645->pll_out = 0;
2881 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2882 RT5645_SCLK_SRC_MASK, RT5645_SCLK_SRC_MCLK);
2883 return 0;
2884 }
2885
2886 switch (source) {
2887 case RT5645_PLL1_S_MCLK:
2888 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2889 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_MCLK);
2890 break;
2891 case RT5645_PLL1_S_BCLK1:
2892 case RT5645_PLL1_S_BCLK2:
2893 switch (dai->id) {
2894 case RT5645_AIF1:
2895 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2896 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK1);
2897 break;
2898 case RT5645_AIF2:
2899 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2900 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK2);
2901 break;
2902 default:
2903 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2904 return -EINVAL;
2905 }
2906 break;
2907 default:
2908 dev_err(codec->dev, "Unknown PLL source %d\n", source);
2909 return -EINVAL;
2910 }
2911
71c7a2d6 2912 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
1319b2f6
OC		 2913 if (ret < 0) {
2914 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
2915 return ret;
2916 }
2917
2918 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
2919 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2920 pll_code.n_code, pll_code.k_code);
2921
2922 snd_soc_write(codec, RT5645_PLL_CTRL1,
2923 pll_code.n_code << RT5645_PLL_N_SFT | pll_code.k_code);
2924 snd_soc_write(codec, RT5645_PLL_CTRL2,
2925 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5645_PLL_M_SFT |
2926 pll_code.m_bp << RT5645_PLL_M_BP_SFT);
2927
2928 rt5645->pll_in = freq_in;
2929 rt5645->pll_out = freq_out;
2930 rt5645->pll_src = source;
2931
2932 return 0;
2933}
2934
2935static int rt5645_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2936 unsigned int rx_mask, int slots, int slot_width)
2937{
2938 struct snd_soc_codec *codec = dai->codec;
42ce5b8a
BL		 2939 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2940 unsigned int i_slot_sft, o_slot_sft, i_width_sht, o_width_sht, en_sft;
2941 unsigned int mask, val = 0;
2942
2943 switch (rt5645->codec_type) {
2944 case CODEC_TYPE_RT5650:
2945 en_sft = 15;
2946 i_slot_sft = 10;
2947 o_slot_sft = 8;
2948 i_width_sht = 6;
2949 o_width_sht = 4;
2950 mask = 0x8ff0;
2951 break;
2952 default:
2953 en_sft = 14;
2954 i_slot_sft = o_slot_sft = 12;
2955 i_width_sht = o_width_sht = 10;
2956 mask = 0x7c00;
2957 break;
2958 }
850577db 2959 if (rx_mask || tx_mask) {
42ce5b8a
BL		 2960 val |= (1 << en_sft);
2961 if (rt5645->codec_type == CODEC_TYPE_RT5645)
2962 snd_soc_update_bits(codec, RT5645_BASS_BACK,
2963 RT5645_G_BB_BST_MASK, RT5645_G_BB_BST_25DB);
850577db 2964 }
1319b2f6
OC		 2965
2966 switch (slots) {
2967 case 4:
42ce5b8a 2968 val |= (1 << i_slot_sft) | (1 << o_slot_sft);
1319b2f6
OC		 2969 break;
2970 case 6:
42ce5b8a 2971 val |= (2 << i_slot_sft) | (2 << o_slot_sft);
1319b2f6
OC		 2972 break;
2973 case 8:
42ce5b8a 2974 val |= (3 << i_slot_sft) | (3 << o_slot_sft);
1319b2f6
OC		 2975 break;
2976 case 2:
2977 default:
2978 break;
2979 }
2980
2981 switch (slot_width) {
2982 case 20:
42ce5b8a 2983 val |= (1 << i_width_sht) | (1 << o_width_sht);
1319b2f6
OC		 2984 break;
2985 case 24:
42ce5b8a 2986 val |= (2 << i_width_sht) | (2 << o_width_sht);
1319b2f6
OC		 2987 break;
2988 case 32:
42ce5b8a 2989 val |= (3 << i_width_sht) | (3 << o_width_sht);
1319b2f6
OC		 2990 break;
2991 case 16:
2992 default:
2993 break;
2994 }
2995
42ce5b8a 2996 snd_soc_update_bits(codec, RT5645_TDM_CTRL_1, mask, val);
1319b2f6
OC		 2997
2998 return 0;
2999}
3000
3001static int rt5645_set_bias_level(struct snd_soc_codec *codec,
3002 enum snd_soc_bias_level level)
3003{
6e747d53
BL		 3004 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
3005
1319b2f6 3006 switch (level) {
0b2e4959 3007 case SND_SOC_BIAS_PREPARE:
e2ada818 3008 if (SND_SOC_BIAS_STANDBY == snd_soc_codec_get_bias_level(codec)) {
1319b2f6
OC		 3009 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
3010 RT5645_PWR_VREF1 | RT5645_PWR_MB |
3011 RT5645_PWR_BG | RT5645_PWR_VREF2,
3012 RT5645_PWR_VREF1 | RT5645_PWR_MB |
3013 RT5645_PWR_BG | RT5645_PWR_VREF2);
3014 mdelay(10);
3015 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
3016 RT5645_PWR_FV1 | RT5645_PWR_FV2,
3017 RT5645_PWR_FV1 | RT5645_PWR_FV2);
3018 snd_soc_update_bits(codec, RT5645_GEN_CTRL1,
3019 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
3020 }
3021 break;
3022
0b2e4959
BL		 3023 case SND_SOC_BIAS_STANDBY:
3024 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
3025 RT5645_PWR_VREF1 | RT5645_PWR_MB |
3026 RT5645_PWR_BG | RT5645_PWR_VREF2,
3027 RT5645_PWR_VREF1 | RT5645_PWR_MB |
3028 RT5645_PWR_BG | RT5645_PWR_VREF2);
3029 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
3030 RT5645_PWR_FV1 | RT5645_PWR_FV2,
3031 RT5645_PWR_FV1 | RT5645_PWR_FV2);
c962d03b
OC		 3032 if (rt5645->en_button_func &&
3033 snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF)
3034 queue_delayed_work(system_power_efficient_wq,
3035 &rt5645->jack_detect_work, msecs_to_jiffies(0));
0b2e4959
BL		 3036 break;
3037
1319b2f6
OC		 3038 case SND_SOC_BIAS_OFF:
3039 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1100);
6e747d53
BL		 3040 if (!rt5645->en_button_func)
3041 snd_soc_update_bits(codec, RT5645_GEN_CTRL1,
3042 RT5645_DIG_GATE_CTRL, 0);
0b2e4959
BL		 3043 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
3044 RT5645_PWR_VREF1 | RT5645_PWR_MB |
3045 RT5645_PWR_BG | RT5645_PWR_VREF2 |
3046 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0x0);
1319b2f6
OC		 3047 break;
3048
3049 default:
3050 break;
3051 }
1319b2f6
OC		 3052
3053 return 0;
3054}
3055
6e747d53
BL		 3056static void rt5645_enable_push_button_irq(struct snd_soc_codec *codec,
3057 bool enable)
f3fa1bbd 3058{
e2ada818 3059 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
f3fa1bbd 3060
6e747d53 3061 if (enable) {
a4e3c5fa
NB		 3062 snd_soc_dapm_force_enable_pin(dapm, "ADC L power");
3063 snd_soc_dapm_force_enable_pin(dapm, "ADC R power");
3064 snd_soc_dapm_sync(dapm);
22f5d9f8 3065
6e747d53
BL		 3066 snd_soc_update_bits(codec,
3067 RT5645_INT_IRQ_ST, 0x8, 0x8);
3068 snd_soc_update_bits(codec,
3069 RT5650_4BTN_IL_CMD2, 0x8000, 0x8000);
3070 snd_soc_read(codec, RT5650_4BTN_IL_CMD1);
3071 pr_debug("%s read %x = %x\n", __func__, RT5650_4BTN_IL_CMD1,
3072 snd_soc_read(codec, RT5650_4BTN_IL_CMD1));
3073 } else {
3074 snd_soc_update_bits(codec, RT5650_4BTN_IL_CMD2, 0x8000, 0x0);
3075 snd_soc_update_bits(codec, RT5645_INT_IRQ_ST, 0x8, 0x0);
22f5d9f8 3076
a4e3c5fa
NB		 3077 snd_soc_dapm_disable_pin(dapm, "ADC L power");
3078 snd_soc_dapm_disable_pin(dapm, "ADC R power");
3079 snd_soc_dapm_sync(dapm);
75945896 3080 }
6e747d53 3081}
f3fa1bbd 3082
6e747d53
BL		 3083static int rt5645_jack_detect(struct snd_soc_codec *codec, int jack_insert)
3084{
e2ada818 3085 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
6e747d53
BL		 3086 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
3087 unsigned int val;
f3fa1bbd 3088
6e747d53 3089 if (jack_insert) {
05a9b46a
JL		 3090 regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0006);
3091
b14c9174
NB		 3092 /* for jack type detect */
3093 snd_soc_dapm_force_enable_pin(dapm, "LDO2");
3094 snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power");
3095 snd_soc_dapm_sync(dapm);
3096 if (!dapm->card->instantiated) {
6e747d53
BL		 3097 /* Power up necessary bits for JD if dapm is
3098 not ready yet */
05a9b46a
JL		 3099 regmap_update_bits(rt5645->regmap, RT5645_PWR_ANLG1,
3100 RT5645_PWR_MB | RT5645_PWR_VREF2,
3101 RT5645_PWR_MB | RT5645_PWR_VREF2);
3102 regmap_update_bits(rt5645->regmap, RT5645_PWR_MIXER,
6e747d53 3103 RT5645_PWR_LDO2, RT5645_PWR_LDO2);
05a9b46a 3104 regmap_update_bits(rt5645->regmap, RT5645_PWR_VOL,
6e747d53
BL		 3105 RT5645_PWR_MIC_DET, RT5645_PWR_MIC_DET);
3106 }
f3fa1bbd 3107
05a9b46a 3108 regmap_write(rt5645->regmap, RT5645_JD_CTRL3, 0x00f0);
f2988afe
OC		 3109 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2,
3110 RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD);
3111 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1,
3112 RT5645_CBJ_BST1_EN, RT5645_CBJ_BST1_EN);
05a9b46a 3113 msleep(100);
f2988afe
OC		 3114 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2,
3115 RT5645_CBJ_MN_JD, 0);
05a9b46a 3116
8db7f56d 3117 msleep(600);
05a9b46a
JL		 3118 regmap_read(rt5645->regmap, RT5645_IN1_CTRL3, &val);
3119 val &= 0x7;
f3fa1bbd
OC		 3120 dev_dbg(codec->dev, "val = %d\n", val);
3121
6e747d53
BL		 3122 if (val == 1 || val == 2) {
3123 rt5645->jack_type = SND_JACK_HEADSET;
3124 if (rt5645->en_button_func) {
6e747d53
BL		 3125 rt5645_enable_push_button_irq(codec, true);
3126 }
3127 } else {
b14c9174
NB		 3128 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
3129 snd_soc_dapm_sync(dapm);
6e747d53
BL		 3130 rt5645->jack_type = SND_JACK_HEADPHONE;
3131 }
917536ae
JL		 3132 if (rt5645->pdata.jd_invert)
3133 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
7ff6319e 3134 RT5645_JD_1_1_MASK, RT5645_JD_1_1_NOR);
6e747d53
BL		 3135 } else { /* jack out */
3136 rt5645->jack_type = 0;
a4e3c5fa 3137
fce97b4d
OC		 3138 regmap_update_bits(rt5645->regmap, RT5645_HP_VOL,
3139 RT5645_L_MUTE | RT5645_R_MUTE,
3140 RT5645_L_MUTE | RT5645_R_MUTE);
f2988afe
OC		 3141 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2,
3142 RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD);
3143 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1,
3144 RT5645_CBJ_BST1_EN, 0);
8db7f56d 3145
6e747d53
BL		 3146 if (rt5645->en_button_func)
3147 rt5645_enable_push_button_irq(codec, false);
a4e3c5fa
NB		 3148
3149 if (rt5645->pdata.jd_mode == 0)
3150 snd_soc_dapm_disable_pin(dapm, "LDO2");
3151 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
3152 snd_soc_dapm_sync(dapm);
917536ae
JL		 3153 if (rt5645->pdata.jd_invert)
3154 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
7ff6319e 3155 RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV);
f3fa1bbd
OC		 3156 }
3157
6e747d53 3158 return rt5645->jack_type;
f3fa1bbd
OC		 3159}
3160
f312bc59
NB		 3161static int rt5645_button_detect(struct snd_soc_codec *codec)
3162{
3163 int btn_type, val;
3164
3165 val = snd_soc_read(codec, RT5650_4BTN_IL_CMD1);
3166 pr_debug("val=0x%x\n", val);
3167 btn_type = val & 0xfff0;
3168 snd_soc_write(codec, RT5650_4BTN_IL_CMD1, val);
3169
3170 return btn_type;
3171}
3172
345b0f50 3173static irqreturn_t rt5645_irq(int irq, void *data);
d5660422 3174
f3fa1bbd 3175int rt5645_set_jack_detect(struct snd_soc_codec *codec,
6e747d53
BL		 3176 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack,
3177 struct snd_soc_jack *btn_jack)
f3fa1bbd
OC		 3178{
3179 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
3180
471f208a
BL		 3181 rt5645->hp_jack = hp_jack;
3182 rt5645->mic_jack = mic_jack;
6e747d53
BL		 3183 rt5645->btn_jack = btn_jack;
3184 if (rt5645->btn_jack && rt5645->codec_type == CODEC_TYPE_RT5650) {
3185 rt5645->en_button_func = true;
3186 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3187 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);
6e747d53
BL		 3188 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL1,
3189 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
3190 }
345b0f50 3191 rt5645_irq(0, rt5645);
f3fa1bbd
OC		 3192
3193 return 0;
3194}
3195EXPORT_SYMBOL_GPL(rt5645_set_jack_detect);
3196
cd6e82b8
OC		 3197static void rt5645_jack_detect_work(struct work_struct *work)
3198{
3199 struct rt5645_priv *rt5645 =
3200 container_of(work, struct rt5645_priv, jack_detect_work.work);
6e747d53
BL		 3201 int val, btn_type, gpio_state = 0, report = 0;
3202
f2a5ded3 3203 if (!rt5645->codec)
f136dce4 3204 return;
f2a5ded3 3205
6e747d53
BL		 3206 switch (rt5645->pdata.jd_mode) {
3207 case 0: /* Not using rt5645 JD */
0b0cefc8
OC		 3208 if (rt5645->gpiod_hp_det) {
3209 gpio_state = gpiod_get_value(rt5645->gpiod_hp_det);
3210 dev_dbg(rt5645->codec->dev, "gpio_state = %d\n",
3211 gpio_state);
3212 report = rt5645_jack_detect(rt5645->codec, gpio_state);
6e747d53
BL		 3213 }
3214 snd_soc_jack_report(rt5645->hp_jack,
3215 report, SND_JACK_HEADPHONE);
3216 snd_soc_jack_report(rt5645->mic_jack,
3217 report, SND_JACK_MICROPHONE);
f312bc59 3218 return;
6e747d53
BL		 3219 case 1: /* 2 port */
3220 val = snd_soc_read(rt5645->codec, RT5645_A_JD_CTRL1) & 0x0070;
3221 break;
3222 default: /* 1 port */
3223 val = snd_soc_read(rt5645->codec, RT5645_A_JD_CTRL1) & 0x0020;
3224 break;
3225
3226 }
3227
3228 switch (val) {
3229 /* jack in */
3230 case 0x30: /* 2 port */
3231 case 0x0: /* 1 port or 2 port */
3232 if (rt5645->jack_type == 0) {
3233 report = rt5645_jack_detect(rt5645->codec, 1);
3234 /* for push button and jack out */
3235 break;
3236 }
3237 btn_type = 0;
3238 if (snd_soc_read(rt5645->codec, RT5645_INT_IRQ_ST) & 0x4) {
3239 /* button pressed */
3240 report = SND_JACK_HEADSET;
3241 btn_type = rt5645_button_detect(rt5645->codec);
3242 /* rt5650 can report three kinds of button behavior,
3243 one click, double click and hold. However,
3244 currently we will report button pressed/released
3245 event. So all the three button behaviors are
3246 treated as button pressed. */
3247 switch (btn_type) {
3248 case 0x8000:
3249 case 0x4000:
3250 case 0x2000:
3251 report |= SND_JACK_BTN_0;
3252 break;
3253 case 0x1000:
3254 case 0x0800:
3255 case 0x0400:
3256 report |= SND_JACK_BTN_1;
3257 break;
3258 case 0x0200:
3259 case 0x0100:
3260 case 0x0080:
3261 report |= SND_JACK_BTN_2;
3262 break;
3263 case 0x0040:
3264 case 0x0020:
3265 case 0x0010:
3266 report |= SND_JACK_BTN_3;
3267 break;
3268 case 0x0000: /* unpressed */
3269 break;
3270 default:
3271 dev_err(rt5645->codec->dev,
3272 "Unexpected button code 0x%04x\n",
3273 btn_type);
3274 break;
3275 }
3276 }
3277 if (btn_type == 0)/* button release */
3278 report = rt5645->jack_type;
7ff6319e
BL		 3279 else {
3280 if (rt5645->pdata.jd_invert) {
3281 mod_timer(&rt5645->btn_check_timer,
3282 msecs_to_jiffies(100));
3283 }
3284 }
6e747d53
BL		 3285
3286 break;
3287 /* jack out */
3288 case 0x70: /* 2 port */
3289 case 0x10: /* 2 port */
3290 case 0x20: /* 1 port */
3291 report = 0;
3292 snd_soc_update_bits(rt5645->codec,
3293 RT5645_INT_IRQ_ST, 0x1, 0x0);
3294 rt5645_jack_detect(rt5645->codec, 0);
3295 break;
3296 default:
3297 break;
3298 }
3299
3300 snd_soc_jack_report(rt5645->hp_jack, report, SND_JACK_HEADPHONE);
3301 snd_soc_jack_report(rt5645->mic_jack, report, SND_JACK_MICROPHONE);
3302 if (rt5645->en_button_func)
3303 snd_soc_jack_report(rt5645->btn_jack,
e0b5d906
BL		 3304 report, SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3305 SND_JACK_BTN_2 | SND_JACK_BTN_3);
f312bc59 3306}
6e747d53 3307
7099ee85
OC		 3308static void rt5645_rcclock_work(struct work_struct *work)
3309{
3310 struct rt5645_priv *rt5645 =
3311 container_of(work, struct rt5645_priv, rcclock_work.work);
3312
3313 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
3314 RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PD);
3315}
3316
f312bc59
NB		 3317static irqreturn_t rt5645_irq(int irq, void *data)
3318{
3319 struct rt5645_priv *rt5645 = data;
3320
3321 queue_delayed_work(system_power_efficient_wq,
3322 &rt5645->jack_detect_work, msecs_to_jiffies(250));
6e747d53 3323
f312bc59 3324 return IRQ_HANDLED;
6e747d53
BL		 3325}
3326
7ff6319e
BL		 3327static void rt5645_btn_check_callback(unsigned long data)
3328{
3329 struct rt5645_priv *rt5645 = (struct rt5645_priv *)data;
3330
3331 queue_delayed_work(system_power_efficient_wq,
3332 &rt5645->jack_detect_work, msecs_to_jiffies(5));
3333}
3334
1319b2f6
OC		 3335static int rt5645_probe(struct snd_soc_codec *codec)
3336{
e2ada818 3337 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
1319b2f6
OC		 3338 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
3339
3340 rt5645->codec = codec;
3341
5c4ca99d
BL		 3342 switch (rt5645->codec_type) {
3343 case CODEC_TYPE_RT5645:
f2a76385 3344 snd_soc_dapm_new_controls(dapm,
83c09290
BL		 3345 rt5645_specific_dapm_widgets,
3346 ARRAY_SIZE(rt5645_specific_dapm_widgets));
e2ada818 3347 snd_soc_dapm_add_routes(dapm,
5c4ca99d
BL		 3348 rt5645_specific_dapm_routes,
3349 ARRAY_SIZE(rt5645_specific_dapm_routes));
3350 break;
3351 case CODEC_TYPE_RT5650:
e2ada818 3352 snd_soc_dapm_new_controls(dapm,
5c4ca99d
BL		 3353 rt5650_specific_dapm_widgets,
3354 ARRAY_SIZE(rt5650_specific_dapm_widgets));
e2ada818 3355 snd_soc_dapm_add_routes(dapm,
5c4ca99d
BL		 3356 rt5650_specific_dapm_routes,
3357 ARRAY_SIZE(rt5650_specific_dapm_routes));
3358 break;
3359 }
3360
bd1204cb 3361 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF);
1319b2f6 3362
bb656add 3363 /* for JD function */
ac4fc3ee 3364 if (rt5645->pdata.jd_mode) {
e2ada818
LPC		 3365 snd_soc_dapm_force_enable_pin(dapm, "JD Power");
3366 snd_soc_dapm_force_enable_pin(dapm, "LDO2");
3367 snd_soc_dapm_sync(dapm);
bb656add
BL		 3368 }
3369
be77b38a
OC		 3370 rt5645->eq_param = devm_kzalloc(codec->dev,
3371 RT5645_HWEQ_NUM * sizeof(struct rt5645_eq_param_s), GFP_KERNEL);
3372
1319b2f6
OC		 3373 return 0;
3374}
3375
3376static int rt5645_remove(struct snd_soc_codec *codec)
3377{
3378 rt5645_reset(codec);
3379 return 0;
3380}
3381
3382#ifdef CONFIG_PM
3383static int rt5645_suspend(struct snd_soc_codec *codec)
3384{
3385 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
3386
3387 regcache_cache_only(rt5645->regmap, true);
3388 regcache_mark_dirty(rt5645->regmap);
3389
3390 return 0;
3391}
3392
3393static int rt5645_resume(struct snd_soc_codec *codec)
3394{
3395 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
3396
3397 regcache_cache_only(rt5645->regmap, false);
0f776efd 3398 regcache_sync(rt5645->regmap);
1319b2f6
OC		 3399
3400 return 0;
3401}
3402#else
3403#define rt5645_suspend NULL
3404#define rt5645_resume NULL
3405#endif
3406
3407#define RT5645_STEREO_RATES SNDRV_PCM_RATE_8000_96000
3408#define RT5645_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3409 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
3410
64793047 3411static const struct snd_soc_dai_ops rt5645_aif_dai_ops = {
1319b2f6
OC		 3412 .hw_params = rt5645_hw_params,
3413 .set_fmt = rt5645_set_dai_fmt,
3414 .set_sysclk = rt5645_set_dai_sysclk,
3415 .set_tdm_slot = rt5645_set_tdm_slot,
3416 .set_pll = rt5645_set_dai_pll,
3417};
3418
9e22f782 3419static struct snd_soc_dai_driver rt5645_dai[] = {
1319b2f6
OC		 3420 {
3421 .name = "rt5645-aif1",
3422 .id = RT5645_AIF1,
3423 .playback = {
3424 .stream_name = "AIF1 Playback",
3425 .channels_min = 1,
3426 .channels_max = 2,
3427 .rates = RT5645_STEREO_RATES,
3428 .formats = RT5645_FORMATS,
3429 },
3430 .capture = {
3431 .stream_name = "AIF1 Capture",
3432 .channels_min = 1,
fbe039bb 3433 .channels_max = 4,
1319b2f6
OC		 3434 .rates = RT5645_STEREO_RATES,
3435 .formats = RT5645_FORMATS,
3436 },
3437 .ops = &rt5645_aif_dai_ops,
3438 },
3439 {
3440 .name = "rt5645-aif2",
3441 .id = RT5645_AIF2,
3442 .playback = {
3443 .stream_name = "AIF2 Playback",
3444 .channels_min = 1,
3445 .channels_max = 2,
3446 .rates = RT5645_STEREO_RATES,
3447 .formats = RT5645_FORMATS,
3448 },
3449 .capture = {
3450 .stream_name = "AIF2 Capture",
3451 .channels_min = 1,
3452 .channels_max = 2,
3453 .rates = RT5645_STEREO_RATES,
3454 .formats = RT5645_FORMATS,
3455 },
3456 .ops = &rt5645_aif_dai_ops,
3457 },
3458};
3459
3460static struct snd_soc_codec_driver soc_codec_dev_rt5645 = {
3461 .probe = rt5645_probe,
3462 .remove = rt5645_remove,
3463 .suspend = rt5645_suspend,
3464 .resume = rt5645_resume,
3465 .set_bias_level = rt5645_set_bias_level,
3466 .idle_bias_off = true,
3467 .controls = rt5645_snd_controls,
3468 .num_controls = ARRAY_SIZE(rt5645_snd_controls),
3469 .dapm_widgets = rt5645_dapm_widgets,
3470 .num_dapm_widgets = ARRAY_SIZE(rt5645_dapm_widgets),
3471 .dapm_routes = rt5645_dapm_routes,
3472 .num_dapm_routes = ARRAY_SIZE(rt5645_dapm_routes),
3473};
3474
3475static const struct regmap_config rt5645_regmap = {
3476 .reg_bits = 8,
3477 .val_bits = 16,
afefc128 3478 .use_single_rw = true,
1319b2f6
OC		 3479 .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) *
3480 RT5645_PR_SPACING),
3481 .volatile_reg = rt5645_volatile_register,
3482 .readable_reg = rt5645_readable_register,
3483
3484 .cache_type = REGCACHE_RBTREE,
3485 .reg_defaults = rt5645_reg,
3486 .num_reg_defaults = ARRAY_SIZE(rt5645_reg),
3487 .ranges = rt5645_ranges,
3488 .num_ranges = ARRAY_SIZE(rt5645_ranges),
3489};
3490
49abc6cd
BL		 3491static const struct regmap_config rt5650_regmap = {
3492 .reg_bits = 8,
3493 .val_bits = 16,
3494 .use_single_rw = true,
3495 .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) *
3496 RT5645_PR_SPACING),
3497 .volatile_reg = rt5645_volatile_register,
3498 .readable_reg = rt5645_readable_register,
3499
3500 .cache_type = REGCACHE_RBTREE,
3501 .reg_defaults = rt5650_reg,
3502 .num_reg_defaults = ARRAY_SIZE(rt5650_reg),
3503 .ranges = rt5645_ranges,
3504 .num_ranges = ARRAY_SIZE(rt5645_ranges),
3505};
3506
3507static const struct regmap_config temp_regmap = {
3508 .name="nocache",
3509 .reg_bits = 8,
3510 .val_bits = 16,
3511 .use_single_rw = true,
3512 .max_register = RT5645_VENDOR_ID2 + 1,
3513 .cache_type = REGCACHE_NONE,
3514};
3515
1319b2f6
OC		 3516static const struct i2c_device_id rt5645_i2c_id[] = {
3517 { "rt5645", 0 },
5c4ca99d 3518 { "rt5650", 0 },
1319b2f6
OC		 3519 { }
3520};
3521MODULE_DEVICE_TABLE(i2c, rt5645_i2c_id);
3522
3168c201
FY		 3523#ifdef CONFIG_ACPI
3524static struct acpi_device_id rt5645_acpi_match[] = {
3525 { "10EC5645", 0 },
3526 { "10EC5650", 0 },
3527 {},
3528};
3529MODULE_DEVICE_TABLE(acpi, rt5645_acpi_match);
3530#endif
3531
9761c0f6 3532static struct rt5645_platform_data general_platform_data = {
ac4fc3ee 3533 .dmic1_data_pin = RT5645_DMIC1_DISABLE,
78c34fd4 3534 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
78c34fd4
FY		 3535 .jd_mode = 3,
3536};
3537
0bc7d10c 3538static const struct dmi_system_id dmi_platform_intel_braswell[] = {
78c34fd4
FY		 3539 {
3540 .ident = "Intel Strago",
78c34fd4
FY		 3541 .matches = {
3542 DMI_MATCH(DMI_PRODUCT_NAME, "Strago"),
3543 },
3544 },
c1713485 3545 {
9761c0f6 3546 .ident = "Google Chrome",
721b51fc 3547 .matches = {
9761c0f6 3548 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
6b3cecd1
BL		 3549 },
3550 },
78c34fd4
FY		 3551 { }
3552};
3553
e9159e75
JL		 3554static struct rt5645_platform_data buddy_platform_data = {
3555 .dmic1_data_pin = RT5645_DMIC_DATA_GPIO5,
3556 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
3557 .jd_mode = 3,
917536ae 3558 .jd_invert = true,
e9159e75
JL		 3559};
3560
dc542fb4 3561static struct dmi_system_id dmi_platform_intel_broadwell[] = {
e9159e75
JL		 3562 {
3563 .ident = "Chrome Buddy",
e9159e75
JL		 3564 .matches = {
3565 DMI_MATCH(DMI_PRODUCT_NAME, "Buddy"),
3566 },
3567 },
3568 { }
3569};
3570
9761c0f6
BL		 3571static bool rt5645_check_dp(struct device *dev)
3572{
3573 if (device_property_present(dev, "realtek,in2-differential") ||
3574 device_property_present(dev, "realtek,dmic1-data-pin") ||
3575 device_property_present(dev, "realtek,dmic2-data-pin") ||
3576 device_property_present(dev, "realtek,jd-mode"))
3577 return true;
3578
3579 return false;
3580}
e9159e75 3581
48edaa4b
OC		 3582static int rt5645_parse_dt(struct rt5645_priv *rt5645, struct device *dev)
3583{
3584 rt5645->pdata.in2_diff = device_property_read_bool(dev,
3585 "realtek,in2-differential");
3586 device_property_read_u32(dev,
3587 "realtek,dmic1-data-pin", &rt5645->pdata.dmic1_data_pin);
3588 device_property_read_u32(dev,
3589 "realtek,dmic2-data-pin", &rt5645->pdata.dmic2_data_pin);
3590 device_property_read_u32(dev,
3591 "realtek,jd-mode", &rt5645->pdata.jd_mode);
3592
3593 return 0;
3594}
3595
1319b2f6
OC		 3596static int rt5645_i2c_probe(struct i2c_client *i2c,
3597 const struct i2c_device_id *id)
3598{
3599 struct rt5645_platform_data *pdata = dev_get_platdata(&i2c->dev);
3600 struct rt5645_priv *rt5645;
9fc114c5 3601 int ret, i;
1319b2f6 3602 unsigned int val;
49abc6cd 3603 struct regmap *regmap;
1319b2f6
OC		 3604
3605 rt5645 = devm_kzalloc(&i2c->dev, sizeof(struct rt5645_priv),
3606 GFP_KERNEL);
3607 if (rt5645 == NULL)
3608 return -ENOMEM;
3609
f3fa1bbd 3610 rt5645->i2c = i2c;
1319b2f6
OC		 3611 i2c_set_clientdata(i2c, rt5645);
3612
48edaa4b 3613 if (pdata)
1319b2f6 3614 rt5645->pdata = *pdata;
9761c0f6
BL		 3615 else if (dmi_check_system(dmi_platform_intel_broadwell))
3616 rt5645->pdata = buddy_platform_data;
3617 else if (rt5645_check_dp(&i2c->dev))
48edaa4b 3618 rt5645_parse_dt(rt5645, &i2c->dev);
9761c0f6
BL		 3619 else if (dmi_check_system(dmi_platform_intel_braswell))
3620 rt5645->pdata = general_platform_data;
1319b2f6 3621
25c8888a
AL		 3622 rt5645->gpiod_hp_det = devm_gpiod_get_optional(&i2c->dev, "hp-detect",
3623 GPIOD_IN);
0b0cefc8
OC		 3624
3625 if (IS_ERR(rt5645->gpiod_hp_det)) {
0b0cefc8 3626 dev_err(&i2c->dev, "failed to initialize gpiod\n");
25c8888a 3627 return PTR_ERR(rt5645->gpiod_hp_det);
0b0cefc8
OC		 3628 }
3629
9fc114c5
KC		 3630 for (i = 0; i < ARRAY_SIZE(rt5645->supplies); i++)
3631 rt5645->supplies[i].supply = rt5645_supply_names[i];
3632
3633 ret = devm_regulator_bulk_get(&i2c->dev,
3634 ARRAY_SIZE(rt5645->supplies),
3635 rt5645->supplies);
3636 if (ret) {
3637 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
3638 return ret;
3639 }
3640
3641 ret = regulator_bulk_enable(ARRAY_SIZE(rt5645->supplies),
3642 rt5645->supplies);
3643 if (ret) {
3644 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
3645 return ret;
3646 }
3647
49abc6cd
BL		 3648 regmap = devm_regmap_init_i2c(i2c, &temp_regmap);
3649 if (IS_ERR(regmap)) {
3650 ret = PTR_ERR(regmap);
3651 dev_err(&i2c->dev, "Failed to allocate temp register map: %d\n",
3652 ret);
3653 return ret;
3654 }
3655 regmap_read(regmap, RT5645_VENDOR_ID2, &val);
5c4ca99d
BL		 3656
3657 switch (val) {
3658 case RT5645_DEVICE_ID:
49abc6cd 3659 rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5645_regmap);
5c4ca99d
BL		 3660 rt5645->codec_type = CODEC_TYPE_RT5645;
3661 break;
3662 case RT5650_DEVICE_ID:
49abc6cd 3663 rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5650_regmap);
5c4ca99d
BL		 3664 rt5645->codec_type = CODEC_TYPE_RT5650;
3665 break;
3666 default:
1319b2f6 3667 dev_err(&i2c->dev,
8f68e80f 3668 "Device with ID register %#x is not rt5645 or rt5650\n",
5c4ca99d 3669 val);
9fc114c5
KC		 3670 ret = -ENODEV;
3671 goto err_enable;
d12d6c4e
JL		 3672 }
3673
49abc6cd
BL		 3674 if (IS_ERR(rt5645->regmap)) {
3675 ret = PTR_ERR(rt5645->regmap);
3676 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
3677 ret);
3678 return ret;
3679 }
3680
1319b2f6
OC		 3681 regmap_write(rt5645->regmap, RT5645_RESET, 0);
3682
3683 ret = regmap_register_patch(rt5645->regmap, init_list,
3684 ARRAY_SIZE(init_list));
3685 if (ret != 0)
3686 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
3687
5c4ca99d
BL		 3688 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
3689 ret = regmap_register_patch(rt5645->regmap, rt5650_init_list,
3690 ARRAY_SIZE(rt5650_init_list));
3691 if (ret != 0)
3692 dev_warn(&i2c->dev, "Apply rt5650 patch failed: %d\n",
3693 ret);
3694 }
3695
1319b2f6
OC		 3696 if (rt5645->pdata.in2_diff)
3697 regmap_update_bits(rt5645->regmap, RT5645_IN2_CTRL,
3698 RT5645_IN_DF2, RT5645_IN_DF2);
3699
ac4fc3ee 3700 if (rt5645->pdata.dmic1_data_pin || rt5645->pdata.dmic2_data_pin) {
1319b2f6
OC		 3701 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3702 RT5645_GP2_PIN_MASK, RT5645_GP2_PIN_DMIC1_SCL);
ac4fc3ee
BL		 3703 }
3704 switch (rt5645->pdata.dmic1_data_pin) {
3705 case RT5645_DMIC_DATA_IN2N:
3706 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3707 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_IN2N);
3708 break;
1319b2f6 3709
ac4fc3ee 3710 case RT5645_DMIC_DATA_GPIO5:
a094935e
BL		 3711 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3712 RT5645_I2S2_DAC_PIN_MASK, RT5645_I2S2_DAC_PIN_GPIO);
ac4fc3ee
BL		 3713 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3714 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO5);
3715 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3716 RT5645_GP5_PIN_MASK, RT5645_GP5_PIN_DMIC1_SDA);
3717 break;
1319b2f6 3718
ac4fc3ee
BL		 3719 case RT5645_DMIC_DATA_GPIO11:
3720 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3721 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO11);
3722 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3723 RT5645_GP11_PIN_MASK,
3724 RT5645_GP11_PIN_DMIC1_SDA);
3725 break;
1319b2f6 3726
ac4fc3ee
BL		 3727 default:
3728 break;
3729 }
1319b2f6 3730
ac4fc3ee
BL		 3731 switch (rt5645->pdata.dmic2_data_pin) {
3732 case RT5645_DMIC_DATA_IN2P:
3733 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3734 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_IN2P);
3735 break;
1319b2f6 3736
ac4fc3ee
BL		 3737 case RT5645_DMIC_DATA_GPIO6:
3738 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3739 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO6);
3740 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3741 RT5645_GP6_PIN_MASK, RT5645_GP6_PIN_DMIC2_SDA);
3742 break;
1319b2f6 3743
ac4fc3ee
BL		 3744 case RT5645_DMIC_DATA_GPIO10:
3745 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3746 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO10);
3747 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3748 RT5645_GP10_PIN_MASK,
3749 RT5645_GP10_PIN_DMIC2_SDA);
3750 break;
1319b2f6 3751
ac4fc3ee
BL		 3752 case RT5645_DMIC_DATA_GPIO12:
3753 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3754 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO12);
3755 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3756 RT5645_GP12_PIN_MASK,
3757 RT5645_GP12_PIN_DMIC2_SDA);
3758 break;
1319b2f6 3759
ac4fc3ee
BL		 3760 default:
3761 break;
1319b2f6
OC		 3762 }
3763
ac4fc3ee 3764 if (rt5645->pdata.jd_mode) {
bb656add 3765 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
ac4fc3ee
BL		 3766 RT5645_IRQ_CLK_GATE_CTRL,
3767 RT5645_IRQ_CLK_GATE_CTRL);
bb656add 3768 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
ac4fc3ee 3769 RT5645_IRQ_CLK_INT, RT5645_IRQ_CLK_INT);
2d4e2d02
BL		 3770 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
3771 RT5645_IRQ_JD_1_1_EN, RT5645_IRQ_JD_1_1_EN);
3772 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
3773 RT5645_JD_PSV_MODE, RT5645_JD_PSV_MODE);
3774 regmap_update_bits(rt5645->regmap, RT5645_HPO_MIXER,
3775 RT5645_IRQ_PSV_MODE, RT5645_IRQ_PSV_MODE);
3776 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
3777 RT5645_MIC2_OVCD_EN, RT5645_MIC2_OVCD_EN);
3778 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3779 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);
3780 switch (rt5645->pdata.jd_mode) {
3781 case 1:
3782 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
3783 RT5645_JD1_MODE_MASK,
3784 RT5645_JD1_MODE_0);
3785 break;
3786 case 2:
3787 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
3788 RT5645_JD1_MODE_MASK,
3789 RT5645_JD1_MODE_1);
3790 break;
3791 case 3:
3792 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
3793 RT5645_JD1_MODE_MASK,
3794 RT5645_JD1_MODE_2);
3795 break;
3796 default:
3797 break;
3798 }
3799 }
3800
7ff6319e
BL		 3801 if (rt5645->pdata.jd_invert) {
3802 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
3803 RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV);
3804 setup_timer(&rt5645->btn_check_timer,
3805 rt5645_btn_check_callback, (unsigned long)rt5645);
3806 }
3807
7ea3470a 3808 INIT_DELAYED_WORK(&rt5645->jack_detect_work, rt5645_jack_detect_work);
7099ee85 3809 INIT_DELAYED_WORK(&rt5645->rcclock_work, rt5645_rcclock_work);
7ea3470a 3810
f3fa1bbd
OC		 3811 if (rt5645->i2c->irq) {
3812 ret = request_threaded_irq(rt5645->i2c->irq, NULL, rt5645_irq,
3813 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
3814 | IRQF_ONESHOT, "rt5645", rt5645);
5168c547 3815 if (ret) {
f3fa1bbd 3816 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
9fc114c5 3817 goto err_enable;
5168c547 3818 }
f3fa1bbd
OC		 3819 }
3820
5168c547
KC		 3821 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5645,
3822 rt5645_dai, ARRAY_SIZE(rt5645_dai));
3823 if (ret)
3824 goto err_irq;
3825
3826 return 0;
3827
3828err_irq:
3829 if (rt5645->i2c->irq)
3830 free_irq(rt5645->i2c->irq, rt5645);
9fc114c5
KC		 3831err_enable:
3832 regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies);
5168c547 3833 return ret;
1319b2f6
OC		 3834}
3835
3836static int rt5645_i2c_remove(struct i2c_client *i2c)
3837{
f3fa1bbd
OC		 3838 struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c);
3839
3840 if (i2c->irq)
3841 free_irq(i2c->irq, rt5645);
3842
cd6e82b8 3843 cancel_delayed_work_sync(&rt5645->jack_detect_work);
7099ee85 3844 cancel_delayed_work_sync(&rt5645->rcclock_work);
cd6e82b8 3845
1319b2f6 3846 snd_soc_unregister_codec(&i2c->dev);
9fc114c5 3847 regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies);
1319b2f6
OC		 3848
3849 return 0;
3850}
3851
f2988afe
OC		 3852static void rt5645_i2c_shutdown(struct i2c_client *i2c)
3853{
3854 struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c);
3855
3856 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
3857 RT5645_RING2_SLEEVE_GND, RT5645_RING2_SLEEVE_GND);
3858 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, RT5645_CBJ_MN_JD,
3859 RT5645_CBJ_MN_JD);
3860 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1, RT5645_CBJ_BST1_EN,
3861 0);
a2c026cf
OC		 3862 msleep(20);
3863 regmap_write(rt5645->regmap, RT5645_RESET, 0);
f2988afe
OC		 3864}
3865
9e22f782 3866static struct i2c_driver rt5645_i2c_driver = {
1319b2f6
OC		 3867 .driver = {
3868 .name = "rt5645",
3168c201 3869 .acpi_match_table = ACPI_PTR(rt5645_acpi_match),
1319b2f6
OC		 3870 },
3871 .probe = rt5645_i2c_probe,
f2988afe
OC		 3872 .remove = rt5645_i2c_remove,
3873 .shutdown = rt5645_i2c_shutdown,
1319b2f6
OC		 3874 .id_table = rt5645_i2c_id,
3875};
3876module_i2c_driver(rt5645_i2c_driver);
3877
3878MODULE_DESCRIPTION("ASoC RT5645 driver");
3879MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
3880MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)