projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ASoC: rt5645: Fix mask for setting RT5645_DMIC_2_DP_GPIO12 bit
[linux-2.6-block.git] / sound / soc / codecs / rt5645.c
CommitLineData
1319b2f6
OC		 1/*
2 * rt5645.c -- RT5645 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/platform_device.h>
19#include <linux/spi/spi.h>
f3fa1bbd 20#include <linux/gpio.h>
3168c201 21#include <linux/acpi.h>
1319b2f6
OC		 22#include <sound/core.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/jack.h>
26#include <sound/soc.h>
27#include <sound/soc-dapm.h>
28#include <sound/initval.h>
29#include <sound/tlv.h>
30
49ef7925 31#include "rl6231.h"
1319b2f6
OC		 32#include "rt5645.h"
33
34#define RT5645_DEVICE_ID 0x6308
5c4ca99d 35#define RT5650_DEVICE_ID 0x6419
1319b2f6
OC		 36
37#define RT5645_PR_RANGE_BASE (0xff + 1)
38#define RT5645_PR_SPACING 0x100
39
40#define RT5645_PR_BASE (RT5645_PR_RANGE_BASE + (0 * RT5645_PR_SPACING))
41
42static const struct regmap_range_cfg rt5645_ranges[] = {
43 {
44 .name = "PR",
45 .range_min = RT5645_PR_BASE,
46 .range_max = RT5645_PR_BASE + 0xf8,
47 .selector_reg = RT5645_PRIV_INDEX,
48 .selector_mask = 0xff,
49 .selector_shift = 0x0,
50 .window_start = RT5645_PRIV_DATA,
51 .window_len = 0x1,
52 },
53};
54
55static const struct reg_default init_list[] = {
56 {RT5645_PR_BASE + 0x3d, 0x3600},
4809b96e
OC		 57 {RT5645_PR_BASE + 0x1c, 0xfd20},
58 {RT5645_PR_BASE + 0x20, 0x611f},
59 {RT5645_PR_BASE + 0x21, 0x4040},
60 {RT5645_PR_BASE + 0x23, 0x0004},
1319b2f6
OC		 61};
62#define RT5645_INIT_REG_LEN ARRAY_SIZE(init_list)
63
5c4ca99d
BL		 64static const struct reg_default rt5650_init_list[] = {
65 {0xf6, 0x0100},
66};
67
1319b2f6
OC		 68static const struct reg_default rt5645_reg[] = {
69 { 0x00, 0x0000 },
70 { 0x01, 0xc8c8 },
71 { 0x02, 0xc8c8 },
72 { 0x03, 0xc8c8 },
73 { 0x0a, 0x0002 },
74 { 0x0b, 0x2827 },
75 { 0x0c, 0xe000 },
76 { 0x0d, 0x0000 },
77 { 0x0e, 0x0000 },
78 { 0x0f, 0x0808 },
79 { 0x14, 0x3333 },
80 { 0x16, 0x4b00 },
81 { 0x18, 0x018b },
82 { 0x19, 0xafaf },
83 { 0x1a, 0xafaf },
84 { 0x1b, 0x0001 },
85 { 0x1c, 0x2f2f },
86 { 0x1d, 0x2f2f },
87 { 0x1e, 0x0000 },
88 { 0x20, 0x0000 },
89 { 0x27, 0x7060 },
90 { 0x28, 0x7070 },
91 { 0x29, 0x8080 },
92 { 0x2a, 0x5656 },
93 { 0x2b, 0x5454 },
94 { 0x2c, 0xaaa0 },
5c4ca99d 95 { 0x2d, 0x0000 },
1319b2f6
OC		 96 { 0x2f, 0x1002 },
97 { 0x31, 0x5000 },
98 { 0x32, 0x0000 },
99 { 0x33, 0x0000 },
100 { 0x34, 0x0000 },
101 { 0x35, 0x0000 },
102 { 0x3b, 0x0000 },
103 { 0x3c, 0x007f },
104 { 0x3d, 0x0000 },
105 { 0x3e, 0x007f },
106 { 0x3f, 0x0000 },
107 { 0x40, 0x001f },
108 { 0x41, 0x0000 },
109 { 0x42, 0x001f },
110 { 0x45, 0x6000 },
111 { 0x46, 0x003e },
112 { 0x47, 0x003e },
113 { 0x48, 0xf807 },
114 { 0x4a, 0x0004 },
115 { 0x4d, 0x0000 },
116 { 0x4e, 0x0000 },
117 { 0x4f, 0x01ff },
118 { 0x50, 0x0000 },
119 { 0x51, 0x0000 },
120 { 0x52, 0x01ff },
121 { 0x53, 0xf000 },
122 { 0x56, 0x0111 },
123 { 0x57, 0x0064 },
124 { 0x58, 0xef0e },
125 { 0x59, 0xf0f0 },
126 { 0x5a, 0xef0e },
127 { 0x5b, 0xf0f0 },
128 { 0x5c, 0xef0e },
129 { 0x5d, 0xf0f0 },
130 { 0x5e, 0xf000 },
131 { 0x5f, 0x0000 },
132 { 0x61, 0x0300 },
133 { 0x62, 0x0000 },
134 { 0x63, 0x00c2 },
135 { 0x64, 0x0000 },
136 { 0x65, 0x0000 },
137 { 0x66, 0x0000 },
138 { 0x6a, 0x0000 },
139 { 0x6c, 0x0aaa },
140 { 0x70, 0x8000 },
141 { 0x71, 0x8000 },
142 { 0x72, 0x8000 },
143 { 0x73, 0x7770 },
144 { 0x74, 0x3e00 },
145 { 0x75, 0x2409 },
146 { 0x76, 0x000a },
147 { 0x77, 0x0c00 },
148 { 0x78, 0x0000 },
df078d29 149 { 0x79, 0x0123 },
1319b2f6
OC		 150 { 0x80, 0x0000 },
151 { 0x81, 0x0000 },
152 { 0x82, 0x0000 },
153 { 0x83, 0x0000 },
154 { 0x84, 0x0000 },
155 { 0x85, 0x0000 },
156 { 0x8a, 0x0000 },
157 { 0x8e, 0x0004 },
158 { 0x8f, 0x1100 },
159 { 0x90, 0x0646 },
160 { 0x91, 0x0c06 },
161 { 0x93, 0x0000 },
162 { 0x94, 0x0200 },
163 { 0x95, 0x0000 },
164 { 0x9a, 0x2184 },
165 { 0x9b, 0x010a },
166 { 0x9c, 0x0aea },
167 { 0x9d, 0x000c },
168 { 0x9e, 0x0400 },
169 { 0xa0, 0xa0a8 },
170 { 0xa1, 0x0059 },
171 { 0xa2, 0x0001 },
172 { 0xae, 0x6000 },
173 { 0xaf, 0x0000 },
174 { 0xb0, 0x6000 },
175 { 0xb1, 0x0000 },
176 { 0xb2, 0x0000 },
177 { 0xb3, 0x001f },
178 { 0xb4, 0x020c },
179 { 0xb5, 0x1f00 },
180 { 0xb6, 0x0000 },
181 { 0xbb, 0x0000 },
182 { 0xbc, 0x0000 },
183 { 0xbd, 0x0000 },
184 { 0xbe, 0x0000 },
185 { 0xbf, 0x3100 },
186 { 0xc0, 0x0000 },
187 { 0xc1, 0x0000 },
188 { 0xc2, 0x0000 },
189 { 0xc3, 0x2000 },
190 { 0xcd, 0x0000 },
191 { 0xce, 0x0000 },
192 { 0xcf, 0x1813 },
193 { 0xd0, 0x0690 },
194 { 0xd1, 0x1c17 },
195 { 0xd3, 0xb320 },
196 { 0xd4, 0x0000 },
197 { 0xd6, 0x0400 },
198 { 0xd9, 0x0809 },
199 { 0xda, 0x0000 },
200 { 0xdb, 0x0003 },
201 { 0xdc, 0x0049 },
202 { 0xdd, 0x001b },
5c4ca99d
BL		 203 { 0xdf, 0x0008 },
204 { 0xe0, 0x4000 },
1319b2f6
OC		 205 { 0xe6, 0x8000 },
206 { 0xe7, 0x0200 },
207 { 0xec, 0xb300 },
208 { 0xed, 0x0000 },
209 { 0xf0, 0x001f },
210 { 0xf1, 0x020c },
211 { 0xf2, 0x1f00 },
212 { 0xf3, 0x0000 },
213 { 0xf4, 0x4000 },
214 { 0xf8, 0x0000 },
215 { 0xf9, 0x0000 },
216 { 0xfa, 0x2060 },
217 { 0xfb, 0x4040 },
218 { 0xfc, 0x0000 },
219 { 0xfd, 0x0002 },
220 { 0xfe, 0x10ec },
221 { 0xff, 0x6308 },
222};
223
224static int rt5645_reset(struct snd_soc_codec *codec)
225{
226 return snd_soc_write(codec, RT5645_RESET, 0);
227}
228
229static bool rt5645_volatile_register(struct device *dev, unsigned int reg)
230{
231 int i;
232
233 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
234 if (reg >= rt5645_ranges[i].range_min &&
235 reg <= rt5645_ranges[i].range_max) {
236 return true;
237 }
238 }
239
240 switch (reg) {
241 case RT5645_RESET:
242 case RT5645_PRIV_DATA:
243 case RT5645_IN1_CTRL1:
244 case RT5645_IN1_CTRL2:
245 case RT5645_IN1_CTRL3:
246 case RT5645_A_JD_CTRL1:
247 case RT5645_ADC_EQ_CTRL1:
248 case RT5645_EQ_CTRL1:
249 case RT5645_ALC_CTRL_1:
250 case RT5645_IRQ_CTRL2:
251 case RT5645_IRQ_CTRL3:
252 case RT5645_INT_IRQ_ST:
253 case RT5645_IL_CMD:
5c4ca99d 254 case RT5650_4BTN_IL_CMD1:
1319b2f6
OC		 255 case RT5645_VENDOR_ID:
256 case RT5645_VENDOR_ID1:
257 case RT5645_VENDOR_ID2:
71bfa9b4 258 return true;
1319b2f6 259 default:
71bfa9b4 260 return false;
1319b2f6
OC		 261 }
262}
263
264static bool rt5645_readable_register(struct device *dev, unsigned int reg)
265{
266 int i;
267
268 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
269 if (reg >= rt5645_ranges[i].range_min &&
270 reg <= rt5645_ranges[i].range_max) {
271 return true;
272 }
273 }
274
275 switch (reg) {
276 case RT5645_RESET:
277 case RT5645_SPK_VOL:
278 case RT5645_HP_VOL:
279 case RT5645_LOUT1:
280 case RT5645_IN1_CTRL1:
281 case RT5645_IN1_CTRL2:
282 case RT5645_IN1_CTRL3:
283 case RT5645_IN2_CTRL:
284 case RT5645_INL1_INR1_VOL:
285 case RT5645_SPK_FUNC_LIM:
286 case RT5645_ADJ_HPF_CTRL:
287 case RT5645_DAC1_DIG_VOL:
288 case RT5645_DAC2_DIG_VOL:
289 case RT5645_DAC_CTRL:
290 case RT5645_STO1_ADC_DIG_VOL:
291 case RT5645_MONO_ADC_DIG_VOL:
292 case RT5645_ADC_BST_VOL1:
293 case RT5645_ADC_BST_VOL2:
294 case RT5645_STO1_ADC_MIXER:
295 case RT5645_MONO_ADC_MIXER:
296 case RT5645_AD_DA_MIXER:
297 case RT5645_STO_DAC_MIXER:
298 case RT5645_MONO_DAC_MIXER:
299 case RT5645_DIG_MIXER:
5c4ca99d 300 case RT5650_A_DAC_SOUR:
1319b2f6
OC		 301 case RT5645_DIG_INF1_DATA:
302 case RT5645_PDM_OUT_CTRL:
303 case RT5645_REC_L1_MIXER:
304 case RT5645_REC_L2_MIXER:
305 case RT5645_REC_R1_MIXER:
306 case RT5645_REC_R2_MIXER:
307 case RT5645_HPMIXL_CTRL:
308 case RT5645_HPOMIXL_CTRL:
309 case RT5645_HPMIXR_CTRL:
310 case RT5645_HPOMIXR_CTRL:
311 case RT5645_HPO_MIXER:
312 case RT5645_SPK_L_MIXER:
313 case RT5645_SPK_R_MIXER:
314 case RT5645_SPO_MIXER:
315 case RT5645_SPO_CLSD_RATIO:
316 case RT5645_OUT_L1_MIXER:
317 case RT5645_OUT_R1_MIXER:
318 case RT5645_OUT_L_GAIN1:
319 case RT5645_OUT_L_GAIN2:
320 case RT5645_OUT_R_GAIN1:
321 case RT5645_OUT_R_GAIN2:
322 case RT5645_LOUT_MIXER:
323 case RT5645_HAPTIC_CTRL1:
324 case RT5645_HAPTIC_CTRL2:
325 case RT5645_HAPTIC_CTRL3:
326 case RT5645_HAPTIC_CTRL4:
327 case RT5645_HAPTIC_CTRL5:
328 case RT5645_HAPTIC_CTRL6:
329 case RT5645_HAPTIC_CTRL7:
330 case RT5645_HAPTIC_CTRL8:
331 case RT5645_HAPTIC_CTRL9:
332 case RT5645_HAPTIC_CTRL10:
333 case RT5645_PWR_DIG1:
334 case RT5645_PWR_DIG2:
335 case RT5645_PWR_ANLG1:
336 case RT5645_PWR_ANLG2:
337 case RT5645_PWR_MIXER:
338 case RT5645_PWR_VOL:
339 case RT5645_PRIV_INDEX:
340 case RT5645_PRIV_DATA:
341 case RT5645_I2S1_SDP:
342 case RT5645_I2S2_SDP:
343 case RT5645_ADDA_CLK1:
344 case RT5645_ADDA_CLK2:
345 case RT5645_DMIC_CTRL1:
346 case RT5645_DMIC_CTRL2:
347 case RT5645_TDM_CTRL_1:
348 case RT5645_TDM_CTRL_2:
df078d29 349 case RT5645_TDM_CTRL_3:
1319b2f6
OC		 350 case RT5645_GLB_CLK:
351 case RT5645_PLL_CTRL1:
352 case RT5645_PLL_CTRL2:
353 case RT5645_ASRC_1:
354 case RT5645_ASRC_2:
355 case RT5645_ASRC_3:
356 case RT5645_ASRC_4:
357 case RT5645_DEPOP_M1:
358 case RT5645_DEPOP_M2:
359 case RT5645_DEPOP_M3:
360 case RT5645_MICBIAS:
361 case RT5645_A_JD_CTRL1:
362 case RT5645_VAD_CTRL4:
363 case RT5645_CLSD_OUT_CTRL:
364 case RT5645_ADC_EQ_CTRL1:
365 case RT5645_ADC_EQ_CTRL2:
366 case RT5645_EQ_CTRL1:
367 case RT5645_EQ_CTRL2:
368 case RT5645_ALC_CTRL_1:
369 case RT5645_ALC_CTRL_2:
370 case RT5645_ALC_CTRL_3:
371 case RT5645_ALC_CTRL_4:
372 case RT5645_ALC_CTRL_5:
373 case RT5645_JD_CTRL:
374 case RT5645_IRQ_CTRL1:
375 case RT5645_IRQ_CTRL2:
376 case RT5645_IRQ_CTRL3:
377 case RT5645_INT_IRQ_ST:
378 case RT5645_GPIO_CTRL1:
379 case RT5645_GPIO_CTRL2:
380 case RT5645_GPIO_CTRL3:
381 case RT5645_BASS_BACK:
382 case RT5645_MP3_PLUS1:
383 case RT5645_MP3_PLUS2:
384 case RT5645_ADJ_HPF1:
385 case RT5645_ADJ_HPF2:
386 case RT5645_HP_CALIB_AMP_DET:
387 case RT5645_SV_ZCD1:
388 case RT5645_SV_ZCD2:
389 case RT5645_IL_CMD:
390 case RT5645_IL_CMD2:
391 case RT5645_IL_CMD3:
5c4ca99d
BL		 392 case RT5650_4BTN_IL_CMD1:
393 case RT5650_4BTN_IL_CMD2:
1319b2f6
OC		 394 case RT5645_DRC1_HL_CTRL1:
395 case RT5645_DRC2_HL_CTRL1:
396 case RT5645_ADC_MONO_HP_CTRL1:
397 case RT5645_ADC_MONO_HP_CTRL2:
398 case RT5645_DRC2_CTRL1:
399 case RT5645_DRC2_CTRL2:
400 case RT5645_DRC2_CTRL3:
401 case RT5645_DRC2_CTRL4:
402 case RT5645_DRC2_CTRL5:
403 case RT5645_JD_CTRL3:
404 case RT5645_JD_CTRL4:
405 case RT5645_GEN_CTRL1:
406 case RT5645_GEN_CTRL2:
407 case RT5645_GEN_CTRL3:
408 case RT5645_VENDOR_ID:
409 case RT5645_VENDOR_ID1:
410 case RT5645_VENDOR_ID2:
71bfa9b4 411 return true;
1319b2f6 412 default:
71bfa9b4 413 return false;
1319b2f6
OC		 414 }
415}
416
417static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
418static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
419static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
420static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
421static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
422
423/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
424static unsigned int bst_tlv[] = {
425 TLV_DB_RANGE_HEAD(7),
426 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
427 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
428 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
429 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
430 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
431 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
432 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
433};
434
435static const char * const rt5645_tdm_data_swap_select[] = {
436 "L/R", "R/L", "L/L", "R/R"
437};
438
439static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot0_1_enum,
440 RT5645_TDM_CTRL_1, 6, rt5645_tdm_data_swap_select);
441
442static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot2_3_enum,
443 RT5645_TDM_CTRL_1, 4, rt5645_tdm_data_swap_select);
444
445static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot4_5_enum,
446 RT5645_TDM_CTRL_1, 2, rt5645_tdm_data_swap_select);
447
448static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot6_7_enum,
449 RT5645_TDM_CTRL_1, 0, rt5645_tdm_data_swap_select);
450
451static const char * const rt5645_tdm_adc_data_select[] = {
452 "1/2/R", "2/1/R", "R/1/2", "R/2/1"
453};
454
455static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_sel_enum,
456 RT5645_TDM_CTRL_1, 8,
457 rt5645_tdm_adc_data_select);
458
459static const struct snd_kcontrol_new rt5645_snd_controls[] = {
460 /* Speaker Output Volume */
461 SOC_DOUBLE("Speaker Channel Switch", RT5645_SPK_VOL,
462 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
463 SOC_DOUBLE_TLV("Speaker Playback Volume", RT5645_SPK_VOL,
464 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
465
466 /* Headphone Output Volume */
467 SOC_DOUBLE("HP Channel Switch", RT5645_HP_VOL,
468 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
469 SOC_DOUBLE_TLV("HP Playback Volume", RT5645_HP_VOL,
470 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
471
472 /* OUTPUT Control */
473 SOC_DOUBLE("OUT Playback Switch", RT5645_LOUT1,
474 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
475 SOC_DOUBLE("OUT Channel Switch", RT5645_LOUT1,
476 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
477 SOC_DOUBLE_TLV("OUT Playback Volume", RT5645_LOUT1,
478 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
479
480 /* DAC Digital Volume */
481 SOC_DOUBLE("DAC2 Playback Switch", RT5645_DAC_CTRL,
482 RT5645_M_DAC_L2_VOL_SFT, RT5645_M_DAC_R2_VOL_SFT, 1, 1),
483 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5645_DAC1_DIG_VOL,
484 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 175, 0, dac_vol_tlv),
485 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5645_DAC2_DIG_VOL,
486 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 175, 0, dac_vol_tlv),
487
488 /* IN1/IN2 Control */
489 SOC_SINGLE_TLV("IN1 Boost", RT5645_IN1_CTRL1,
490 RT5645_BST_SFT1, 8, 0, bst_tlv),
491 SOC_SINGLE_TLV("IN2 Boost", RT5645_IN2_CTRL,
492 RT5645_BST_SFT2, 8, 0, bst_tlv),
493
494 /* INL/INR Volume Control */
495 SOC_DOUBLE_TLV("IN Capture Volume", RT5645_INL1_INR1_VOL,
496 RT5645_INL_VOL_SFT, RT5645_INR_VOL_SFT, 31, 1, in_vol_tlv),
497
498 /* ADC Digital Volume Control */
499 SOC_DOUBLE("ADC Capture Switch", RT5645_STO1_ADC_DIG_VOL,
500 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
501 SOC_DOUBLE_TLV("ADC Capture Volume", RT5645_STO1_ADC_DIG_VOL,
502 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 127, 0, adc_vol_tlv),
503 SOC_DOUBLE("Mono ADC Capture Switch", RT5645_MONO_ADC_DIG_VOL,
504 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
505 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5645_MONO_ADC_DIG_VOL,
506 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 127, 0, adc_vol_tlv),
507
508 /* ADC Boost Volume Control */
509 SOC_DOUBLE_TLV("STO1 ADC Boost Gain", RT5645_ADC_BST_VOL1,
510 RT5645_STO1_ADC_L_BST_SFT, RT5645_STO1_ADC_R_BST_SFT, 3, 0,
511 adc_bst_tlv),
512 SOC_DOUBLE_TLV("STO2 ADC Boost Gain", RT5645_ADC_BST_VOL1,
513 RT5645_STO2_ADC_L_BST_SFT, RT5645_STO2_ADC_R_BST_SFT, 3, 0,
514 adc_bst_tlv),
515
516 /* I2S2 function select */
517 SOC_SINGLE("I2S2 Func Switch", RT5645_GPIO_CTRL1, RT5645_I2S2_SEL_SFT,
518 1, 1),
519
520 /* TDM */
521 SOC_ENUM("TDM Adc Slot0 1 Data", rt5645_tdm_adc_slot0_1_enum),
522 SOC_ENUM("TDM Adc Slot2 3 Data", rt5645_tdm_adc_slot2_3_enum),
523 SOC_ENUM("TDM Adc Slot4 5 Data", rt5645_tdm_adc_slot4_5_enum),
524 SOC_ENUM("TDM Adc Slot6 7 Data", rt5645_tdm_adc_slot6_7_enum),
525 SOC_ENUM("TDM IF1 ADC DATA Sel", rt5645_tdm_adc_sel_enum),
526 SOC_SINGLE("TDM IF1_DAC1_L Sel", RT5645_TDM_CTRL_3, 12, 7, 0),
527 SOC_SINGLE("TDM IF1_DAC1_R Sel", RT5645_TDM_CTRL_3, 8, 7, 0),
528 SOC_SINGLE("TDM IF1_DAC2_L Sel", RT5645_TDM_CTRL_3, 4, 7, 0),
529 SOC_SINGLE("TDM IF1_DAC2_R Sel", RT5645_TDM_CTRL_3, 0, 7, 0),
530};
531
532/**
533 * set_dmic_clk - Set parameter of dmic.
534 *
535 * @w: DAPM widget.
536 * @kcontrol: The kcontrol of this widget.
537 * @event: Event id.
538 *
1319b2f6
OC		 539 */
540static int set_dmic_clk(struct snd_soc_dapm_widget *w,
541 struct snd_kcontrol *kcontrol, int event)
542{
c5f596cb 543 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1319b2f6 544 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
49ef7925
OC		 545 int idx = -EINVAL;
546
547 idx = rl6231_calc_dmic_clk(rt5645->sysclk);
1319b2f6
OC		 548
549 if (idx < 0)
550 dev_err(codec->dev, "Failed to set DMIC clock\n");
551 else
552 snd_soc_update_bits(codec, RT5645_DMIC_CTRL1,
553 RT5645_DMIC_CLK_MASK, idx << RT5645_DMIC_CLK_SFT);
554 return idx;
555}
556
557static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
558 struct snd_soc_dapm_widget *sink)
559{
c5f596cb 560 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
1319b2f6
OC		 561 unsigned int val;
562
c5f596cb 563 val = snd_soc_read(codec, RT5645_GLB_CLK);
1319b2f6
OC		 564 val &= RT5645_SCLK_SRC_MASK;
565 if (val == RT5645_SCLK_SRC_PLL1)
566 return 1;
567 else
568 return 0;
569}
570
9e268353
BL		 571static int is_using_asrc(struct snd_soc_dapm_widget *source,
572 struct snd_soc_dapm_widget *sink)
573{
c5f596cb 574 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
9e268353
BL		 575 unsigned int reg, shift, val;
576
577 switch (source->shift) {
578 case 0:
579 reg = RT5645_ASRC_3;
580 shift = 0;
581 break;
582 case 1:
583 reg = RT5645_ASRC_3;
584 shift = 4;
585 break;
586 case 3:
587 reg = RT5645_ASRC_2;
588 shift = 0;
589 break;
590 case 8:
591 reg = RT5645_ASRC_2;
592 shift = 4;
593 break;
594 case 9:
595 reg = RT5645_ASRC_2;
596 shift = 8;
597 break;
598 case 10:
599 reg = RT5645_ASRC_2;
600 shift = 12;
601 break;
602 default:
603 return 0;
604 }
605
c5f596cb 606 val = (snd_soc_read(codec, reg) >> shift) & 0xf;
9e268353
BL		 607 switch (val) {
608 case 1:
609 case 2:
610 case 3:
611 case 4:
612 return 1;
613 default:
614 return 0;
615 }
616
617}
618
79080a8b
FY		 619/**
620 * rt5645_sel_asrc_clk_src - select ASRC clock source for a set of filters
621 * @codec: SoC audio codec device.
622 * @filter_mask: mask of filters.
623 * @clk_src: clock source
624 *
625 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5645 can
626 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
627 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
628 * ASRC function will track i2s clock and generate a corresponding system clock
629 * for codec. This function provides an API to select the clock source for a
630 * set of filters specified by the mask. And the codec driver will turn on ASRC
631 * for these filters if ASRC is selected as their clock source.
632 */
633int rt5645_sel_asrc_clk_src(struct snd_soc_codec *codec,
634 unsigned int filter_mask, unsigned int clk_src)
635{
636 unsigned int asrc2_mask = 0;
637 unsigned int asrc2_value = 0;
638 unsigned int asrc3_mask = 0;
639 unsigned int asrc3_value = 0;
640
641 switch (clk_src) {
642 case RT5645_CLK_SEL_SYS:
643 case RT5645_CLK_SEL_I2S1_ASRC:
644 case RT5645_CLK_SEL_I2S2_ASRC:
645 case RT5645_CLK_SEL_SYS2:
646 break;
647
648 default:
649 return -EINVAL;
650 }
651
652 if (filter_mask & RT5645_DA_STEREO_FILTER) {
653 asrc2_mask |= RT5645_DA_STO_CLK_SEL_MASK;
654 asrc2_value = (asrc2_value & ~RT5645_DA_STO_CLK_SEL_MASK)
655 | (clk_src << RT5645_DA_STO_CLK_SEL_SFT);
656 }
657
658 if (filter_mask & RT5645_DA_MONO_L_FILTER) {
659 asrc2_mask |= RT5645_DA_MONOL_CLK_SEL_MASK;
660 asrc2_value = (asrc2_value & ~RT5645_DA_MONOL_CLK_SEL_MASK)
661 | (clk_src << RT5645_DA_MONOL_CLK_SEL_SFT);
662 }
663
664 if (filter_mask & RT5645_DA_MONO_R_FILTER) {
665 asrc2_mask |= RT5645_DA_MONOR_CLK_SEL_MASK;
666 asrc2_value = (asrc2_value & ~RT5645_DA_MONOR_CLK_SEL_MASK)
667 | (clk_src << RT5645_DA_MONOR_CLK_SEL_SFT);
668 }
669
670 if (filter_mask & RT5645_AD_STEREO_FILTER) {
671 asrc2_mask |= RT5645_AD_STO1_CLK_SEL_MASK;
672 asrc2_value = (asrc2_value & ~RT5645_AD_STO1_CLK_SEL_MASK)
673 | (clk_src << RT5645_AD_STO1_CLK_SEL_SFT);
674 }
675
676 if (filter_mask & RT5645_AD_MONO_L_FILTER) {
677 asrc3_mask |= RT5645_AD_MONOL_CLK_SEL_MASK;
678 asrc3_value = (asrc3_value & ~RT5645_AD_MONOL_CLK_SEL_MASK)
679 | (clk_src << RT5645_AD_MONOL_CLK_SEL_SFT);
680 }
681
682 if (filter_mask & RT5645_AD_MONO_R_FILTER) {
683 asrc3_mask |= RT5645_AD_MONOR_CLK_SEL_MASK;
684 asrc3_value = (asrc3_value & ~RT5645_AD_MONOR_CLK_SEL_MASK)
685 | (clk_src << RT5645_AD_MONOR_CLK_SEL_SFT);
686 }
687
688 if (asrc2_mask)
689 snd_soc_update_bits(codec, RT5645_ASRC_2,
690 asrc2_mask, asrc2_value);
691
692 if (asrc3_mask)
693 snd_soc_update_bits(codec, RT5645_ASRC_3,
694 asrc3_mask, asrc3_value);
695
696 return 0;
697}
698EXPORT_SYMBOL_GPL(rt5645_sel_asrc_clk_src);
699
1319b2f6
OC		 700/* Digital Mixer */
701static const struct snd_kcontrol_new rt5645_sto1_adc_l_mix[] = {
702 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
703 RT5645_M_ADC_L1_SFT, 1, 1),
704 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
705 RT5645_M_ADC_L2_SFT, 1, 1),
706};
707
708static const struct snd_kcontrol_new rt5645_sto1_adc_r_mix[] = {
709 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
710 RT5645_M_ADC_R1_SFT, 1, 1),
711 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
712 RT5645_M_ADC_R2_SFT, 1, 1),
713};
714
715static const struct snd_kcontrol_new rt5645_mono_adc_l_mix[] = {
716 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
717 RT5645_M_MONO_ADC_L1_SFT, 1, 1),
718 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
719 RT5645_M_MONO_ADC_L2_SFT, 1, 1),
720};
721
722static const struct snd_kcontrol_new rt5645_mono_adc_r_mix[] = {
723 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
724 RT5645_M_MONO_ADC_R1_SFT, 1, 1),
725 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
726 RT5645_M_MONO_ADC_R2_SFT, 1, 1),
727};
728
729static const struct snd_kcontrol_new rt5645_dac_l_mix[] = {
730 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
731 RT5645_M_ADCMIX_L_SFT, 1, 1),
732 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_AD_DA_MIXER,
733 RT5645_M_DAC1_L_SFT, 1, 1),
734};
735
736static const struct snd_kcontrol_new rt5645_dac_r_mix[] = {
737 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
738 RT5645_M_ADCMIX_R_SFT, 1, 1),
739 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_AD_DA_MIXER,
740 RT5645_M_DAC1_R_SFT, 1, 1),
741};
742
743static const struct snd_kcontrol_new rt5645_sto_dac_l_mix[] = {
744 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
745 RT5645_M_DAC_L1_SFT, 1, 1),
746 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_STO_DAC_MIXER,
747 RT5645_M_DAC_L2_SFT, 1, 1),
748 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
749 RT5645_M_DAC_R1_STO_L_SFT, 1, 1),
750};
751
752static const struct snd_kcontrol_new rt5645_sto_dac_r_mix[] = {
753 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
754 RT5645_M_DAC_R1_SFT, 1, 1),
755 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_STO_DAC_MIXER,
756 RT5645_M_DAC_R2_SFT, 1, 1),
757 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
758 RT5645_M_DAC_L1_STO_R_SFT, 1, 1),
759};
760
761static const struct snd_kcontrol_new rt5645_mono_dac_l_mix[] = {
762 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_MONO_DAC_MIXER,
763 RT5645_M_DAC_L1_MONO_L_SFT, 1, 1),
764 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
765 RT5645_M_DAC_L2_MONO_L_SFT, 1, 1),
766 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
767 RT5645_M_DAC_R2_MONO_L_SFT, 1, 1),
768};
769
770static const struct snd_kcontrol_new rt5645_mono_dac_r_mix[] = {
771 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_MONO_DAC_MIXER,
772 RT5645_M_DAC_R1_MONO_R_SFT, 1, 1),
773 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
774 RT5645_M_DAC_R2_MONO_R_SFT, 1, 1),
775 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
776 RT5645_M_DAC_L2_MONO_R_SFT, 1, 1),
777};
778
779static const struct snd_kcontrol_new rt5645_dig_l_mix[] = {
780 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5645_DIG_MIXER,
781 RT5645_M_STO_L_DAC_L_SFT, 1, 1),
782 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
783 RT5645_M_DAC_L2_DAC_L_SFT, 1, 1),
784 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
785 RT5645_M_DAC_R2_DAC_L_SFT, 1, 1),
786};
787
788static const struct snd_kcontrol_new rt5645_dig_r_mix[] = {
789 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5645_DIG_MIXER,
790 RT5645_M_STO_R_DAC_R_SFT, 1, 1),
791 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
792 RT5645_M_DAC_R2_DAC_R_SFT, 1, 1),
793 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
794 RT5645_M_DAC_L2_DAC_R_SFT, 1, 1),
795};
796
797/* Analog Input Mixer */
798static const struct snd_kcontrol_new rt5645_rec_l_mix[] = {
799 SOC_DAPM_SINGLE("HPOL Switch", RT5645_REC_L2_MIXER,
800 RT5645_M_HP_L_RM_L_SFT, 1, 1),
801 SOC_DAPM_SINGLE("INL Switch", RT5645_REC_L2_MIXER,
802 RT5645_M_IN_L_RM_L_SFT, 1, 1),
803 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_L2_MIXER,
804 RT5645_M_BST2_RM_L_SFT, 1, 1),
805 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_L2_MIXER,
806 RT5645_M_BST1_RM_L_SFT, 1, 1),
807 SOC_DAPM_SINGLE("OUT MIXL Switch", RT5645_REC_L2_MIXER,
808 RT5645_M_OM_L_RM_L_SFT, 1, 1),
809};
810
811static const struct snd_kcontrol_new rt5645_rec_r_mix[] = {
812 SOC_DAPM_SINGLE("HPOR Switch", RT5645_REC_R2_MIXER,
813 RT5645_M_HP_R_RM_R_SFT, 1, 1),
814 SOC_DAPM_SINGLE("INR Switch", RT5645_REC_R2_MIXER,
815 RT5645_M_IN_R_RM_R_SFT, 1, 1),
816 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_R2_MIXER,
817 RT5645_M_BST2_RM_R_SFT, 1, 1),
818 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_R2_MIXER,
819 RT5645_M_BST1_RM_R_SFT, 1, 1),
820 SOC_DAPM_SINGLE("OUT MIXR Switch", RT5645_REC_R2_MIXER,
821 RT5645_M_OM_R_RM_R_SFT, 1, 1),
822};
823
824static const struct snd_kcontrol_new rt5645_spk_l_mix[] = {
825 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPK_L_MIXER,
826 RT5645_M_DAC_L1_SM_L_SFT, 1, 1),
827 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_SPK_L_MIXER,
828 RT5645_M_DAC_L2_SM_L_SFT, 1, 1),
829 SOC_DAPM_SINGLE("INL Switch", RT5645_SPK_L_MIXER,
830 RT5645_M_IN_L_SM_L_SFT, 1, 1),
831 SOC_DAPM_SINGLE("BST1 Switch", RT5645_SPK_L_MIXER,
832 RT5645_M_BST1_L_SM_L_SFT, 1, 1),
833};
834
835static const struct snd_kcontrol_new rt5645_spk_r_mix[] = {
836 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPK_R_MIXER,
837 RT5645_M_DAC_R1_SM_R_SFT, 1, 1),
838 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_SPK_R_MIXER,
839 RT5645_M_DAC_R2_SM_R_SFT, 1, 1),
840 SOC_DAPM_SINGLE("INR Switch", RT5645_SPK_R_MIXER,
841 RT5645_M_IN_R_SM_R_SFT, 1, 1),
842 SOC_DAPM_SINGLE("BST2 Switch", RT5645_SPK_R_MIXER,
843 RT5645_M_BST2_R_SM_R_SFT, 1, 1),
844};
845
846static const struct snd_kcontrol_new rt5645_out_l_mix[] = {
847 SOC_DAPM_SINGLE("BST1 Switch", RT5645_OUT_L1_MIXER,
848 RT5645_M_BST1_OM_L_SFT, 1, 1),
849 SOC_DAPM_SINGLE("INL Switch", RT5645_OUT_L1_MIXER,
850 RT5645_M_IN_L_OM_L_SFT, 1, 1),
851 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_OUT_L1_MIXER,
852 RT5645_M_DAC_L2_OM_L_SFT, 1, 1),
853 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_OUT_L1_MIXER,
854 RT5645_M_DAC_L1_OM_L_SFT, 1, 1),
855};
856
857static const struct snd_kcontrol_new rt5645_out_r_mix[] = {
858 SOC_DAPM_SINGLE("BST2 Switch", RT5645_OUT_R1_MIXER,
859 RT5645_M_BST2_OM_R_SFT, 1, 1),
860 SOC_DAPM_SINGLE("INR Switch", RT5645_OUT_R1_MIXER,
861 RT5645_M_IN_R_OM_R_SFT, 1, 1),
862 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_OUT_R1_MIXER,
863 RT5645_M_DAC_R2_OM_R_SFT, 1, 1),
864 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_OUT_R1_MIXER,
865 RT5645_M_DAC_R1_OM_R_SFT, 1, 1),
866};
867
868static const struct snd_kcontrol_new rt5645_spo_l_mix[] = {
869 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
870 RT5645_M_DAC_R1_SPM_L_SFT, 1, 1),
871 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPO_MIXER,
872 RT5645_M_DAC_L1_SPM_L_SFT, 1, 1),
873 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
874 RT5645_M_SV_R_SPM_L_SFT, 1, 1),
875 SOC_DAPM_SINGLE("SPKVOL L Switch", RT5645_SPO_MIXER,
876 RT5645_M_SV_L_SPM_L_SFT, 1, 1),
877};
878
879static const struct snd_kcontrol_new rt5645_spo_r_mix[] = {
880 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
881 RT5645_M_DAC_R1_SPM_R_SFT, 1, 1),
882 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
883 RT5645_M_SV_R_SPM_R_SFT, 1, 1),
884};
885
886static const struct snd_kcontrol_new rt5645_hpo_mix[] = {
887 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPO_MIXER,
888 RT5645_M_DAC1_HM_SFT, 1, 1),
889 SOC_DAPM_SINGLE("HPVOL Switch", RT5645_HPO_MIXER,
890 RT5645_M_HPVOL_HM_SFT, 1, 1),
891};
892
893static const struct snd_kcontrol_new rt5645_hpvoll_mix[] = {
894 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXL_CTRL,
895 RT5645_M_DAC1_HV_SFT, 1, 1),
896 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXL_CTRL,
897 RT5645_M_DAC2_HV_SFT, 1, 1),
898 SOC_DAPM_SINGLE("INL Switch", RT5645_HPOMIXL_CTRL,
899 RT5645_M_IN_HV_SFT, 1, 1),
900 SOC_DAPM_SINGLE("BST1 Switch", RT5645_HPOMIXL_CTRL,
901 RT5645_M_BST1_HV_SFT, 1, 1),
902};
903
904static const struct snd_kcontrol_new rt5645_hpvolr_mix[] = {
905 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXR_CTRL,
906 RT5645_M_DAC1_HV_SFT, 1, 1),
907 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXR_CTRL,
908 RT5645_M_DAC2_HV_SFT, 1, 1),
909 SOC_DAPM_SINGLE("INR Switch", RT5645_HPOMIXR_CTRL,
910 RT5645_M_IN_HV_SFT, 1, 1),
911 SOC_DAPM_SINGLE("BST2 Switch", RT5645_HPOMIXR_CTRL,
912 RT5645_M_BST2_HV_SFT, 1, 1),
913};
914
915static const struct snd_kcontrol_new rt5645_lout_mix[] = {
916 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_LOUT_MIXER,
917 RT5645_M_DAC_L1_LM_SFT, 1, 1),
918 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_LOUT_MIXER,
919 RT5645_M_DAC_R1_LM_SFT, 1, 1),
920 SOC_DAPM_SINGLE("OUTMIX L Switch", RT5645_LOUT_MIXER,
921 RT5645_M_OV_L_LM_SFT, 1, 1),
922 SOC_DAPM_SINGLE("OUTMIX R Switch", RT5645_LOUT_MIXER,
923 RT5645_M_OV_R_LM_SFT, 1, 1),
924};
925
926/*DAC1 L/R source*/ /* MX-29 [9:8] [11:10] */
927static const char * const rt5645_dac1_src[] = {
928 "IF1 DAC", "IF2 DAC", "IF3 DAC"
929};
930
931static SOC_ENUM_SINGLE_DECL(
932 rt5645_dac1l_enum, RT5645_AD_DA_MIXER,
933 RT5645_DAC1_L_SEL_SFT, rt5645_dac1_src);
934
935static const struct snd_kcontrol_new rt5645_dac1l_mux =
936 SOC_DAPM_ENUM("DAC1 L source", rt5645_dac1l_enum);
937
938static SOC_ENUM_SINGLE_DECL(
939 rt5645_dac1r_enum, RT5645_AD_DA_MIXER,
940 RT5645_DAC1_R_SEL_SFT, rt5645_dac1_src);
941
942static const struct snd_kcontrol_new rt5645_dac1r_mux =
943 SOC_DAPM_ENUM("DAC1 R source", rt5645_dac1r_enum);
944
945/*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */
946static const char * const rt5645_dac12_src[] = {
947 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "VAD_ADC"
948};
949
950static SOC_ENUM_SINGLE_DECL(
951 rt5645_dac2l_enum, RT5645_DAC_CTRL,
952 RT5645_DAC2_L_SEL_SFT, rt5645_dac12_src);
953
954static const struct snd_kcontrol_new rt5645_dac_l2_mux =
955 SOC_DAPM_ENUM("DAC2 L source", rt5645_dac2l_enum);
956
957static const char * const rt5645_dacr2_src[] = {
958 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "Haptic"
959};
960
961static SOC_ENUM_SINGLE_DECL(
962 rt5645_dac2r_enum, RT5645_DAC_CTRL,
963 RT5645_DAC2_R_SEL_SFT, rt5645_dacr2_src);
964
965static const struct snd_kcontrol_new rt5645_dac_r2_mux =
966 SOC_DAPM_ENUM("DAC2 R source", rt5645_dac2r_enum);
967
968
969/* INL/R source */
970static const char * const rt5645_inl_src[] = {
971 "IN2P", "MonoP"
972};
973
974static SOC_ENUM_SINGLE_DECL(
975 rt5645_inl_enum, RT5645_INL1_INR1_VOL,
976 RT5645_INL_SEL_SFT, rt5645_inl_src);
977
978static const struct snd_kcontrol_new rt5645_inl_mux =
979 SOC_DAPM_ENUM("INL source", rt5645_inl_enum);
980
981static const char * const rt5645_inr_src[] = {
982 "IN2N", "MonoN"
983};
984
985static SOC_ENUM_SINGLE_DECL(
986 rt5645_inr_enum, RT5645_INL1_INR1_VOL,
987 RT5645_INR_SEL_SFT, rt5645_inr_src);
988
989static const struct snd_kcontrol_new rt5645_inr_mux =
990 SOC_DAPM_ENUM("INR source", rt5645_inr_enum);
991
992/* Stereo1 ADC source */
993/* MX-27 [12] */
994static const char * const rt5645_stereo_adc1_src[] = {
995 "DAC MIX", "ADC"
996};
997
998static SOC_ENUM_SINGLE_DECL(
999 rt5645_stereo1_adc1_enum, RT5645_STO1_ADC_MIXER,
1000 RT5645_ADC_1_SRC_SFT, rt5645_stereo_adc1_src);
1001
1002static const struct snd_kcontrol_new rt5645_sto_adc1_mux =
1003 SOC_DAPM_ENUM("Stereo1 ADC1 Mux", rt5645_stereo1_adc1_enum);
1004
1005/* MX-27 [11] */
1006static const char * const rt5645_stereo_adc2_src[] = {
1007 "DAC MIX", "DMIC"
1008};
1009
1010static SOC_ENUM_SINGLE_DECL(
1011 rt5645_stereo1_adc2_enum, RT5645_STO1_ADC_MIXER,
1012 RT5645_ADC_2_SRC_SFT, rt5645_stereo_adc2_src);
1013
1014static const struct snd_kcontrol_new rt5645_sto_adc2_mux =
1015 SOC_DAPM_ENUM("Stereo1 ADC2 Mux", rt5645_stereo1_adc2_enum);
1016
1017/* MX-27 [8] */
1018static const char * const rt5645_stereo_dmic_src[] = {
1019 "DMIC1", "DMIC2"
1020};
1021
1022static SOC_ENUM_SINGLE_DECL(
1023 rt5645_stereo1_dmic_enum, RT5645_STO1_ADC_MIXER,
1024 RT5645_DMIC_SRC_SFT, rt5645_stereo_dmic_src);
1025
1026static const struct snd_kcontrol_new rt5645_sto1_dmic_mux =
1027 SOC_DAPM_ENUM("Stereo1 DMIC source", rt5645_stereo1_dmic_enum);
1028
1029/* Mono ADC source */
1030/* MX-28 [12] */
1031static const char * const rt5645_mono_adc_l1_src[] = {
1032 "Mono DAC MIXL", "ADC"
1033};
1034
1035static SOC_ENUM_SINGLE_DECL(
1036 rt5645_mono_adc_l1_enum, RT5645_MONO_ADC_MIXER,
1037 RT5645_MONO_ADC_L1_SRC_SFT, rt5645_mono_adc_l1_src);
1038
1039static const struct snd_kcontrol_new rt5645_mono_adc_l1_mux =
1040 SOC_DAPM_ENUM("Mono ADC1 left source", rt5645_mono_adc_l1_enum);
1041/* MX-28 [11] */
1042static const char * const rt5645_mono_adc_l2_src[] = {
1043 "Mono DAC MIXL", "DMIC"
1044};
1045
1046static SOC_ENUM_SINGLE_DECL(
1047 rt5645_mono_adc_l2_enum, RT5645_MONO_ADC_MIXER,
1048 RT5645_MONO_ADC_L2_SRC_SFT, rt5645_mono_adc_l2_src);
1049
1050static const struct snd_kcontrol_new rt5645_mono_adc_l2_mux =
1051 SOC_DAPM_ENUM("Mono ADC2 left source", rt5645_mono_adc_l2_enum);
1052
1053/* MX-28 [8] */
1054static const char * const rt5645_mono_dmic_src[] = {
1055 "DMIC1", "DMIC2"
1056};
1057
1058static SOC_ENUM_SINGLE_DECL(
1059 rt5645_mono_dmic_l_enum, RT5645_MONO_ADC_MIXER,
1060 RT5645_MONO_DMIC_L_SRC_SFT, rt5645_mono_dmic_src);
1061
1062static const struct snd_kcontrol_new rt5645_mono_dmic_l_mux =
1063 SOC_DAPM_ENUM("Mono DMIC left source", rt5645_mono_dmic_l_enum);
1064/* MX-28 [1:0] */
1065static SOC_ENUM_SINGLE_DECL(
1066 rt5645_mono_dmic_r_enum, RT5645_MONO_ADC_MIXER,
1067 RT5645_MONO_DMIC_R_SRC_SFT, rt5645_mono_dmic_src);
1068
1069static const struct snd_kcontrol_new rt5645_mono_dmic_r_mux =
1070 SOC_DAPM_ENUM("Mono DMIC Right source", rt5645_mono_dmic_r_enum);
1071/* MX-28 [4] */
1072static const char * const rt5645_mono_adc_r1_src[] = {
1073 "Mono DAC MIXR", "ADC"
1074};
1075
1076static SOC_ENUM_SINGLE_DECL(
1077 rt5645_mono_adc_r1_enum, RT5645_MONO_ADC_MIXER,
1078 RT5645_MONO_ADC_R1_SRC_SFT, rt5645_mono_adc_r1_src);
1079
1080static const struct snd_kcontrol_new rt5645_mono_adc_r1_mux =
1081 SOC_DAPM_ENUM("Mono ADC1 right source", rt5645_mono_adc_r1_enum);
1082/* MX-28 [3] */
1083static const char * const rt5645_mono_adc_r2_src[] = {
1084 "Mono DAC MIXR", "DMIC"
1085};
1086
1087static SOC_ENUM_SINGLE_DECL(
1088 rt5645_mono_adc_r2_enum, RT5645_MONO_ADC_MIXER,
1089 RT5645_MONO_ADC_R2_SRC_SFT, rt5645_mono_adc_r2_src);
1090
1091static const struct snd_kcontrol_new rt5645_mono_adc_r2_mux =
1092 SOC_DAPM_ENUM("Mono ADC2 right source", rt5645_mono_adc_r2_enum);
1093
1094/* MX-77 [9:8] */
1095static const char * const rt5645_if1_adc_in_src[] = {
1096 "IF_ADC1", "IF_ADC2", "VAD_ADC"
1097};
1098
1099static SOC_ENUM_SINGLE_DECL(
1100 rt5645_if1_adc_in_enum, RT5645_TDM_CTRL_1,
1101 RT5645_IF1_ADC_IN_SFT, rt5645_if1_adc_in_src);
1102
1103static const struct snd_kcontrol_new rt5645_if1_adc_in_mux =
1104 SOC_DAPM_ENUM("IF1 ADC IN source", rt5645_if1_adc_in_enum);
1105
5c4ca99d
BL		 1106/* MX-2d [3] [2] */
1107static const char * const rt5650_a_dac1_src[] = {
1108 "DAC1", "Stereo DAC Mixer"
1109};
1110
1111static SOC_ENUM_SINGLE_DECL(
1112 rt5650_a_dac1_l_enum, RT5650_A_DAC_SOUR,
1113 RT5650_A_DAC1_L_IN_SFT, rt5650_a_dac1_src);
1114
1115static const struct snd_kcontrol_new rt5650_a_dac1_l_mux =
1116 SOC_DAPM_ENUM("A DAC1 L source", rt5650_a_dac1_l_enum);
1117
1118static SOC_ENUM_SINGLE_DECL(
1119 rt5650_a_dac1_r_enum, RT5650_A_DAC_SOUR,
1120 RT5650_A_DAC1_R_IN_SFT, rt5650_a_dac1_src);
1121
1122static const struct snd_kcontrol_new rt5650_a_dac1_r_mux =
1123 SOC_DAPM_ENUM("A DAC1 R source", rt5650_a_dac1_r_enum);
1124
1125/* MX-2d [1] [0] */
1126static const char * const rt5650_a_dac2_src[] = {
1127 "Stereo DAC Mixer", "Mono DAC Mixer"
1128};
1129
1130static SOC_ENUM_SINGLE_DECL(
1131 rt5650_a_dac2_l_enum, RT5650_A_DAC_SOUR,
1132 RT5650_A_DAC2_L_IN_SFT, rt5650_a_dac2_src);
1133
1134static const struct snd_kcontrol_new rt5650_a_dac2_l_mux =
1135 SOC_DAPM_ENUM("A DAC2 L source", rt5650_a_dac2_l_enum);
1136
1137static SOC_ENUM_SINGLE_DECL(
1138 rt5650_a_dac2_r_enum, RT5650_A_DAC_SOUR,
1139 RT5650_A_DAC2_R_IN_SFT, rt5650_a_dac2_src);
1140
1141static const struct snd_kcontrol_new rt5650_a_dac2_r_mux =
1142 SOC_DAPM_ENUM("A DAC2 R source", rt5650_a_dac2_r_enum);
1143
1319b2f6
OC		 1144/* MX-2F [13:12] */
1145static const char * const rt5645_if2_adc_in_src[] = {
1146 "IF_ADC1", "IF_ADC2", "VAD_ADC"
1147};
1148
1149static SOC_ENUM_SINGLE_DECL(
1150 rt5645_if2_adc_in_enum, RT5645_DIG_INF1_DATA,
1151 RT5645_IF2_ADC_IN_SFT, rt5645_if2_adc_in_src);
1152
1153static const struct snd_kcontrol_new rt5645_if2_adc_in_mux =
1154 SOC_DAPM_ENUM("IF2 ADC IN source", rt5645_if2_adc_in_enum);
1155
1156/* MX-2F [1:0] */
1157static const char * const rt5645_if3_adc_in_src[] = {
1158 "IF_ADC1", "IF_ADC2", "VAD_ADC"
1159};
1160
1161static SOC_ENUM_SINGLE_DECL(
1162 rt5645_if3_adc_in_enum, RT5645_DIG_INF1_DATA,
1163 RT5645_IF3_ADC_IN_SFT, rt5645_if3_adc_in_src);
1164
1165static const struct snd_kcontrol_new rt5645_if3_adc_in_mux =
1166 SOC_DAPM_ENUM("IF3 ADC IN source", rt5645_if3_adc_in_enum);
1167
1168/* MX-31 [15] [13] [11] [9] */
1169static const char * const rt5645_pdm_src[] = {
1170 "Mono DAC", "Stereo DAC"
1171};
1172
1173static SOC_ENUM_SINGLE_DECL(
1174 rt5645_pdm1_l_enum, RT5645_PDM_OUT_CTRL,
1175 RT5645_PDM1_L_SFT, rt5645_pdm_src);
1176
1177static const struct snd_kcontrol_new rt5645_pdm1_l_mux =
1178 SOC_DAPM_ENUM("PDM1 L source", rt5645_pdm1_l_enum);
1179
1180static SOC_ENUM_SINGLE_DECL(
1181 rt5645_pdm1_r_enum, RT5645_PDM_OUT_CTRL,
1182 RT5645_PDM1_R_SFT, rt5645_pdm_src);
1183
1184static const struct snd_kcontrol_new rt5645_pdm1_r_mux =
1185 SOC_DAPM_ENUM("PDM1 R source", rt5645_pdm1_r_enum);
1186
1187/* MX-9D [9:8] */
1188static const char * const rt5645_vad_adc_src[] = {
1189 "Sto1 ADC L", "Mono ADC L", "Mono ADC R"
1190};
1191
1192static SOC_ENUM_SINGLE_DECL(
1193 rt5645_vad_adc_enum, RT5645_VAD_CTRL4,
1194 RT5645_VAD_SEL_SFT, rt5645_vad_adc_src);
1195
1196static const struct snd_kcontrol_new rt5645_vad_adc_mux =
1197 SOC_DAPM_ENUM("VAD ADC source", rt5645_vad_adc_enum);
1198
1199static const struct snd_kcontrol_new spk_l_vol_control =
1200 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1201 RT5645_L_MUTE_SFT, 1, 1);
1202
1203static const struct snd_kcontrol_new spk_r_vol_control =
1204 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1205 RT5645_R_MUTE_SFT, 1, 1);
1206
1207static const struct snd_kcontrol_new hp_l_vol_control =
1208 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1209 RT5645_L_MUTE_SFT, 1, 1);
1210
1211static const struct snd_kcontrol_new hp_r_vol_control =
1212 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1213 RT5645_R_MUTE_SFT, 1, 1);
1214
1215static const struct snd_kcontrol_new pdm1_l_vol_control =
1216 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1217 RT5645_M_PDM1_L, 1, 1);
1218
1219static const struct snd_kcontrol_new pdm1_r_vol_control =
1220 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1221 RT5645_M_PDM1_R, 1, 1);
1222
1223static void hp_amp_power(struct snd_soc_codec *codec, int on)
1224{
1225 static int hp_amp_power_count;
1226 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1227
1228 if (on) {
1229 if (hp_amp_power_count <= 0) {
1230 /* depop parameters */
1231 snd_soc_update_bits(codec, RT5645_DEPOP_M2,
1232 RT5645_DEPOP_MASK, RT5645_DEPOP_MAN);
1233 snd_soc_write(codec, RT5645_DEPOP_M1, 0x000d);
1234 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1235 RT5645_HP_DCC_INT1, 0x9f01);
1236 mdelay(150);
1237 /* headphone amp power on */
1238 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1239 RT5645_PWR_FV1 | RT5645_PWR_FV2 , 0);
1240 snd_soc_update_bits(codec, RT5645_PWR_VOL,
1241 RT5645_PWR_HV_L | RT5645_PWR_HV_R,
1242 RT5645_PWR_HV_L | RT5645_PWR_HV_R);
1243 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1244 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1245 RT5645_PWR_HA,
1246 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1247 RT5645_PWR_HA);
1248 mdelay(5);
1249 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1250 RT5645_PWR_FV1 | RT5645_PWR_FV2,
1251 RT5645_PWR_FV1 | RT5645_PWR_FV2);
1252
1253 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1254 RT5645_HP_CO_MASK | RT5645_HP_SG_MASK,
1255 RT5645_HP_CO_EN | RT5645_HP_SG_EN);
1256 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1257 0x14, 0x1aaa);
1258 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1259 0x24, 0x0430);
1260 }
1261 hp_amp_power_count++;
1262 } else {
1263 hp_amp_power_count--;
1264 if (hp_amp_power_count <= 0) {
1265 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1266 RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK |
1267 RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS |
1268 RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS);
1269 /* headphone amp power down */
1270 snd_soc_write(codec, RT5645_DEPOP_M1, 0x0000);
1271 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1272 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1273 RT5645_PWR_HA, 0);
1274 }
1275 }
1276}
1277
1278static int rt5645_hp_event(struct snd_soc_dapm_widget *w,
1279 struct snd_kcontrol *kcontrol, int event)
1280{
c5f596cb 1281 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1319b2f6
OC		 1282 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1283
1284 switch (event) {
1285 case SND_SOC_DAPM_POST_PMU:
1286 hp_amp_power(codec, 1);
1287 /* headphone unmute sequence */
5c4ca99d
BL		 1288 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
1289 snd_soc_write(codec, RT5645_DEPOP_M3, 0x0737);
1290 } else {
1291 snd_soc_update_bits(codec, RT5645_DEPOP_M3,
1292 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1293 RT5645_CP_FQ3_MASK,
1294 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ1_SFT) |
1295 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1296 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ3_SFT));
1297 }
1319b2f6
OC		 1298 regmap_write(rt5645->regmap,
1299 RT5645_PR_BASE + RT5645_MAMP_INT_REG2, 0xfc00);
1300 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1301 RT5645_SMT_TRIG_MASK, RT5645_SMT_TRIG_EN);
1302 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1303 RT5645_RSTN_MASK, RT5645_RSTN_EN);
1304 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1305 RT5645_RSTN_MASK | RT5645_HP_L_SMT_MASK |
1306 RT5645_HP_R_SMT_MASK, RT5645_RSTN_DIS |
1307 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1308 msleep(40);
1309 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1310 RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK |
1311 RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS |
1312 RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS);
1313 break;
1314
1315 case SND_SOC_DAPM_PRE_PMD:
1316 /* headphone mute sequence */
5c4ca99d
BL		 1317 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
1318 snd_soc_write(codec, RT5645_DEPOP_M3, 0x0737);
1319 } else {
1320 snd_soc_update_bits(codec, RT5645_DEPOP_M3,
1321 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1322 RT5645_CP_FQ3_MASK,
1323 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ1_SFT) |
1324 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1325 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ3_SFT));
1326 }
1319b2f6
OC		 1327 regmap_write(rt5645->regmap,
1328 RT5645_PR_BASE + RT5645_MAMP_INT_REG2, 0xfc00);
1329 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1330 RT5645_HP_SG_MASK, RT5645_HP_SG_EN);
1331 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1332 RT5645_RSTP_MASK, RT5645_RSTP_EN);
1333 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1334 RT5645_RSTP_MASK | RT5645_HP_L_SMT_MASK |
1335 RT5645_HP_R_SMT_MASK, RT5645_RSTP_DIS |
1336 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1337 msleep(30);
1338 hp_amp_power(codec, 0);
1339 break;
1340
1341 default:
1342 return 0;
1343 }
1344
1345 return 0;
1346}
1347
1348static int rt5645_spk_event(struct snd_soc_dapm_widget *w,
1349 struct snd_kcontrol *kcontrol, int event)
1350{
c5f596cb 1351 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1319b2f6
OC		 1352
1353 switch (event) {
1354 case SND_SOC_DAPM_POST_PMU:
1355 snd_soc_update_bits(codec, RT5645_PWR_DIG1,
1356 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1357 RT5645_PWR_CLS_D_L,
1358 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1359 RT5645_PWR_CLS_D_L);
1360 break;
1361
1362 case SND_SOC_DAPM_PRE_PMD:
1363 snd_soc_update_bits(codec, RT5645_PWR_DIG1,
1364 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1365 RT5645_PWR_CLS_D_L, 0);
1366 break;
1367
1368 default:
1369 return 0;
1370 }
1371
1372 return 0;
1373}
1374
1375static int rt5645_lout_event(struct snd_soc_dapm_widget *w,
1376 struct snd_kcontrol *kcontrol, int event)
1377{
c5f596cb 1378 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1319b2f6
OC		 1379
1380 switch (event) {
1381 case SND_SOC_DAPM_POST_PMU:
1382 hp_amp_power(codec, 1);
1383 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1384 RT5645_PWR_LM, RT5645_PWR_LM);
1385 snd_soc_update_bits(codec, RT5645_LOUT1,
1386 RT5645_L_MUTE | RT5645_R_MUTE, 0);
1387 break;
1388
1389 case SND_SOC_DAPM_PRE_PMD:
1390 snd_soc_update_bits(codec, RT5645_LOUT1,
1391 RT5645_L_MUTE | RT5645_R_MUTE,
1392 RT5645_L_MUTE | RT5645_R_MUTE);
1393 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1394 RT5645_PWR_LM, 0);
1395 hp_amp_power(codec, 0);
1396 break;
1397
1398 default:
1399 return 0;
1400 }
1401
1402 return 0;
1403}
1404
1405static int rt5645_bst2_event(struct snd_soc_dapm_widget *w,
1406 struct snd_kcontrol *kcontrol, int event)
1407{
c5f596cb 1408 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1319b2f6
OC		 1409
1410 switch (event) {
1411 case SND_SOC_DAPM_POST_PMU:
1412 snd_soc_update_bits(codec, RT5645_PWR_ANLG2,
1413 RT5645_PWR_BST2_P, RT5645_PWR_BST2_P);
1414 break;
1415
1416 case SND_SOC_DAPM_PRE_PMD:
1417 snd_soc_update_bits(codec, RT5645_PWR_ANLG2,
1418 RT5645_PWR_BST2_P, 0);
1419 break;
1420
1421 default:
1422 return 0;
1423 }
1424
1425 return 0;
1426}
1427
1428static const struct snd_soc_dapm_widget rt5645_dapm_widgets[] = {
1429 SND_SOC_DAPM_SUPPLY("LDO2", RT5645_PWR_MIXER,
1430 RT5645_PWR_LDO2_BIT, 0, NULL, 0),
1431 SND_SOC_DAPM_SUPPLY("PLL1", RT5645_PWR_ANLG2,
1432 RT5645_PWR_PLL_BIT, 0, NULL, 0),
1433
1434 SND_SOC_DAPM_SUPPLY("JD Power", RT5645_PWR_ANLG2,
1435 RT5645_PWR_JD1_BIT, 0, NULL, 0),
1436 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5645_PWR_VOL,
1437 RT5645_PWR_MIC_DET_BIT, 0, NULL, 0),
1438
9e268353
BL		 1439 /* ASRC */
1440 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5645_ASRC_1,
1441 11, 0, NULL, 0),
1442 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5645_ASRC_1,
1443 12, 0, NULL, 0),
1444 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5645_ASRC_1,
1445 10, 0, NULL, 0),
1446 SND_SOC_DAPM_SUPPLY_S("DAC MONO L ASRC", 1, RT5645_ASRC_1,
1447 9, 0, NULL, 0),
1448 SND_SOC_DAPM_SUPPLY_S("DAC MONO R ASRC", 1, RT5645_ASRC_1,
1449 8, 0, NULL, 0),
1450 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5645_ASRC_1,
1451 7, 0, NULL, 0),
1452 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5645_ASRC_1,
1453 5, 0, NULL, 0),
1454 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5645_ASRC_1,
1455 4, 0, NULL, 0),
1456 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5645_ASRC_1,
1457 3, 0, NULL, 0),
1458 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5645_ASRC_1,
1459 1, 0, NULL, 0),
1460 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5645_ASRC_1,
1461 0, 0, NULL, 0),
1462
1319b2f6
OC		 1463 /* Input Side */
1464 /* micbias */
1465 SND_SOC_DAPM_MICBIAS("micbias1", RT5645_PWR_ANLG2,
1466 RT5645_PWR_MB1_BIT, 0),
1467 SND_SOC_DAPM_MICBIAS("micbias2", RT5645_PWR_ANLG2,
1468 RT5645_PWR_MB2_BIT, 0),
1469 /* Input Lines */
1470 SND_SOC_DAPM_INPUT("DMIC L1"),
1471 SND_SOC_DAPM_INPUT("DMIC R1"),
1472 SND_SOC_DAPM_INPUT("DMIC L2"),
1473 SND_SOC_DAPM_INPUT("DMIC R2"),
1474
1475 SND_SOC_DAPM_INPUT("IN1P"),
1476 SND_SOC_DAPM_INPUT("IN1N"),
1477 SND_SOC_DAPM_INPUT("IN2P"),
1478 SND_SOC_DAPM_INPUT("IN2N"),
1479
1480 SND_SOC_DAPM_INPUT("Haptic Generator"),
1481
1482 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1483 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1484 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1485 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1486 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5645_DMIC_CTRL1,
1487 RT5645_DMIC_1_EN_SFT, 0, NULL, 0),
1488 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5645_DMIC_CTRL1,
1489 RT5645_DMIC_2_EN_SFT, 0, NULL, 0),
1490 /* Boost */
1491 SND_SOC_DAPM_PGA("BST1", RT5645_PWR_ANLG2,
1492 RT5645_PWR_BST1_BIT, 0, NULL, 0),
1493 SND_SOC_DAPM_PGA_E("BST2", RT5645_PWR_ANLG2,
1494 RT5645_PWR_BST2_BIT, 0, NULL, 0, rt5645_bst2_event,
1495 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1496 /* Input Volume */
1497 SND_SOC_DAPM_PGA("INL VOL", RT5645_PWR_VOL,
1498 RT5645_PWR_IN_L_BIT, 0, NULL, 0),
1499 SND_SOC_DAPM_PGA("INR VOL", RT5645_PWR_VOL,
1500 RT5645_PWR_IN_R_BIT, 0, NULL, 0),
1501 /* REC Mixer */
1502 SND_SOC_DAPM_MIXER("RECMIXL", RT5645_PWR_MIXER, RT5645_PWR_RM_L_BIT,
1503 0, rt5645_rec_l_mix, ARRAY_SIZE(rt5645_rec_l_mix)),
1504 SND_SOC_DAPM_MIXER("RECMIXR", RT5645_PWR_MIXER, RT5645_PWR_RM_R_BIT,
1505 0, rt5645_rec_r_mix, ARRAY_SIZE(rt5645_rec_r_mix)),
1506 /* ADCs */
1507 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
1508 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
1509
1510 SND_SOC_DAPM_SUPPLY("ADC L power", RT5645_PWR_DIG1,
1511 RT5645_PWR_ADC_L_BIT, 0, NULL, 0),
1512 SND_SOC_DAPM_SUPPLY("ADC R power", RT5645_PWR_DIG1,
1513 RT5645_PWR_ADC_R_BIT, 0, NULL, 0),
1514
1515 /* ADC Mux */
1516 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
1517 &rt5645_sto1_dmic_mux),
1518 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1519 &rt5645_sto_adc2_mux),
1520 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1521 &rt5645_sto_adc2_mux),
1522 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1523 &rt5645_sto_adc1_mux),
1524 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1525 &rt5645_sto_adc1_mux),
1526 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
1527 &rt5645_mono_dmic_l_mux),
1528 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
1529 &rt5645_mono_dmic_r_mux),
1530 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1531 &rt5645_mono_adc_l2_mux),
1532 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1533 &rt5645_mono_adc_l1_mux),
1534 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1535 &rt5645_mono_adc_r1_mux),
1536 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1537 &rt5645_mono_adc_r2_mux),
1538 /* ADC Mixer */
1539
1540 SND_SOC_DAPM_SUPPLY_S("adc stereo1 filter", 1, RT5645_PWR_DIG2,
1541 RT5645_PWR_ADC_S1F_BIT, 0, NULL, 0),
1542 SND_SOC_DAPM_SUPPLY_S("adc stereo2 filter", 1, RT5645_PWR_DIG2,
1543 RT5645_PWR_ADC_S2F_BIT, 0, NULL, 0),
1544 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
1545 rt5645_sto1_adc_l_mix, ARRAY_SIZE(rt5645_sto1_adc_l_mix),
1546 NULL, 0),
1547 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
1548 rt5645_sto1_adc_r_mix, ARRAY_SIZE(rt5645_sto1_adc_r_mix),
1549 NULL, 0),
1550 SND_SOC_DAPM_SUPPLY_S("adc mono left filter", 1, RT5645_PWR_DIG2,
1551 RT5645_PWR_ADC_MF_L_BIT, 0, NULL, 0),
1552 SND_SOC_DAPM_MIXER_E("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
1553 rt5645_mono_adc_l_mix, ARRAY_SIZE(rt5645_mono_adc_l_mix),
1554 NULL, 0),
1555 SND_SOC_DAPM_SUPPLY_S("adc mono right filter", 1, RT5645_PWR_DIG2,
1556 RT5645_PWR_ADC_MF_R_BIT, 0, NULL, 0),
1557 SND_SOC_DAPM_MIXER_E("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
1558 rt5645_mono_adc_r_mix, ARRAY_SIZE(rt5645_mono_adc_r_mix),
1559 NULL, 0),
1560
1561 /* ADC PGA */
1562 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1563 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1564 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1565 SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1566 SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1567 SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1568 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1569 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1570 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1571 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1572
1573 /* IF1 2 Mux */
1574 SND_SOC_DAPM_MUX("IF1 ADC Mux", SND_SOC_NOPM,
1575 0, 0, &rt5645_if1_adc_in_mux),
1576 SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM,
1577 0, 0, &rt5645_if2_adc_in_mux),
1578
1579 /* Digital Interface */
1580 SND_SOC_DAPM_SUPPLY("I2S1", RT5645_PWR_DIG1,
1581 RT5645_PWR_I2S1_BIT, 0, NULL, 0),
1582 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1583 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1584 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1585 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1586 SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1587 SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1588 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1589 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1590 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1591 SND_SOC_DAPM_SUPPLY("I2S2", RT5645_PWR_DIG1,
1592 RT5645_PWR_I2S2_BIT, 0, NULL, 0),
1593 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1594 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1595 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1596 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1597
1598 /* Digital Interface Select */
1599 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM,
1600 0, 0, &rt5645_vad_adc_mux),
1601
1602 /* Audio Interface */
1603 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1604 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1605 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1606 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1607
1608 /* Output Side */
1609 /* DAC mixer before sound effect */
1610 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1611 rt5645_dac_l_mix, ARRAY_SIZE(rt5645_dac_l_mix)),
1612 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1613 rt5645_dac_r_mix, ARRAY_SIZE(rt5645_dac_r_mix)),
1614
1615 /* DAC2 channel Mux */
1616 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_l2_mux),
1617 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_r2_mux),
1618 SND_SOC_DAPM_PGA("DAC L2 Volume", RT5645_PWR_DIG1,
1619 RT5645_PWR_DAC_L2_BIT, 0, NULL, 0),
1620 SND_SOC_DAPM_PGA("DAC R2 Volume", RT5645_PWR_DIG1,
1621 RT5645_PWR_DAC_R2_BIT, 0, NULL, 0),
1622
1623 SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1l_mux),
1624 SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1r_mux),
1625
1626 /* DAC Mixer */
1627 SND_SOC_DAPM_SUPPLY_S("dac stereo1 filter", 1, RT5645_PWR_DIG2,
1628 RT5645_PWR_DAC_S1F_BIT, 0, NULL, 0),
1629 SND_SOC_DAPM_SUPPLY_S("dac mono left filter", 1, RT5645_PWR_DIG2,
1630 RT5645_PWR_DAC_MF_L_BIT, 0, NULL, 0),
1631 SND_SOC_DAPM_SUPPLY_S("dac mono right filter", 1, RT5645_PWR_DIG2,
1632 RT5645_PWR_DAC_MF_R_BIT, 0, NULL, 0),
1633 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
1634 rt5645_sto_dac_l_mix, ARRAY_SIZE(rt5645_sto_dac_l_mix)),
1635 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
1636 rt5645_sto_dac_r_mix, ARRAY_SIZE(rt5645_sto_dac_r_mix)),
1637 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
1638 rt5645_mono_dac_l_mix, ARRAY_SIZE(rt5645_mono_dac_l_mix)),
1639 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
1640 rt5645_mono_dac_r_mix, ARRAY_SIZE(rt5645_mono_dac_r_mix)),
1641 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
1642 rt5645_dig_l_mix, ARRAY_SIZE(rt5645_dig_l_mix)),
1643 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
1644 rt5645_dig_r_mix, ARRAY_SIZE(rt5645_dig_r_mix)),
1645
1646 /* DACs */
1647 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L1_BIT,
1648 0),
1649 SND_SOC_DAPM_DAC("DAC L2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L2_BIT,
1650 0),
1651 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R1_BIT,
1652 0),
1653 SND_SOC_DAPM_DAC("DAC R2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R2_BIT,
1654 0),
1655 /* OUT Mixer */
1656 SND_SOC_DAPM_MIXER("SPK MIXL", RT5645_PWR_MIXER, RT5645_PWR_SM_L_BIT,
1657 0, rt5645_spk_l_mix, ARRAY_SIZE(rt5645_spk_l_mix)),
1658 SND_SOC_DAPM_MIXER("SPK MIXR", RT5645_PWR_MIXER, RT5645_PWR_SM_R_BIT,
1659 0, rt5645_spk_r_mix, ARRAY_SIZE(rt5645_spk_r_mix)),
1660 SND_SOC_DAPM_MIXER("OUT MIXL", RT5645_PWR_MIXER, RT5645_PWR_OM_L_BIT,
1661 0, rt5645_out_l_mix, ARRAY_SIZE(rt5645_out_l_mix)),
1662 SND_SOC_DAPM_MIXER("OUT MIXR", RT5645_PWR_MIXER, RT5645_PWR_OM_R_BIT,
1663 0, rt5645_out_r_mix, ARRAY_SIZE(rt5645_out_r_mix)),
1664 /* Ouput Volume */
1665 SND_SOC_DAPM_SWITCH("SPKVOL L", RT5645_PWR_VOL, RT5645_PWR_SV_L_BIT, 0,
1666 &spk_l_vol_control),
1667 SND_SOC_DAPM_SWITCH("SPKVOL R", RT5645_PWR_VOL, RT5645_PWR_SV_R_BIT, 0,
1668 &spk_r_vol_control),
1669 SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5645_PWR_VOL, RT5645_PWR_HV_L_BIT,
1670 0, rt5645_hpvoll_mix, ARRAY_SIZE(rt5645_hpvoll_mix)),
1671 SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5645_PWR_VOL, RT5645_PWR_HV_R_BIT,
1672 0, rt5645_hpvolr_mix, ARRAY_SIZE(rt5645_hpvolr_mix)),
1673 SND_SOC_DAPM_SUPPLY("HPOVOL MIXL Power", RT5645_PWR_MIXER,
1674 RT5645_PWR_HM_L_BIT, 0, NULL, 0),
1675 SND_SOC_DAPM_SUPPLY("HPOVOL MIXR Power", RT5645_PWR_MIXER,
1676 RT5645_PWR_HM_R_BIT, 0, NULL, 0),
1677 SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 0, 0, NULL, 0),
1678 SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM, 0, 0, NULL, 0),
1679 SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM, 0, 0, NULL, 0),
1680 SND_SOC_DAPM_SWITCH("HPOVOL L", SND_SOC_NOPM, 0, 0, &hp_l_vol_control),
1681 SND_SOC_DAPM_SWITCH("HPOVOL R", SND_SOC_NOPM, 0, 0, &hp_r_vol_control),
1682
1683 /* HPO/LOUT/Mono Mixer */
1684 SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_l_mix,
1685 ARRAY_SIZE(rt5645_spo_l_mix)),
1686 SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_r_mix,
1687 ARRAY_SIZE(rt5645_spo_r_mix)),
1688 SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0, rt5645_hpo_mix,
1689 ARRAY_SIZE(rt5645_hpo_mix)),
1690 SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0, rt5645_lout_mix,
1691 ARRAY_SIZE(rt5645_lout_mix)),
1692
1693 SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0, rt5645_hp_event,
1694 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1695 SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0, rt5645_lout_event,
1696 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1697 SND_SOC_DAPM_PGA_S("SPK amp", 2, SND_SOC_NOPM, 0, 0, rt5645_spk_event,
1698 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1699
1700 /* PDM */
1701 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5645_PWR_DIG2, RT5645_PWR_PDM1_BIT,
1702 0, NULL, 0),
1703 SND_SOC_DAPM_MUX("PDM1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_l_mux),
1704 SND_SOC_DAPM_MUX("PDM1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_r_mux),
1705
1706 SND_SOC_DAPM_SWITCH("PDM1 L", SND_SOC_NOPM, 0, 0, &pdm1_l_vol_control),
1707 SND_SOC_DAPM_SWITCH("PDM1 R", SND_SOC_NOPM, 0, 0, &pdm1_r_vol_control),
1708
1709 /* Output Lines */
1710 SND_SOC_DAPM_OUTPUT("HPOL"),
1711 SND_SOC_DAPM_OUTPUT("HPOR"),
1712 SND_SOC_DAPM_OUTPUT("LOUTL"),
1713 SND_SOC_DAPM_OUTPUT("LOUTR"),
1714 SND_SOC_DAPM_OUTPUT("PDM1L"),
1715 SND_SOC_DAPM_OUTPUT("PDM1R"),
1716 SND_SOC_DAPM_OUTPUT("SPOL"),
1717 SND_SOC_DAPM_OUTPUT("SPOR"),
1718};
1719
5c4ca99d
BL		 1720static const struct snd_soc_dapm_widget rt5650_specific_dapm_widgets[] = {
1721 SND_SOC_DAPM_MUX("A DAC1 L Mux", SND_SOC_NOPM,
1722 0, 0, &rt5650_a_dac1_l_mux),
1723 SND_SOC_DAPM_MUX("A DAC1 R Mux", SND_SOC_NOPM,
1724 0, 0, &rt5650_a_dac1_r_mux),
1725 SND_SOC_DAPM_MUX("A DAC2 L Mux", SND_SOC_NOPM,
1726 0, 0, &rt5650_a_dac2_l_mux),
1727 SND_SOC_DAPM_MUX("A DAC2 R Mux", SND_SOC_NOPM,
1728 0, 0, &rt5650_a_dac2_r_mux),
1729};
1730
1319b2f6 1731static const struct snd_soc_dapm_route rt5645_dapm_routes[] = {
9e268353
BL		 1732 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
1733 { "adc stereo2 filter", NULL, "ADC STO2 ASRC", is_using_asrc },
1734 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
1735 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
1736 { "dac mono left filter", NULL, "DAC MONO L ASRC", is_using_asrc },
1737 { "dac mono right filter", NULL, "DAC MONO R ASRC", is_using_asrc },
1738 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
1739
1740 { "I2S1", NULL, "I2S1 ASRC" },
1741 { "I2S2", NULL, "I2S2 ASRC" },
1742
1319b2f6
OC		 1743 { "IN1P", NULL, "LDO2" },
1744 { "IN2P", NULL, "LDO2" },
1745
1746 { "DMIC1", NULL, "DMIC L1" },
1747 { "DMIC1", NULL, "DMIC R1" },
1748 { "DMIC2", NULL, "DMIC L2" },
1749 { "DMIC2", NULL, "DMIC R2" },
1750
1751 { "BST1", NULL, "IN1P" },
1752 { "BST1", NULL, "IN1N" },
1753 { "BST1", NULL, "JD Power" },
1754 { "BST1", NULL, "Mic Det Power" },
1755 { "BST2", NULL, "IN2P" },
1756 { "BST2", NULL, "IN2N" },
1757
1758 { "INL VOL", NULL, "IN2P" },
1759 { "INR VOL", NULL, "IN2N" },
1760
1761 { "RECMIXL", "HPOL Switch", "HPOL" },
1762 { "RECMIXL", "INL Switch", "INL VOL" },
1763 { "RECMIXL", "BST2 Switch", "BST2" },
1764 { "RECMIXL", "BST1 Switch", "BST1" },
1765 { "RECMIXL", "OUT MIXL Switch", "OUT MIXL" },
1766
1767 { "RECMIXR", "HPOR Switch", "HPOR" },
1768 { "RECMIXR", "INR Switch", "INR VOL" },
1769 { "RECMIXR", "BST2 Switch", "BST2" },
1770 { "RECMIXR", "BST1 Switch", "BST1" },
1771 { "RECMIXR", "OUT MIXR Switch", "OUT MIXR" },
1772
1773 { "ADC L", NULL, "RECMIXL" },
1774 { "ADC L", NULL, "ADC L power" },
1775 { "ADC R", NULL, "RECMIXR" },
1776 { "ADC R", NULL, "ADC R power" },
1777
1778 {"DMIC L1", NULL, "DMIC CLK"},
1779 {"DMIC L1", NULL, "DMIC1 Power"},
1780 {"DMIC R1", NULL, "DMIC CLK"},
1781 {"DMIC R1", NULL, "DMIC1 Power"},
1782 {"DMIC L2", NULL, "DMIC CLK"},
1783 {"DMIC L2", NULL, "DMIC2 Power"},
1784 {"DMIC R2", NULL, "DMIC CLK"},
1785 {"DMIC R2", NULL, "DMIC2 Power"},
1786
1787 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
1788 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
9e268353 1789 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC" },
1319b2f6
OC		 1790
1791 { "Mono DMIC L Mux", "DMIC1", "DMIC L1" },
1792 { "Mono DMIC L Mux", "DMIC2", "DMIC L2" },
9e268353 1793 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC" },
1319b2f6
OC		 1794
1795 { "Mono DMIC R Mux", "DMIC1", "DMIC R1" },
1796 { "Mono DMIC R Mux", "DMIC2", "DMIC R2" },
9e268353 1797 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC" },
1319b2f6
OC		 1798
1799 { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" },
1800 { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
1801 { "Stereo1 ADC L1 Mux", "ADC", "ADC L" },
1802 { "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
1803
1804 { "Stereo1 ADC R1 Mux", "ADC", "ADC R" },
1805 { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
1806 { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" },
1807 { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
1808
1809 { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },
1810 { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
1811 { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
1812 { "Mono ADC L1 Mux", "ADC", "ADC L" },
1813
1814 { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
1815 { "Mono ADC R1 Mux", "ADC", "ADC R" },
1816 { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },
1817 { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
1818
1819 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" },
1820 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" },
1821 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" },
1822 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" },
1823
1824 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
1825 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
1826 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
1827
1828 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
1829 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
1830 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
1831
1832 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" },
1833 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },
1834 { "Mono ADC MIXL", NULL, "adc mono left filter" },
1835 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
1836
1837 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },
1838 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },
1839 { "Mono ADC MIXR", NULL, "adc mono right filter" },
1840 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
1841
1842 { "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" },
1843 { "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" },
1844 { "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" },
1845
1846 { "IF_ADC1", NULL, "Stereo1 ADC MIXL" },
1847 { "IF_ADC1", NULL, "Stereo1 ADC MIXR" },
1848 { "IF_ADC2", NULL, "Mono ADC MIXL" },
1849 { "IF_ADC2", NULL, "Mono ADC MIXR" },
1850 { "VAD_ADC", NULL, "VAD ADC Mux" },
1851
1852 { "IF1 ADC Mux", "IF_ADC1", "IF_ADC1" },
1853 { "IF1 ADC Mux", "IF_ADC2", "IF_ADC2" },
1854 { "IF1 ADC Mux", "VAD_ADC", "VAD_ADC" },
1855
1856 { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" },
1857 { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" },
1858 { "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" },
1859
1860 { "IF1 ADC", NULL, "I2S1" },
1861 { "IF1 ADC", NULL, "IF1 ADC Mux" },
1862 { "IF2 ADC", NULL, "I2S2" },
1863 { "IF2 ADC", NULL, "IF2 ADC Mux" },
1864
1865 { "AIF1TX", NULL, "IF1 ADC" },
1866 { "AIF1TX", NULL, "IF2 ADC" },
1867 { "AIF2TX", NULL, "IF2 ADC" },
1868
1869 { "IF1 DAC1", NULL, "AIF1RX" },
1870 { "IF1 DAC2", NULL, "AIF1RX" },
1871 { "IF2 DAC", NULL, "AIF2RX" },
1872
1873 { "IF1 DAC1", NULL, "I2S1" },
1874 { "IF1 DAC2", NULL, "I2S1" },
1875 { "IF2 DAC", NULL, "I2S2" },
1876
1877 { "IF1 DAC2 L", NULL, "IF1 DAC2" },
1878 { "IF1 DAC2 R", NULL, "IF1 DAC2" },
1879 { "IF1 DAC1 L", NULL, "IF1 DAC1" },
1880 { "IF1 DAC1 R", NULL, "IF1 DAC1" },
1881 { "IF2 DAC L", NULL, "IF2 DAC" },
1882 { "IF2 DAC R", NULL, "IF2 DAC" },
1883
1884 { "DAC1 L Mux", "IF1 DAC", "IF1 DAC1 L" },
1885 { "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" },
1886
1887 { "DAC1 R Mux", "IF1 DAC", "IF1 DAC1 R" },
1888 { "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" },
1889
1890 { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" },
1891 { "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" },
1892 { "DAC1 MIXL", NULL, "dac stereo1 filter" },
1893 { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" },
1894 { "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" },
1895 { "DAC1 MIXR", NULL, "dac stereo1 filter" },
1896
1897 { "DAC L2 Mux", "IF1 DAC", "IF1 DAC2 L" },
1898 { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },
1899 { "DAC L2 Mux", "Mono ADC", "Mono ADC MIXL" },
1900 { "DAC L2 Mux", "VAD_ADC", "VAD_ADC" },
1901 { "DAC L2 Volume", NULL, "DAC L2 Mux" },
1902 { "DAC L2 Volume", NULL, "dac mono left filter" },
1903
1904 { "DAC R2 Mux", "IF1 DAC", "IF1 DAC2 R" },
1905 { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },
1906 { "DAC R2 Mux", "Mono ADC", "Mono ADC MIXR" },
1907 { "DAC R2 Mux", "Haptic", "Haptic Generator" },
1908 { "DAC R2 Volume", NULL, "DAC R2 Mux" },
1909 { "DAC R2 Volume", NULL, "dac mono right filter" },
1910
1911 { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
1912 { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
1913 { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
1914 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
1915 { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
1916 { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
1917 { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
1918 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
1919
1920 { "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
1921 { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
1922 { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
1923 { "Mono DAC MIXL", NULL, "dac mono left filter" },
1924 { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
1925 { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
1926 { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
1927 { "Mono DAC MIXR", NULL, "dac mono right filter" },
1928
1929 { "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
1930 { "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
1931 { "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
1932 { "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
1933 { "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
1934 { "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
1935
1319b2f6 1936 { "DAC L1", NULL, "PLL1", is_sys_clk_from_pll },
1319b2f6 1937 { "DAC R1", NULL, "PLL1", is_sys_clk_from_pll },
1319b2f6 1938 { "DAC L2", NULL, "PLL1", is_sys_clk_from_pll },
1319b2f6
OC		 1939 { "DAC R2", NULL, "PLL1", is_sys_clk_from_pll },
1940
1941 { "SPK MIXL", "BST1 Switch", "BST1" },
1942 { "SPK MIXL", "INL Switch", "INL VOL" },
1943 { "SPK MIXL", "DAC L1 Switch", "DAC L1" },
1944 { "SPK MIXL", "DAC L2 Switch", "DAC L2" },
1945 { "SPK MIXR", "BST2 Switch", "BST2" },
1946 { "SPK MIXR", "INR Switch", "INR VOL" },
1947 { "SPK MIXR", "DAC R1 Switch", "DAC R1" },
1948 { "SPK MIXR", "DAC R2 Switch", "DAC R2" },
1949
1950 { "OUT MIXL", "BST1 Switch", "BST1" },
1951 { "OUT MIXL", "INL Switch", "INL VOL" },
1952 { "OUT MIXL", "DAC L2 Switch", "DAC L2" },
1953 { "OUT MIXL", "DAC L1 Switch", "DAC L1" },
1954
1955 { "OUT MIXR", "BST2 Switch", "BST2" },
1956 { "OUT MIXR", "INR Switch", "INR VOL" },
1957 { "OUT MIXR", "DAC R2 Switch", "DAC R2" },
1958 { "OUT MIXR", "DAC R1 Switch", "DAC R1" },
1959
1960 { "HPOVOL MIXL", "DAC1 Switch", "DAC L1" },
1961 { "HPOVOL MIXL", "DAC2 Switch", "DAC L2" },
1962 { "HPOVOL MIXL", "INL Switch", "INL VOL" },
1963 { "HPOVOL MIXL", "BST1 Switch", "BST1" },
1964 { "HPOVOL MIXL", NULL, "HPOVOL MIXL Power" },
1965 { "HPOVOL MIXR", "DAC1 Switch", "DAC R1" },
1966 { "HPOVOL MIXR", "DAC2 Switch", "DAC R2" },
1967 { "HPOVOL MIXR", "INR Switch", "INR VOL" },
1968 { "HPOVOL MIXR", "BST2 Switch", "BST2" },
1969 { "HPOVOL MIXR", NULL, "HPOVOL MIXR Power" },
1970
1971 { "DAC 2", NULL, "DAC L2" },
1972 { "DAC 2", NULL, "DAC R2" },
1973 { "DAC 1", NULL, "DAC L1" },
1974 { "DAC 1", NULL, "DAC R1" },
1975 { "HPOVOL L", "Switch", "HPOVOL MIXL" },
1976 { "HPOVOL R", "Switch", "HPOVOL MIXR" },
1977 { "HPOVOL", NULL, "HPOVOL L" },
1978 { "HPOVOL", NULL, "HPOVOL R" },
1979 { "HPO MIX", "DAC1 Switch", "DAC 1" },
1980 { "HPO MIX", "HPVOL Switch", "HPOVOL" },
1981
1982 { "SPKVOL L", "Switch", "SPK MIXL" },
1983 { "SPKVOL R", "Switch", "SPK MIXR" },
1984
1985 { "SPOL MIX", "DAC R1 Switch", "DAC R1" },
1986 { "SPOL MIX", "DAC L1 Switch", "DAC L1" },
1987 { "SPOL MIX", "SPKVOL R Switch", "SPKVOL R" },
1988 { "SPOL MIX", "SPKVOL L Switch", "SPKVOL L" },
1989 { "SPOR MIX", "DAC R1 Switch", "DAC R1" },
1990 { "SPOR MIX", "SPKVOL R Switch", "SPKVOL R" },
1991
1992 { "LOUT MIX", "DAC L1 Switch", "DAC L1" },
1993 { "LOUT MIX", "DAC R1 Switch", "DAC R1" },
1994 { "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" },
1995 { "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" },
1996
1997 { "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" },
1998 { "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" },
1999 { "PDM1 L Mux", NULL, "PDM1 Power" },
2000 { "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" },
2001 { "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" },
2002 { "PDM1 R Mux", NULL, "PDM1 Power" },
2003
2004 { "HP amp", NULL, "HPO MIX" },
2005 { "HP amp", NULL, "JD Power" },
2006 { "HP amp", NULL, "Mic Det Power" },
2007 { "HP amp", NULL, "LDO2" },
2008 { "HPOL", NULL, "HP amp" },
2009 { "HPOR", NULL, "HP amp" },
2010
2011 { "LOUT amp", NULL, "LOUT MIX" },
2012 { "LOUTL", NULL, "LOUT amp" },
2013 { "LOUTR", NULL, "LOUT amp" },
2014
2015 { "PDM1 L", "Switch", "PDM1 L Mux" },
2016 { "PDM1 R", "Switch", "PDM1 R Mux" },
2017
2018 { "PDM1L", NULL, "PDM1 L" },
2019 { "PDM1R", NULL, "PDM1 R" },
2020
2021 { "SPK amp", NULL, "SPOL MIX" },
2022 { "SPK amp", NULL, "SPOR MIX" },
2023 { "SPOL", NULL, "SPK amp" },
2024 { "SPOR", NULL, "SPK amp" },
2025};
2026
5c4ca99d
BL		 2027static const struct snd_soc_dapm_route rt5650_specific_dapm_routes[] = {
2028 { "A DAC1 L Mux", "DAC1", "DAC1 MIXL"},
2029 { "A DAC1 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
2030 { "A DAC1 R Mux", "DAC1", "DAC1 MIXR"},
2031 { "A DAC1 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
2032
2033 { "A DAC2 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
2034 { "A DAC2 L Mux", "Mono DAC Mixer", "Mono DAC MIXL"},
2035 { "A DAC2 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
2036 { "A DAC2 R Mux", "Mono DAC Mixer", "Mono DAC MIXR"},
2037
2038 { "DAC L1", NULL, "A DAC1 L Mux" },
2039 { "DAC R1", NULL, "A DAC1 R Mux" },
2040 { "DAC L2", NULL, "A DAC2 L Mux" },
2041 { "DAC R2", NULL, "A DAC2 R Mux" },
2042};
2043
2044static const struct snd_soc_dapm_route rt5645_specific_dapm_routes[] = {
2045 { "DAC L1", NULL, "Stereo DAC MIXL" },
2046 { "DAC R1", NULL, "Stereo DAC MIXR" },
2047 { "DAC L2", NULL, "Mono DAC MIXL" },
2048 { "DAC R2", NULL, "Mono DAC MIXR" },
2049};
2050
1319b2f6
OC		 2051static int rt5645_hw_params(struct snd_pcm_substream *substream,
2052 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2053{
2054 struct snd_soc_codec *codec = dai->codec;
2055 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2056 unsigned int val_len = 0, val_clk, mask_clk;
2057 int pre_div, bclk_ms, frame_size;
2058
2059 rt5645->lrck[dai->id] = params_rate(params);
d92950e7 2060 pre_div = rl6231_get_clk_info(rt5645->sysclk, rt5645->lrck[dai->id]);
1319b2f6
OC		 2061 if (pre_div < 0) {
2062 dev_err(codec->dev, "Unsupported clock setting\n");
2063 return -EINVAL;
2064 }
2065 frame_size = snd_soc_params_to_frame_size(params);
2066 if (frame_size < 0) {
2067 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
2068 return -EINVAL;
2069 }
2070 bclk_ms = frame_size > 32;
2071 rt5645->bclk[dai->id] = rt5645->lrck[dai->id] * (32 << bclk_ms);
2072
2073 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
2074 rt5645->bclk[dai->id], rt5645->lrck[dai->id]);
2075 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
2076 bclk_ms, pre_div, dai->id);
2077
2078 switch (params_width(params)) {
2079 case 16:
2080 break;
2081 case 20:
2082 val_len |= RT5645_I2S_DL_20;
2083 break;
2084 case 24:
2085 val_len |= RT5645_I2S_DL_24;
2086 break;
2087 case 8:
2088 val_len |= RT5645_I2S_DL_8;
2089 break;
2090 default:
2091 return -EINVAL;
2092 }
2093
2094 switch (dai->id) {
2095 case RT5645_AIF1:
2096 mask_clk = RT5645_I2S_BCLK_MS1_MASK | RT5645_I2S_PD1_MASK;
2097 val_clk = bclk_ms << RT5645_I2S_BCLK_MS1_SFT |
2098 pre_div << RT5645_I2S_PD1_SFT;
2099 snd_soc_update_bits(codec, RT5645_I2S1_SDP,
2100 RT5645_I2S_DL_MASK, val_len);
2101 snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk);
2102 break;
2103 case RT5645_AIF2:
2104 mask_clk = RT5645_I2S_BCLK_MS2_MASK | RT5645_I2S_PD2_MASK;
2105 val_clk = bclk_ms << RT5645_I2S_BCLK_MS2_SFT |
2106 pre_div << RT5645_I2S_PD2_SFT;
2107 snd_soc_update_bits(codec, RT5645_I2S2_SDP,
2108 RT5645_I2S_DL_MASK, val_len);
2109 snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk);
2110 break;
2111 default:
2112 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2113 return -EINVAL;
2114 }
2115
2116 return 0;
2117}
2118
2119static int rt5645_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2120{
2121 struct snd_soc_codec *codec = dai->codec;
2122 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2123 unsigned int reg_val = 0;
2124
2125 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2126 case SND_SOC_DAIFMT_CBM_CFM:
2127 rt5645->master[dai->id] = 1;
2128 break;
2129 case SND_SOC_DAIFMT_CBS_CFS:
2130 reg_val |= RT5645_I2S_MS_S;
2131 rt5645->master[dai->id] = 0;
2132 break;
2133 default:
2134 return -EINVAL;
2135 }
2136
2137 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2138 case SND_SOC_DAIFMT_NB_NF:
2139 break;
2140 case SND_SOC_DAIFMT_IB_NF:
2141 reg_val |= RT5645_I2S_BP_INV;
2142 break;
2143 default:
2144 return -EINVAL;
2145 }
2146
2147 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2148 case SND_SOC_DAIFMT_I2S:
2149 break;
2150 case SND_SOC_DAIFMT_LEFT_J:
2151 reg_val |= RT5645_I2S_DF_LEFT;
2152 break;
2153 case SND_SOC_DAIFMT_DSP_A:
2154 reg_val |= RT5645_I2S_DF_PCM_A;
2155 break;
2156 case SND_SOC_DAIFMT_DSP_B:
2157 reg_val |= RT5645_I2S_DF_PCM_B;
2158 break;
2159 default:
2160 return -EINVAL;
2161 }
2162 switch (dai->id) {
2163 case RT5645_AIF1:
2164 snd_soc_update_bits(codec, RT5645_I2S1_SDP,
2165 RT5645_I2S_MS_MASK | RT5645_I2S_BP_MASK |
2166 RT5645_I2S_DF_MASK, reg_val);
2167 break;
8c325704
AL		 2168 case RT5645_AIF2:
2169 snd_soc_update_bits(codec, RT5645_I2S2_SDP,
1319b2f6
OC		 2170 RT5645_I2S_MS_MASK | RT5645_I2S_BP_MASK |
2171 RT5645_I2S_DF_MASK, reg_val);
2172 break;
2173 default:
2174 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2175 return -EINVAL;
2176 }
2177 return 0;
2178}
2179
2180static int rt5645_set_dai_sysclk(struct snd_soc_dai *dai,
2181 int clk_id, unsigned int freq, int dir)
2182{
2183 struct snd_soc_codec *codec = dai->codec;
2184 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2185 unsigned int reg_val = 0;
2186
2187 if (freq == rt5645->sysclk && clk_id == rt5645->sysclk_src)
2188 return 0;
2189
2190 switch (clk_id) {
2191 case RT5645_SCLK_S_MCLK:
2192 reg_val |= RT5645_SCLK_SRC_MCLK;
2193 break;
2194 case RT5645_SCLK_S_PLL1:
2195 reg_val |= RT5645_SCLK_SRC_PLL1;
2196 break;
2197 case RT5645_SCLK_S_RCCLK:
2198 reg_val |= RT5645_SCLK_SRC_RCCLK;
2199 break;
2200 default:
2201 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
2202 return -EINVAL;
2203 }
2204 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2205 RT5645_SCLK_SRC_MASK, reg_val);
2206 rt5645->sysclk = freq;
2207 rt5645->sysclk_src = clk_id;
2208
2209 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
2210
2211 return 0;
2212}
2213
1319b2f6
OC		 2214static int rt5645_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2215 unsigned int freq_in, unsigned int freq_out)
2216{
2217 struct snd_soc_codec *codec = dai->codec;
2218 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
71c7a2d6 2219 struct rl6231_pll_code pll_code;
1319b2f6
OC		 2220 int ret;
2221
2222 if (source == rt5645->pll_src && freq_in == rt5645->pll_in &&
2223 freq_out == rt5645->pll_out)
2224 return 0;
2225
2226 if (!freq_in || !freq_out) {
2227 dev_dbg(codec->dev, "PLL disabled\n");
2228
2229 rt5645->pll_in = 0;
2230 rt5645->pll_out = 0;
2231 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2232 RT5645_SCLK_SRC_MASK, RT5645_SCLK_SRC_MCLK);
2233 return 0;
2234 }
2235
2236 switch (source) {
2237 case RT5645_PLL1_S_MCLK:
2238 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2239 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_MCLK);
2240 break;
2241 case RT5645_PLL1_S_BCLK1:
2242 case RT5645_PLL1_S_BCLK2:
2243 switch (dai->id) {
2244 case RT5645_AIF1:
2245 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2246 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK1);
2247 break;
2248 case RT5645_AIF2:
2249 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2250 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK2);
2251 break;
2252 default:
2253 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2254 return -EINVAL;
2255 }
2256 break;
2257 default:
2258 dev_err(codec->dev, "Unknown PLL source %d\n", source);
2259 return -EINVAL;
2260 }
2261
71c7a2d6 2262 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
1319b2f6
OC		 2263 if (ret < 0) {
2264 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
2265 return ret;
2266 }
2267
2268 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
2269 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2270 pll_code.n_code, pll_code.k_code);
2271
2272 snd_soc_write(codec, RT5645_PLL_CTRL1,
2273 pll_code.n_code << RT5645_PLL_N_SFT | pll_code.k_code);
2274 snd_soc_write(codec, RT5645_PLL_CTRL2,
2275 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5645_PLL_M_SFT |
2276 pll_code.m_bp << RT5645_PLL_M_BP_SFT);
2277
2278 rt5645->pll_in = freq_in;
2279 rt5645->pll_out = freq_out;
2280 rt5645->pll_src = source;
2281
2282 return 0;
2283}
2284
2285static int rt5645_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2286 unsigned int rx_mask, int slots, int slot_width)
2287{
2288 struct snd_soc_codec *codec = dai->codec;
2289 unsigned int val = 0;
2290
850577db 2291 if (rx_mask || tx_mask) {
1319b2f6 2292 val |= (1 << 14);
850577db
BL		 2293 snd_soc_update_bits(codec, RT5645_BASS_BACK,
2294 RT5645_G_BB_BST_MASK, RT5645_G_BB_BST_25DB);
2295 }
1319b2f6
OC		 2296
2297 switch (slots) {
2298 case 4:
2299 val |= (1 << 12);
2300 break;
2301 case 6:
2302 val |= (2 << 12);
2303 break;
2304 case 8:
2305 val |= (3 << 12);
2306 break;
2307 case 2:
2308 default:
2309 break;
2310 }
2311
2312 switch (slot_width) {
2313 case 20:
2314 val |= (1 << 10);
2315 break;
2316 case 24:
2317 val |= (2 << 10);
2318 break;
2319 case 32:
2320 val |= (3 << 10);
2321 break;
2322 case 16:
2323 default:
2324 break;
2325 }
2326
2327 snd_soc_update_bits(codec, RT5645_TDM_CTRL_1, 0x7c00, val);
2328
2329 return 0;
2330}
2331
2332static int rt5645_set_bias_level(struct snd_soc_codec *codec,
2333 enum snd_soc_bias_level level)
2334{
2335 switch (level) {
0b2e4959
BL		 2336 case SND_SOC_BIAS_PREPARE:
2337 if (SND_SOC_BIAS_STANDBY == codec->dapm.bias_level) {
1319b2f6
OC		 2338 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2339 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2340 RT5645_PWR_BG | RT5645_PWR_VREF2,
2341 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2342 RT5645_PWR_BG | RT5645_PWR_VREF2);
2343 mdelay(10);
2344 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2345 RT5645_PWR_FV1 | RT5645_PWR_FV2,
2346 RT5645_PWR_FV1 | RT5645_PWR_FV2);
2347 snd_soc_update_bits(codec, RT5645_GEN_CTRL1,
2348 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
2349 }
2350 break;
2351
0b2e4959
BL		 2352 case SND_SOC_BIAS_STANDBY:
2353 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2354 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2355 RT5645_PWR_BG | RT5645_PWR_VREF2,
2356 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2357 RT5645_PWR_BG | RT5645_PWR_VREF2);
2358 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2359 RT5645_PWR_FV1 | RT5645_PWR_FV2,
2360 RT5645_PWR_FV1 | RT5645_PWR_FV2);
2361 break;
2362
1319b2f6
OC		 2363 case SND_SOC_BIAS_OFF:
2364 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1100);
2365 snd_soc_write(codec, RT5645_GEN_CTRL1, 0x0128);
0b2e4959
BL		 2366 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2367 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2368 RT5645_PWR_BG | RT5645_PWR_VREF2 |
2369 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0x0);
1319b2f6
OC		 2370 break;
2371
2372 default:
2373 break;
2374 }
2375 codec->dapm.bias_level = level;
2376
2377 return 0;
2378}
2379
471f208a 2380static int rt5645_jack_detect(struct snd_soc_codec *codec)
f3fa1bbd
OC		 2381{
2382 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2383 int gpio_state, jack_type = 0;
2384 unsigned int val;
2385
75945896
BL		 2386 if (!gpio_is_valid(rt5645->pdata.hp_det_gpio)) {
2387 dev_err(codec->dev, "invalid gpio\n");
2388 return -EINVAL;
2389 }
f3fa1bbd
OC		 2390 gpio_state = gpio_get_value(rt5645->pdata.hp_det_gpio);
2391
2392 dev_dbg(codec->dev, "gpio = %d(%d)\n", rt5645->pdata.hp_det_gpio,
2393 gpio_state);
2394
2395 if ((rt5645->pdata.gpio_hp_det_active_high && gpio_state) ||
2396 (!rt5645->pdata.gpio_hp_det_active_high && !gpio_state)) {
2397 snd_soc_dapm_force_enable_pin(&codec->dapm, "micbias1");
2398 snd_soc_dapm_force_enable_pin(&codec->dapm, "micbias2");
2399 snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2");
2400 snd_soc_dapm_force_enable_pin(&codec->dapm, "Mic Det Power");
2401 snd_soc_dapm_sync(&codec->dapm);
2402
2403 snd_soc_write(codec, RT5645_IN1_CTRL1, 0x0006);
2404 snd_soc_write(codec, RT5645_JD_CTRL3, 0x00b0);
2405
2406 snd_soc_update_bits(codec, RT5645_IN1_CTRL2,
2407 RT5645_CBJ_MN_JD, 0);
2408 snd_soc_update_bits(codec, RT5645_IN1_CTRL2,
2409 RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD);
2410
2411 msleep(400);
2412 val = snd_soc_read(codec, RT5645_IN1_CTRL3) & 0x7;
2413 dev_dbg(codec->dev, "val = %d\n", val);
2414
2415 if (val == 1 || val == 2)
2416 jack_type = SND_JACK_HEADSET;
2417 else
2418 jack_type = SND_JACK_HEADPHONE;
2419
2420 snd_soc_dapm_disable_pin(&codec->dapm, "micbias1");
2421 snd_soc_dapm_disable_pin(&codec->dapm, "micbias2");
2d4e2d02
BL		 2422 if (rt5645->pdata.jd_mode == 0)
2423 snd_soc_dapm_disable_pin(&codec->dapm, "LDO2");
f3fa1bbd
OC		 2424 snd_soc_dapm_disable_pin(&codec->dapm, "Mic Det Power");
2425 snd_soc_dapm_sync(&codec->dapm);
2426 }
2427
471f208a
BL		 2428 snd_soc_jack_report(rt5645->hp_jack, jack_type, SND_JACK_HEADPHONE);
2429 snd_soc_jack_report(rt5645->mic_jack, jack_type, SND_JACK_MICROPHONE);
f3fa1bbd
OC		 2430 return 0;
2431}
2432
2433int rt5645_set_jack_detect(struct snd_soc_codec *codec,
471f208a 2434 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack)
f3fa1bbd
OC		 2435{
2436 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2437
471f208a
BL		 2438 rt5645->hp_jack = hp_jack;
2439 rt5645->mic_jack = mic_jack;
2440 rt5645_jack_detect(codec);
f3fa1bbd
OC		 2441
2442 return 0;
2443}
2444EXPORT_SYMBOL_GPL(rt5645_set_jack_detect);
2445
cd6e82b8
OC		 2446static void rt5645_jack_detect_work(struct work_struct *work)
2447{
2448 struct rt5645_priv *rt5645 =
2449 container_of(work, struct rt5645_priv, jack_detect_work.work);
2450
471f208a 2451 rt5645_jack_detect(rt5645->codec);
cd6e82b8
OC		 2452}
2453
f3fa1bbd
OC		 2454static irqreturn_t rt5645_irq(int irq, void *data)
2455{
2456 struct rt5645_priv *rt5645 = data;
2457
cd6e82b8
OC		 2458 queue_delayed_work(system_power_efficient_wq,
2459 &rt5645->jack_detect_work, msecs_to_jiffies(250));
f3fa1bbd
OC		 2460
2461 return IRQ_HANDLED;
2462}
2463
1319b2f6
OC		 2464static int rt5645_probe(struct snd_soc_codec *codec)
2465{
2466 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2467
2468 rt5645->codec = codec;
2469
5c4ca99d
BL		 2470 switch (rt5645->codec_type) {
2471 case CODEC_TYPE_RT5645:
2472 snd_soc_dapm_add_routes(&codec->dapm,
2473 rt5645_specific_dapm_routes,
2474 ARRAY_SIZE(rt5645_specific_dapm_routes));
2475 break;
2476 case CODEC_TYPE_RT5650:
2477 snd_soc_dapm_new_controls(&codec->dapm,
2478 rt5650_specific_dapm_widgets,
2479 ARRAY_SIZE(rt5650_specific_dapm_widgets));
2480 snd_soc_dapm_add_routes(&codec->dapm,
2481 rt5650_specific_dapm_routes,
2482 ARRAY_SIZE(rt5650_specific_dapm_routes));
2483 break;
2484 }
2485
1319b2f6
OC		 2486 rt5645_set_bias_level(codec, SND_SOC_BIAS_OFF);
2487
2488 snd_soc_update_bits(codec, RT5645_CHARGE_PUMP, 0x0300, 0x0200);
1319b2f6 2489
bb656add
BL		 2490 /* for JD function */
2491 if (rt5645->pdata.en_jd_func) {
2492 snd_soc_dapm_force_enable_pin(&codec->dapm, "JD Power");
2493 snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2");
2494 snd_soc_dapm_sync(&codec->dapm);
2495 }
2496
1319b2f6
OC		 2497 return 0;
2498}
2499
2500static int rt5645_remove(struct snd_soc_codec *codec)
2501{
2502 rt5645_reset(codec);
2503 return 0;
2504}
2505
2506#ifdef CONFIG_PM
2507static int rt5645_suspend(struct snd_soc_codec *codec)
2508{
2509 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2510
2511 regcache_cache_only(rt5645->regmap, true);
2512 regcache_mark_dirty(rt5645->regmap);
2513
2514 return 0;
2515}
2516
2517static int rt5645_resume(struct snd_soc_codec *codec)
2518{
2519 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2520
2521 regcache_cache_only(rt5645->regmap, false);
0f776efd 2522 regcache_sync(rt5645->regmap);
1319b2f6
OC		 2523
2524 return 0;
2525}
2526#else
2527#define rt5645_suspend NULL
2528#define rt5645_resume NULL
2529#endif
2530
2531#define RT5645_STEREO_RATES SNDRV_PCM_RATE_8000_96000
2532#define RT5645_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
2533 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
2534
9e22f782 2535static struct snd_soc_dai_ops rt5645_aif_dai_ops = {
1319b2f6
OC		 2536 .hw_params = rt5645_hw_params,
2537 .set_fmt = rt5645_set_dai_fmt,
2538 .set_sysclk = rt5645_set_dai_sysclk,
2539 .set_tdm_slot = rt5645_set_tdm_slot,
2540 .set_pll = rt5645_set_dai_pll,
2541};
2542
9e22f782 2543static struct snd_soc_dai_driver rt5645_dai[] = {
1319b2f6
OC		 2544 {
2545 .name = "rt5645-aif1",
2546 .id = RT5645_AIF1,
2547 .playback = {
2548 .stream_name = "AIF1 Playback",
2549 .channels_min = 1,
2550 .channels_max = 2,
2551 .rates = RT5645_STEREO_RATES,
2552 .formats = RT5645_FORMATS,
2553 },
2554 .capture = {
2555 .stream_name = "AIF1 Capture",
2556 .channels_min = 1,
2557 .channels_max = 2,
2558 .rates = RT5645_STEREO_RATES,
2559 .formats = RT5645_FORMATS,
2560 },
2561 .ops = &rt5645_aif_dai_ops,
2562 },
2563 {
2564 .name = "rt5645-aif2",
2565 .id = RT5645_AIF2,
2566 .playback = {
2567 .stream_name = "AIF2 Playback",
2568 .channels_min = 1,
2569 .channels_max = 2,
2570 .rates = RT5645_STEREO_RATES,
2571 .formats = RT5645_FORMATS,
2572 },
2573 .capture = {
2574 .stream_name = "AIF2 Capture",
2575 .channels_min = 1,
2576 .channels_max = 2,
2577 .rates = RT5645_STEREO_RATES,
2578 .formats = RT5645_FORMATS,
2579 },
2580 .ops = &rt5645_aif_dai_ops,
2581 },
2582};
2583
2584static struct snd_soc_codec_driver soc_codec_dev_rt5645 = {
2585 .probe = rt5645_probe,
2586 .remove = rt5645_remove,
2587 .suspend = rt5645_suspend,
2588 .resume = rt5645_resume,
2589 .set_bias_level = rt5645_set_bias_level,
2590 .idle_bias_off = true,
2591 .controls = rt5645_snd_controls,
2592 .num_controls = ARRAY_SIZE(rt5645_snd_controls),
2593 .dapm_widgets = rt5645_dapm_widgets,
2594 .num_dapm_widgets = ARRAY_SIZE(rt5645_dapm_widgets),
2595 .dapm_routes = rt5645_dapm_routes,
2596 .num_dapm_routes = ARRAY_SIZE(rt5645_dapm_routes),
2597};
2598
2599static const struct regmap_config rt5645_regmap = {
2600 .reg_bits = 8,
2601 .val_bits = 16,
2602
2603 .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) *
2604 RT5645_PR_SPACING),
2605 .volatile_reg = rt5645_volatile_register,
2606 .readable_reg = rt5645_readable_register,
2607
2608 .cache_type = REGCACHE_RBTREE,
2609 .reg_defaults = rt5645_reg,
2610 .num_reg_defaults = ARRAY_SIZE(rt5645_reg),
2611 .ranges = rt5645_ranges,
2612 .num_ranges = ARRAY_SIZE(rt5645_ranges),
2613};
2614
2615static const struct i2c_device_id rt5645_i2c_id[] = {
2616 { "rt5645", 0 },
5c4ca99d 2617 { "rt5650", 0 },
1319b2f6
OC		 2618 { }
2619};
2620MODULE_DEVICE_TABLE(i2c, rt5645_i2c_id);
2621
3168c201
FY		 2622#ifdef CONFIG_ACPI
2623static struct acpi_device_id rt5645_acpi_match[] = {
2624 { "10EC5645", 0 },
2625 { "10EC5650", 0 },
2626 {},
2627};
2628MODULE_DEVICE_TABLE(acpi, rt5645_acpi_match);
2629#endif
2630
1319b2f6
OC		 2631static int rt5645_i2c_probe(struct i2c_client *i2c,
2632 const struct i2c_device_id *id)
2633{
2634 struct rt5645_platform_data *pdata = dev_get_platdata(&i2c->dev);
2635 struct rt5645_priv *rt5645;
2636 int ret;
2637 unsigned int val;
2638
2639 rt5645 = devm_kzalloc(&i2c->dev, sizeof(struct rt5645_priv),
2640 GFP_KERNEL);
2641 if (rt5645 == NULL)
2642 return -ENOMEM;
2643
f3fa1bbd 2644 rt5645->i2c = i2c;
1319b2f6
OC		 2645 i2c_set_clientdata(i2c, rt5645);
2646
2647 if (pdata)
2648 rt5645->pdata = *pdata;
2649
2650 rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5645_regmap);
2651 if (IS_ERR(rt5645->regmap)) {
2652 ret = PTR_ERR(rt5645->regmap);
2653 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2654 ret);
2655 return ret;
2656 }
2657
2658 regmap_read(rt5645->regmap, RT5645_VENDOR_ID2, &val);
5c4ca99d
BL		 2659
2660 switch (val) {
2661 case RT5645_DEVICE_ID:
2662 rt5645->codec_type = CODEC_TYPE_RT5645;
2663 break;
2664 case RT5650_DEVICE_ID:
2665 rt5645->codec_type = CODEC_TYPE_RT5650;
2666 break;
2667 default:
1319b2f6 2668 dev_err(&i2c->dev,
5c4ca99d
BL		 2669 "Device with ID register %x is not rt5645 or rt5650\n",
2670 val);
1319b2f6
OC		 2671 return -ENODEV;
2672 }
2673
2674 regmap_write(rt5645->regmap, RT5645_RESET, 0);
2675
2676 ret = regmap_register_patch(rt5645->regmap, init_list,
2677 ARRAY_SIZE(init_list));
2678 if (ret != 0)
2679 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
2680
5c4ca99d
BL		 2681 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
2682 ret = regmap_register_patch(rt5645->regmap, rt5650_init_list,
2683 ARRAY_SIZE(rt5650_init_list));
2684 if (ret != 0)
2685 dev_warn(&i2c->dev, "Apply rt5650 patch failed: %d\n",
2686 ret);
2687 }
2688
1319b2f6
OC		 2689 if (rt5645->pdata.in2_diff)
2690 regmap_update_bits(rt5645->regmap, RT5645_IN2_CTRL,
2691 RT5645_IN_DF2, RT5645_IN_DF2);
2692
2693 if (rt5645->pdata.dmic_en) {
2694 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2695 RT5645_GP2_PIN_MASK, RT5645_GP2_PIN_DMIC1_SCL);
2696
2697 switch (rt5645->pdata.dmic1_data_pin) {
2698 case RT5645_DMIC_DATA_IN2N:
2699 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2700 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_IN2N);
2701 break;
2702
2703 case RT5645_DMIC_DATA_GPIO5:
2704 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2705 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO5);
2706 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2707 RT5645_GP5_PIN_MASK, RT5645_GP5_PIN_DMIC1_SDA);
2708 break;
2709
2710 case RT5645_DMIC_DATA_GPIO11:
2711 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2712 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO11);
2713 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2714 RT5645_GP11_PIN_MASK,
2715 RT5645_GP11_PIN_DMIC1_SDA);
2716 break;
2717
2718 default:
2719 break;
2720 }
2721
2722 switch (rt5645->pdata.dmic2_data_pin) {
2723 case RT5645_DMIC_DATA_IN2P:
2724 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2725 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_IN2P);
2726 break;
2727
2728 case RT5645_DMIC_DATA_GPIO6:
2729 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2730 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO6);
2731 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2732 RT5645_GP6_PIN_MASK, RT5645_GP6_PIN_DMIC2_SDA);
2733 break;
2734
2735 case RT5645_DMIC_DATA_GPIO10:
2736 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2737 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO10);
2738 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2739 RT5645_GP10_PIN_MASK,
2740 RT5645_GP10_PIN_DMIC2_SDA);
2741 break;
2742
2743 case RT5645_DMIC_DATA_GPIO12:
2744 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
53f9b3ba 2745 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO12);
1319b2f6
OC		 2746 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2747 RT5645_GP12_PIN_MASK,
2748 RT5645_GP12_PIN_DMIC2_SDA);
2749 break;
2750
2751 default:
2752 break;
2753 }
2754
2755 }
2756
bb656add
BL		 2757 if (rt5645->pdata.en_jd_func) {
2758 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
2759 RT5645_IRQ_CLK_GATE_CTRL | RT5645_MICINDET_MANU,
2760 RT5645_IRQ_CLK_GATE_CTRL | RT5645_MICINDET_MANU);
2761 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1,
2762 RT5645_CBJ_BST1_EN, RT5645_CBJ_BST1_EN);
2763 regmap_update_bits(rt5645->regmap, RT5645_JD_CTRL3,
2764 RT5645_JD_CBJ_EN | RT5645_JD_CBJ_POL,
2765 RT5645_JD_CBJ_EN | RT5645_JD_CBJ_POL);
2766 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
2767 RT5645_IRQ_CLK_INT, RT5645_IRQ_CLK_INT);
2768 }
2769
2d4e2d02
BL		 2770 if (rt5645->pdata.jd_mode) {
2771 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
2772 RT5645_IRQ_JD_1_1_EN, RT5645_IRQ_JD_1_1_EN);
2773 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
2774 RT5645_JD_PSV_MODE, RT5645_JD_PSV_MODE);
2775 regmap_update_bits(rt5645->regmap, RT5645_HPO_MIXER,
2776 RT5645_IRQ_PSV_MODE, RT5645_IRQ_PSV_MODE);
2777 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
2778 RT5645_MIC2_OVCD_EN, RT5645_MIC2_OVCD_EN);
2779 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2780 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);
2781 switch (rt5645->pdata.jd_mode) {
2782 case 1:
2783 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
2784 RT5645_JD1_MODE_MASK,
2785 RT5645_JD1_MODE_0);
2786 break;
2787 case 2:
2788 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
2789 RT5645_JD1_MODE_MASK,
2790 RT5645_JD1_MODE_1);
2791 break;
2792 case 3:
2793 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
2794 RT5645_JD1_MODE_MASK,
2795 RT5645_JD1_MODE_2);
2796 break;
2797 default:
2798 break;
2799 }
2800 }
2801
f3fa1bbd
OC		 2802 if (rt5645->i2c->irq) {
2803 ret = request_threaded_irq(rt5645->i2c->irq, NULL, rt5645_irq,
2804 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2805 | IRQF_ONESHOT, "rt5645", rt5645);
2806 if (ret)
2807 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
2808 }
2809
2810 if (gpio_is_valid(rt5645->pdata.hp_det_gpio)) {
2811 ret = gpio_request(rt5645->pdata.hp_det_gpio, "rt5645");
2812 if (ret)
2813 dev_err(&i2c->dev, "Fail gpio_request hp_det_gpio\n");
2814
2815 ret = gpio_direction_input(rt5645->pdata.hp_det_gpio);
2816 if (ret)
2817 dev_err(&i2c->dev, "Fail gpio_direction hp_det_gpio\n");
2818 }
2819
cd6e82b8
OC		 2820 INIT_DELAYED_WORK(&rt5645->jack_detect_work, rt5645_jack_detect_work);
2821
dd56ebad
AL		 2822 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5645,
2823 rt5645_dai, ARRAY_SIZE(rt5645_dai));
1319b2f6
OC		 2824}
2825
2826static int rt5645_i2c_remove(struct i2c_client *i2c)
2827{
f3fa1bbd
OC		 2828 struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c);
2829
2830 if (i2c->irq)
2831 free_irq(i2c->irq, rt5645);
2832
cd6e82b8
OC		 2833 cancel_delayed_work_sync(&rt5645->jack_detect_work);
2834
f3fa1bbd
OC		 2835 if (gpio_is_valid(rt5645->pdata.hp_det_gpio))
2836 gpio_free(rt5645->pdata.hp_det_gpio);
2837
1319b2f6
OC		 2838 snd_soc_unregister_codec(&i2c->dev);
2839
2840 return 0;
2841}
2842
9e22f782 2843static struct i2c_driver rt5645_i2c_driver = {
1319b2f6
OC		 2844 .driver = {
2845 .name = "rt5645",
2846 .owner = THIS_MODULE,
3168c201 2847 .acpi_match_table = ACPI_PTR(rt5645_acpi_match),
1319b2f6
OC		 2848 },
2849 .probe = rt5645_i2c_probe,
2850 .remove = rt5645_i2c_remove,
2851 .id_table = rt5645_i2c_id,
2852};
2853module_i2c_driver(rt5645_i2c_driver);
2854
2855MODULE_DESCRIPTION("ASoC RT5645 driver");
2856MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
2857MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)