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ASoC: SMA1303: Remove the sysclk setting in devicetree
[linux-2.6-block.git] / sound / soc / codecs / rt5640.c
CommitLineData
d2912cb1 1// SPDX-License-Identifier: GPL-2.0-only
997b0520 2/*
b0c27846 3 * rt5640.c -- RT5640/RT5639 ALSA SoC audio codec driver
997b0520
BL		 4 *
5 * Copyright 2011 Realtek Semiconductor Corp.
6 * Author: Johnny Hsu <johnnyhsu@realtek.com>
7 * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
997b0520
BL		 8 */
9
10#include <linux/module.h>
11#include <linux/moduleparam.h>
12#include <linux/init.h>
13#include <linux/delay.h>
14#include <linux/pm.h>
15#include <linux/gpio.h>
16#include <linux/i2c.h>
17#include <linux/regmap.h>
affb74ad 18#include <linux/of.h>
dcad9f03 19#include <linux/of_gpio.h>
997b0520
BL		 20#include <linux/platform_device.h>
21#include <linux/spi/spi.h>
02b80773 22#include <linux/acpi.h>
997b0520 23#include <sound/core.h>
8210804b 24#include <sound/jack.h>
997b0520
BL		 25#include <sound/pcm.h>
26#include <sound/pcm_params.h>
27#include <sound/soc.h>
28#include <sound/soc-dapm.h>
29#include <sound/initval.h>
30#include <sound/tlv.h>
31
49ef7925 32#include "rl6231.h"
997b0520
BL		 33#include "rt5640.h"
34
35#define RT5640_DEVICE_ID 0x6231
36
37#define RT5640_PR_RANGE_BASE (0xff + 1)
38#define RT5640_PR_SPACING 0x100
39
40#define RT5640_PR_BASE (RT5640_PR_RANGE_BASE + (0 * RT5640_PR_SPACING))
41
42static const struct regmap_range_cfg rt5640_ranges[] = {
43 { .name = "PR", .range_min = RT5640_PR_BASE,
44 .range_max = RT5640_PR_BASE + 0xb4,
45 .selector_reg = RT5640_PRIV_INDEX,
46 .selector_mask = 0xff,
47 .selector_shift = 0x0,
48 .window_start = RT5640_PRIV_DATA,
49 .window_len = 0x1, },
50};
51
8019ff6c 52static const struct reg_sequence init_list[] = {
997b0520 53 {RT5640_PR_BASE + 0x3d, 0x3600},
997b0520
BL		 54 {RT5640_PR_BASE + 0x12, 0x0aa8},
55 {RT5640_PR_BASE + 0x14, 0x0aaa},
56 {RT5640_PR_BASE + 0x20, 0x6110},
57 {RT5640_PR_BASE + 0x21, 0xe0e0},
58 {RT5640_PR_BASE + 0x23, 0x1804},
59};
997b0520 60
2f2a714c 61static const struct reg_default rt5640_reg[] = {
997b0520
BL		 62 { 0x00, 0x000e },
63 { 0x01, 0xc8c8 },
64 { 0x02, 0xc8c8 },
65 { 0x03, 0xc8c8 },
66 { 0x04, 0x8000 },
67 { 0x0d, 0x0000 },
68 { 0x0e, 0x0000 },
69 { 0x0f, 0x0808 },
70 { 0x19, 0xafaf },
71 { 0x1a, 0xafaf },
72 { 0x1b, 0x0000 },
73 { 0x1c, 0x2f2f },
74 { 0x1d, 0x2f2f },
75 { 0x1e, 0x0000 },
76 { 0x27, 0x7060 },
77 { 0x28, 0x7070 },
78 { 0x29, 0x8080 },
79 { 0x2a, 0x5454 },
80 { 0x2b, 0x5454 },
81 { 0x2c, 0xaa00 },
82 { 0x2d, 0x0000 },
83 { 0x2e, 0xa000 },
84 { 0x2f, 0x0000 },
85 { 0x3b, 0x0000 },
86 { 0x3c, 0x007f },
87 { 0x3d, 0x0000 },
88 { 0x3e, 0x007f },
89 { 0x45, 0xe000 },
90 { 0x46, 0x003e },
91 { 0x47, 0x003e },
92 { 0x48, 0xf800 },
93 { 0x49, 0x3800 },
94 { 0x4a, 0x0004 },
95 { 0x4c, 0xfc00 },
96 { 0x4d, 0x0000 },
97 { 0x4f, 0x01ff },
98 { 0x50, 0x0000 },
99 { 0x51, 0x0000 },
100 { 0x52, 0x01ff },
101 { 0x53, 0xf000 },
102 { 0x61, 0x0000 },
103 { 0x62, 0x0000 },
104 { 0x63, 0x00c0 },
105 { 0x64, 0x0000 },
106 { 0x65, 0x0000 },
107 { 0x66, 0x0000 },
108 { 0x6a, 0x0000 },
109 { 0x6c, 0x0000 },
110 { 0x70, 0x8000 },
111 { 0x71, 0x8000 },
112 { 0x72, 0x8000 },
113 { 0x73, 0x1114 },
114 { 0x74, 0x0c00 },
115 { 0x75, 0x1d00 },
116 { 0x80, 0x0000 },
117 { 0x81, 0x0000 },
118 { 0x82, 0x0000 },
119 { 0x83, 0x0000 },
120 { 0x84, 0x0000 },
121 { 0x85, 0x0008 },
122 { 0x89, 0x0000 },
123 { 0x8a, 0x0000 },
124 { 0x8b, 0x0600 },
125 { 0x8c, 0x0228 },
126 { 0x8d, 0xa000 },
127 { 0x8e, 0x0004 },
128 { 0x8f, 0x1100 },
129 { 0x90, 0x0646 },
130 { 0x91, 0x0c00 },
131 { 0x92, 0x0000 },
132 { 0x93, 0x3000 },
133 { 0xb0, 0x2080 },
134 { 0xb1, 0x0000 },
135 { 0xb4, 0x2206 },
136 { 0xb5, 0x1f00 },
137 { 0xb6, 0x0000 },
138 { 0xb8, 0x034b },
139 { 0xb9, 0x0066 },
140 { 0xba, 0x000b },
141 { 0xbb, 0x0000 },
142 { 0xbc, 0x0000 },
143 { 0xbd, 0x0000 },
144 { 0xbe, 0x0000 },
145 { 0xbf, 0x0000 },
146 { 0xc0, 0x0400 },
147 { 0xc2, 0x0000 },
148 { 0xc4, 0x0000 },
149 { 0xc5, 0x0000 },
150 { 0xc6, 0x2000 },
151 { 0xc8, 0x0000 },
152 { 0xc9, 0x0000 },
153 { 0xca, 0x0000 },
154 { 0xcb, 0x0000 },
155 { 0xcc, 0x0000 },
156 { 0xcf, 0x0013 },
157 { 0xd0, 0x0680 },
158 { 0xd1, 0x1c17 },
159 { 0xd2, 0x8c00 },
160 { 0xd3, 0xaa20 },
161 { 0xd6, 0x0400 },
162 { 0xd9, 0x0809 },
163 { 0xfe, 0x10ec },
164 { 0xff, 0x6231 },
165};
166
d5a41b5d 167static int rt5640_reset(struct snd_soc_component *component)
997b0520 168{
d5a41b5d 169 return snd_soc_component_write(component, RT5640_RESET, 0);
997b0520
BL		 170}
171
172static bool rt5640_volatile_register(struct device *dev, unsigned int reg)
173{
174 int i;
175
176 for (i = 0; i < ARRAY_SIZE(rt5640_ranges); i++)
177 if ((reg >= rt5640_ranges[i].window_start &&
178 reg <= rt5640_ranges[i].window_start +
179 rt5640_ranges[i].window_len) ||
180 (reg >= rt5640_ranges[i].range_min &&
181 reg <= rt5640_ranges[i].range_max))
182 return true;
183
184 switch (reg) {
185 case RT5640_RESET:
186 case RT5640_ASRC_5:
187 case RT5640_EQ_CTRL1:
188 case RT5640_DRC_AGC_1:
189 case RT5640_ANC_CTRL1:
190 case RT5640_IRQ_CTRL2:
191 case RT5640_INT_IRQ_ST:
192 case RT5640_DSP_CTRL2:
193 case RT5640_DSP_CTRL3:
194 case RT5640_PRIV_INDEX:
195 case RT5640_PRIV_DATA:
196 case RT5640_PGM_REG_ARR1:
197 case RT5640_PGM_REG_ARR3:
2b9c8d2b 198 case RT5640_DUMMY2:
997b0520
BL		 199 case RT5640_VENDOR_ID:
200 case RT5640_VENDOR_ID1:
201 case RT5640_VENDOR_ID2:
202 return true;
203 default:
204 return false;
205 }
206}
207
208static bool rt5640_readable_register(struct device *dev, unsigned int reg)
209{
210 int i;
211
212 for (i = 0; i < ARRAY_SIZE(rt5640_ranges); i++)
213 if ((reg >= rt5640_ranges[i].window_start &&
214 reg <= rt5640_ranges[i].window_start +
215 rt5640_ranges[i].window_len) ||
216 (reg >= rt5640_ranges[i].range_min &&
217 reg <= rt5640_ranges[i].range_max))
218 return true;
219
220 switch (reg) {
221 case RT5640_RESET:
222 case RT5640_SPK_VOL:
223 case RT5640_HP_VOL:
224 case RT5640_OUTPUT:
225 case RT5640_MONO_OUT:
226 case RT5640_IN1_IN2:
227 case RT5640_IN3_IN4:
228 case RT5640_INL_INR_VOL:
229 case RT5640_DAC1_DIG_VOL:
230 case RT5640_DAC2_DIG_VOL:
231 case RT5640_DAC2_CTRL:
232 case RT5640_ADC_DIG_VOL:
233 case RT5640_ADC_DATA:
234 case RT5640_ADC_BST_VOL:
235 case RT5640_STO_ADC_MIXER:
236 case RT5640_MONO_ADC_MIXER:
237 case RT5640_AD_DA_MIXER:
238 case RT5640_STO_DAC_MIXER:
239 case RT5640_MONO_DAC_MIXER:
240 case RT5640_DIG_MIXER:
241 case RT5640_DSP_PATH1:
242 case RT5640_DSP_PATH2:
243 case RT5640_DIG_INF_DATA:
244 case RT5640_REC_L1_MIXER:
245 case RT5640_REC_L2_MIXER:
246 case RT5640_REC_R1_MIXER:
247 case RT5640_REC_R2_MIXER:
248 case RT5640_HPO_MIXER:
249 case RT5640_SPK_L_MIXER:
250 case RT5640_SPK_R_MIXER:
251 case RT5640_SPO_L_MIXER:
252 case RT5640_SPO_R_MIXER:
253 case RT5640_SPO_CLSD_RATIO:
254 case RT5640_MONO_MIXER:
255 case RT5640_OUT_L1_MIXER:
256 case RT5640_OUT_L2_MIXER:
257 case RT5640_OUT_L3_MIXER:
258 case RT5640_OUT_R1_MIXER:
259 case RT5640_OUT_R2_MIXER:
260 case RT5640_OUT_R3_MIXER:
261 case RT5640_LOUT_MIXER:
262 case RT5640_PWR_DIG1:
263 case RT5640_PWR_DIG2:
264 case RT5640_PWR_ANLG1:
265 case RT5640_PWR_ANLG2:
266 case RT5640_PWR_MIXER:
267 case RT5640_PWR_VOL:
268 case RT5640_PRIV_INDEX:
269 case RT5640_PRIV_DATA:
270 case RT5640_I2S1_SDP:
271 case RT5640_I2S2_SDP:
272 case RT5640_ADDA_CLK1:
273 case RT5640_ADDA_CLK2:
274 case RT5640_DMIC:
275 case RT5640_GLB_CLK:
276 case RT5640_PLL_CTRL1:
277 case RT5640_PLL_CTRL2:
278 case RT5640_ASRC_1:
279 case RT5640_ASRC_2:
280 case RT5640_ASRC_3:
281 case RT5640_ASRC_4:
282 case RT5640_ASRC_5:
283 case RT5640_HP_OVCD:
284 case RT5640_CLS_D_OVCD:
285 case RT5640_CLS_D_OUT:
286 case RT5640_DEPOP_M1:
287 case RT5640_DEPOP_M2:
288 case RT5640_DEPOP_M3:
289 case RT5640_CHARGE_PUMP:
290 case RT5640_PV_DET_SPK_G:
291 case RT5640_MICBIAS:
292 case RT5640_EQ_CTRL1:
293 case RT5640_EQ_CTRL2:
294 case RT5640_WIND_FILTER:
295 case RT5640_DRC_AGC_1:
296 case RT5640_DRC_AGC_2:
297 case RT5640_DRC_AGC_3:
298 case RT5640_SVOL_ZC:
299 case RT5640_ANC_CTRL1:
300 case RT5640_ANC_CTRL2:
301 case RT5640_ANC_CTRL3:
302 case RT5640_JD_CTRL:
303 case RT5640_ANC_JD:
304 case RT5640_IRQ_CTRL1:
305 case RT5640_IRQ_CTRL2:
306 case RT5640_INT_IRQ_ST:
307 case RT5640_GPIO_CTRL1:
308 case RT5640_GPIO_CTRL2:
309 case RT5640_GPIO_CTRL3:
310 case RT5640_DSP_CTRL1:
311 case RT5640_DSP_CTRL2:
312 case RT5640_DSP_CTRL3:
313 case RT5640_DSP_CTRL4:
314 case RT5640_PGM_REG_ARR1:
315 case RT5640_PGM_REG_ARR2:
316 case RT5640_PGM_REG_ARR3:
317 case RT5640_PGM_REG_ARR4:
318 case RT5640_PGM_REG_ARR5:
319 case RT5640_SCB_FUNC:
320 case RT5640_SCB_CTRL:
321 case RT5640_BASE_BACK:
322 case RT5640_MP3_PLUS1:
323 case RT5640_MP3_PLUS2:
324 case RT5640_3D_HP:
325 case RT5640_ADJ_HPF:
326 case RT5640_HP_CALIB_AMP_DET:
327 case RT5640_HP_CALIB2:
328 case RT5640_SV_ZCD1:
329 case RT5640_SV_ZCD2:
330 case RT5640_DUMMY1:
331 case RT5640_DUMMY2:
332 case RT5640_DUMMY3:
333 case RT5640_VENDOR_ID:
334 case RT5640_VENDOR_ID1:
335 case RT5640_VENDOR_ID2:
336 return true;
337 default:
338 return false;
339 }
340}
341
342static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
cfa26ed1 343static const DECLARE_TLV_DB_MINMAX(dac_vol_tlv, -6562, 0);
997b0520 344static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
cfa26ed1 345static const DECLARE_TLV_DB_MINMAX(adc_vol_tlv, -1762, 3000);
997b0520
BL		 346static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
347
348/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
8295822d 349static const DECLARE_TLV_DB_RANGE(bst_tlv,
997b0520
BL		 350 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
351 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
352 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
353 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
354 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
355 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
8295822d
LPC		 356 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
357);
997b0520
BL		 358
359/* Interface data select */
360static const char * const rt5640_data_select[] = {
653aa464 361 "Normal", "Swap", "left copy to right", "right copy to left"};
997b0520 362
4c03cb6f
TI		 363static SOC_ENUM_SINGLE_DECL(rt5640_if1_dac_enum, RT5640_DIG_INF_DATA,
364 RT5640_IF1_DAC_SEL_SFT, rt5640_data_select);
997b0520 365
4c03cb6f
TI		 366static SOC_ENUM_SINGLE_DECL(rt5640_if1_adc_enum, RT5640_DIG_INF_DATA,
367 RT5640_IF1_ADC_SEL_SFT, rt5640_data_select);
997b0520 368
4c03cb6f
TI		 369static SOC_ENUM_SINGLE_DECL(rt5640_if2_dac_enum, RT5640_DIG_INF_DATA,
370 RT5640_IF2_DAC_SEL_SFT, rt5640_data_select);
997b0520 371
4c03cb6f
TI		 372static SOC_ENUM_SINGLE_DECL(rt5640_if2_adc_enum, RT5640_DIG_INF_DATA,
373 RT5640_IF2_ADC_SEL_SFT, rt5640_data_select);
997b0520
BL		 374
375/* Class D speaker gain ratio */
376static const char * const rt5640_clsd_spk_ratio[] = {"1.66x", "1.83x", "1.94x",
377 "2x", "2.11x", "2.22x", "2.33x", "2.44x", "2.55x", "2.66x", "2.77x"};
378
4c03cb6f
TI		 379static SOC_ENUM_SINGLE_DECL(rt5640_clsd_spk_ratio_enum, RT5640_CLS_D_OUT,
380 RT5640_CLSD_RATIO_SFT, rt5640_clsd_spk_ratio);
997b0520
BL		 381
382static const struct snd_kcontrol_new rt5640_snd_controls[] = {
383 /* Speaker Output Volume */
997b0520
BL		 384 SOC_DOUBLE("Speaker Channel Switch", RT5640_SPK_VOL,
385 RT5640_VOL_L_SFT, RT5640_VOL_R_SFT, 1, 1),
386 SOC_DOUBLE_TLV("Speaker Playback Volume", RT5640_SPK_VOL,
387 RT5640_L_VOL_SFT, RT5640_R_VOL_SFT, 39, 1, out_vol_tlv),
388 /* Headphone Output Volume */
997b0520
BL		 389 SOC_DOUBLE("HP Channel Switch", RT5640_HP_VOL,
390 RT5640_VOL_L_SFT, RT5640_VOL_R_SFT, 1, 1),
391 SOC_DOUBLE_TLV("HP Playback Volume", RT5640_HP_VOL,
392 RT5640_L_VOL_SFT, RT5640_R_VOL_SFT, 39, 1, out_vol_tlv),
393 /* OUTPUT Control */
394 SOC_DOUBLE("OUT Playback Switch", RT5640_OUTPUT,
395 RT5640_L_MUTE_SFT, RT5640_R_MUTE_SFT, 1, 1),
396 SOC_DOUBLE("OUT Channel Switch", RT5640_OUTPUT,
397 RT5640_VOL_L_SFT, RT5640_VOL_R_SFT, 1, 1),
398 SOC_DOUBLE_TLV("OUT Playback Volume", RT5640_OUTPUT,
399 RT5640_L_VOL_SFT, RT5640_R_VOL_SFT, 39, 1, out_vol_tlv),
022d21f0 400
997b0520
BL		 401 /* DAC Digital Volume */
402 SOC_DOUBLE("DAC2 Playback Switch", RT5640_DAC2_CTRL,
403 RT5640_M_DAC_L2_VOL_SFT, RT5640_M_DAC_R2_VOL_SFT, 1, 1),
40e40469
HG		 404 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5640_DAC2_DIG_VOL,
405 RT5640_L_VOL_SFT, RT5640_R_VOL_SFT,
406 175, 0, dac_vol_tlv),
997b0520
BL		 407 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5640_DAC1_DIG_VOL,
408 RT5640_L_VOL_SFT, RT5640_R_VOL_SFT,
409 175, 0, dac_vol_tlv),
16566e47 410 /* IN1/IN2/IN3 Control */
997b0520
BL		 411 SOC_SINGLE_TLV("IN1 Boost", RT5640_IN1_IN2,
412 RT5640_BST_SFT1, 8, 0, bst_tlv),
413 SOC_SINGLE_TLV("IN2 Boost", RT5640_IN3_IN4,
414 RT5640_BST_SFT2, 8, 0, bst_tlv),
16566e47
OC		 415 SOC_SINGLE_TLV("IN3 Boost", RT5640_IN1_IN2,
416 RT5640_BST_SFT2, 8, 0, bst_tlv),
417
997b0520
BL		 418 /* INL/INR Volume Control */
419 SOC_DOUBLE_TLV("IN Capture Volume", RT5640_INL_INR_VOL,
420 RT5640_INL_VOL_SFT, RT5640_INR_VOL_SFT,
421 31, 1, in_vol_tlv),
422 /* ADC Digital Volume Control */
423 SOC_DOUBLE("ADC Capture Switch", RT5640_ADC_DIG_VOL,
424 RT5640_L_MUTE_SFT, RT5640_R_MUTE_SFT, 1, 1),
425 SOC_DOUBLE_TLV("ADC Capture Volume", RT5640_ADC_DIG_VOL,
426 RT5640_L_VOL_SFT, RT5640_R_VOL_SFT,
427 127, 0, adc_vol_tlv),
ca5f17c5
BL		 428 SOC_DOUBLE("Mono ADC Capture Switch", RT5640_DUMMY1,
429 RT5640_M_MONO_ADC_L_SFT, RT5640_M_MONO_ADC_R_SFT, 1, 1),
997b0520
BL		 430 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5640_ADC_DATA,
431 RT5640_L_VOL_SFT, RT5640_R_VOL_SFT,
432 127, 0, adc_vol_tlv),
433 /* ADC Boost Volume Control */
434 SOC_DOUBLE_TLV("ADC Boost Gain", RT5640_ADC_BST_VOL,
435 RT5640_ADC_L_BST_SFT, RT5640_ADC_R_BST_SFT,
436 3, 0, adc_bst_tlv),
437 /* Class D speaker gain ratio */
438 SOC_ENUM("Class D SPK Ratio Control", rt5640_clsd_spk_ratio_enum),
439
440 SOC_ENUM("ADC IF1 Data Switch", rt5640_if1_adc_enum),
441 SOC_ENUM("DAC IF1 Data Switch", rt5640_if1_dac_enum),
442 SOC_ENUM("ADC IF2 Data Switch", rt5640_if2_adc_enum),
443 SOC_ENUM("DAC IF2 Data Switch", rt5640_if2_dac_enum),
444};
445
022d21f0
OC		 446static const struct snd_kcontrol_new rt5640_specific_snd_controls[] = {
447 /* MONO Output Control */
448 SOC_SINGLE("Mono Playback Switch", RT5640_MONO_OUT, RT5640_L_MUTE_SFT,
449 1, 1),
022d21f0
OC		 450};
451
997b0520
BL		 452/**
453 * set_dmic_clk - Set parameter of dmic.
454 *
455 * @w: DAPM widget.
456 * @kcontrol: The kcontrol of this widget.
457 * @event: Event id.
458 *
997b0520
BL		 459 */
460static int set_dmic_clk(struct snd_soc_dapm_widget *w,
461 struct snd_kcontrol *kcontrol, int event)
462{
d5a41b5d
KM		 463 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
464 struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
00a6d6e5 465 int idx, rate;
49ef7925 466
00a6d6e5
OC		 467 rate = rt5640->sysclk / rl6231_get_pre_div(rt5640->regmap,
468 RT5640_ADDA_CLK1, RT5640_I2S_PD1_SFT);
469 idx = rl6231_calc_dmic_clk(rate);
997b0520 470 if (idx < 0)
d5a41b5d 471 dev_err(component->dev, "Failed to set DMIC clock\n");
997b0520 472 else
d5a41b5d 473 snd_soc_component_update_bits(component, RT5640_DMIC, RT5640_DMIC_CLK_MASK,
997b0520
BL		 474 idx << RT5640_DMIC_CLK_SFT);
475 return idx;
476}
477
bee3e020
JY		 478static int is_using_asrc(struct snd_soc_dapm_widget *source,
479 struct snd_soc_dapm_widget *sink)
480{
d5a41b5d
KM		 481 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
482 struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
bee3e020
JY		 483
484 if (!rt5640->asrc_en)
485 return 0;
486
487 return 1;
488}
489
997b0520
BL		 490/* Digital Mixer */
491static const struct snd_kcontrol_new rt5640_sto_adc_l_mix[] = {
492 SOC_DAPM_SINGLE("ADC1 Switch", RT5640_STO_ADC_MIXER,
493 RT5640_M_ADC_L1_SFT, 1, 1),
494 SOC_DAPM_SINGLE("ADC2 Switch", RT5640_STO_ADC_MIXER,
495 RT5640_M_ADC_L2_SFT, 1, 1),
496};
497
498static const struct snd_kcontrol_new rt5640_sto_adc_r_mix[] = {
499 SOC_DAPM_SINGLE("ADC1 Switch", RT5640_STO_ADC_MIXER,
500 RT5640_M_ADC_R1_SFT, 1, 1),
501 SOC_DAPM_SINGLE("ADC2 Switch", RT5640_STO_ADC_MIXER,
502 RT5640_M_ADC_R2_SFT, 1, 1),
503};
504
505static const struct snd_kcontrol_new rt5640_mono_adc_l_mix[] = {
506 SOC_DAPM_SINGLE("ADC1 Switch", RT5640_MONO_ADC_MIXER,
507 RT5640_M_MONO_ADC_L1_SFT, 1, 1),
508 SOC_DAPM_SINGLE("ADC2 Switch", RT5640_MONO_ADC_MIXER,
509 RT5640_M_MONO_ADC_L2_SFT, 1, 1),
510};
511
512static const struct snd_kcontrol_new rt5640_mono_adc_r_mix[] = {
513 SOC_DAPM_SINGLE("ADC1 Switch", RT5640_MONO_ADC_MIXER,
514 RT5640_M_MONO_ADC_R1_SFT, 1, 1),
515 SOC_DAPM_SINGLE("ADC2 Switch", RT5640_MONO_ADC_MIXER,
516 RT5640_M_MONO_ADC_R2_SFT, 1, 1),
517};
518
519static const struct snd_kcontrol_new rt5640_dac_l_mix[] = {
520 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5640_AD_DA_MIXER,
521 RT5640_M_ADCMIX_L_SFT, 1, 1),
522 SOC_DAPM_SINGLE("INF1 Switch", RT5640_AD_DA_MIXER,
523 RT5640_M_IF1_DAC_L_SFT, 1, 1),
524};
525
526static const struct snd_kcontrol_new rt5640_dac_r_mix[] = {
527 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5640_AD_DA_MIXER,
528 RT5640_M_ADCMIX_R_SFT, 1, 1),
529 SOC_DAPM_SINGLE("INF1 Switch", RT5640_AD_DA_MIXER,
530 RT5640_M_IF1_DAC_R_SFT, 1, 1),
531};
532
533static const struct snd_kcontrol_new rt5640_sto_dac_l_mix[] = {
534 SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_STO_DAC_MIXER,
535 RT5640_M_DAC_L1_SFT, 1, 1),
536 SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_STO_DAC_MIXER,
537 RT5640_M_DAC_L2_SFT, 1, 1),
538 SOC_DAPM_SINGLE("ANC Switch", RT5640_STO_DAC_MIXER,
539 RT5640_M_ANC_DAC_L_SFT, 1, 1),
540};
541
542static const struct snd_kcontrol_new rt5640_sto_dac_r_mix[] = {
543 SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_STO_DAC_MIXER,
544 RT5640_M_DAC_R1_SFT, 1, 1),
545 SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_STO_DAC_MIXER,
546 RT5640_M_DAC_R2_SFT, 1, 1),
547 SOC_DAPM_SINGLE("ANC Switch", RT5640_STO_DAC_MIXER,
548 RT5640_M_ANC_DAC_R_SFT, 1, 1),
549};
550
022d21f0
OC		 551static const struct snd_kcontrol_new rt5639_sto_dac_l_mix[] = {
552 SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_STO_DAC_MIXER,
553 RT5640_M_DAC_L1_SFT, 1, 1),
554 SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_STO_DAC_MIXER,
555 RT5640_M_DAC_L2_SFT, 1, 1),
556};
557
558static const struct snd_kcontrol_new rt5639_sto_dac_r_mix[] = {
559 SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_STO_DAC_MIXER,
560 RT5640_M_DAC_R1_SFT, 1, 1),
561 SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_STO_DAC_MIXER,
562 RT5640_M_DAC_R2_SFT, 1, 1),
563};
564
997b0520
BL		 565static const struct snd_kcontrol_new rt5640_mono_dac_l_mix[] = {
566 SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_MONO_DAC_MIXER,
567 RT5640_M_DAC_L1_MONO_L_SFT, 1, 1),
568 SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_MONO_DAC_MIXER,
569 RT5640_M_DAC_L2_MONO_L_SFT, 1, 1),
570 SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_MONO_DAC_MIXER,
571 RT5640_M_DAC_R2_MONO_L_SFT, 1, 1),
572};
573
574static const struct snd_kcontrol_new rt5640_mono_dac_r_mix[] = {
575 SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_MONO_DAC_MIXER,
576 RT5640_M_DAC_R1_MONO_R_SFT, 1, 1),
577 SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_MONO_DAC_MIXER,
578 RT5640_M_DAC_R2_MONO_R_SFT, 1, 1),
579 SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_MONO_DAC_MIXER,
580 RT5640_M_DAC_L2_MONO_R_SFT, 1, 1),
581};
582
583static const struct snd_kcontrol_new rt5640_dig_l_mix[] = {
584 SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_DIG_MIXER,
585 RT5640_M_STO_L_DAC_L_SFT, 1, 1),
586 SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_DIG_MIXER,
587 RT5640_M_DAC_L2_DAC_L_SFT, 1, 1),
588};
589
590static const struct snd_kcontrol_new rt5640_dig_r_mix[] = {
591 SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_DIG_MIXER,
592 RT5640_M_STO_R_DAC_R_SFT, 1, 1),
593 SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_DIG_MIXER,
594 RT5640_M_DAC_R2_DAC_R_SFT, 1, 1),
595};
596
597/* Analog Input Mixer */
598static const struct snd_kcontrol_new rt5640_rec_l_mix[] = {
599 SOC_DAPM_SINGLE("HPOL Switch", RT5640_REC_L2_MIXER,
600 RT5640_M_HP_L_RM_L_SFT, 1, 1),
601 SOC_DAPM_SINGLE("INL Switch", RT5640_REC_L2_MIXER,
602 RT5640_M_IN_L_RM_L_SFT, 1, 1),
16566e47
OC		 603 SOC_DAPM_SINGLE("BST3 Switch", RT5640_REC_L2_MIXER,
604 RT5640_M_BST2_RM_L_SFT, 1, 1),
997b0520
BL		 605 SOC_DAPM_SINGLE("BST2 Switch", RT5640_REC_L2_MIXER,
606 RT5640_M_BST4_RM_L_SFT, 1, 1),
607 SOC_DAPM_SINGLE("BST1 Switch", RT5640_REC_L2_MIXER,
608 RT5640_M_BST1_RM_L_SFT, 1, 1),
609 SOC_DAPM_SINGLE("OUT MIXL Switch", RT5640_REC_L2_MIXER,
610 RT5640_M_OM_L_RM_L_SFT, 1, 1),
611};
612
613static const struct snd_kcontrol_new rt5640_rec_r_mix[] = {
614 SOC_DAPM_SINGLE("HPOR Switch", RT5640_REC_R2_MIXER,
615 RT5640_M_HP_R_RM_R_SFT, 1, 1),
616 SOC_DAPM_SINGLE("INR Switch", RT5640_REC_R2_MIXER,
617 RT5640_M_IN_R_RM_R_SFT, 1, 1),
16566e47
OC		 618 SOC_DAPM_SINGLE("BST3 Switch", RT5640_REC_R2_MIXER,
619 RT5640_M_BST2_RM_R_SFT, 1, 1),
997b0520
BL		 620 SOC_DAPM_SINGLE("BST2 Switch", RT5640_REC_R2_MIXER,
621 RT5640_M_BST4_RM_R_SFT, 1, 1),
622 SOC_DAPM_SINGLE("BST1 Switch", RT5640_REC_R2_MIXER,
623 RT5640_M_BST1_RM_R_SFT, 1, 1),
624 SOC_DAPM_SINGLE("OUT MIXR Switch", RT5640_REC_R2_MIXER,
625 RT5640_M_OM_R_RM_R_SFT, 1, 1),
626};
627
628/* Analog Output Mixer */
629static const struct snd_kcontrol_new rt5640_spk_l_mix[] = {
630 SOC_DAPM_SINGLE("REC MIXL Switch", RT5640_SPK_L_MIXER,
631 RT5640_M_RM_L_SM_L_SFT, 1, 1),
632 SOC_DAPM_SINGLE("INL Switch", RT5640_SPK_L_MIXER,
633 RT5640_M_IN_L_SM_L_SFT, 1, 1),
634 SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_SPK_L_MIXER,
635 RT5640_M_DAC_L1_SM_L_SFT, 1, 1),
636 SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_SPK_L_MIXER,
637 RT5640_M_DAC_L2_SM_L_SFT, 1, 1),
638 SOC_DAPM_SINGLE("OUT MIXL Switch", RT5640_SPK_L_MIXER,
639 RT5640_M_OM_L_SM_L_SFT, 1, 1),
640};
641
642static const struct snd_kcontrol_new rt5640_spk_r_mix[] = {
643 SOC_DAPM_SINGLE("REC MIXR Switch", RT5640_SPK_R_MIXER,
644 RT5640_M_RM_R_SM_R_SFT, 1, 1),
645 SOC_DAPM_SINGLE("INR Switch", RT5640_SPK_R_MIXER,
646 RT5640_M_IN_R_SM_R_SFT, 1, 1),
647 SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_SPK_R_MIXER,
648 RT5640_M_DAC_R1_SM_R_SFT, 1, 1),
649 SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_SPK_R_MIXER,
650 RT5640_M_DAC_R2_SM_R_SFT, 1, 1),
651 SOC_DAPM_SINGLE("OUT MIXR Switch", RT5640_SPK_R_MIXER,
652 RT5640_M_OM_R_SM_R_SFT, 1, 1),
653};
654
655static const struct snd_kcontrol_new rt5640_out_l_mix[] = {
656 SOC_DAPM_SINGLE("SPK MIXL Switch", RT5640_OUT_L3_MIXER,
657 RT5640_M_SM_L_OM_L_SFT, 1, 1),
658 SOC_DAPM_SINGLE("BST1 Switch", RT5640_OUT_L3_MIXER,
659 RT5640_M_BST1_OM_L_SFT, 1, 1),
660 SOC_DAPM_SINGLE("INL Switch", RT5640_OUT_L3_MIXER,
661 RT5640_M_IN_L_OM_L_SFT, 1, 1),
662 SOC_DAPM_SINGLE("REC MIXL Switch", RT5640_OUT_L3_MIXER,
663 RT5640_M_RM_L_OM_L_SFT, 1, 1),
664 SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_OUT_L3_MIXER,
665 RT5640_M_DAC_R2_OM_L_SFT, 1, 1),
666 SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_OUT_L3_MIXER,
667 RT5640_M_DAC_L2_OM_L_SFT, 1, 1),
668 SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_OUT_L3_MIXER,
669 RT5640_M_DAC_L1_OM_L_SFT, 1, 1),
670};
671
672static const struct snd_kcontrol_new rt5640_out_r_mix[] = {
673 SOC_DAPM_SINGLE("SPK MIXR Switch", RT5640_OUT_R3_MIXER,
674 RT5640_M_SM_L_OM_R_SFT, 1, 1),
675 SOC_DAPM_SINGLE("BST2 Switch", RT5640_OUT_R3_MIXER,
676 RT5640_M_BST4_OM_R_SFT, 1, 1),
677 SOC_DAPM_SINGLE("BST1 Switch", RT5640_OUT_R3_MIXER,
678 RT5640_M_BST1_OM_R_SFT, 1, 1),
679 SOC_DAPM_SINGLE("INR Switch", RT5640_OUT_R3_MIXER,
680 RT5640_M_IN_R_OM_R_SFT, 1, 1),
681 SOC_DAPM_SINGLE("REC MIXR Switch", RT5640_OUT_R3_MIXER,
682 RT5640_M_RM_R_OM_R_SFT, 1, 1),
683 SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_OUT_R3_MIXER,
684 RT5640_M_DAC_L2_OM_R_SFT, 1, 1),
685 SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_OUT_R3_MIXER,
686 RT5640_M_DAC_R2_OM_R_SFT, 1, 1),
687 SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_OUT_R3_MIXER,
688 RT5640_M_DAC_R1_OM_R_SFT, 1, 1),
689};
690
022d21f0
OC		 691static const struct snd_kcontrol_new rt5639_out_l_mix[] = {
692 SOC_DAPM_SINGLE("BST1 Switch", RT5640_OUT_L3_MIXER,
693 RT5640_M_BST1_OM_L_SFT, 1, 1),
694 SOC_DAPM_SINGLE("INL Switch", RT5640_OUT_L3_MIXER,
695 RT5640_M_IN_L_OM_L_SFT, 1, 1),
696 SOC_DAPM_SINGLE("REC MIXL Switch", RT5640_OUT_L3_MIXER,
697 RT5640_M_RM_L_OM_L_SFT, 1, 1),
698 SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_OUT_L3_MIXER,
699 RT5640_M_DAC_L1_OM_L_SFT, 1, 1),
700};
701
702static const struct snd_kcontrol_new rt5639_out_r_mix[] = {
703 SOC_DAPM_SINGLE("BST2 Switch", RT5640_OUT_R3_MIXER,
704 RT5640_M_BST4_OM_R_SFT, 1, 1),
705 SOC_DAPM_SINGLE("BST1 Switch", RT5640_OUT_R3_MIXER,
706 RT5640_M_BST1_OM_R_SFT, 1, 1),
707 SOC_DAPM_SINGLE("INR Switch", RT5640_OUT_R3_MIXER,
708 RT5640_M_IN_R_OM_R_SFT, 1, 1),
709 SOC_DAPM_SINGLE("REC MIXR Switch", RT5640_OUT_R3_MIXER,
710 RT5640_M_RM_R_OM_R_SFT, 1, 1),
711 SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_OUT_R3_MIXER,
712 RT5640_M_DAC_R1_OM_R_SFT, 1, 1),
713};
714
997b0520
BL		 715static const struct snd_kcontrol_new rt5640_spo_l_mix[] = {
716 SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_SPO_L_MIXER,
717 RT5640_M_DAC_R1_SPM_L_SFT, 1, 1),
718 SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_SPO_L_MIXER,
719 RT5640_M_DAC_L1_SPM_L_SFT, 1, 1),
720 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5640_SPO_L_MIXER,
721 RT5640_M_SV_R_SPM_L_SFT, 1, 1),
722 SOC_DAPM_SINGLE("SPKVOL L Switch", RT5640_SPO_L_MIXER,
723 RT5640_M_SV_L_SPM_L_SFT, 1, 1),
724 SOC_DAPM_SINGLE("BST1 Switch", RT5640_SPO_L_MIXER,
725 RT5640_M_BST1_SPM_L_SFT, 1, 1),
726};
727
728static const struct snd_kcontrol_new rt5640_spo_r_mix[] = {
729 SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_SPO_R_MIXER,
730 RT5640_M_DAC_R1_SPM_R_SFT, 1, 1),
731 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5640_SPO_R_MIXER,
732 RT5640_M_SV_R_SPM_R_SFT, 1, 1),
733 SOC_DAPM_SINGLE("BST1 Switch", RT5640_SPO_R_MIXER,
734 RT5640_M_BST1_SPM_R_SFT, 1, 1),
735};
736
737static const struct snd_kcontrol_new rt5640_hpo_mix[] = {
738 SOC_DAPM_SINGLE("HPO MIX DAC2 Switch", RT5640_HPO_MIXER,
739 RT5640_M_DAC2_HM_SFT, 1, 1),
740 SOC_DAPM_SINGLE("HPO MIX DAC1 Switch", RT5640_HPO_MIXER,
741 RT5640_M_DAC1_HM_SFT, 1, 1),
742 SOC_DAPM_SINGLE("HPO MIX HPVOL Switch", RT5640_HPO_MIXER,
743 RT5640_M_HPVOL_HM_SFT, 1, 1),
744};
745
022d21f0
OC		 746static const struct snd_kcontrol_new rt5639_hpo_mix[] = {
747 SOC_DAPM_SINGLE("HPO MIX DAC1 Switch", RT5640_HPO_MIXER,
748 RT5640_M_DAC1_HM_SFT, 1, 1),
749 SOC_DAPM_SINGLE("HPO MIX HPVOL Switch", RT5640_HPO_MIXER,
750 RT5640_M_HPVOL_HM_SFT, 1, 1),
751};
752
997b0520
BL		 753static const struct snd_kcontrol_new rt5640_lout_mix[] = {
754 SOC_DAPM_SINGLE("DAC L1 Switch", RT5640_LOUT_MIXER,
755 RT5640_M_DAC_L1_LM_SFT, 1, 1),
756 SOC_DAPM_SINGLE("DAC R1 Switch", RT5640_LOUT_MIXER,
757 RT5640_M_DAC_R1_LM_SFT, 1, 1),
758 SOC_DAPM_SINGLE("OUTVOL L Switch", RT5640_LOUT_MIXER,
759 RT5640_M_OV_L_LM_SFT, 1, 1),
760 SOC_DAPM_SINGLE("OUTVOL R Switch", RT5640_LOUT_MIXER,
761 RT5640_M_OV_R_LM_SFT, 1, 1),
762};
763
764static const struct snd_kcontrol_new rt5640_mono_mix[] = {
765 SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_MONO_MIXER,
766 RT5640_M_DAC_R2_MM_SFT, 1, 1),
767 SOC_DAPM_SINGLE("DAC L2 Switch", RT5640_MONO_MIXER,
768 RT5640_M_DAC_L2_MM_SFT, 1, 1),
769 SOC_DAPM_SINGLE("OUTVOL R Switch", RT5640_MONO_MIXER,
770 RT5640_M_OV_R_MM_SFT, 1, 1),
771 SOC_DAPM_SINGLE("OUTVOL L Switch", RT5640_MONO_MIXER,
772 RT5640_M_OV_L_MM_SFT, 1, 1),
773 SOC_DAPM_SINGLE("BST1 Switch", RT5640_MONO_MIXER,
774 RT5640_M_BST1_MM_SFT, 1, 1),
775};
776
246693ba
BL		 777static const struct snd_kcontrol_new spk_l_enable_control =
778 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5640_SPK_VOL,
779 RT5640_L_MUTE_SFT, 1, 1);
780
781static const struct snd_kcontrol_new spk_r_enable_control =
782 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5640_SPK_VOL,
783 RT5640_R_MUTE_SFT, 1, 1);
784
785static const struct snd_kcontrol_new hp_l_enable_control =
786 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5640_HP_VOL,
787 RT5640_L_MUTE_SFT, 1, 1);
788
789static const struct snd_kcontrol_new hp_r_enable_control =
790 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5640_HP_VOL,
791 RT5640_R_MUTE_SFT, 1, 1);
792
997b0520
BL		 793/* Stereo ADC source */
794static const char * const rt5640_stereo_adc1_src[] = {
795 "DIG MIX", "ADC"
796};
797
4c03cb6f
TI		 798static SOC_ENUM_SINGLE_DECL(rt5640_stereo_adc1_enum, RT5640_STO_ADC_MIXER,
799 RT5640_ADC_1_SRC_SFT, rt5640_stereo_adc1_src);
997b0520
BL		 800
801static const struct snd_kcontrol_new rt5640_sto_adc_1_mux =
802 SOC_DAPM_ENUM("Stereo ADC1 Mux", rt5640_stereo_adc1_enum);
803
804static const char * const rt5640_stereo_adc2_src[] = {
805 "DMIC1", "DMIC2", "DIG MIX"
806};
807
4c03cb6f
TI		 808static SOC_ENUM_SINGLE_DECL(rt5640_stereo_adc2_enum, RT5640_STO_ADC_MIXER,
809 RT5640_ADC_2_SRC_SFT, rt5640_stereo_adc2_src);
997b0520
BL		 810
811static const struct snd_kcontrol_new rt5640_sto_adc_2_mux =
812 SOC_DAPM_ENUM("Stereo ADC2 Mux", rt5640_stereo_adc2_enum);
813
814/* Mono ADC source */
815static const char * const rt5640_mono_adc_l1_src[] = {
816 "Mono DAC MIXL", "ADCL"
817};
818
4c03cb6f
TI		 819static SOC_ENUM_SINGLE_DECL(rt5640_mono_adc_l1_enum, RT5640_MONO_ADC_MIXER,
820 RT5640_MONO_ADC_L1_SRC_SFT, rt5640_mono_adc_l1_src);
997b0520
BL		 821
822static const struct snd_kcontrol_new rt5640_mono_adc_l1_mux =
823 SOC_DAPM_ENUM("Mono ADC1 left source", rt5640_mono_adc_l1_enum);
824
825static const char * const rt5640_mono_adc_l2_src[] = {
826 "DMIC L1", "DMIC L2", "Mono DAC MIXL"
827};
828
4c03cb6f
TI		 829static SOC_ENUM_SINGLE_DECL(rt5640_mono_adc_l2_enum, RT5640_MONO_ADC_MIXER,
830 RT5640_MONO_ADC_L2_SRC_SFT, rt5640_mono_adc_l2_src);
997b0520
BL		 831
832static const struct snd_kcontrol_new rt5640_mono_adc_l2_mux =
833 SOC_DAPM_ENUM("Mono ADC2 left source", rt5640_mono_adc_l2_enum);
834
835static const char * const rt5640_mono_adc_r1_src[] = {
836 "Mono DAC MIXR", "ADCR"
837};
838
4c03cb6f
TI		 839static SOC_ENUM_SINGLE_DECL(rt5640_mono_adc_r1_enum, RT5640_MONO_ADC_MIXER,
840 RT5640_MONO_ADC_R1_SRC_SFT, rt5640_mono_adc_r1_src);
997b0520
BL		 841
842static const struct snd_kcontrol_new rt5640_mono_adc_r1_mux =
843 SOC_DAPM_ENUM("Mono ADC1 right source", rt5640_mono_adc_r1_enum);
844
845static const char * const rt5640_mono_adc_r2_src[] = {
846 "DMIC R1", "DMIC R2", "Mono DAC MIXR"
847};
848
4c03cb6f
TI		 849static SOC_ENUM_SINGLE_DECL(rt5640_mono_adc_r2_enum, RT5640_MONO_ADC_MIXER,
850 RT5640_MONO_ADC_R2_SRC_SFT, rt5640_mono_adc_r2_src);
997b0520
BL		 851
852static const struct snd_kcontrol_new rt5640_mono_adc_r2_mux =
853 SOC_DAPM_ENUM("Mono ADC2 right source", rt5640_mono_adc_r2_enum);
854
855/* DAC2 channel source */
856static const char * const rt5640_dac_l2_src[] = {
857 "IF2", "Base L/R"
858};
859
860static int rt5640_dac_l2_values[] = {
861 0,
862 3,
863};
864
4c03cb6f
TI		 865static SOC_VALUE_ENUM_SINGLE_DECL(rt5640_dac_l2_enum,
866 RT5640_DSP_PATH2, RT5640_DAC_L2_SEL_SFT,
867 0x3, rt5640_dac_l2_src, rt5640_dac_l2_values);
997b0520
BL		 868
869static const struct snd_kcontrol_new rt5640_dac_l2_mux =
712fb1c2 870 SOC_DAPM_ENUM("DAC2 left channel source", rt5640_dac_l2_enum);
997b0520
BL		 871
872static const char * const rt5640_dac_r2_src[] = {
873 "IF2",
874};
875
876static int rt5640_dac_r2_values[] = {
877 0,
878};
879
4c03cb6f
TI		 880static SOC_VALUE_ENUM_SINGLE_DECL(rt5640_dac_r2_enum,
881 RT5640_DSP_PATH2, RT5640_DAC_R2_SEL_SFT,
882 0x3, rt5640_dac_r2_src, rt5640_dac_r2_values);
997b0520
BL		 883
884static const struct snd_kcontrol_new rt5640_dac_r2_mux =
885 SOC_DAPM_ENUM("DAC2 right channel source", rt5640_dac_r2_enum);
886
887/* digital interface and iis interface map */
888static const char * const rt5640_dai_iis_map[] = {
889 "1:1|2:2", "1:2|2:1", "1:1|2:1", "1:2|2:2"
890};
891
892static int rt5640_dai_iis_map_values[] = {
893 0,
894 5,
895 6,
896 7,
897};
898
4c03cb6f
TI		 899static SOC_VALUE_ENUM_SINGLE_DECL(rt5640_dai_iis_map_enum,
900 RT5640_I2S1_SDP, RT5640_I2S_IF_SFT,
901 0x7, rt5640_dai_iis_map,
902 rt5640_dai_iis_map_values);
997b0520
BL		 903
904static const struct snd_kcontrol_new rt5640_dai_mux =
712fb1c2 905 SOC_DAPM_ENUM("DAI select", rt5640_dai_iis_map_enum);
997b0520
BL		 906
907/* SDI select */
908static const char * const rt5640_sdi_sel[] = {
909 "IF1", "IF2"
910};
911
4c03cb6f
TI		 912static SOC_ENUM_SINGLE_DECL(rt5640_sdi_sel_enum, RT5640_I2S2_SDP,
913 RT5640_I2S2_SDI_SFT, rt5640_sdi_sel);
997b0520
BL		 914
915static const struct snd_kcontrol_new rt5640_sdi_mux =
916 SOC_DAPM_ENUM("SDI select", rt5640_sdi_sel_enum);
917
d5a41b5d 918static void hp_amp_power_on(struct snd_soc_component *component)
246693ba 919{
d5a41b5d 920 struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
246693ba
BL		 921
922 /* depop parameters */
923 regmap_update_bits(rt5640->regmap, RT5640_PR_BASE +
924 RT5640_CHPUMP_INT_REG1, 0x0700, 0x0200);
925 regmap_update_bits(rt5640->regmap, RT5640_DEPOP_M2,
926 RT5640_DEPOP_MASK, RT5640_DEPOP_MAN);
927 regmap_update_bits(rt5640->regmap, RT5640_DEPOP_M1,
928 RT5640_HP_CP_MASK | RT5640_HP_SG_MASK | RT5640_HP_CB_MASK,
929 RT5640_HP_CP_PU | RT5640_HP_SG_DIS | RT5640_HP_CB_PU);
930 regmap_write(rt5640->regmap, RT5640_PR_BASE + RT5640_HP_DCC_INT1,
931 0x9f00);
932 /* headphone amp power on */
933 regmap_update_bits(rt5640->regmap, RT5640_PWR_ANLG1,
934 RT5640_PWR_FV1 | RT5640_PWR_FV2, 0);
935 regmap_update_bits(rt5640->regmap, RT5640_PWR_ANLG1,
936 RT5640_PWR_HA,
937 RT5640_PWR_HA);
938 usleep_range(10000, 15000);
939 regmap_update_bits(rt5640->regmap, RT5640_PWR_ANLG1,
940 RT5640_PWR_FV1 | RT5640_PWR_FV2 ,
941 RT5640_PWR_FV1 | RT5640_PWR_FV2);
942}
943
d5a41b5d 944static void rt5640_pmu_depop(struct snd_soc_component *component)
246693ba 945{
d5a41b5d 946 struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
246693ba
BL		 947
948 regmap_update_bits(rt5640->regmap, RT5640_DEPOP_M2,
949 RT5640_DEPOP_MASK | RT5640_DIG_DP_MASK,
950 RT5640_DEPOP_AUTO | RT5640_DIG_DP_EN);
951 regmap_update_bits(rt5640->regmap, RT5640_CHARGE_PUMP,
952 RT5640_PM_HP_MASK, RT5640_PM_HP_HV);
953
954 regmap_update_bits(rt5640->regmap, RT5640_DEPOP_M3,
955 RT5640_CP_FQ1_MASK | RT5640_CP_FQ2_MASK | RT5640_CP_FQ3_MASK,
956 (RT5640_CP_FQ_192_KHZ << RT5640_CP_FQ1_SFT) |
957 (RT5640_CP_FQ_12_KHZ << RT5640_CP_FQ2_SFT) |
958 (RT5640_CP_FQ_192_KHZ << RT5640_CP_FQ3_SFT));
959
960 regmap_write(rt5640->regmap, RT5640_PR_BASE +
961 RT5640_MAMP_INT_REG2, 0x1c00);
962 regmap_update_bits(rt5640->regmap, RT5640_DEPOP_M1,
963 RT5640_HP_CP_MASK | RT5640_HP_SG_MASK,
964 RT5640_HP_CP_PD | RT5640_HP_SG_EN);
965 regmap_update_bits(rt5640->regmap, RT5640_PR_BASE +
966 RT5640_CHPUMP_INT_REG1, 0x0700, 0x0400);
967}
968
969static int rt5640_hp_event(struct snd_soc_dapm_widget *w,
970 struct snd_kcontrol *kcontrol, int event)
971{
d5a41b5d
KM		 972 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
973 struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
246693ba
BL		 974
975 switch (event) {
976 case SND_SOC_DAPM_POST_PMU:
d5a41b5d 977 rt5640_pmu_depop(component);
e0a99927 978 rt5640->hp_mute = false;
246693ba
BL		 979 break;
980
981 case SND_SOC_DAPM_PRE_PMD:
e0a99927 982 rt5640->hp_mute = true;
4a312c9c 983 msleep(70);
246693ba
BL		 984 break;
985
986 default:
987 return 0;
988 }
989
990 return 0;
991}
992
9b850ca4
JL		 993static int rt5640_lout_event(struct snd_soc_dapm_widget *w,
994 struct snd_kcontrol *kcontrol, int event)
995{
d5a41b5d 996 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
9b850ca4
JL		 997
998 switch (event) {
999 case SND_SOC_DAPM_POST_PMU:
d5a41b5d
KM		 1000 hp_amp_power_on(component);
1001 snd_soc_component_update_bits(component, RT5640_PWR_ANLG1,
9b850ca4 1002 RT5640_PWR_LM, RT5640_PWR_LM);
d5a41b5d 1003 snd_soc_component_update_bits(component, RT5640_OUTPUT,
9b850ca4
JL		 1004 RT5640_L_MUTE | RT5640_R_MUTE, 0);
1005 break;
1006
1007 case SND_SOC_DAPM_PRE_PMD:
d5a41b5d 1008 snd_soc_component_update_bits(component, RT5640_OUTPUT,
9b850ca4
JL		 1009 RT5640_L_MUTE | RT5640_R_MUTE,
1010 RT5640_L_MUTE | RT5640_R_MUTE);
d5a41b5d 1011 snd_soc_component_update_bits(component, RT5640_PWR_ANLG1,
9b850ca4
JL		 1012 RT5640_PWR_LM, 0);
1013 break;
1014
1015 default:
1016 return 0;
1017 }
1018
1019 return 0;
1020}
1021
246693ba
BL		 1022static int rt5640_hp_power_event(struct snd_soc_dapm_widget *w,
1023 struct snd_kcontrol *kcontrol, int event)
1024{
d5a41b5d 1025 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
246693ba
BL		 1026
1027 switch (event) {
1028 case SND_SOC_DAPM_POST_PMU:
d5a41b5d 1029 hp_amp_power_on(component);
246693ba
BL		 1030 break;
1031 default:
1032 return 0;
1033 }
1034
1035 return 0;
1036}
1037
1038static int rt5640_hp_post_event(struct snd_soc_dapm_widget *w,
1039 struct snd_kcontrol *kcontrol, int event)
1040{
d5a41b5d
KM		 1041 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1042 struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
246693ba
BL		 1043
1044 switch (event) {
1045 case SND_SOC_DAPM_POST_PMU:
1046 if (!rt5640->hp_mute)
4a312c9c 1047 msleep(80);
246693ba
BL		 1048
1049 break;
1050
1051 default:
1052 return 0;
1053 }
1054
1055 return 0;
1056}
1057
997b0520 1058static const struct snd_soc_dapm_widget rt5640_dapm_widgets[] = {
bee3e020
JY		 1059 /* ASRC */
1060 SND_SOC_DAPM_SUPPLY_S("Stereo Filter ASRC", 1, RT5640_ASRC_1,
1061 15, 0, NULL, 0),
1062 SND_SOC_DAPM_SUPPLY_S("I2S2 Filter ASRC", 1, RT5640_ASRC_1,
1063 12, 0, NULL, 0),
1064 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5640_ASRC_1,
1065 11, 0, NULL, 0),
1066 SND_SOC_DAPM_SUPPLY_S("DMIC1 ASRC", 1, RT5640_ASRC_1,
1067 9, 0, NULL, 0),
1068 SND_SOC_DAPM_SUPPLY_S("DMIC2 ASRC", 1, RT5640_ASRC_1,
1069 8, 0, NULL, 0),
1070
1071
997b0520
BL		 1072 /* Input Side */
1073 /* micbias */
1074 SND_SOC_DAPM_SUPPLY("LDO2", RT5640_PWR_ANLG1,
1075 RT5640_PWR_LDO2_BIT, 0, NULL, 0),
1076 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5640_PWR_ANLG2,
9be94aea 1077 RT5640_PWR_MB1_BIT, 0, NULL, 0),
997b0520
BL		 1078 /* Input Lines */
1079 SND_SOC_DAPM_INPUT("DMIC1"),
1080 SND_SOC_DAPM_INPUT("DMIC2"),
1081 SND_SOC_DAPM_INPUT("IN1P"),
1082 SND_SOC_DAPM_INPUT("IN1N"),
1083 SND_SOC_DAPM_INPUT("IN2P"),
1084 SND_SOC_DAPM_INPUT("IN2N"),
16566e47
OC		 1085 SND_SOC_DAPM_INPUT("IN3P"),
1086 SND_SOC_DAPM_INPUT("IN3N"),
997b0520
BL		 1087 SND_SOC_DAPM_PGA("DMIC L1", SND_SOC_NOPM, 0, 0, NULL, 0),
1088 SND_SOC_DAPM_PGA("DMIC R1", SND_SOC_NOPM, 0, 0, NULL, 0),
1089 SND_SOC_DAPM_PGA("DMIC L2", SND_SOC_NOPM, 0, 0, NULL, 0),
1090 SND_SOC_DAPM_PGA("DMIC R2", SND_SOC_NOPM, 0, 0, NULL, 0),
1091
1092 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1093 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
71d97a79
OC		 1094 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5640_DMIC, RT5640_DMIC_1_EN_SFT, 0,
1095 NULL, 0),
1096 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5640_DMIC, RT5640_DMIC_2_EN_SFT, 0,
1097 NULL, 0),
997b0520
BL		 1098 /* Boost */
1099 SND_SOC_DAPM_PGA("BST1", RT5640_PWR_ANLG2,
1100 RT5640_PWR_BST1_BIT, 0, NULL, 0),
1101 SND_SOC_DAPM_PGA("BST2", RT5640_PWR_ANLG2,
1102 RT5640_PWR_BST4_BIT, 0, NULL, 0),
16566e47
OC		 1103 SND_SOC_DAPM_PGA("BST3", RT5640_PWR_ANLG2,
1104 RT5640_PWR_BST2_BIT, 0, NULL, 0),
997b0520
BL		 1105 /* Input Volume */
1106 SND_SOC_DAPM_PGA("INL VOL", RT5640_PWR_VOL,
1107 RT5640_PWR_IN_L_BIT, 0, NULL, 0),
1108 SND_SOC_DAPM_PGA("INR VOL", RT5640_PWR_VOL,
1109 RT5640_PWR_IN_R_BIT, 0, NULL, 0),
997b0520
BL		 1110 /* REC Mixer */
1111 SND_SOC_DAPM_MIXER("RECMIXL", RT5640_PWR_MIXER, RT5640_PWR_RM_L_BIT, 0,
1112 rt5640_rec_l_mix, ARRAY_SIZE(rt5640_rec_l_mix)),
1113 SND_SOC_DAPM_MIXER("RECMIXR", RT5640_PWR_MIXER, RT5640_PWR_RM_R_BIT, 0,
1114 rt5640_rec_r_mix, ARRAY_SIZE(rt5640_rec_r_mix)),
1115 /* ADCs */
1116 SND_SOC_DAPM_ADC("ADC L", NULL, RT5640_PWR_DIG1,
1117 RT5640_PWR_ADC_L_BIT, 0),
1118 SND_SOC_DAPM_ADC("ADC R", NULL, RT5640_PWR_DIG1,
1119 RT5640_PWR_ADC_R_BIT, 0),
1120 /* ADC Mux */
1121 SND_SOC_DAPM_MUX("Stereo ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1122 &rt5640_sto_adc_2_mux),
1123 SND_SOC_DAPM_MUX("Stereo ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1124 &rt5640_sto_adc_2_mux),
1125 SND_SOC_DAPM_MUX("Stereo ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1126 &rt5640_sto_adc_1_mux),
1127 SND_SOC_DAPM_MUX("Stereo ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1128 &rt5640_sto_adc_1_mux),
1129 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1130 &rt5640_mono_adc_l2_mux),
1131 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1132 &rt5640_mono_adc_l1_mux),
1133 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1134 &rt5640_mono_adc_r1_mux),
1135 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1136 &rt5640_mono_adc_r2_mux),
1137 /* ADC Mixer */
1138 SND_SOC_DAPM_SUPPLY("Stereo Filter", RT5640_PWR_DIG2,
1139 RT5640_PWR_ADC_SF_BIT, 0, NULL, 0),
1140 SND_SOC_DAPM_MIXER("Stereo ADC MIXL", SND_SOC_NOPM, 0, 0,
1141 rt5640_sto_adc_l_mix, ARRAY_SIZE(rt5640_sto_adc_l_mix)),
1142 SND_SOC_DAPM_MIXER("Stereo ADC MIXR", SND_SOC_NOPM, 0, 0,
1143 rt5640_sto_adc_r_mix, ARRAY_SIZE(rt5640_sto_adc_r_mix)),
1144 SND_SOC_DAPM_SUPPLY("Mono Left Filter", RT5640_PWR_DIG2,
1145 RT5640_PWR_ADC_MF_L_BIT, 0, NULL, 0),
1146 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
1147 rt5640_mono_adc_l_mix, ARRAY_SIZE(rt5640_mono_adc_l_mix)),
1148 SND_SOC_DAPM_SUPPLY("Mono Right Filter", RT5640_PWR_DIG2,
1149 RT5640_PWR_ADC_MF_R_BIT, 0, NULL, 0),
1150 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
1151 rt5640_mono_adc_r_mix, ARRAY_SIZE(rt5640_mono_adc_r_mix)),
1152
1153 /* Digital Interface */
1154 SND_SOC_DAPM_SUPPLY("I2S1", RT5640_PWR_DIG1,
1155 RT5640_PWR_I2S1_BIT, 0, NULL, 0),
1156 SND_SOC_DAPM_PGA("IF1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1157 SND_SOC_DAPM_PGA("IF1 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1158 SND_SOC_DAPM_PGA("IF1 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1159 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1160 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1161 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1162 SND_SOC_DAPM_SUPPLY("I2S2", RT5640_PWR_DIG1,
1163 RT5640_PWR_I2S2_BIT, 0, NULL, 0),
1164 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1165 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1166 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1167 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1168 SND_SOC_DAPM_PGA("IF2 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1169 SND_SOC_DAPM_PGA("IF2 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1170 /* Digital Interface Select */
1171 SND_SOC_DAPM_MUX("DAI1 RX Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
1172 SND_SOC_DAPM_MUX("DAI1 TX Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
1173 SND_SOC_DAPM_MUX("DAI1 IF1 Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
1174 SND_SOC_DAPM_MUX("DAI1 IF2 Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
1175 SND_SOC_DAPM_MUX("SDI1 TX Mux", SND_SOC_NOPM, 0, 0, &rt5640_sdi_mux),
1176 SND_SOC_DAPM_MUX("DAI2 RX Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
1177 SND_SOC_DAPM_MUX("DAI2 TX Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
1178 SND_SOC_DAPM_MUX("DAI2 IF1 Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
1179 SND_SOC_DAPM_MUX("DAI2 IF2 Mux", SND_SOC_NOPM, 0, 0, &rt5640_dai_mux),
1180 SND_SOC_DAPM_MUX("SDI2 TX Mux", SND_SOC_NOPM, 0, 0, &rt5640_sdi_mux),
1181 /* Audio Interface */
1182 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1183 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1184 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1185 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
022d21f0 1186
997b0520
BL		 1187 /* Output Side */
1188 /* DAC mixer before sound effect */
1189 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
1190 rt5640_dac_l_mix, ARRAY_SIZE(rt5640_dac_l_mix)),
1191 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
1192 rt5640_dac_r_mix, ARRAY_SIZE(rt5640_dac_r_mix)),
022d21f0 1193
997b0520 1194 /* DAC Mixer */
997b0520
BL		 1195 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
1196 rt5640_mono_dac_l_mix, ARRAY_SIZE(rt5640_mono_dac_l_mix)),
1197 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
1198 rt5640_mono_dac_r_mix, ARRAY_SIZE(rt5640_mono_dac_r_mix)),
1199 SND_SOC_DAPM_MIXER("DIG MIXL", SND_SOC_NOPM, 0, 0,
1200 rt5640_dig_l_mix, ARRAY_SIZE(rt5640_dig_l_mix)),
1201 SND_SOC_DAPM_MIXER("DIG MIXR", SND_SOC_NOPM, 0, 0,
1202 rt5640_dig_r_mix, ARRAY_SIZE(rt5640_dig_r_mix)),
1203 /* DACs */
57586fb7
BL		 1204 SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM,
1205 0, 0),
1206 SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM,
1207 0, 0),
1208 SND_SOC_DAPM_SUPPLY("DAC L1 Power", RT5640_PWR_DIG1,
1209 RT5640_PWR_DAC_L1_BIT, 0, NULL, 0),
1210 SND_SOC_DAPM_SUPPLY("DAC R1 Power", RT5640_PWR_DIG1,
1211 RT5640_PWR_DAC_R1_BIT, 0, NULL, 0),
80317c2c
BL		 1212 SND_SOC_DAPM_SUPPLY("DAC L2 Power", RT5640_PWR_DIG1,
1213 RT5640_PWR_DAC_L2_BIT, 0, NULL, 0),
1214 SND_SOC_DAPM_SUPPLY("DAC R2 Power", RT5640_PWR_DIG1,
1215 RT5640_PWR_DAC_R2_BIT, 0, NULL, 0),
997b0520
BL		 1216 /* SPK/OUT Mixer */
1217 SND_SOC_DAPM_MIXER("SPK MIXL", RT5640_PWR_MIXER, RT5640_PWR_SM_L_BIT,
1218 0, rt5640_spk_l_mix, ARRAY_SIZE(rt5640_spk_l_mix)),
1219 SND_SOC_DAPM_MIXER("SPK MIXR", RT5640_PWR_MIXER, RT5640_PWR_SM_R_BIT,
1220 0, rt5640_spk_r_mix, ARRAY_SIZE(rt5640_spk_r_mix)),
997b0520
BL		 1221 /* Ouput Volume */
1222 SND_SOC_DAPM_PGA("SPKVOL L", RT5640_PWR_VOL,
1223 RT5640_PWR_SV_L_BIT, 0, NULL, 0),
1224 SND_SOC_DAPM_PGA("SPKVOL R", RT5640_PWR_VOL,
1225 RT5640_PWR_SV_R_BIT, 0, NULL, 0),
1226 SND_SOC_DAPM_PGA("OUTVOL L", RT5640_PWR_VOL,
1227 RT5640_PWR_OV_L_BIT, 0, NULL, 0),
1228 SND_SOC_DAPM_PGA("OUTVOL R", RT5640_PWR_VOL,
1229 RT5640_PWR_OV_R_BIT, 0, NULL, 0),
1230 SND_SOC_DAPM_PGA("HPOVOL L", RT5640_PWR_VOL,
1231 RT5640_PWR_HV_L_BIT, 0, NULL, 0),
1232 SND_SOC_DAPM_PGA("HPOVOL R", RT5640_PWR_VOL,
1233 RT5640_PWR_HV_R_BIT, 0, NULL, 0),
1234 /* SPO/HPO/LOUT/Mono Mixer */
1235 SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0,
1236 0, rt5640_spo_l_mix, ARRAY_SIZE(rt5640_spo_l_mix)),
1237 SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0,
1238 0, rt5640_spo_r_mix, ARRAY_SIZE(rt5640_spo_r_mix)),
9b850ca4 1239 SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0,
997b0520 1240 rt5640_lout_mix, ARRAY_SIZE(rt5640_lout_mix)),
246693ba
BL		 1241 SND_SOC_DAPM_SUPPLY_S("Improve HP Amp Drv", 1, SND_SOC_NOPM,
1242 0, 0, rt5640_hp_power_event, SND_SOC_DAPM_POST_PMU),
1243 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0,
1244 rt5640_hp_event,
1245 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
9b850ca4
JL		 1246 SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0,
1247 rt5640_lout_event,
1248 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
246693ba 1249 SND_SOC_DAPM_SUPPLY("HP L Amp", RT5640_PWR_ANLG1,
997b0520 1250 RT5640_PWR_HP_L_BIT, 0, NULL, 0),
246693ba 1251 SND_SOC_DAPM_SUPPLY("HP R Amp", RT5640_PWR_ANLG1,
997b0520
BL		 1252 RT5640_PWR_HP_R_BIT, 0, NULL, 0),
1253 SND_SOC_DAPM_SUPPLY("Improve SPK Amp Drv", RT5640_PWR_DIG1,
246693ba
BL		 1254 RT5640_PWR_CLS_D_BIT, 0, NULL, 0),
1255
1256 /* Output Switch */
1257 SND_SOC_DAPM_SWITCH("Speaker L Playback", SND_SOC_NOPM, 0, 0,
1258 &spk_l_enable_control),
1259 SND_SOC_DAPM_SWITCH("Speaker R Playback", SND_SOC_NOPM, 0, 0,
1260 &spk_r_enable_control),
1261 SND_SOC_DAPM_SWITCH("HP L Playback", SND_SOC_NOPM, 0, 0,
1262 &hp_l_enable_control),
1263 SND_SOC_DAPM_SWITCH("HP R Playback", SND_SOC_NOPM, 0, 0,
1264 &hp_r_enable_control),
1265 SND_SOC_DAPM_POST("HP Post", rt5640_hp_post_event),
997b0520
BL		 1266 /* Output Lines */
1267 SND_SOC_DAPM_OUTPUT("SPOLP"),
1268 SND_SOC_DAPM_OUTPUT("SPOLN"),
1269 SND_SOC_DAPM_OUTPUT("SPORP"),
1270 SND_SOC_DAPM_OUTPUT("SPORN"),
1271 SND_SOC_DAPM_OUTPUT("HPOL"),
1272 SND_SOC_DAPM_OUTPUT("HPOR"),
1273 SND_SOC_DAPM_OUTPUT("LOUTL"),
1274 SND_SOC_DAPM_OUTPUT("LOUTR"),
022d21f0
OC		 1275};
1276
1277static const struct snd_soc_dapm_widget rt5640_specific_dapm_widgets[] = {
1278 /* Audio DSP */
1279 SND_SOC_DAPM_PGA("Audio DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
1280 /* ANC */
1281 SND_SOC_DAPM_PGA("ANC", SND_SOC_NOPM, 0, 0, NULL, 0),
1282
1283 /* DAC2 channel Mux */
1284 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5640_dac_l2_mux),
1285 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5640_dac_r2_mux),
1286
1287 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
1288 rt5640_sto_dac_l_mix, ARRAY_SIZE(rt5640_sto_dac_l_mix)),
1289 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
1290 rt5640_sto_dac_r_mix, ARRAY_SIZE(rt5640_sto_dac_r_mix)),
1291
57586fb7 1292 SND_SOC_DAPM_DAC("DAC R2", NULL, SND_SOC_NOPM, 0,
022d21f0 1293 0),
57586fb7 1294 SND_SOC_DAPM_DAC("DAC L2", NULL, SND_SOC_NOPM, 0,
022d21f0
OC		 1295 0),
1296
1297 SND_SOC_DAPM_MIXER("OUT MIXL", RT5640_PWR_MIXER, RT5640_PWR_OM_L_BIT,
1298 0, rt5640_out_l_mix, ARRAY_SIZE(rt5640_out_l_mix)),
1299 SND_SOC_DAPM_MIXER("OUT MIXR", RT5640_PWR_MIXER, RT5640_PWR_OM_R_BIT,
1300 0, rt5640_out_r_mix, ARRAY_SIZE(rt5640_out_r_mix)),
1301
1302 SND_SOC_DAPM_MIXER("HPO MIX L", SND_SOC_NOPM, 0, 0,
1303 rt5640_hpo_mix, ARRAY_SIZE(rt5640_hpo_mix)),
1304 SND_SOC_DAPM_MIXER("HPO MIX R", SND_SOC_NOPM, 0, 0,
1305 rt5640_hpo_mix, ARRAY_SIZE(rt5640_hpo_mix)),
1306
1307 SND_SOC_DAPM_MIXER("Mono MIX", RT5640_PWR_ANLG1, RT5640_PWR_MM_BIT, 0,
1308 rt5640_mono_mix, ARRAY_SIZE(rt5640_mono_mix)),
1309 SND_SOC_DAPM_SUPPLY("Improve MONO Amp Drv", RT5640_PWR_ANLG1,
1310 RT5640_PWR_MA_BIT, 0, NULL, 0),
1311
997b0520
BL		 1312 SND_SOC_DAPM_OUTPUT("MONOP"),
1313 SND_SOC_DAPM_OUTPUT("MONON"),
1314};
1315
022d21f0
OC		 1316static const struct snd_soc_dapm_widget rt5639_specific_dapm_widgets[] = {
1317 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
1318 rt5639_sto_dac_l_mix, ARRAY_SIZE(rt5639_sto_dac_l_mix)),
1319 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
1320 rt5639_sto_dac_r_mix, ARRAY_SIZE(rt5639_sto_dac_r_mix)),
1321
022d21f0
OC		 1322 SND_SOC_DAPM_MIXER("OUT MIXL", RT5640_PWR_MIXER, RT5640_PWR_OM_L_BIT,
1323 0, rt5639_out_l_mix, ARRAY_SIZE(rt5639_out_l_mix)),
1324 SND_SOC_DAPM_MIXER("OUT MIXR", RT5640_PWR_MIXER, RT5640_PWR_OM_R_BIT,
1325 0, rt5639_out_r_mix, ARRAY_SIZE(rt5639_out_r_mix)),
1326
1327 SND_SOC_DAPM_MIXER("HPO MIX L", SND_SOC_NOPM, 0, 0,
1328 rt5639_hpo_mix, ARRAY_SIZE(rt5639_hpo_mix)),
1329 SND_SOC_DAPM_MIXER("HPO MIX R", SND_SOC_NOPM, 0, 0,
1330 rt5639_hpo_mix, ARRAY_SIZE(rt5639_hpo_mix)),
1331};
1332
997b0520 1333static const struct snd_soc_dapm_route rt5640_dapm_routes[] = {
bee3e020
JY		 1334 { "I2S1", NULL, "Stereo Filter ASRC", is_using_asrc },
1335 { "I2S2", NULL, "I2S2 ASRC", is_using_asrc },
1336 { "I2S2", NULL, "I2S2 Filter ASRC", is_using_asrc },
1337 { "DMIC1", NULL, "DMIC1 ASRC", is_using_asrc },
1338 { "DMIC2", NULL, "DMIC2 ASRC", is_using_asrc },
1339
997b0520
BL		 1340 {"IN1P", NULL, "LDO2"},
1341 {"IN2P", NULL, "LDO2"},
16566e47 1342 {"IN3P", NULL, "LDO2"},
997b0520
BL		 1343
1344 {"DMIC L1", NULL, "DMIC1"},
1345 {"DMIC R1", NULL, "DMIC1"},
1346 {"DMIC L2", NULL, "DMIC2"},
1347 {"DMIC R2", NULL, "DMIC2"},
1348
1349 {"BST1", NULL, "IN1P"},
1350 {"BST1", NULL, "IN1N"},
1351 {"BST2", NULL, "IN2P"},
1352 {"BST2", NULL, "IN2N"},
16566e47
OC		 1353 {"BST3", NULL, "IN3P"},
1354 {"BST3", NULL, "IN3N"},
997b0520
BL		 1355
1356 {"INL VOL", NULL, "IN2P"},
1357 {"INR VOL", NULL, "IN2N"},
1358
1359 {"RECMIXL", "HPOL Switch", "HPOL"},
1360 {"RECMIXL", "INL Switch", "INL VOL"},
16566e47 1361 {"RECMIXL", "BST3 Switch", "BST3"},
997b0520
BL		 1362 {"RECMIXL", "BST2 Switch", "BST2"},
1363 {"RECMIXL", "BST1 Switch", "BST1"},
1364 {"RECMIXL", "OUT MIXL Switch", "OUT MIXL"},
1365
1366 {"RECMIXR", "HPOR Switch", "HPOR"},
1367 {"RECMIXR", "INR Switch", "INR VOL"},
16566e47 1368 {"RECMIXR", "BST3 Switch", "BST3"},
997b0520
BL		 1369 {"RECMIXR", "BST2 Switch", "BST2"},
1370 {"RECMIXR", "BST1 Switch", "BST1"},
1371 {"RECMIXR", "OUT MIXR Switch", "OUT MIXR"},
1372
1373 {"ADC L", NULL, "RECMIXL"},
1374 {"ADC R", NULL, "RECMIXR"},
1375
1376 {"DMIC L1", NULL, "DMIC CLK"},
1377 {"DMIC L1", NULL, "DMIC1 Power"},
1378 {"DMIC R1", NULL, "DMIC CLK"},
1379 {"DMIC R1", NULL, "DMIC1 Power"},
1380 {"DMIC L2", NULL, "DMIC CLK"},
1381 {"DMIC L2", NULL, "DMIC2 Power"},
1382 {"DMIC R2", NULL, "DMIC CLK"},
1383 {"DMIC R2", NULL, "DMIC2 Power"},
1384
1385 {"Stereo ADC L2 Mux", "DMIC1", "DMIC L1"},
1386 {"Stereo ADC L2 Mux", "DMIC2", "DMIC L2"},
1387 {"Stereo ADC L2 Mux", "DIG MIX", "DIG MIXL"},
1388 {"Stereo ADC L1 Mux", "ADC", "ADC L"},
1389 {"Stereo ADC L1 Mux", "DIG MIX", "DIG MIXL"},
1390
1391 {"Stereo ADC R1 Mux", "ADC", "ADC R"},
1392 {"Stereo ADC R1 Mux", "DIG MIX", "DIG MIXR"},
1393 {"Stereo ADC R2 Mux", "DMIC1", "DMIC R1"},
1394 {"Stereo ADC R2 Mux", "DMIC2", "DMIC R2"},
1395 {"Stereo ADC R2 Mux", "DIG MIX", "DIG MIXR"},
1396
1397 {"Mono ADC L2 Mux", "DMIC L1", "DMIC L1"},
1398 {"Mono ADC L2 Mux", "DMIC L2", "DMIC L2"},
1399 {"Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL"},
1400 {"Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL"},
1401 {"Mono ADC L1 Mux", "ADCL", "ADC L"},
1402
1403 {"Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR"},
1404 {"Mono ADC R1 Mux", "ADCR", "ADC R"},
1405 {"Mono ADC R2 Mux", "DMIC R1", "DMIC R1"},
1406 {"Mono ADC R2 Mux", "DMIC R2", "DMIC R2"},
1407 {"Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR"},
1408
1409 {"Stereo ADC MIXL", "ADC1 Switch", "Stereo ADC L1 Mux"},
1410 {"Stereo ADC MIXL", "ADC2 Switch", "Stereo ADC L2 Mux"},
1411 {"Stereo ADC MIXL", NULL, "Stereo Filter"},
997b0520
BL		 1412
1413 {"Stereo ADC MIXR", "ADC1 Switch", "Stereo ADC R1 Mux"},
1414 {"Stereo ADC MIXR", "ADC2 Switch", "Stereo ADC R2 Mux"},
1415 {"Stereo ADC MIXR", NULL, "Stereo Filter"},
997b0520
BL		 1416
1417 {"Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux"},
1418 {"Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux"},
1419 {"Mono ADC MIXL", NULL, "Mono Left Filter"},
997b0520
BL		 1420
1421 {"Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux"},
1422 {"Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux"},
1423 {"Mono ADC MIXR", NULL, "Mono Right Filter"},
997b0520
BL		 1424
1425 {"IF2 ADC L", NULL, "Mono ADC MIXL"},
1426 {"IF2 ADC R", NULL, "Mono ADC MIXR"},
1427 {"IF1 ADC L", NULL, "Stereo ADC MIXL"},
1428 {"IF1 ADC R", NULL, "Stereo ADC MIXR"},
1429
1430 {"IF1 ADC", NULL, "I2S1"},
1431 {"IF1 ADC", NULL, "IF1 ADC L"},
1432 {"IF1 ADC", NULL, "IF1 ADC R"},
1433 {"IF2 ADC", NULL, "I2S2"},
1434 {"IF2 ADC", NULL, "IF2 ADC L"},
1435 {"IF2 ADC", NULL, "IF2 ADC R"},
1436
1437 {"DAI1 TX Mux", "1:1|2:2", "IF1 ADC"},
1438 {"DAI1 TX Mux", "1:2|2:1", "IF2 ADC"},
1439 {"DAI1 IF1 Mux", "1:1|2:1", "IF1 ADC"},
1440 {"DAI1 IF2 Mux", "1:1|2:1", "IF2 ADC"},
1441 {"SDI1 TX Mux", "IF1", "DAI1 IF1 Mux"},
1442 {"SDI1 TX Mux", "IF2", "DAI1 IF2 Mux"},
1443
1444 {"DAI2 TX Mux", "1:2|2:1", "IF1 ADC"},
1445 {"DAI2 TX Mux", "1:1|2:2", "IF2 ADC"},
1446 {"DAI2 IF1 Mux", "1:2|2:2", "IF1 ADC"},
1447 {"DAI2 IF2 Mux", "1:2|2:2", "IF2 ADC"},
1448 {"SDI2 TX Mux", "IF1", "DAI2 IF1 Mux"},
1449 {"SDI2 TX Mux", "IF2", "DAI2 IF2 Mux"},
1450
1451 {"AIF1TX", NULL, "DAI1 TX Mux"},
1452 {"AIF1TX", NULL, "SDI1 TX Mux"},
1453 {"AIF2TX", NULL, "DAI2 TX Mux"},
1454 {"AIF2TX", NULL, "SDI2 TX Mux"},
1455
1456 {"DAI1 RX Mux", "1:1|2:2", "AIF1RX"},
1457 {"DAI1 RX Mux", "1:1|2:1", "AIF1RX"},
1458 {"DAI1 RX Mux", "1:2|2:1", "AIF2RX"},
1459 {"DAI1 RX Mux", "1:2|2:2", "AIF2RX"},
1460
1461 {"DAI2 RX Mux", "1:2|2:1", "AIF1RX"},
1462 {"DAI2 RX Mux", "1:1|2:1", "AIF1RX"},
1463 {"DAI2 RX Mux", "1:1|2:2", "AIF2RX"},
1464 {"DAI2 RX Mux", "1:2|2:2", "AIF2RX"},
1465
1466 {"IF1 DAC", NULL, "I2S1"},
1467 {"IF1 DAC", NULL, "DAI1 RX Mux"},
1468 {"IF2 DAC", NULL, "I2S2"},
1469 {"IF2 DAC", NULL, "DAI2 RX Mux"},
1470
1471 {"IF1 DAC L", NULL, "IF1 DAC"},
1472 {"IF1 DAC R", NULL, "IF1 DAC"},
1473 {"IF2 DAC L", NULL, "IF2 DAC"},
1474 {"IF2 DAC R", NULL, "IF2 DAC"},
1475
1476 {"DAC MIXL", "Stereo ADC Switch", "Stereo ADC MIXL"},
1477 {"DAC MIXL", "INF1 Switch", "IF1 DAC L"},
57586fb7 1478 {"DAC MIXL", NULL, "DAC L1 Power"},
997b0520
BL		 1479 {"DAC MIXR", "Stereo ADC Switch", "Stereo ADC MIXR"},
1480 {"DAC MIXR", "INF1 Switch", "IF1 DAC R"},
57586fb7 1481 {"DAC MIXR", NULL, "DAC R1 Power"},
997b0520 1482
997b0520 1483 {"Stereo DAC MIXL", "DAC L1 Switch", "DAC MIXL"},
997b0520 1484 {"Stereo DAC MIXR", "DAC R1 Switch", "DAC MIXR"},
997b0520
BL		 1485
1486 {"Mono DAC MIXL", "DAC L1 Switch", "DAC MIXL"},
997b0520 1487 {"Mono DAC MIXR", "DAC R1 Switch", "DAC MIXR"},
997b0520
BL		 1488
1489 {"DIG MIXL", "DAC L1 Switch", "DAC MIXL"},
997b0520 1490 {"DIG MIXR", "DAC R1 Switch", "DAC MIXR"},
997b0520
BL		 1491
1492 {"DAC L1", NULL, "Stereo DAC MIXL"},
57586fb7 1493 {"DAC L1", NULL, "DAC L1 Power"},
997b0520 1494 {"DAC R1", NULL, "Stereo DAC MIXR"},
57586fb7 1495 {"DAC R1", NULL, "DAC R1 Power"},
997b0520
BL		 1496
1497 {"SPK MIXL", "REC MIXL Switch", "RECMIXL"},
1498 {"SPK MIXL", "INL Switch", "INL VOL"},
1499 {"SPK MIXL", "DAC L1 Switch", "DAC L1"},
997b0520
BL		 1500 {"SPK MIXL", "OUT MIXL Switch", "OUT MIXL"},
1501 {"SPK MIXR", "REC MIXR Switch", "RECMIXR"},
1502 {"SPK MIXR", "INR Switch", "INR VOL"},
1503 {"SPK MIXR", "DAC R1 Switch", "DAC R1"},
997b0520
BL		 1504 {"SPK MIXR", "OUT MIXR Switch", "OUT MIXR"},
1505
997b0520
BL		 1506 {"OUT MIXL", "BST1 Switch", "BST1"},
1507 {"OUT MIXL", "INL Switch", "INL VOL"},
1508 {"OUT MIXL", "REC MIXL Switch", "RECMIXL"},
997b0520
BL		 1509 {"OUT MIXL", "DAC L1 Switch", "DAC L1"},
1510
997b0520
BL		 1511 {"OUT MIXR", "BST2 Switch", "BST2"},
1512 {"OUT MIXR", "BST1 Switch", "BST1"},
1513 {"OUT MIXR", "INR Switch", "INR VOL"},
1514 {"OUT MIXR", "REC MIXR Switch", "RECMIXR"},
997b0520
BL		 1515 {"OUT MIXR", "DAC R1 Switch", "DAC R1"},
1516
1517 {"SPKVOL L", NULL, "SPK MIXL"},
1518 {"SPKVOL R", NULL, "SPK MIXR"},
1519 {"HPOVOL L", NULL, "OUT MIXL"},
1520 {"HPOVOL R", NULL, "OUT MIXR"},
1521 {"OUTVOL L", NULL, "OUT MIXL"},
1522 {"OUTVOL R", NULL, "OUT MIXR"},
1523
1524 {"SPOL MIX", "DAC R1 Switch", "DAC R1"},
1525 {"SPOL MIX", "DAC L1 Switch", "DAC L1"},
1526 {"SPOL MIX", "SPKVOL R Switch", "SPKVOL R"},
1527 {"SPOL MIX", "SPKVOL L Switch", "SPKVOL L"},
1528 {"SPOL MIX", "BST1 Switch", "BST1"},
1529 {"SPOR MIX", "DAC R1 Switch", "DAC R1"},
1530 {"SPOR MIX", "SPKVOL R Switch", "SPKVOL R"},
1531 {"SPOR MIX", "BST1 Switch", "BST1"},
1532
997b0520
BL		 1533 {"HPO MIX L", "HPO MIX DAC1 Switch", "DAC L1"},
1534 {"HPO MIX L", "HPO MIX HPVOL Switch", "HPOVOL L"},
246693ba 1535 {"HPO MIX L", NULL, "HP L Amp"},
997b0520
BL		 1536 {"HPO MIX R", "HPO MIX DAC1 Switch", "DAC R1"},
1537 {"HPO MIX R", "HPO MIX HPVOL Switch", "HPOVOL R"},
246693ba 1538 {"HPO MIX R", NULL, "HP R Amp"},
997b0520
BL		 1539
1540 {"LOUT MIX", "DAC L1 Switch", "DAC L1"},
1541 {"LOUT MIX", "DAC R1 Switch", "DAC R1"},
1542 {"LOUT MIX", "OUTVOL L Switch", "OUTVOL L"},
1543 {"LOUT MIX", "OUTVOL R Switch", "OUTVOL R"},
1544
246693ba
BL		 1545 {"HP Amp", NULL, "HPO MIX L"},
1546 {"HP Amp", NULL, "HPO MIX R"},
997b0520 1547
246693ba
BL		 1548 {"Speaker L Playback", "Switch", "SPOL MIX"},
1549 {"Speaker R Playback", "Switch", "SPOR MIX"},
1550 {"SPOLP", NULL, "Speaker L Playback"},
1551 {"SPOLN", NULL, "Speaker L Playback"},
1552 {"SPORP", NULL, "Speaker R Playback"},
1553 {"SPORN", NULL, "Speaker R Playback"},
997b0520
BL		 1554
1555 {"SPOLP", NULL, "Improve SPK Amp Drv"},
1556 {"SPOLN", NULL, "Improve SPK Amp Drv"},
1557 {"SPORP", NULL, "Improve SPK Amp Drv"},
1558 {"SPORN", NULL, "Improve SPK Amp Drv"},
1559
1560 {"HPOL", NULL, "Improve HP Amp Drv"},
1561 {"HPOR", NULL, "Improve HP Amp Drv"},
1562
246693ba
BL		 1563 {"HP L Playback", "Switch", "HP Amp"},
1564 {"HP R Playback", "Switch", "HP Amp"},
1565 {"HPOL", NULL, "HP L Playback"},
1566 {"HPOR", NULL, "HP R Playback"},
9b850ca4
JL		 1567
1568 {"LOUT amp", NULL, "LOUT MIX"},
1569 {"LOUTL", NULL, "LOUT amp"},
1570 {"LOUTR", NULL, "LOUT amp"},
022d21f0
OC		 1571};
1572
1573static const struct snd_soc_dapm_route rt5640_specific_dapm_routes[] = {
1574 {"ANC", NULL, "Stereo ADC MIXL"},
1575 {"ANC", NULL, "Stereo ADC MIXR"},
1576
1577 {"Audio DSP", NULL, "DAC MIXL"},
1578 {"Audio DSP", NULL, "DAC MIXR"},
1579
1580 {"DAC L2 Mux", "IF2", "IF2 DAC L"},
1581 {"DAC L2 Mux", "Base L/R", "Audio DSP"},
57586fb7 1582 {"DAC L2 Mux", NULL, "DAC L2 Power"},
022d21f0 1583 {"DAC R2 Mux", "IF2", "IF2 DAC R"},
57586fb7 1584 {"DAC R2 Mux", NULL, "DAC R2 Power"},
022d21f0
OC		 1585
1586 {"Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
1587 {"Stereo DAC MIXL", "ANC Switch", "ANC"},
1588 {"Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
1589 {"Stereo DAC MIXR", "ANC Switch", "ANC"},
1590
1591 {"Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
1592 {"Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
1593
1594 {"Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
1595 {"Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
1596
1597 {"DIG MIXR", "DAC R2 Switch", "DAC R2 Mux"},
1598 {"DIG MIXL", "DAC L2 Switch", "DAC L2 Mux"},
1599
1600 {"DAC L2", NULL, "Mono DAC MIXL"},
57586fb7 1601 {"DAC L2", NULL, "DAC L2 Power"},
022d21f0 1602 {"DAC R2", NULL, "Mono DAC MIXR"},
57586fb7 1603 {"DAC R2", NULL, "DAC R2 Power"},
022d21f0
OC		 1604
1605 {"SPK MIXL", "DAC L2 Switch", "DAC L2"},
1606 {"SPK MIXR", "DAC R2 Switch", "DAC R2"},
1607
1608 {"OUT MIXL", "SPK MIXL Switch", "SPK MIXL"},
1609 {"OUT MIXR", "SPK MIXR Switch", "SPK MIXR"},
1610
1611 {"OUT MIXL", "DAC R2 Switch", "DAC R2"},
1612 {"OUT MIXL", "DAC L2 Switch", "DAC L2"},
1613
1614 {"OUT MIXR", "DAC L2 Switch", "DAC L2"},
1615 {"OUT MIXR", "DAC R2 Switch", "DAC R2"},
1616
1617 {"HPO MIX L", "HPO MIX DAC2 Switch", "DAC L2"},
1618 {"HPO MIX R", "HPO MIX DAC2 Switch", "DAC R2"},
1619
1620 {"Mono MIX", "DAC R2 Switch", "DAC R2"},
1621 {"Mono MIX", "DAC L2 Switch", "DAC L2"},
1622 {"Mono MIX", "OUTVOL R Switch", "OUTVOL R"},
1623 {"Mono MIX", "OUTVOL L Switch", "OUTVOL L"},
1624 {"Mono MIX", "BST1 Switch", "BST1"},
1625
997b0520
BL		 1626 {"MONOP", NULL, "Mono MIX"},
1627 {"MONON", NULL, "Mono MIX"},
1628 {"MONOP", NULL, "Improve MONO Amp Drv"},
1629};
1630
022d21f0
OC		 1631static const struct snd_soc_dapm_route rt5639_specific_dapm_routes[] = {
1632 {"Stereo DAC MIXL", "DAC L2 Switch", "IF2 DAC L"},
1633 {"Stereo DAC MIXR", "DAC R2 Switch", "IF2 DAC R"},
1634
1635 {"Mono DAC MIXL", "DAC L2 Switch", "IF2 DAC L"},
1636 {"Mono DAC MIXL", "DAC R2 Switch", "IF2 DAC R"},
1637
1638 {"Mono DAC MIXR", "DAC R2 Switch", "IF2 DAC R"},
1639 {"Mono DAC MIXR", "DAC L2 Switch", "IF2 DAC L"},
1640
1641 {"DIG MIXL", "DAC L2 Switch", "IF2 DAC L"},
1642 {"DIG MIXR", "DAC R2 Switch", "IF2 DAC R"},
1643
57586fb7
BL		 1644 {"IF2 DAC L", NULL, "DAC L2 Power"},
1645 {"IF2 DAC R", NULL, "DAC R2 Power"},
022d21f0
OC		 1646};
1647
d5a41b5d 1648static int get_sdp_info(struct snd_soc_component *component, int dai_id)
997b0520
BL		 1649{
1650 int ret = 0, val;
1651
d5a41b5d 1652 if (component == NULL)
997b0520
BL		 1653 return -EINVAL;
1654
467a2553 1655 val = snd_soc_component_read(component, RT5640_I2S1_SDP);
997b0520
BL		 1656 val = (val & RT5640_I2S_IF_MASK) >> RT5640_I2S_IF_SFT;
1657 switch (dai_id) {
1658 case RT5640_AIF1:
1659 switch (val) {
1660 case RT5640_IF_123:
1661 case RT5640_IF_132:
1662 ret |= RT5640_U_IF1;
1663 break;
1664 case RT5640_IF_113:
1665 ret |= RT5640_U_IF1;
3e146b55 1666 fallthrough;
997b0520
BL		 1667 case RT5640_IF_312:
1668 case RT5640_IF_213:
1669 ret |= RT5640_U_IF2;
1670 break;
1671 }
1672 break;
1673
1674 case RT5640_AIF2:
1675 switch (val) {
1676 case RT5640_IF_231:
1677 case RT5640_IF_213:
1678 ret |= RT5640_U_IF1;
1679 break;
1680 case RT5640_IF_223:
1681 ret |= RT5640_U_IF1;
3e146b55 1682 fallthrough;
997b0520
BL		 1683 case RT5640_IF_123:
1684 case RT5640_IF_321:
1685 ret |= RT5640_U_IF2;
1686 break;
1687 }
1688 break;
1689
1690 default:
1691 ret = -EINVAL;
1692 break;
1693 }
1694
1695 return ret;
1696}
1697
997b0520
BL		 1698static int rt5640_hw_params(struct snd_pcm_substream *substream,
1699 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1700{
d5a41b5d
KM		 1701 struct snd_soc_component *component = dai->component;
1702 struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
5a7615cf
TI		 1703 unsigned int val_len = 0, val_clk, mask_clk;
1704 int dai_sel, pre_div, bclk_ms, frame_size;
997b0520
BL		 1705
1706 rt5640->lrck[dai->id] = params_rate(params);
d92950e7 1707 pre_div = rl6231_get_clk_info(rt5640->sysclk, rt5640->lrck[dai->id]);
997b0520 1708 if (pre_div < 0) {
d5a41b5d 1709 dev_err(component->dev, "Unsupported clock setting %d for DAI %d\n",
9e9cb9b9 1710 rt5640->lrck[dai->id], dai->id);
997b0520
BL		 1711 return -EINVAL;
1712 }
1713 frame_size = snd_soc_params_to_frame_size(params);
1714 if (frame_size < 0) {
d5a41b5d 1715 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
997b0520
BL		 1716 return frame_size;
1717 }
1718 if (frame_size > 32)
1719 bclk_ms = 1;
1720 else
1721 bclk_ms = 0;
1722 rt5640->bclk[dai->id] = rt5640->lrck[dai->id] * (32 << bclk_ms);
1723
1724 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
1725 rt5640->bclk[dai->id], rt5640->lrck[dai->id]);
1726 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
1727 bclk_ms, pre_div, dai->id);
1728
9bccae73
OC		 1729 switch (params_width(params)) {
1730 case 16:
997b0520 1731 break;
9bccae73 1732 case 20:
997b0520
BL		 1733 val_len |= RT5640_I2S_DL_20;
1734 break;
9bccae73 1735 case 24:
997b0520
BL		 1736 val_len |= RT5640_I2S_DL_24;
1737 break;
9bccae73 1738 case 8:
997b0520
BL		 1739 val_len |= RT5640_I2S_DL_8;
1740 break;
1741 default:
1742 return -EINVAL;
1743 }
1744
d5a41b5d 1745 dai_sel = get_sdp_info(component, dai->id);
997b0520 1746 if (dai_sel < 0) {
d5a41b5d 1747 dev_err(component->dev, "Failed to get sdp info: %d\n", dai_sel);
997b0520
BL		 1748 return -EINVAL;
1749 }
1750 if (dai_sel & RT5640_U_IF1) {
1751 mask_clk = RT5640_I2S_BCLK_MS1_MASK | RT5640_I2S_PD1_MASK;
1752 val_clk = bclk_ms << RT5640_I2S_BCLK_MS1_SFT |
1753 pre_div << RT5640_I2S_PD1_SFT;
d5a41b5d 1754 snd_soc_component_update_bits(component, RT5640_I2S1_SDP,
997b0520 1755 RT5640_I2S_DL_MASK, val_len);
d5a41b5d 1756 snd_soc_component_update_bits(component, RT5640_ADDA_CLK1, mask_clk, val_clk);
997b0520
BL		 1757 }
1758 if (dai_sel & RT5640_U_IF2) {
1759 mask_clk = RT5640_I2S_BCLK_MS2_MASK | RT5640_I2S_PD2_MASK;
1760 val_clk = bclk_ms << RT5640_I2S_BCLK_MS2_SFT |
1761 pre_div << RT5640_I2S_PD2_SFT;
d5a41b5d 1762 snd_soc_component_update_bits(component, RT5640_I2S2_SDP,
997b0520 1763 RT5640_I2S_DL_MASK, val_len);
d5a41b5d 1764 snd_soc_component_update_bits(component, RT5640_ADDA_CLK1, mask_clk, val_clk);
997b0520
BL		 1765 }
1766
1767 return 0;
1768}
1769
1770static int rt5640_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1771{
d5a41b5d
KM		 1772 struct snd_soc_component *component = dai->component;
1773 struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
5a7615cf
TI		 1774 unsigned int reg_val = 0;
1775 int dai_sel;
997b0520
BL		 1776
1777 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1778 case SND_SOC_DAIFMT_CBM_CFM:
1779 rt5640->master[dai->id] = 1;
1780 break;
1781 case SND_SOC_DAIFMT_CBS_CFS:
1782 reg_val |= RT5640_I2S_MS_S;
1783 rt5640->master[dai->id] = 0;
1784 break;
1785 default:
1786 return -EINVAL;
1787 }
1788
1789 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1790 case SND_SOC_DAIFMT_NB_NF:
1791 break;
1792 case SND_SOC_DAIFMT_IB_NF:
1793 reg_val |= RT5640_I2S_BP_INV;
1794 break;
1795 default:
1796 return -EINVAL;
1797 }
1798
1799 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1800 case SND_SOC_DAIFMT_I2S:
1801 break;
1802 case SND_SOC_DAIFMT_LEFT_J:
1803 reg_val |= RT5640_I2S_DF_LEFT;
1804 break;
1805 case SND_SOC_DAIFMT_DSP_A:
1806 reg_val |= RT5640_I2S_DF_PCM_A;
1807 break;
1808 case SND_SOC_DAIFMT_DSP_B:
1809 reg_val |= RT5640_I2S_DF_PCM_B;
1810 break;
1811 default:
1812 return -EINVAL;
1813 }
1814
d5a41b5d 1815 dai_sel = get_sdp_info(component, dai->id);
997b0520 1816 if (dai_sel < 0) {
d5a41b5d 1817 dev_err(component->dev, "Failed to get sdp info: %d\n", dai_sel);
997b0520
BL		 1818 return -EINVAL;
1819 }
1820 if (dai_sel & RT5640_U_IF1) {
d5a41b5d 1821 snd_soc_component_update_bits(component, RT5640_I2S1_SDP,
997b0520
BL		 1822 RT5640_I2S_MS_MASK | RT5640_I2S_BP_MASK |
1823 RT5640_I2S_DF_MASK, reg_val);
1824 }
1825 if (dai_sel & RT5640_U_IF2) {
d5a41b5d 1826 snd_soc_component_update_bits(component, RT5640_I2S2_SDP,
997b0520
BL		 1827 RT5640_I2S_MS_MASK | RT5640_I2S_BP_MASK |
1828 RT5640_I2S_DF_MASK, reg_val);
1829 }
1830
1831 return 0;
1832}
1833
1834static int rt5640_set_dai_sysclk(struct snd_soc_dai *dai,
1835 int clk_id, unsigned int freq, int dir)
1836{
d5a41b5d
KM		 1837 struct snd_soc_component *component = dai->component;
1838 struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
997b0520 1839 unsigned int reg_val = 0;
8e7a1f1f 1840 unsigned int pll_bit = 0;
997b0520 1841
997b0520
BL		 1842 switch (clk_id) {
1843 case RT5640_SCLK_S_MCLK:
1844 reg_val |= RT5640_SCLK_SRC_MCLK;
1845 break;
1846 case RT5640_SCLK_S_PLL1:
1847 reg_val |= RT5640_SCLK_SRC_PLL1;
8e7a1f1f 1848 pll_bit |= RT5640_PWR_PLL;
997b0520 1849 break;
c49aed77
PLB		 1850 case RT5640_SCLK_S_RCCLK:
1851 reg_val |= RT5640_SCLK_SRC_RCCLK;
1852 break;
997b0520 1853 default:
d5a41b5d 1854 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
997b0520
BL		 1855 return -EINVAL;
1856 }
8e7a1f1f
HG		 1857 snd_soc_component_update_bits(component, RT5640_PWR_ANLG2,
1858 RT5640_PWR_PLL, pll_bit);
d5a41b5d 1859 snd_soc_component_update_bits(component, RT5640_GLB_CLK,
997b0520
BL		 1860 RT5640_SCLK_SRC_MASK, reg_val);
1861 rt5640->sysclk = freq;
1862 rt5640->sysclk_src = clk_id;
1863
1864 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
1865 return 0;
1866}
1867
997b0520
BL		 1868static int rt5640_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
1869 unsigned int freq_in, unsigned int freq_out)
1870{
d5a41b5d
KM		 1871 struct snd_soc_component *component = dai->component;
1872 struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
71c7a2d6 1873 struct rl6231_pll_code pll_code;
c77dd678 1874 int ret;
997b0520
BL		 1875
1876 if (source == rt5640->pll_src && freq_in == rt5640->pll_in &&
1877 freq_out == rt5640->pll_out)
1878 return 0;
1879
1880 if (!freq_in || !freq_out) {
d5a41b5d 1881 dev_dbg(component->dev, "PLL disabled\n");
997b0520
BL		 1882
1883 rt5640->pll_in = 0;
1884 rt5640->pll_out = 0;
d5a41b5d 1885 snd_soc_component_update_bits(component, RT5640_GLB_CLK,
997b0520
BL		 1886 RT5640_SCLK_SRC_MASK, RT5640_SCLK_SRC_MCLK);
1887 return 0;
1888 }
1889
1890 switch (source) {
1891 case RT5640_PLL1_S_MCLK:
d5a41b5d 1892 snd_soc_component_update_bits(component, RT5640_GLB_CLK,
997b0520
BL		 1893 RT5640_PLL1_SRC_MASK, RT5640_PLL1_SRC_MCLK);
1894 break;
1895 case RT5640_PLL1_S_BCLK1:
d5a41b5d 1896 snd_soc_component_update_bits(component, RT5640_GLB_CLK,
c467fc0e
BL		 1897 RT5640_PLL1_SRC_MASK, RT5640_PLL1_SRC_BCLK1);
1898 break;
997b0520 1899 case RT5640_PLL1_S_BCLK2:
d5a41b5d 1900 snd_soc_component_update_bits(component, RT5640_GLB_CLK,
c467fc0e 1901 RT5640_PLL1_SRC_MASK, RT5640_PLL1_SRC_BCLK2);
997b0520
BL		 1902 break;
1903 default:
d5a41b5d 1904 dev_err(component->dev, "Unknown PLL source %d\n", source);
997b0520
BL		 1905 return -EINVAL;
1906 }
1907
71c7a2d6 1908 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
997b0520 1909 if (ret < 0) {
a4db95b2 1910 dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
997b0520
BL		 1911 return ret;
1912 }
1913
d5a41b5d 1914 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
71c7a2d6
OC		 1915 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
1916 pll_code.n_code, pll_code.k_code);
997b0520 1917
d5a41b5d 1918 snd_soc_component_write(component, RT5640_PLL_CTRL1,
4fbd2978 1919 (pll_code.n_code << RT5640_PLL_N_SFT) | pll_code.k_code);
d5a41b5d 1920 snd_soc_component_write(component, RT5640_PLL_CTRL2,
4fbd2978
PLB		 1921 ((pll_code.m_bp ? 0 : pll_code.m_code) << RT5640_PLL_M_SFT) |
1922 (pll_code.m_bp << RT5640_PLL_M_BP_SFT));
997b0520
BL		 1923
1924 rt5640->pll_in = freq_in;
1925 rt5640->pll_out = freq_out;
1926 rt5640->pll_src = source;
1927
1928 return 0;
1929}
1930
d5a41b5d 1931static int rt5640_set_bias_level(struct snd_soc_component *component,
997b0520
BL		 1932 enum snd_soc_bias_level level)
1933{
d5a41b5d 1934 struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
6049af00
SZ		 1935 int ret;
1936
997b0520 1937 switch (level) {
6049af00
SZ		 1938 case SND_SOC_BIAS_ON:
1939 break;
1940
1941 case SND_SOC_BIAS_PREPARE:
1942 /*
1943 * SND_SOC_BIAS_PREPARE is called while preparing for a
1944 * transition to ON or away from ON. If current bias_level
1945 * is SND_SOC_BIAS_ON, then it is preparing for a transition
1946 * away from ON. Disable the clock in that case, otherwise
1947 * enable it.
1948 */
1949 if (IS_ERR(rt5640->mclk))
1950 break;
1951
d5a41b5d 1952 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON) {
6049af00
SZ		 1953 clk_disable_unprepare(rt5640->mclk);
1954 } else {
1955 ret = clk_prepare_enable(rt5640->mclk);
1956 if (ret)
1957 return ret;
1958 }
1959 break;
1960
997b0520 1961 case SND_SOC_BIAS_STANDBY:
d5a41b5d
KM		 1962 if (SND_SOC_BIAS_OFF == snd_soc_component_get_bias_level(component)) {
1963 snd_soc_component_update_bits(component, RT5640_PWR_ANLG1,
997b0520
BL		 1964 RT5640_PWR_VREF1 | RT5640_PWR_MB |
1965 RT5640_PWR_BG | RT5640_PWR_VREF2,
1966 RT5640_PWR_VREF1 | RT5640_PWR_MB |
1967 RT5640_PWR_BG | RT5640_PWR_VREF2);
246693ba 1968 usleep_range(10000, 15000);
d5a41b5d 1969 snd_soc_component_update_bits(component, RT5640_PWR_ANLG1,
997b0520
BL		 1970 RT5640_PWR_FV1 | RT5640_PWR_FV2,
1971 RT5640_PWR_FV1 | RT5640_PWR_FV2);
d5a41b5d 1972 snd_soc_component_update_bits(component, RT5640_DUMMY1,
e3dd4424 1973 0x1, 0x1);
d5a41b5d 1974 snd_soc_component_update_bits(component, RT5640_MICBIAS,
997b0520
BL		 1975 0x0030, 0x0030);
1976 }
1977 break;
1978
1979 case SND_SOC_BIAS_OFF:
d5a41b5d
KM		 1980 snd_soc_component_write(component, RT5640_DEPOP_M1, 0x0004);
1981 snd_soc_component_write(component, RT5640_DEPOP_M2, 0x1100);
1982 snd_soc_component_update_bits(component, RT5640_DUMMY1, 0x1, 0);
1983 snd_soc_component_write(component, RT5640_PWR_DIG1, 0x0000);
1984 snd_soc_component_write(component, RT5640_PWR_DIG2, 0x0000);
1985 snd_soc_component_write(component, RT5640_PWR_VOL, 0x0000);
1986 snd_soc_component_write(component, RT5640_PWR_MIXER, 0x0000);
051dade3
OC		 1987 if (rt5640->jd_src == RT5640_JD_SRC_HDA_HEADER)
1988 snd_soc_component_write(component, RT5640_PWR_ANLG1,
afb176d4 1989 0x2818);
051dade3
OC		 1990 else
1991 snd_soc_component_write(component, RT5640_PWR_ANLG1,
1992 0x0000);
d5a41b5d 1993 snd_soc_component_write(component, RT5640_PWR_ANLG2, 0x0000);
997b0520
BL		 1994 break;
1995
1996 default:
1997 break;
1998 }
997b0520
BL		 1999
2000 return 0;
2001}
2002
d5a41b5d 2003int rt5640_dmic_enable(struct snd_soc_component *component,
cd69dc88
JN		 2004 bool dmic1_data_pin, bool dmic2_data_pin)
2005{
d5a41b5d 2006 struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
cd69dc88
JN		 2007
2008 regmap_update_bits(rt5640->regmap, RT5640_GPIO_CTRL1,
2009 RT5640_GP2_PIN_MASK, RT5640_GP2_PIN_DMIC1_SCL);
2010
2011 if (dmic1_data_pin) {
2012 regmap_update_bits(rt5640->regmap, RT5640_DMIC,
2013 RT5640_DMIC_1_DP_MASK, RT5640_DMIC_1_DP_GPIO3);
2014 regmap_update_bits(rt5640->regmap, RT5640_GPIO_CTRL1,
2015 RT5640_GP3_PIN_MASK, RT5640_GP3_PIN_DMIC1_SDA);
2016 }
2017
2018 if (dmic2_data_pin) {
2019 regmap_update_bits(rt5640->regmap, RT5640_DMIC,
2020 RT5640_DMIC_2_DP_MASK, RT5640_DMIC_2_DP_GPIO4);
2021 regmap_update_bits(rt5640->regmap, RT5640_GPIO_CTRL1,
2022 RT5640_GP4_PIN_MASK, RT5640_GP4_PIN_DMIC2_SDA);
2023 }
2024
2025 return 0;
2026}
2027EXPORT_SYMBOL_GPL(rt5640_dmic_enable);
2028
d5a41b5d 2029int rt5640_sel_asrc_clk_src(struct snd_soc_component *component,
bee3e020
JY		 2030 unsigned int filter_mask, unsigned int clk_src)
2031{
d5a41b5d 2032 struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
bee3e020
JY		 2033 unsigned int asrc2_mask = 0;
2034 unsigned int asrc2_value = 0;
2035
2036 switch (clk_src) {
2037 case RT5640_CLK_SEL_SYS:
2038 case RT5640_CLK_SEL_ASRC:
2039 break;
2040
2041 default:
2042 return -EINVAL;
2043 }
2044
2045 if (!filter_mask)
2046 return -EINVAL;
2047
2048 if (filter_mask & RT5640_DA_STEREO_FILTER) {
2049 asrc2_mask |= RT5640_STO_DAC_M_MASK;
2050 asrc2_value = (asrc2_value & ~RT5640_STO_DAC_M_MASK)
2051 | (clk_src << RT5640_STO_DAC_M_SFT);
2052 }
2053
2054 if (filter_mask & RT5640_DA_MONO_L_FILTER) {
2055 asrc2_mask |= RT5640_MDA_L_M_MASK;
2056 asrc2_value = (asrc2_value & ~RT5640_MDA_L_M_MASK)
2057 | (clk_src << RT5640_MDA_L_M_SFT);
2058 }
2059
2060 if (filter_mask & RT5640_DA_MONO_R_FILTER) {
2061 asrc2_mask |= RT5640_MDA_R_M_MASK;
2062 asrc2_value = (asrc2_value & ~RT5640_MDA_R_M_MASK)
2063 | (clk_src << RT5640_MDA_R_M_SFT);
2064 }
2065
2066 if (filter_mask & RT5640_AD_STEREO_FILTER) {
2067 asrc2_mask |= RT5640_ADC_M_MASK;
2068 asrc2_value = (asrc2_value & ~RT5640_ADC_M_MASK)
2069 | (clk_src << RT5640_ADC_M_SFT);
2070 }
2071
2072 if (filter_mask & RT5640_AD_MONO_L_FILTER) {
2073 asrc2_mask |= RT5640_MAD_L_M_MASK;
2074 asrc2_value = (asrc2_value & ~RT5640_MAD_L_M_MASK)
2075 | (clk_src << RT5640_MAD_L_M_SFT);
2076 }
2077
2078 if (filter_mask & RT5640_AD_MONO_R_FILTER) {
2079 asrc2_mask |= RT5640_MAD_R_M_MASK;
2080 asrc2_value = (asrc2_value & ~RT5640_MAD_R_M_MASK)
2081 | (clk_src << RT5640_MAD_R_M_SFT);
2082 }
2083
d5a41b5d 2084 snd_soc_component_update_bits(component, RT5640_ASRC_2,
bee3e020
JY		 2085 asrc2_mask, asrc2_value);
2086
467a2553 2087 if (snd_soc_component_read(component, RT5640_ASRC_2)) {
bee3e020 2088 rt5640->asrc_en = true;
d5a41b5d 2089 snd_soc_component_update_bits(component, RT5640_JD_CTRL, 0x3, 0x3);
bee3e020
JY		 2090 } else {
2091 rt5640->asrc_en = false;
d5a41b5d 2092 snd_soc_component_update_bits(component, RT5640_JD_CTRL, 0x3, 0x0);
bee3e020
JY		 2093 }
2094
2095 return 0;
2096}
2097EXPORT_SYMBOL_GPL(rt5640_sel_asrc_clk_src);
2098
e3f2a660 2099void rt5640_enable_micbias1_for_ovcd(struct snd_soc_component *component)
8210804b
HG		 2100{
2101 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
83229680 2102 struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
8210804b
HG		 2103
2104 snd_soc_dapm_mutex_lock(dapm);
2105 snd_soc_dapm_force_enable_pin_unlocked(dapm, "LDO2");
2106 snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS1");
2107 /* OVCD is unreliable when used with RCCLK as sysclk-source */
83229680
OC		 2108 if (rt5640->use_platform_clock)
2109 snd_soc_dapm_force_enable_pin_unlocked(dapm, "Platform Clock");
8210804b
HG		 2110 snd_soc_dapm_sync_unlocked(dapm);
2111 snd_soc_dapm_mutex_unlock(dapm);
2112}
e3f2a660 2113EXPORT_SYMBOL_GPL(rt5640_enable_micbias1_for_ovcd);
8210804b 2114
e3f2a660 2115void rt5640_disable_micbias1_for_ovcd(struct snd_soc_component *component)
8210804b
HG		 2116{
2117 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
83229680 2118 struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
8210804b
HG		 2119
2120 snd_soc_dapm_mutex_lock(dapm);
83229680
OC		 2121 if (rt5640->use_platform_clock)
2122 snd_soc_dapm_disable_pin_unlocked(dapm, "Platform Clock");
8210804b
HG		 2123 snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS1");
2124 snd_soc_dapm_disable_pin_unlocked(dapm, "LDO2");
2125 snd_soc_dapm_sync_unlocked(dapm);
2126 snd_soc_dapm_mutex_unlock(dapm);
2127}
e3f2a660 2128EXPORT_SYMBOL_GPL(rt5640_disable_micbias1_for_ovcd);
8210804b 2129
b16188a2
HG		 2130static void rt5640_enable_micbias1_ovcd_irq(struct snd_soc_component *component)
2131{
2132 struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
2133
2134 snd_soc_component_update_bits(component, RT5640_IRQ_CTRL2,
2135 RT5640_IRQ_MB1_OC_MASK, RT5640_IRQ_MB1_OC_NOR);
2136 rt5640->ovcd_irq_enabled = true;
2137}
2138
2139static void rt5640_disable_micbias1_ovcd_irq(struct snd_soc_component *component)
2140{
2141 struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
2142
2143 snd_soc_component_update_bits(component, RT5640_IRQ_CTRL2,
2144 RT5640_IRQ_MB1_OC_MASK, RT5640_IRQ_MB1_OC_BP);
2145 rt5640->ovcd_irq_enabled = false;
2146}
2147
8210804b
HG		 2148static void rt5640_clear_micbias1_ovcd(struct snd_soc_component *component)
2149{
2150 snd_soc_component_update_bits(component, RT5640_IRQ_CTRL2,
2151 RT5640_MB1_OC_STATUS, 0);
2152}
2153
2154static bool rt5640_micbias1_ovcd(struct snd_soc_component *component)
2155{
2156 int val;
2157
467a2553 2158 val = snd_soc_component_read(component, RT5640_IRQ_CTRL2);
8210804b
HG		 2159 dev_dbg(component->dev, "irq ctrl2 %#04x\n", val);
2160
2161 return (val & RT5640_MB1_OC_STATUS);
2162}
2163
2164static bool rt5640_jack_inserted(struct snd_soc_component *component)
2165{
2166 struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
2167 int val;
2168
701d636a
HG		 2169 if (rt5640->jd_gpio)
2170 val = gpiod_get_value(rt5640->jd_gpio) ? RT5640_JD_STATUS : 0;
2171 else
2172 val = snd_soc_component_read(component, RT5640_INT_IRQ_ST);
2173
8210804b
HG		 2174 dev_dbg(component->dev, "irq status %#04x\n", val);
2175
2176 if (rt5640->jd_inverted)
2177 return !(val & RT5640_JD_STATUS);
2178 else
2179 return (val & RT5640_JD_STATUS);
2180}
2181
b16188a2 2182/* Jack detect and button-press timings */
8210804b
HG		 2183#define JACK_SETTLE_TIME 100 /* milli seconds */
2184#define JACK_DETECT_COUNT 5
2185#define JACK_DETECT_MAXCOUNT 20 /* Aprox. 2 seconds worth of tries */
b16188a2
HG		 2186#define JACK_UNPLUG_TIME 80 /* milli seconds */
2187#define BP_POLL_TIME 10 /* milli seconds */
2188#define BP_POLL_MAXCOUNT 200 /* assume something is wrong after this */
2189#define BP_THRESHOLD 3
2190
2191static void rt5640_start_button_press_work(struct snd_soc_component *component)
2192{
2193 struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
2194
2195 rt5640->poll_count = 0;
2196 rt5640->press_count = 0;
2197 rt5640->release_count = 0;
2198 rt5640->pressed = false;
2199 rt5640->press_reported = false;
2200 rt5640_clear_micbias1_ovcd(component);
2201 schedule_delayed_work(&rt5640->bp_work, msecs_to_jiffies(BP_POLL_TIME));
2202}
2203
2204static void rt5640_button_press_work(struct work_struct *work)
2205{
2206 struct rt5640_priv *rt5640 =
2207 container_of(work, struct rt5640_priv, bp_work.work);
2208 struct snd_soc_component *component = rt5640->component;
2209
2210 /* Check the jack was not removed underneath us */
2211 if (!rt5640_jack_inserted(component))
2212 return;
2213
2214 if (rt5640_micbias1_ovcd(component)) {
2215 rt5640->release_count = 0;
2216 rt5640->press_count++;
2217 /* Remember till after JACK_UNPLUG_TIME wait */
2218 if (rt5640->press_count >= BP_THRESHOLD)
2219 rt5640->pressed = true;
2220 rt5640_clear_micbias1_ovcd(component);
2221 } else {
2222 rt5640->press_count = 0;
2223 rt5640->release_count++;
2224 }
2225
2226 /*
2227 * The pins get temporarily shorted on jack unplug, so we poll for
2228 * at least JACK_UNPLUG_TIME milli-seconds before reporting a press.
2229 */
2230 rt5640->poll_count++;
2231 if (rt5640->poll_count < (JACK_UNPLUG_TIME / BP_POLL_TIME)) {
2232 schedule_delayed_work(&rt5640->bp_work,
2233 msecs_to_jiffies(BP_POLL_TIME));
2234 return;
2235 }
2236
2237 if (rt5640->pressed && !rt5640->press_reported) {
2238 dev_dbg(component->dev, "headset button press\n");
2239 snd_soc_jack_report(rt5640->jack, SND_JACK_BTN_0,
2240 SND_JACK_BTN_0);
2241 rt5640->press_reported = true;
2242 }
2243
2244 if (rt5640->release_count >= BP_THRESHOLD) {
2245 if (rt5640->press_reported) {
2246 dev_dbg(component->dev, "headset button release\n");
2247 snd_soc_jack_report(rt5640->jack, 0, SND_JACK_BTN_0);
2248 }
2249 /* Re-enable OVCD IRQ to detect next press */
2250 rt5640_enable_micbias1_ovcd_irq(component);
2251 return; /* Stop polling */
2252 }
2253
2254 schedule_delayed_work(&rt5640->bp_work, msecs_to_jiffies(BP_POLL_TIME));
2255}
8210804b 2256
d21213b4 2257int rt5640_detect_headset(struct snd_soc_component *component, struct gpio_desc *hp_det_gpio)
8210804b
HG		 2258{
2259 int i, headset_count = 0, headphone_count = 0;
2260
2261 /*
2262 * We get the insertion event before the jack is fully inserted at which
2263 * point the second ring on a TRRS connector may short the 2nd ring and
2264 * sleeve contacts, also the overcurrent detection is not entirely
2265 * reliable. So we try several times with a wait in between until we
2266 * detect the same type JACK_DETECT_COUNT times in a row.
2267 */
2268 for (i = 0; i < JACK_DETECT_MAXCOUNT; i++) {
2269 /* Clear any previous over-current status flag */
2270 rt5640_clear_micbias1_ovcd(component);
2271
2272 msleep(JACK_SETTLE_TIME);
2273
2274 /* Check the jack is still connected before checking ovcd */
d21213b4
HG		 2275 if (hp_det_gpio) {
2276 if (gpiod_get_value_cansleep(hp_det_gpio))
2277 return 0;
2278 } else {
2279 if (!rt5640_jack_inserted(component))
2280 return 0;
2281 }
8210804b
HG		 2282
2283 if (rt5640_micbias1_ovcd(component)) {
2284 /*
2285 * Over current detected, there is a short between the
2286 * 2nd ring contact and the ground, so a TRS connector
2287 * without a mic contact and thus plain headphones.
2288 */
2289 dev_dbg(component->dev, "jack mic-gnd shorted\n");
2290 headset_count = 0;
2291 headphone_count++;
2292 if (headphone_count == JACK_DETECT_COUNT)
2293 return SND_JACK_HEADPHONE;
2294 } else {
2295 dev_dbg(component->dev, "jack mic-gnd open\n");
2296 headphone_count = 0;
2297 headset_count++;
2298 if (headset_count == JACK_DETECT_COUNT)
2299 return SND_JACK_HEADSET;
2300 }
2301 }
2302
2303 dev_err(component->dev, "Error detecting headset vs headphones, bad contact?, assuming headphones\n");
2304 return SND_JACK_HEADPHONE;
2305}
d21213b4 2306EXPORT_SYMBOL_GPL(rt5640_detect_headset);
8210804b
HG		 2307
2308static void rt5640_jack_work(struct work_struct *work)
2309{
2310 struct rt5640_priv *rt5640 =
a3b1aaf7 2311 container_of(work, struct rt5640_priv, jack_work.work);
8210804b
HG		 2312 struct snd_soc_component *component = rt5640->component;
2313 int status;
2314
2b9c8d2b
OC		 2315 if (rt5640->jd_src == RT5640_JD_SRC_HDA_HEADER) {
2316 int val, jack_type = 0, hda_mic_plugged, hda_hp_plugged;
2317
2318 /* mic jack */
2319 val = snd_soc_component_read(component, RT5640_INT_IRQ_ST);
2320 hda_mic_plugged = !(val & RT5640_JD_STATUS);
2321 dev_dbg(component->dev, "mic jack status %d\n",
2322 hda_mic_plugged);
2323
2324 snd_soc_component_update_bits(component, RT5640_IRQ_CTRL1,
2325 RT5640_JD_P_MASK, !hda_mic_plugged << RT5640_JD_P_SFT);
2326
2327 if (hda_mic_plugged)
2328 jack_type |= SND_JACK_MICROPHONE;
2329
2330 /* headphone jack */
2331 val = snd_soc_component_read(component, RT5640_DUMMY2);
2332 hda_hp_plugged = !(val & (0x1 << 11));
2333 dev_dbg(component->dev, "headphone jack status %d\n",
2334 hda_hp_plugged);
2335
2336 snd_soc_component_update_bits(component, RT5640_DUMMY2,
2337 (0x1 << 10), !hda_hp_plugged << 10);
2338
2339 if (hda_hp_plugged)
2340 jack_type |= SND_JACK_HEADPHONE;
2341
2342 snd_soc_jack_report(rt5640->jack, jack_type, SND_JACK_HEADSET);
2343
2344 return;
2345 }
2346
8210804b
HG		 2347 if (!rt5640_jack_inserted(component)) {
2348 /* Jack removed, or spurious IRQ? */
2349 if (rt5640->jack->status & SND_JACK_HEADPHONE) {
b16188a2
HG		 2350 if (rt5640->jack->status & SND_JACK_MICROPHONE) {
2351 cancel_delayed_work_sync(&rt5640->bp_work);
2352 rt5640_disable_micbias1_ovcd_irq(component);
2353 rt5640_disable_micbias1_for_ovcd(component);
2354 }
2355 snd_soc_jack_report(rt5640->jack, 0,
2356 SND_JACK_HEADSET | SND_JACK_BTN_0);
8210804b
HG		 2357 dev_dbg(component->dev, "jack unplugged\n");
2358 }
2359 } else if (!(rt5640->jack->status & SND_JACK_HEADPHONE)) {
2360 /* Jack inserted */
b16188a2 2361 WARN_ON(rt5640->ovcd_irq_enabled);
8210804b 2362 rt5640_enable_micbias1_for_ovcd(component);
d21213b4 2363 status = rt5640_detect_headset(component, NULL);
b16188a2
HG		 2364 if (status == SND_JACK_HEADSET) {
2365 /* Enable ovcd IRQ for button press detect. */
2366 rt5640_enable_micbias1_ovcd_irq(component);
2367 } else {
2368 /* No more need for overcurrent detect. */
2369 rt5640_disable_micbias1_for_ovcd(component);
2370 }
8210804b
HG		 2371 dev_dbg(component->dev, "detect status %#02x\n", status);
2372 snd_soc_jack_report(rt5640->jack, status, SND_JACK_HEADSET);
b16188a2
HG		 2373 } else if (rt5640->ovcd_irq_enabled && rt5640_micbias1_ovcd(component)) {
2374 dev_dbg(component->dev, "OVCD IRQ\n");
2375
2376 /*
2377 * The ovcd IRQ keeps firing while the button is pressed, so
2378 * we disable it and start polling the button until released.
2379 *
2380 * The disable will make the IRQ pin 0 again and since we get
2381 * IRQs on both edges (so as to detect both jack plugin and
2382 * unplug) this means we will immediately get another IRQ.
2383 * The ovcd_irq_enabled check above makes the 2ND IRQ a NOP.
2384 */
2385 rt5640_disable_micbias1_ovcd_irq(component);
2386 rt5640_start_button_press_work(component);
2387
2388 /*
2389 * If the jack-detect IRQ flag goes high (unplug) after our
2390 * above rt5640_jack_inserted() check and before we have
2391 * disabled the OVCD IRQ, the IRQ pin will stay high and as
2392 * we react to edges, we miss the unplug event -> recheck.
2393 */
a3b1aaf7 2394 queue_delayed_work(system_long_wq, &rt5640->jack_work, 0);
8210804b
HG		 2395 }
2396}
2397
2398static irqreturn_t rt5640_irq(int irq, void *data)
2399{
2400 struct rt5640_priv *rt5640 = data;
051dade3
OC		 2401 int delay = 0;
2402
2403 if (rt5640->jd_src == RT5640_JD_SRC_HDA_HEADER) {
2404 cancel_delayed_work_sync(&rt5640->jack_work);
2405 delay = 100;
2406 }
8210804b
HG		 2407
2408 if (rt5640->jack)
051dade3 2409 queue_delayed_work(system_long_wq, &rt5640->jack_work, delay);
8210804b
HG		 2410
2411 return IRQ_HANDLED;
2412}
2413
701d636a
HG		 2414static irqreturn_t rt5640_jd_gpio_irq(int irq, void *data)
2415{
2416 struct rt5640_priv *rt5640 = data;
2417
2418 queue_delayed_work(system_long_wq, &rt5640->jack_work,
2419 msecs_to_jiffies(JACK_SETTLE_TIME));
2420
2421 return IRQ_HANDLED;
2422}
2423
8210804b
HG		 2424static void rt5640_cancel_work(void *data)
2425{
2426 struct rt5640_priv *rt5640 = data;
2427
a3b1aaf7 2428 cancel_delayed_work_sync(&rt5640->jack_work);
b16188a2 2429 cancel_delayed_work_sync(&rt5640->bp_work);
8210804b
HG		 2430}
2431
e3f2a660
HG		 2432void rt5640_set_ovcd_params(struct snd_soc_component *component)
2433{
2434 struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
2435
2436 snd_soc_component_write(component, RT5640_PR_BASE + RT5640_BIAS_CUR4,
2437 0xa800 | rt5640->ovcd_sf);
2438
2439 snd_soc_component_update_bits(component, RT5640_MICBIAS,
2440 RT5640_MIC1_OVTH_MASK | RT5640_MIC1_OVCD_MASK,
2441 rt5640->ovcd_th | RT5640_MIC1_OVCD_EN);
2442
2443 /*
2444 * The over-current-detect is only reliable in detecting the absence
2445 * of over-current, when the mic-contact in the jack is short-circuited,
2446 * the hardware periodically retries if it can apply the bias-current
2447 * leading to the ovcd status flip-flopping 1-0-1 with it being 0 about
2448 * 10% of the time, as we poll the ovcd status bit we might hit that
2449 * 10%, so we enable sticky mode and when checking OVCD we clear the
2450 * status, msleep() a bit and then check to get a reliable reading.
2451 */
2452 snd_soc_component_update_bits(component, RT5640_IRQ_CTRL2,
2453 RT5640_MB1_OC_STKY_MASK, RT5640_MB1_OC_STKY_EN);
2454}
2455EXPORT_SYMBOL_GPL(rt5640_set_ovcd_params);
2456
5caab9f4
HG		 2457static void rt5640_disable_jack_detect(struct snd_soc_component *component)
2458{
2459 struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
2460
2461 /*
2462 * soc_remove_component() force-disables jack and thus rt5640->jack
2463 * could be NULL at the time of driver's module unloading.
2464 */
2465 if (!rt5640->jack)
2466 return;
2467
701d636a
HG		 2468 if (rt5640->jd_gpio_irq_requested)
2469 free_irq(rt5640->jd_gpio_irq, rt5640);
2470
2471 if (rt5640->irq_requested)
2472 free_irq(rt5640->irq, rt5640);
2473
5caab9f4
HG		 2474 rt5640_cancel_work(rt5640);
2475
2476 if (rt5640->jack->status & SND_JACK_MICROPHONE) {
2477 rt5640_disable_micbias1_ovcd_irq(component);
2478 rt5640_disable_micbias1_for_ovcd(component);
2479 snd_soc_jack_report(rt5640->jack, 0, SND_JACK_BTN_0);
2480 }
2481
701d636a
HG		 2482 rt5640->jd_gpio_irq_requested = false;
2483 rt5640->irq_requested = false;
2484 rt5640->jd_gpio = NULL;
5caab9f4
HG		 2485 rt5640->jack = NULL;
2486}
2487
8210804b 2488static void rt5640_enable_jack_detect(struct snd_soc_component *component,
b35a9ab4
HG		 2489 struct snd_soc_jack *jack,
2490 struct rt5640_set_jack_data *jack_data)
8210804b
HG		 2491{
2492 struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
15d54840 2493 int ret;
8210804b
HG		 2494
2495 /* Select JD-source */
2496 snd_soc_component_update_bits(component, RT5640_JD_CTRL,
b2ddf399 2497 RT5640_JD_MASK, rt5640->jd_src << RT5640_JD_SFT);
8210804b
HG		 2498
2499 /* Selecting GPIO01 as an interrupt */
2500 snd_soc_component_update_bits(component, RT5640_GPIO_CTRL1,
2501 RT5640_GP1_PIN_MASK, RT5640_GP1_PIN_IRQ);
2502
2503 /* Set GPIO1 output */
2504 snd_soc_component_update_bits(component, RT5640_GPIO_CTRL3,
2505 RT5640_GP1_PF_MASK, RT5640_GP1_PF_OUT);
2506
8210804b
HG		 2507 snd_soc_component_write(component, RT5640_DUMMY1, 0x3f41);
2508
e3f2a660 2509 rt5640_set_ovcd_params(component);
8210804b 2510
b16188a2
HG		 2511 /*
2512 * All IRQs get or-ed together, so we need the jack IRQ to report 0
2513 * when a jack is inserted so that the OVCD IRQ then toggles the IRQ
2514 * pin 0/1 instead of it being stuck to 1. So we invert the JD polarity
2515 * on systems where the hardware does not already do this.
2516 */
b2ddf399
OC		 2517 if (rt5640->jd_inverted) {
2518 if (rt5640->jd_src == RT5640_JD_SRC_JD1_IN4P)
2519 snd_soc_component_write(component, RT5640_IRQ_CTRL1,
2520 RT5640_IRQ_JD_NOR);
2521 else if (rt5640->jd_src == RT5640_JD_SRC_JD2_IN4N)
2522 snd_soc_component_update_bits(component, RT5640_DUMMY2,
2523 RT5640_IRQ_JD2_MASK | RT5640_JD2_MASK,
2524 RT5640_IRQ_JD2_NOR | RT5640_JD2_EN);
2525 } else {
2526 if (rt5640->jd_src == RT5640_JD_SRC_JD1_IN4P)
2527 snd_soc_component_write(component, RT5640_IRQ_CTRL1,
2528 RT5640_IRQ_JD_NOR | RT5640_JD_P_INV);
2529 else if (rt5640->jd_src == RT5640_JD_SRC_JD2_IN4N)
2530 snd_soc_component_update_bits(component, RT5640_DUMMY2,
2531 RT5640_IRQ_JD2_MASK | RT5640_JD2_P_MASK |
2532 RT5640_JD2_MASK,
2533 RT5640_IRQ_JD2_NOR | RT5640_JD2_P_INV |
2534 RT5640_JD2_EN);
2535 }
8210804b
HG		 2536
2537 rt5640->jack = jack;
b16188a2
HG		 2538 if (rt5640->jack->status & SND_JACK_MICROPHONE) {
2539 rt5640_enable_micbias1_for_ovcd(component);
2540 rt5640_enable_micbias1_ovcd_irq(component);
2541 }
2542
b35a9ab4
HG		 2543 if (jack_data && jack_data->codec_irq_override)
2544 rt5640->irq = jack_data->codec_irq_override;
2545
701d636a
HG		 2546 if (jack_data && jack_data->jd_gpio) {
2547 rt5640->jd_gpio = jack_data->jd_gpio;
2548 rt5640->jd_gpio_irq = gpiod_to_irq(rt5640->jd_gpio);
2549
2550 ret = request_irq(rt5640->jd_gpio_irq, rt5640_jd_gpio_irq,
2551 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
2552 "rt5640-jd-gpio", rt5640);
2553 if (ret) {
2554 dev_warn(component->dev, "Failed to request jd GPIO IRQ %d: %d\n",
2555 rt5640->jd_gpio_irq, ret);
2556 rt5640_disable_jack_detect(component);
2557 return;
2558 }
2559 rt5640->jd_gpio_irq_requested = true;
2560 }
2561
83229680
OC		 2562 if (jack_data && jack_data->use_platform_clock)
2563 rt5640->use_platform_clock = jack_data->use_platform_clock;
2564
15d54840
HG		 2565 ret = request_irq(rt5640->irq, rt5640_irq,
2566 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
2567 "rt5640", rt5640);
2568 if (ret) {
2569 dev_warn(component->dev, "Failed to reguest IRQ %d: %d\n", rt5640->irq, ret);
15d54840
HG		 2570 rt5640_disable_jack_detect(component);
2571 return;
2572 }
701d636a 2573 rt5640->irq_requested = true;
15d54840 2574
8210804b 2575 /* sync initial jack state */
a3b1aaf7 2576 queue_delayed_work(system_long_wq, &rt5640->jack_work, 0);
8210804b
HG		 2577}
2578
8dbefb20
OC		 2579static const struct snd_soc_dapm_route rt5640_hda_jack_dapm_routes[] = {
2580 {"IN1P", NULL, "MICBIAS1"},
2581 {"IN2P", NULL, "MICBIAS1"},
2582 {"IN3P", NULL, "MICBIAS1"},
2583};
2584
2b9c8d2b
OC		 2585static void rt5640_enable_hda_jack_detect(
2586 struct snd_soc_component *component, struct snd_soc_jack *jack)
2587{
2588 struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
8dbefb20
OC		 2589 struct snd_soc_dapm_context *dapm =
2590 snd_soc_component_get_dapm(component);
2b9c8d2b
OC		 2591 int ret;
2592
2593 /* Select JD1 for Mic */
2594 snd_soc_component_update_bits(component, RT5640_JD_CTRL,
2595 RT5640_JD_MASK, RT5640_JD_JD1_IN4P);
2596 snd_soc_component_write(component, RT5640_IRQ_CTRL1, RT5640_IRQ_JD_NOR);
2597
2598 /* Select JD2 for Headphone */
2599 snd_soc_component_update_bits(component, RT5640_DUMMY2, 0x1100, 0x1100);
2600
2601 /* Selecting GPIO01 as an interrupt */
2602 snd_soc_component_update_bits(component, RT5640_GPIO_CTRL1,
2603 RT5640_GP1_PIN_MASK, RT5640_GP1_PIN_IRQ);
2604
2605 /* Set GPIO1 output */
2606 snd_soc_component_update_bits(component, RT5640_GPIO_CTRL3,
2607 RT5640_GP1_PF_MASK, RT5640_GP1_PF_OUT);
2608
e3dd4424 2609 snd_soc_component_update_bits(component, RT5640_DUMMY1, 0x400, 0x0);
2b9c8d2b 2610
051dade3 2611 snd_soc_component_update_bits(component, RT5640_PWR_ANLG1,
afb176d4
OC		 2612 RT5640_PWR_VREF2 | RT5640_PWR_MB | RT5640_PWR_BG,
2613 RT5640_PWR_VREF2 | RT5640_PWR_MB | RT5640_PWR_BG);
051dade3
OC		 2614 usleep_range(10000, 15000);
2615 snd_soc_component_update_bits(component, RT5640_PWR_ANLG1,
2616 RT5640_PWR_FV2, RT5640_PWR_FV2);
2617
2b9c8d2b
OC		 2618 rt5640->jack = jack;
2619
2620 ret = request_irq(rt5640->irq, rt5640_irq,
2621 IRQF_TRIGGER_RISING | IRQF_ONESHOT, "rt5640", rt5640);
2622 if (ret) {
2623 dev_warn(component->dev, "Failed to reguest IRQ %d: %d\n", rt5640->irq, ret);
2624 rt5640->irq = -ENXIO;
2625 return;
2626 }
2627
2628 /* sync initial jack state */
a3b1aaf7 2629 queue_delayed_work(system_long_wq, &rt5640->jack_work, 0);
8dbefb20
OC		 2630
2631 snd_soc_dapm_add_routes(dapm, rt5640_hda_jack_dapm_routes,
2632 ARRAY_SIZE(rt5640_hda_jack_dapm_routes));
2b9c8d2b
OC		 2633}
2634
8210804b
HG		 2635static int rt5640_set_jack(struct snd_soc_component *component,
2636 struct snd_soc_jack *jack, void *data)
2637{
2b9c8d2b
OC		 2638 struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
2639
2640 if (jack) {
2641 if (rt5640->jd_src == RT5640_JD_SRC_HDA_HEADER)
2642 rt5640_enable_hda_jack_detect(component, jack);
2643 else
b35a9ab4 2644 rt5640_enable_jack_detect(component, jack, data);
2b9c8d2b 2645 } else {
8210804b 2646 rt5640_disable_jack_detect(component);
2b9c8d2b 2647 }
8210804b
HG		 2648
2649 return 0;
2650}
2651
d5a41b5d 2652static int rt5640_probe(struct snd_soc_component *component)
997b0520 2653{
d5a41b5d
KM		 2654 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
2655 struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
fb509fa9
HG		 2656 u32 dmic1_data_pin = 0;
2657 u32 dmic2_data_pin = 0;
2658 bool dmic_en = false;
2659 u32 val;
997b0520 2660
6049af00 2661 /* Check if MCLK provided */
d5a41b5d 2662 rt5640->mclk = devm_clk_get(component->dev, "mclk");
6049af00
SZ		 2663 if (PTR_ERR(rt5640->mclk) == -EPROBE_DEFER)
2664 return -EPROBE_DEFER;
2665
d5a41b5d 2666 rt5640->component = component;
997b0520 2667
d5a41b5d 2668 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
997b0520 2669
d5a41b5d
KM		 2670 snd_soc_component_update_bits(component, RT5640_DUMMY1, 0x0301, 0x0301);
2671 snd_soc_component_update_bits(component, RT5640_MICBIAS, 0x0030, 0x0030);
2672 snd_soc_component_update_bits(component, RT5640_DSP_PATH2, 0xfc00, 0x0c00);
997b0520 2673
467a2553 2674 switch (snd_soc_component_read(component, RT5640_RESET) & RT5640_ID_MASK) {
8bfc6d2d
BL		 2675 case RT5640_ID_5640:
2676 case RT5640_ID_5642:
d5a41b5d 2677 snd_soc_add_component_controls(component,
022d21f0
OC		 2678 rt5640_specific_snd_controls,
2679 ARRAY_SIZE(rt5640_specific_snd_controls));
76aad74b 2680 snd_soc_dapm_new_controls(dapm,
022d21f0
OC		 2681 rt5640_specific_dapm_widgets,
2682 ARRAY_SIZE(rt5640_specific_dapm_widgets));
76aad74b 2683 snd_soc_dapm_add_routes(dapm,
022d21f0
OC		 2684 rt5640_specific_dapm_routes,
2685 ARRAY_SIZE(rt5640_specific_dapm_routes));
2686 break;
8bfc6d2d 2687 case RT5640_ID_5639:
76aad74b 2688 snd_soc_dapm_new_controls(dapm,
022d21f0
OC		 2689 rt5639_specific_dapm_widgets,
2690 ARRAY_SIZE(rt5639_specific_dapm_widgets));
76aad74b 2691 snd_soc_dapm_add_routes(dapm,
022d21f0
OC		 2692 rt5639_specific_dapm_routes,
2693 ARRAY_SIZE(rt5639_specific_dapm_routes));
2694 break;
57f174f4 2695 default:
d5a41b5d 2696 dev_err(component->dev,
57f174f4
BL		 2697 "The driver is for RT5639 RT5640 or RT5642 only\n");
2698 return -ENODEV;
022d21f0
OC		 2699 }
2700
988a5e01
HG		 2701 /*
2702 * Note on some platforms the platform code may need to add device-props
2703 * rather then relying only on properties set by the firmware.
2704 * Therefor the property parsing MUST be done here, rather then from
2705 * rt5640_i2c_probe(), so that the platform-code can attach extra
2706 * properties before calling snd_soc_register_card().
2707 */
2708 if (device_property_read_bool(component->dev, "realtek,in1-differential"))
2709 snd_soc_component_update_bits(component, RT5640_IN1_IN2,
2710 RT5640_IN_DF1, RT5640_IN_DF1);
2711
2712 if (device_property_read_bool(component->dev, "realtek,in2-differential"))
2713 snd_soc_component_update_bits(component, RT5640_IN3_IN4,
2714 RT5640_IN_DF2, RT5640_IN_DF2);
2715
2716 if (device_property_read_bool(component->dev, "realtek,in3-differential"))
2717 snd_soc_component_update_bits(component, RT5640_IN1_IN2,
2718 RT5640_IN_DF2, RT5640_IN_DF2);
2719
44b54f54
OJ		 2720 if (device_property_read_bool(component->dev, "realtek,lout-differential"))
2721 snd_soc_component_update_bits(component, RT5640_DUMMY1,
2722 RT5640_EN_LOUT_DF, RT5640_EN_LOUT_DF);
2723
fb509fa9
HG		 2724 if (device_property_read_u32(component->dev, "realtek,dmic1-data-pin",
2725 &val) == 0 && val) {
2726 dmic1_data_pin = val - 1;
2727 dmic_en = true;
2728 }
2729
2730 if (device_property_read_u32(component->dev, "realtek,dmic2-data-pin",
2731 &val) == 0 && val) {
2732 dmic2_data_pin = val - 1;
2733 dmic_en = true;
2734 }
2735
2736 if (dmic_en)
2737 rt5640_dmic_enable(component, dmic1_data_pin, dmic2_data_pin);
2738
8210804b
HG		 2739 if (device_property_read_u32(component->dev,
2740 "realtek,jack-detect-source", &val) == 0) {
b2ddf399
OC		 2741 if (val <= RT5640_JD_SRC_HDA_HEADER)
2742 rt5640->jd_src = val;
051dade3 2743 else
8210804b
HG		 2744 dev_warn(component->dev, "Warning: Invalid jack-detect-source value: %d, leaving jack-detect disabled\n",
2745 val);
2746 }
2747
2748 if (!device_property_read_bool(component->dev, "realtek,jack-detect-not-inverted"))
2749 rt5640->jd_inverted = true;
2750
2751 /*
2752 * Testing on various boards has shown that good defaults for the OVCD
2753 * threshold and scale-factor are 2000µA and 0.75. For an effective
2754 * limit of 1500µA, this seems to be more reliable then 1500µA and 1.0.
2755 */
2756 rt5640->ovcd_th = RT5640_MIC1_OVTH_2000UA;
2757 rt5640->ovcd_sf = RT5640_MIC_OVCD_SF_0P75;
2758
2759 if (device_property_read_u32(component->dev,
2760 "realtek,over-current-threshold-microamp", &val) == 0) {
2761 switch (val) {
2762 case 600:
2763 rt5640->ovcd_th = RT5640_MIC1_OVTH_600UA;
2764 break;
2765 case 1500:
2766 rt5640->ovcd_th = RT5640_MIC1_OVTH_1500UA;
2767 break;
2768 case 2000:
2769 rt5640->ovcd_th = RT5640_MIC1_OVTH_2000UA;
2770 break;
2771 default:
2772 dev_warn(component->dev, "Warning: Invalid over-current-threshold-microamp value: %d, defaulting to 2000uA\n",
2773 val);
2774 }
2775 }
2776
2777 if (device_property_read_u32(component->dev,
2778 "realtek,over-current-scale-factor", &val) == 0) {
2779 if (val <= RT5640_OVCD_SF_1P5)
2780 rt5640->ovcd_sf = val << RT5640_MIC_OVCD_SF_SFT;
2781 else
2782 dev_warn(component->dev, "Warning: Invalid over-current-scale-factor value: %d, defaulting to 0.75\n",
2783 val);
2784 }
2785
997b0520
BL		 2786 return 0;
2787}
2788
d5a41b5d 2789static void rt5640_remove(struct snd_soc_component *component)
997b0520 2790{
d5a41b5d 2791 rt5640_reset(component);
997b0520
BL		 2792}
2793
2794#ifdef CONFIG_PM
d5a41b5d 2795static int rt5640_suspend(struct snd_soc_component *component)
997b0520 2796{
d5a41b5d 2797 struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
997b0520 2798
5fabcc90
OC		 2799 if (rt5640->irq) {
2800 /* disable jack interrupts during system suspend */
2801 disable_irq(rt5640->irq);
2802 }
2803
2b9c8d2b 2804 rt5640_cancel_work(rt5640);
d5a41b5d
KM		 2805 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
2806 rt5640_reset(component);
997b0520
BL		 2807 regcache_cache_only(rt5640->regmap, true);
2808 regcache_mark_dirty(rt5640->regmap);
8e3ebf5e
HG		 2809 if (gpio_is_valid(rt5640->ldo1_en))
2810 gpio_set_value_cansleep(rt5640->ldo1_en, 0);
997b0520
BL		 2811
2812 return 0;
2813}
2814
d5a41b5d 2815static int rt5640_resume(struct snd_soc_component *component)
997b0520 2816{
d5a41b5d 2817 struct rt5640_priv *rt5640 = snd_soc_component_get_drvdata(component);
e58f301e 2818
8e3ebf5e
HG		 2819 if (gpio_is_valid(rt5640->ldo1_en)) {
2820 gpio_set_value_cansleep(rt5640->ldo1_en, 1);
e58f301e
MB		 2821 msleep(400);
2822 }
997b0520 2823
4c9185be
OC		 2824 regcache_cache_only(rt5640->regmap, false);
2825 regcache_sync(rt5640->regmap);
2826
5fabcc90
OC		 2827 if (rt5640->irq)
2828 enable_irq(rt5640->irq);
2829
a2d6d84d 2830 if (rt5640->jack) {
b2ddf399 2831 if (rt5640->jd_src == RT5640_JD_SRC_HDA_HEADER) {
2b9c8d2b
OC		 2832 snd_soc_component_update_bits(component,
2833 RT5640_DUMMY2, 0x1100, 0x1100);
b2ddf399
OC		 2834 } else {
2835 if (rt5640->jd_inverted) {
2836 if (rt5640->jd_src == RT5640_JD_SRC_JD2_IN4N)
2837 snd_soc_component_update_bits(
2838 component, RT5640_DUMMY2,
2839 RT5640_IRQ_JD2_MASK |
2840 RT5640_JD2_MASK,
2841 RT5640_IRQ_JD2_NOR |
2842 RT5640_JD2_EN);
2843
2844 } else {
2845 if (rt5640->jd_src == RT5640_JD_SRC_JD2_IN4N)
2846 snd_soc_component_update_bits(
2847 component, RT5640_DUMMY2,
2848 RT5640_IRQ_JD2_MASK |
2849 RT5640_JD2_P_MASK |
2850 RT5640_JD2_MASK,
2851 RT5640_IRQ_JD2_NOR |
2852 RT5640_JD2_P_INV |
2853 RT5640_JD2_EN);
2854 }
2855 }
2b9c8d2b 2856
a3b1aaf7 2857 queue_delayed_work(system_long_wq, &rt5640->jack_work, 0);
2b9c8d2b
OC		 2858 }
2859
997b0520
BL		 2860 return 0;
2861}
2862#else
2863#define rt5640_suspend NULL
2864#define rt5640_resume NULL
2865#endif
2866
2867#define RT5640_STEREO_RATES SNDRV_PCM_RATE_8000_96000
2868#define RT5640_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
2869 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
2870
9be94aea 2871static const struct snd_soc_dai_ops rt5640_aif_dai_ops = {
997b0520
BL		 2872 .hw_params = rt5640_hw_params,
2873 .set_fmt = rt5640_set_dai_fmt,
2874 .set_sysclk = rt5640_set_dai_sysclk,
2875 .set_pll = rt5640_set_dai_pll,
2876};
2877
9be94aea 2878static struct snd_soc_dai_driver rt5640_dai[] = {
997b0520
BL		 2879 {
2880 .name = "rt5640-aif1",
2881 .id = RT5640_AIF1,
2882 .playback = {
2883 .stream_name = "AIF1 Playback",
2884 .channels_min = 1,
2885 .channels_max = 2,
2886 .rates = RT5640_STEREO_RATES,
2887 .formats = RT5640_FORMATS,
2888 },
2889 .capture = {
2890 .stream_name = "AIF1 Capture",
2891 .channels_min = 1,
2892 .channels_max = 2,
2893 .rates = RT5640_STEREO_RATES,
2894 .formats = RT5640_FORMATS,
2895 },
2896 .ops = &rt5640_aif_dai_ops,
2897 },
2898 {
2899 .name = "rt5640-aif2",
2900 .id = RT5640_AIF2,
2901 .playback = {
2902 .stream_name = "AIF2 Playback",
2903 .channels_min = 1,
2904 .channels_max = 2,
2905 .rates = RT5640_STEREO_RATES,
2906 .formats = RT5640_FORMATS,
2907 },
2908 .capture = {
2909 .stream_name = "AIF2 Capture",
2910 .channels_min = 1,
2911 .channels_max = 2,
2912 .rates = RT5640_STEREO_RATES,
2913 .formats = RT5640_FORMATS,
2914 },
2915 .ops = &rt5640_aif_dai_ops,
2916 },
2917};
2918
d5a41b5d
KM		 2919static const struct snd_soc_component_driver soc_component_dev_rt5640 = {
2920 .probe = rt5640_probe,
2921 .remove = rt5640_remove,
2922 .suspend = rt5640_suspend,
2923 .resume = rt5640_resume,
2924 .set_bias_level = rt5640_set_bias_level,
8210804b 2925 .set_jack = rt5640_set_jack,
d5a41b5d
KM		 2926 .controls = rt5640_snd_controls,
2927 .num_controls = ARRAY_SIZE(rt5640_snd_controls),
2928 .dapm_widgets = rt5640_dapm_widgets,
2929 .num_dapm_widgets = ARRAY_SIZE(rt5640_dapm_widgets),
2930 .dapm_routes = rt5640_dapm_routes,
2931 .num_dapm_routes = ARRAY_SIZE(rt5640_dapm_routes),
2932 .use_pmdown_time = 1,
2933 .endianness = 1,
997b0520
BL		 2934};
2935
2936static const struct regmap_config rt5640_regmap = {
2937 .reg_bits = 8,
2938 .val_bits = 16,
1c96a2f6
DF		 2939 .use_single_read = true,
2940 .use_single_write = true,
997b0520
BL		 2941
2942 .max_register = RT5640_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5640_ranges) *
2943 RT5640_PR_SPACING),
2944 .volatile_reg = rt5640_volatile_register,
2945 .readable_reg = rt5640_readable_register,
2946
2947 .cache_type = REGCACHE_RBTREE,
2948 .reg_defaults = rt5640_reg,
2949 .num_reg_defaults = ARRAY_SIZE(rt5640_reg),
2950 .ranges = rt5640_ranges,
2951 .num_ranges = ARRAY_SIZE(rt5640_ranges),
2952};
2953
2954static const struct i2c_device_id rt5640_i2c_id[] = {
2955 { "rt5640", 0 },
b0c27846 2956 { "rt5639", 0 },
8bfc6d2d 2957 { "rt5642", 0 },
997b0520
BL		 2958 { }
2959};
2960MODULE_DEVICE_TABLE(i2c, rt5640_i2c_id);
2961
03a620d8
SW		 2962#if defined(CONFIG_OF)
2963static const struct of_device_id rt5640_of_match[] = {
33fcec29 2964 { .compatible = "realtek,rt5639", },
03a620d8
SW		 2965 { .compatible = "realtek,rt5640", },
2966 {},
2967};
2968MODULE_DEVICE_TABLE(of, rt5640_of_match);
2969#endif
2970
32fcb97b 2971#ifdef CONFIG_ACPI
b895dc2c 2972static const struct acpi_device_id rt5640_acpi_match[] = {
02b80773 2973 { "INT33CA", 0 },
03200140 2974 { "10EC3276", 0 },
b31b2b6d 2975 { "10EC5640", 0 },
3463667a 2976 { "10EC5642", 0 },
55fc2056 2977 { "INTCCFFD", 0 },
02b80773
LG		 2978 { },
2979};
2980MODULE_DEVICE_TABLE(acpi, rt5640_acpi_match);
32fcb97b 2981#endif
02b80773 2982
dcad9f03
SW		 2983static int rt5640_parse_dt(struct rt5640_priv *rt5640, struct device_node *np)
2984{
8e3ebf5e 2985 rt5640->ldo1_en = of_get_named_gpio(np, "realtek,ldo1-en-gpios", 0);
dcad9f03
SW		 2986 /*
2987 * LDO1_EN is optional (it may be statically tied on the board).
2988 * -ENOENT means that the property doesn't exist, i.e. there is no
2989 * GPIO, so is not an error. Any other error code means the property
2990 * exists, but could not be parsed.
2991 */
8e3ebf5e
HG		 2992 if (!gpio_is_valid(rt5640->ldo1_en) &&
2993 (rt5640->ldo1_en != -ENOENT))
2994 return rt5640->ldo1_en;
dcad9f03
SW		 2995
2996 return 0;
2997}
2998
35b88858 2999static int rt5640_i2c_probe(struct i2c_client *i2c)
997b0520 3000{
997b0520
BL		 3001 struct rt5640_priv *rt5640;
3002 int ret;
3003 unsigned int val;
3004
3005 rt5640 = devm_kzalloc(&i2c->dev,
3006 sizeof(struct rt5640_priv),
3007 GFP_KERNEL);
3008 if (NULL == rt5640)
3009 return -ENOMEM;
dcad9f03
SW		 3010 i2c_set_clientdata(i2c, rt5640);
3011
8e3ebf5e 3012 if (i2c->dev.of_node) {
dcad9f03
SW		 3013 ret = rt5640_parse_dt(rt5640, i2c->dev.of_node);
3014 if (ret)
3015 return ret;
3016 } else
8e3ebf5e 3017 rt5640->ldo1_en = -EINVAL;
997b0520
BL		 3018
3019 rt5640->regmap = devm_regmap_init_i2c(i2c, &rt5640_regmap);
3020 if (IS_ERR(rt5640->regmap)) {
3021 ret = PTR_ERR(rt5640->regmap);
3022 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
3023 ret);
3024 return ret;
3025 }
3026
8e3ebf5e
HG		 3027 if (gpio_is_valid(rt5640->ldo1_en)) {
3028 ret = devm_gpio_request_one(&i2c->dev, rt5640->ldo1_en,
997b0520
BL		 3029 GPIOF_OUT_INIT_HIGH,
3030 "RT5640 LDO1_EN");
3031 if (ret < 0) {
3032 dev_err(&i2c->dev, "Failed to request LDO1_EN %d: %d\n",
8e3ebf5e 3033 rt5640->ldo1_en, ret);
997b0520
BL		 3034 return ret;
3035 }
3036 msleep(400);
3037 }
3038
3039 regmap_read(rt5640->regmap, RT5640_VENDOR_ID2, &val);
3441e524 3040 if (val != RT5640_DEVICE_ID) {
997b0520 3041 dev_err(&i2c->dev,
818454d1 3042 "Device with ID register %#x is not rt5640/39\n", val);
997b0520
BL		 3043 return -ENODEV;
3044 }
3045
3046 regmap_write(rt5640->regmap, RT5640_RESET, 0);
3047
3048 ret = regmap_register_patch(rt5640->regmap, init_list,
3049 ARRAY_SIZE(init_list));
3050 if (ret != 0)
3051 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
3052
25fb7062
BL		 3053 regmap_update_bits(rt5640->regmap, RT5640_DUMMY1,
3054 RT5640_MCLK_DET, RT5640_MCLK_DET);
3055
e0a99927 3056 rt5640->hp_mute = true;
8210804b 3057 rt5640->irq = i2c->irq;
b16188a2 3058 INIT_DELAYED_WORK(&rt5640->bp_work, rt5640_button_press_work);
a3b1aaf7 3059 INIT_DELAYED_WORK(&rt5640->jack_work, rt5640_jack_work);
8210804b
HG		 3060
3061 /* Make sure work is stopped on probe-error / remove */
3062 ret = devm_add_action_or_reset(&i2c->dev, rt5640_cancel_work, rt5640);
3063 if (ret)
3064 return ret;
3065
d5a41b5d
KM		 3066 return devm_snd_soc_register_component(&i2c->dev,
3067 &soc_component_dev_rt5640,
1657caf5 3068 rt5640_dai, ARRAY_SIZE(rt5640_dai));
997b0520
BL		 3069}
3070
9be94aea 3071static struct i2c_driver rt5640_i2c_driver = {
997b0520
BL		 3072 .driver = {
3073 .name = "rt5640",
02b80773 3074 .acpi_match_table = ACPI_PTR(rt5640_acpi_match),
03a620d8 3075 .of_match_table = of_match_ptr(rt5640_of_match),
997b0520 3076 },
35b88858 3077 .probe_new = rt5640_i2c_probe,
997b0520
BL		 3078 .id_table = rt5640_i2c_id,
3079};
3080module_i2c_driver(rt5640_i2c_driver);
3081
b0c27846 3082MODULE_DESCRIPTION("ASoC RT5640/RT5639 driver");
997b0520
BL		 3083MODULE_AUTHOR("Johnny Hsu <johnnyhsu@realtek.com>");
3084MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)