Commit | Line | Data |
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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
07cf7cba BL |
2 | /* |
3 | * rt286.c -- RT286 ALSA SoC audio codec driver | |
4 | * | |
5 | * Copyright 2013 Realtek Semiconductor Corp. | |
6 | * Author: Bard Liao <bardliao@realtek.com> | |
07cf7cba BL |
7 | */ |
8 | ||
9 | #include <linux/module.h> | |
10 | #include <linux/moduleparam.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/pm.h> | |
14 | #include <linux/i2c.h> | |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/spi/spi.h> | |
6c67cde2 | 17 | #include <linux/dmi.h> |
07cf7cba BL |
18 | #include <linux/acpi.h> |
19 | #include <sound/core.h> | |
20 | #include <sound/pcm.h> | |
21 | #include <sound/pcm_params.h> | |
22 | #include <sound/soc.h> | |
23 | #include <sound/soc-dapm.h> | |
24 | #include <sound/initval.h> | |
25 | #include <sound/tlv.h> | |
26 | #include <sound/jack.h> | |
27 | #include <linux/workqueue.h> | |
28 | #include <sound/rt286.h> | |
07cf7cba | 29 | |
bc08f96b | 30 | #include "rl6347a.h" |
07cf7cba BL |
31 | #include "rt286.h" |
32 | ||
33 | #define RT286_VENDOR_ID 0x10ec0286 | |
3ab888db | 34 | #define RT288_VENDOR_ID 0x10ec0288 |
07cf7cba BL |
35 | |
36 | struct rt286_priv { | |
dc6d84c6 | 37 | struct reg_default *index_cache; |
bc08f96b | 38 | int index_cache_size; |
07cf7cba | 39 | struct regmap *regmap; |
45101122 | 40 | struct snd_soc_component *component; |
07cf7cba BL |
41 | struct rt286_platform_data pdata; |
42 | struct i2c_client *i2c; | |
43 | struct snd_soc_jack *jack; | |
44 | struct delayed_work jack_detect_work; | |
45 | int sys_clk; | |
6879db76 | 46 | int clk_id; |
07cf7cba BL |
47 | }; |
48 | ||
c418a84a | 49 | static const struct reg_default rt286_index_def[] = { |
07cf7cba BL |
50 | { 0x01, 0xaaaa }, |
51 | { 0x02, 0x8aaa }, | |
52 | { 0x03, 0x0002 }, | |
53 | { 0x04, 0xaf01 }, | |
54 | { 0x08, 0x000d }, | |
55 | { 0x09, 0xd810 }, | |
b7a29767 | 56 | { 0x0a, 0x0120 }, |
07cf7cba | 57 | { 0x0b, 0x0000 }, |
bc6c4e45 | 58 | { 0x0d, 0x2800 }, |
07cf7cba BL |
59 | { 0x0f, 0x0000 }, |
60 | { 0x19, 0x0a17 }, | |
61 | { 0x20, 0x0020 }, | |
62 | { 0x33, 0x0208 }, | |
63 | { 0x49, 0x0004 }, | |
64 | { 0x4f, 0x50e9 }, | |
b7a29767 | 65 | { 0x50, 0x2000 }, |
07cf7cba | 66 | { 0x63, 0x2902 }, |
bc6c4e45 BL |
67 | { 0x67, 0x1111 }, |
68 | { 0x68, 0x1016 }, | |
69 | { 0x69, 0x273f }, | |
07cf7cba BL |
70 | }; |
71 | #define INDEX_CACHE_SIZE ARRAY_SIZE(rt286_index_def) | |
72 | ||
73 | static const struct reg_default rt286_reg[] = { | |
74 | { 0x00170500, 0x00000400 }, | |
75 | { 0x00220000, 0x00000031 }, | |
76 | { 0x00239000, 0x0000007f }, | |
77 | { 0x0023a000, 0x0000007f }, | |
78 | { 0x00270500, 0x00000400 }, | |
79 | { 0x00370500, 0x00000400 }, | |
80 | { 0x00870500, 0x00000400 }, | |
81 | { 0x00920000, 0x00000031 }, | |
82 | { 0x00935000, 0x000000c3 }, | |
83 | { 0x00936000, 0x000000c3 }, | |
84 | { 0x00970500, 0x00000400 }, | |
85 | { 0x00b37000, 0x00000097 }, | |
86 | { 0x00b37200, 0x00000097 }, | |
87 | { 0x00b37300, 0x00000097 }, | |
88 | { 0x00c37000, 0x00000000 }, | |
89 | { 0x00c37100, 0x00000080 }, | |
90 | { 0x01270500, 0x00000400 }, | |
91 | { 0x01370500, 0x00000400 }, | |
92 | { 0x01371f00, 0x411111f0 }, | |
93 | { 0x01439000, 0x00000080 }, | |
94 | { 0x0143a000, 0x00000080 }, | |
95 | { 0x01470700, 0x00000000 }, | |
96 | { 0x01470500, 0x00000400 }, | |
97 | { 0x01470c00, 0x00000000 }, | |
98 | { 0x01470100, 0x00000000 }, | |
99 | { 0x01837000, 0x00000000 }, | |
100 | { 0x01870500, 0x00000400 }, | |
101 | { 0x02050000, 0x00000000 }, | |
102 | { 0x02139000, 0x00000080 }, | |
103 | { 0x0213a000, 0x00000080 }, | |
104 | { 0x02170100, 0x00000000 }, | |
105 | { 0x02170500, 0x00000400 }, | |
106 | { 0x02170700, 0x00000000 }, | |
107 | { 0x02270100, 0x00000000 }, | |
108 | { 0x02370100, 0x00000000 }, | |
07cf7cba BL |
109 | { 0x01870700, 0x00000020 }, |
110 | { 0x00830000, 0x000000c3 }, | |
111 | { 0x00930000, 0x000000c3 }, | |
112 | { 0x01270700, 0x00000000 }, | |
113 | }; | |
114 | ||
115 | static bool rt286_volatile_register(struct device *dev, unsigned int reg) | |
116 | { | |
117 | switch (reg) { | |
118 | case 0 ... 0xff: | |
119 | case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID): | |
120 | case RT286_GET_HP_SENSE: | |
121 | case RT286_GET_MIC1_SENSE: | |
122 | case RT286_PROC_COEF: | |
123 | return true; | |
124 | default: | |
125 | return false; | |
126 | } | |
127 | ||
128 | ||
129 | } | |
130 | ||
131 | static bool rt286_readable_register(struct device *dev, unsigned int reg) | |
132 | { | |
133 | switch (reg) { | |
134 | case 0 ... 0xff: | |
135 | case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID): | |
136 | case RT286_GET_HP_SENSE: | |
137 | case RT286_GET_MIC1_SENSE: | |
138 | case RT286_SET_AUDIO_POWER: | |
139 | case RT286_SET_HPO_POWER: | |
140 | case RT286_SET_SPK_POWER: | |
141 | case RT286_SET_DMIC1_POWER: | |
142 | case RT286_SPK_MUX: | |
143 | case RT286_HPO_MUX: | |
144 | case RT286_ADC0_MUX: | |
145 | case RT286_ADC1_MUX: | |
146 | case RT286_SET_MIC1: | |
147 | case RT286_SET_PIN_HPO: | |
148 | case RT286_SET_PIN_SPK: | |
149 | case RT286_SET_PIN_DMIC1: | |
150 | case RT286_SPK_EAPD: | |
151 | case RT286_SET_AMP_GAIN_HPO: | |
152 | case RT286_SET_DMIC2_DEFAULT: | |
153 | case RT286_DACL_GAIN: | |
154 | case RT286_DACR_GAIN: | |
155 | case RT286_ADCL_GAIN: | |
156 | case RT286_ADCR_GAIN: | |
157 | case RT286_MIC_GAIN: | |
158 | case RT286_SPOL_GAIN: | |
159 | case RT286_SPOR_GAIN: | |
160 | case RT286_HPOL_GAIN: | |
161 | case RT286_HPOR_GAIN: | |
162 | case RT286_F_DAC_SWITCH: | |
163 | case RT286_F_RECMIX_SWITCH: | |
164 | case RT286_REC_MIC_SWITCH: | |
165 | case RT286_REC_I2S_SWITCH: | |
166 | case RT286_REC_LINE_SWITCH: | |
167 | case RT286_REC_BEEP_SWITCH: | |
168 | case RT286_DAC_FORMAT: | |
169 | case RT286_ADC_FORMAT: | |
170 | case RT286_COEF_INDEX: | |
171 | case RT286_PROC_COEF: | |
172 | case RT286_SET_AMP_GAIN_ADC_IN1: | |
173 | case RT286_SET_AMP_GAIN_ADC_IN2: | |
cd8499d5 DW |
174 | case RT286_SET_GPIO_MASK: |
175 | case RT286_SET_GPIO_DIRECTION: | |
176 | case RT286_SET_GPIO_DATA: | |
07cf7cba BL |
177 | case RT286_SET_POWER(RT286_DAC_OUT1): |
178 | case RT286_SET_POWER(RT286_DAC_OUT2): | |
179 | case RT286_SET_POWER(RT286_ADC_IN1): | |
180 | case RT286_SET_POWER(RT286_ADC_IN2): | |
181 | case RT286_SET_POWER(RT286_DMIC2): | |
182 | case RT286_SET_POWER(RT286_MIC1): | |
183 | return true; | |
184 | default: | |
185 | return false; | |
186 | } | |
187 | } | |
188 | ||
81f3dfe1 | 189 | #ifdef CONFIG_PM |
45101122 | 190 | static void rt286_index_sync(struct snd_soc_component *component) |
07cf7cba | 191 | { |
45101122 | 192 | struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component); |
07cf7cba BL |
193 | int i; |
194 | ||
195 | for (i = 0; i < INDEX_CACHE_SIZE; i++) { | |
45101122 | 196 | snd_soc_component_write(component, rt286->index_cache[i].reg, |
07cf7cba BL |
197 | rt286->index_cache[i].def); |
198 | } | |
199 | } | |
81f3dfe1 | 200 | #endif |
07cf7cba BL |
201 | |
202 | static int rt286_support_power_controls[] = { | |
203 | RT286_DAC_OUT1, | |
204 | RT286_DAC_OUT2, | |
205 | RT286_ADC_IN1, | |
206 | RT286_ADC_IN2, | |
207 | RT286_MIC1, | |
208 | RT286_DMIC1, | |
209 | RT286_DMIC2, | |
210 | RT286_SPK_OUT, | |
211 | RT286_HP_OUT, | |
212 | }; | |
213 | #define RT286_POWER_REG_LEN ARRAY_SIZE(rt286_support_power_controls) | |
214 | ||
90f601ef | 215 | static int rt286_jack_detect(struct rt286_priv *rt286, bool *hp, bool *mic) |
07cf7cba | 216 | { |
b1cd8457 | 217 | struct snd_soc_dapm_context *dapm; |
07cf7cba | 218 | unsigned int val, buf; |
07cf7cba BL |
219 | |
220 | *hp = false; | |
221 | *mic = false; | |
222 | ||
45101122 | 223 | if (!rt286->component) |
28d1ad09 | 224 | return -EINVAL; |
b1cd8457 | 225 | |
45101122 | 226 | dapm = snd_soc_component_get_dapm(rt286->component); |
b1cd8457 | 227 | |
07cf7cba | 228 | if (rt286->pdata.cbj_en) { |
90f601ef | 229 | regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf); |
07cf7cba BL |
230 | *hp = buf & 0x80000000; |
231 | if (*hp) { | |
232 | /* power on HV,VERF */ | |
90f601ef | 233 | regmap_update_bits(rt286->regmap, |
6879db76 BL |
234 | RT286_DC_GAIN, 0x200, 0x200); |
235 | ||
b1cd8457 LPC |
236 | snd_soc_dapm_force_enable_pin(dapm, "HV"); |
237 | snd_soc_dapm_force_enable_pin(dapm, "VREF"); | |
07cf7cba | 238 | /* power LDO1 */ |
b1cd8457 LPC |
239 | snd_soc_dapm_force_enable_pin(dapm, "LDO1"); |
240 | snd_soc_dapm_sync(dapm); | |
07cf7cba | 241 | |
6879db76 BL |
242 | regmap_write(rt286->regmap, RT286_SET_MIC1, 0x24); |
243 | msleep(50); | |
07cf7cba | 244 | |
6879db76 BL |
245 | regmap_update_bits(rt286->regmap, |
246 | RT286_CBJ_CTRL1, 0xfcc0, 0xd400); | |
247 | msleep(300); | |
248 | regmap_read(rt286->regmap, RT286_CBJ_CTRL2, &val); | |
07cf7cba | 249 | |
6879db76 | 250 | if (0x0070 == (val & 0x0070)) { |
07cf7cba | 251 | *mic = true; |
07cf7cba | 252 | } else { |
6879db76 BL |
253 | regmap_update_bits(rt286->regmap, |
254 | RT286_CBJ_CTRL1, 0xfcc0, 0xe400); | |
255 | msleep(300); | |
256 | regmap_read(rt286->regmap, | |
257 | RT286_CBJ_CTRL2, &val); | |
b15c3ea7 | 258 | if (0x0070 == (val & 0x0070)) { |
6879db76 | 259 | *mic = true; |
b15c3ea7 | 260 | } else { |
6879db76 | 261 | *mic = false; |
b15c3ea7 DW |
262 | regmap_update_bits(rt286->regmap, |
263 | RT286_CBJ_CTRL1, | |
264 | 0xfcc0, 0xc400); | |
265 | } | |
07cf7cba | 266 | } |
b15c3ea7 | 267 | |
90f601ef | 268 | regmap_update_bits(rt286->regmap, |
6879db76 | 269 | RT286_DC_GAIN, 0x200, 0x0); |
07cf7cba | 270 | |
6879db76 | 271 | } else { |
07cf7cba | 272 | *mic = false; |
6879db76 | 273 | regmap_write(rt286->regmap, RT286_SET_MIC1, 0x20); |
6d514c72 BL |
274 | regmap_update_bits(rt286->regmap, |
275 | RT286_CBJ_CTRL1, 0x0400, 0x0000); | |
07cf7cba BL |
276 | } |
277 | } else { | |
90f601ef | 278 | regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf); |
07cf7cba | 279 | *hp = buf & 0x80000000; |
90f601ef | 280 | regmap_read(rt286->regmap, RT286_GET_MIC1_SENSE, &buf); |
07cf7cba BL |
281 | *mic = buf & 0x80000000; |
282 | } | |
12eb3ad0 SF |
283 | |
284 | if (!*hp) { | |
8153362e BL |
285 | snd_soc_dapm_disable_pin(dapm, "HV"); |
286 | snd_soc_dapm_disable_pin(dapm, "VREF"); | |
b1cd8457 | 287 | snd_soc_dapm_disable_pin(dapm, "LDO1"); |
12eb3ad0 SF |
288 | snd_soc_dapm_sync(dapm); |
289 | } | |
6879db76 | 290 | |
07cf7cba BL |
291 | return 0; |
292 | } | |
293 | ||
294 | static void rt286_jack_detect_work(struct work_struct *work) | |
295 | { | |
296 | struct rt286_priv *rt286 = | |
297 | container_of(work, struct rt286_priv, jack_detect_work.work); | |
298 | int status = 0; | |
299 | bool hp = false; | |
300 | bool mic = false; | |
301 | ||
90f601ef | 302 | rt286_jack_detect(rt286, &hp, &mic); |
07cf7cba | 303 | |
af3b2b54 | 304 | if (hp) |
07cf7cba BL |
305 | status |= SND_JACK_HEADPHONE; |
306 | ||
af3b2b54 | 307 | if (mic) |
07cf7cba BL |
308 | status |= SND_JACK_MICROPHONE; |
309 | ||
310 | snd_soc_jack_report(rt286->jack, status, | |
311 | SND_JACK_MICROPHONE | SND_JACK_HEADPHONE); | |
312 | } | |
313 | ||
3082afe0 CR |
314 | static int rt286_mic_detect(struct snd_soc_component *component, |
315 | struct snd_soc_jack *jack, void *data) | |
07cf7cba | 316 | { |
45101122 KM |
317 | struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); |
318 | struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component); | |
07cf7cba BL |
319 | |
320 | rt286->jack = jack; | |
321 | ||
e2cef68d JY |
322 | if (jack) { |
323 | /* enable IRQ */ | |
5af76d5c | 324 | if (rt286->jack->status & SND_JACK_HEADPHONE) |
b1cd8457 | 325 | snd_soc_dapm_force_enable_pin(dapm, "LDO1"); |
e2cef68d JY |
326 | regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x2, 0x2); |
327 | /* Send an initial empty report */ | |
328 | snd_soc_jack_report(rt286->jack, rt286->jack->status, | |
329 | SND_JACK_MICROPHONE | SND_JACK_HEADPHONE); | |
330 | } else { | |
331 | /* disable IRQ */ | |
332 | regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x2, 0x0); | |
b1cd8457 | 333 | snd_soc_dapm_disable_pin(dapm, "LDO1"); |
e2cef68d | 334 | } |
b1cd8457 | 335 | snd_soc_dapm_sync(dapm); |
07cf7cba BL |
336 | |
337 | return 0; | |
338 | } | |
07cf7cba | 339 | |
6879db76 BL |
340 | static int is_mclk_mode(struct snd_soc_dapm_widget *source, |
341 | struct snd_soc_dapm_widget *sink) | |
342 | { | |
45101122 KM |
343 | struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); |
344 | struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component); | |
6879db76 BL |
345 | |
346 | if (rt286->clk_id == RT286_SCLK_S_MCLK) | |
347 | return 1; | |
348 | else | |
349 | return 0; | |
350 | } | |
351 | ||
07cf7cba BL |
352 | static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0); |
353 | static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0); | |
354 | ||
355 | static const struct snd_kcontrol_new rt286_snd_controls[] = { | |
356 | SOC_DOUBLE_R_TLV("DAC0 Playback Volume", RT286_DACL_GAIN, | |
357 | RT286_DACR_GAIN, 0, 0x7f, 0, out_vol_tlv), | |
54d96a40 BL |
358 | SOC_DOUBLE_R("ADC0 Capture Switch", RT286_ADCL_GAIN, |
359 | RT286_ADCR_GAIN, 7, 1, 1), | |
07cf7cba BL |
360 | SOC_DOUBLE_R_TLV("ADC0 Capture Volume", RT286_ADCL_GAIN, |
361 | RT286_ADCR_GAIN, 0, 0x7f, 0, out_vol_tlv), | |
362 | SOC_SINGLE_TLV("AMIC Volume", RT286_MIC_GAIN, | |
363 | 0, 0x3, 0, mic_vol_tlv), | |
364 | SOC_DOUBLE_R("Speaker Playback Switch", RT286_SPOL_GAIN, | |
365 | RT286_SPOR_GAIN, RT286_MUTE_SFT, 1, 1), | |
366 | }; | |
367 | ||
368 | /* Digital Mixer */ | |
369 | static const struct snd_kcontrol_new rt286_front_mix[] = { | |
370 | SOC_DAPM_SINGLE("DAC Switch", RT286_F_DAC_SWITCH, | |
371 | RT286_MUTE_SFT, 1, 1), | |
372 | SOC_DAPM_SINGLE("RECMIX Switch", RT286_F_RECMIX_SWITCH, | |
373 | RT286_MUTE_SFT, 1, 1), | |
374 | }; | |
375 | ||
376 | /* Analog Input Mixer */ | |
377 | static const struct snd_kcontrol_new rt286_rec_mix[] = { | |
378 | SOC_DAPM_SINGLE("Mic1 Switch", RT286_REC_MIC_SWITCH, | |
379 | RT286_MUTE_SFT, 1, 1), | |
380 | SOC_DAPM_SINGLE("I2S Switch", RT286_REC_I2S_SWITCH, | |
381 | RT286_MUTE_SFT, 1, 1), | |
382 | SOC_DAPM_SINGLE("Line1 Switch", RT286_REC_LINE_SWITCH, | |
383 | RT286_MUTE_SFT, 1, 1), | |
384 | SOC_DAPM_SINGLE("Beep Switch", RT286_REC_BEEP_SWITCH, | |
385 | RT286_MUTE_SFT, 1, 1), | |
386 | }; | |
387 | ||
388 | static const struct snd_kcontrol_new spo_enable_control = | |
389 | SOC_DAPM_SINGLE("Switch", RT286_SET_PIN_SPK, | |
390 | RT286_SET_PIN_SFT, 1, 0); | |
391 | ||
392 | static const struct snd_kcontrol_new hpol_enable_control = | |
393 | SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOL_GAIN, | |
394 | RT286_MUTE_SFT, 1, 1); | |
395 | ||
396 | static const struct snd_kcontrol_new hpor_enable_control = | |
397 | SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOR_GAIN, | |
398 | RT286_MUTE_SFT, 1, 1); | |
399 | ||
400 | /* ADC0 source */ | |
401 | static const char * const rt286_adc_src[] = { | |
402 | "Mic", "RECMIX", "Dmic" | |
403 | }; | |
404 | ||
405 | static const int rt286_adc_values[] = { | |
406 | 0, 4, 5, | |
407 | }; | |
408 | ||
409 | static SOC_VALUE_ENUM_SINGLE_DECL( | |
410 | rt286_adc0_enum, RT286_ADC0_MUX, RT286_ADC_SEL_SFT, | |
411 | RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values); | |
412 | ||
413 | static const struct snd_kcontrol_new rt286_adc0_mux = | |
414 | SOC_DAPM_ENUM("ADC 0 source", rt286_adc0_enum); | |
415 | ||
416 | static SOC_VALUE_ENUM_SINGLE_DECL( | |
417 | rt286_adc1_enum, RT286_ADC1_MUX, RT286_ADC_SEL_SFT, | |
418 | RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values); | |
419 | ||
420 | static const struct snd_kcontrol_new rt286_adc1_mux = | |
421 | SOC_DAPM_ENUM("ADC 1 source", rt286_adc1_enum); | |
422 | ||
423 | static const char * const rt286_dac_src[] = { | |
424 | "Front", "Surround" | |
425 | }; | |
426 | /* HP-OUT source */ | |
427 | static SOC_ENUM_SINGLE_DECL(rt286_hpo_enum, RT286_HPO_MUX, | |
428 | 0, rt286_dac_src); | |
429 | ||
430 | static const struct snd_kcontrol_new rt286_hpo_mux = | |
431 | SOC_DAPM_ENUM("HPO source", rt286_hpo_enum); | |
432 | ||
433 | /* SPK-OUT source */ | |
434 | static SOC_ENUM_SINGLE_DECL(rt286_spo_enum, RT286_SPK_MUX, | |
435 | 0, rt286_dac_src); | |
436 | ||
437 | static const struct snd_kcontrol_new rt286_spo_mux = | |
438 | SOC_DAPM_ENUM("SPO source", rt286_spo_enum); | |
439 | ||
440 | static int rt286_spk_event(struct snd_soc_dapm_widget *w, | |
441 | struct snd_kcontrol *kcontrol, int event) | |
442 | { | |
45101122 | 443 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); |
07cf7cba BL |
444 | |
445 | switch (event) { | |
446 | case SND_SOC_DAPM_POST_PMU: | |
45101122 | 447 | snd_soc_component_write(component, |
07cf7cba BL |
448 | RT286_SPK_EAPD, RT286_SET_EAPD_HIGH); |
449 | break; | |
450 | case SND_SOC_DAPM_PRE_PMD: | |
45101122 | 451 | snd_soc_component_write(component, |
07cf7cba BL |
452 | RT286_SPK_EAPD, RT286_SET_EAPD_LOW); |
453 | break; | |
454 | ||
455 | default: | |
456 | return 0; | |
457 | } | |
458 | ||
459 | return 0; | |
460 | } | |
461 | ||
462 | static int rt286_set_dmic1_event(struct snd_soc_dapm_widget *w, | |
463 | struct snd_kcontrol *kcontrol, int event) | |
464 | { | |
45101122 | 465 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); |
07cf7cba BL |
466 | |
467 | switch (event) { | |
468 | case SND_SOC_DAPM_POST_PMU: | |
45101122 | 469 | snd_soc_component_write(component, RT286_SET_PIN_DMIC1, 0x20); |
07cf7cba BL |
470 | break; |
471 | case SND_SOC_DAPM_PRE_PMD: | |
45101122 | 472 | snd_soc_component_write(component, RT286_SET_PIN_DMIC1, 0); |
07cf7cba BL |
473 | break; |
474 | default: | |
475 | return 0; | |
476 | } | |
477 | ||
478 | return 0; | |
479 | } | |
480 | ||
6879db76 BL |
481 | static int rt286_ldo2_event(struct snd_soc_dapm_widget *w, |
482 | struct snd_kcontrol *kcontrol, int event) | |
483 | { | |
45101122 | 484 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); |
6879db76 BL |
485 | |
486 | switch (event) { | |
487 | case SND_SOC_DAPM_POST_PMU: | |
45101122 | 488 | snd_soc_component_update_bits(component, RT286_POWER_CTRL2, 0x38, 0x08); |
6879db76 BL |
489 | break; |
490 | case SND_SOC_DAPM_PRE_PMD: | |
45101122 | 491 | snd_soc_component_update_bits(component, RT286_POWER_CTRL2, 0x38, 0x30); |
6879db76 BL |
492 | break; |
493 | default: | |
494 | return 0; | |
495 | } | |
496 | ||
497 | return 0; | |
498 | } | |
499 | ||
500 | static int rt286_mic1_event(struct snd_soc_dapm_widget *w, | |
501 | struct snd_kcontrol *kcontrol, int event) | |
502 | { | |
45101122 | 503 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); |
6879db76 BL |
504 | |
505 | switch (event) { | |
506 | case SND_SOC_DAPM_PRE_PMU: | |
45101122 | 507 | snd_soc_component_update_bits(component, |
6879db76 | 508 | RT286_A_BIAS_CTRL3, 0xc000, 0x8000); |
45101122 | 509 | snd_soc_component_update_bits(component, |
6879db76 BL |
510 | RT286_A_BIAS_CTRL2, 0xc000, 0x8000); |
511 | break; | |
512 | case SND_SOC_DAPM_POST_PMD: | |
45101122 | 513 | snd_soc_component_update_bits(component, |
6879db76 | 514 | RT286_A_BIAS_CTRL3, 0xc000, 0x0000); |
45101122 | 515 | snd_soc_component_update_bits(component, |
6879db76 BL |
516 | RT286_A_BIAS_CTRL2, 0xc000, 0x0000); |
517 | break; | |
518 | default: | |
519 | return 0; | |
520 | } | |
521 | ||
522 | return 0; | |
523 | } | |
524 | ||
07cf7cba | 525 | static const struct snd_soc_dapm_widget rt286_dapm_widgets[] = { |
6879db76 BL |
526 | SND_SOC_DAPM_SUPPLY_S("HV", 1, RT286_POWER_CTRL1, |
527 | 12, 1, NULL, 0), | |
528 | SND_SOC_DAPM_SUPPLY("VREF", RT286_POWER_CTRL1, | |
6d514c72 | 529 | 0, 1, NULL, 0), |
6879db76 BL |
530 | SND_SOC_DAPM_SUPPLY_S("LDO1", 1, RT286_POWER_CTRL2, |
531 | 2, 0, NULL, 0), | |
532 | SND_SOC_DAPM_SUPPLY_S("LDO2", 2, RT286_POWER_CTRL1, | |
533 | 13, 1, rt286_ldo2_event, SND_SOC_DAPM_PRE_PMD | | |
534 | SND_SOC_DAPM_POST_PMU), | |
535 | SND_SOC_DAPM_SUPPLY("MCLK MODE", RT286_PLL_CTRL1, | |
536 | 5, 0, NULL, 0), | |
537 | SND_SOC_DAPM_SUPPLY("MIC1 Input Buffer", SND_SOC_NOPM, | |
538 | 0, 0, rt286_mic1_event, SND_SOC_DAPM_PRE_PMU | | |
539 | SND_SOC_DAPM_POST_PMD), | |
540 | ||
07cf7cba BL |
541 | /* Input Lines */ |
542 | SND_SOC_DAPM_INPUT("DMIC1 Pin"), | |
543 | SND_SOC_DAPM_INPUT("DMIC2 Pin"), | |
544 | SND_SOC_DAPM_INPUT("MIC1"), | |
545 | SND_SOC_DAPM_INPUT("LINE1"), | |
546 | SND_SOC_DAPM_INPUT("Beep"), | |
547 | ||
548 | /* DMIC */ | |
549 | SND_SOC_DAPM_PGA_E("DMIC1", RT286_SET_POWER(RT286_DMIC1), 0, 1, | |
550 | NULL, 0, rt286_set_dmic1_event, | |
551 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), | |
552 | SND_SOC_DAPM_PGA("DMIC2", RT286_SET_POWER(RT286_DMIC2), 0, 1, | |
553 | NULL, 0), | |
554 | SND_SOC_DAPM_SUPPLY("DMIC Receiver", SND_SOC_NOPM, | |
555 | 0, 0, NULL, 0), | |
556 | ||
557 | /* REC Mixer */ | |
558 | SND_SOC_DAPM_MIXER("RECMIX", SND_SOC_NOPM, 0, 0, | |
559 | rt286_rec_mix, ARRAY_SIZE(rt286_rec_mix)), | |
560 | ||
561 | /* ADCs */ | |
562 | SND_SOC_DAPM_ADC("ADC 0", NULL, SND_SOC_NOPM, 0, 0), | |
563 | SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 0, 0), | |
564 | ||
565 | /* ADC Mux */ | |
54d96a40 BL |
566 | SND_SOC_DAPM_MUX("ADC 0 Mux", RT286_SET_POWER(RT286_ADC_IN1), 0, 1, |
567 | &rt286_adc0_mux), | |
568 | SND_SOC_DAPM_MUX("ADC 1 Mux", RT286_SET_POWER(RT286_ADC_IN2), 0, 1, | |
569 | &rt286_adc1_mux), | |
07cf7cba BL |
570 | |
571 | /* Audio Interface */ | |
572 | SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), | |
573 | SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), | |
574 | SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), | |
575 | SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), | |
576 | ||
577 | /* Output Side */ | |
578 | /* DACs */ | |
579 | SND_SOC_DAPM_DAC("DAC 0", NULL, SND_SOC_NOPM, 0, 0), | |
580 | SND_SOC_DAPM_DAC("DAC 1", NULL, SND_SOC_NOPM, 0, 0), | |
581 | ||
582 | /* Output Mux */ | |
583 | SND_SOC_DAPM_MUX("SPK Mux", SND_SOC_NOPM, 0, 0, &rt286_spo_mux), | |
584 | SND_SOC_DAPM_MUX("HPO Mux", SND_SOC_NOPM, 0, 0, &rt286_hpo_mux), | |
585 | ||
586 | SND_SOC_DAPM_SUPPLY("HP Power", RT286_SET_PIN_HPO, | |
587 | RT286_SET_PIN_SFT, 0, NULL, 0), | |
588 | ||
589 | /* Output Mixer */ | |
590 | SND_SOC_DAPM_MIXER("Front", RT286_SET_POWER(RT286_DAC_OUT1), 0, 1, | |
591 | rt286_front_mix, ARRAY_SIZE(rt286_front_mix)), | |
592 | SND_SOC_DAPM_PGA("Surround", RT286_SET_POWER(RT286_DAC_OUT2), 0, 1, | |
593 | NULL, 0), | |
594 | ||
595 | /* Output Pga */ | |
596 | SND_SOC_DAPM_SWITCH_E("SPO", SND_SOC_NOPM, 0, 0, | |
597 | &spo_enable_control, rt286_spk_event, | |
598 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), | |
599 | SND_SOC_DAPM_SWITCH("HPO L", SND_SOC_NOPM, 0, 0, | |
600 | &hpol_enable_control), | |
601 | SND_SOC_DAPM_SWITCH("HPO R", SND_SOC_NOPM, 0, 0, | |
602 | &hpor_enable_control), | |
603 | ||
604 | /* Output Lines */ | |
605 | SND_SOC_DAPM_OUTPUT("SPOL"), | |
606 | SND_SOC_DAPM_OUTPUT("SPOR"), | |
607 | SND_SOC_DAPM_OUTPUT("HPO Pin"), | |
608 | SND_SOC_DAPM_OUTPUT("SPDIF"), | |
609 | }; | |
610 | ||
611 | static const struct snd_soc_dapm_route rt286_dapm_routes[] = { | |
6879db76 BL |
612 | {"ADC 0", NULL, "MCLK MODE", is_mclk_mode}, |
613 | {"ADC 1", NULL, "MCLK MODE", is_mclk_mode}, | |
614 | {"Front", NULL, "MCLK MODE", is_mclk_mode}, | |
615 | {"Surround", NULL, "MCLK MODE", is_mclk_mode}, | |
616 | ||
617 | {"HP Power", NULL, "LDO1"}, | |
618 | {"HP Power", NULL, "LDO2"}, | |
619 | ||
620 | {"MIC1", NULL, "LDO1"}, | |
621 | {"MIC1", NULL, "LDO2"}, | |
622 | {"MIC1", NULL, "HV"}, | |
623 | {"MIC1", NULL, "VREF"}, | |
624 | {"MIC1", NULL, "MIC1 Input Buffer"}, | |
625 | ||
626 | {"SPO", NULL, "LDO1"}, | |
627 | {"SPO", NULL, "LDO2"}, | |
628 | {"SPO", NULL, "HV"}, | |
629 | {"SPO", NULL, "VREF"}, | |
630 | ||
07cf7cba BL |
631 | {"DMIC1", NULL, "DMIC1 Pin"}, |
632 | {"DMIC2", NULL, "DMIC2 Pin"}, | |
633 | {"DMIC1", NULL, "DMIC Receiver"}, | |
634 | {"DMIC2", NULL, "DMIC Receiver"}, | |
635 | ||
636 | {"RECMIX", "Beep Switch", "Beep"}, | |
637 | {"RECMIX", "Line1 Switch", "LINE1"}, | |
638 | {"RECMIX", "Mic1 Switch", "MIC1"}, | |
639 | ||
640 | {"ADC 0 Mux", "Dmic", "DMIC1"}, | |
641 | {"ADC 0 Mux", "RECMIX", "RECMIX"}, | |
642 | {"ADC 0 Mux", "Mic", "MIC1"}, | |
643 | {"ADC 1 Mux", "Dmic", "DMIC2"}, | |
644 | {"ADC 1 Mux", "RECMIX", "RECMIX"}, | |
645 | {"ADC 1 Mux", "Mic", "MIC1"}, | |
646 | ||
647 | {"ADC 0", NULL, "ADC 0 Mux"}, | |
648 | {"ADC 1", NULL, "ADC 1 Mux"}, | |
649 | ||
650 | {"AIF1TX", NULL, "ADC 0"}, | |
651 | {"AIF2TX", NULL, "ADC 1"}, | |
652 | ||
653 | {"DAC 0", NULL, "AIF1RX"}, | |
654 | {"DAC 1", NULL, "AIF2RX"}, | |
655 | ||
656 | {"Front", "DAC Switch", "DAC 0"}, | |
657 | {"Front", "RECMIX Switch", "RECMIX"}, | |
658 | ||
659 | {"Surround", NULL, "DAC 1"}, | |
660 | ||
661 | {"SPK Mux", "Front", "Front"}, | |
662 | {"SPK Mux", "Surround", "Surround"}, | |
663 | ||
664 | {"HPO Mux", "Front", "Front"}, | |
665 | {"HPO Mux", "Surround", "Surround"}, | |
666 | ||
667 | {"SPO", "Switch", "SPK Mux"}, | |
668 | {"HPO L", "Switch", "HPO Mux"}, | |
669 | {"HPO R", "Switch", "HPO Mux"}, | |
670 | {"HPO L", NULL, "HP Power"}, | |
671 | {"HPO R", NULL, "HP Power"}, | |
672 | ||
673 | {"SPOL", NULL, "SPO"}, | |
674 | {"SPOR", NULL, "SPO"}, | |
675 | {"HPO Pin", NULL, "HPO L"}, | |
676 | {"HPO Pin", NULL, "HPO R"}, | |
677 | }; | |
678 | ||
679 | static int rt286_hw_params(struct snd_pcm_substream *substream, | |
680 | struct snd_pcm_hw_params *params, | |
681 | struct snd_soc_dai *dai) | |
682 | { | |
45101122 KM |
683 | struct snd_soc_component *component = dai->component; |
684 | struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component); | |
07cf7cba BL |
685 | unsigned int val = 0; |
686 | int d_len_code; | |
687 | ||
688 | switch (params_rate(params)) { | |
689 | /* bit 14 0:48K 1:44.1K */ | |
690 | case 44100: | |
691 | val |= 0x4000; | |
692 | break; | |
693 | case 48000: | |
694 | break; | |
695 | default: | |
45101122 | 696 | dev_err(component->dev, "Unsupported sample rate %d\n", |
07cf7cba BL |
697 | params_rate(params)); |
698 | return -EINVAL; | |
699 | } | |
700 | switch (rt286->sys_clk) { | |
701 | case 12288000: | |
702 | case 24576000: | |
703 | if (params_rate(params) != 48000) { | |
45101122 | 704 | dev_err(component->dev, "Sys_clk is not matched (%d %d)\n", |
07cf7cba BL |
705 | params_rate(params), rt286->sys_clk); |
706 | return -EINVAL; | |
707 | } | |
708 | break; | |
709 | case 11289600: | |
710 | case 22579200: | |
711 | if (params_rate(params) != 44100) { | |
45101122 | 712 | dev_err(component->dev, "Sys_clk is not matched (%d %d)\n", |
07cf7cba BL |
713 | params_rate(params), rt286->sys_clk); |
714 | return -EINVAL; | |
715 | } | |
716 | break; | |
717 | } | |
718 | ||
719 | if (params_channels(params) <= 16) { | |
720 | /* bit 3:0 Number of Channel */ | |
721 | val |= (params_channels(params) - 1); | |
722 | } else { | |
45101122 | 723 | dev_err(component->dev, "Unsupported channels %d\n", |
07cf7cba BL |
724 | params_channels(params)); |
725 | return -EINVAL; | |
726 | } | |
727 | ||
07cf7cba BL |
728 | switch (params_width(params)) { |
729 | /* bit 6:4 Bits per Sample */ | |
730 | case 16: | |
731 | d_len_code = 0; | |
732 | val |= (0x1 << 4); | |
733 | break; | |
734 | case 32: | |
735 | d_len_code = 2; | |
736 | val |= (0x4 << 4); | |
737 | break; | |
738 | case 20: | |
739 | d_len_code = 1; | |
740 | val |= (0x2 << 4); | |
741 | break; | |
742 | case 24: | |
743 | d_len_code = 2; | |
744 | val |= (0x3 << 4); | |
745 | break; | |
746 | case 8: | |
747 | d_len_code = 3; | |
748 | break; | |
749 | default: | |
750 | return -EINVAL; | |
751 | } | |
752 | ||
45101122 | 753 | snd_soc_component_update_bits(component, |
07cf7cba | 754 | RT286_I2S_CTRL1, 0x0018, d_len_code << 3); |
45101122 | 755 | dev_dbg(component->dev, "format val = 0x%x\n", val); |
07cf7cba | 756 | |
45101122 KM |
757 | snd_soc_component_update_bits(component, RT286_DAC_FORMAT, 0x407f, val); |
758 | snd_soc_component_update_bits(component, RT286_ADC_FORMAT, 0x407f, val); | |
07cf7cba BL |
759 | |
760 | return 0; | |
761 | } | |
762 | ||
763 | static int rt286_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) | |
764 | { | |
45101122 | 765 | struct snd_soc_component *component = dai->component; |
07cf7cba BL |
766 | |
767 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
768 | case SND_SOC_DAIFMT_CBM_CFM: | |
45101122 | 769 | snd_soc_component_update_bits(component, |
07cf7cba BL |
770 | RT286_I2S_CTRL1, 0x800, 0x800); |
771 | break; | |
772 | case SND_SOC_DAIFMT_CBS_CFS: | |
45101122 | 773 | snd_soc_component_update_bits(component, |
07cf7cba BL |
774 | RT286_I2S_CTRL1, 0x800, 0x0); |
775 | break; | |
776 | default: | |
777 | return -EINVAL; | |
778 | } | |
779 | ||
780 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
781 | case SND_SOC_DAIFMT_I2S: | |
45101122 | 782 | snd_soc_component_update_bits(component, |
07cf7cba BL |
783 | RT286_I2S_CTRL1, 0x300, 0x0); |
784 | break; | |
785 | case SND_SOC_DAIFMT_LEFT_J: | |
45101122 | 786 | snd_soc_component_update_bits(component, |
07cf7cba BL |
787 | RT286_I2S_CTRL1, 0x300, 0x1 << 8); |
788 | break; | |
789 | case SND_SOC_DAIFMT_DSP_A: | |
45101122 | 790 | snd_soc_component_update_bits(component, |
07cf7cba BL |
791 | RT286_I2S_CTRL1, 0x300, 0x2 << 8); |
792 | break; | |
793 | case SND_SOC_DAIFMT_DSP_B: | |
45101122 | 794 | snd_soc_component_update_bits(component, |
07cf7cba BL |
795 | RT286_I2S_CTRL1, 0x300, 0x3 << 8); |
796 | break; | |
797 | default: | |
798 | return -EINVAL; | |
799 | } | |
800 | /* bit 15 Stream Type 0:PCM 1:Non-PCM */ | |
45101122 KM |
801 | snd_soc_component_update_bits(component, RT286_DAC_FORMAT, 0x8000, 0); |
802 | snd_soc_component_update_bits(component, RT286_ADC_FORMAT, 0x8000, 0); | |
07cf7cba BL |
803 | |
804 | return 0; | |
805 | } | |
806 | ||
807 | static int rt286_set_dai_sysclk(struct snd_soc_dai *dai, | |
808 | int clk_id, unsigned int freq, int dir) | |
809 | { | |
45101122 KM |
810 | struct snd_soc_component *component = dai->component; |
811 | struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component); | |
07cf7cba | 812 | |
45101122 | 813 | dev_dbg(component->dev, "%s freq=%d\n", __func__, freq); |
07cf7cba BL |
814 | |
815 | if (RT286_SCLK_S_MCLK == clk_id) { | |
45101122 | 816 | snd_soc_component_update_bits(component, |
07cf7cba | 817 | RT286_I2S_CTRL2, 0x0100, 0x0); |
45101122 | 818 | snd_soc_component_update_bits(component, |
07cf7cba BL |
819 | RT286_PLL_CTRL1, 0x20, 0x20); |
820 | } else { | |
45101122 | 821 | snd_soc_component_update_bits(component, |
07cf7cba | 822 | RT286_I2S_CTRL2, 0x0100, 0x0100); |
45101122 | 823 | snd_soc_component_update_bits(component, |
07cf7cba | 824 | RT286_PLL_CTRL, 0x4, 0x4); |
45101122 | 825 | snd_soc_component_update_bits(component, |
07cf7cba BL |
826 | RT286_PLL_CTRL1, 0x20, 0x0); |
827 | } | |
828 | ||
829 | switch (freq) { | |
830 | case 19200000: | |
831 | if (RT286_SCLK_S_MCLK == clk_id) { | |
45101122 | 832 | dev_err(component->dev, "Should not use MCLK\n"); |
07cf7cba BL |
833 | return -EINVAL; |
834 | } | |
45101122 | 835 | snd_soc_component_update_bits(component, |
07cf7cba BL |
836 | RT286_I2S_CTRL2, 0x40, 0x40); |
837 | break; | |
838 | case 24000000: | |
839 | if (RT286_SCLK_S_MCLK == clk_id) { | |
45101122 | 840 | dev_err(component->dev, "Should not use MCLK\n"); |
07cf7cba BL |
841 | return -EINVAL; |
842 | } | |
45101122 | 843 | snd_soc_component_update_bits(component, |
07cf7cba BL |
844 | RT286_I2S_CTRL2, 0x40, 0x0); |
845 | break; | |
846 | case 12288000: | |
847 | case 11289600: | |
45101122 | 848 | snd_soc_component_update_bits(component, |
07cf7cba | 849 | RT286_I2S_CTRL2, 0x8, 0x0); |
45101122 | 850 | snd_soc_component_update_bits(component, |
07cf7cba BL |
851 | RT286_CLK_DIV, 0xfc1e, 0x0004); |
852 | break; | |
853 | case 24576000: | |
854 | case 22579200: | |
45101122 | 855 | snd_soc_component_update_bits(component, |
07cf7cba | 856 | RT286_I2S_CTRL2, 0x8, 0x8); |
45101122 | 857 | snd_soc_component_update_bits(component, |
07cf7cba BL |
858 | RT286_CLK_DIV, 0xfc1e, 0x5406); |
859 | break; | |
860 | default: | |
45101122 | 861 | dev_err(component->dev, "Unsupported system clock\n"); |
07cf7cba BL |
862 | return -EINVAL; |
863 | } | |
864 | ||
865 | rt286->sys_clk = freq; | |
6879db76 | 866 | rt286->clk_id = clk_id; |
07cf7cba BL |
867 | |
868 | return 0; | |
869 | } | |
870 | ||
871 | static int rt286_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) | |
872 | { | |
45101122 | 873 | struct snd_soc_component *component = dai->component; |
07cf7cba | 874 | |
45101122 | 875 | dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio); |
07cf7cba | 876 | if (50 == ratio) |
45101122 | 877 | snd_soc_component_update_bits(component, |
07cf7cba BL |
878 | RT286_I2S_CTRL1, 0x1000, 0x1000); |
879 | else | |
45101122 | 880 | snd_soc_component_update_bits(component, |
07cf7cba BL |
881 | RT286_I2S_CTRL1, 0x1000, 0x0); |
882 | ||
883 | ||
884 | return 0; | |
885 | } | |
886 | ||
45101122 | 887 | static int rt286_set_bias_level(struct snd_soc_component *component, |
07cf7cba BL |
888 | enum snd_soc_bias_level level) |
889 | { | |
890 | switch (level) { | |
891 | case SND_SOC_BIAS_PREPARE: | |
45101122 KM |
892 | if (SND_SOC_BIAS_STANDBY == snd_soc_component_get_bias_level(component)) { |
893 | snd_soc_component_write(component, | |
07cf7cba | 894 | RT286_SET_AUDIO_POWER, AC_PWRST_D0); |
45101122 | 895 | snd_soc_component_update_bits(component, |
bc6c4e45 BL |
896 | RT286_DC_GAIN, 0x200, 0x200); |
897 | } | |
898 | break; | |
899 | ||
900 | case SND_SOC_BIAS_ON: | |
901 | mdelay(10); | |
45101122 | 902 | snd_soc_component_update_bits(component, |
6879db76 BL |
903 | RT286_DC_GAIN, 0x200, 0x0); |
904 | ||
07cf7cba BL |
905 | break; |
906 | ||
907 | case SND_SOC_BIAS_STANDBY: | |
45101122 | 908 | snd_soc_component_write(component, |
07cf7cba BL |
909 | RT286_SET_AUDIO_POWER, AC_PWRST_D3); |
910 | break; | |
911 | ||
912 | default: | |
913 | break; | |
914 | } | |
07cf7cba BL |
915 | |
916 | return 0; | |
917 | } | |
918 | ||
919 | static irqreturn_t rt286_irq(int irq, void *data) | |
920 | { | |
921 | struct rt286_priv *rt286 = data; | |
922 | bool hp = false; | |
923 | bool mic = false; | |
924 | int status = 0; | |
925 | ||
90f601ef | 926 | rt286_jack_detect(rt286, &hp, &mic); |
07cf7cba BL |
927 | |
928 | /* Clear IRQ */ | |
90f601ef | 929 | regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x1, 0x1); |
07cf7cba | 930 | |
af3b2b54 | 931 | if (hp) |
07cf7cba BL |
932 | status |= SND_JACK_HEADPHONE; |
933 | ||
af3b2b54 | 934 | if (mic) |
07cf7cba BL |
935 | status |= SND_JACK_MICROPHONE; |
936 | ||
937 | snd_soc_jack_report(rt286->jack, status, | |
938 | SND_JACK_MICROPHONE | SND_JACK_HEADPHONE); | |
939 | ||
940 | pm_wakeup_event(&rt286->i2c->dev, 300); | |
941 | ||
942 | return IRQ_HANDLED; | |
943 | } | |
944 | ||
45101122 | 945 | static int rt286_probe(struct snd_soc_component *component) |
07cf7cba | 946 | { |
45101122 | 947 | struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component); |
07cf7cba | 948 | |
45101122 | 949 | rt286->component = component; |
3082afe0 | 950 | INIT_DELAYED_WORK(&rt286->jack_detect_work, rt286_jack_detect_work); |
90f601ef | 951 | |
3082afe0 | 952 | if (rt286->i2c->irq) |
90f601ef | 953 | schedule_delayed_work(&rt286->jack_detect_work, |
3082afe0 | 954 | msecs_to_jiffies(50)); |
07cf7cba BL |
955 | return 0; |
956 | } | |
957 | ||
45101122 | 958 | static void rt286_remove(struct snd_soc_component *component) |
07cf7cba | 959 | { |
45101122 | 960 | struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component); |
07cf7cba BL |
961 | |
962 | cancel_delayed_work_sync(&rt286->jack_detect_work); | |
c1d7ebda | 963 | rt286->component = NULL; |
07cf7cba BL |
964 | } |
965 | ||
966 | #ifdef CONFIG_PM | |
45101122 | 967 | static int rt286_suspend(struct snd_soc_component *component) |
07cf7cba | 968 | { |
45101122 | 969 | struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component); |
07cf7cba BL |
970 | |
971 | regcache_cache_only(rt286->regmap, true); | |
972 | regcache_mark_dirty(rt286->regmap); | |
973 | ||
974 | return 0; | |
975 | } | |
976 | ||
45101122 | 977 | static int rt286_resume(struct snd_soc_component *component) |
07cf7cba | 978 | { |
45101122 | 979 | struct rt286_priv *rt286 = snd_soc_component_get_drvdata(component); |
07cf7cba BL |
980 | |
981 | regcache_cache_only(rt286->regmap, false); | |
45101122 | 982 | rt286_index_sync(component); |
07cf7cba BL |
983 | regcache_sync(rt286->regmap); |
984 | ||
985 | return 0; | |
986 | } | |
987 | #else | |
988 | #define rt286_suspend NULL | |
989 | #define rt286_resume NULL | |
990 | #endif | |
991 | ||
992 | #define RT286_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) | |
993 | #define RT286_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ | |
994 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) | |
995 | ||
996 | static const struct snd_soc_dai_ops rt286_aif_dai_ops = { | |
997 | .hw_params = rt286_hw_params, | |
998 | .set_fmt = rt286_set_dai_fmt, | |
999 | .set_sysclk = rt286_set_dai_sysclk, | |
1000 | .set_bclk_ratio = rt286_set_bclk_ratio, | |
1001 | }; | |
1002 | ||
1003 | static struct snd_soc_dai_driver rt286_dai[] = { | |
1004 | { | |
1005 | .name = "rt286-aif1", | |
1006 | .id = RT286_AIF1, | |
1007 | .playback = { | |
1008 | .stream_name = "AIF1 Playback", | |
1009 | .channels_min = 1, | |
1010 | .channels_max = 2, | |
1011 | .rates = RT286_STEREO_RATES, | |
1012 | .formats = RT286_FORMATS, | |
1013 | }, | |
1014 | .capture = { | |
1015 | .stream_name = "AIF1 Capture", | |
1016 | .channels_min = 1, | |
1017 | .channels_max = 2, | |
1018 | .rates = RT286_STEREO_RATES, | |
1019 | .formats = RT286_FORMATS, | |
1020 | }, | |
1021 | .ops = &rt286_aif_dai_ops, | |
bc03b391 | 1022 | .symmetric_rate = 1, |
07cf7cba BL |
1023 | }, |
1024 | { | |
1025 | .name = "rt286-aif2", | |
1026 | .id = RT286_AIF2, | |
1027 | .playback = { | |
1028 | .stream_name = "AIF2 Playback", | |
1029 | .channels_min = 1, | |
1030 | .channels_max = 2, | |
1031 | .rates = RT286_STEREO_RATES, | |
1032 | .formats = RT286_FORMATS, | |
1033 | }, | |
1034 | .capture = { | |
1035 | .stream_name = "AIF2 Capture", | |
1036 | .channels_min = 1, | |
1037 | .channels_max = 2, | |
1038 | .rates = RT286_STEREO_RATES, | |
1039 | .formats = RT286_FORMATS, | |
1040 | }, | |
1041 | .ops = &rt286_aif_dai_ops, | |
bc03b391 | 1042 | .symmetric_rate = 1, |
07cf7cba BL |
1043 | }, |
1044 | ||
1045 | }; | |
1046 | ||
45101122 KM |
1047 | static const struct snd_soc_component_driver soc_component_dev_rt286 = { |
1048 | .probe = rt286_probe, | |
1049 | .remove = rt286_remove, | |
1050 | .suspend = rt286_suspend, | |
1051 | .resume = rt286_resume, | |
1052 | .set_bias_level = rt286_set_bias_level, | |
3082afe0 | 1053 | .set_jack = rt286_mic_detect, |
45101122 KM |
1054 | .controls = rt286_snd_controls, |
1055 | .num_controls = ARRAY_SIZE(rt286_snd_controls), | |
1056 | .dapm_widgets = rt286_dapm_widgets, | |
1057 | .num_dapm_widgets = ARRAY_SIZE(rt286_dapm_widgets), | |
1058 | .dapm_routes = rt286_dapm_routes, | |
1059 | .num_dapm_routes = ARRAY_SIZE(rt286_dapm_routes), | |
1060 | .use_pmdown_time = 1, | |
1061 | .endianness = 1, | |
07cf7cba BL |
1062 | }; |
1063 | ||
1064 | static const struct regmap_config rt286_regmap = { | |
1065 | .reg_bits = 32, | |
1066 | .val_bits = 32, | |
1067 | .max_register = 0x02370100, | |
1068 | .volatile_reg = rt286_volatile_register, | |
1069 | .readable_reg = rt286_readable_register, | |
bc08f96b OC |
1070 | .reg_write = rl6347a_hw_write, |
1071 | .reg_read = rl6347a_hw_read, | |
07cf7cba BL |
1072 | .cache_type = REGCACHE_RBTREE, |
1073 | .reg_defaults = rt286_reg, | |
1074 | .num_reg_defaults = ARRAY_SIZE(rt286_reg), | |
1075 | }; | |
1076 | ||
1077 | static const struct i2c_device_id rt286_i2c_id[] = { | |
1078 | {"rt286", 0}, | |
3ab888db | 1079 | {"rt288", 0}, |
07cf7cba BL |
1080 | {} |
1081 | }; | |
1082 | MODULE_DEVICE_TABLE(i2c, rt286_i2c_id); | |
1083 | ||
56bbfbfd | 1084 | #ifdef CONFIG_ACPI |
07cf7cba BL |
1085 | static const struct acpi_device_id rt286_acpi_match[] = { |
1086 | { "INT343A", 0 }, | |
1087 | {}, | |
1088 | }; | |
1089 | MODULE_DEVICE_TABLE(acpi, rt286_acpi_match); | |
56bbfbfd | 1090 | #endif |
07cf7cba | 1091 | |
a5afdc5b | 1092 | static const struct dmi_system_id force_combo_jack_table[] = { |
6c67cde2 BL |
1093 | { |
1094 | .ident = "Intel Wilson Beach", | |
1095 | .matches = { | |
1096 | DMI_MATCH(DMI_BOARD_NAME, "Wilson Beach SDS") | |
1097 | } | |
1098 | }, | |
166765ea VK |
1099 | { |
1100 | .ident = "Intel Skylake RVP", | |
1101 | .matches = { | |
1102 | DMI_MATCH(DMI_PRODUCT_NAME, "Skylake Client platform") | |
1103 | } | |
1104 | }, | |
d06de6d9 VK |
1105 | { |
1106 | .ident = "Intel Kabylake RVP", | |
1107 | .matches = { | |
1108 | DMI_MATCH(DMI_PRODUCT_NAME, "Kabylake Client platform") | |
1109 | } | |
1110 | }, | |
fe0dfd63 YL |
1111 | { |
1112 | .ident = "Thinkpad Helix 2nd", | |
1113 | .matches = { | |
1114 | DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), | |
1115 | DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad Helix 2nd") | |
1116 | } | |
1117 | }, | |
d06de6d9 | 1118 | |
6c67cde2 BL |
1119 | { } |
1120 | }; | |
1121 | ||
aa2f9c12 | 1122 | static const struct dmi_system_id dmi_dell[] = { |
2cc3f234 | 1123 | { |
aa2f9c12 | 1124 | .ident = "Dell", |
2cc3f234 BL |
1125 | .matches = { |
1126 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
2cc3f234 BL |
1127 | } |
1128 | }, | |
1129 | { } | |
1130 | }; | |
1131 | ||
35b88858 | 1132 | static int rt286_i2c_probe(struct i2c_client *i2c) |
07cf7cba BL |
1133 | { |
1134 | struct rt286_platform_data *pdata = dev_get_platdata(&i2c->dev); | |
1135 | struct rt286_priv *rt286; | |
aa2f9c12 | 1136 | int i, ret, vendor_id; |
07cf7cba BL |
1137 | |
1138 | rt286 = devm_kzalloc(&i2c->dev, sizeof(*rt286), | |
1139 | GFP_KERNEL); | |
1140 | if (NULL == rt286) | |
1141 | return -ENOMEM; | |
1142 | ||
1143 | rt286->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt286_regmap); | |
1144 | if (IS_ERR(rt286->regmap)) { | |
1145 | ret = PTR_ERR(rt286->regmap); | |
1146 | dev_err(&i2c->dev, "Failed to allocate register map: %d\n", | |
1147 | ret); | |
1148 | return ret; | |
1149 | } | |
1150 | ||
143526ee | 1151 | ret = regmap_read(rt286->regmap, |
aa2f9c12 | 1152 | RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &vendor_id); |
143526ee BL |
1153 | if (ret != 0) { |
1154 | dev_err(&i2c->dev, "I2C error %d\n", ret); | |
1155 | return ret; | |
1156 | } | |
aa2f9c12 | 1157 | if (vendor_id != RT286_VENDOR_ID && vendor_id != RT288_VENDOR_ID) { |
4b21768a | 1158 | dev_err(&i2c->dev, |
aa2f9c12 DW |
1159 | "Device with ID register %#x is not rt286\n", |
1160 | vendor_id); | |
4b21768a BL |
1161 | return -ENODEV; |
1162 | } | |
1163 | ||
dc6d84c6 AL |
1164 | rt286->index_cache = devm_kmemdup(&i2c->dev, rt286_index_def, |
1165 | sizeof(rt286_index_def), GFP_KERNEL); | |
1166 | if (!rt286->index_cache) | |
1167 | return -ENOMEM; | |
1168 | ||
bc08f96b | 1169 | rt286->index_cache_size = INDEX_CACHE_SIZE; |
07cf7cba BL |
1170 | rt286->i2c = i2c; |
1171 | i2c_set_clientdata(i2c, rt286); | |
1172 | ||
d53d59ec BL |
1173 | /* restore codec default */ |
1174 | for (i = 0; i < INDEX_CACHE_SIZE; i++) | |
1175 | regmap_write(rt286->regmap, rt286->index_cache[i].reg, | |
1176 | rt286->index_cache[i].def); | |
1177 | for (i = 0; i < ARRAY_SIZE(rt286_reg); i++) | |
1178 | regmap_write(rt286->regmap, rt286_reg[i].reg, | |
1179 | rt286_reg[i].def); | |
1180 | ||
07cf7cba BL |
1181 | if (pdata) |
1182 | rt286->pdata = *pdata; | |
1183 | ||
aa2f9c12 DW |
1184 | if ((vendor_id == RT288_VENDOR_ID && dmi_check_system(dmi_dell)) || |
1185 | dmi_check_system(force_combo_jack_table)) | |
6c67cde2 BL |
1186 | rt286->pdata.cbj_en = true; |
1187 | ||
61a414c4 BL |
1188 | regmap_write(rt286->regmap, RT286_SET_AUDIO_POWER, AC_PWRST_D3); |
1189 | ||
1190 | for (i = 0; i < RT286_POWER_REG_LEN; i++) | |
1191 | regmap_write(rt286->regmap, | |
1192 | RT286_SET_POWER(rt286_support_power_controls[i]), | |
1193 | AC_PWRST_D1); | |
1194 | ||
1195 | if (!rt286->pdata.cbj_en) { | |
1196 | regmap_write(rt286->regmap, RT286_CBJ_CTRL2, 0x0000); | |
1197 | regmap_write(rt286->regmap, RT286_MIC1_DET_CTRL, 0x0816); | |
61a414c4 BL |
1198 | regmap_update_bits(rt286->regmap, |
1199 | RT286_CBJ_CTRL1, 0xf000, 0xb000); | |
1200 | } else { | |
1201 | regmap_update_bits(rt286->regmap, | |
1202 | RT286_CBJ_CTRL1, 0xf000, 0x5000); | |
1203 | } | |
1204 | ||
1205 | mdelay(10); | |
1206 | ||
1207 | if (!rt286->pdata.gpio2_en) | |
dfa7b01d | 1208 | regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0x40); |
61a414c4 BL |
1209 | else |
1210 | regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0); | |
1211 | ||
1212 | mdelay(10); | |
1213 | ||
6879db76 | 1214 | regmap_write(rt286->regmap, RT286_MISC_CTRL1, 0x0000); |
f8c101bc | 1215 | /* Power down LDO, VREF */ |
6879db76 BL |
1216 | regmap_update_bits(rt286->regmap, RT286_POWER_CTRL2, 0xc, 0x0); |
1217 | regmap_update_bits(rt286->regmap, RT286_POWER_CTRL1, 0x1001, 0x1001); | |
61a414c4 | 1218 | |
f8c101bc | 1219 | /* Set depop parameter */ |
bc6c4e45 BL |
1220 | regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL2, 0x403a, 0x401a); |
1221 | regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL3, 0xf777, 0x4737); | |
1222 | regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL4, 0x00ff, 0x003f); | |
1223 | ||
aa2f9c12 | 1224 | if (vendor_id == RT288_VENDOR_ID && dmi_check_system(dmi_dell)) { |
2cc3f234 BL |
1225 | regmap_update_bits(rt286->regmap, |
1226 | RT286_SET_GPIO_MASK, 0x40, 0x40); | |
1227 | regmap_update_bits(rt286->regmap, | |
1228 | RT286_SET_GPIO_DIRECTION, 0x40, 0x40); | |
1229 | regmap_update_bits(rt286->regmap, | |
1230 | RT286_SET_GPIO_DATA, 0x40, 0x40); | |
1231 | regmap_update_bits(rt286->regmap, | |
1232 | RT286_GPIO_CTRL, 0xc, 0x8); | |
1233 | } | |
1234 | ||
61a414c4 | 1235 | if (rt286->i2c->irq) { |
61a414c4 BL |
1236 | ret = request_threaded_irq(rt286->i2c->irq, NULL, rt286_irq, |
1237 | IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt286", rt286); | |
1238 | if (ret != 0) { | |
1239 | dev_err(&i2c->dev, | |
00933c49 | 1240 | "Failed to request IRQ: %d\n", ret); |
61a414c4 BL |
1241 | return ret; |
1242 | } | |
1243 | } | |
1244 | ||
45101122 KM |
1245 | ret = devm_snd_soc_register_component(&i2c->dev, |
1246 | &soc_component_dev_rt286, | |
07cf7cba BL |
1247 | rt286_dai, ARRAY_SIZE(rt286_dai)); |
1248 | ||
1249 | return ret; | |
1250 | } | |
1251 | ||
ed5c2f5f | 1252 | static void rt286_i2c_remove(struct i2c_client *i2c) |
07cf7cba BL |
1253 | { |
1254 | struct rt286_priv *rt286 = i2c_get_clientdata(i2c); | |
1255 | ||
1256 | if (i2c->irq) | |
1257 | free_irq(i2c->irq, rt286); | |
07cf7cba BL |
1258 | } |
1259 | ||
1260 | ||
23c4fd5c | 1261 | static struct i2c_driver rt286_i2c_driver = { |
07cf7cba BL |
1262 | .driver = { |
1263 | .name = "rt286", | |
07cf7cba BL |
1264 | .acpi_match_table = ACPI_PTR(rt286_acpi_match), |
1265 | }, | |
9abcd240 | 1266 | .probe = rt286_i2c_probe, |
07cf7cba BL |
1267 | .remove = rt286_i2c_remove, |
1268 | .id_table = rt286_i2c_id, | |
1269 | }; | |
1270 | ||
1271 | module_i2c_driver(rt286_i2c_driver); | |
1272 | ||
1273 | MODULE_DESCRIPTION("ASoC RT286 driver"); | |
1274 | MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>"); | |
1275 | MODULE_LICENSE("GPL"); |