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[linux-block.git] / sound / soc / codecs / pcm512x.c
CommitLineData
5a3af129
MB		 1/*
2 * Driver for the PCM512x CODECs
3 *
da924c3a 4 * Author: Mark Brown <broonie@kernel.org>
5a3af129
MB		 5 * Copyright 2014 Linaro Ltd
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 */
16
17
18#include <linux/init.h>
19#include <linux/module.h>
20#include <linux/clk.h>
d48502ea 21#include <linux/kernel.h>
5a3af129
MB		 22#include <linux/pm_runtime.h>
23#include <linux/regmap.h>
24#include <linux/regulator/consumer.h>
f086ba9d 25#include <linux/gcd.h>
5a3af129
MB		 26#include <sound/soc.h>
27#include <sound/soc-dapm.h>
81249307 28#include <sound/pcm_params.h>
5a3af129
MB		 29#include <sound/tlv.h>
30
31#include "pcm512x.h"
32
33#define PCM512x_NUM_SUPPLIES 3
06d0ffcc 34static const char * const pcm512x_supply_names[PCM512x_NUM_SUPPLIES] = {
5a3af129
MB		 35 "AVDD",
36 "DVDD",
37 "CPVDD",
38};
39
40struct pcm512x_priv {
41 struct regmap *regmap;
42 struct clk *sclk;
43 struct regulator_bulk_data supplies[PCM512x_NUM_SUPPLIES];
44 struct notifier_block supply_nb[PCM512x_NUM_SUPPLIES];
81249307 45 int fmt;
f086ba9d
PR		 46 int pll_in;
47 int pll_out;
48 int pll_r;
49 int pll_j;
50 int pll_d;
51 int pll_p;
52 unsigned long real_pll;
f29933c9
PR		 53 unsigned long overclock_pll;
54 unsigned long overclock_dac;
55 unsigned long overclock_dsp;
5a3af129
MB		 56};
57
58/*
59 * We can't use the same notifier block for more than one supply and
60 * there's no way I can see to get from a callback to the caller
61 * except container_of().
62 */
63#define PCM512x_REGULATOR_EVENT(n) \
64static int pcm512x_regulator_event_##n(struct notifier_block *nb, \
65 unsigned long event, void *data) \
66{ \
67 struct pcm512x_priv *pcm512x = container_of(nb, struct pcm512x_priv, \
68 supply_nb[n]); \
69 if (event & REGULATOR_EVENT_DISABLE) { \
70 regcache_mark_dirty(pcm512x->regmap); \
71 regcache_cache_only(pcm512x->regmap, true); \
72 } \
73 return 0; \
74}
75
76PCM512x_REGULATOR_EVENT(0)
77PCM512x_REGULATOR_EVENT(1)
78PCM512x_REGULATOR_EVENT(2)
79
80static const struct reg_default pcm512x_reg_defaults[] = {
806d6466
MB		 81 { PCM512x_RESET, 0x00 },
82 { PCM512x_POWER, 0x00 },
83 { PCM512x_MUTE, 0x00 },
84 { PCM512x_DSP, 0x00 },
85 { PCM512x_PLL_REF, 0x00 },
81249307 86 { PCM512x_DAC_REF, 0x00 },
806d6466
MB		 87 { PCM512x_DAC_ROUTING, 0x11 },
88 { PCM512x_DSP_PROGRAM, 0x01 },
89 { PCM512x_CLKDET, 0x00 },
90 { PCM512x_AUTO_MUTE, 0x00 },
91 { PCM512x_ERROR_DETECT, 0x00 },
92 { PCM512x_DIGITAL_VOLUME_1, 0x00 },
93 { PCM512x_DIGITAL_VOLUME_2, 0x30 },
94 { PCM512x_DIGITAL_VOLUME_3, 0x30 },
95 { PCM512x_DIGITAL_MUTE_1, 0x22 },
96 { PCM512x_DIGITAL_MUTE_2, 0x00 },
97 { PCM512x_DIGITAL_MUTE_3, 0x07 },
98 { PCM512x_OUTPUT_AMPLITUDE, 0x00 },
99 { PCM512x_ANALOG_GAIN_CTRL, 0x00 },
100 { PCM512x_UNDERVOLTAGE_PROT, 0x00 },
101 { PCM512x_ANALOG_MUTE_CTRL, 0x00 },
102 { PCM512x_ANALOG_GAIN_BOOST, 0x00 },
103 { PCM512x_VCOM_CTRL_1, 0x00 },
104 { PCM512x_VCOM_CTRL_2, 0x01 },
81249307
PR		 105 { PCM512x_BCLK_LRCLK_CFG, 0x00 },
106 { PCM512x_MASTER_MODE, 0x7c },
7c4e1119 107 { PCM512x_GPIO_DACIN, 0x00 },
f086ba9d 108 { PCM512x_GPIO_PLLIN, 0x00 },
81249307 109 { PCM512x_SYNCHRONIZE, 0x10 },
f086ba9d
PR		 110 { PCM512x_PLL_COEFF_0, 0x00 },
111 { PCM512x_PLL_COEFF_1, 0x00 },
112 { PCM512x_PLL_COEFF_2, 0x00 },
113 { PCM512x_PLL_COEFF_3, 0x00 },
114 { PCM512x_PLL_COEFF_4, 0x00 },
81249307
PR		 115 { PCM512x_DSP_CLKDIV, 0x00 },
116 { PCM512x_DAC_CLKDIV, 0x00 },
117 { PCM512x_NCP_CLKDIV, 0x00 },
118 { PCM512x_OSR_CLKDIV, 0x00 },
119 { PCM512x_MASTER_CLKDIV_1, 0x00 },
120 { PCM512x_MASTER_CLKDIV_2, 0x00 },
121 { PCM512x_FS_SPEED_MODE, 0x00 },
122 { PCM512x_IDAC_1, 0x01 },
123 { PCM512x_IDAC_2, 0x00 },
5a3af129
MB		 124};
125
126static bool pcm512x_readable(struct device *dev, unsigned int reg)
127{
128 switch (reg) {
129 case PCM512x_RESET:
130 case PCM512x_POWER:
131 case PCM512x_MUTE:
132 case PCM512x_PLL_EN:
133 case PCM512x_SPI_MISO_FUNCTION:
134 case PCM512x_DSP:
135 case PCM512x_GPIO_EN:
136 case PCM512x_BCLK_LRCLK_CFG:
137 case PCM512x_DSP_GPIO_INPUT:
138 case PCM512x_MASTER_MODE:
139 case PCM512x_PLL_REF:
81249307 140 case PCM512x_DAC_REF:
7c4e1119 141 case PCM512x_GPIO_DACIN:
f086ba9d 142 case PCM512x_GPIO_PLLIN:
81249307 143 case PCM512x_SYNCHRONIZE:
5a3af129
MB		 144 case PCM512x_PLL_COEFF_0:
145 case PCM512x_PLL_COEFF_1:
146 case PCM512x_PLL_COEFF_2:
147 case PCM512x_PLL_COEFF_3:
148 case PCM512x_PLL_COEFF_4:
149 case PCM512x_DSP_CLKDIV:
150 case PCM512x_DAC_CLKDIV:
151 case PCM512x_NCP_CLKDIV:
152 case PCM512x_OSR_CLKDIV:
153 case PCM512x_MASTER_CLKDIV_1:
154 case PCM512x_MASTER_CLKDIV_2:
155 case PCM512x_FS_SPEED_MODE:
156 case PCM512x_IDAC_1:
157 case PCM512x_IDAC_2:
158 case PCM512x_ERROR_DETECT:
159 case PCM512x_I2S_1:
160 case PCM512x_I2S_2:
161 case PCM512x_DAC_ROUTING:
162 case PCM512x_DSP_PROGRAM:
163 case PCM512x_CLKDET:
164 case PCM512x_AUTO_MUTE:
165 case PCM512x_DIGITAL_VOLUME_1:
166 case PCM512x_DIGITAL_VOLUME_2:
167 case PCM512x_DIGITAL_VOLUME_3:
168 case PCM512x_DIGITAL_MUTE_1:
169 case PCM512x_DIGITAL_MUTE_2:
170 case PCM512x_DIGITAL_MUTE_3:
171 case PCM512x_GPIO_OUTPUT_1:
172 case PCM512x_GPIO_OUTPUT_2:
173 case PCM512x_GPIO_OUTPUT_3:
174 case PCM512x_GPIO_OUTPUT_4:
175 case PCM512x_GPIO_OUTPUT_5:
176 case PCM512x_GPIO_OUTPUT_6:
177 case PCM512x_GPIO_CONTROL_1:
178 case PCM512x_GPIO_CONTROL_2:
179 case PCM512x_OVERFLOW:
180 case PCM512x_RATE_DET_1:
181 case PCM512x_RATE_DET_2:
182 case PCM512x_RATE_DET_3:
183 case PCM512x_RATE_DET_4:
f086ba9d 184 case PCM512x_CLOCK_STATUS:
5a3af129
MB		 185 case PCM512x_ANALOG_MUTE_DET:
186 case PCM512x_GPIN:
187 case PCM512x_DIGITAL_MUTE_DET:
806d6466
MB		 188 case PCM512x_OUTPUT_AMPLITUDE:
189 case PCM512x_ANALOG_GAIN_CTRL:
190 case PCM512x_UNDERVOLTAGE_PROT:
191 case PCM512x_ANALOG_MUTE_CTRL:
192 case PCM512x_ANALOG_GAIN_BOOST:
193 case PCM512x_VCOM_CTRL_1:
194 case PCM512x_VCOM_CTRL_2:
195 case PCM512x_CRAM_CTRL:
f086ba9d
PR		 196 case PCM512x_FLEX_A:
197 case PCM512x_FLEX_B:
5a3af129
MB		 198 return true;
199 default:
806d6466
MB		 200 /* There are 256 raw register addresses */
201 return reg < 0xff;
5a3af129
MB		 202 }
203}
204
205static bool pcm512x_volatile(struct device *dev, unsigned int reg)
206{
207 switch (reg) {
208 case PCM512x_PLL_EN:
209 case PCM512x_OVERFLOW:
210 case PCM512x_RATE_DET_1:
211 case PCM512x_RATE_DET_2:
212 case PCM512x_RATE_DET_3:
213 case PCM512x_RATE_DET_4:
f086ba9d 214 case PCM512x_CLOCK_STATUS:
5a3af129
MB		 215 case PCM512x_ANALOG_MUTE_DET:
216 case PCM512x_GPIN:
217 case PCM512x_DIGITAL_MUTE_DET:
806d6466 218 case PCM512x_CRAM_CTRL:
5a3af129
MB		 219 return true;
220 default:
806d6466
MB		 221 /* There are 256 raw register addresses */
222 return reg < 0xff;
5a3af129
MB		 223 }
224}
225
f29933c9
PR		 226static int pcm512x_overclock_pll_get(struct snd_kcontrol *kcontrol,
227 struct snd_ctl_elem_value *ucontrol)
228{
5bdef14a
KM		 229 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
230 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
f29933c9
PR		 231
232 ucontrol->value.integer.value[0] = pcm512x->overclock_pll;
233 return 0;
234}
235
236static int pcm512x_overclock_pll_put(struct snd_kcontrol *kcontrol,
237 struct snd_ctl_elem_value *ucontrol)
238{
5bdef14a
KM		 239 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
240 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
f29933c9 241
5bdef14a 242 switch (snd_soc_component_get_bias_level(component)) {
f29933c9
PR		 243 case SND_SOC_BIAS_OFF:
244 case SND_SOC_BIAS_STANDBY:
245 break;
246 default:
247 return -EBUSY;
248 }
249
250 pcm512x->overclock_pll = ucontrol->value.integer.value[0];
251 return 0;
252}
253
254static int pcm512x_overclock_dsp_get(struct snd_kcontrol *kcontrol,
255 struct snd_ctl_elem_value *ucontrol)
256{
5bdef14a
KM		 257 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
258 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
f29933c9
PR		 259
260 ucontrol->value.integer.value[0] = pcm512x->overclock_dsp;
261 return 0;
262}
263
264static int pcm512x_overclock_dsp_put(struct snd_kcontrol *kcontrol,
265 struct snd_ctl_elem_value *ucontrol)
266{
5bdef14a
KM		 267 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
268 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
f29933c9 269
5bdef14a 270 switch (snd_soc_component_get_bias_level(component)) {
f29933c9
PR		 271 case SND_SOC_BIAS_OFF:
272 case SND_SOC_BIAS_STANDBY:
273 break;
274 default:
275 return -EBUSY;
276 }
277
278 pcm512x->overclock_dsp = ucontrol->value.integer.value[0];
279 return 0;
280}
281
282static int pcm512x_overclock_dac_get(struct snd_kcontrol *kcontrol,
283 struct snd_ctl_elem_value *ucontrol)
284{
5bdef14a
KM		 285 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
286 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
f29933c9
PR		 287
288 ucontrol->value.integer.value[0] = pcm512x->overclock_dac;
289 return 0;
290}
291
292static int pcm512x_overclock_dac_put(struct snd_kcontrol *kcontrol,
293 struct snd_ctl_elem_value *ucontrol)
294{
5bdef14a
KM		 295 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
296 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
f29933c9 297
5bdef14a 298 switch (snd_soc_component_get_bias_level(component)) {
f29933c9
PR		 299 case SND_SOC_BIAS_OFF:
300 case SND_SOC_BIAS_STANDBY:
301 break;
302 default:
303 return -EBUSY;
304 }
305
306 pcm512x->overclock_dac = ucontrol->value.integer.value[0];
307 return 0;
308}
309
5a3af129 310static const DECLARE_TLV_DB_SCALE(digital_tlv, -10350, 50, 1);
5be2fc20
MB		 311static const DECLARE_TLV_DB_SCALE(analog_tlv, -600, 600, 0);
312static const DECLARE_TLV_DB_SCALE(boost_tlv, 0, 80, 0);
5a3af129 313
06d0ffcc 314static const char * const pcm512x_dsp_program_texts[] = {
5a3af129
MB		 315 "FIR interpolation with de-emphasis",
316 "Low latency IIR with de-emphasis",
5a3af129 317 "High attenuation with de-emphasis",
3a8e5019 318 "Fixed process flow",
5a3af129
MB		 319 "Ringing-less low latency FIR",
320};
321
322static const unsigned int pcm512x_dsp_program_values[] = {
323 1,
324 2,
325 3,
326 5,
327 7,
328};
329
e97db9ab
MB		 330static SOC_VALUE_ENUM_SINGLE_DECL(pcm512x_dsp_program,
331 PCM512x_DSP_PROGRAM, 0, 0x1f,
332 pcm512x_dsp_program_texts,
333 pcm512x_dsp_program_values);
5a3af129 334
06d0ffcc 335static const char * const pcm512x_clk_missing_text[] = {
5a3af129
MB		 336 "1s", "2s", "3s", "4s", "5s", "6s", "7s", "8s"
337};
338
339static const struct soc_enum pcm512x_clk_missing =
340 SOC_ENUM_SINGLE(PCM512x_CLKDET, 0, 8, pcm512x_clk_missing_text);
341
06d0ffcc 342static const char * const pcm512x_autom_text[] = {
5a3af129
MB		 343 "21ms", "106ms", "213ms", "533ms", "1.07s", "2.13s", "5.33s", "10.66s"
344};
345
346static const struct soc_enum pcm512x_autom_l =
347 SOC_ENUM_SINGLE(PCM512x_AUTO_MUTE, PCM512x_ATML_SHIFT, 8,
348 pcm512x_autom_text);
349
350static const struct soc_enum pcm512x_autom_r =
351 SOC_ENUM_SINGLE(PCM512x_AUTO_MUTE, PCM512x_ATMR_SHIFT, 8,
352 pcm512x_autom_text);
353
06d0ffcc 354static const char * const pcm512x_ramp_rate_text[] = {
5a3af129
MB		 355 "1 sample/update", "2 samples/update", "4 samples/update",
356 "Immediate"
357};
358
359static const struct soc_enum pcm512x_vndf =
360 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNDF_SHIFT, 4,
361 pcm512x_ramp_rate_text);
362
363static const struct soc_enum pcm512x_vnuf =
364 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNUF_SHIFT, 4,
365 pcm512x_ramp_rate_text);
366
367static const struct soc_enum pcm512x_vedf =
368 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_2, PCM512x_VEDF_SHIFT, 4,
369 pcm512x_ramp_rate_text);
370
06d0ffcc 371static const char * const pcm512x_ramp_step_text[] = {
5a3af129
MB		 372 "4dB/step", "2dB/step", "1dB/step", "0.5dB/step"
373};
374
375static const struct soc_enum pcm512x_vnds =
376 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNDS_SHIFT, 4,
377 pcm512x_ramp_step_text);
378
379static const struct soc_enum pcm512x_vnus =
380 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNUS_SHIFT, 4,
381 pcm512x_ramp_step_text);
382
383static const struct soc_enum pcm512x_veds =
384 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_2, PCM512x_VEDS_SHIFT, 4,
385 pcm512x_ramp_step_text);
386
387static const struct snd_kcontrol_new pcm512x_controls[] = {
1c6d3680 388SOC_DOUBLE_R_TLV("Digital Playback Volume", PCM512x_DIGITAL_VOLUME_2,
5a3af129 389 PCM512x_DIGITAL_VOLUME_3, 0, 255, 1, digital_tlv),
4d9b13c7 390SOC_DOUBLE_TLV("Analogue Playback Volume", PCM512x_ANALOG_GAIN_CTRL,
5be2fc20 391 PCM512x_LAGN_SHIFT, PCM512x_RAGN_SHIFT, 1, 1, analog_tlv),
4d9b13c7 392SOC_DOUBLE_TLV("Analogue Playback Boost Volume", PCM512x_ANALOG_GAIN_BOOST,
5be2fc20 393 PCM512x_AGBL_SHIFT, PCM512x_AGBR_SHIFT, 1, 0, boost_tlv),
1c6d3680 394SOC_DOUBLE("Digital Playback Switch", PCM512x_MUTE, PCM512x_RQML_SHIFT,
5a3af129
MB		 395 PCM512x_RQMR_SHIFT, 1, 1),
396
397SOC_SINGLE("Deemphasis Switch", PCM512x_DSP, PCM512x_DEMP_SHIFT, 1, 1),
54581be7 398SOC_ENUM("DSP Program", pcm512x_dsp_program),
5a3af129
MB		 399
400SOC_ENUM("Clock Missing Period", pcm512x_clk_missing),
401SOC_ENUM("Auto Mute Time Left", pcm512x_autom_l),
402SOC_ENUM("Auto Mute Time Right", pcm512x_autom_r),
403SOC_SINGLE("Auto Mute Mono Switch", PCM512x_DIGITAL_MUTE_3,
404 PCM512x_ACTL_SHIFT, 1, 0),
405SOC_DOUBLE("Auto Mute Switch", PCM512x_DIGITAL_MUTE_3, PCM512x_AMLE_SHIFT,
376dc490 406 PCM512x_AMRE_SHIFT, 1, 0),
5a3af129
MB		 407
408SOC_ENUM("Volume Ramp Down Rate", pcm512x_vndf),
409SOC_ENUM("Volume Ramp Down Step", pcm512x_vnds),
410SOC_ENUM("Volume Ramp Up Rate", pcm512x_vnuf),
411SOC_ENUM("Volume Ramp Up Step", pcm512x_vnus),
412SOC_ENUM("Volume Ramp Down Emergency Rate", pcm512x_vedf),
413SOC_ENUM("Volume Ramp Down Emergency Step", pcm512x_veds),
f29933c9
PR		 414
415SOC_SINGLE_EXT("Max Overclock PLL", SND_SOC_NOPM, 0, 20, 0,
416 pcm512x_overclock_pll_get, pcm512x_overclock_pll_put),
417SOC_SINGLE_EXT("Max Overclock DSP", SND_SOC_NOPM, 0, 40, 0,
418 pcm512x_overclock_dsp_get, pcm512x_overclock_dsp_put),
419SOC_SINGLE_EXT("Max Overclock DAC", SND_SOC_NOPM, 0, 40, 0,
420 pcm512x_overclock_dac_get, pcm512x_overclock_dac_put),
5a3af129
MB		 421};
422
423static const struct snd_soc_dapm_widget pcm512x_dapm_widgets[] = {
424SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0),
425SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0),
426
427SND_SOC_DAPM_OUTPUT("OUTL"),
428SND_SOC_DAPM_OUTPUT("OUTR"),
429};
430
431static const struct snd_soc_dapm_route pcm512x_dapm_routes[] = {
432 { "DACL", NULL, "Playback" },
433 { "DACR", NULL, "Playback" },
434
435 { "OUTL", NULL, "DACL" },
436 { "OUTR", NULL, "DACR" },
437};
438
f29933c9
PR		 439static unsigned long pcm512x_pll_max(struct pcm512x_priv *pcm512x)
440{
441 return 25000000 + 25000000 * pcm512x->overclock_pll / 100;
442}
443
444static unsigned long pcm512x_dsp_max(struct pcm512x_priv *pcm512x)
445{
446 return 50000000 + 50000000 * pcm512x->overclock_dsp / 100;
447}
448
449static unsigned long pcm512x_dac_max(struct pcm512x_priv *pcm512x,
450 unsigned long rate)
451{
452 return rate + rate * pcm512x->overclock_dac / 100;
453}
454
455static unsigned long pcm512x_sck_max(struct pcm512x_priv *pcm512x)
456{
457 if (!pcm512x->pll_out)
458 return 25000000;
459 return pcm512x_pll_max(pcm512x);
460}
461
462static unsigned long pcm512x_ncp_target(struct pcm512x_priv *pcm512x,
463 unsigned long dac_rate)
464{
465 /*
466 * If the DAC is not actually overclocked, use the good old
467 * NCP target rate...
468 */
469 if (dac_rate <= 6144000)
470 return 1536000;
471 /*
472 * ...but if the DAC is in fact overclocked, bump the NCP target
473 * rate to get the recommended dividers even when overclocking.
474 */
475 return pcm512x_dac_max(pcm512x, 1536000);
476}
477
81249307
PR		 478static const u32 pcm512x_dai_rates[] = {
479 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
480 88200, 96000, 176400, 192000, 384000,
481};
482
483static const struct snd_pcm_hw_constraint_list constraints_slave = {
484 .count = ARRAY_SIZE(pcm512x_dai_rates),
485 .list = pcm512x_dai_rates,
486};
487
f086ba9d
PR		 488static int pcm512x_hw_rule_rate(struct snd_pcm_hw_params *params,
489 struct snd_pcm_hw_rule *rule)
490{
f29933c9 491 struct pcm512x_priv *pcm512x = rule->private;
9c7da1a5 492 struct snd_interval ranges[2];
f086ba9d
PR		 493 int frame_size;
494
495 frame_size = snd_soc_params_to_frame_size(params);
496 if (frame_size < 0)
497 return frame_size;
498
9c7da1a5
PR		 499 switch (frame_size) {
500 case 32:
501 /* No hole when the frame size is 32. */
f086ba9d 502 return 0;
9c7da1a5
PR		 503 case 48:
504 case 64:
505 /* There is only one hole in the range of supported
506 * rates, but it moves with the frame size.
507 */
508 memset(ranges, 0, sizeof(ranges));
509 ranges[0].min = 8000;
f29933c9 510 ranges[0].max = pcm512x_sck_max(pcm512x) / frame_size / 2;
9c7da1a5
PR		 511 ranges[1].min = DIV_ROUND_UP(16000000, frame_size);
512 ranges[1].max = 384000;
513 break;
514 default:
515 return -EINVAL;
516 }
f086ba9d
PR		 517
518 return snd_interval_ranges(hw_param_interval(params, rule->var),
9c7da1a5 519 ARRAY_SIZE(ranges), ranges, 0);
f086ba9d
PR		 520}
521
81249307
PR		 522static int pcm512x_dai_startup_master(struct snd_pcm_substream *substream,
523 struct snd_soc_dai *dai)
524{
5bdef14a
KM		 525 struct snd_soc_component *component = dai->component;
526 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
81249307
PR		 527 struct device *dev = dai->dev;
528 struct snd_pcm_hw_constraint_ratnums *constraints_no_pll;
529 struct snd_ratnum *rats_no_pll;
530
531 if (IS_ERR(pcm512x->sclk)) {
532 dev_err(dev, "Need SCLK for master mode: %ld\n",
533 PTR_ERR(pcm512x->sclk));
534 return PTR_ERR(pcm512x->sclk);
535 }
536
f086ba9d
PR		 537 if (pcm512x->pll_out)
538 return snd_pcm_hw_rule_add(substream->runtime, 0,
539 SNDRV_PCM_HW_PARAM_RATE,
540 pcm512x_hw_rule_rate,
f29933c9 541 pcm512x,
f086ba9d
PR		 542 SNDRV_PCM_HW_PARAM_FRAME_BITS,
543 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
544
81249307
PR		 545 constraints_no_pll = devm_kzalloc(dev, sizeof(*constraints_no_pll),
546 GFP_KERNEL);
547 if (!constraints_no_pll)
548 return -ENOMEM;
549 constraints_no_pll->nrats = 1;
550 rats_no_pll = devm_kzalloc(dev, sizeof(*rats_no_pll), GFP_KERNEL);
551 if (!rats_no_pll)
552 return -ENOMEM;
553 constraints_no_pll->rats = rats_no_pll;
554 rats_no_pll->num = clk_get_rate(pcm512x->sclk) / 64;
555 rats_no_pll->den_min = 1;
556 rats_no_pll->den_max = 128;
557 rats_no_pll->den_step = 1;
558
559 return snd_pcm_hw_constraint_ratnums(substream->runtime, 0,
560 SNDRV_PCM_HW_PARAM_RATE,
561 constraints_no_pll);
562}
563
564static int pcm512x_dai_startup_slave(struct snd_pcm_substream *substream,
565 struct snd_soc_dai *dai)
566{
5bdef14a
KM		 567 struct snd_soc_component *component = dai->component;
568 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
81249307
PR		 569 struct device *dev = dai->dev;
570 struct regmap *regmap = pcm512x->regmap;
571
572 if (IS_ERR(pcm512x->sclk)) {
573 dev_info(dev, "No SCLK, using BCLK: %ld\n",
574 PTR_ERR(pcm512x->sclk));
575
576 /* Disable reporting of missing SCLK as an error */
577 regmap_update_bits(regmap, PCM512x_ERROR_DETECT,
578 PCM512x_IDCH, PCM512x_IDCH);
579
580 /* Switch PLL input to BCLK */
581 regmap_update_bits(regmap, PCM512x_PLL_REF,
582 PCM512x_SREF, PCM512x_SREF_BCK);
583 }
584
585 return snd_pcm_hw_constraint_list(substream->runtime, 0,
586 SNDRV_PCM_HW_PARAM_RATE,
587 &constraints_slave);
588}
589
590static int pcm512x_dai_startup(struct snd_pcm_substream *substream,
591 struct snd_soc_dai *dai)
592{
5bdef14a
KM		 593 struct snd_soc_component *component = dai->component;
594 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
81249307
PR		 595
596 switch (pcm512x->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
597 case SND_SOC_DAIFMT_CBM_CFM:
d11c2978 598 case SND_SOC_DAIFMT_CBM_CFS:
81249307
PR		 599 return pcm512x_dai_startup_master(substream, dai);
600
601 case SND_SOC_DAIFMT_CBS_CFS:
602 return pcm512x_dai_startup_slave(substream, dai);
603
604 default:
605 return -EINVAL;
606 }
607}
608
5bdef14a 609static int pcm512x_set_bias_level(struct snd_soc_component *component,
5a3af129
MB		 610 enum snd_soc_bias_level level)
611{
5bdef14a 612 struct pcm512x_priv *pcm512x = dev_get_drvdata(component->dev);
5a3af129
MB		 613 int ret;
614
615 switch (level) {
616 case SND_SOC_BIAS_ON:
617 case SND_SOC_BIAS_PREPARE:
618 break;
619
620 case SND_SOC_BIAS_STANDBY:
621 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
622 PCM512x_RQST, 0);
623 if (ret != 0) {
5bdef14a 624 dev_err(component->dev, "Failed to remove standby: %d\n",
5a3af129
MB		 625 ret);
626 return ret;
627 }
628 break;
629
630 case SND_SOC_BIAS_OFF:
631 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
632 PCM512x_RQST, PCM512x_RQST);
633 if (ret != 0) {
5bdef14a 634 dev_err(component->dev, "Failed to request standby: %d\n",
5a3af129
MB		 635 ret);
636 return ret;
637 }
638 break;
639 }
640
5a3af129
MB		 641 return 0;
642}
643
f086ba9d
PR		 644static unsigned long pcm512x_find_sck(struct snd_soc_dai *dai,
645 unsigned long bclk_rate)
646{
647 struct device *dev = dai->dev;
5bdef14a
KM		 648 struct snd_soc_component *component = dai->component;
649 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
f086ba9d
PR		 650 unsigned long sck_rate;
651 int pow2;
652
653 /* 64 MHz <= pll_rate <= 100 MHz, VREF mode */
654 /* 16 MHz <= sck_rate <= 25 MHz, VREF mode */
655
656 /* select sck_rate as a multiple of bclk_rate but still with
657 * as many factors of 2 as possible, as that makes it easier
658 * to find a fast DAC rate
659 */
f29933c9 660 pow2 = 1 << fls((pcm512x_pll_max(pcm512x) - 16000000) / bclk_rate);
f086ba9d 661 for (; pow2; pow2 >>= 1) {
f29933c9
PR		 662 sck_rate = rounddown(pcm512x_pll_max(pcm512x),
663 bclk_rate * pow2);
f086ba9d
PR		 664 if (sck_rate >= 16000000)
665 break;
666 }
667 if (!pow2) {
668 dev_err(dev, "Impossible to generate a suitable SCK\n");
669 return 0;
670 }
671
672 dev_dbg(dev, "sck_rate %lu\n", sck_rate);
673 return sck_rate;
674}
675
676/* pll_rate = pllin_rate * R * J.D / P
677 * 1 <= R <= 16
678 * 1 <= J <= 63
679 * 0 <= D <= 9999
680 * 1 <= P <= 15
681 * 64 MHz <= pll_rate <= 100 MHz
682 * if D == 0
683 * 1 MHz <= pllin_rate / P <= 20 MHz
684 * else if D > 0
685 * 6.667 MHz <= pllin_rate / P <= 20 MHz
686 * 4 <= J <= 11
687 * R = 1
688 */
689static int pcm512x_find_pll_coeff(struct snd_soc_dai *dai,
690 unsigned long pllin_rate,
691 unsigned long pll_rate)
692{
693 struct device *dev = dai->dev;
5bdef14a
KM		 694 struct snd_soc_component *component = dai->component;
695 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
f086ba9d
PR		 696 unsigned long common;
697 int R, J, D, P;
698 unsigned long K; /* 10000 * J.D */
699 unsigned long num;
700 unsigned long den;
701
702 common = gcd(pll_rate, pllin_rate);
703 dev_dbg(dev, "pll %lu pllin %lu common %lu\n",
704 pll_rate, pllin_rate, common);
705 num = pll_rate / common;
706 den = pllin_rate / common;
707
708 /* pllin_rate / P (or here, den) cannot be greater than 20 MHz */
709 if (pllin_rate / den > 20000000 && num < 8) {
f073faa7
HM		 710 num *= DIV_ROUND_UP(pllin_rate / den, 20000000);
711 den *= DIV_ROUND_UP(pllin_rate / den, 20000000);
f086ba9d
PR		 712 }
713 dev_dbg(dev, "num / den = %lu / %lu\n", num, den);
714
715 P = den;
716 if (den <= 15 && num <= 16 * 63
717 && 1000000 <= pllin_rate / P && pllin_rate / P <= 20000000) {
718 /* Try the case with D = 0 */
719 D = 0;
720 /* factor 'num' into J and R, such that R <= 16 and J <= 63 */
721 for (R = 16; R; R--) {
722 if (num % R)
723 continue;
724 J = num / R;
725 if (J == 0 || J > 63)
726 continue;
727
728 dev_dbg(dev, "R * J / P = %d * %d / %d\n", R, J, P);
729 pcm512x->real_pll = pll_rate;
730 goto done;
731 }
732 /* no luck */
733 }
734
735 R = 1;
736
737 if (num > 0xffffffffUL / 10000)
738 goto fallback;
739
740 /* Try to find an exact pll_rate using the D > 0 case */
741 common = gcd(10000 * num, den);
742 num = 10000 * num / common;
743 den /= common;
744 dev_dbg(dev, "num %lu den %lu common %lu\n", num, den, common);
745
746 for (P = den; P <= 15; P++) {
747 if (pllin_rate / P < 6667000 || 200000000 < pllin_rate / P)
748 continue;
749 if (num * P % den)
750 continue;
751 K = num * P / den;
752 /* J == 12 is ok if D == 0 */
753 if (K < 40000 || K > 120000)
754 continue;
755
756 J = K / 10000;
757 D = K % 10000;
758 dev_dbg(dev, "J.D / P = %d.%04d / %d\n", J, D, P);
759 pcm512x->real_pll = pll_rate;
760 goto done;
761 }
762
763 /* Fall back to an approximate pll_rate */
764
765fallback:
766 /* find smallest possible P */
767 P = DIV_ROUND_UP(pllin_rate, 20000000);
768 if (!P)
769 P = 1;
770 else if (P > 15) {
771 dev_err(dev, "Need a slower clock as pll-input\n");
772 return -EINVAL;
773 }
774 if (pllin_rate / P < 6667000) {
775 dev_err(dev, "Need a faster clock as pll-input\n");
776 return -EINVAL;
777 }
778 K = DIV_ROUND_CLOSEST_ULL(10000ULL * pll_rate * P, pllin_rate);
779 if (K < 40000)
780 K = 40000;
781 /* J == 12 is ok if D == 0 */
782 if (K > 120000)
783 K = 120000;
784 J = K / 10000;
785 D = K % 10000;
786 dev_dbg(dev, "J.D / P ~ %d.%04d / %d\n", J, D, P);
787 pcm512x->real_pll = DIV_ROUND_DOWN_ULL((u64)K * pllin_rate, 10000 * P);
788
789done:
790 pcm512x->pll_r = R;
791 pcm512x->pll_j = J;
792 pcm512x->pll_d = D;
793 pcm512x->pll_p = P;
794 return 0;
795}
796
7c4e1119
PR		 797static unsigned long pcm512x_pllin_dac_rate(struct snd_soc_dai *dai,
798 unsigned long osr_rate,
799 unsigned long pllin_rate)
800{
5bdef14a
KM		 801 struct snd_soc_component *component = dai->component;
802 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
7c4e1119
PR		 803 unsigned long dac_rate;
804
805 if (!pcm512x->pll_out)
806 return 0; /* no PLL to bypass, force SCK as DAC input */
807
808 if (pllin_rate % osr_rate)
809 return 0; /* futile, quit early */
810
811 /* run DAC no faster than 6144000 Hz */
f29933c9 812 for (dac_rate = rounddown(pcm512x_dac_max(pcm512x, 6144000), osr_rate);
7c4e1119
PR		 813 dac_rate;
814 dac_rate -= osr_rate) {
815
816 if (pllin_rate / dac_rate > 128)
817 return 0; /* DAC divider would be too big */
818
819 if (!(pllin_rate % dac_rate))
820 return dac_rate;
821
822 dac_rate -= osr_rate;
823 }
824
825 return 0;
826}
827
81249307
PR		 828static int pcm512x_set_dividers(struct snd_soc_dai *dai,
829 struct snd_pcm_hw_params *params)
830{
831 struct device *dev = dai->dev;
5bdef14a
KM		 832 struct snd_soc_component *component = dai->component;
833 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
f086ba9d
PR		 834 unsigned long pllin_rate = 0;
835 unsigned long pll_rate;
81249307
PR		 836 unsigned long sck_rate;
837 unsigned long mck_rate;
838 unsigned long bclk_rate;
839 unsigned long sample_rate;
840 unsigned long osr_rate;
7c4e1119 841 unsigned long dacsrc_rate;
81249307
PR		 842 int bclk_div;
843 int lrclk_div;
844 int dsp_div;
845 int dac_div;
846 unsigned long dac_rate;
847 int ncp_div;
848 int osr_div;
81249307
PR		 849 int ret;
850 int idac;
851 int fssp;
7c4e1119 852 int gpio;
81249307
PR		 853
854 lrclk_div = snd_soc_params_to_frame_size(params);
855 if (lrclk_div == 0) {
856 dev_err(dev, "No LRCLK?\n");
857 return -EINVAL;
858 }
859
f086ba9d
PR		 860 if (!pcm512x->pll_out) {
861 sck_rate = clk_get_rate(pcm512x->sclk);
862 bclk_div = params->rate_den * 64 / lrclk_div;
863 bclk_rate = DIV_ROUND_CLOSEST(sck_rate, bclk_div);
864
865 mck_rate = sck_rate;
866 } else {
867 ret = snd_soc_params_to_bclk(params);
868 if (ret < 0) {
869 dev_err(dev, "Failed to find suitable BCLK: %d\n", ret);
870 return ret;
871 }
872 if (ret == 0) {
873 dev_err(dev, "No BCLK?\n");
874 return -EINVAL;
875 }
876 bclk_rate = ret;
877
878 pllin_rate = clk_get_rate(pcm512x->sclk);
879
880 sck_rate = pcm512x_find_sck(dai, bclk_rate);
881 if (!sck_rate)
882 return -EINVAL;
883 pll_rate = 4 * sck_rate;
884
885 ret = pcm512x_find_pll_coeff(dai, pllin_rate, pll_rate);
886 if (ret != 0)
887 return ret;
888
889 ret = regmap_write(pcm512x->regmap,
890 PCM512x_PLL_COEFF_0, pcm512x->pll_p - 1);
891 if (ret != 0) {
892 dev_err(dev, "Failed to write PLL P: %d\n", ret);
893 return ret;
894 }
895
896 ret = regmap_write(pcm512x->regmap,
897 PCM512x_PLL_COEFF_1, pcm512x->pll_j);
898 if (ret != 0) {
899 dev_err(dev, "Failed to write PLL J: %d\n", ret);
900 return ret;
901 }
902
903 ret = regmap_write(pcm512x->regmap,
904 PCM512x_PLL_COEFF_2, pcm512x->pll_d >> 8);
905 if (ret != 0) {
906 dev_err(dev, "Failed to write PLL D msb: %d\n", ret);
907 return ret;
908 }
909
910 ret = regmap_write(pcm512x->regmap,
911 PCM512x_PLL_COEFF_3, pcm512x->pll_d & 0xff);
912 if (ret != 0) {
913 dev_err(dev, "Failed to write PLL D lsb: %d\n", ret);
914 return ret;
915 }
916
917 ret = regmap_write(pcm512x->regmap,
918 PCM512x_PLL_COEFF_4, pcm512x->pll_r - 1);
919 if (ret != 0) {
920 dev_err(dev, "Failed to write PLL R: %d\n", ret);
921 return ret;
922 }
923
924 mck_rate = pcm512x->real_pll;
81249307 925
f086ba9d
PR		 926 bclk_div = DIV_ROUND_CLOSEST(sck_rate, bclk_rate);
927 }
81249307
PR		 928
929 if (bclk_div > 128) {
930 dev_err(dev, "Failed to find BCLK divider\n");
931 return -EINVAL;
932 }
933
934 /* the actual rate */
935 sample_rate = sck_rate / bclk_div / lrclk_div;
936 osr_rate = 16 * sample_rate;
937
938 /* run DSP no faster than 50 MHz */
f29933c9 939 dsp_div = mck_rate > pcm512x_dsp_max(pcm512x) ? 2 : 1;
81249307 940
7c4e1119
PR		 941 dac_rate = pcm512x_pllin_dac_rate(dai, osr_rate, pllin_rate);
942 if (dac_rate) {
943 /* the desired clock rate is "compatible" with the pll input
944 * clock, so use that clock as dac input instead of the pll
945 * output clock since the pll will introduce jitter and thus
946 * noise.
947 */
948 dev_dbg(dev, "using pll input as dac input\n");
949 ret = regmap_update_bits(pcm512x->regmap, PCM512x_DAC_REF,
950 PCM512x_SDAC, PCM512x_SDAC_GPIO);
951 if (ret != 0) {
5bdef14a 952 dev_err(component->dev,
7c4e1119
PR		 953 "Failed to set gpio as dacref: %d\n", ret);
954 return ret;
955 }
81249307 956
7c4e1119
PR		 957 gpio = PCM512x_GREF_GPIO1 + pcm512x->pll_in - 1;
958 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_DACIN,
959 PCM512x_GREF, gpio);
960 if (ret != 0) {
5bdef14a 961 dev_err(component->dev,
7c4e1119
PR		 962 "Failed to set gpio %d as dacin: %d\n",
963 pcm512x->pll_in, ret);
964 return ret;
965 }
966
967 dacsrc_rate = pllin_rate;
968 } else {
969 /* run DAC no faster than 6144000 Hz */
f29933c9
PR		 970 unsigned long dac_mul = pcm512x_dac_max(pcm512x, 6144000)
971 / osr_rate;
7c4e1119
PR		 972 unsigned long sck_mul = sck_rate / osr_rate;
973
974 for (; dac_mul; dac_mul--) {
975 if (!(sck_mul % dac_mul))
976 break;
977 }
978 if (!dac_mul) {
979 dev_err(dev, "Failed to find DAC rate\n");
980 return -EINVAL;
981 }
81249307 982
7c4e1119
PR		 983 dac_rate = dac_mul * osr_rate;
984 dev_dbg(dev, "dac_rate %lu sample_rate %lu\n",
985 dac_rate, sample_rate);
986
987 ret = regmap_update_bits(pcm512x->regmap, PCM512x_DAC_REF,
988 PCM512x_SDAC, PCM512x_SDAC_SCK);
989 if (ret != 0) {
5bdef14a 990 dev_err(component->dev,
7c4e1119
PR		 991 "Failed to set sck as dacref: %d\n", ret);
992 return ret;
993 }
994
995 dacsrc_rate = sck_rate;
996 }
997
5890bd52
PR		 998 osr_div = DIV_ROUND_CLOSEST(dac_rate, osr_rate);
999 if (osr_div > 128) {
1000 dev_err(dev, "Failed to find OSR divider\n");
1001 return -EINVAL;
1002 }
1003
7c4e1119 1004 dac_div = DIV_ROUND_CLOSEST(dacsrc_rate, dac_rate);
81249307
PR		 1005 if (dac_div > 128) {
1006 dev_err(dev, "Failed to find DAC divider\n");
1007 return -EINVAL;
1008 }
5890bd52 1009 dac_rate = dacsrc_rate / dac_div;
81249307 1010
f29933c9
PR		 1011 ncp_div = DIV_ROUND_CLOSEST(dac_rate,
1012 pcm512x_ncp_target(pcm512x, dac_rate));
5890bd52 1013 if (ncp_div > 128 || dac_rate / ncp_div > 2048000) {
81249307 1014 /* run NCP no faster than 2048000 Hz, but why? */
5890bd52 1015 ncp_div = DIV_ROUND_UP(dac_rate, 2048000);
81249307
PR		 1016 if (ncp_div > 128) {
1017 dev_err(dev, "Failed to find NCP divider\n");
1018 return -EINVAL;
1019 }
1020 }
1021
81249307
PR		 1022 idac = mck_rate / (dsp_div * sample_rate);
1023
1024 ret = regmap_write(pcm512x->regmap, PCM512x_DSP_CLKDIV, dsp_div - 1);
1025 if (ret != 0) {
1026 dev_err(dev, "Failed to write DSP divider: %d\n", ret);
1027 return ret;
1028 }
1029
1030 ret = regmap_write(pcm512x->regmap, PCM512x_DAC_CLKDIV, dac_div - 1);
1031 if (ret != 0) {
1032 dev_err(dev, "Failed to write DAC divider: %d\n", ret);
1033 return ret;
1034 }
1035
1036 ret = regmap_write(pcm512x->regmap, PCM512x_NCP_CLKDIV, ncp_div - 1);
1037 if (ret != 0) {
1038 dev_err(dev, "Failed to write NCP divider: %d\n", ret);
1039 return ret;
1040 }
1041
1042 ret = regmap_write(pcm512x->regmap, PCM512x_OSR_CLKDIV, osr_div - 1);
1043 if (ret != 0) {
1044 dev_err(dev, "Failed to write OSR divider: %d\n", ret);
1045 return ret;
1046 }
1047
1048 ret = regmap_write(pcm512x->regmap,
1049 PCM512x_MASTER_CLKDIV_1, bclk_div - 1);
1050 if (ret != 0) {
1051 dev_err(dev, "Failed to write BCLK divider: %d\n", ret);
1052 return ret;
1053 }
1054
1055 ret = regmap_write(pcm512x->regmap,
1056 PCM512x_MASTER_CLKDIV_2, lrclk_div - 1);
1057 if (ret != 0) {
1058 dev_err(dev, "Failed to write LRCLK divider: %d\n", ret);
1059 return ret;
1060 }
1061
1062 ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_1, idac >> 8);
1063 if (ret != 0) {
1064 dev_err(dev, "Failed to write IDAC msb divider: %d\n", ret);
1065 return ret;
1066 }
1067
1068 ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_2, idac & 0xff);
1069 if (ret != 0) {
1070 dev_err(dev, "Failed to write IDAC lsb divider: %d\n", ret);
1071 return ret;
1072 }
1073
f29933c9 1074 if (sample_rate <= pcm512x_dac_max(pcm512x, 48000))
81249307 1075 fssp = PCM512x_FSSP_48KHZ;
f29933c9 1076 else if (sample_rate <= pcm512x_dac_max(pcm512x, 96000))
81249307 1077 fssp = PCM512x_FSSP_96KHZ;
f29933c9 1078 else if (sample_rate <= pcm512x_dac_max(pcm512x, 192000))
81249307
PR		 1079 fssp = PCM512x_FSSP_192KHZ;
1080 else
1081 fssp = PCM512x_FSSP_384KHZ;
1082 ret = regmap_update_bits(pcm512x->regmap, PCM512x_FS_SPEED_MODE,
1083 PCM512x_FSSP, fssp);
1084 if (ret != 0) {
5bdef14a 1085 dev_err(component->dev, "Failed to set fs speed: %d\n", ret);
81249307
PR		 1086 return ret;
1087 }
1088
5bdef14a
KM		 1089 dev_dbg(component->dev, "DSP divider %d\n", dsp_div);
1090 dev_dbg(component->dev, "DAC divider %d\n", dac_div);
1091 dev_dbg(component->dev, "NCP divider %d\n", ncp_div);
1092 dev_dbg(component->dev, "OSR divider %d\n", osr_div);
1093 dev_dbg(component->dev, "BCK divider %d\n", bclk_div);
1094 dev_dbg(component->dev, "LRCK divider %d\n", lrclk_div);
1095 dev_dbg(component->dev, "IDAC %d\n", idac);
1096 dev_dbg(component->dev, "1<<FSSP %d\n", 1 << fssp);
81249307
PR		 1097
1098 return 0;
1099}
1100
1101static int pcm512x_hw_params(struct snd_pcm_substream *substream,
1102 struct snd_pcm_hw_params *params,
1103 struct snd_soc_dai *dai)
1104{
5bdef14a
KM		 1105 struct snd_soc_component *component = dai->component;
1106 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
81249307 1107 int alen;
f086ba9d 1108 int gpio;
d11c2978
PR		 1109 int clock_output;
1110 int master_mode;
81249307
PR		 1111 int ret;
1112
5bdef14a 1113 dev_dbg(component->dev, "hw_params %u Hz, %u channels\n",
81249307
PR		 1114 params_rate(params),
1115 params_channels(params));
1116
0a3dcb50 1117 switch (params_width(params)) {
81249307
PR		 1118 case 16:
1119 alen = PCM512x_ALEN_16;
1120 break;
1121 case 20:
1122 alen = PCM512x_ALEN_20;
1123 break;
1124 case 24:
1125 alen = PCM512x_ALEN_24;
1126 break;
1127 case 32:
1128 alen = PCM512x_ALEN_32;
1129 break;
1130 default:
5bdef14a 1131 dev_err(component->dev, "Bad frame size: %d\n",
0a3dcb50 1132 params_width(params));
81249307
PR		 1133 return -EINVAL;
1134 }
1135
1136 switch (pcm512x->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1137 case SND_SOC_DAIFMT_CBS_CFS:
1138 ret = regmap_update_bits(pcm512x->regmap,
1139 PCM512x_BCLK_LRCLK_CFG,
1140 PCM512x_BCKP
1141 | PCM512x_BCKO | PCM512x_LRKO,
1142 0);
1143 if (ret != 0) {
5bdef14a 1144 dev_err(component->dev,
81249307
PR		 1145 "Failed to enable slave mode: %d\n", ret);
1146 return ret;
1147 }
1148
1149 ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT,
1150 PCM512x_DCAS, 0);
1151 if (ret != 0) {
5bdef14a 1152 dev_err(component->dev,
81249307
PR		 1153 "Failed to enable clock divider autoset: %d\n",
1154 ret);
1155 return ret;
1156 }
1157 return 0;
1158 case SND_SOC_DAIFMT_CBM_CFM:
d11c2978
PR		 1159 clock_output = PCM512x_BCKO | PCM512x_LRKO;
1160 master_mode = PCM512x_RLRK | PCM512x_RBCK;
1161 break;
1162 case SND_SOC_DAIFMT_CBM_CFS:
1163 clock_output = PCM512x_BCKO;
1164 master_mode = PCM512x_RBCK;
81249307
PR		 1165 break;
1166 default:
1167 return -EINVAL;
1168 }
1169
1170 ret = regmap_update_bits(pcm512x->regmap, PCM512x_I2S_1,
1171 PCM512x_ALEN, alen);
1172 if (ret != 0) {
5bdef14a 1173 dev_err(component->dev, "Failed to set frame size: %d\n", ret);
81249307
PR		 1174 return ret;
1175 }
1176
f086ba9d
PR		 1177 if (pcm512x->pll_out) {
1178 ret = regmap_write(pcm512x->regmap, PCM512x_FLEX_A, 0x11);
1179 if (ret != 0) {
5bdef14a 1180 dev_err(component->dev, "Failed to set FLEX_A: %d\n", ret);
f086ba9d
PR		 1181 return ret;
1182 }
81249307 1183
f086ba9d
PR		 1184 ret = regmap_write(pcm512x->regmap, PCM512x_FLEX_B, 0xff);
1185 if (ret != 0) {
5bdef14a 1186 dev_err(component->dev, "Failed to set FLEX_B: %d\n", ret);
f086ba9d
PR		 1187 return ret;
1188 }
1189
1190 ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT,
1191 PCM512x_IDFS | PCM512x_IDBK
1192 | PCM512x_IDSK | PCM512x_IDCH
1193 | PCM512x_IDCM | PCM512x_DCAS
1194 | PCM512x_IPLK,
1195 PCM512x_IDFS | PCM512x_IDBK
1196 | PCM512x_IDSK | PCM512x_IDCH
1197 | PCM512x_DCAS);
1198 if (ret != 0) {
5bdef14a 1199 dev_err(component->dev,
f086ba9d
PR		 1200 "Failed to ignore auto-clock failures: %d\n",
1201 ret);
1202 return ret;
1203 }
1204 } else {
1205 ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT,
1206 PCM512x_IDFS | PCM512x_IDBK
1207 | PCM512x_IDSK | PCM512x_IDCH
1208 | PCM512x_IDCM | PCM512x_DCAS
1209 | PCM512x_IPLK,
1210 PCM512x_IDFS | PCM512x_IDBK
1211 | PCM512x_IDSK | PCM512x_IDCH
1212 | PCM512x_DCAS | PCM512x_IPLK);
1213 if (ret != 0) {
5bdef14a 1214 dev_err(component->dev,
f086ba9d
PR		 1215 "Failed to ignore auto-clock failures: %d\n",
1216 ret);
1217 return ret;
1218 }
1219
1220 ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_EN,
1221 PCM512x_PLLE, 0);
1222 if (ret != 0) {
5bdef14a 1223 dev_err(component->dev, "Failed to disable pll: %d\n", ret);
f086ba9d
PR		 1224 return ret;
1225 }
81249307
PR		 1226 }
1227
1228 ret = pcm512x_set_dividers(dai, params);
1229 if (ret != 0)
1230 return ret;
1231
f086ba9d
PR		 1232 if (pcm512x->pll_out) {
1233 ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_REF,
1234 PCM512x_SREF, PCM512x_SREF_GPIO);
1235 if (ret != 0) {
5bdef14a 1236 dev_err(component->dev,
f086ba9d
PR		 1237 "Failed to set gpio as pllref: %d\n", ret);
1238 return ret;
1239 }
1240
1241 gpio = PCM512x_GREF_GPIO1 + pcm512x->pll_in - 1;
1242 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_PLLIN,
1243 PCM512x_GREF, gpio);
1244 if (ret != 0) {
5bdef14a 1245 dev_err(component->dev,
f086ba9d
PR		 1246 "Failed to set gpio %d as pllin: %d\n",
1247 pcm512x->pll_in, ret);
1248 return ret;
1249 }
1250
1251 ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_EN,
1252 PCM512x_PLLE, PCM512x_PLLE);
1253 if (ret != 0) {
5bdef14a 1254 dev_err(component->dev, "Failed to enable pll: %d\n", ret);
f086ba9d
PR		 1255 return ret;
1256 }
1257 }
1258
81249307
PR		 1259 ret = regmap_update_bits(pcm512x->regmap, PCM512x_BCLK_LRCLK_CFG,
1260 PCM512x_BCKP | PCM512x_BCKO | PCM512x_LRKO,
d11c2978 1261 clock_output);
81249307 1262 if (ret != 0) {
5bdef14a 1263 dev_err(component->dev, "Failed to enable clock output: %d\n", ret);
81249307
PR		 1264 return ret;
1265 }
1266
1267 ret = regmap_update_bits(pcm512x->regmap, PCM512x_MASTER_MODE,
1268 PCM512x_RLRK | PCM512x_RBCK,
d11c2978 1269 master_mode);
81249307 1270 if (ret != 0) {
5bdef14a 1271 dev_err(component->dev, "Failed to enable master mode: %d\n", ret);
81249307
PR		 1272 return ret;
1273 }
1274
f086ba9d
PR		 1275 if (pcm512x->pll_out) {
1276 gpio = PCM512x_G1OE << (pcm512x->pll_out - 1);
1277 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_EN,
1278 gpio, gpio);
1279 if (ret != 0) {
5bdef14a 1280 dev_err(component->dev, "Failed to enable gpio %d: %d\n",
f086ba9d
PR		 1281 pcm512x->pll_out, ret);
1282 return ret;
1283 }
1284
1285 gpio = PCM512x_GPIO_OUTPUT_1 + pcm512x->pll_out - 1;
1286 ret = regmap_update_bits(pcm512x->regmap, gpio,
1287 PCM512x_GxSL, PCM512x_GxSL_PLLCK);
1288 if (ret != 0) {
5bdef14a 1289 dev_err(component->dev, "Failed to output pll on %d: %d\n",
f086ba9d
PR		 1290 ret, pcm512x->pll_out);
1291 return ret;
1292 }
f086ba9d
PR		 1293 }
1294
81249307
PR		 1295 ret = regmap_update_bits(pcm512x->regmap, PCM512x_SYNCHRONIZE,
1296 PCM512x_RQSY, PCM512x_RQSY_HALT);
1297 if (ret != 0) {
5bdef14a 1298 dev_err(component->dev, "Failed to halt clocks: %d\n", ret);
81249307
PR		 1299 return ret;
1300 }
1301
1302 ret = regmap_update_bits(pcm512x->regmap, PCM512x_SYNCHRONIZE,
1303 PCM512x_RQSY, PCM512x_RQSY_RESUME);
1304 if (ret != 0) {
5bdef14a 1305 dev_err(component->dev, "Failed to resume clocks: %d\n", ret);
81249307
PR		 1306 return ret;
1307 }
1308
1309 return 0;
1310}
1311
1312static int pcm512x_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1313{
5bdef14a
KM		 1314 struct snd_soc_component *component = dai->component;
1315 struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);
81249307
PR		 1316
1317 pcm512x->fmt = fmt;
1318
1319 return 0;
1320}
1321
1322static const struct snd_soc_dai_ops pcm512x_dai_ops = {
1323 .startup = pcm512x_dai_startup,
1324 .hw_params = pcm512x_hw_params,
1325 .set_fmt = pcm512x_set_fmt,
1326};
1327
5a3af129
MB		 1328static struct snd_soc_dai_driver pcm512x_dai = {
1329 .name = "pcm512x-hifi",
1330 .playback = {
1331 .stream_name = "Playback",
1332 .channels_min = 2,
1333 .channels_max = 2,
81249307
PR		 1334 .rates = SNDRV_PCM_RATE_CONTINUOUS,
1335 .rate_min = 8000,
1336 .rate_max = 384000,
5a3af129
MB		 1337 .formats = SNDRV_PCM_FMTBIT_S16_LE |
1338 SNDRV_PCM_FMTBIT_S24_LE |
1339 SNDRV_PCM_FMTBIT_S32_LE
1340 },
81249307 1341 .ops = &pcm512x_dai_ops,
5a3af129
MB		 1342};
1343
5bdef14a
KM		 1344static const struct snd_soc_component_driver pcm512x_component_driver = {
1345 .set_bias_level = pcm512x_set_bias_level,
1346 .controls = pcm512x_controls,
1347 .num_controls = ARRAY_SIZE(pcm512x_controls),
1348 .dapm_widgets = pcm512x_dapm_widgets,
1349 .num_dapm_widgets = ARRAY_SIZE(pcm512x_dapm_widgets),
1350 .dapm_routes = pcm512x_dapm_routes,
1351 .num_dapm_routes = ARRAY_SIZE(pcm512x_dapm_routes),
1352 .use_pmdown_time = 1,
1353 .endianness = 1,
1354 .non_legacy_dai_naming = 1,
5a3af129
MB		 1355};
1356
806d6466
MB		 1357static const struct regmap_range_cfg pcm512x_range = {
1358 .name = "Pages", .range_min = PCM512x_VIRT_BASE,
1359 .range_max = PCM512x_MAX_REGISTER,
1360 .selector_reg = PCM512x_PAGE,
1361 .selector_mask = 0xff,
1362 .window_start = 0, .window_len = 0x100,
1363};
1364
22066226 1365const struct regmap_config pcm512x_regmap = {
5a3af129
MB		 1366 .reg_bits = 8,
1367 .val_bits = 8,
1368
1369 .readable_reg = pcm512x_readable,
1370 .volatile_reg = pcm512x_volatile,
1371
806d6466
MB		 1372 .ranges = &pcm512x_range,
1373 .num_ranges = 1,
1374
5a3af129
MB		 1375 .max_register = PCM512x_MAX_REGISTER,
1376 .reg_defaults = pcm512x_reg_defaults,
1377 .num_reg_defaults = ARRAY_SIZE(pcm512x_reg_defaults),
1378 .cache_type = REGCACHE_RBTREE,
1379};
22066226 1380EXPORT_SYMBOL_GPL(pcm512x_regmap);
5a3af129 1381
22066226 1382int pcm512x_probe(struct device *dev, struct regmap *regmap)
5a3af129
MB		 1383{
1384 struct pcm512x_priv *pcm512x;
1385 int i, ret;
1386
1387 pcm512x = devm_kzalloc(dev, sizeof(struct pcm512x_priv), GFP_KERNEL);
1388 if (!pcm512x)
1389 return -ENOMEM;
1390
1391 dev_set_drvdata(dev, pcm512x);
1392 pcm512x->regmap = regmap;
1393
1394 for (i = 0; i < ARRAY_SIZE(pcm512x->supplies); i++)
1395 pcm512x->supplies[i].supply = pcm512x_supply_names[i];
1396
1397 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pcm512x->supplies),
1398 pcm512x->supplies);
1399 if (ret != 0) {
1400 dev_err(dev, "Failed to get supplies: %d\n", ret);
1401 return ret;
1402 }
1403
1404 pcm512x->supply_nb[0].notifier_call = pcm512x_regulator_event_0;
1405 pcm512x->supply_nb[1].notifier_call = pcm512x_regulator_event_1;
1406 pcm512x->supply_nb[2].notifier_call = pcm512x_regulator_event_2;
1407
1408 for (i = 0; i < ARRAY_SIZE(pcm512x->supplies); i++) {
1409 ret = regulator_register_notifier(pcm512x->supplies[i].consumer,
1410 &pcm512x->supply_nb[i]);
1411 if (ret != 0) {
1412 dev_err(dev,
1413 "Failed to register regulator notifier: %d\n",
1414 ret);
1415 }
1416 }
1417
1418 ret = regulator_bulk_enable(ARRAY_SIZE(pcm512x->supplies),
1419 pcm512x->supplies);
1420 if (ret != 0) {
1421 dev_err(dev, "Failed to enable supplies: %d\n", ret);
1422 return ret;
1423 }
1424
1425 /* Reset the device, verifying I/O in the process for I2C */
1426 ret = regmap_write(regmap, PCM512x_RESET,
1427 PCM512x_RSTM | PCM512x_RSTR);
1428 if (ret != 0) {
1429 dev_err(dev, "Failed to reset device: %d\n", ret);
1430 goto err;
1431 }
1432
1433 ret = regmap_write(regmap, PCM512x_RESET, 0);
1434 if (ret != 0) {
1435 dev_err(dev, "Failed to reset device: %d\n", ret);
1436 goto err;
1437 }
1438
1439 pcm512x->sclk = devm_clk_get(dev, NULL);
81249307
PR		 1440 if (PTR_ERR(pcm512x->sclk) == -EPROBE_DEFER)
1441 return -EPROBE_DEFER;
1442 if (!IS_ERR(pcm512x->sclk)) {
5a3af129
MB		 1443 ret = clk_prepare_enable(pcm512x->sclk);
1444 if (ret != 0) {
1445 dev_err(dev, "Failed to enable SCLK: %d\n", ret);
1446 return ret;
1447 }
1448 }
1449
1450 /* Default to standby mode */
1451 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
1452 PCM512x_RQST, PCM512x_RQST);
1453 if (ret != 0) {
1454 dev_err(dev, "Failed to request standby: %d\n",
1455 ret);
1456 goto err_clk;
1457 }
1458
1459 pm_runtime_set_active(dev);
1460 pm_runtime_enable(dev);
1461 pm_runtime_idle(dev);
1462
f086ba9d
PR		 1463#ifdef CONFIG_OF
1464 if (dev->of_node) {
1465 const struct device_node *np = dev->of_node;
2599a960 1466 u32 val;
f086ba9d
PR		 1467
1468 if (of_property_read_u32(np, "pll-in", &val) >= 0) {
1469 if (val > 6) {
1470 dev_err(dev, "Invalid pll-in\n");
1471 ret = -EINVAL;
1472 goto err_clk;
1473 }
1474 pcm512x->pll_in = val;
1475 }
1476
1477 if (of_property_read_u32(np, "pll-out", &val) >= 0) {
1478 if (val > 6) {
1479 dev_err(dev, "Invalid pll-out\n");
1480 ret = -EINVAL;
1481 goto err_clk;
1482 }
1483 pcm512x->pll_out = val;
1484 }
1485
1486 if (!pcm512x->pll_in != !pcm512x->pll_out) {
1487 dev_err(dev,
1488 "Error: both pll-in and pll-out, or none\n");
1489 ret = -EINVAL;
1490 goto err_clk;
1491 }
1492 if (pcm512x->pll_in && pcm512x->pll_in == pcm512x->pll_out) {
1493 dev_err(dev, "Error: pll-in == pll-out\n");
1494 ret = -EINVAL;
1495 goto err_clk;
1496 }
1497 }
1498#endif
1499
5bdef14a 1500 ret = devm_snd_soc_register_component(dev, &pcm512x_component_driver,
5a3af129
MB		 1501 &pcm512x_dai, 1);
1502 if (ret != 0) {
1503 dev_err(dev, "Failed to register CODEC: %d\n", ret);
1504 goto err_pm;
1505 }
1506
1507 return 0;
1508
1509err_pm:
1510 pm_runtime_disable(dev);
1511err_clk:
1512 if (!IS_ERR(pcm512x->sclk))
1513 clk_disable_unprepare(pcm512x->sclk);
1514err:
1515 regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies),
1516 pcm512x->supplies);
1517 return ret;
1518}
22066226 1519EXPORT_SYMBOL_GPL(pcm512x_probe);
5a3af129 1520
22066226 1521void pcm512x_remove(struct device *dev)
5a3af129
MB		 1522{
1523 struct pcm512x_priv *pcm512x = dev_get_drvdata(dev);
1524
5a3af129
MB		 1525 pm_runtime_disable(dev);
1526 if (!IS_ERR(pcm512x->sclk))
1527 clk_disable_unprepare(pcm512x->sclk);
1528 regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies),
1529 pcm512x->supplies);
1530}
22066226 1531EXPORT_SYMBOL_GPL(pcm512x_remove);
5a3af129 1532
641d334b 1533#ifdef CONFIG_PM
5a3af129
MB		 1534static int pcm512x_suspend(struct device *dev)
1535{
1536 struct pcm512x_priv *pcm512x = dev_get_drvdata(dev);
1537 int ret;
1538
1539 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
1540 PCM512x_RQPD, PCM512x_RQPD);
1541 if (ret != 0) {
1542 dev_err(dev, "Failed to request power down: %d\n", ret);
1543 return ret;
1544 }
1545
1546 ret = regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies),
1547 pcm512x->supplies);
1548 if (ret != 0) {
1549 dev_err(dev, "Failed to disable supplies: %d\n", ret);
1550 return ret;
1551 }
1552
1553 if (!IS_ERR(pcm512x->sclk))
1554 clk_disable_unprepare(pcm512x->sclk);
1555
1556 return 0;
1557}
1558
1559static int pcm512x_resume(struct device *dev)
1560{
1561 struct pcm512x_priv *pcm512x = dev_get_drvdata(dev);
1562 int ret;
1563
1564 if (!IS_ERR(pcm512x->sclk)) {
1565 ret = clk_prepare_enable(pcm512x->sclk);
1566 if (ret != 0) {
1567 dev_err(dev, "Failed to enable SCLK: %d\n", ret);
1568 return ret;
1569 }
1570 }
1571
1572 ret = regulator_bulk_enable(ARRAY_SIZE(pcm512x->supplies),
1573 pcm512x->supplies);
1574 if (ret != 0) {
1575 dev_err(dev, "Failed to enable supplies: %d\n", ret);
1576 return ret;
1577 }
1578
1579 regcache_cache_only(pcm512x->regmap, false);
1580 ret = regcache_sync(pcm512x->regmap);
1581 if (ret != 0) {
1582 dev_err(dev, "Failed to sync cache: %d\n", ret);
1583 return ret;
1584 }
1585
1586 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
1587 PCM512x_RQPD, 0);
1588 if (ret != 0) {
1589 dev_err(dev, "Failed to remove power down: %d\n", ret);
1590 return ret;
1591 }
1592
1593 return 0;
1594}
ccffbd27 1595#endif
5a3af129 1596
22066226 1597const struct dev_pm_ops pcm512x_pm_ops = {
5a3af129
MB		 1598 SET_RUNTIME_PM_OPS(pcm512x_suspend, pcm512x_resume, NULL)
1599};
22066226 1600EXPORT_SYMBOL_GPL(pcm512x_pm_ops);
5a3af129
MB		 1601
1602MODULE_DESCRIPTION("ASoC PCM512x codec driver");
da924c3a 1603MODULE_AUTHOR("Mark Brown <broonie@kernel.org>");
5a3af129 1604MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)