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1802d0be | 1 | // SPDX-License-Identifier: GPL-2.0-only |
5a3af129 MB |
2 | /* |
3 | * Driver for the PCM512x CODECs | |
4 | * | |
da924c3a | 5 | * Author: Mark Brown <broonie@kernel.org> |
5a3af129 | 6 | * Copyright 2014 Linaro Ltd |
5a3af129 MB |
7 | */ |
8 | ||
9 | ||
10 | #include <linux/init.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/clk.h> | |
d48502ea | 13 | #include <linux/kernel.h> |
5a3af129 MB |
14 | #include <linux/pm_runtime.h> |
15 | #include <linux/regmap.h> | |
16 | #include <linux/regulator/consumer.h> | |
f086ba9d | 17 | #include <linux/gcd.h> |
5a3af129 MB |
18 | #include <sound/soc.h> |
19 | #include <sound/soc-dapm.h> | |
81249307 | 20 | #include <sound/pcm_params.h> |
5a3af129 MB |
21 | #include <sound/tlv.h> |
22 | ||
23 | #include "pcm512x.h" | |
24 | ||
25 | #define PCM512x_NUM_SUPPLIES 3 | |
06d0ffcc | 26 | static const char * const pcm512x_supply_names[PCM512x_NUM_SUPPLIES] = { |
5a3af129 MB |
27 | "AVDD", |
28 | "DVDD", | |
29 | "CPVDD", | |
30 | }; | |
31 | ||
32 | struct pcm512x_priv { | |
33 | struct regmap *regmap; | |
34 | struct clk *sclk; | |
35 | struct regulator_bulk_data supplies[PCM512x_NUM_SUPPLIES]; | |
36 | struct notifier_block supply_nb[PCM512x_NUM_SUPPLIES]; | |
81249307 | 37 | int fmt; |
f086ba9d PR |
38 | int pll_in; |
39 | int pll_out; | |
40 | int pll_r; | |
41 | int pll_j; | |
42 | int pll_d; | |
43 | int pll_p; | |
44 | unsigned long real_pll; | |
f29933c9 PR |
45 | unsigned long overclock_pll; |
46 | unsigned long overclock_dac; | |
47 | unsigned long overclock_dsp; | |
3500f1c5 DP |
48 | int mute; |
49 | struct mutex mutex; | |
ccc8d6c7 | 50 | unsigned int bclk_ratio; |
5a3af129 MB |
51 | }; |
52 | ||
53 | /* | |
54 | * We can't use the same notifier block for more than one supply and | |
55 | * there's no way I can see to get from a callback to the caller | |
56 | * except container_of(). | |
57 | */ | |
58 | #define PCM512x_REGULATOR_EVENT(n) \ | |
59 | static int pcm512x_regulator_event_##n(struct notifier_block *nb, \ | |
60 | unsigned long event, void *data) \ | |
61 | { \ | |
62 | struct pcm512x_priv *pcm512x = container_of(nb, struct pcm512x_priv, \ | |
63 | supply_nb[n]); \ | |
64 | if (event & REGULATOR_EVENT_DISABLE) { \ | |
65 | regcache_mark_dirty(pcm512x->regmap); \ | |
66 | regcache_cache_only(pcm512x->regmap, true); \ | |
67 | } \ | |
68 | return 0; \ | |
69 | } | |
70 | ||
71 | PCM512x_REGULATOR_EVENT(0) | |
72 | PCM512x_REGULATOR_EVENT(1) | |
73 | PCM512x_REGULATOR_EVENT(2) | |
74 | ||
75 | static const struct reg_default pcm512x_reg_defaults[] = { | |
806d6466 MB |
76 | { PCM512x_RESET, 0x00 }, |
77 | { PCM512x_POWER, 0x00 }, | |
78 | { PCM512x_MUTE, 0x00 }, | |
79 | { PCM512x_DSP, 0x00 }, | |
80 | { PCM512x_PLL_REF, 0x00 }, | |
81249307 | 81 | { PCM512x_DAC_REF, 0x00 }, |
806d6466 MB |
82 | { PCM512x_DAC_ROUTING, 0x11 }, |
83 | { PCM512x_DSP_PROGRAM, 0x01 }, | |
84 | { PCM512x_CLKDET, 0x00 }, | |
85 | { PCM512x_AUTO_MUTE, 0x00 }, | |
86 | { PCM512x_ERROR_DETECT, 0x00 }, | |
87 | { PCM512x_DIGITAL_VOLUME_1, 0x00 }, | |
88 | { PCM512x_DIGITAL_VOLUME_2, 0x30 }, | |
89 | { PCM512x_DIGITAL_VOLUME_3, 0x30 }, | |
90 | { PCM512x_DIGITAL_MUTE_1, 0x22 }, | |
91 | { PCM512x_DIGITAL_MUTE_2, 0x00 }, | |
92 | { PCM512x_DIGITAL_MUTE_3, 0x07 }, | |
93 | { PCM512x_OUTPUT_AMPLITUDE, 0x00 }, | |
94 | { PCM512x_ANALOG_GAIN_CTRL, 0x00 }, | |
95 | { PCM512x_UNDERVOLTAGE_PROT, 0x00 }, | |
96 | { PCM512x_ANALOG_MUTE_CTRL, 0x00 }, | |
97 | { PCM512x_ANALOG_GAIN_BOOST, 0x00 }, | |
98 | { PCM512x_VCOM_CTRL_1, 0x00 }, | |
99 | { PCM512x_VCOM_CTRL_2, 0x01 }, | |
81249307 PR |
100 | { PCM512x_BCLK_LRCLK_CFG, 0x00 }, |
101 | { PCM512x_MASTER_MODE, 0x7c }, | |
7c4e1119 | 102 | { PCM512x_GPIO_DACIN, 0x00 }, |
f086ba9d | 103 | { PCM512x_GPIO_PLLIN, 0x00 }, |
81249307 | 104 | { PCM512x_SYNCHRONIZE, 0x10 }, |
f086ba9d PR |
105 | { PCM512x_PLL_COEFF_0, 0x00 }, |
106 | { PCM512x_PLL_COEFF_1, 0x00 }, | |
107 | { PCM512x_PLL_COEFF_2, 0x00 }, | |
108 | { PCM512x_PLL_COEFF_3, 0x00 }, | |
109 | { PCM512x_PLL_COEFF_4, 0x00 }, | |
81249307 PR |
110 | { PCM512x_DSP_CLKDIV, 0x00 }, |
111 | { PCM512x_DAC_CLKDIV, 0x00 }, | |
112 | { PCM512x_NCP_CLKDIV, 0x00 }, | |
113 | { PCM512x_OSR_CLKDIV, 0x00 }, | |
114 | { PCM512x_MASTER_CLKDIV_1, 0x00 }, | |
115 | { PCM512x_MASTER_CLKDIV_2, 0x00 }, | |
116 | { PCM512x_FS_SPEED_MODE, 0x00 }, | |
117 | { PCM512x_IDAC_1, 0x01 }, | |
118 | { PCM512x_IDAC_2, 0x00 }, | |
3f4b57ad PR |
119 | { PCM512x_I2S_1, 0x02 }, |
120 | { PCM512x_I2S_2, 0x00 }, | |
5a3af129 MB |
121 | }; |
122 | ||
123 | static bool pcm512x_readable(struct device *dev, unsigned int reg) | |
124 | { | |
125 | switch (reg) { | |
126 | case PCM512x_RESET: | |
127 | case PCM512x_POWER: | |
128 | case PCM512x_MUTE: | |
129 | case PCM512x_PLL_EN: | |
130 | case PCM512x_SPI_MISO_FUNCTION: | |
131 | case PCM512x_DSP: | |
132 | case PCM512x_GPIO_EN: | |
133 | case PCM512x_BCLK_LRCLK_CFG: | |
134 | case PCM512x_DSP_GPIO_INPUT: | |
135 | case PCM512x_MASTER_MODE: | |
136 | case PCM512x_PLL_REF: | |
81249307 | 137 | case PCM512x_DAC_REF: |
7c4e1119 | 138 | case PCM512x_GPIO_DACIN: |
f086ba9d | 139 | case PCM512x_GPIO_PLLIN: |
81249307 | 140 | case PCM512x_SYNCHRONIZE: |
5a3af129 MB |
141 | case PCM512x_PLL_COEFF_0: |
142 | case PCM512x_PLL_COEFF_1: | |
143 | case PCM512x_PLL_COEFF_2: | |
144 | case PCM512x_PLL_COEFF_3: | |
145 | case PCM512x_PLL_COEFF_4: | |
146 | case PCM512x_DSP_CLKDIV: | |
147 | case PCM512x_DAC_CLKDIV: | |
148 | case PCM512x_NCP_CLKDIV: | |
149 | case PCM512x_OSR_CLKDIV: | |
150 | case PCM512x_MASTER_CLKDIV_1: | |
151 | case PCM512x_MASTER_CLKDIV_2: | |
152 | case PCM512x_FS_SPEED_MODE: | |
153 | case PCM512x_IDAC_1: | |
154 | case PCM512x_IDAC_2: | |
155 | case PCM512x_ERROR_DETECT: | |
156 | case PCM512x_I2S_1: | |
157 | case PCM512x_I2S_2: | |
158 | case PCM512x_DAC_ROUTING: | |
159 | case PCM512x_DSP_PROGRAM: | |
160 | case PCM512x_CLKDET: | |
161 | case PCM512x_AUTO_MUTE: | |
162 | case PCM512x_DIGITAL_VOLUME_1: | |
163 | case PCM512x_DIGITAL_VOLUME_2: | |
164 | case PCM512x_DIGITAL_VOLUME_3: | |
165 | case PCM512x_DIGITAL_MUTE_1: | |
166 | case PCM512x_DIGITAL_MUTE_2: | |
167 | case PCM512x_DIGITAL_MUTE_3: | |
168 | case PCM512x_GPIO_OUTPUT_1: | |
169 | case PCM512x_GPIO_OUTPUT_2: | |
170 | case PCM512x_GPIO_OUTPUT_3: | |
171 | case PCM512x_GPIO_OUTPUT_4: | |
172 | case PCM512x_GPIO_OUTPUT_5: | |
173 | case PCM512x_GPIO_OUTPUT_6: | |
174 | case PCM512x_GPIO_CONTROL_1: | |
175 | case PCM512x_GPIO_CONTROL_2: | |
176 | case PCM512x_OVERFLOW: | |
177 | case PCM512x_RATE_DET_1: | |
178 | case PCM512x_RATE_DET_2: | |
179 | case PCM512x_RATE_DET_3: | |
180 | case PCM512x_RATE_DET_4: | |
f086ba9d | 181 | case PCM512x_CLOCK_STATUS: |
5a3af129 MB |
182 | case PCM512x_ANALOG_MUTE_DET: |
183 | case PCM512x_GPIN: | |
184 | case PCM512x_DIGITAL_MUTE_DET: | |
806d6466 MB |
185 | case PCM512x_OUTPUT_AMPLITUDE: |
186 | case PCM512x_ANALOG_GAIN_CTRL: | |
187 | case PCM512x_UNDERVOLTAGE_PROT: | |
188 | case PCM512x_ANALOG_MUTE_CTRL: | |
189 | case PCM512x_ANALOG_GAIN_BOOST: | |
190 | case PCM512x_VCOM_CTRL_1: | |
191 | case PCM512x_VCOM_CTRL_2: | |
192 | case PCM512x_CRAM_CTRL: | |
f086ba9d PR |
193 | case PCM512x_FLEX_A: |
194 | case PCM512x_FLEX_B: | |
5a3af129 MB |
195 | return true; |
196 | default: | |
806d6466 MB |
197 | /* There are 256 raw register addresses */ |
198 | return reg < 0xff; | |
5a3af129 MB |
199 | } |
200 | } | |
201 | ||
202 | static bool pcm512x_volatile(struct device *dev, unsigned int reg) | |
203 | { | |
204 | switch (reg) { | |
205 | case PCM512x_PLL_EN: | |
206 | case PCM512x_OVERFLOW: | |
207 | case PCM512x_RATE_DET_1: | |
208 | case PCM512x_RATE_DET_2: | |
209 | case PCM512x_RATE_DET_3: | |
210 | case PCM512x_RATE_DET_4: | |
f086ba9d | 211 | case PCM512x_CLOCK_STATUS: |
5a3af129 MB |
212 | case PCM512x_ANALOG_MUTE_DET: |
213 | case PCM512x_GPIN: | |
214 | case PCM512x_DIGITAL_MUTE_DET: | |
806d6466 | 215 | case PCM512x_CRAM_CTRL: |
5a3af129 MB |
216 | return true; |
217 | default: | |
806d6466 MB |
218 | /* There are 256 raw register addresses */ |
219 | return reg < 0xff; | |
5a3af129 MB |
220 | } |
221 | } | |
222 | ||
f29933c9 PR |
223 | static int pcm512x_overclock_pll_get(struct snd_kcontrol *kcontrol, |
224 | struct snd_ctl_elem_value *ucontrol) | |
225 | { | |
5bdef14a KM |
226 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
227 | struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); | |
f29933c9 PR |
228 | |
229 | ucontrol->value.integer.value[0] = pcm512x->overclock_pll; | |
230 | return 0; | |
231 | } | |
232 | ||
233 | static int pcm512x_overclock_pll_put(struct snd_kcontrol *kcontrol, | |
234 | struct snd_ctl_elem_value *ucontrol) | |
235 | { | |
5bdef14a KM |
236 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
237 | struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); | |
f29933c9 | 238 | |
5bdef14a | 239 | switch (snd_soc_component_get_bias_level(component)) { |
f29933c9 PR |
240 | case SND_SOC_BIAS_OFF: |
241 | case SND_SOC_BIAS_STANDBY: | |
242 | break; | |
243 | default: | |
244 | return -EBUSY; | |
245 | } | |
246 | ||
247 | pcm512x->overclock_pll = ucontrol->value.integer.value[0]; | |
248 | return 0; | |
249 | } | |
250 | ||
251 | static int pcm512x_overclock_dsp_get(struct snd_kcontrol *kcontrol, | |
252 | struct snd_ctl_elem_value *ucontrol) | |
253 | { | |
5bdef14a KM |
254 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
255 | struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); | |
f29933c9 PR |
256 | |
257 | ucontrol->value.integer.value[0] = pcm512x->overclock_dsp; | |
258 | return 0; | |
259 | } | |
260 | ||
261 | static int pcm512x_overclock_dsp_put(struct snd_kcontrol *kcontrol, | |
262 | struct snd_ctl_elem_value *ucontrol) | |
263 | { | |
5bdef14a KM |
264 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
265 | struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); | |
f29933c9 | 266 | |
5bdef14a | 267 | switch (snd_soc_component_get_bias_level(component)) { |
f29933c9 PR |
268 | case SND_SOC_BIAS_OFF: |
269 | case SND_SOC_BIAS_STANDBY: | |
270 | break; | |
271 | default: | |
272 | return -EBUSY; | |
273 | } | |
274 | ||
275 | pcm512x->overclock_dsp = ucontrol->value.integer.value[0]; | |
276 | return 0; | |
277 | } | |
278 | ||
279 | static int pcm512x_overclock_dac_get(struct snd_kcontrol *kcontrol, | |
280 | struct snd_ctl_elem_value *ucontrol) | |
281 | { | |
5bdef14a KM |
282 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
283 | struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); | |
f29933c9 PR |
284 | |
285 | ucontrol->value.integer.value[0] = pcm512x->overclock_dac; | |
286 | return 0; | |
287 | } | |
288 | ||
289 | static int pcm512x_overclock_dac_put(struct snd_kcontrol *kcontrol, | |
290 | struct snd_ctl_elem_value *ucontrol) | |
291 | { | |
5bdef14a KM |
292 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
293 | struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); | |
f29933c9 | 294 | |
5bdef14a | 295 | switch (snd_soc_component_get_bias_level(component)) { |
f29933c9 PR |
296 | case SND_SOC_BIAS_OFF: |
297 | case SND_SOC_BIAS_STANDBY: | |
298 | break; | |
299 | default: | |
300 | return -EBUSY; | |
301 | } | |
302 | ||
303 | pcm512x->overclock_dac = ucontrol->value.integer.value[0]; | |
304 | return 0; | |
305 | } | |
306 | ||
5a3af129 | 307 | static const DECLARE_TLV_DB_SCALE(digital_tlv, -10350, 50, 1); |
5be2fc20 MB |
308 | static const DECLARE_TLV_DB_SCALE(analog_tlv, -600, 600, 0); |
309 | static const DECLARE_TLV_DB_SCALE(boost_tlv, 0, 80, 0); | |
5a3af129 | 310 | |
06d0ffcc | 311 | static const char * const pcm512x_dsp_program_texts[] = { |
5a3af129 MB |
312 | "FIR interpolation with de-emphasis", |
313 | "Low latency IIR with de-emphasis", | |
5a3af129 | 314 | "High attenuation with de-emphasis", |
3a8e5019 | 315 | "Fixed process flow", |
5a3af129 MB |
316 | "Ringing-less low latency FIR", |
317 | }; | |
318 | ||
319 | static const unsigned int pcm512x_dsp_program_values[] = { | |
320 | 1, | |
321 | 2, | |
322 | 3, | |
323 | 5, | |
324 | 7, | |
325 | }; | |
326 | ||
e97db9ab MB |
327 | static SOC_VALUE_ENUM_SINGLE_DECL(pcm512x_dsp_program, |
328 | PCM512x_DSP_PROGRAM, 0, 0x1f, | |
329 | pcm512x_dsp_program_texts, | |
330 | pcm512x_dsp_program_values); | |
5a3af129 | 331 | |
06d0ffcc | 332 | static const char * const pcm512x_clk_missing_text[] = { |
5a3af129 MB |
333 | "1s", "2s", "3s", "4s", "5s", "6s", "7s", "8s" |
334 | }; | |
335 | ||
336 | static const struct soc_enum pcm512x_clk_missing = | |
337 | SOC_ENUM_SINGLE(PCM512x_CLKDET, 0, 8, pcm512x_clk_missing_text); | |
338 | ||
06d0ffcc | 339 | static const char * const pcm512x_autom_text[] = { |
5a3af129 MB |
340 | "21ms", "106ms", "213ms", "533ms", "1.07s", "2.13s", "5.33s", "10.66s" |
341 | }; | |
342 | ||
343 | static const struct soc_enum pcm512x_autom_l = | |
344 | SOC_ENUM_SINGLE(PCM512x_AUTO_MUTE, PCM512x_ATML_SHIFT, 8, | |
345 | pcm512x_autom_text); | |
346 | ||
347 | static const struct soc_enum pcm512x_autom_r = | |
348 | SOC_ENUM_SINGLE(PCM512x_AUTO_MUTE, PCM512x_ATMR_SHIFT, 8, | |
349 | pcm512x_autom_text); | |
350 | ||
06d0ffcc | 351 | static const char * const pcm512x_ramp_rate_text[] = { |
5a3af129 MB |
352 | "1 sample/update", "2 samples/update", "4 samples/update", |
353 | "Immediate" | |
354 | }; | |
355 | ||
356 | static const struct soc_enum pcm512x_vndf = | |
357 | SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNDF_SHIFT, 4, | |
358 | pcm512x_ramp_rate_text); | |
359 | ||
360 | static const struct soc_enum pcm512x_vnuf = | |
361 | SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNUF_SHIFT, 4, | |
362 | pcm512x_ramp_rate_text); | |
363 | ||
364 | static const struct soc_enum pcm512x_vedf = | |
365 | SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_2, PCM512x_VEDF_SHIFT, 4, | |
366 | pcm512x_ramp_rate_text); | |
367 | ||
06d0ffcc | 368 | static const char * const pcm512x_ramp_step_text[] = { |
5a3af129 MB |
369 | "4dB/step", "2dB/step", "1dB/step", "0.5dB/step" |
370 | }; | |
371 | ||
372 | static const struct soc_enum pcm512x_vnds = | |
373 | SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNDS_SHIFT, 4, | |
374 | pcm512x_ramp_step_text); | |
375 | ||
376 | static const struct soc_enum pcm512x_vnus = | |
377 | SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNUS_SHIFT, 4, | |
378 | pcm512x_ramp_step_text); | |
379 | ||
380 | static const struct soc_enum pcm512x_veds = | |
381 | SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_2, PCM512x_VEDS_SHIFT, 4, | |
382 | pcm512x_ramp_step_text); | |
383 | ||
3500f1c5 DP |
384 | static int pcm512x_update_mute(struct pcm512x_priv *pcm512x) |
385 | { | |
386 | return regmap_update_bits( | |
387 | pcm512x->regmap, PCM512x_MUTE, PCM512x_RQML | PCM512x_RQMR, | |
388 | (!!(pcm512x->mute & 0x5) << PCM512x_RQML_SHIFT) | |
389 | | (!!(pcm512x->mute & 0x3) << PCM512x_RQMR_SHIFT)); | |
390 | } | |
391 | ||
392 | static int pcm512x_digital_playback_switch_get(struct snd_kcontrol *kcontrol, | |
393 | struct snd_ctl_elem_value *ucontrol) | |
394 | { | |
395 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); | |
396 | struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); | |
397 | ||
398 | mutex_lock(&pcm512x->mutex); | |
399 | ucontrol->value.integer.value[0] = !(pcm512x->mute & 0x4); | |
400 | ucontrol->value.integer.value[1] = !(pcm512x->mute & 0x2); | |
401 | mutex_unlock(&pcm512x->mutex); | |
402 | ||
403 | return 0; | |
404 | } | |
405 | ||
406 | static int pcm512x_digital_playback_switch_put(struct snd_kcontrol *kcontrol, | |
407 | struct snd_ctl_elem_value *ucontrol) | |
408 | { | |
409 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); | |
410 | struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); | |
411 | int ret, changed = 0; | |
412 | ||
413 | mutex_lock(&pcm512x->mutex); | |
414 | ||
415 | if ((pcm512x->mute & 0x4) == (ucontrol->value.integer.value[0] << 2)) { | |
416 | pcm512x->mute ^= 0x4; | |
417 | changed = 1; | |
418 | } | |
419 | if ((pcm512x->mute & 0x2) == (ucontrol->value.integer.value[1] << 1)) { | |
420 | pcm512x->mute ^= 0x2; | |
421 | changed = 1; | |
422 | } | |
423 | ||
424 | if (changed) { | |
425 | ret = pcm512x_update_mute(pcm512x); | |
426 | if (ret != 0) { | |
427 | dev_err(component->dev, | |
428 | "Failed to update digital mute: %d\n", ret); | |
429 | mutex_unlock(&pcm512x->mutex); | |
430 | return ret; | |
431 | } | |
432 | } | |
433 | ||
434 | mutex_unlock(&pcm512x->mutex); | |
435 | ||
436 | return changed; | |
437 | } | |
438 | ||
5a3af129 | 439 | static const struct snd_kcontrol_new pcm512x_controls[] = { |
1c6d3680 | 440 | SOC_DOUBLE_R_TLV("Digital Playback Volume", PCM512x_DIGITAL_VOLUME_2, |
5a3af129 | 441 | PCM512x_DIGITAL_VOLUME_3, 0, 255, 1, digital_tlv), |
4d9b13c7 | 442 | SOC_DOUBLE_TLV("Analogue Playback Volume", PCM512x_ANALOG_GAIN_CTRL, |
5be2fc20 | 443 | PCM512x_LAGN_SHIFT, PCM512x_RAGN_SHIFT, 1, 1, analog_tlv), |
4d9b13c7 | 444 | SOC_DOUBLE_TLV("Analogue Playback Boost Volume", PCM512x_ANALOG_GAIN_BOOST, |
5be2fc20 | 445 | PCM512x_AGBL_SHIFT, PCM512x_AGBR_SHIFT, 1, 0, boost_tlv), |
3500f1c5 DP |
446 | { |
447 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
448 | .name = "Digital Playback Switch", | |
449 | .index = 0, | |
450 | .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, | |
451 | .info = snd_ctl_boolean_stereo_info, | |
452 | .get = pcm512x_digital_playback_switch_get, | |
453 | .put = pcm512x_digital_playback_switch_put | |
454 | }, | |
5a3af129 MB |
455 | |
456 | SOC_SINGLE("Deemphasis Switch", PCM512x_DSP, PCM512x_DEMP_SHIFT, 1, 1), | |
54581be7 | 457 | SOC_ENUM("DSP Program", pcm512x_dsp_program), |
5a3af129 MB |
458 | |
459 | SOC_ENUM("Clock Missing Period", pcm512x_clk_missing), | |
460 | SOC_ENUM("Auto Mute Time Left", pcm512x_autom_l), | |
461 | SOC_ENUM("Auto Mute Time Right", pcm512x_autom_r), | |
462 | SOC_SINGLE("Auto Mute Mono Switch", PCM512x_DIGITAL_MUTE_3, | |
463 | PCM512x_ACTL_SHIFT, 1, 0), | |
464 | SOC_DOUBLE("Auto Mute Switch", PCM512x_DIGITAL_MUTE_3, PCM512x_AMLE_SHIFT, | |
376dc490 | 465 | PCM512x_AMRE_SHIFT, 1, 0), |
5a3af129 MB |
466 | |
467 | SOC_ENUM("Volume Ramp Down Rate", pcm512x_vndf), | |
468 | SOC_ENUM("Volume Ramp Down Step", pcm512x_vnds), | |
469 | SOC_ENUM("Volume Ramp Up Rate", pcm512x_vnuf), | |
470 | SOC_ENUM("Volume Ramp Up Step", pcm512x_vnus), | |
471 | SOC_ENUM("Volume Ramp Down Emergency Rate", pcm512x_vedf), | |
472 | SOC_ENUM("Volume Ramp Down Emergency Step", pcm512x_veds), | |
f29933c9 PR |
473 | |
474 | SOC_SINGLE_EXT("Max Overclock PLL", SND_SOC_NOPM, 0, 20, 0, | |
475 | pcm512x_overclock_pll_get, pcm512x_overclock_pll_put), | |
476 | SOC_SINGLE_EXT("Max Overclock DSP", SND_SOC_NOPM, 0, 40, 0, | |
477 | pcm512x_overclock_dsp_get, pcm512x_overclock_dsp_put), | |
478 | SOC_SINGLE_EXT("Max Overclock DAC", SND_SOC_NOPM, 0, 40, 0, | |
479 | pcm512x_overclock_dac_get, pcm512x_overclock_dac_put), | |
5a3af129 MB |
480 | }; |
481 | ||
482 | static const struct snd_soc_dapm_widget pcm512x_dapm_widgets[] = { | |
483 | SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0), | |
484 | SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0), | |
485 | ||
486 | SND_SOC_DAPM_OUTPUT("OUTL"), | |
487 | SND_SOC_DAPM_OUTPUT("OUTR"), | |
488 | }; | |
489 | ||
490 | static const struct snd_soc_dapm_route pcm512x_dapm_routes[] = { | |
491 | { "DACL", NULL, "Playback" }, | |
492 | { "DACR", NULL, "Playback" }, | |
493 | ||
494 | { "OUTL", NULL, "DACL" }, | |
495 | { "OUTR", NULL, "DACR" }, | |
496 | }; | |
497 | ||
f29933c9 PR |
498 | static unsigned long pcm512x_pll_max(struct pcm512x_priv *pcm512x) |
499 | { | |
500 | return 25000000 + 25000000 * pcm512x->overclock_pll / 100; | |
501 | } | |
502 | ||
503 | static unsigned long pcm512x_dsp_max(struct pcm512x_priv *pcm512x) | |
504 | { | |
505 | return 50000000 + 50000000 * pcm512x->overclock_dsp / 100; | |
506 | } | |
507 | ||
508 | static unsigned long pcm512x_dac_max(struct pcm512x_priv *pcm512x, | |
509 | unsigned long rate) | |
510 | { | |
511 | return rate + rate * pcm512x->overclock_dac / 100; | |
512 | } | |
513 | ||
514 | static unsigned long pcm512x_sck_max(struct pcm512x_priv *pcm512x) | |
515 | { | |
516 | if (!pcm512x->pll_out) | |
517 | return 25000000; | |
518 | return pcm512x_pll_max(pcm512x); | |
519 | } | |
520 | ||
521 | static unsigned long pcm512x_ncp_target(struct pcm512x_priv *pcm512x, | |
522 | unsigned long dac_rate) | |
523 | { | |
524 | /* | |
525 | * If the DAC is not actually overclocked, use the good old | |
526 | * NCP target rate... | |
527 | */ | |
528 | if (dac_rate <= 6144000) | |
529 | return 1536000; | |
530 | /* | |
531 | * ...but if the DAC is in fact overclocked, bump the NCP target | |
532 | * rate to get the recommended dividers even when overclocking. | |
533 | */ | |
534 | return pcm512x_dac_max(pcm512x, 1536000); | |
535 | } | |
536 | ||
81249307 PR |
537 | static const u32 pcm512x_dai_rates[] = { |
538 | 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, | |
539 | 88200, 96000, 176400, 192000, 384000, | |
540 | }; | |
541 | ||
542 | static const struct snd_pcm_hw_constraint_list constraints_slave = { | |
543 | .count = ARRAY_SIZE(pcm512x_dai_rates), | |
544 | .list = pcm512x_dai_rates, | |
545 | }; | |
546 | ||
f086ba9d PR |
547 | static int pcm512x_hw_rule_rate(struct snd_pcm_hw_params *params, |
548 | struct snd_pcm_hw_rule *rule) | |
549 | { | |
f29933c9 | 550 | struct pcm512x_priv *pcm512x = rule->private; |
9c7da1a5 | 551 | struct snd_interval ranges[2]; |
f086ba9d PR |
552 | int frame_size; |
553 | ||
554 | frame_size = snd_soc_params_to_frame_size(params); | |
555 | if (frame_size < 0) | |
556 | return frame_size; | |
557 | ||
9c7da1a5 PR |
558 | switch (frame_size) { |
559 | case 32: | |
560 | /* No hole when the frame size is 32. */ | |
f086ba9d | 561 | return 0; |
9c7da1a5 PR |
562 | case 48: |
563 | case 64: | |
564 | /* There is only one hole in the range of supported | |
565 | * rates, but it moves with the frame size. | |
566 | */ | |
567 | memset(ranges, 0, sizeof(ranges)); | |
568 | ranges[0].min = 8000; | |
f29933c9 | 569 | ranges[0].max = pcm512x_sck_max(pcm512x) / frame_size / 2; |
9c7da1a5 PR |
570 | ranges[1].min = DIV_ROUND_UP(16000000, frame_size); |
571 | ranges[1].max = 384000; | |
572 | break; | |
573 | default: | |
574 | return -EINVAL; | |
575 | } | |
f086ba9d PR |
576 | |
577 | return snd_interval_ranges(hw_param_interval(params, rule->var), | |
9c7da1a5 | 578 | ARRAY_SIZE(ranges), ranges, 0); |
f086ba9d PR |
579 | } |
580 | ||
81249307 PR |
581 | static int pcm512x_dai_startup_master(struct snd_pcm_substream *substream, |
582 | struct snd_soc_dai *dai) | |
583 | { | |
5bdef14a KM |
584 | struct snd_soc_component *component = dai->component; |
585 | struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); | |
81249307 PR |
586 | struct device *dev = dai->dev; |
587 | struct snd_pcm_hw_constraint_ratnums *constraints_no_pll; | |
588 | struct snd_ratnum *rats_no_pll; | |
589 | ||
590 | if (IS_ERR(pcm512x->sclk)) { | |
591 | dev_err(dev, "Need SCLK for master mode: %ld\n", | |
592 | PTR_ERR(pcm512x->sclk)); | |
593 | return PTR_ERR(pcm512x->sclk); | |
594 | } | |
595 | ||
f086ba9d PR |
596 | if (pcm512x->pll_out) |
597 | return snd_pcm_hw_rule_add(substream->runtime, 0, | |
598 | SNDRV_PCM_HW_PARAM_RATE, | |
599 | pcm512x_hw_rule_rate, | |
f29933c9 | 600 | pcm512x, |
f086ba9d PR |
601 | SNDRV_PCM_HW_PARAM_FRAME_BITS, |
602 | SNDRV_PCM_HW_PARAM_CHANNELS, -1); | |
603 | ||
81249307 PR |
604 | constraints_no_pll = devm_kzalloc(dev, sizeof(*constraints_no_pll), |
605 | GFP_KERNEL); | |
606 | if (!constraints_no_pll) | |
607 | return -ENOMEM; | |
608 | constraints_no_pll->nrats = 1; | |
609 | rats_no_pll = devm_kzalloc(dev, sizeof(*rats_no_pll), GFP_KERNEL); | |
610 | if (!rats_no_pll) | |
611 | return -ENOMEM; | |
612 | constraints_no_pll->rats = rats_no_pll; | |
613 | rats_no_pll->num = clk_get_rate(pcm512x->sclk) / 64; | |
614 | rats_no_pll->den_min = 1; | |
615 | rats_no_pll->den_max = 128; | |
616 | rats_no_pll->den_step = 1; | |
617 | ||
618 | return snd_pcm_hw_constraint_ratnums(substream->runtime, 0, | |
619 | SNDRV_PCM_HW_PARAM_RATE, | |
620 | constraints_no_pll); | |
621 | } | |
622 | ||
623 | static int pcm512x_dai_startup_slave(struct snd_pcm_substream *substream, | |
624 | struct snd_soc_dai *dai) | |
625 | { | |
5bdef14a KM |
626 | struct snd_soc_component *component = dai->component; |
627 | struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); | |
81249307 PR |
628 | struct device *dev = dai->dev; |
629 | struct regmap *regmap = pcm512x->regmap; | |
630 | ||
631 | if (IS_ERR(pcm512x->sclk)) { | |
632 | dev_info(dev, "No SCLK, using BCLK: %ld\n", | |
633 | PTR_ERR(pcm512x->sclk)); | |
634 | ||
635 | /* Disable reporting of missing SCLK as an error */ | |
636 | regmap_update_bits(regmap, PCM512x_ERROR_DETECT, | |
637 | PCM512x_IDCH, PCM512x_IDCH); | |
638 | ||
639 | /* Switch PLL input to BCLK */ | |
640 | regmap_update_bits(regmap, PCM512x_PLL_REF, | |
641 | PCM512x_SREF, PCM512x_SREF_BCK); | |
642 | } | |
643 | ||
644 | return snd_pcm_hw_constraint_list(substream->runtime, 0, | |
645 | SNDRV_PCM_HW_PARAM_RATE, | |
646 | &constraints_slave); | |
647 | } | |
648 | ||
649 | static int pcm512x_dai_startup(struct snd_pcm_substream *substream, | |
650 | struct snd_soc_dai *dai) | |
651 | { | |
5bdef14a KM |
652 | struct snd_soc_component *component = dai->component; |
653 | struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); | |
81249307 PR |
654 | |
655 | switch (pcm512x->fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
656 | case SND_SOC_DAIFMT_CBM_CFM: | |
d11c2978 | 657 | case SND_SOC_DAIFMT_CBM_CFS: |
81249307 PR |
658 | return pcm512x_dai_startup_master(substream, dai); |
659 | ||
660 | case SND_SOC_DAIFMT_CBS_CFS: | |
661 | return pcm512x_dai_startup_slave(substream, dai); | |
662 | ||
663 | default: | |
664 | return -EINVAL; | |
665 | } | |
666 | } | |
667 | ||
5bdef14a | 668 | static int pcm512x_set_bias_level(struct snd_soc_component *component, |
5a3af129 MB |
669 | enum snd_soc_bias_level level) |
670 | { | |
5bdef14a | 671 | struct pcm512x_priv *pcm512x = dev_get_drvdata(component->dev); |
5a3af129 MB |
672 | int ret; |
673 | ||
674 | switch (level) { | |
675 | case SND_SOC_BIAS_ON: | |
676 | case SND_SOC_BIAS_PREPARE: | |
677 | break; | |
678 | ||
679 | case SND_SOC_BIAS_STANDBY: | |
680 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER, | |
681 | PCM512x_RQST, 0); | |
682 | if (ret != 0) { | |
5bdef14a | 683 | dev_err(component->dev, "Failed to remove standby: %d\n", |
5a3af129 MB |
684 | ret); |
685 | return ret; | |
686 | } | |
687 | break; | |
688 | ||
689 | case SND_SOC_BIAS_OFF: | |
690 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER, | |
691 | PCM512x_RQST, PCM512x_RQST); | |
692 | if (ret != 0) { | |
5bdef14a | 693 | dev_err(component->dev, "Failed to request standby: %d\n", |
5a3af129 MB |
694 | ret); |
695 | return ret; | |
696 | } | |
697 | break; | |
698 | } | |
699 | ||
5a3af129 MB |
700 | return 0; |
701 | } | |
702 | ||
f086ba9d PR |
703 | static unsigned long pcm512x_find_sck(struct snd_soc_dai *dai, |
704 | unsigned long bclk_rate) | |
705 | { | |
706 | struct device *dev = dai->dev; | |
5bdef14a KM |
707 | struct snd_soc_component *component = dai->component; |
708 | struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); | |
f086ba9d PR |
709 | unsigned long sck_rate; |
710 | int pow2; | |
711 | ||
712 | /* 64 MHz <= pll_rate <= 100 MHz, VREF mode */ | |
713 | /* 16 MHz <= sck_rate <= 25 MHz, VREF mode */ | |
714 | ||
715 | /* select sck_rate as a multiple of bclk_rate but still with | |
716 | * as many factors of 2 as possible, as that makes it easier | |
717 | * to find a fast DAC rate | |
718 | */ | |
f29933c9 | 719 | pow2 = 1 << fls((pcm512x_pll_max(pcm512x) - 16000000) / bclk_rate); |
f086ba9d | 720 | for (; pow2; pow2 >>= 1) { |
f29933c9 PR |
721 | sck_rate = rounddown(pcm512x_pll_max(pcm512x), |
722 | bclk_rate * pow2); | |
f086ba9d PR |
723 | if (sck_rate >= 16000000) |
724 | break; | |
725 | } | |
726 | if (!pow2) { | |
727 | dev_err(dev, "Impossible to generate a suitable SCK\n"); | |
728 | return 0; | |
729 | } | |
730 | ||
731 | dev_dbg(dev, "sck_rate %lu\n", sck_rate); | |
732 | return sck_rate; | |
733 | } | |
734 | ||
735 | /* pll_rate = pllin_rate * R * J.D / P | |
736 | * 1 <= R <= 16 | |
737 | * 1 <= J <= 63 | |
738 | * 0 <= D <= 9999 | |
739 | * 1 <= P <= 15 | |
740 | * 64 MHz <= pll_rate <= 100 MHz | |
741 | * if D == 0 | |
742 | * 1 MHz <= pllin_rate / P <= 20 MHz | |
743 | * else if D > 0 | |
744 | * 6.667 MHz <= pllin_rate / P <= 20 MHz | |
745 | * 4 <= J <= 11 | |
746 | * R = 1 | |
747 | */ | |
748 | static int pcm512x_find_pll_coeff(struct snd_soc_dai *dai, | |
749 | unsigned long pllin_rate, | |
750 | unsigned long pll_rate) | |
751 | { | |
752 | struct device *dev = dai->dev; | |
5bdef14a KM |
753 | struct snd_soc_component *component = dai->component; |
754 | struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); | |
f086ba9d PR |
755 | unsigned long common; |
756 | int R, J, D, P; | |
757 | unsigned long K; /* 10000 * J.D */ | |
758 | unsigned long num; | |
759 | unsigned long den; | |
760 | ||
761 | common = gcd(pll_rate, pllin_rate); | |
762 | dev_dbg(dev, "pll %lu pllin %lu common %lu\n", | |
763 | pll_rate, pllin_rate, common); | |
764 | num = pll_rate / common; | |
765 | den = pllin_rate / common; | |
766 | ||
767 | /* pllin_rate / P (or here, den) cannot be greater than 20 MHz */ | |
768 | if (pllin_rate / den > 20000000 && num < 8) { | |
f073faa7 HM |
769 | num *= DIV_ROUND_UP(pllin_rate / den, 20000000); |
770 | den *= DIV_ROUND_UP(pllin_rate / den, 20000000); | |
f086ba9d PR |
771 | } |
772 | dev_dbg(dev, "num / den = %lu / %lu\n", num, den); | |
773 | ||
774 | P = den; | |
775 | if (den <= 15 && num <= 16 * 63 | |
776 | && 1000000 <= pllin_rate / P && pllin_rate / P <= 20000000) { | |
777 | /* Try the case with D = 0 */ | |
778 | D = 0; | |
779 | /* factor 'num' into J and R, such that R <= 16 and J <= 63 */ | |
780 | for (R = 16; R; R--) { | |
781 | if (num % R) | |
782 | continue; | |
783 | J = num / R; | |
784 | if (J == 0 || J > 63) | |
785 | continue; | |
786 | ||
787 | dev_dbg(dev, "R * J / P = %d * %d / %d\n", R, J, P); | |
788 | pcm512x->real_pll = pll_rate; | |
789 | goto done; | |
790 | } | |
791 | /* no luck */ | |
792 | } | |
793 | ||
794 | R = 1; | |
795 | ||
796 | if (num > 0xffffffffUL / 10000) | |
797 | goto fallback; | |
798 | ||
799 | /* Try to find an exact pll_rate using the D > 0 case */ | |
800 | common = gcd(10000 * num, den); | |
801 | num = 10000 * num / common; | |
802 | den /= common; | |
803 | dev_dbg(dev, "num %lu den %lu common %lu\n", num, den, common); | |
804 | ||
805 | for (P = den; P <= 15; P++) { | |
806 | if (pllin_rate / P < 6667000 || 200000000 < pllin_rate / P) | |
807 | continue; | |
808 | if (num * P % den) | |
809 | continue; | |
810 | K = num * P / den; | |
811 | /* J == 12 is ok if D == 0 */ | |
812 | if (K < 40000 || K > 120000) | |
813 | continue; | |
814 | ||
815 | J = K / 10000; | |
816 | D = K % 10000; | |
817 | dev_dbg(dev, "J.D / P = %d.%04d / %d\n", J, D, P); | |
818 | pcm512x->real_pll = pll_rate; | |
819 | goto done; | |
820 | } | |
821 | ||
822 | /* Fall back to an approximate pll_rate */ | |
823 | ||
824 | fallback: | |
825 | /* find smallest possible P */ | |
826 | P = DIV_ROUND_UP(pllin_rate, 20000000); | |
827 | if (!P) | |
828 | P = 1; | |
829 | else if (P > 15) { | |
830 | dev_err(dev, "Need a slower clock as pll-input\n"); | |
831 | return -EINVAL; | |
832 | } | |
833 | if (pllin_rate / P < 6667000) { | |
834 | dev_err(dev, "Need a faster clock as pll-input\n"); | |
835 | return -EINVAL; | |
836 | } | |
837 | K = DIV_ROUND_CLOSEST_ULL(10000ULL * pll_rate * P, pllin_rate); | |
838 | if (K < 40000) | |
839 | K = 40000; | |
840 | /* J == 12 is ok if D == 0 */ | |
841 | if (K > 120000) | |
842 | K = 120000; | |
843 | J = K / 10000; | |
844 | D = K % 10000; | |
845 | dev_dbg(dev, "J.D / P ~ %d.%04d / %d\n", J, D, P); | |
846 | pcm512x->real_pll = DIV_ROUND_DOWN_ULL((u64)K * pllin_rate, 10000 * P); | |
847 | ||
848 | done: | |
849 | pcm512x->pll_r = R; | |
850 | pcm512x->pll_j = J; | |
851 | pcm512x->pll_d = D; | |
852 | pcm512x->pll_p = P; | |
853 | return 0; | |
854 | } | |
855 | ||
7c4e1119 PR |
856 | static unsigned long pcm512x_pllin_dac_rate(struct snd_soc_dai *dai, |
857 | unsigned long osr_rate, | |
858 | unsigned long pllin_rate) | |
859 | { | |
5bdef14a KM |
860 | struct snd_soc_component *component = dai->component; |
861 | struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); | |
7c4e1119 PR |
862 | unsigned long dac_rate; |
863 | ||
864 | if (!pcm512x->pll_out) | |
865 | return 0; /* no PLL to bypass, force SCK as DAC input */ | |
866 | ||
867 | if (pllin_rate % osr_rate) | |
868 | return 0; /* futile, quit early */ | |
869 | ||
870 | /* run DAC no faster than 6144000 Hz */ | |
f29933c9 | 871 | for (dac_rate = rounddown(pcm512x_dac_max(pcm512x, 6144000), osr_rate); |
7c4e1119 PR |
872 | dac_rate; |
873 | dac_rate -= osr_rate) { | |
874 | ||
875 | if (pllin_rate / dac_rate > 128) | |
876 | return 0; /* DAC divider would be too big */ | |
877 | ||
878 | if (!(pllin_rate % dac_rate)) | |
879 | return dac_rate; | |
880 | ||
881 | dac_rate -= osr_rate; | |
882 | } | |
883 | ||
884 | return 0; | |
885 | } | |
886 | ||
81249307 PR |
887 | static int pcm512x_set_dividers(struct snd_soc_dai *dai, |
888 | struct snd_pcm_hw_params *params) | |
889 | { | |
890 | struct device *dev = dai->dev; | |
5bdef14a KM |
891 | struct snd_soc_component *component = dai->component; |
892 | struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); | |
f086ba9d PR |
893 | unsigned long pllin_rate = 0; |
894 | unsigned long pll_rate; | |
81249307 PR |
895 | unsigned long sck_rate; |
896 | unsigned long mck_rate; | |
897 | unsigned long bclk_rate; | |
898 | unsigned long sample_rate; | |
899 | unsigned long osr_rate; | |
7c4e1119 | 900 | unsigned long dacsrc_rate; |
81249307 PR |
901 | int bclk_div; |
902 | int lrclk_div; | |
903 | int dsp_div; | |
904 | int dac_div; | |
905 | unsigned long dac_rate; | |
906 | int ncp_div; | |
907 | int osr_div; | |
81249307 PR |
908 | int ret; |
909 | int idac; | |
910 | int fssp; | |
7c4e1119 | 911 | int gpio; |
81249307 | 912 | |
ccc8d6c7 DP |
913 | if (pcm512x->bclk_ratio > 0) { |
914 | lrclk_div = pcm512x->bclk_ratio; | |
915 | } else { | |
916 | lrclk_div = snd_soc_params_to_frame_size(params); | |
917 | ||
918 | if (lrclk_div == 0) { | |
919 | dev_err(dev, "No LRCLK?\n"); | |
920 | return -EINVAL; | |
921 | } | |
81249307 PR |
922 | } |
923 | ||
f086ba9d PR |
924 | if (!pcm512x->pll_out) { |
925 | sck_rate = clk_get_rate(pcm512x->sclk); | |
51b033c2 DP |
926 | bclk_rate = params_rate(params) * lrclk_div; |
927 | bclk_div = DIV_ROUND_CLOSEST(sck_rate, bclk_rate); | |
f086ba9d PR |
928 | |
929 | mck_rate = sck_rate; | |
930 | } else { | |
931 | ret = snd_soc_params_to_bclk(params); | |
932 | if (ret < 0) { | |
933 | dev_err(dev, "Failed to find suitable BCLK: %d\n", ret); | |
934 | return ret; | |
935 | } | |
936 | if (ret == 0) { | |
937 | dev_err(dev, "No BCLK?\n"); | |
938 | return -EINVAL; | |
939 | } | |
940 | bclk_rate = ret; | |
941 | ||
942 | pllin_rate = clk_get_rate(pcm512x->sclk); | |
943 | ||
944 | sck_rate = pcm512x_find_sck(dai, bclk_rate); | |
945 | if (!sck_rate) | |
946 | return -EINVAL; | |
947 | pll_rate = 4 * sck_rate; | |
948 | ||
949 | ret = pcm512x_find_pll_coeff(dai, pllin_rate, pll_rate); | |
950 | if (ret != 0) | |
951 | return ret; | |
952 | ||
953 | ret = regmap_write(pcm512x->regmap, | |
954 | PCM512x_PLL_COEFF_0, pcm512x->pll_p - 1); | |
955 | if (ret != 0) { | |
956 | dev_err(dev, "Failed to write PLL P: %d\n", ret); | |
957 | return ret; | |
958 | } | |
959 | ||
960 | ret = regmap_write(pcm512x->regmap, | |
961 | PCM512x_PLL_COEFF_1, pcm512x->pll_j); | |
962 | if (ret != 0) { | |
963 | dev_err(dev, "Failed to write PLL J: %d\n", ret); | |
964 | return ret; | |
965 | } | |
966 | ||
967 | ret = regmap_write(pcm512x->regmap, | |
968 | PCM512x_PLL_COEFF_2, pcm512x->pll_d >> 8); | |
969 | if (ret != 0) { | |
970 | dev_err(dev, "Failed to write PLL D msb: %d\n", ret); | |
971 | return ret; | |
972 | } | |
973 | ||
974 | ret = regmap_write(pcm512x->regmap, | |
975 | PCM512x_PLL_COEFF_3, pcm512x->pll_d & 0xff); | |
976 | if (ret != 0) { | |
977 | dev_err(dev, "Failed to write PLL D lsb: %d\n", ret); | |
978 | return ret; | |
979 | } | |
980 | ||
981 | ret = regmap_write(pcm512x->regmap, | |
982 | PCM512x_PLL_COEFF_4, pcm512x->pll_r - 1); | |
983 | if (ret != 0) { | |
984 | dev_err(dev, "Failed to write PLL R: %d\n", ret); | |
985 | return ret; | |
986 | } | |
987 | ||
988 | mck_rate = pcm512x->real_pll; | |
81249307 | 989 | |
f086ba9d PR |
990 | bclk_div = DIV_ROUND_CLOSEST(sck_rate, bclk_rate); |
991 | } | |
81249307 PR |
992 | |
993 | if (bclk_div > 128) { | |
994 | dev_err(dev, "Failed to find BCLK divider\n"); | |
995 | return -EINVAL; | |
996 | } | |
997 | ||
998 | /* the actual rate */ | |
999 | sample_rate = sck_rate / bclk_div / lrclk_div; | |
1000 | osr_rate = 16 * sample_rate; | |
1001 | ||
1002 | /* run DSP no faster than 50 MHz */ | |
f29933c9 | 1003 | dsp_div = mck_rate > pcm512x_dsp_max(pcm512x) ? 2 : 1; |
81249307 | 1004 | |
7c4e1119 PR |
1005 | dac_rate = pcm512x_pllin_dac_rate(dai, osr_rate, pllin_rate); |
1006 | if (dac_rate) { | |
1007 | /* the desired clock rate is "compatible" with the pll input | |
1008 | * clock, so use that clock as dac input instead of the pll | |
1009 | * output clock since the pll will introduce jitter and thus | |
1010 | * noise. | |
1011 | */ | |
1012 | dev_dbg(dev, "using pll input as dac input\n"); | |
1013 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_DAC_REF, | |
1014 | PCM512x_SDAC, PCM512x_SDAC_GPIO); | |
1015 | if (ret != 0) { | |
5bdef14a | 1016 | dev_err(component->dev, |
7c4e1119 PR |
1017 | "Failed to set gpio as dacref: %d\n", ret); |
1018 | return ret; | |
1019 | } | |
81249307 | 1020 | |
7c4e1119 PR |
1021 | gpio = PCM512x_GREF_GPIO1 + pcm512x->pll_in - 1; |
1022 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_DACIN, | |
1023 | PCM512x_GREF, gpio); | |
1024 | if (ret != 0) { | |
5bdef14a | 1025 | dev_err(component->dev, |
7c4e1119 PR |
1026 | "Failed to set gpio %d as dacin: %d\n", |
1027 | pcm512x->pll_in, ret); | |
1028 | return ret; | |
1029 | } | |
1030 | ||
1031 | dacsrc_rate = pllin_rate; | |
1032 | } else { | |
1033 | /* run DAC no faster than 6144000 Hz */ | |
f29933c9 PR |
1034 | unsigned long dac_mul = pcm512x_dac_max(pcm512x, 6144000) |
1035 | / osr_rate; | |
7c4e1119 PR |
1036 | unsigned long sck_mul = sck_rate / osr_rate; |
1037 | ||
1038 | for (; dac_mul; dac_mul--) { | |
1039 | if (!(sck_mul % dac_mul)) | |
1040 | break; | |
1041 | } | |
1042 | if (!dac_mul) { | |
1043 | dev_err(dev, "Failed to find DAC rate\n"); | |
1044 | return -EINVAL; | |
1045 | } | |
81249307 | 1046 | |
7c4e1119 PR |
1047 | dac_rate = dac_mul * osr_rate; |
1048 | dev_dbg(dev, "dac_rate %lu sample_rate %lu\n", | |
1049 | dac_rate, sample_rate); | |
1050 | ||
1051 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_DAC_REF, | |
1052 | PCM512x_SDAC, PCM512x_SDAC_SCK); | |
1053 | if (ret != 0) { | |
5bdef14a | 1054 | dev_err(component->dev, |
7c4e1119 PR |
1055 | "Failed to set sck as dacref: %d\n", ret); |
1056 | return ret; | |
1057 | } | |
1058 | ||
1059 | dacsrc_rate = sck_rate; | |
1060 | } | |
1061 | ||
5890bd52 PR |
1062 | osr_div = DIV_ROUND_CLOSEST(dac_rate, osr_rate); |
1063 | if (osr_div > 128) { | |
1064 | dev_err(dev, "Failed to find OSR divider\n"); | |
1065 | return -EINVAL; | |
1066 | } | |
1067 | ||
7c4e1119 | 1068 | dac_div = DIV_ROUND_CLOSEST(dacsrc_rate, dac_rate); |
81249307 PR |
1069 | if (dac_div > 128) { |
1070 | dev_err(dev, "Failed to find DAC divider\n"); | |
1071 | return -EINVAL; | |
1072 | } | |
5890bd52 | 1073 | dac_rate = dacsrc_rate / dac_div; |
81249307 | 1074 | |
f29933c9 PR |
1075 | ncp_div = DIV_ROUND_CLOSEST(dac_rate, |
1076 | pcm512x_ncp_target(pcm512x, dac_rate)); | |
5890bd52 | 1077 | if (ncp_div > 128 || dac_rate / ncp_div > 2048000) { |
81249307 | 1078 | /* run NCP no faster than 2048000 Hz, but why? */ |
5890bd52 | 1079 | ncp_div = DIV_ROUND_UP(dac_rate, 2048000); |
81249307 PR |
1080 | if (ncp_div > 128) { |
1081 | dev_err(dev, "Failed to find NCP divider\n"); | |
1082 | return -EINVAL; | |
1083 | } | |
1084 | } | |
1085 | ||
81249307 PR |
1086 | idac = mck_rate / (dsp_div * sample_rate); |
1087 | ||
1088 | ret = regmap_write(pcm512x->regmap, PCM512x_DSP_CLKDIV, dsp_div - 1); | |
1089 | if (ret != 0) { | |
1090 | dev_err(dev, "Failed to write DSP divider: %d\n", ret); | |
1091 | return ret; | |
1092 | } | |
1093 | ||
1094 | ret = regmap_write(pcm512x->regmap, PCM512x_DAC_CLKDIV, dac_div - 1); | |
1095 | if (ret != 0) { | |
1096 | dev_err(dev, "Failed to write DAC divider: %d\n", ret); | |
1097 | return ret; | |
1098 | } | |
1099 | ||
1100 | ret = regmap_write(pcm512x->regmap, PCM512x_NCP_CLKDIV, ncp_div - 1); | |
1101 | if (ret != 0) { | |
1102 | dev_err(dev, "Failed to write NCP divider: %d\n", ret); | |
1103 | return ret; | |
1104 | } | |
1105 | ||
1106 | ret = regmap_write(pcm512x->regmap, PCM512x_OSR_CLKDIV, osr_div - 1); | |
1107 | if (ret != 0) { | |
1108 | dev_err(dev, "Failed to write OSR divider: %d\n", ret); | |
1109 | return ret; | |
1110 | } | |
1111 | ||
1112 | ret = regmap_write(pcm512x->regmap, | |
1113 | PCM512x_MASTER_CLKDIV_1, bclk_div - 1); | |
1114 | if (ret != 0) { | |
1115 | dev_err(dev, "Failed to write BCLK divider: %d\n", ret); | |
1116 | return ret; | |
1117 | } | |
1118 | ||
1119 | ret = regmap_write(pcm512x->regmap, | |
1120 | PCM512x_MASTER_CLKDIV_2, lrclk_div - 1); | |
1121 | if (ret != 0) { | |
1122 | dev_err(dev, "Failed to write LRCLK divider: %d\n", ret); | |
1123 | return ret; | |
1124 | } | |
1125 | ||
1126 | ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_1, idac >> 8); | |
1127 | if (ret != 0) { | |
1128 | dev_err(dev, "Failed to write IDAC msb divider: %d\n", ret); | |
1129 | return ret; | |
1130 | } | |
1131 | ||
1132 | ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_2, idac & 0xff); | |
1133 | if (ret != 0) { | |
1134 | dev_err(dev, "Failed to write IDAC lsb divider: %d\n", ret); | |
1135 | return ret; | |
1136 | } | |
1137 | ||
f29933c9 | 1138 | if (sample_rate <= pcm512x_dac_max(pcm512x, 48000)) |
81249307 | 1139 | fssp = PCM512x_FSSP_48KHZ; |
f29933c9 | 1140 | else if (sample_rate <= pcm512x_dac_max(pcm512x, 96000)) |
81249307 | 1141 | fssp = PCM512x_FSSP_96KHZ; |
f29933c9 | 1142 | else if (sample_rate <= pcm512x_dac_max(pcm512x, 192000)) |
81249307 PR |
1143 | fssp = PCM512x_FSSP_192KHZ; |
1144 | else | |
1145 | fssp = PCM512x_FSSP_384KHZ; | |
1146 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_FS_SPEED_MODE, | |
1147 | PCM512x_FSSP, fssp); | |
1148 | if (ret != 0) { | |
5bdef14a | 1149 | dev_err(component->dev, "Failed to set fs speed: %d\n", ret); |
81249307 PR |
1150 | return ret; |
1151 | } | |
1152 | ||
5bdef14a KM |
1153 | dev_dbg(component->dev, "DSP divider %d\n", dsp_div); |
1154 | dev_dbg(component->dev, "DAC divider %d\n", dac_div); | |
1155 | dev_dbg(component->dev, "NCP divider %d\n", ncp_div); | |
1156 | dev_dbg(component->dev, "OSR divider %d\n", osr_div); | |
1157 | dev_dbg(component->dev, "BCK divider %d\n", bclk_div); | |
1158 | dev_dbg(component->dev, "LRCK divider %d\n", lrclk_div); | |
1159 | dev_dbg(component->dev, "IDAC %d\n", idac); | |
1160 | dev_dbg(component->dev, "1<<FSSP %d\n", 1 << fssp); | |
81249307 PR |
1161 | |
1162 | return 0; | |
1163 | } | |
1164 | ||
1165 | static int pcm512x_hw_params(struct snd_pcm_substream *substream, | |
1166 | struct snd_pcm_hw_params *params, | |
1167 | struct snd_soc_dai *dai) | |
1168 | { | |
5bdef14a KM |
1169 | struct snd_soc_component *component = dai->component; |
1170 | struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); | |
81249307 | 1171 | int alen; |
f086ba9d | 1172 | int gpio; |
81249307 PR |
1173 | int ret; |
1174 | ||
5bdef14a | 1175 | dev_dbg(component->dev, "hw_params %u Hz, %u channels\n", |
81249307 PR |
1176 | params_rate(params), |
1177 | params_channels(params)); | |
1178 | ||
0a3dcb50 | 1179 | switch (params_width(params)) { |
81249307 PR |
1180 | case 16: |
1181 | alen = PCM512x_ALEN_16; | |
1182 | break; | |
1183 | case 20: | |
1184 | alen = PCM512x_ALEN_20; | |
1185 | break; | |
1186 | case 24: | |
1187 | alen = PCM512x_ALEN_24; | |
1188 | break; | |
1189 | case 32: | |
1190 | alen = PCM512x_ALEN_32; | |
1191 | break; | |
1192 | default: | |
5bdef14a | 1193 | dev_err(component->dev, "Bad frame size: %d\n", |
0a3dcb50 | 1194 | params_width(params)); |
81249307 PR |
1195 | return -EINVAL; |
1196 | } | |
1197 | ||
6feaaa7c KM |
1198 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_I2S_1, |
1199 | PCM512x_ALEN, alen); | |
1200 | if (ret != 0) { | |
1201 | dev_err(component->dev, "Failed to set frame size: %d\n", ret); | |
1202 | return ret; | |
1203 | } | |
1204 | ||
26b97d95 KM |
1205 | if ((pcm512x->fmt & SND_SOC_DAIFMT_MASTER_MASK) == |
1206 | SND_SOC_DAIFMT_CBS_CFS) { | |
81249307 PR |
1207 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT, |
1208 | PCM512x_DCAS, 0); | |
1209 | if (ret != 0) { | |
5bdef14a | 1210 | dev_err(component->dev, |
81249307 PR |
1211 | "Failed to enable clock divider autoset: %d\n", |
1212 | ret); | |
1213 | return ret; | |
1214 | } | |
798714b6 | 1215 | goto skip_pll; |
81249307 PR |
1216 | } |
1217 | ||
f086ba9d PR |
1218 | if (pcm512x->pll_out) { |
1219 | ret = regmap_write(pcm512x->regmap, PCM512x_FLEX_A, 0x11); | |
1220 | if (ret != 0) { | |
5bdef14a | 1221 | dev_err(component->dev, "Failed to set FLEX_A: %d\n", ret); |
f086ba9d PR |
1222 | return ret; |
1223 | } | |
81249307 | 1224 | |
f086ba9d PR |
1225 | ret = regmap_write(pcm512x->regmap, PCM512x_FLEX_B, 0xff); |
1226 | if (ret != 0) { | |
5bdef14a | 1227 | dev_err(component->dev, "Failed to set FLEX_B: %d\n", ret); |
f086ba9d PR |
1228 | return ret; |
1229 | } | |
1230 | ||
1231 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT, | |
1232 | PCM512x_IDFS | PCM512x_IDBK | |
1233 | | PCM512x_IDSK | PCM512x_IDCH | |
1234 | | PCM512x_IDCM | PCM512x_DCAS | |
1235 | | PCM512x_IPLK, | |
1236 | PCM512x_IDFS | PCM512x_IDBK | |
1237 | | PCM512x_IDSK | PCM512x_IDCH | |
1238 | | PCM512x_DCAS); | |
1239 | if (ret != 0) { | |
5bdef14a | 1240 | dev_err(component->dev, |
f086ba9d PR |
1241 | "Failed to ignore auto-clock failures: %d\n", |
1242 | ret); | |
1243 | return ret; | |
1244 | } | |
1245 | } else { | |
1246 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT, | |
1247 | PCM512x_IDFS | PCM512x_IDBK | |
1248 | | PCM512x_IDSK | PCM512x_IDCH | |
1249 | | PCM512x_IDCM | PCM512x_DCAS | |
1250 | | PCM512x_IPLK, | |
1251 | PCM512x_IDFS | PCM512x_IDBK | |
1252 | | PCM512x_IDSK | PCM512x_IDCH | |
1253 | | PCM512x_DCAS | PCM512x_IPLK); | |
1254 | if (ret != 0) { | |
5bdef14a | 1255 | dev_err(component->dev, |
f086ba9d PR |
1256 | "Failed to ignore auto-clock failures: %d\n", |
1257 | ret); | |
1258 | return ret; | |
1259 | } | |
1260 | ||
1261 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_EN, | |
1262 | PCM512x_PLLE, 0); | |
1263 | if (ret != 0) { | |
5bdef14a | 1264 | dev_err(component->dev, "Failed to disable pll: %d\n", ret); |
f086ba9d PR |
1265 | return ret; |
1266 | } | |
81249307 PR |
1267 | } |
1268 | ||
1269 | ret = pcm512x_set_dividers(dai, params); | |
1270 | if (ret != 0) | |
1271 | return ret; | |
1272 | ||
f086ba9d PR |
1273 | if (pcm512x->pll_out) { |
1274 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_REF, | |
1275 | PCM512x_SREF, PCM512x_SREF_GPIO); | |
1276 | if (ret != 0) { | |
5bdef14a | 1277 | dev_err(component->dev, |
f086ba9d PR |
1278 | "Failed to set gpio as pllref: %d\n", ret); |
1279 | return ret; | |
1280 | } | |
1281 | ||
1282 | gpio = PCM512x_GREF_GPIO1 + pcm512x->pll_in - 1; | |
1283 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_PLLIN, | |
1284 | PCM512x_GREF, gpio); | |
1285 | if (ret != 0) { | |
5bdef14a | 1286 | dev_err(component->dev, |
f086ba9d PR |
1287 | "Failed to set gpio %d as pllin: %d\n", |
1288 | pcm512x->pll_in, ret); | |
1289 | return ret; | |
1290 | } | |
1291 | ||
1292 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_EN, | |
1293 | PCM512x_PLLE, PCM512x_PLLE); | |
1294 | if (ret != 0) { | |
5bdef14a | 1295 | dev_err(component->dev, "Failed to enable pll: %d\n", ret); |
f086ba9d PR |
1296 | return ret; |
1297 | } | |
81249307 | 1298 | |
f086ba9d PR |
1299 | gpio = PCM512x_G1OE << (pcm512x->pll_out - 1); |
1300 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_EN, | |
1301 | gpio, gpio); | |
1302 | if (ret != 0) { | |
5bdef14a | 1303 | dev_err(component->dev, "Failed to enable gpio %d: %d\n", |
f086ba9d PR |
1304 | pcm512x->pll_out, ret); |
1305 | return ret; | |
1306 | } | |
1307 | ||
1308 | gpio = PCM512x_GPIO_OUTPUT_1 + pcm512x->pll_out - 1; | |
1309 | ret = regmap_update_bits(pcm512x->regmap, gpio, | |
1310 | PCM512x_GxSL, PCM512x_GxSL_PLLCK); | |
1311 | if (ret != 0) { | |
5bdef14a | 1312 | dev_err(component->dev, "Failed to output pll on %d: %d\n", |
f086ba9d PR |
1313 | ret, pcm512x->pll_out); |
1314 | return ret; | |
1315 | } | |
f086ba9d PR |
1316 | } |
1317 | ||
81249307 PR |
1318 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_SYNCHRONIZE, |
1319 | PCM512x_RQSY, PCM512x_RQSY_HALT); | |
1320 | if (ret != 0) { | |
5bdef14a | 1321 | dev_err(component->dev, "Failed to halt clocks: %d\n", ret); |
81249307 PR |
1322 | return ret; |
1323 | } | |
1324 | ||
1325 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_SYNCHRONIZE, | |
1326 | PCM512x_RQSY, PCM512x_RQSY_RESUME); | |
1327 | if (ret != 0) { | |
5bdef14a | 1328 | dev_err(component->dev, "Failed to resume clocks: %d\n", ret); |
81249307 PR |
1329 | return ret; |
1330 | } | |
1331 | ||
798714b6 | 1332 | skip_pll: |
26b97d95 KM |
1333 | return 0; |
1334 | } | |
1335 | ||
1336 | static int pcm512x_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) | |
1337 | { | |
1338 | struct snd_soc_component *component = dai->component; | |
1339 | struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); | |
25d27c4f KM |
1340 | int afmt; |
1341 | int offset = 0; | |
26b97d95 KM |
1342 | int clock_output; |
1343 | int master_mode; | |
1344 | int ret; | |
1345 | ||
1346 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1347 | case SND_SOC_DAIFMT_CBS_CFS: | |
1348 | clock_output = 0; | |
1349 | master_mode = 0; | |
1350 | break; | |
1351 | case SND_SOC_DAIFMT_CBM_CFM: | |
1352 | clock_output = PCM512x_BCKO | PCM512x_LRKO; | |
1353 | master_mode = PCM512x_RLRK | PCM512x_RBCK; | |
1354 | break; | |
1355 | case SND_SOC_DAIFMT_CBM_CFS: | |
1356 | clock_output = PCM512x_BCKO; | |
1357 | master_mode = PCM512x_RBCK; | |
1358 | break; | |
1359 | default: | |
1360 | return -EINVAL; | |
1361 | } | |
1362 | ||
798714b6 KM |
1363 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_BCLK_LRCLK_CFG, |
1364 | PCM512x_BCKP | PCM512x_BCKO | PCM512x_LRKO, | |
1365 | clock_output); | |
1366 | if (ret != 0) { | |
1367 | dev_err(component->dev, "Failed to enable clock output: %d\n", ret); | |
1368 | return ret; | |
1369 | } | |
1370 | ||
1371 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_MASTER_MODE, | |
1372 | PCM512x_RLRK | PCM512x_RBCK, | |
1373 | master_mode); | |
1374 | if (ret != 0) { | |
1375 | dev_err(component->dev, "Failed to enable master mode: %d\n", ret); | |
1376 | return ret; | |
1377 | } | |
1378 | ||
25d27c4f KM |
1379 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
1380 | case SND_SOC_DAIFMT_I2S: | |
1381 | afmt = PCM512x_AFMT_I2S; | |
1382 | break; | |
1383 | case SND_SOC_DAIFMT_RIGHT_J: | |
1384 | afmt = PCM512x_AFMT_RTJ; | |
1385 | break; | |
1386 | case SND_SOC_DAIFMT_LEFT_J: | |
1387 | afmt = PCM512x_AFMT_LTJ; | |
1388 | break; | |
1389 | case SND_SOC_DAIFMT_DSP_A: | |
1390 | offset = 1; | |
1391 | fallthrough; | |
1392 | case SND_SOC_DAIFMT_DSP_B: | |
1393 | afmt = PCM512x_AFMT_DSP; | |
1394 | break; | |
1395 | default: | |
1396 | dev_err(component->dev, "unsupported DAI format: 0x%x\n", | |
1397 | pcm512x->fmt); | |
1398 | return -EINVAL; | |
1399 | } | |
1400 | ||
1401 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_I2S_1, | |
1402 | PCM512x_AFMT, afmt); | |
1403 | if (ret != 0) { | |
1404 | dev_err(component->dev, "Failed to set data format: %d\n", ret); | |
1405 | return ret; | |
1406 | } | |
1407 | ||
1408 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_I2S_2, | |
1409 | 0xFF, offset); | |
1410 | if (ret != 0) { | |
1411 | dev_err(component->dev, "Failed to set data offset: %d\n", ret); | |
1412 | return ret; | |
1413 | } | |
1414 | ||
81249307 PR |
1415 | pcm512x->fmt = fmt; |
1416 | ||
1417 | return 0; | |
1418 | } | |
1419 | ||
ccc8d6c7 DP |
1420 | static int pcm512x_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) |
1421 | { | |
1422 | struct snd_soc_component *component = dai->component; | |
1423 | struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); | |
1424 | ||
1425 | if (ratio > 256) | |
1426 | return -EINVAL; | |
1427 | ||
1428 | pcm512x->bclk_ratio = ratio; | |
1429 | ||
1430 | return 0; | |
1431 | } | |
1432 | ||
1eb2c43d | 1433 | static int pcm512x_mute(struct snd_soc_dai *dai, int mute, int direction) |
3500f1c5 DP |
1434 | { |
1435 | struct snd_soc_component *component = dai->component; | |
1436 | struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component); | |
1437 | int ret; | |
1438 | unsigned int mute_det; | |
1439 | ||
1440 | mutex_lock(&pcm512x->mutex); | |
1441 | ||
1442 | if (mute) { | |
1443 | pcm512x->mute |= 0x1; | |
1444 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_MUTE, | |
1445 | PCM512x_RQML | PCM512x_RQMR, | |
1446 | PCM512x_RQML | PCM512x_RQMR); | |
1447 | if (ret != 0) { | |
1448 | dev_err(component->dev, | |
1449 | "Failed to set digital mute: %d\n", ret); | |
28b698b7 | 1450 | goto unlock; |
3500f1c5 DP |
1451 | } |
1452 | ||
1453 | regmap_read_poll_timeout(pcm512x->regmap, | |
1454 | PCM512x_ANALOG_MUTE_DET, | |
1455 | mute_det, (mute_det & 0x3) == 0, | |
1456 | 200, 10000); | |
3500f1c5 DP |
1457 | } else { |
1458 | pcm512x->mute &= ~0x1; | |
1459 | ret = pcm512x_update_mute(pcm512x); | |
1460 | if (ret != 0) { | |
1461 | dev_err(component->dev, | |
1462 | "Failed to update digital mute: %d\n", ret); | |
28b698b7 | 1463 | goto unlock; |
3500f1c5 DP |
1464 | } |
1465 | ||
1466 | regmap_read_poll_timeout(pcm512x->regmap, | |
1467 | PCM512x_ANALOG_MUTE_DET, | |
1468 | mute_det, | |
1469 | (mute_det & 0x3) | |
1470 | == ((~pcm512x->mute >> 1) & 0x3), | |
1471 | 200, 10000); | |
1472 | } | |
1473 | ||
28b698b7 | 1474 | unlock: |
3500f1c5 DP |
1475 | mutex_unlock(&pcm512x->mutex); |
1476 | ||
28b698b7 | 1477 | return ret; |
3500f1c5 DP |
1478 | } |
1479 | ||
81249307 PR |
1480 | static const struct snd_soc_dai_ops pcm512x_dai_ops = { |
1481 | .startup = pcm512x_dai_startup, | |
1482 | .hw_params = pcm512x_hw_params, | |
1483 | .set_fmt = pcm512x_set_fmt, | |
1eb2c43d | 1484 | .mute_stream = pcm512x_mute, |
ccc8d6c7 | 1485 | .set_bclk_ratio = pcm512x_set_bclk_ratio, |
1eb2c43d | 1486 | .no_capture_mute = 1, |
81249307 PR |
1487 | }; |
1488 | ||
5a3af129 MB |
1489 | static struct snd_soc_dai_driver pcm512x_dai = { |
1490 | .name = "pcm512x-hifi", | |
1491 | .playback = { | |
1492 | .stream_name = "Playback", | |
1493 | .channels_min = 2, | |
1494 | .channels_max = 2, | |
81249307 PR |
1495 | .rates = SNDRV_PCM_RATE_CONTINUOUS, |
1496 | .rate_min = 8000, | |
1497 | .rate_max = 384000, | |
5a3af129 MB |
1498 | .formats = SNDRV_PCM_FMTBIT_S16_LE | |
1499 | SNDRV_PCM_FMTBIT_S24_LE | | |
1500 | SNDRV_PCM_FMTBIT_S32_LE | |
1501 | }, | |
81249307 | 1502 | .ops = &pcm512x_dai_ops, |
5a3af129 MB |
1503 | }; |
1504 | ||
5bdef14a KM |
1505 | static const struct snd_soc_component_driver pcm512x_component_driver = { |
1506 | .set_bias_level = pcm512x_set_bias_level, | |
1507 | .controls = pcm512x_controls, | |
1508 | .num_controls = ARRAY_SIZE(pcm512x_controls), | |
1509 | .dapm_widgets = pcm512x_dapm_widgets, | |
1510 | .num_dapm_widgets = ARRAY_SIZE(pcm512x_dapm_widgets), | |
1511 | .dapm_routes = pcm512x_dapm_routes, | |
1512 | .num_dapm_routes = ARRAY_SIZE(pcm512x_dapm_routes), | |
1513 | .use_pmdown_time = 1, | |
1514 | .endianness = 1, | |
1515 | .non_legacy_dai_naming = 1, | |
5a3af129 MB |
1516 | }; |
1517 | ||
806d6466 MB |
1518 | static const struct regmap_range_cfg pcm512x_range = { |
1519 | .name = "Pages", .range_min = PCM512x_VIRT_BASE, | |
1520 | .range_max = PCM512x_MAX_REGISTER, | |
1521 | .selector_reg = PCM512x_PAGE, | |
1522 | .selector_mask = 0xff, | |
1523 | .window_start = 0, .window_len = 0x100, | |
1524 | }; | |
1525 | ||
22066226 | 1526 | const struct regmap_config pcm512x_regmap = { |
5a3af129 MB |
1527 | .reg_bits = 8, |
1528 | .val_bits = 8, | |
1529 | ||
1530 | .readable_reg = pcm512x_readable, | |
1531 | .volatile_reg = pcm512x_volatile, | |
1532 | ||
806d6466 MB |
1533 | .ranges = &pcm512x_range, |
1534 | .num_ranges = 1, | |
1535 | ||
5a3af129 MB |
1536 | .max_register = PCM512x_MAX_REGISTER, |
1537 | .reg_defaults = pcm512x_reg_defaults, | |
1538 | .num_reg_defaults = ARRAY_SIZE(pcm512x_reg_defaults), | |
1539 | .cache_type = REGCACHE_RBTREE, | |
1540 | }; | |
22066226 | 1541 | EXPORT_SYMBOL_GPL(pcm512x_regmap); |
5a3af129 | 1542 | |
22066226 | 1543 | int pcm512x_probe(struct device *dev, struct regmap *regmap) |
5a3af129 MB |
1544 | { |
1545 | struct pcm512x_priv *pcm512x; | |
1546 | int i, ret; | |
1547 | ||
1548 | pcm512x = devm_kzalloc(dev, sizeof(struct pcm512x_priv), GFP_KERNEL); | |
1549 | if (!pcm512x) | |
1550 | return -ENOMEM; | |
1551 | ||
3500f1c5 DP |
1552 | mutex_init(&pcm512x->mutex); |
1553 | ||
5a3af129 MB |
1554 | dev_set_drvdata(dev, pcm512x); |
1555 | pcm512x->regmap = regmap; | |
1556 | ||
1557 | for (i = 0; i < ARRAY_SIZE(pcm512x->supplies); i++) | |
1558 | pcm512x->supplies[i].supply = pcm512x_supply_names[i]; | |
1559 | ||
1560 | ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pcm512x->supplies), | |
1561 | pcm512x->supplies); | |
1562 | if (ret != 0) { | |
1563 | dev_err(dev, "Failed to get supplies: %d\n", ret); | |
1564 | return ret; | |
1565 | } | |
1566 | ||
1567 | pcm512x->supply_nb[0].notifier_call = pcm512x_regulator_event_0; | |
1568 | pcm512x->supply_nb[1].notifier_call = pcm512x_regulator_event_1; | |
1569 | pcm512x->supply_nb[2].notifier_call = pcm512x_regulator_event_2; | |
1570 | ||
1571 | for (i = 0; i < ARRAY_SIZE(pcm512x->supplies); i++) { | |
0bb423f2 GL |
1572 | ret = devm_regulator_register_notifier( |
1573 | pcm512x->supplies[i].consumer, | |
1574 | &pcm512x->supply_nb[i]); | |
5a3af129 MB |
1575 | if (ret != 0) { |
1576 | dev_err(dev, | |
1577 | "Failed to register regulator notifier: %d\n", | |
1578 | ret); | |
1579 | } | |
1580 | } | |
1581 | ||
1582 | ret = regulator_bulk_enable(ARRAY_SIZE(pcm512x->supplies), | |
1583 | pcm512x->supplies); | |
1584 | if (ret != 0) { | |
1585 | dev_err(dev, "Failed to enable supplies: %d\n", ret); | |
1586 | return ret; | |
1587 | } | |
1588 | ||
1589 | /* Reset the device, verifying I/O in the process for I2C */ | |
1590 | ret = regmap_write(regmap, PCM512x_RESET, | |
1591 | PCM512x_RSTM | PCM512x_RSTR); | |
1592 | if (ret != 0) { | |
1593 | dev_err(dev, "Failed to reset device: %d\n", ret); | |
1594 | goto err; | |
1595 | } | |
1596 | ||
1597 | ret = regmap_write(regmap, PCM512x_RESET, 0); | |
1598 | if (ret != 0) { | |
1599 | dev_err(dev, "Failed to reset device: %d\n", ret); | |
1600 | goto err; | |
1601 | } | |
1602 | ||
1603 | pcm512x->sclk = devm_clk_get(dev, NULL); | |
ac0a6899 MR |
1604 | if (PTR_ERR(pcm512x->sclk) == -EPROBE_DEFER) { |
1605 | ret = -EPROBE_DEFER; | |
1606 | goto err; | |
1607 | } | |
81249307 | 1608 | if (!IS_ERR(pcm512x->sclk)) { |
5a3af129 MB |
1609 | ret = clk_prepare_enable(pcm512x->sclk); |
1610 | if (ret != 0) { | |
1611 | dev_err(dev, "Failed to enable SCLK: %d\n", ret); | |
ac0a6899 | 1612 | goto err; |
5a3af129 MB |
1613 | } |
1614 | } | |
1615 | ||
1616 | /* Default to standby mode */ | |
1617 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER, | |
1618 | PCM512x_RQST, PCM512x_RQST); | |
1619 | if (ret != 0) { | |
1620 | dev_err(dev, "Failed to request standby: %d\n", | |
1621 | ret); | |
1622 | goto err_clk; | |
1623 | } | |
1624 | ||
1625 | pm_runtime_set_active(dev); | |
1626 | pm_runtime_enable(dev); | |
1627 | pm_runtime_idle(dev); | |
1628 | ||
f086ba9d PR |
1629 | #ifdef CONFIG_OF |
1630 | if (dev->of_node) { | |
1631 | const struct device_node *np = dev->of_node; | |
2599a960 | 1632 | u32 val; |
f086ba9d PR |
1633 | |
1634 | if (of_property_read_u32(np, "pll-in", &val) >= 0) { | |
1635 | if (val > 6) { | |
1636 | dev_err(dev, "Invalid pll-in\n"); | |
1637 | ret = -EINVAL; | |
1638 | goto err_clk; | |
1639 | } | |
1640 | pcm512x->pll_in = val; | |
1641 | } | |
1642 | ||
1643 | if (of_property_read_u32(np, "pll-out", &val) >= 0) { | |
1644 | if (val > 6) { | |
1645 | dev_err(dev, "Invalid pll-out\n"); | |
1646 | ret = -EINVAL; | |
1647 | goto err_clk; | |
1648 | } | |
1649 | pcm512x->pll_out = val; | |
1650 | } | |
1651 | ||
1652 | if (!pcm512x->pll_in != !pcm512x->pll_out) { | |
1653 | dev_err(dev, | |
1654 | "Error: both pll-in and pll-out, or none\n"); | |
1655 | ret = -EINVAL; | |
1656 | goto err_clk; | |
1657 | } | |
1658 | if (pcm512x->pll_in && pcm512x->pll_in == pcm512x->pll_out) { | |
1659 | dev_err(dev, "Error: pll-in == pll-out\n"); | |
1660 | ret = -EINVAL; | |
1661 | goto err_clk; | |
1662 | } | |
1663 | } | |
1664 | #endif | |
1665 | ||
5bdef14a | 1666 | ret = devm_snd_soc_register_component(dev, &pcm512x_component_driver, |
5a3af129 MB |
1667 | &pcm512x_dai, 1); |
1668 | if (ret != 0) { | |
1669 | dev_err(dev, "Failed to register CODEC: %d\n", ret); | |
1670 | goto err_pm; | |
1671 | } | |
1672 | ||
1673 | return 0; | |
1674 | ||
1675 | err_pm: | |
1676 | pm_runtime_disable(dev); | |
1677 | err_clk: | |
1678 | if (!IS_ERR(pcm512x->sclk)) | |
1679 | clk_disable_unprepare(pcm512x->sclk); | |
1680 | err: | |
1681 | regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies), | |
1682 | pcm512x->supplies); | |
1683 | return ret; | |
1684 | } | |
22066226 | 1685 | EXPORT_SYMBOL_GPL(pcm512x_probe); |
5a3af129 | 1686 | |
22066226 | 1687 | void pcm512x_remove(struct device *dev) |
5a3af129 MB |
1688 | { |
1689 | struct pcm512x_priv *pcm512x = dev_get_drvdata(dev); | |
1690 | ||
5a3af129 MB |
1691 | pm_runtime_disable(dev); |
1692 | if (!IS_ERR(pcm512x->sclk)) | |
1693 | clk_disable_unprepare(pcm512x->sclk); | |
1694 | regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies), | |
1695 | pcm512x->supplies); | |
1696 | } | |
22066226 | 1697 | EXPORT_SYMBOL_GPL(pcm512x_remove); |
5a3af129 | 1698 | |
641d334b | 1699 | #ifdef CONFIG_PM |
5a3af129 MB |
1700 | static int pcm512x_suspend(struct device *dev) |
1701 | { | |
1702 | struct pcm512x_priv *pcm512x = dev_get_drvdata(dev); | |
1703 | int ret; | |
1704 | ||
1705 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER, | |
1706 | PCM512x_RQPD, PCM512x_RQPD); | |
1707 | if (ret != 0) { | |
1708 | dev_err(dev, "Failed to request power down: %d\n", ret); | |
1709 | return ret; | |
1710 | } | |
1711 | ||
1712 | ret = regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies), | |
1713 | pcm512x->supplies); | |
1714 | if (ret != 0) { | |
1715 | dev_err(dev, "Failed to disable supplies: %d\n", ret); | |
1716 | return ret; | |
1717 | } | |
1718 | ||
1719 | if (!IS_ERR(pcm512x->sclk)) | |
1720 | clk_disable_unprepare(pcm512x->sclk); | |
1721 | ||
1722 | return 0; | |
1723 | } | |
1724 | ||
1725 | static int pcm512x_resume(struct device *dev) | |
1726 | { | |
1727 | struct pcm512x_priv *pcm512x = dev_get_drvdata(dev); | |
1728 | int ret; | |
1729 | ||
1730 | if (!IS_ERR(pcm512x->sclk)) { | |
1731 | ret = clk_prepare_enable(pcm512x->sclk); | |
1732 | if (ret != 0) { | |
1733 | dev_err(dev, "Failed to enable SCLK: %d\n", ret); | |
1734 | return ret; | |
1735 | } | |
1736 | } | |
1737 | ||
1738 | ret = regulator_bulk_enable(ARRAY_SIZE(pcm512x->supplies), | |
1739 | pcm512x->supplies); | |
1740 | if (ret != 0) { | |
1741 | dev_err(dev, "Failed to enable supplies: %d\n", ret); | |
1742 | return ret; | |
1743 | } | |
1744 | ||
1745 | regcache_cache_only(pcm512x->regmap, false); | |
1746 | ret = regcache_sync(pcm512x->regmap); | |
1747 | if (ret != 0) { | |
1748 | dev_err(dev, "Failed to sync cache: %d\n", ret); | |
1749 | return ret; | |
1750 | } | |
1751 | ||
1752 | ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER, | |
1753 | PCM512x_RQPD, 0); | |
1754 | if (ret != 0) { | |
1755 | dev_err(dev, "Failed to remove power down: %d\n", ret); | |
1756 | return ret; | |
1757 | } | |
1758 | ||
1759 | return 0; | |
1760 | } | |
ccffbd27 | 1761 | #endif |
5a3af129 | 1762 | |
22066226 | 1763 | const struct dev_pm_ops pcm512x_pm_ops = { |
5a3af129 MB |
1764 | SET_RUNTIME_PM_OPS(pcm512x_suspend, pcm512x_resume, NULL) |
1765 | }; | |
22066226 | 1766 | EXPORT_SYMBOL_GPL(pcm512x_pm_ops); |
5a3af129 MB |
1767 | |
1768 | MODULE_DESCRIPTION("ASoC PCM512x codec driver"); | |
da924c3a | 1769 | MODULE_AUTHOR("Mark Brown <broonie@kernel.org>"); |
5a3af129 | 1770 | MODULE_LICENSE("GPL v2"); |