projects / linux-block.git / blame
| Commit | Line | Data |
|---|---|---|
| d2912cb1 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 34ca27f3 AP |
2 | /* |
| 3 | * NAU8825 ALSA SoC audio driver | |
| 4 | * | |
| 5 | * Copyright 2015 Google Inc. | |
| 6 | * Author: Anatol Pomozov <anatol.pomozov@chrominium.org> | |
| 34ca27f3 AP |
7 | */ |
| 8 | ||
| 9 | #ifndef __NAU8825_H__ | |
| 10 | #define __NAU8825_H__ | |
| 11 | ||
| 12 | #define NAU8825_REG_RESET 0x00 | |
| 13 | #define NAU8825_REG_ENA_CTRL 0x01 | |
| 45d5eb3a | 14 | #define NAU8825_REG_IIC_ADDR_SET 0x02 |
| 34ca27f3 AP |
15 | #define NAU8825_REG_CLK_DIVIDER 0x03 |
| 16 | #define NAU8825_REG_FLL1 0x04 | |
| 17 | #define NAU8825_REG_FLL2 0x05 | |
| 18 | #define NAU8825_REG_FLL3 0x06 | |
| 19 | #define NAU8825_REG_FLL4 0x07 | |
| 20 | #define NAU8825_REG_FLL5 0x08 | |
| 21 | #define NAU8825_REG_FLL6 0x09 | |
| 22 | #define NAU8825_REG_FLL_VCO_RSV 0x0a | |
| 23 | #define NAU8825_REG_HSD_CTRL 0x0c | |
| 24 | #define NAU8825_REG_JACK_DET_CTRL 0x0d | |
| 25 | #define NAU8825_REG_INTERRUPT_MASK 0x0f | |
| 26 | #define NAU8825_REG_IRQ_STATUS 0x10 | |
| 27 | #define NAU8825_REG_INT_CLR_KEY_STATUS 0x11 | |
| 28 | #define NAU8825_REG_INTERRUPT_DIS_CTRL 0x12 | |
| 29 | #define NAU8825_REG_SAR_CTRL 0x13 | |
| 30 | #define NAU8825_REG_KEYDET_CTRL 0x14 | |
| 31 | #define NAU8825_REG_VDET_THRESHOLD_1 0x15 | |
| 32 | #define NAU8825_REG_VDET_THRESHOLD_2 0x16 | |
| 33 | #define NAU8825_REG_VDET_THRESHOLD_3 0x17 | |
| 34 | #define NAU8825_REG_VDET_THRESHOLD_4 0x18 | |
| 35 | #define NAU8825_REG_GPIO34_CTRL 0x19 | |
| 36 | #define NAU8825_REG_GPIO12_CTRL 0x1a | |
| 37 | #define NAU8825_REG_TDM_CTRL 0x1b | |
| 38 | #define NAU8825_REG_I2S_PCM_CTRL1 0x1c | |
| 39 | #define NAU8825_REG_I2S_PCM_CTRL2 0x1d | |
| 40 | #define NAU8825_REG_LEFT_TIME_SLOT 0x1e | |
| 41 | #define NAU8825_REG_RIGHT_TIME_SLOT 0x1f | |
| 42 | #define NAU8825_REG_BIQ_CTRL 0x20 | |
| 43 | #define NAU8825_REG_BIQ_COF1 0x21 | |
| 44 | #define NAU8825_REG_BIQ_COF2 0x22 | |
| 45 | #define NAU8825_REG_BIQ_COF3 0x23 | |
| 46 | #define NAU8825_REG_BIQ_COF4 0x24 | |
| 47 | #define NAU8825_REG_BIQ_COF5 0x25 | |
| 48 | #define NAU8825_REG_BIQ_COF6 0x26 | |
| 49 | #define NAU8825_REG_BIQ_COF7 0x27 | |
| 50 | #define NAU8825_REG_BIQ_COF8 0x28 | |
| 51 | #define NAU8825_REG_BIQ_COF9 0x29 | |
| 52 | #define NAU8825_REG_BIQ_COF10 0x2a | |
| 53 | #define NAU8825_REG_ADC_RATE 0x2b | |
| 54 | #define NAU8825_REG_DAC_CTRL1 0x2c | |
| 55 | #define NAU8825_REG_DAC_CTRL2 0x2d | |
| 56 | #define NAU8825_REG_DAC_DGAIN_CTRL 0x2f | |
| 57 | #define NAU8825_REG_ADC_DGAIN_CTRL 0x30 | |
| 58 | #define NAU8825_REG_MUTE_CTRL 0x31 | |
| 59 | #define NAU8825_REG_HSVOL_CTRL 0x32 | |
| 60 | #define NAU8825_REG_DACL_CTRL 0x33 | |
| 61 | #define NAU8825_REG_DACR_CTRL 0x34 | |
| 62 | #define NAU8825_REG_ADC_DRC_KNEE_IP12 0x38 | |
| 63 | #define NAU8825_REG_ADC_DRC_KNEE_IP34 0x39 | |
| 64 | #define NAU8825_REG_ADC_DRC_SLOPES 0x3a | |
| 65 | #define NAU8825_REG_ADC_DRC_ATKDCY 0x3b | |
| 66 | #define NAU8825_REG_DAC_DRC_KNEE_IP12 0x45 | |
| 67 | #define NAU8825_REG_DAC_DRC_KNEE_IP34 0x46 | |
| 68 | #define NAU8825_REG_DAC_DRC_SLOPES 0x47 | |
| 69 | #define NAU8825_REG_DAC_DRC_ATKDCY 0x48 | |
| 70 | #define NAU8825_REG_IMM_MODE_CTRL 0x4c | |
| 71 | #define NAU8825_REG_IMM_RMS_L 0x4d | |
| 72 | #define NAU8825_REG_IMM_RMS_R 0x4e | |
| 73 | #define NAU8825_REG_CLASSG_CTRL 0x50 | |
| 74 | #define NAU8825_REG_OPT_EFUSE_CTRL 0x51 | |
| 75 | #define NAU8825_REG_MISC_CTRL 0x55 | |
| 76 | #define NAU8825_REG_I2C_DEVICE_ID 0x58 | |
| 77 | #define NAU8825_REG_SARDOUT_RAM_STATUS 0x59 | |
| 78 | #define NAU8825_REG_BIAS_ADJ 0x66 | |
| 79 | #define NAU8825_REG_TRIM_SETTINGS 0x68 | |
| 80 | #define NAU8825_REG_ANALOG_CONTROL_1 0x69 | |
| 81 | #define NAU8825_REG_ANALOG_CONTROL_2 0x6a | |
| 82 | #define NAU8825_REG_ANALOG_ADC_1 0x71 | |
| 83 | #define NAU8825_REG_ANALOG_ADC_2 0x72 | |
| 84 | #define NAU8825_REG_RDAC 0x73 | |
| 85 | #define NAU8825_REG_MIC_BIAS 0x74 | |
| 86 | #define NAU8825_REG_BOOST 0x76 | |
| 87 | #define NAU8825_REG_FEPGA 0x77 | |
| 88 | #define NAU8825_REG_POWER_UP_CONTROL 0x7f | |
| 89 | #define NAU8825_REG_CHARGE_PUMP 0x80 | |
| 90 | #define NAU8825_REG_CHARGE_PUMP_INPUT_READ 0x81 | |
| 91 | #define NAU8825_REG_GENERAL_STATUS 0x82 | |
| 92 | #define NAU8825_REG_MAX NAU8825_REG_GENERAL_STATUS | |
| 2ec30f60 JH |
93 | /* 16-bit control register address, and 16-bits control register data */ |
| 94 | #define NAU8825_REG_ADDR_LEN 16 | |
| 95 | #define NAU8825_REG_DATA_LEN 16 | |
| 34ca27f3 AP |
96 | |
| 97 | /* ENA_CTRL (0x1) */ | |
| 98 | #define NAU8825_ENABLE_DACR_SFT 10 | |
| 99 | #define NAU8825_ENABLE_DACR (1 << NAU8825_ENABLE_DACR_SFT) | |
| 100 | #define NAU8825_ENABLE_DACL_SFT 9 | |
| b50455fa | 101 | #define NAU8825_ENABLE_DACL (1 << NAU8825_ENABLE_DACL_SFT) |
| 34ca27f3 | 102 | #define NAU8825_ENABLE_ADC_SFT 8 |
| eeef16ac | 103 | #define NAU8825_ENABLE_ADC (1 << NAU8825_ENABLE_ADC_SFT) |
| b50455fa JH |
104 | #define NAU8825_ENABLE_ADC_CLK_SFT 7 |
| 105 | #define NAU8825_ENABLE_ADC_CLK (1 << NAU8825_ENABLE_ADC_CLK_SFT) | |
| 106 | #define NAU8825_ENABLE_DAC_CLK_SFT 6 | |
| 107 | #define NAU8825_ENABLE_DAC_CLK (1 << NAU8825_ENABLE_DAC_CLK_SFT) | |
| 34ca27f3 AP |
108 | #define NAU8825_ENABLE_SAR_SFT 1 |
| 109 | ||
| 110 | /* CLK_DIVIDER (0x3) */ | |
| c86ba612 BZ |
111 | #define NAU8825_CLK_SRC_SFT 15 |
| 112 | #define NAU8825_CLK_SRC_MASK (1 << NAU8825_CLK_SRC_SFT) | |
| 113 | #define NAU8825_CLK_SRC_VCO (1 << NAU8825_CLK_SRC_SFT) | |
| 114 | #define NAU8825_CLK_SRC_MCLK (0 << NAU8825_CLK_SRC_SFT) | |
| d6d19745 JH |
115 | #define NAU8825_CLK_ADC_SRC_SFT 6 |
| 116 | #define NAU8825_CLK_ADC_SRC_MASK (0x3 << NAU8825_CLK_ADC_SRC_SFT) | |
| 117 | #define NAU8825_CLK_DAC_SRC_SFT 4 | |
| 118 | #define NAU8825_CLK_DAC_SRC_MASK (0x3 << NAU8825_CLK_DAC_SRC_SFT) | |
| c86ba612 BZ |
119 | #define NAU8825_CLK_MCLK_SRC_MASK (0xf << 0) |
| 120 | ||
| 121 | /* FLL1 (0x04) */ | |
| aee02c75 JH |
122 | #define NAU8825_ICTRL_LATCH_SFT 10 |
| 123 | #define NAU8825_ICTRL_LATCH_MASK (0x7 << NAU8825_ICTRL_LATCH_SFT) | |
| c86ba612 BZ |
124 | #define NAU8825_FLL_RATIO_MASK (0x7f << 0) |
| 125 | ||
| 126 | /* FLL3 (0x06) */ | |
| aee02c75 JH |
127 | #define NAU8825_GAIN_ERR_SFT 12 |
| 128 | #define NAU8825_GAIN_ERR_MASK (0xf << NAU8825_GAIN_ERR_SFT) | |
| c86ba612 | 129 | #define NAU8825_FLL_INTEGER_MASK (0x3ff << 0) |
| 70543c30 JH |
130 | #define NAU8825_FLL_CLK_SRC_SFT 10 |
| 131 | #define NAU8825_FLL_CLK_SRC_MASK (0x3 << NAU8825_FLL_CLK_SRC_SFT) | |
| 132 | #define NAU8825_FLL_CLK_SRC_MCLK (0 << NAU8825_FLL_CLK_SRC_SFT) | |
| 133 | #define NAU8825_FLL_CLK_SRC_BLK (0x2 << NAU8825_FLL_CLK_SRC_SFT) | |
| 134 | #define NAU8825_FLL_CLK_SRC_FS (0x3 << NAU8825_FLL_CLK_SRC_SFT) | |
| c86ba612 BZ |
135 | |
| 136 | /* FLL4 (0x07) */ | |
| a1792cda JH |
137 | #define NAU8825_FLL_REF_DIV_SFT 10 |
| 138 | #define NAU8825_FLL_REF_DIV_MASK (0x3 << NAU8825_FLL_REF_DIV_SFT) | |
| c86ba612 BZ |
139 | |
| 140 | /* FLL5 (0x08) */ | |
| 407c71b6 JH |
141 | #define NAU8825_FLL_PDB_DAC_EN (0x1 << 15) |
| 142 | #define NAU8825_FLL_LOOP_FTR_EN (0x1 << 14) | |
| 143 | #define NAU8825_FLL_CLK_SW_MASK (0x1 << 13) | |
| 144 | #define NAU8825_FLL_CLK_SW_N2 (0x1 << 13) | |
| 145 | #define NAU8825_FLL_CLK_SW_REF (0x0 << 13) | |
| 146 | #define NAU8825_FLL_FTR_SW_MASK (0x1 << 12) | |
| 147 | #define NAU8825_FLL_FTR_SW_ACCU (0x1 << 12) | |
| 148 | #define NAU8825_FLL_FTR_SW_FILTER (0x0 << 12) | |
| 34ca27f3 AP |
149 | |
| 150 | /* FLL6 (0x9) */ | |
| c86ba612 | 151 | #define NAU8825_DCO_EN (0x1 << 15) |
| c86ba612 | 152 | #define NAU8825_SDM_EN (0x1 << 14) |
| aee02c75 | 153 | #define NAU8825_CUTOFF500 (0x1 << 13) |
| 34ca27f3 AP |
154 | |
| 155 | /* HSD_CTRL (0xc) */ | |
| 156 | #define NAU8825_HSD_AUTO_MODE (1 << 6) | |
| 45d5eb3a | 157 | /* 0 - open, 1 - short to GND */ |
| 7a372650 DL |
158 | #define NAU8825_SPKR_ENGND1 (1 << 3) |
| 159 | #define NAU8825_SPKR_ENGND2 (1 << 2) | |
| 34ca27f3 AP |
160 | #define NAU8825_SPKR_DWN1R (1 << 1) |
| 161 | #define NAU8825_SPKR_DWN1L (1 << 0) | |
| 162 | ||
| 163 | /* JACK_DET_CTRL (0xd) */ | |
| 164 | #define NAU8825_JACK_DET_RESTART (1 << 9) | |
| 2ec30f60 | 165 | #define NAU8825_JACK_DET_DB_BYPASS (1 << 8) |
| 34ca27f3 AP |
166 | #define NAU8825_JACK_INSERT_DEBOUNCE_SFT 5 |
| 167 | #define NAU8825_JACK_INSERT_DEBOUNCE_MASK (0x7 << NAU8825_JACK_INSERT_DEBOUNCE_SFT) | |
| 168 | #define NAU8825_JACK_EJECT_DEBOUNCE_SFT 2 | |
| 169 | #define NAU8825_JACK_EJECT_DEBOUNCE_MASK (0x7 << NAU8825_JACK_EJECT_DEBOUNCE_SFT) | |
| 170 | #define NAU8825_JACK_POLARITY (1 << 1) /* 0 - active low, 1 - active high */ | |
| 171 | ||
| 172 | /* INTERRUPT_MASK (0xf) */ | |
| cbb9f8cc JH |
173 | #define NAU8825_IRQ_PIN_PULLUP (1 << 14) |
| 174 | #define NAU8825_IRQ_PIN_PULL_EN (1 << 13) | |
| 34ca27f3 AP |
175 | #define NAU8825_IRQ_OUTPUT_EN (1 << 11) |
| 176 | #define NAU8825_IRQ_HEADSET_COMPLETE_EN (1 << 10) | |
| b50455fa | 177 | #define NAU8825_IRQ_RMS_EN (1 << 8) |
| 34ca27f3 AP |
178 | #define NAU8825_IRQ_KEY_RELEASE_EN (1 << 7) |
| 179 | #define NAU8825_IRQ_KEY_SHORT_PRESS_EN (1 << 5) | |
| 180 | #define NAU8825_IRQ_EJECT_EN (1 << 2) | |
| 2ec30f60 | 181 | #define NAU8825_IRQ_INSERT_EN (1 << 0) |
| 34ca27f3 AP |
182 | |
| 183 | /* IRQ_STATUS (0x10) */ | |
| 184 | #define NAU8825_HEADSET_COMPLETION_IRQ (1 << 10) | |
| 185 | #define NAU8825_SHORT_CIRCUIT_IRQ (1 << 9) | |
| 186 | #define NAU8825_IMPEDANCE_MEAS_IRQ (1 << 8) | |
| 187 | #define NAU8825_KEY_IRQ_MASK (0x7 << 5) | |
| 188 | #define NAU8825_KEY_RELEASE_IRQ (1 << 7) | |
| 189 | #define NAU8825_KEY_LONG_PRESS_IRQ (1 << 6) | |
| 190 | #define NAU8825_KEY_SHORT_PRESS_IRQ (1 << 5) | |
| 191 | #define NAU8825_MIC_DETECTION_IRQ (1 << 4) | |
| 192 | #define NAU8825_JACK_EJECTION_IRQ_MASK (3 << 2) | |
| 193 | #define NAU8825_JACK_EJECTION_DETECTED (1 << 2) | |
| 194 | #define NAU8825_JACK_INSERTION_IRQ_MASK (3 << 0) | |
| 195 | #define NAU8825_JACK_INSERTION_DETECTED (1 << 0) | |
| 196 | ||
| 197 | /* INTERRUPT_DIS_CTRL (0x12) */ | |
| 198 | #define NAU8825_IRQ_HEADSET_COMPLETE_DIS (1 << 10) | |
| 199 | #define NAU8825_IRQ_KEY_RELEASE_DIS (1 << 7) | |
| 200 | #define NAU8825_IRQ_KEY_SHORT_PRESS_DIS (1 << 5) | |
| 201 | #define NAU8825_IRQ_EJECT_DIS (1 << 2) | |
| 2ec30f60 | 202 | #define NAU8825_IRQ_INSERT_DIS (1 << 0) |
| 34ca27f3 AP |
203 | |
| 204 | /* SAR_CTRL (0x13) */ | |
| 205 | #define NAU8825_SAR_ADC_EN_SFT 12 | |
| 206 | #define NAU8825_SAR_ADC_EN (1 << NAU8825_SAR_ADC_EN_SFT) | |
| 207 | #define NAU8825_SAR_INPUT_MASK (1 << 11) | |
| 208 | #define NAU8825_SAR_INPUT_JKSLV (1 << 11) | |
| 209 | #define NAU8825_SAR_INPUT_JKR2 (0 << 11) | |
| 210 | #define NAU8825_SAR_TRACKING_GAIN_SFT 8 | |
| 211 | #define NAU8825_SAR_TRACKING_GAIN_MASK (0x7 << NAU8825_SAR_TRACKING_GAIN_SFT) | |
| 7a372650 DL |
212 | #define NAU8825_SAR_HV_SEL_SFT 7 |
| 213 | #define NAU8825_SAR_HV_SEL_MASK (1 << NAU8825_SAR_HV_SEL_SFT) | |
| 214 | #define NAU8825_SAR_HV_SEL_MICBIAS (0 << NAU8825_SAR_HV_SEL_SFT) | |
| 215 | #define NAU8825_SAR_HV_SEL_VDDMIC (1 << NAU8825_SAR_HV_SEL_SFT) | |
| 216 | #define NAU8825_SAR_RES_SEL_SFT 4 | |
| 217 | #define NAU8825_SAR_RES_SEL_MASK (0x7 << NAU8825_SAR_RES_SEL_SFT) | |
| 218 | #define NAU8825_SAR_RES_SEL_35K (0 << NAU8825_SAR_RES_SEL_SFT) | |
| 219 | #define NAU8825_SAR_RES_SEL_70K (1 << NAU8825_SAR_RES_SEL_SFT) | |
| 220 | #define NAU8825_SAR_RES_SEL_170K (2 << NAU8825_SAR_RES_SEL_SFT) | |
| 221 | #define NAU8825_SAR_RES_SEL_360K (3 << NAU8825_SAR_RES_SEL_SFT) | |
| 222 | #define NAU8825_SAR_RES_SEL_SHORTED (4 << NAU8825_SAR_RES_SEL_SFT) | |
| 34ca27f3 AP |
223 | #define NAU8825_SAR_COMPARE_TIME_SFT 2 |
| 224 | #define NAU8825_SAR_COMPARE_TIME_MASK (3 << 2) | |
| 225 | #define NAU8825_SAR_SAMPLING_TIME_SFT 0 | |
| 226 | #define NAU8825_SAR_SAMPLING_TIME_MASK (3 << 0) | |
| 227 | ||
| 228 | /* KEYDET_CTRL (0x14) */ | |
| 229 | #define NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT 12 | |
| 230 | #define NAU8825_KEYDET_SHORTKEY_DEBOUNCE_MASK (0x3 << NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT) | |
| 231 | #define NAU8825_KEYDET_LEVELS_NR_SFT 8 | |
| 232 | #define NAU8825_KEYDET_LEVELS_NR_MASK (0x7 << 8) | |
| 233 | #define NAU8825_KEYDET_HYSTERESIS_SFT 0 | |
| 234 | #define NAU8825_KEYDET_HYSTERESIS_MASK 0xf | |
| 235 | ||
| 236 | /* GPIO12_CTRL (0x1a) */ | |
| 237 | #define NAU8825_JKDET_PULL_UP (1 << 11) /* 0 - pull down, 1 - pull up */ | |
| 238 | #define NAU8825_JKDET_PULL_EN (1 << 9) /* 0 - enable pull, 1 - disable */ | |
| 239 | #define NAU8825_JKDET_OUTPUT_EN (1 << 8) /* 0 - enable input, 1 - enable output */ | |
| 240 | ||
| dacdef1b DL |
241 | /* TDM_CTRL (0x1b) */ |
| 242 | #define NAU8825_TDM_MODE (0x1 << 15) | |
| 243 | #define NAU8825_TDM_OFFSET_EN (0x1 << 14) | |
| 244 | #define NAU8825_TDM_DACL_RX_SFT 6 | |
| 245 | #define NAU8825_TDM_DACL_RX_MASK (0x3 << NAU8825_TDM_DACL_RX_SFT) | |
| 246 | #define NAU8825_TDM_DACR_RX_SFT 4 | |
| 247 | #define NAU8825_TDM_DACR_RX_MASK (0x3 << NAU8825_TDM_DACR_RX_SFT) | |
| 248 | #define NAU8825_TDM_TX_MASK 0x3 | |
| 249 | ||
| 34ca27f3 AP |
250 | /* I2S_PCM_CTRL1 (0x1c) */ |
| 251 | #define NAU8825_I2S_BP_SFT 7 | |
| 252 | #define NAU8825_I2S_BP_MASK (1 << NAU8825_I2S_BP_SFT) | |
| 253 | #define NAU8825_I2S_BP_INV (1 << NAU8825_I2S_BP_SFT) | |
| 254 | #define NAU8825_I2S_PCMB_SFT 6 | |
| 255 | #define NAU8825_I2S_PCMB_MASK (1 << NAU8825_I2S_PCMB_SFT) | |
| 256 | #define NAU8825_I2S_PCMB_EN (1 << NAU8825_I2S_PCMB_SFT) | |
| 257 | #define NAU8825_I2S_DL_SFT 2 | |
| 258 | #define NAU8825_I2S_DL_MASK (0x3 << NAU8825_I2S_DL_SFT) | |
| 259 | #define NAU8825_I2S_DL_16 (0 << NAU8825_I2S_DL_SFT) | |
| 260 | #define NAU8825_I2S_DL_20 (1 << NAU8825_I2S_DL_SFT) | |
| 261 | #define NAU8825_I2S_DL_24 (2 << NAU8825_I2S_DL_SFT) | |
| 262 | #define NAU8825_I2S_DL_32 (3 << NAU8825_I2S_DL_SFT) | |
| 263 | #define NAU8825_I2S_DF_SFT 0 | |
| 264 | #define NAU8825_I2S_DF_MASK (0x3 << NAU8825_I2S_DF_SFT) | |
| 265 | #define NAU8825_I2S_DF_RIGTH (0 << NAU8825_I2S_DF_SFT) | |
| 266 | #define NAU8825_I2S_DF_LEFT (1 << NAU8825_I2S_DF_SFT) | |
| 267 | #define NAU8825_I2S_DF_I2S (2 << NAU8825_I2S_DF_SFT) | |
| 268 | #define NAU8825_I2S_DF_PCM_AB (3 << NAU8825_I2S_DF_SFT) | |
| 269 | ||
| 270 | /* I2S_PCM_CTRL2 (0x1d) */ | |
| 271 | #define NAU8825_I2S_TRISTATE (1 << 15) /* 0 - normal mode, 1 - Hi-Z output */ | |
| a33b56a6 JH |
272 | #define NAU8825_I2S_LRC_DIV_SFT 12 |
| 273 | #define NAU8825_I2S_LRC_DIV_MASK (0x3 << NAU8825_I2S_LRC_DIV_SFT) | |
| dacdef1b DL |
274 | #define NAU8825_I2S_PCM_TS_EN_SFT 10 |
| 275 | #define NAU8825_I2S_PCM_TS_EN_MASK (1 << NAU8825_I2S_PCM_TS_EN_SFT) | |
| 276 | #define NAU8825_I2S_PCM_TS_EN (1 << NAU8825_I2S_PCM_TS_EN_SFT) | |
| 34ca27f3 AP |
277 | #define NAU8825_I2S_MS_SFT 3 |
| 278 | #define NAU8825_I2S_MS_MASK (1 << NAU8825_I2S_MS_SFT) | |
| 279 | #define NAU8825_I2S_MS_MASTER (1 << NAU8825_I2S_MS_SFT) | |
| 280 | #define NAU8825_I2S_MS_SLAVE (0 << NAU8825_I2S_MS_SFT) | |
| b50455fa | 281 | #define NAU8825_I2S_BLK_DIV_MASK 0x7 |
| 34ca27f3 | 282 | |
| 93dfec75 JH |
283 | /* LEFT_TIME_SLOT (0x1e) */ |
| 284 | #define NAU8825_FS_ERR_CMP_SEL_SFT 14 | |
| 285 | #define NAU8825_FS_ERR_CMP_SEL_MASK (0x3 << NAU8825_FS_ERR_CMP_SEL_SFT) | |
| 286 | #define NAU8825_DIS_FS_SHORT_DET (1 << 13) | |
| dacdef1b DL |
287 | #define NAU8825_TSLOT_L0_MASK 0x3ff |
| 288 | #define NAU8825_TSLOT_R0_MASK 0x3ff | |
| 93dfec75 | 289 | |
| 18d8306d JH |
290 | /* BIQ_CTRL (0x20) */ |
| 291 | #define NAU8825_BIQ_WRT_SFT 4 | |
| 292 | #define NAU8825_BIQ_WRT_EN (1 << NAU8825_BIQ_WRT_SFT) | |
| 293 | #define NAU8825_BIQ_PATH_SFT 0 | |
| 294 | #define NAU8825_BIQ_PATH_MASK (1 << NAU8825_BIQ_PATH_SFT) | |
| 295 | #define NAU8825_BIQ_PATH_ADC (0 << NAU8825_BIQ_PATH_SFT) | |
| 296 | #define NAU8825_BIQ_PATH_DAC (1 << NAU8825_BIQ_PATH_SFT) | |
| 297 | ||
| 34ca27f3 | 298 | /* ADC_RATE (0x2b) */ |
| 5f1516d5 JH |
299 | #define NAU8825_ADC_SINC4_SFT 4 |
| 300 | #define NAU8825_ADC_SINC4_EN (1 << NAU8825_ADC_SINC4_SFT) | |
| 34ca27f3 AP |
301 | #define NAU8825_ADC_SYNC_DOWN_SFT 0 |
| 302 | #define NAU8825_ADC_SYNC_DOWN_MASK 0x3 | |
| 303 | #define NAU8825_ADC_SYNC_DOWN_32 0 | |
| 304 | #define NAU8825_ADC_SYNC_DOWN_64 1 | |
| 305 | #define NAU8825_ADC_SYNC_DOWN_128 2 | |
| 306 | #define NAU8825_ADC_SYNC_DOWN_256 3 | |
| 307 | ||
| 308 | /* DAC_CTRL1 (0x2c) */ | |
| 309 | #define NAU8825_DAC_CLIP_OFF (1 << 7) | |
| 310 | #define NAU8825_DAC_OVERSAMPLE_SFT 0 | |
| 311 | #define NAU8825_DAC_OVERSAMPLE_MASK 0x7 | |
| 312 | #define NAU8825_DAC_OVERSAMPLE_64 0 | |
| 313 | #define NAU8825_DAC_OVERSAMPLE_256 1 | |
| 314 | #define NAU8825_DAC_OVERSAMPLE_128 2 | |
| 315 | #define NAU8825_DAC_OVERSAMPLE_32 4 | |
| 316 | ||
| b50455fa JH |
317 | /* ADC_DGAIN_CTRL (0x30) */ |
| 318 | #define NAU8825_ADC_DIG_VOL_MASK 0xff | |
| 319 | ||
| 34ca27f3 AP |
320 | /* MUTE_CTRL (0x31) */ |
| 321 | #define NAU8825_DAC_ZERO_CROSSING_EN (1 << 9) | |
| 322 | #define NAU8825_DAC_SOFT_MUTE (1 << 9) | |
| 323 | ||
| 324 | /* HSVOL_CTRL (0x32) */ | |
| 325 | #define NAU8825_HP_MUTE (1 << 15) | |
| b50455fa JH |
326 | #define NAU8825_HP_MUTE_AUTO (1 << 14) |
| 327 | #define NAU8825_HPL_MUTE (1 << 13) | |
| 328 | #define NAU8825_HPR_MUTE (1 << 12) | |
| 329 | #define NAU8825_HPL_VOL_SFT 6 | |
| 330 | #define NAU8825_HPL_VOL_MASK (0x3f << NAU8825_HPL_VOL_SFT) | |
| 331 | #define NAU8825_HPR_VOL_SFT 0 | |
| 332 | #define NAU8825_HPR_VOL_MASK (0x3f << NAU8825_HPR_VOL_SFT) | |
| 333 | #define NAU8825_HP_VOL_MIN 0x36 | |
| 34ca27f3 AP |
334 | |
| 335 | /* DACL_CTRL (0x33) */ | |
| 336 | #define NAU8825_DACL_CH_SEL_SFT 9 | |
| 3f039169 JH |
337 | #define NAU8825_DACL_CH_SEL_MASK (0x1 << NAU8825_DACL_CH_SEL_SFT) |
| 338 | #define NAU8825_DACL_CH_SEL_L (0x0 << NAU8825_DACL_CH_SEL_SFT) | |
| 339 | #define NAU8825_DACL_CH_SEL_R (0x1 << NAU8825_DACL_CH_SEL_SFT) | |
| b50455fa | 340 | #define NAU8825_DACL_CH_VOL_MASK 0xff |
| 34ca27f3 AP |
341 | |
| 342 | /* DACR_CTRL (0x34) */ | |
| 343 | #define NAU8825_DACR_CH_SEL_SFT 9 | |
| 3f039169 JH |
344 | #define NAU8825_DACR_CH_SEL_MASK (0x1 << NAU8825_DACR_CH_SEL_SFT) |
| 345 | #define NAU8825_DACR_CH_SEL_L (0x0 << NAU8825_DACR_CH_SEL_SFT) | |
| 346 | #define NAU8825_DACR_CH_SEL_R (0x1 << NAU8825_DACR_CH_SEL_SFT) | |
| b50455fa JH |
347 | #define NAU8825_DACR_CH_VOL_MASK 0xff |
| 348 | ||
| 349 | /* IMM_MODE_CTRL (0x4C) */ | |
| 350 | #define NAU8825_IMM_THD_SFT 8 | |
| 351 | #define NAU8825_IMM_THD_MASK (0x3f << NAU8825_IMM_THD_SFT) | |
| 352 | #define NAU8825_IMM_GEN_VOL_SFT 6 | |
| 353 | #define NAU8825_IMM_GEN_VOL_MASK (0x3 << NAU8825_IMM_GEN_VOL_SFT) | |
| 354 | #define NAU8825_IMM_GEN_VOL_1_2nd (0x0 << NAU8825_IMM_GEN_VOL_SFT) | |
| 355 | #define NAU8825_IMM_GEN_VOL_1_4th (0x1 << NAU8825_IMM_GEN_VOL_SFT) | |
| 356 | #define NAU8825_IMM_GEN_VOL_1_8th (0x2 << NAU8825_IMM_GEN_VOL_SFT) | |
| 357 | #define NAU8825_IMM_GEN_VOL_1_16th (0x3 << NAU8825_IMM_GEN_VOL_SFT) | |
| 358 | ||
| 359 | #define NAU8825_IMM_CYC_SFT 4 | |
| 360 | #define NAU8825_IMM_CYC_MASK (0x3 << NAU8825_IMM_CYC_SFT) | |
| 361 | #define NAU8825_IMM_CYC_1024 (0x0 << NAU8825_IMM_CYC_SFT) | |
| 362 | #define NAU8825_IMM_CYC_2048 (0x1 << NAU8825_IMM_CYC_SFT) | |
| 363 | #define NAU8825_IMM_CYC_4096 (0x2 << NAU8825_IMM_CYC_SFT) | |
| 364 | #define NAU8825_IMM_CYC_8192 (0x3 << NAU8825_IMM_CYC_SFT) | |
| 365 | #define NAU8825_IMM_EN (1 << 3) | |
| 366 | #define NAU8825_IMM_DAC_SRC_MASK 0x7 | |
| 367 | #define NAU8825_IMM_DAC_SRC_BIQ 0x0 | |
| 368 | #define NAU8825_IMM_DAC_SRC_DRC 0x1 | |
| 369 | #define NAU8825_IMM_DAC_SRC_MIX 0x2 | |
| 370 | #define NAU8825_IMM_DAC_SRC_SIN 0x3 | |
| 34ca27f3 | 371 | |
| 45d5eb3a JH |
372 | /* CLASSG_CTRL (0x50) */ |
| 373 | #define NAU8825_CLASSG_TIMER_SFT 8 | |
| 374 | #define NAU8825_CLASSG_TIMER_MASK (0x3f << NAU8825_CLASSG_TIMER_SFT) | |
| b50455fa JH |
375 | #define NAU8825_CLASSG_TIMER_1ms (0x1 << NAU8825_CLASSG_TIMER_SFT) |
| 376 | #define NAU8825_CLASSG_TIMER_2ms (0x2 << NAU8825_CLASSG_TIMER_SFT) | |
| 377 | #define NAU8825_CLASSG_TIMER_8ms (0x4 << NAU8825_CLASSG_TIMER_SFT) | |
| 378 | #define NAU8825_CLASSG_TIMER_16ms (0x8 << NAU8825_CLASSG_TIMER_SFT) | |
| 379 | #define NAU8825_CLASSG_TIMER_32ms (0x10 << NAU8825_CLASSG_TIMER_SFT) | |
| 380 | #define NAU8825_CLASSG_TIMER_64ms (0x20 << NAU8825_CLASSG_TIMER_SFT) | |
| 381 | #define NAU8825_CLASSG_LDAC_EN (0x1 << 2) | |
| 382 | #define NAU8825_CLASSG_RDAC_EN (0x1 << 1) | |
| 45d5eb3a JH |
383 | #define NAU8825_CLASSG_EN (1 << 0) |
| 384 | ||
| 34ca27f3 AP |
385 | /* I2C_DEVICE_ID (0x58) */ |
| 386 | #define NAU8825_GPIO2JD1 (1 << 7) | |
| 387 | #define NAU8825_SOFTWARE_ID_MASK 0x3 | |
| 388 | #define NAU8825_SOFTWARE_ID_NAU8825 0x0 | |
| 389 | ||
| 390 | /* BIAS_ADJ (0x66) */ | |
| b50455fa JH |
391 | #define NAU8825_BIAS_HPR_IMP (1 << 15) |
| 392 | #define NAU8825_BIAS_HPL_IMP (1 << 14) | |
| 393 | #define NAU8825_BIAS_TESTDAC_SFT 8 | |
| 394 | #define NAU8825_BIAS_TESTDAC_EN (0x3 << NAU8825_BIAS_TESTDAC_SFT) | |
| 395 | #define NAU8825_BIAS_TESTDACR_EN (0x2 << NAU8825_BIAS_TESTDAC_SFT) | |
| 396 | #define NAU8825_BIAS_TESTDACL_EN (0x1 << NAU8825_BIAS_TESTDAC_SFT) | |
| 34ca27f3 AP |
397 | #define NAU8825_BIAS_VMID (1 << 6) |
| 398 | #define NAU8825_BIAS_VMID_SEL_SFT 4 | |
| 399 | #define NAU8825_BIAS_VMID_SEL_MASK (3 << NAU8825_BIAS_VMID_SEL_SFT) | |
| 400 | ||
| 7a372650 DL |
401 | /* ANALOG_CONTROL_1 (0x69) */ |
| 402 | #define NAU8825_TESTDACIN_SFT 14 | |
| 403 | #define NAU8825_TESTDACIN_MASK (0x3 << NAU8825_TESTDACIN_SFT) | |
| 404 | #define NAU8825_TESTDACIN_HIGH (1 << NAU8825_TESTDACIN_SFT) | |
| 405 | #define NAU8825_TESTDACIN_LOW (2 << NAU8825_TESTDACIN_SFT) | |
| 406 | #define NAU8825_TESTDACIN_GND (3 << NAU8825_TESTDACIN_SFT) | |
| 407 | ||
| 34ca27f3 AP |
408 | /* ANALOG_CONTROL_2 (0x6a) */ |
| 409 | #define NAU8825_HP_NON_CLASSG_CURRENT_2xADJ (1 << 12) | |
| 410 | #define NAU8825_DAC_CAPACITOR_MSB (1 << 1) | |
| 411 | #define NAU8825_DAC_CAPACITOR_LSB (1 << 0) | |
| 412 | ||
| 413 | /* ANALOG_ADC_2 (0x72) */ | |
| 414 | #define NAU8825_ADC_VREFSEL_MASK (0x3 << 8) | |
| 415 | #define NAU8825_ADC_VREFSEL_ANALOG (0 << 8) | |
| 416 | #define NAU8825_ADC_VREFSEL_VMID (1 << 8) | |
| 417 | #define NAU8825_ADC_VREFSEL_VMID_PLUS_0_5DB (2 << 8) | |
| 418 | #define NAU8825_ADC_VREFSEL_VMID_PLUS_1DB (3 << 8) | |
| 419 | #define NAU8825_POWERUP_ADCL (1 << 6) | |
| 420 | ||
| 45d5eb3a | 421 | /* RDAC (0x73) */ |
| b50455fa JH |
422 | #define NAU8825_RDAC_FS_BCLK_ENB (1 << 15) |
| 423 | #define NAU8825_RDAC_EN_SFT 12 | |
| 424 | #define NAU8825_RDAC_EN (0x3 << NAU8825_RDAC_EN_SFT) | |
| 425 | #define NAU8825_RDAC_CLK_EN_SFT 8 | |
| 426 | #define NAU8825_RDAC_CLK_EN (0x3 << NAU8825_RDAC_CLK_EN_SFT) | |
| 45d5eb3a JH |
427 | #define NAU8825_RDAC_CLK_DELAY_SFT 4 |
| 428 | #define NAU8825_RDAC_CLK_DELAY_MASK (0x7 << NAU8825_RDAC_CLK_DELAY_SFT) | |
| 429 | #define NAU8825_RDAC_VREF_SFT 2 | |
| 430 | #define NAU8825_RDAC_VREF_MASK (0x3 << NAU8825_RDAC_VREF_SFT) | |
| 431 | ||
| 34ca27f3 AP |
432 | /* MIC_BIAS (0x74) */ |
| 433 | #define NAU8825_MICBIAS_JKSLV (1 << 14) | |
| 434 | #define NAU8825_MICBIAS_JKR2 (1 << 12) | |
| 7a372650 DL |
435 | #define NAU8825_MICBIAS_LOWNOISE_SFT 10 |
| 436 | #define NAU8825_MICBIAS_LOWNOISE_MASK (0x1 << NAU8825_MICBIAS_LOWNOISE_SFT) | |
| 437 | #define NAU8825_MICBIAS_LOWNOISE_EN (0x1 << NAU8825_MICBIAS_LOWNOISE_SFT) | |
| 34ca27f3 AP |
438 | #define NAU8825_MICBIAS_POWERUP_SFT 8 |
| 439 | #define NAU8825_MICBIAS_VOLTAGE_SFT 0 | |
| 440 | #define NAU8825_MICBIAS_VOLTAGE_MASK 0x7 | |
| 441 | ||
| 442 | /* BOOST (0x76) */ | |
| 443 | #define NAU8825_PRECHARGE_DIS (1 << 13) | |
| 444 | #define NAU8825_GLOBAL_BIAS_EN (1 << 12) | |
| 45d5eb3a | 445 | #define NAU8825_HP_BOOST_DIS (1 << 9) |
| 34ca27f3 AP |
446 | #define NAU8825_HP_BOOST_G_DIS (1 << 8) |
| 447 | #define NAU8825_SHORT_SHUTDOWN_EN (1 << 6) | |
| 448 | ||
| 449 | /* POWER_UP_CONTROL (0x7f) */ | |
| 450 | #define NAU8825_POWERUP_INTEGR_R (1 << 5) | |
| 451 | #define NAU8825_POWERUP_INTEGR_L (1 << 4) | |
| 452 | #define NAU8825_POWERUP_DRV_IN_R (1 << 3) | |
| 453 | #define NAU8825_POWERUP_DRV_IN_L (1 << 2) | |
| 454 | #define NAU8825_POWERUP_HP_DRV_R (1 << 1) | |
| 455 | #define NAU8825_POWERUP_HP_DRV_L (1 << 0) | |
| 456 | ||
| 457 | /* CHARGE_PUMP (0x80) */ | |
| ed857072 DL |
458 | #define NAU8825_ADCOUT_DS_SFT 12 |
| 459 | #define NAU8825_ADCOUT_DS_MASK (1 << NAU8825_ADCOUT_DS_SFT) | |
| 34ca27f3 AP |
460 | #define NAU8825_JAMNODCLOW (1 << 10) |
| 461 | #define NAU8825_POWER_DOWN_DACR (1 << 9) | |
| 462 | #define NAU8825_POWER_DOWN_DACL (1 << 8) | |
| 463 | #define NAU8825_CHANRGE_PUMP_EN (1 << 5) | |
| 464 | ||
| 465 | ||
| 466 | /* System Clock Source */ | |
| 467 | enum { | |
| 2ec30f60 JH |
468 | NAU8825_CLK_DIS = 0, |
| 469 | NAU8825_CLK_MCLK, | |
| 34ca27f3 | 470 | NAU8825_CLK_INTERNAL, |
| 70543c30 JH |
471 | NAU8825_CLK_FLL_MCLK, |
| 472 | NAU8825_CLK_FLL_BLK, | |
| 473 | NAU8825_CLK_FLL_FS, | |
| 34ca27f3 AP |
474 | }; |
| 475 | ||
| b50455fa JH |
476 | /* Cross talk detection state */ |
| 477 | enum { | |
| 478 | NAU8825_XTALK_PREPARE = 0, | |
| 479 | NAU8825_XTALK_HPR_R2L, | |
| 480 | NAU8825_XTALK_HPL_R2L, | |
| 481 | NAU8825_XTALK_IMM, | |
| 482 | NAU8825_XTALK_DONE, | |
| 483 | }; | |
| 484 | ||
| 34ca27f3 AP |
485 | struct nau8825 { |
| 486 | struct device *dev; | |
| 487 | struct regmap *regmap; | |
| 488 | struct snd_soc_dapm_context *dapm; | |
| 489 | struct snd_soc_jack *jack; | |
| 490 | struct clk *mclk; | |
| b50455fa JH |
491 | struct work_struct xtalk_work; |
| 492 | struct semaphore xtalk_sem; | |
| 34ca27f3 AP |
493 | int irq; |
| 494 | int mclk_freq; /* 0 - mclk is disabled */ | |
| 495 | int button_pressed; | |
| 496 | int micbias_voltage; | |
| 497 | int vref_impedance; | |
| 498 | bool jkdet_enable; | |
| 499 | bool jkdet_pull_enable; | |
| 500 | bool jkdet_pull_up; | |
| 501 | int jkdet_polarity; | |
| 502 | int sar_threshold_num; | |
| 503 | int sar_threshold[8]; | |
| 504 | int sar_hysteresis; | |
| 505 | int sar_voltage; | |
| 506 | int sar_compare_time; | |
| 507 | int sar_sampling_time; | |
| 508 | int key_debounce; | |
| 509 | int jack_insert_debounce; | |
| 510 | int jack_eject_debounce; | |
| b50455fa JH |
511 | int high_imped; |
| 512 | int xtalk_state; | |
| 513 | int xtalk_event; | |
| 514 | int xtalk_event_mask; | |
| 515 | bool xtalk_protect; | |
| 516 | int imp_rms[NAU8825_XTALK_IMM]; | |
| 226d7449 | 517 | int xtalk_enable; |
| fa25b4f5 | 518 | bool xtalk_baktab_initialized; /* True if initialized. */ |
| ed857072 | 519 | bool adcout_ds; |
| fc0b096c | 520 | int adc_delay; |
| 34ca27f3 AP |
521 | }; |
| 522 | ||
| 45101122 | 523 | int nau8825_enable_jack_detect(struct snd_soc_component *component, |
| 34ca27f3 AP |
524 | struct snd_soc_jack *jack); |
| 525 | ||
| 526 | ||
| 527 | #endif /* __NAU8825_H__ */ |