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fda8d26e | 1 | // SPDX-License-Identifier: GPL-2.0-only |
34ca27f3 AP |
2 | /* |
3 | * Nuvoton NAU8825 audio codec driver | |
4 | * | |
5 | * Copyright 2015 Google Chromium project. | |
6 | * Author: Anatol Pomozov <anatol@chromium.org> | |
7 | * Copyright 2015 Nuvoton Technology Corp. | |
8 | * Co-author: Meng-Huang Kuo <mhkuo@nuvoton.com> | |
34ca27f3 AP |
9 | */ |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/init.h> | |
a0461632 | 14 | #include <linux/int_log.h> |
34ca27f3 AP |
15 | #include <linux/i2c.h> |
16 | #include <linux/regmap.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/clk.h> | |
b3681308 | 19 | #include <linux/acpi.h> |
c86ba612 | 20 | #include <linux/math64.h> |
b50455fa | 21 | #include <linux/semaphore.h> |
34ca27f3 AP |
22 | |
23 | #include <sound/initval.h> | |
24 | #include <sound/tlv.h> | |
25 | #include <sound/core.h> | |
26 | #include <sound/pcm.h> | |
27 | #include <sound/pcm_params.h> | |
28 | #include <sound/soc.h> | |
29 | #include <sound/jack.h> | |
30 | ||
31 | ||
32 | #include "nau8825.h" | |
33 | ||
2ec30f60 JH |
34 | |
35 | #define NUVOTON_CODEC_DAI "nau8825-hifi" | |
36 | ||
c86ba612 | 37 | #define NAU_FREF_MAX 13500000 |
407c71b6 | 38 | #define NAU_FVCO_MAX 124000000 |
c86ba612 BZ |
39 | #define NAU_FVCO_MIN 90000000 |
40 | ||
b50455fa | 41 | /* cross talk suppression detection */ |
b50455fa JH |
42 | #define GAIN_AUGMENT 22500 |
43 | #define SIDETONE_BASE 207000 | |
44 | ||
d6d19745 JH |
45 | /* the maximum frequency of CLK_ADC and CLK_DAC */ |
46 | #define CLK_DA_AD_MAX 6144000 | |
b50455fa | 47 | |
2ec30f60 JH |
48 | static int nau8825_configure_sysclk(struct nau8825 *nau8825, |
49 | int clk_id, unsigned int freq); | |
6133148c | 50 | static bool nau8825_is_jack_inserted(struct regmap *regmap); |
2ec30f60 | 51 | |
c86ba612 BZ |
52 | struct nau8825_fll { |
53 | int mclk_src; | |
54 | int ratio; | |
55 | int fll_frac; | |
6d64c33f | 56 | int fll_frac_num; |
c86ba612 BZ |
57 | int fll_int; |
58 | int clk_ref_div; | |
59 | }; | |
60 | ||
61 | struct nau8825_fll_attr { | |
62 | unsigned int param; | |
63 | unsigned int val; | |
64 | }; | |
65 | ||
66 | /* scaling for mclk from sysclk_src output */ | |
67 | static const struct nau8825_fll_attr mclk_src_scaling[] = { | |
68 | { 1, 0x0 }, | |
69 | { 2, 0x2 }, | |
70 | { 4, 0x3 }, | |
71 | { 8, 0x4 }, | |
72 | { 16, 0x5 }, | |
73 | { 32, 0x6 }, | |
74 | { 3, 0x7 }, | |
75 | { 6, 0xa }, | |
76 | { 12, 0xb }, | |
77 | { 24, 0xc }, | |
78 | { 48, 0xd }, | |
79 | { 96, 0xe }, | |
80 | { 5, 0xf }, | |
81 | }; | |
82 | ||
83 | /* ratio for input clk freq */ | |
84 | static const struct nau8825_fll_attr fll_ratio[] = { | |
85 | { 512000, 0x01 }, | |
86 | { 256000, 0x02 }, | |
87 | { 128000, 0x04 }, | |
88 | { 64000, 0x08 }, | |
89 | { 32000, 0x10 }, | |
90 | { 8000, 0x20 }, | |
91 | { 4000, 0x40 }, | |
92 | }; | |
93 | ||
94 | static const struct nau8825_fll_attr fll_pre_scalar[] = { | |
95 | { 1, 0x0 }, | |
96 | { 2, 0x1 }, | |
97 | { 4, 0x2 }, | |
98 | { 8, 0x3 }, | |
99 | }; | |
100 | ||
d6d19745 JH |
101 | /* over sampling rate */ |
102 | struct nau8825_osr_attr { | |
103 | unsigned int osr; | |
104 | unsigned int clk_src; | |
105 | }; | |
106 | ||
107 | static const struct nau8825_osr_attr osr_dac_sel[] = { | |
108 | { 64, 2 }, /* OSR 64, SRC 1/4 */ | |
109 | { 256, 0 }, /* OSR 256, SRC 1 */ | |
110 | { 128, 1 }, /* OSR 128, SRC 1/2 */ | |
111 | { 0, 0 }, | |
112 | { 32, 3 }, /* OSR 32, SRC 1/8 */ | |
113 | }; | |
114 | ||
115 | static const struct nau8825_osr_attr osr_adc_sel[] = { | |
116 | { 32, 3 }, /* OSR 32, SRC 1/8 */ | |
117 | { 64, 2 }, /* OSR 64, SRC 1/4 */ | |
118 | { 128, 1 }, /* OSR 128, SRC 1/2 */ | |
119 | { 256, 0 }, /* OSR 256, SRC 1 */ | |
120 | }; | |
121 | ||
34ca27f3 AP |
122 | static const struct reg_default nau8825_reg_defaults[] = { |
123 | { NAU8825_REG_ENA_CTRL, 0x00ff }, | |
45d5eb3a | 124 | { NAU8825_REG_IIC_ADDR_SET, 0x0 }, |
34ca27f3 AP |
125 | { NAU8825_REG_CLK_DIVIDER, 0x0050 }, |
126 | { NAU8825_REG_FLL1, 0x0 }, | |
127 | { NAU8825_REG_FLL2, 0x3126 }, | |
128 | { NAU8825_REG_FLL3, 0x0008 }, | |
129 | { NAU8825_REG_FLL4, 0x0010 }, | |
130 | { NAU8825_REG_FLL5, 0x0 }, | |
131 | { NAU8825_REG_FLL6, 0x6000 }, | |
132 | { NAU8825_REG_FLL_VCO_RSV, 0xf13c }, | |
133 | { NAU8825_REG_HSD_CTRL, 0x000c }, | |
134 | { NAU8825_REG_JACK_DET_CTRL, 0x0 }, | |
135 | { NAU8825_REG_INTERRUPT_MASK, 0x0 }, | |
136 | { NAU8825_REG_INTERRUPT_DIS_CTRL, 0xffff }, | |
137 | { NAU8825_REG_SAR_CTRL, 0x0015 }, | |
138 | { NAU8825_REG_KEYDET_CTRL, 0x0110 }, | |
139 | { NAU8825_REG_VDET_THRESHOLD_1, 0x0 }, | |
140 | { NAU8825_REG_VDET_THRESHOLD_2, 0x0 }, | |
141 | { NAU8825_REG_VDET_THRESHOLD_3, 0x0 }, | |
142 | { NAU8825_REG_VDET_THRESHOLD_4, 0x0 }, | |
143 | { NAU8825_REG_GPIO34_CTRL, 0x0 }, | |
144 | { NAU8825_REG_GPIO12_CTRL, 0x0 }, | |
145 | { NAU8825_REG_TDM_CTRL, 0x0 }, | |
146 | { NAU8825_REG_I2S_PCM_CTRL1, 0x000b }, | |
147 | { NAU8825_REG_I2S_PCM_CTRL2, 0x8010 }, | |
148 | { NAU8825_REG_LEFT_TIME_SLOT, 0x0 }, | |
149 | { NAU8825_REG_RIGHT_TIME_SLOT, 0x0 }, | |
150 | { NAU8825_REG_BIQ_CTRL, 0x0 }, | |
151 | { NAU8825_REG_BIQ_COF1, 0x0 }, | |
152 | { NAU8825_REG_BIQ_COF2, 0x0 }, | |
153 | { NAU8825_REG_BIQ_COF3, 0x0 }, | |
154 | { NAU8825_REG_BIQ_COF4, 0x0 }, | |
155 | { NAU8825_REG_BIQ_COF5, 0x0 }, | |
156 | { NAU8825_REG_BIQ_COF6, 0x0 }, | |
157 | { NAU8825_REG_BIQ_COF7, 0x0 }, | |
158 | { NAU8825_REG_BIQ_COF8, 0x0 }, | |
159 | { NAU8825_REG_BIQ_COF9, 0x0 }, | |
160 | { NAU8825_REG_BIQ_COF10, 0x0 }, | |
161 | { NAU8825_REG_ADC_RATE, 0x0010 }, | |
162 | { NAU8825_REG_DAC_CTRL1, 0x0001 }, | |
163 | { NAU8825_REG_DAC_CTRL2, 0x0 }, | |
164 | { NAU8825_REG_DAC_DGAIN_CTRL, 0x0 }, | |
165 | { NAU8825_REG_ADC_DGAIN_CTRL, 0x00cf }, | |
166 | { NAU8825_REG_MUTE_CTRL, 0x0 }, | |
167 | { NAU8825_REG_HSVOL_CTRL, 0x0 }, | |
168 | { NAU8825_REG_DACL_CTRL, 0x02cf }, | |
169 | { NAU8825_REG_DACR_CTRL, 0x00cf }, | |
170 | { NAU8825_REG_ADC_DRC_KNEE_IP12, 0x1486 }, | |
171 | { NAU8825_REG_ADC_DRC_KNEE_IP34, 0x0f12 }, | |
172 | { NAU8825_REG_ADC_DRC_SLOPES, 0x25ff }, | |
173 | { NAU8825_REG_ADC_DRC_ATKDCY, 0x3457 }, | |
174 | { NAU8825_REG_DAC_DRC_KNEE_IP12, 0x1486 }, | |
175 | { NAU8825_REG_DAC_DRC_KNEE_IP34, 0x0f12 }, | |
176 | { NAU8825_REG_DAC_DRC_SLOPES, 0x25f9 }, | |
177 | { NAU8825_REG_DAC_DRC_ATKDCY, 0x3457 }, | |
178 | { NAU8825_REG_IMM_MODE_CTRL, 0x0 }, | |
179 | { NAU8825_REG_CLASSG_CTRL, 0x0 }, | |
180 | { NAU8825_REG_OPT_EFUSE_CTRL, 0x0 }, | |
181 | { NAU8825_REG_MISC_CTRL, 0x0 }, | |
b81a2cc9 DL |
182 | { NAU8825_REG_FLL2_LOWER, 0x0 }, |
183 | { NAU8825_REG_FLL2_UPPER, 0x0 }, | |
34ca27f3 AP |
184 | { NAU8825_REG_BIAS_ADJ, 0x0 }, |
185 | { NAU8825_REG_TRIM_SETTINGS, 0x0 }, | |
186 | { NAU8825_REG_ANALOG_CONTROL_1, 0x0 }, | |
187 | { NAU8825_REG_ANALOG_CONTROL_2, 0x0 }, | |
188 | { NAU8825_REG_ANALOG_ADC_1, 0x0011 }, | |
189 | { NAU8825_REG_ANALOG_ADC_2, 0x0020 }, | |
190 | { NAU8825_REG_RDAC, 0x0008 }, | |
191 | { NAU8825_REG_MIC_BIAS, 0x0006 }, | |
192 | { NAU8825_REG_BOOST, 0x0 }, | |
193 | { NAU8825_REG_FEPGA, 0x0 }, | |
194 | { NAU8825_REG_POWER_UP_CONTROL, 0x0 }, | |
195 | { NAU8825_REG_CHARGE_PUMP, 0x0 }, | |
196 | }; | |
197 | ||
b50455fa JH |
198 | /* register backup table when cross talk detection */ |
199 | static struct reg_default nau8825_xtalk_baktab[] = { | |
fa25b4f5 | 200 | { NAU8825_REG_ADC_DGAIN_CTRL, 0x00cf }, |
b50455fa | 201 | { NAU8825_REG_HSVOL_CTRL, 0 }, |
fa25b4f5 JH |
202 | { NAU8825_REG_DACL_CTRL, 0x00cf }, |
203 | { NAU8825_REG_DACR_CTRL, 0x02cf }, | |
b50455fa JH |
204 | }; |
205 | ||
b81a2cc9 DL |
206 | /* The regmap patch for Rev C */ |
207 | static const struct reg_sequence nau8825_regmap_patch[] = { | |
208 | { NAU8825_REG_FLL2, 0x0000 }, | |
209 | { NAU8825_REG_FLL4, 0x8010 }, | |
210 | { NAU8825_REG_FLL_VCO_RSV, 0x0bc0 }, | |
211 | { NAU8825_REG_INTERRUPT_MASK, 0x0800 }, | |
212 | { NAU8825_REG_DACL_CTRL, 0x00cf }, | |
213 | { NAU8825_REG_DACR_CTRL, 0x02cf }, | |
214 | { NAU8825_REG_OPT_EFUSE_CTRL, 0x0400 }, | |
215 | { NAU8825_REG_FLL2_LOWER, 0x26e9 }, | |
216 | { NAU8825_REG_FLL2_UPPER, 0x0031 }, | |
217 | { NAU8825_REG_ANALOG_CONTROL_2, 0x0020 }, | |
218 | { NAU8825_REG_ANALOG_ADC_2, 0x0220 }, | |
219 | { NAU8825_REG_MIC_BIAS, 0x0046 }, | |
220 | }; | |
221 | ||
b50455fa JH |
222 | /** |
223 | * nau8825_sema_acquire - acquire the semaphore of nau88l25 | |
224 | * @nau8825: component to register the codec private data with | |
225 | * @timeout: how long in jiffies to wait before failure or zero to wait | |
226 | * until release | |
227 | * | |
228 | * Attempts to acquire the semaphore with number of jiffies. If no more | |
229 | * tasks are allowed to acquire the semaphore, calling this function will | |
230 | * put the task to sleep. If the semaphore is not released within the | |
231 | * specified number of jiffies, this function returns. | |
06746c67 | 232 | * If the semaphore is not released within the specified number of jiffies, |
70424d8e JH |
233 | * this function returns -ETIME. If the sleep is interrupted by a signal, |
234 | * this function will return -EINTR. It returns 0 if the semaphore was | |
235 | * acquired successfully. | |
236 | * | |
237 | * Acquires the semaphore without jiffies. Try to acquire the semaphore | |
238 | * atomically. Returns 0 if the semaphore has been acquired successfully | |
85131d94 | 239 | * or 1 if it cannot be acquired. |
b50455fa | 240 | */ |
06746c67 | 241 | static int nau8825_sema_acquire(struct nau8825 *nau8825, long timeout) |
b50455fa JH |
242 | { |
243 | int ret; | |
244 | ||
06746c67 | 245 | if (timeout) { |
b50455fa | 246 | ret = down_timeout(&nau8825->xtalk_sem, timeout); |
06746c67 | 247 | if (ret < 0) |
3dfcd346 | 248 | dev_warn(nau8825->dev, "Acquire semaphore timeout\n"); |
06746c67 | 249 | } else { |
70424d8e JH |
250 | ret = down_trylock(&nau8825->xtalk_sem); |
251 | if (ret) | |
3dfcd346 | 252 | dev_warn(nau8825->dev, "Acquire semaphore fail\n"); |
06746c67 | 253 | } |
b50455fa | 254 | |
06746c67 | 255 | return ret; |
b50455fa JH |
256 | } |
257 | ||
258 | /** | |
259 | * nau8825_sema_release - release the semaphore of nau88l25 | |
260 | * @nau8825: component to register the codec private data with | |
261 | * | |
262 | * Release the semaphore which may be called from any context and | |
263 | * even by tasks which have never called down(). | |
264 | */ | |
265 | static inline void nau8825_sema_release(struct nau8825 *nau8825) | |
266 | { | |
267 | up(&nau8825->xtalk_sem); | |
268 | } | |
269 | ||
270 | /** | |
271 | * nau8825_sema_reset - reset the semaphore for nau88l25 | |
272 | * @nau8825: component to register the codec private data with | |
273 | * | |
274 | * Reset the counter of the semaphore. Call this function to restart | |
275 | * a new round task management. | |
276 | */ | |
277 | static inline void nau8825_sema_reset(struct nau8825 *nau8825) | |
278 | { | |
279 | nau8825->xtalk_sem.count = 1; | |
280 | } | |
281 | ||
282 | /** | |
075d7da7 | 283 | * nau8825_hpvol_ramp - Ramp up the headphone volume change gradually to target level. |
b50455fa JH |
284 | * |
285 | * @nau8825: component to register the codec private data with | |
286 | * @vol_from: the volume to start up | |
287 | * @vol_to: the target volume | |
288 | * @step: the volume span to move on | |
289 | * | |
290 | * The headphone volume is from 0dB to minimum -54dB and -1dB per step. | |
291 | * If the volume changes sharp, there is a pop noise heard in headphone. We | |
292 | * provide the function to ramp up the volume up or down by delaying 10ms | |
293 | * per step. | |
294 | */ | |
295 | static void nau8825_hpvol_ramp(struct nau8825 *nau8825, | |
296 | unsigned int vol_from, unsigned int vol_to, unsigned int step) | |
297 | { | |
298 | unsigned int value, volume, ramp_up, from, to; | |
299 | ||
300 | if (vol_from == vol_to || step == 0) { | |
301 | return; | |
302 | } else if (vol_from < vol_to) { | |
303 | ramp_up = true; | |
304 | from = vol_from; | |
305 | to = vol_to; | |
306 | } else { | |
307 | ramp_up = false; | |
308 | from = vol_to; | |
309 | to = vol_from; | |
310 | } | |
311 | /* only handle volume from 0dB to minimum -54dB */ | |
312 | if (to > NAU8825_HP_VOL_MIN) | |
313 | to = NAU8825_HP_VOL_MIN; | |
314 | ||
315 | for (volume = from; volume < to; volume += step) { | |
316 | if (ramp_up) | |
317 | value = volume; | |
318 | else | |
319 | value = to - volume + from; | |
320 | regmap_update_bits(nau8825->regmap, NAU8825_REG_HSVOL_CTRL, | |
321 | NAU8825_HPL_VOL_MASK | NAU8825_HPR_VOL_MASK, | |
322 | (value << NAU8825_HPL_VOL_SFT) | value); | |
323 | usleep_range(10000, 10500); | |
324 | } | |
325 | if (ramp_up) | |
326 | value = to; | |
327 | else | |
328 | value = from; | |
329 | regmap_update_bits(nau8825->regmap, NAU8825_REG_HSVOL_CTRL, | |
330 | NAU8825_HPL_VOL_MASK | NAU8825_HPR_VOL_MASK, | |
331 | (value << NAU8825_HPL_VOL_SFT) | value); | |
332 | } | |
333 | ||
334 | /** | |
a0461632 | 335 | * nau8825_intlog10_dec3 - Computes log10 of a value, rounding the result to 3 decimal places. |
dc22a409 | 336 | * @value: input for log10 |
b50455fa JH |
337 | * |
338 | * return log10(value) * 1000 | |
339 | */ | |
340 | static u32 nau8825_intlog10_dec3(u32 value) | |
341 | { | |
a0461632 | 342 | return intlog10(value) / ((1 << 24) / 1000); |
b50455fa JH |
343 | } |
344 | ||
345 | /** | |
075d7da7 | 346 | * nau8825_xtalk_sidetone - computes cross talk suppression sidetone gain. |
b50455fa JH |
347 | * |
348 | * @sig_org: orignal signal level | |
349 | * @sig_cros: cross talk signal level | |
350 | * | |
351 | * The orignal and cross talk signal vlues need to be characterized. | |
352 | * Once these values have been characterized, this sidetone value | |
353 | * can be converted to decibel with the equation below. | |
354 | * sidetone = 20 * log (original signal level / crosstalk signal level) | |
355 | * | |
356 | * return cross talk sidetone gain | |
357 | */ | |
358 | static u32 nau8825_xtalk_sidetone(u32 sig_org, u32 sig_cros) | |
359 | { | |
360 | u32 gain, sidetone; | |
361 | ||
0b6277e6 | 362 | if (WARN_ON(sig_org == 0 || sig_cros == 0)) |
b50455fa | 363 | return 0; |
b50455fa JH |
364 | |
365 | sig_org = nau8825_intlog10_dec3(sig_org); | |
366 | sig_cros = nau8825_intlog10_dec3(sig_cros); | |
367 | if (sig_org >= sig_cros) | |
368 | gain = (sig_org - sig_cros) * 20 + GAIN_AUGMENT; | |
369 | else | |
370 | gain = (sig_cros - sig_org) * 20 + GAIN_AUGMENT; | |
371 | sidetone = SIDETONE_BASE - gain * 2; | |
372 | sidetone /= 1000; | |
373 | ||
374 | return sidetone; | |
375 | } | |
376 | ||
377 | static int nau8825_xtalk_baktab_index_by_reg(unsigned int reg) | |
378 | { | |
379 | int index; | |
380 | ||
381 | for (index = 0; index < ARRAY_SIZE(nau8825_xtalk_baktab); index++) | |
382 | if (nau8825_xtalk_baktab[index].reg == reg) | |
383 | return index; | |
384 | return -EINVAL; | |
385 | } | |
386 | ||
387 | static void nau8825_xtalk_backup(struct nau8825 *nau8825) | |
388 | { | |
389 | int i; | |
390 | ||
fa25b4f5 JH |
391 | if (nau8825->xtalk_baktab_initialized) |
392 | return; | |
393 | ||
b50455fa JH |
394 | /* Backup some register values to backup table */ |
395 | for (i = 0; i < ARRAY_SIZE(nau8825_xtalk_baktab); i++) | |
396 | regmap_read(nau8825->regmap, nau8825_xtalk_baktab[i].reg, | |
397 | &nau8825_xtalk_baktab[i].def); | |
fa25b4f5 JH |
398 | |
399 | nau8825->xtalk_baktab_initialized = true; | |
b50455fa JH |
400 | } |
401 | ||
fa25b4f5 | 402 | static void nau8825_xtalk_restore(struct nau8825 *nau8825, bool cause_cancel) |
b50455fa JH |
403 | { |
404 | int i, volume; | |
405 | ||
fa25b4f5 JH |
406 | if (!nau8825->xtalk_baktab_initialized) |
407 | return; | |
408 | ||
b50455fa | 409 | /* Restore register values from backup table; When the driver restores |
fa25b4f5 JH |
410 | * the headphone volume in XTALK_DONE state, it needs recover to |
411 | * original level gradually with 3dB per step for less pop noise. | |
412 | * Otherwise, the restore should do ASAP. | |
b50455fa JH |
413 | */ |
414 | for (i = 0; i < ARRAY_SIZE(nau8825_xtalk_baktab); i++) { | |
fa25b4f5 JH |
415 | if (!cause_cancel && nau8825_xtalk_baktab[i].reg == |
416 | NAU8825_REG_HSVOL_CTRL) { | |
b50455fa JH |
417 | /* Ramping up the volume change to reduce pop noise */ |
418 | volume = nau8825_xtalk_baktab[i].def & | |
419 | NAU8825_HPR_VOL_MASK; | |
420 | nau8825_hpvol_ramp(nau8825, 0, volume, 3); | |
421 | continue; | |
422 | } | |
423 | regmap_write(nau8825->regmap, nau8825_xtalk_baktab[i].reg, | |
424 | nau8825_xtalk_baktab[i].def); | |
425 | } | |
fa25b4f5 JH |
426 | |
427 | nau8825->xtalk_baktab_initialized = false; | |
b50455fa JH |
428 | } |
429 | ||
430 | static void nau8825_xtalk_prepare_dac(struct nau8825 *nau8825) | |
431 | { | |
432 | /* Enable power of DAC path */ | |
433 | regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL, | |
434 | NAU8825_ENABLE_DACR | NAU8825_ENABLE_DACL | | |
435 | NAU8825_ENABLE_ADC | NAU8825_ENABLE_ADC_CLK | | |
436 | NAU8825_ENABLE_DAC_CLK, NAU8825_ENABLE_DACR | | |
437 | NAU8825_ENABLE_DACL | NAU8825_ENABLE_ADC | | |
438 | NAU8825_ENABLE_ADC_CLK | NAU8825_ENABLE_DAC_CLK); | |
439 | /* Prevent startup click by letting charge pump to ramp up and | |
440 | * change bump enable | |
441 | */ | |
442 | regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, | |
443 | NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN, | |
444 | NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN); | |
445 | /* Enable clock sync of DAC and DAC clock */ | |
446 | regmap_update_bits(nau8825->regmap, NAU8825_REG_RDAC, | |
447 | NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN | | |
448 | NAU8825_RDAC_FS_BCLK_ENB, | |
449 | NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN); | |
450 | /* Power up output driver with 2 stage */ | |
451 | regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL, | |
452 | NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L | | |
453 | NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L, | |
454 | NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L | | |
455 | NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L); | |
456 | regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL, | |
457 | NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L, | |
458 | NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L); | |
459 | /* HP outputs not shouted to ground */ | |
460 | regmap_update_bits(nau8825->regmap, NAU8825_REG_HSD_CTRL, | |
461 | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L, 0); | |
462 | /* Enable HP boost driver */ | |
463 | regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST, | |
464 | NAU8825_HP_BOOST_DIS, NAU8825_HP_BOOST_DIS); | |
465 | /* Enable class G compare path to supply 1.8V or 0.9V. */ | |
466 | regmap_update_bits(nau8825->regmap, NAU8825_REG_CLASSG_CTRL, | |
467 | NAU8825_CLASSG_LDAC_EN | NAU8825_CLASSG_RDAC_EN, | |
468 | NAU8825_CLASSG_LDAC_EN | NAU8825_CLASSG_RDAC_EN); | |
469 | } | |
470 | ||
471 | static void nau8825_xtalk_prepare_adc(struct nau8825 *nau8825) | |
472 | { | |
473 | /* Power up left ADC and raise 5dB than Vmid for Vref */ | |
474 | regmap_update_bits(nau8825->regmap, NAU8825_REG_ANALOG_ADC_2, | |
475 | NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_MASK, | |
476 | NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_VMID_PLUS_0_5DB); | |
477 | } | |
478 | ||
479 | static void nau8825_xtalk_clock(struct nau8825 *nau8825) | |
480 | { | |
481 | /* Recover FLL default value */ | |
482 | regmap_write(nau8825->regmap, NAU8825_REG_FLL1, 0x0); | |
483 | regmap_write(nau8825->regmap, NAU8825_REG_FLL2, 0x3126); | |
484 | regmap_write(nau8825->regmap, NAU8825_REG_FLL3, 0x0008); | |
485 | regmap_write(nau8825->regmap, NAU8825_REG_FLL4, 0x0010); | |
486 | regmap_write(nau8825->regmap, NAU8825_REG_FLL5, 0x0); | |
487 | regmap_write(nau8825->regmap, NAU8825_REG_FLL6, 0x6000); | |
488 | /* Enable internal VCO clock for detection signal generated */ | |
489 | regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER, | |
490 | NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO); | |
491 | regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6, NAU8825_DCO_EN, | |
492 | NAU8825_DCO_EN); | |
493 | /* Given specific clock frequency of internal clock to | |
494 | * generate signal. | |
495 | */ | |
496 | regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER, | |
497 | NAU8825_CLK_MCLK_SRC_MASK, 0xf); | |
498 | regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1, | |
499 | NAU8825_FLL_RATIO_MASK, 0x10); | |
500 | } | |
501 | ||
502 | static void nau8825_xtalk_prepare(struct nau8825 *nau8825) | |
503 | { | |
504 | int volume, index; | |
505 | ||
506 | /* Backup those registers changed by cross talk detection */ | |
507 | nau8825_xtalk_backup(nau8825); | |
508 | /* Config IIS as master to output signal by codec */ | |
509 | regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2, | |
a33b56a6 | 510 | NAU8825_I2S_MS_MASK | NAU8825_I2S_LRC_DIV_MASK | |
b50455fa | 511 | NAU8825_I2S_BLK_DIV_MASK, NAU8825_I2S_MS_MASTER | |
a33b56a6 | 512 | (0x2 << NAU8825_I2S_LRC_DIV_SFT) | 0x1); |
b50455fa JH |
513 | /* Ramp up headphone volume to 0dB to get better performance and |
514 | * avoid pop noise in headphone. | |
515 | */ | |
516 | index = nau8825_xtalk_baktab_index_by_reg(NAU8825_REG_HSVOL_CTRL); | |
517 | if (index != -EINVAL) { | |
518 | volume = nau8825_xtalk_baktab[index].def & | |
519 | NAU8825_HPR_VOL_MASK; | |
520 | nau8825_hpvol_ramp(nau8825, volume, 0, 3); | |
521 | } | |
522 | nau8825_xtalk_clock(nau8825); | |
523 | nau8825_xtalk_prepare_dac(nau8825); | |
524 | nau8825_xtalk_prepare_adc(nau8825); | |
525 | /* Config channel path and digital gain */ | |
526 | regmap_update_bits(nau8825->regmap, NAU8825_REG_DACL_CTRL, | |
527 | NAU8825_DACL_CH_SEL_MASK | NAU8825_DACL_CH_VOL_MASK, | |
528 | NAU8825_DACL_CH_SEL_L | 0xab); | |
529 | regmap_update_bits(nau8825->regmap, NAU8825_REG_DACR_CTRL, | |
530 | NAU8825_DACR_CH_SEL_MASK | NAU8825_DACR_CH_VOL_MASK, | |
531 | NAU8825_DACR_CH_SEL_R | 0xab); | |
532 | /* Config cross talk parameters and generate the 23Hz sine wave with | |
533 | * 1/16 full scale of signal level for impedance measurement. | |
534 | */ | |
535 | regmap_update_bits(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL, | |
536 | NAU8825_IMM_THD_MASK | NAU8825_IMM_GEN_VOL_MASK | | |
537 | NAU8825_IMM_CYC_MASK | NAU8825_IMM_DAC_SRC_MASK, | |
538 | (0x9 << NAU8825_IMM_THD_SFT) | NAU8825_IMM_GEN_VOL_1_16th | | |
539 | NAU8825_IMM_CYC_8192 | NAU8825_IMM_DAC_SRC_SIN); | |
540 | /* RMS intrruption enable */ | |
541 | regmap_update_bits(nau8825->regmap, | |
542 | NAU8825_REG_INTERRUPT_MASK, NAU8825_IRQ_RMS_EN, 0); | |
543 | /* Power up left and right DAC */ | |
955b503b DL |
544 | if (nau8825->sw_id == NAU8825_SOFTWARE_ID_NAU8825) |
545 | regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, | |
546 | NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 0); | |
547 | else | |
548 | regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, | |
549 | NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, | |
550 | NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL); | |
b50455fa JH |
551 | } |
552 | ||
553 | static void nau8825_xtalk_clean_dac(struct nau8825 *nau8825) | |
554 | { | |
555 | /* Disable HP boost driver */ | |
556 | regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST, | |
557 | NAU8825_HP_BOOST_DIS, 0); | |
558 | /* HP outputs shouted to ground */ | |
559 | regmap_update_bits(nau8825->regmap, NAU8825_REG_HSD_CTRL, | |
560 | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L, | |
561 | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L); | |
562 | /* Power down left and right DAC */ | |
955b503b DL |
563 | if (nau8825->sw_id == NAU8825_SOFTWARE_ID_NAU8825) |
564 | regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, | |
565 | NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, | |
566 | NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL); | |
567 | else | |
568 | regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, | |
569 | NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 0); | |
570 | ||
b50455fa JH |
571 | /* Enable the TESTDAC and disable L/R HP impedance */ |
572 | regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ, | |
573 | NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP | | |
574 | NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN); | |
575 | /* Power down output driver with 2 stage */ | |
576 | regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL, | |
577 | NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L, 0); | |
578 | regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL, | |
579 | NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L | | |
580 | NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L, 0); | |
581 | /* Disable clock sync of DAC and DAC clock */ | |
582 | regmap_update_bits(nau8825->regmap, NAU8825_REG_RDAC, | |
583 | NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN, 0); | |
584 | /* Disable charge pump ramp up function and change bump */ | |
585 | regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, | |
586 | NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN, 0); | |
587 | /* Disable power of DAC path */ | |
588 | regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL, | |
589 | NAU8825_ENABLE_DACR | NAU8825_ENABLE_DACL | | |
590 | NAU8825_ENABLE_ADC_CLK | NAU8825_ENABLE_DAC_CLK, 0); | |
591 | if (!nau8825->irq) | |
592 | regmap_update_bits(nau8825->regmap, | |
593 | NAU8825_REG_ENA_CTRL, NAU8825_ENABLE_ADC, 0); | |
594 | } | |
595 | ||
596 | static void nau8825_xtalk_clean_adc(struct nau8825 *nau8825) | |
597 | { | |
598 | /* Power down left ADC and restore voltage to Vmid */ | |
599 | regmap_update_bits(nau8825->regmap, NAU8825_REG_ANALOG_ADC_2, | |
600 | NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_MASK, 0); | |
601 | } | |
602 | ||
fa25b4f5 | 603 | static void nau8825_xtalk_clean(struct nau8825 *nau8825, bool cause_cancel) |
b50455fa JH |
604 | { |
605 | /* Enable internal VCO needed for interruptions */ | |
606 | nau8825_configure_sysclk(nau8825, NAU8825_CLK_INTERNAL, 0); | |
607 | nau8825_xtalk_clean_dac(nau8825); | |
608 | nau8825_xtalk_clean_adc(nau8825); | |
609 | /* Clear cross talk parameters and disable */ | |
610 | regmap_write(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL, 0); | |
611 | /* RMS intrruption disable */ | |
612 | regmap_update_bits(nau8825->regmap, NAU8825_REG_INTERRUPT_MASK, | |
613 | NAU8825_IRQ_RMS_EN, NAU8825_IRQ_RMS_EN); | |
614 | /* Recover default value for IIS */ | |
615 | regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2, | |
a33b56a6 | 616 | NAU8825_I2S_MS_MASK | NAU8825_I2S_LRC_DIV_MASK | |
b50455fa JH |
617 | NAU8825_I2S_BLK_DIV_MASK, NAU8825_I2S_MS_SLAVE); |
618 | /* Restore value of specific register for cross talk */ | |
fa25b4f5 | 619 | nau8825_xtalk_restore(nau8825, cause_cancel); |
b50455fa JH |
620 | } |
621 | ||
622 | static void nau8825_xtalk_imm_start(struct nau8825 *nau8825, int vol) | |
623 | { | |
624 | /* Apply ADC volume for better cross talk performance */ | |
625 | regmap_update_bits(nau8825->regmap, NAU8825_REG_ADC_DGAIN_CTRL, | |
626 | NAU8825_ADC_DIG_VOL_MASK, vol); | |
627 | /* Disables JKTIP(HPL) DAC channel for right to left measurement. | |
628 | * Do it before sending signal in order to erase pop noise. | |
629 | */ | |
630 | regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ, | |
631 | NAU8825_BIAS_TESTDACR_EN | NAU8825_BIAS_TESTDACL_EN, | |
632 | NAU8825_BIAS_TESTDACL_EN); | |
633 | switch (nau8825->xtalk_state) { | |
634 | case NAU8825_XTALK_HPR_R2L: | |
635 | /* Enable right headphone impedance */ | |
636 | regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ, | |
637 | NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP, | |
638 | NAU8825_BIAS_HPR_IMP); | |
639 | break; | |
640 | case NAU8825_XTALK_HPL_R2L: | |
641 | /* Enable left headphone impedance */ | |
642 | regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ, | |
643 | NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP, | |
644 | NAU8825_BIAS_HPL_IMP); | |
645 | break; | |
646 | default: | |
647 | break; | |
648 | } | |
649 | msleep(100); | |
650 | /* Impedance measurement mode enable */ | |
651 | regmap_update_bits(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL, | |
652 | NAU8825_IMM_EN, NAU8825_IMM_EN); | |
653 | } | |
654 | ||
655 | static void nau8825_xtalk_imm_stop(struct nau8825 *nau8825) | |
656 | { | |
657 | /* Impedance measurement mode disable */ | |
658 | regmap_update_bits(nau8825->regmap, | |
659 | NAU8825_REG_IMM_MODE_CTRL, NAU8825_IMM_EN, 0); | |
660 | } | |
661 | ||
662 | /* The cross talk measurement function can reduce cross talk across the | |
663 | * JKTIP(HPL) and JKR1(HPR) outputs which measures the cross talk signal | |
664 | * level to determine what cross talk reduction gain is. This system works by | |
665 | * sending a 23Hz -24dBV sine wave into the headset output DAC and through | |
666 | * the PGA. The output of the PGA is then connected to an internal current | |
667 | * sense which measures the attenuated 23Hz signal and passing the output to | |
668 | * an ADC which converts the measurement to a binary code. With two separated | |
669 | * measurement, one for JKR1(HPR) and the other JKTIP(HPL), measurement data | |
670 | * can be separated read in IMM_RMS_L for HSR and HSL after each measurement. | |
671 | * Thus, the measurement function has four states to complete whole sequence. | |
672 | * 1. Prepare state : Prepare the resource for detection and transfer to HPR | |
673 | * IMM stat to make JKR1(HPR) impedance measure. | |
674 | * 2. HPR IMM state : Read out orignal signal level of JKR1(HPR) and transfer | |
675 | * to HPL IMM state to make JKTIP(HPL) impedance measure. | |
676 | * 3. HPL IMM state : Read out cross talk signal level of JKTIP(HPL) and | |
677 | * transfer to IMM state to determine suppression sidetone gain. | |
678 | * 4. IMM state : Computes cross talk suppression sidetone gain with orignal | |
679 | * and cross talk signal level. Apply this gain and then restore codec | |
680 | * configuration. Then transfer to Done state for ending. | |
681 | */ | |
682 | static void nau8825_xtalk_measure(struct nau8825 *nau8825) | |
683 | { | |
684 | u32 sidetone; | |
685 | ||
686 | switch (nau8825->xtalk_state) { | |
687 | case NAU8825_XTALK_PREPARE: | |
688 | /* In prepare state, set up clock, intrruption, DAC path, ADC | |
689 | * path and cross talk detection parameters for preparation. | |
690 | */ | |
691 | nau8825_xtalk_prepare(nau8825); | |
692 | msleep(280); | |
693 | /* Trigger right headphone impedance detection */ | |
694 | nau8825->xtalk_state = NAU8825_XTALK_HPR_R2L; | |
695 | nau8825_xtalk_imm_start(nau8825, 0x00d2); | |
696 | break; | |
697 | case NAU8825_XTALK_HPR_R2L: | |
698 | /* In right headphone IMM state, read out right headphone | |
699 | * impedance measure result, and then start up left side. | |
700 | */ | |
701 | regmap_read(nau8825->regmap, NAU8825_REG_IMM_RMS_L, | |
702 | &nau8825->imp_rms[NAU8825_XTALK_HPR_R2L]); | |
703 | dev_dbg(nau8825->dev, "HPR_R2L imm: %x\n", | |
704 | nau8825->imp_rms[NAU8825_XTALK_HPR_R2L]); | |
705 | /* Disable then re-enable IMM mode to update */ | |
706 | nau8825_xtalk_imm_stop(nau8825); | |
707 | /* Trigger left headphone impedance detection */ | |
708 | nau8825->xtalk_state = NAU8825_XTALK_HPL_R2L; | |
709 | nau8825_xtalk_imm_start(nau8825, 0x00ff); | |
710 | break; | |
711 | case NAU8825_XTALK_HPL_R2L: | |
712 | /* In left headphone IMM state, read out left headphone | |
713 | * impedance measure result, and delay some time to wait | |
714 | * detection sine wave output finish. Then, we can calculate | |
715 | * the cross talk suppresstion side tone according to the L/R | |
716 | * headphone imedance. | |
717 | */ | |
718 | regmap_read(nau8825->regmap, NAU8825_REG_IMM_RMS_L, | |
719 | &nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]); | |
720 | dev_dbg(nau8825->dev, "HPL_R2L imm: %x\n", | |
721 | nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]); | |
722 | nau8825_xtalk_imm_stop(nau8825); | |
723 | msleep(150); | |
724 | nau8825->xtalk_state = NAU8825_XTALK_IMM; | |
725 | break; | |
726 | case NAU8825_XTALK_IMM: | |
727 | /* In impedance measure state, the orignal and cross talk | |
728 | * signal level vlues are ready. The side tone gain is deter- | |
729 | * mined with these signal level. After all, restore codec | |
730 | * configuration. | |
731 | */ | |
732 | sidetone = nau8825_xtalk_sidetone( | |
733 | nau8825->imp_rms[NAU8825_XTALK_HPR_R2L], | |
734 | nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]); | |
735 | dev_dbg(nau8825->dev, "cross talk sidetone: %x\n", sidetone); | |
736 | regmap_write(nau8825->regmap, NAU8825_REG_DAC_DGAIN_CTRL, | |
737 | (sidetone << 8) | sidetone); | |
fa25b4f5 | 738 | nau8825_xtalk_clean(nau8825, false); |
b50455fa JH |
739 | nau8825->xtalk_state = NAU8825_XTALK_DONE; |
740 | break; | |
741 | default: | |
742 | break; | |
743 | } | |
744 | } | |
745 | ||
746 | static void nau8825_xtalk_work(struct work_struct *work) | |
747 | { | |
748 | struct nau8825 *nau8825 = container_of( | |
749 | work, struct nau8825, xtalk_work); | |
750 | ||
751 | nau8825_xtalk_measure(nau8825); | |
752 | /* To determine the cross talk side tone gain when reach | |
753 | * the impedance measure state. | |
754 | */ | |
755 | if (nau8825->xtalk_state == NAU8825_XTALK_IMM) | |
756 | nau8825_xtalk_measure(nau8825); | |
757 | ||
758 | /* Delay jack report until cross talk detection process | |
759 | * completed. It can avoid application to do playback | |
760 | * preparation before cross talk detection is still working. | |
761 | * Meanwhile, the protection of the cross talk detection | |
762 | * is released. | |
763 | */ | |
764 | if (nau8825->xtalk_state == NAU8825_XTALK_DONE) { | |
765 | snd_soc_jack_report(nau8825->jack, nau8825->xtalk_event, | |
766 | nau8825->xtalk_event_mask); | |
767 | nau8825_sema_release(nau8825); | |
768 | nau8825->xtalk_protect = false; | |
769 | } | |
770 | } | |
771 | ||
772 | static void nau8825_xtalk_cancel(struct nau8825 *nau8825) | |
773 | { | |
226d7449 JH |
774 | /* If the crosstalk is eanbled and the process is on going, |
775 | * the driver forces to cancel the crosstalk task and | |
b50455fa JH |
776 | * restores the configuration to original status. |
777 | */ | |
226d7449 JH |
778 | if (nau8825->xtalk_enable && nau8825->xtalk_state != |
779 | NAU8825_XTALK_DONE) { | |
b50455fa | 780 | cancel_work_sync(&nau8825->xtalk_work); |
fa25b4f5 | 781 | nau8825_xtalk_clean(nau8825, true); |
b50455fa JH |
782 | } |
783 | /* Reset parameters for cross talk suppression function */ | |
784 | nau8825_sema_reset(nau8825); | |
785 | nau8825->xtalk_state = NAU8825_XTALK_DONE; | |
786 | nau8825->xtalk_protect = false; | |
787 | } | |
788 | ||
34ca27f3 AP |
789 | static bool nau8825_readable_reg(struct device *dev, unsigned int reg) |
790 | { | |
791 | switch (reg) { | |
45d5eb3a | 792 | case NAU8825_REG_ENA_CTRL ... NAU8825_REG_FLL_VCO_RSV: |
34ca27f3 AP |
793 | case NAU8825_REG_HSD_CTRL ... NAU8825_REG_JACK_DET_CTRL: |
794 | case NAU8825_REG_INTERRUPT_MASK ... NAU8825_REG_KEYDET_CTRL: | |
795 | case NAU8825_REG_VDET_THRESHOLD_1 ... NAU8825_REG_DACR_CTRL: | |
796 | case NAU8825_REG_ADC_DRC_KNEE_IP12 ... NAU8825_REG_ADC_DRC_ATKDCY: | |
797 | case NAU8825_REG_DAC_DRC_KNEE_IP12 ... NAU8825_REG_DAC_DRC_ATKDCY: | |
798 | case NAU8825_REG_IMM_MODE_CTRL ... NAU8825_REG_IMM_RMS_R: | |
799 | case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL: | |
800 | case NAU8825_REG_MISC_CTRL: | |
b81a2cc9 | 801 | case NAU8825_REG_I2C_DEVICE_ID ... NAU8825_REG_FLL2_UPPER: |
34ca27f3 AP |
802 | case NAU8825_REG_BIAS_ADJ: |
803 | case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2: | |
804 | case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS: | |
805 | case NAU8825_REG_BOOST ... NAU8825_REG_FEPGA: | |
806 | case NAU8825_REG_POWER_UP_CONTROL ... NAU8825_REG_GENERAL_STATUS: | |
807 | return true; | |
808 | default: | |
809 | return false; | |
810 | } | |
811 | ||
812 | } | |
813 | ||
814 | static bool nau8825_writeable_reg(struct device *dev, unsigned int reg) | |
815 | { | |
816 | switch (reg) { | |
45d5eb3a | 817 | case NAU8825_REG_RESET ... NAU8825_REG_FLL_VCO_RSV: |
34ca27f3 AP |
818 | case NAU8825_REG_HSD_CTRL ... NAU8825_REG_JACK_DET_CTRL: |
819 | case NAU8825_REG_INTERRUPT_MASK: | |
820 | case NAU8825_REG_INT_CLR_KEY_STATUS ... NAU8825_REG_KEYDET_CTRL: | |
821 | case NAU8825_REG_VDET_THRESHOLD_1 ... NAU8825_REG_DACR_CTRL: | |
822 | case NAU8825_REG_ADC_DRC_KNEE_IP12 ... NAU8825_REG_ADC_DRC_ATKDCY: | |
823 | case NAU8825_REG_DAC_DRC_KNEE_IP12 ... NAU8825_REG_DAC_DRC_ATKDCY: | |
824 | case NAU8825_REG_IMM_MODE_CTRL: | |
825 | case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL: | |
826 | case NAU8825_REG_MISC_CTRL: | |
b81a2cc9 | 827 | case NAU8825_REG_FLL2_LOWER ... NAU8825_REG_FLL2_UPPER: |
34ca27f3 AP |
828 | case NAU8825_REG_BIAS_ADJ: |
829 | case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2: | |
830 | case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS: | |
831 | case NAU8825_REG_BOOST ... NAU8825_REG_FEPGA: | |
832 | case NAU8825_REG_POWER_UP_CONTROL ... NAU8825_REG_CHARGE_PUMP: | |
833 | return true; | |
834 | default: | |
835 | return false; | |
836 | } | |
837 | } | |
838 | ||
839 | static bool nau8825_volatile_reg(struct device *dev, unsigned int reg) | |
840 | { | |
841 | switch (reg) { | |
842 | case NAU8825_REG_RESET: | |
843 | case NAU8825_REG_IRQ_STATUS: | |
844 | case NAU8825_REG_INT_CLR_KEY_STATUS: | |
845 | case NAU8825_REG_IMM_RMS_L: | |
846 | case NAU8825_REG_IMM_RMS_R: | |
847 | case NAU8825_REG_I2C_DEVICE_ID: | |
848 | case NAU8825_REG_SARDOUT_RAM_STATUS: | |
849 | case NAU8825_REG_CHARGE_PUMP_INPUT_READ: | |
850 | case NAU8825_REG_GENERAL_STATUS: | |
18d8306d | 851 | case NAU8825_REG_BIQ_CTRL ... NAU8825_REG_BIQ_COF10: |
34ca27f3 AP |
852 | return true; |
853 | default: | |
854 | return false; | |
855 | } | |
856 | } | |
857 | ||
f9d790c5 DL |
858 | static int nau8825_fepga_event(struct snd_soc_dapm_widget *w, |
859 | struct snd_kcontrol *kcontrol, int event) | |
860 | { | |
861 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); | |
862 | struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); | |
863 | ||
864 | switch (event) { | |
865 | case SND_SOC_DAPM_POST_PMU: | |
866 | regmap_update_bits(nau8825->regmap, NAU8825_REG_FEPGA, | |
867 | NAU8825_ACDC_CTRL_MASK, | |
868 | NAU8825_ACDC_VREF_MICP | NAU8825_ACDC_VREF_MICN); | |
869 | regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST, | |
870 | NAU8825_DISCHRG_EN, NAU8825_DISCHRG_EN); | |
871 | msleep(40); | |
872 | regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST, | |
873 | NAU8825_DISCHRG_EN, 0); | |
874 | regmap_update_bits(nau8825->regmap, NAU8825_REG_FEPGA, | |
875 | NAU8825_ACDC_CTRL_MASK, 0); | |
876 | break; | |
877 | default: | |
878 | break; | |
879 | } | |
880 | ||
881 | return 0; | |
882 | } | |
883 | ||
eeef16ac JH |
884 | static int nau8825_adc_event(struct snd_soc_dapm_widget *w, |
885 | struct snd_kcontrol *kcontrol, int event) | |
886 | { | |
45101122 KM |
887 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); |
888 | struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); | |
eeef16ac JH |
889 | |
890 | switch (event) { | |
891 | case SND_SOC_DAPM_POST_PMU: | |
fc0b096c | 892 | msleep(nau8825->adc_delay); |
eeef16ac JH |
893 | regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL, |
894 | NAU8825_ENABLE_ADC, NAU8825_ENABLE_ADC); | |
895 | break; | |
896 | case SND_SOC_DAPM_POST_PMD: | |
897 | if (!nau8825->irq) | |
898 | regmap_update_bits(nau8825->regmap, | |
899 | NAU8825_REG_ENA_CTRL, NAU8825_ENABLE_ADC, 0); | |
900 | break; | |
901 | default: | |
902 | return -EINVAL; | |
903 | } | |
904 | ||
905 | return 0; | |
906 | } | |
907 | ||
34ca27f3 AP |
908 | static int nau8825_pump_event(struct snd_soc_dapm_widget *w, |
909 | struct snd_kcontrol *kcontrol, int event) | |
910 | { | |
45101122 KM |
911 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); |
912 | struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); | |
45d5eb3a | 913 | |
34ca27f3 AP |
914 | switch (event) { |
915 | case SND_SOC_DAPM_POST_PMU: | |
916 | /* Prevent startup click by letting charge pump to ramp up */ | |
917 | msleep(10); | |
45d5eb3a JH |
918 | regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, |
919 | NAU8825_JAMNODCLOW, NAU8825_JAMNODCLOW); | |
920 | break; | |
921 | case SND_SOC_DAPM_PRE_PMD: | |
922 | regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, | |
923 | NAU8825_JAMNODCLOW, 0); | |
924 | break; | |
925 | default: | |
926 | return -EINVAL; | |
927 | } | |
928 | ||
929 | return 0; | |
930 | } | |
931 | ||
932 | static int nau8825_output_dac_event(struct snd_soc_dapm_widget *w, | |
933 | struct snd_kcontrol *kcontrol, int event) | |
934 | { | |
45101122 KM |
935 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); |
936 | struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); | |
45d5eb3a JH |
937 | |
938 | switch (event) { | |
939 | case SND_SOC_DAPM_PRE_PMU: | |
940 | /* Disables the TESTDAC to let DAC signal pass through. */ | |
941 | regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ, | |
942 | NAU8825_BIAS_TESTDAC_EN, 0); | |
955b503b DL |
943 | if (nau8825->sw_id == NAU8825_SOFTWARE_ID_NAU8825) |
944 | regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, | |
945 | NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 0); | |
946 | else | |
947 | regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, | |
948 | NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, | |
949 | NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL); | |
45d5eb3a JH |
950 | break; |
951 | case SND_SOC_DAPM_POST_PMD: | |
952 | regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ, | |
953 | NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN); | |
955b503b DL |
954 | if (nau8825->sw_id == NAU8825_SOFTWARE_ID_NAU8825) |
955 | regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, | |
956 | NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, | |
957 | NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL); | |
958 | else | |
959 | regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP, | |
960 | NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 0); | |
961 | ||
34ca27f3 AP |
962 | break; |
963 | default: | |
964 | return -EINVAL; | |
965 | } | |
966 | ||
967 | return 0; | |
968 | } | |
969 | ||
6133148c DL |
970 | static int system_clock_control(struct snd_soc_dapm_widget *w, |
971 | struct snd_kcontrol *k, int event) | |
972 | { | |
973 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); | |
974 | struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); | |
975 | struct regmap *regmap = nau8825->regmap; | |
976 | ||
977 | if (SND_SOC_DAPM_EVENT_OFF(event)) { | |
978 | dev_dbg(nau8825->dev, "system clock control : POWER OFF\n"); | |
979 | /* Set clock source to disable or internal clock before the | |
980 | * playback or capture end. Codec needs clock for Jack | |
981 | * detection and button press if jack inserted; otherwise, | |
982 | * the clock should be closed. | |
983 | */ | |
984 | if (nau8825_is_jack_inserted(regmap)) { | |
985 | nau8825_configure_sysclk(nau8825, | |
986 | NAU8825_CLK_INTERNAL, 0); | |
987 | } else { | |
988 | nau8825_configure_sysclk(nau8825, NAU8825_CLK_DIS, 0); | |
989 | } | |
990 | } | |
991 | ||
992 | return 0; | |
993 | } | |
994 | ||
18d8306d JH |
995 | static int nau8825_biq_coeff_get(struct snd_kcontrol *kcontrol, |
996 | struct snd_ctl_elem_value *ucontrol) | |
997 | { | |
998 | struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); | |
999 | struct soc_bytes_ext *params = (void *)kcontrol->private_value; | |
1000 | ||
1001 | if (!component->regmap) | |
1002 | return -EINVAL; | |
1003 | ||
1004 | regmap_raw_read(component->regmap, NAU8825_REG_BIQ_COF1, | |
1005 | ucontrol->value.bytes.data, params->max); | |
1006 | return 0; | |
1007 | } | |
1008 | ||
1009 | static int nau8825_biq_coeff_put(struct snd_kcontrol *kcontrol, | |
1010 | struct snd_ctl_elem_value *ucontrol) | |
1011 | { | |
1012 | struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); | |
1013 | struct soc_bytes_ext *params = (void *)kcontrol->private_value; | |
1014 | void *data; | |
1015 | ||
1016 | if (!component->regmap) | |
1017 | return -EINVAL; | |
1018 | ||
1019 | data = kmemdup(ucontrol->value.bytes.data, | |
1020 | params->max, GFP_KERNEL | GFP_DMA); | |
1021 | if (!data) | |
1022 | return -ENOMEM; | |
1023 | ||
1024 | regmap_update_bits(component->regmap, NAU8825_REG_BIQ_CTRL, | |
1025 | NAU8825_BIQ_WRT_EN, 0); | |
1026 | regmap_raw_write(component->regmap, NAU8825_REG_BIQ_COF1, | |
1027 | data, params->max); | |
1028 | regmap_update_bits(component->regmap, NAU8825_REG_BIQ_CTRL, | |
1029 | NAU8825_BIQ_WRT_EN, NAU8825_BIQ_WRT_EN); | |
1030 | ||
1031 | kfree(data); | |
1032 | return 0; | |
1033 | } | |
1034 | ||
1035 | static const char * const nau8825_biq_path[] = { | |
1036 | "ADC", "DAC" | |
1037 | }; | |
1038 | ||
1039 | static const struct soc_enum nau8825_biq_path_enum = | |
1040 | SOC_ENUM_SINGLE(NAU8825_REG_BIQ_CTRL, NAU8825_BIQ_PATH_SFT, | |
1041 | ARRAY_SIZE(nau8825_biq_path), nau8825_biq_path); | |
1042 | ||
34ca27f3 AP |
1043 | static const char * const nau8825_adc_decimation[] = { |
1044 | "32", "64", "128", "256" | |
1045 | }; | |
1046 | ||
1047 | static const struct soc_enum nau8825_adc_decimation_enum = | |
1048 | SOC_ENUM_SINGLE(NAU8825_REG_ADC_RATE, NAU8825_ADC_SYNC_DOWN_SFT, | |
1049 | ARRAY_SIZE(nau8825_adc_decimation), nau8825_adc_decimation); | |
1050 | ||
1051 | static const char * const nau8825_dac_oversampl[] = { | |
1052 | "64", "256", "128", "", "32" | |
1053 | }; | |
1054 | ||
1055 | static const struct soc_enum nau8825_dac_oversampl_enum = | |
1056 | SOC_ENUM_SINGLE(NAU8825_REG_DAC_CTRL1, NAU8825_DAC_OVERSAMPLE_SFT, | |
1057 | ARRAY_SIZE(nau8825_dac_oversampl), nau8825_dac_oversampl); | |
1058 | ||
1059 | static const DECLARE_TLV_DB_MINMAX_MUTE(adc_vol_tlv, -10300, 2400); | |
1060 | static const DECLARE_TLV_DB_MINMAX_MUTE(sidetone_vol_tlv, -4200, 0); | |
1061 | static const DECLARE_TLV_DB_MINMAX(dac_vol_tlv, -5400, 0); | |
1062 | static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600); | |
1063 | static const DECLARE_TLV_DB_MINMAX_MUTE(crosstalk_vol_tlv, -9600, 2400); | |
1064 | ||
1065 | static const struct snd_kcontrol_new nau8825_controls[] = { | |
1066 | SOC_SINGLE_TLV("Mic Volume", NAU8825_REG_ADC_DGAIN_CTRL, | |
1067 | 0, 0xff, 0, adc_vol_tlv), | |
1068 | SOC_DOUBLE_TLV("Headphone Bypass Volume", NAU8825_REG_ADC_DGAIN_CTRL, | |
1069 | 12, 8, 0x0f, 0, sidetone_vol_tlv), | |
1070 | SOC_DOUBLE_TLV("Headphone Volume", NAU8825_REG_HSVOL_CTRL, | |
1071 | 6, 0, 0x3f, 1, dac_vol_tlv), | |
1072 | SOC_SINGLE_TLV("Frontend PGA Volume", NAU8825_REG_POWER_UP_CONTROL, | |
1073 | 8, 37, 0, fepga_gain_tlv), | |
1074 | SOC_DOUBLE_TLV("Headphone Crosstalk Volume", NAU8825_REG_DAC_DGAIN_CTRL, | |
1075 | 0, 8, 0xff, 0, crosstalk_vol_tlv), | |
1076 | ||
1077 | SOC_ENUM("ADC Decimation Rate", nau8825_adc_decimation_enum), | |
1078 | SOC_ENUM("DAC Oversampling Rate", nau8825_dac_oversampl_enum), | |
18d8306d JH |
1079 | /* programmable biquad filter */ |
1080 | SOC_ENUM("BIQ Path Select", nau8825_biq_path_enum), | |
0cbeccdf | 1081 | SND_SOC_BYTES_EXT("BIQ Coefficients", 20, |
18d8306d | 1082 | nau8825_biq_coeff_get, nau8825_biq_coeff_put), |
34ca27f3 AP |
1083 | }; |
1084 | ||
1085 | /* DAC Mux 0x33[9] and 0x34[9] */ | |
1086 | static const char * const nau8825_dac_src[] = { | |
1087 | "DACL", "DACR", | |
1088 | }; | |
1089 | ||
1090 | static SOC_ENUM_SINGLE_DECL( | |
1091 | nau8825_dacl_enum, NAU8825_REG_DACL_CTRL, | |
1092 | NAU8825_DACL_CH_SEL_SFT, nau8825_dac_src); | |
1093 | ||
1094 | static SOC_ENUM_SINGLE_DECL( | |
1095 | nau8825_dacr_enum, NAU8825_REG_DACR_CTRL, | |
1096 | NAU8825_DACR_CH_SEL_SFT, nau8825_dac_src); | |
1097 | ||
1098 | static const struct snd_kcontrol_new nau8825_dacl_mux = | |
1099 | SOC_DAPM_ENUM("DACL Source", nau8825_dacl_enum); | |
1100 | ||
1101 | static const struct snd_kcontrol_new nau8825_dacr_mux = | |
1102 | SOC_DAPM_ENUM("DACR Source", nau8825_dacr_enum); | |
1103 | ||
1104 | ||
1105 | static const struct snd_soc_dapm_widget nau8825_dapm_widgets[] = { | |
1106 | SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, NAU8825_REG_I2S_PCM_CTRL2, | |
1107 | 15, 1), | |
6133148c DL |
1108 | SND_SOC_DAPM_AIF_IN("AIFRX", "Playback", 0, SND_SOC_NOPM, 0, 0), |
1109 | SND_SOC_DAPM_SUPPLY("System Clock", SND_SOC_NOPM, 0, 0, | |
1110 | system_clock_control, SND_SOC_DAPM_POST_PMD), | |
34ca27f3 AP |
1111 | |
1112 | SND_SOC_DAPM_INPUT("MIC"), | |
1113 | SND_SOC_DAPM_MICBIAS("MICBIAS", NAU8825_REG_MIC_BIAS, 8, 0), | |
1114 | ||
f9d790c5 DL |
1115 | SND_SOC_DAPM_PGA_E("Frontend PGA", NAU8825_REG_POWER_UP_CONTROL, 14, 0, |
1116 | NULL, 0, nau8825_fepga_event, SND_SOC_DAPM_POST_PMU), | |
34ca27f3 | 1117 | |
eeef16ac JH |
1118 | SND_SOC_DAPM_ADC_E("ADC", NULL, SND_SOC_NOPM, 0, 0, |
1119 | nau8825_adc_event, SND_SOC_DAPM_POST_PMU | | |
1120 | SND_SOC_DAPM_POST_PMD), | |
34ca27f3 AP |
1121 | SND_SOC_DAPM_SUPPLY("ADC Clock", NAU8825_REG_ENA_CTRL, 7, 0, NULL, 0), |
1122 | SND_SOC_DAPM_SUPPLY("ADC Power", NAU8825_REG_ANALOG_ADC_2, 6, 0, NULL, | |
1123 | 0), | |
1124 | ||
e6cee900 BZ |
1125 | /* ADC for button press detection. A dapm supply widget is used to |
1126 | * prevent dapm_power_widgets keeping the codec at SND_SOC_BIAS_ON | |
1127 | * during suspend. | |
1128 | */ | |
1129 | SND_SOC_DAPM_SUPPLY("SAR", NAU8825_REG_SAR_CTRL, | |
1130 | NAU8825_SAR_ADC_EN_SFT, 0, NULL, 0), | |
34ca27f3 | 1131 | |
45d5eb3a JH |
1132 | SND_SOC_DAPM_PGA_S("ADACL", 2, NAU8825_REG_RDAC, 12, 0, NULL, 0), |
1133 | SND_SOC_DAPM_PGA_S("ADACR", 2, NAU8825_REG_RDAC, 13, 0, NULL, 0), | |
1134 | SND_SOC_DAPM_PGA_S("ADACL Clock", 3, NAU8825_REG_RDAC, 8, 0, NULL, 0), | |
1135 | SND_SOC_DAPM_PGA_S("ADACR Clock", 3, NAU8825_REG_RDAC, 9, 0, NULL, 0), | |
34ca27f3 AP |
1136 | |
1137 | SND_SOC_DAPM_DAC("DDACR", NULL, NAU8825_REG_ENA_CTRL, | |
1138 | NAU8825_ENABLE_DACR_SFT, 0), | |
1139 | SND_SOC_DAPM_DAC("DDACL", NULL, NAU8825_REG_ENA_CTRL, | |
1140 | NAU8825_ENABLE_DACL_SFT, 0), | |
1141 | SND_SOC_DAPM_SUPPLY("DDAC Clock", NAU8825_REG_ENA_CTRL, 6, 0, NULL, 0), | |
1142 | ||
1143 | SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &nau8825_dacl_mux), | |
1144 | SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &nau8825_dacr_mux), | |
1145 | ||
45d5eb3a JH |
1146 | SND_SOC_DAPM_PGA_S("HP amp L", 0, |
1147 | NAU8825_REG_CLASSG_CTRL, 1, 0, NULL, 0), | |
1148 | SND_SOC_DAPM_PGA_S("HP amp R", 0, | |
1149 | NAU8825_REG_CLASSG_CTRL, 2, 0, NULL, 0), | |
34ca27f3 | 1150 | |
45d5eb3a JH |
1151 | SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8825_REG_CHARGE_PUMP, 5, 0, |
1152 | nau8825_pump_event, SND_SOC_DAPM_POST_PMU | | |
1153 | SND_SOC_DAPM_PRE_PMD), | |
34ca27f3 | 1154 | |
45d5eb3a | 1155 | SND_SOC_DAPM_PGA_S("Output Driver R Stage 1", 4, |
34ca27f3 | 1156 | NAU8825_REG_POWER_UP_CONTROL, 5, 0, NULL, 0), |
45d5eb3a | 1157 | SND_SOC_DAPM_PGA_S("Output Driver L Stage 1", 4, |
34ca27f3 | 1158 | NAU8825_REG_POWER_UP_CONTROL, 4, 0, NULL, 0), |
45d5eb3a | 1159 | SND_SOC_DAPM_PGA_S("Output Driver R Stage 2", 5, |
34ca27f3 | 1160 | NAU8825_REG_POWER_UP_CONTROL, 3, 0, NULL, 0), |
45d5eb3a | 1161 | SND_SOC_DAPM_PGA_S("Output Driver L Stage 2", 5, |
34ca27f3 | 1162 | NAU8825_REG_POWER_UP_CONTROL, 2, 0, NULL, 0), |
45d5eb3a | 1163 | SND_SOC_DAPM_PGA_S("Output Driver R Stage 3", 6, |
34ca27f3 | 1164 | NAU8825_REG_POWER_UP_CONTROL, 1, 0, NULL, 0), |
45d5eb3a | 1165 | SND_SOC_DAPM_PGA_S("Output Driver L Stage 3", 6, |
34ca27f3 AP |
1166 | NAU8825_REG_POWER_UP_CONTROL, 0, 0, NULL, 0), |
1167 | ||
45d5eb3a | 1168 | SND_SOC_DAPM_PGA_S("Output DACL", 7, |
955b503b | 1169 | SND_SOC_NOPM, 0, 0, nau8825_output_dac_event, |
45d5eb3a JH |
1170 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
1171 | SND_SOC_DAPM_PGA_S("Output DACR", 7, | |
955b503b | 1172 | SND_SOC_NOPM, 0, 0, nau8825_output_dac_event, |
45d5eb3a JH |
1173 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
1174 | ||
955b503b | 1175 | |
45d5eb3a JH |
1176 | /* HPOL/R are ungrounded by disabling 16 Ohm pull-downs on playback */ |
1177 | SND_SOC_DAPM_PGA_S("HPOL Pulldown", 8, | |
1178 | NAU8825_REG_HSD_CTRL, 0, 1, NULL, 0), | |
1179 | SND_SOC_DAPM_PGA_S("HPOR Pulldown", 8, | |
1180 | NAU8825_REG_HSD_CTRL, 1, 1, NULL, 0), | |
1181 | ||
1182 | /* High current HPOL/R boost driver */ | |
1183 | SND_SOC_DAPM_PGA_S("HP Boost Driver", 9, | |
1184 | NAU8825_REG_BOOST, 9, 1, NULL, 0), | |
1185 | ||
1186 | /* Class G operation control*/ | |
1187 | SND_SOC_DAPM_PGA_S("Class G", 10, | |
1188 | NAU8825_REG_CLASSG_CTRL, 0, 0, NULL, 0), | |
34ca27f3 AP |
1189 | |
1190 | SND_SOC_DAPM_OUTPUT("HPOL"), | |
1191 | SND_SOC_DAPM_OUTPUT("HPOR"), | |
1192 | }; | |
1193 | ||
1194 | static const struct snd_soc_dapm_route nau8825_dapm_routes[] = { | |
1195 | {"Frontend PGA", NULL, "MIC"}, | |
1196 | {"ADC", NULL, "Frontend PGA"}, | |
1197 | {"ADC", NULL, "ADC Clock"}, | |
1198 | {"ADC", NULL, "ADC Power"}, | |
1199 | {"AIFTX", NULL, "ADC"}, | |
6133148c | 1200 | {"AIFTX", NULL, "System Clock"}, |
34ca27f3 | 1201 | |
6133148c DL |
1202 | {"AIFRX", NULL, "System Clock"}, |
1203 | {"DDACL", NULL, "AIFRX"}, | |
1204 | {"DDACR", NULL, "AIFRX"}, | |
34ca27f3 AP |
1205 | {"DDACL", NULL, "DDAC Clock"}, |
1206 | {"DDACR", NULL, "DDAC Clock"}, | |
1207 | {"DACL Mux", "DACL", "DDACL"}, | |
1208 | {"DACL Mux", "DACR", "DDACR"}, | |
1209 | {"DACR Mux", "DACL", "DDACL"}, | |
1210 | {"DACR Mux", "DACR", "DDACR"}, | |
1211 | {"HP amp L", NULL, "DACL Mux"}, | |
1212 | {"HP amp R", NULL, "DACR Mux"}, | |
45d5eb3a JH |
1213 | {"Charge Pump", NULL, "HP amp L"}, |
1214 | {"Charge Pump", NULL, "HP amp R"}, | |
1215 | {"ADACL", NULL, "Charge Pump"}, | |
1216 | {"ADACR", NULL, "Charge Pump"}, | |
1217 | {"ADACL Clock", NULL, "ADACL"}, | |
1218 | {"ADACR Clock", NULL, "ADACR"}, | |
1219 | {"Output Driver L Stage 1", NULL, "ADACL Clock"}, | |
1220 | {"Output Driver R Stage 1", NULL, "ADACR Clock"}, | |
34ca27f3 AP |
1221 | {"Output Driver L Stage 2", NULL, "Output Driver L Stage 1"}, |
1222 | {"Output Driver R Stage 2", NULL, "Output Driver R Stage 1"}, | |
1223 | {"Output Driver L Stage 3", NULL, "Output Driver L Stage 2"}, | |
1224 | {"Output Driver R Stage 3", NULL, "Output Driver R Stage 2"}, | |
1225 | {"Output DACL", NULL, "Output Driver L Stage 3"}, | |
1226 | {"Output DACR", NULL, "Output Driver R Stage 3"}, | |
45d5eb3a JH |
1227 | {"HPOL Pulldown", NULL, "Output DACL"}, |
1228 | {"HPOR Pulldown", NULL, "Output DACR"}, | |
1229 | {"HP Boost Driver", NULL, "HPOL Pulldown"}, | |
1230 | {"HP Boost Driver", NULL, "HPOR Pulldown"}, | |
1231 | {"Class G", NULL, "HP Boost Driver"}, | |
1232 | {"HPOL", NULL, "Class G"}, | |
1233 | {"HPOR", NULL, "Class G"}, | |
34ca27f3 AP |
1234 | }; |
1235 | ||
bed41de0 TI |
1236 | static const struct nau8825_osr_attr * |
1237 | nau8825_get_osr(struct nau8825 *nau8825, int stream) | |
d6d19745 | 1238 | { |
bed41de0 | 1239 | unsigned int osr; |
d6d19745 JH |
1240 | |
1241 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
bed41de0 TI |
1242 | regmap_read(nau8825->regmap, |
1243 | NAU8825_REG_DAC_CTRL1, &osr); | |
1244 | osr &= NAU8825_DAC_OVERSAMPLE_MASK; | |
d6d19745 | 1245 | if (osr >= ARRAY_SIZE(osr_dac_sel)) |
bed41de0 TI |
1246 | return NULL; |
1247 | return &osr_dac_sel[osr]; | |
d6d19745 | 1248 | } else { |
bed41de0 TI |
1249 | regmap_read(nau8825->regmap, |
1250 | NAU8825_REG_ADC_RATE, &osr); | |
1251 | osr &= NAU8825_ADC_SYNC_DOWN_MASK; | |
d6d19745 | 1252 | if (osr >= ARRAY_SIZE(osr_adc_sel)) |
bed41de0 TI |
1253 | return NULL; |
1254 | return &osr_adc_sel[osr]; | |
d6d19745 | 1255 | } |
bed41de0 | 1256 | } |
d6d19745 | 1257 | |
bed41de0 TI |
1258 | static int nau8825_dai_startup(struct snd_pcm_substream *substream, |
1259 | struct snd_soc_dai *dai) | |
1260 | { | |
1261 | struct snd_soc_component *component = dai->component; | |
1262 | struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); | |
1263 | const struct nau8825_osr_attr *osr; | |
1264 | ||
1265 | osr = nau8825_get_osr(nau8825, substream->stream); | |
1266 | if (!osr || !osr->osr) | |
d6d19745 | 1267 | return -EINVAL; |
d6d19745 | 1268 | |
bed41de0 TI |
1269 | return snd_pcm_hw_constraint_minmax(substream->runtime, |
1270 | SNDRV_PCM_HW_PARAM_RATE, | |
1271 | 0, CLK_DA_AD_MAX / osr->osr); | |
d6d19745 JH |
1272 | } |
1273 | ||
34ca27f3 AP |
1274 | static int nau8825_hw_params(struct snd_pcm_substream *substream, |
1275 | struct snd_pcm_hw_params *params, | |
1276 | struct snd_soc_dai *dai) | |
1277 | { | |
45101122 KM |
1278 | struct snd_soc_component *component = dai->component; |
1279 | struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); | |
bed41de0 TI |
1280 | unsigned int val_len = 0, ctrl_val, bclk_fs, bclk_div; |
1281 | const struct nau8825_osr_attr *osr; | |
1282 | int err = -EINVAL; | |
34ca27f3 | 1283 | |
2263fddc | 1284 | nau8825_sema_acquire(nau8825, 3 * HZ); |
ca6ac305 | 1285 | |
d6d19745 JH |
1286 | /* CLK_DAC or CLK_ADC = OSR * FS |
1287 | * DAC or ADC clock frequency is defined as Over Sampling Rate (OSR) | |
1288 | * multiplied by the audio sample rate (Fs). Note that the OSR and Fs | |
1289 | * values must be selected such that the maximum frequency is less | |
1290 | * than 6.144 MHz. | |
1291 | */ | |
bed41de0 TI |
1292 | osr = nau8825_get_osr(nau8825, substream->stream); |
1293 | if (!osr || !osr->osr) | |
1294 | goto error; | |
1295 | if (params_rate(params) * osr->osr > CLK_DA_AD_MAX) | |
1296 | goto error; | |
1297 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
d6d19745 JH |
1298 | regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER, |
1299 | NAU8825_CLK_DAC_SRC_MASK, | |
bed41de0 TI |
1300 | osr->clk_src << NAU8825_CLK_DAC_SRC_SFT); |
1301 | else | |
d6d19745 JH |
1302 | regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER, |
1303 | NAU8825_CLK_ADC_SRC_MASK, | |
bed41de0 | 1304 | osr->clk_src << NAU8825_CLK_ADC_SRC_SFT); |
d6d19745 | 1305 | |
1e561f61 JH |
1306 | /* make BCLK and LRC divde configuration if the codec as master. */ |
1307 | regmap_read(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2, &ctrl_val); | |
1308 | if (ctrl_val & NAU8825_I2S_MS_MASTER) { | |
1309 | /* get the bclk and fs ratio */ | |
1310 | bclk_fs = snd_soc_params_to_bclk(params) / params_rate(params); | |
1311 | if (bclk_fs <= 32) | |
1312 | bclk_div = 2; | |
1313 | else if (bclk_fs <= 64) | |
1314 | bclk_div = 1; | |
1315 | else if (bclk_fs <= 128) | |
1316 | bclk_div = 0; | |
bed41de0 TI |
1317 | else |
1318 | goto error; | |
1e561f61 JH |
1319 | regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2, |
1320 | NAU8825_I2S_LRC_DIV_MASK | NAU8825_I2S_BLK_DIV_MASK, | |
1321 | ((bclk_div + 1) << NAU8825_I2S_LRC_DIV_SFT) | bclk_div); | |
1322 | } | |
1323 | ||
34ca27f3 AP |
1324 | switch (params_width(params)) { |
1325 | case 16: | |
1326 | val_len |= NAU8825_I2S_DL_16; | |
1327 | break; | |
1328 | case 20: | |
1329 | val_len |= NAU8825_I2S_DL_20; | |
1330 | break; | |
1331 | case 24: | |
1332 | val_len |= NAU8825_I2S_DL_24; | |
1333 | break; | |
1334 | case 32: | |
1335 | val_len |= NAU8825_I2S_DL_32; | |
1336 | break; | |
1337 | default: | |
bed41de0 | 1338 | goto error; |
34ca27f3 AP |
1339 | } |
1340 | ||
1341 | regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1, | |
1342 | NAU8825_I2S_DL_MASK, val_len); | |
bed41de0 | 1343 | err = 0; |
34ca27f3 | 1344 | |
bed41de0 | 1345 | error: |
3dfcd346 | 1346 | /* Release the semaphore. */ |
ca6ac305 JH |
1347 | nau8825_sema_release(nau8825); |
1348 | ||
bed41de0 | 1349 | return err; |
34ca27f3 AP |
1350 | } |
1351 | ||
1352 | static int nau8825_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) | |
1353 | { | |
45101122 KM |
1354 | struct snd_soc_component *component = codec_dai->component; |
1355 | struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); | |
34ca27f3 AP |
1356 | unsigned int ctrl1_val = 0, ctrl2_val = 0; |
1357 | ||
1358 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1359 | case SND_SOC_DAIFMT_CBM_CFM: | |
1360 | ctrl2_val |= NAU8825_I2S_MS_MASTER; | |
1361 | break; | |
1362 | case SND_SOC_DAIFMT_CBS_CFS: | |
1363 | break; | |
1364 | default: | |
1365 | return -EINVAL; | |
1366 | } | |
1367 | ||
1368 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1369 | case SND_SOC_DAIFMT_NB_NF: | |
1370 | break; | |
1371 | case SND_SOC_DAIFMT_IB_NF: | |
1372 | ctrl1_val |= NAU8825_I2S_BP_INV; | |
1373 | break; | |
1374 | default: | |
1375 | return -EINVAL; | |
1376 | } | |
1377 | ||
1378 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1379 | case SND_SOC_DAIFMT_I2S: | |
1380 | ctrl1_val |= NAU8825_I2S_DF_I2S; | |
1381 | break; | |
1382 | case SND_SOC_DAIFMT_LEFT_J: | |
1383 | ctrl1_val |= NAU8825_I2S_DF_LEFT; | |
1384 | break; | |
1385 | case SND_SOC_DAIFMT_RIGHT_J: | |
1386 | ctrl1_val |= NAU8825_I2S_DF_RIGTH; | |
1387 | break; | |
1388 | case SND_SOC_DAIFMT_DSP_A: | |
1389 | ctrl1_val |= NAU8825_I2S_DF_PCM_AB; | |
1390 | break; | |
1391 | case SND_SOC_DAIFMT_DSP_B: | |
1392 | ctrl1_val |= NAU8825_I2S_DF_PCM_AB; | |
1393 | ctrl1_val |= NAU8825_I2S_PCMB_EN; | |
1394 | break; | |
1395 | default: | |
1396 | return -EINVAL; | |
1397 | } | |
1398 | ||
70424d8e JH |
1399 | nau8825_sema_acquire(nau8825, 3 * HZ); |
1400 | ||
34ca27f3 AP |
1401 | regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1, |
1402 | NAU8825_I2S_DL_MASK | NAU8825_I2S_DF_MASK | | |
1403 | NAU8825_I2S_BP_MASK | NAU8825_I2S_PCMB_MASK, | |
1404 | ctrl1_val); | |
1405 | regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2, | |
1406 | NAU8825_I2S_MS_MASK, ctrl2_val); | |
1407 | ||
3dfcd346 | 1408 | /* Release the semaphore. */ |
ca6ac305 JH |
1409 | nau8825_sema_release(nau8825); |
1410 | ||
34ca27f3 AP |
1411 | return 0; |
1412 | } | |
1413 | ||
dacdef1b DL |
1414 | /** |
1415 | * nau8825_set_tdm_slot - configure DAI TDM. | |
1416 | * @dai: DAI | |
1417 | * @tx_mask: bitmask representing active TX slots. | |
1418 | * @rx_mask: bitmask representing active RX slots. | |
1419 | * @slots: Number of slots in use. | |
1420 | * @slot_width: Width in bits for each slot. | |
1421 | * | |
1422 | * Configures a DAI for TDM operation. Support TDM 4/8 slots. | |
1423 | * The limitation is DAC and ADC need shift 4 slots at 8 slots mode. | |
1424 | */ | |
1425 | static int nau8825_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, | |
1426 | unsigned int rx_mask, int slots, int slot_width) | |
1427 | { | |
1428 | struct snd_soc_component *component = dai->component; | |
1429 | struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); | |
1430 | unsigned int ctrl_val = 0, ctrl_offset = 0, value = 0, dac_s, adc_s; | |
1431 | ||
1432 | if (slots != 4 && slots != 8) { | |
1433 | dev_err(nau8825->dev, "Only support 4 or 8 slots!\n"); | |
1434 | return -EINVAL; | |
1435 | } | |
1436 | ||
1437 | /* The driver is limited to 1-channel for ADC, and 2-channel for DAC on TDM mode */ | |
1438 | if (hweight_long((unsigned long) tx_mask) != 1 || | |
1439 | hweight_long((unsigned long) rx_mask) != 2) { | |
1440 | dev_err(nau8825->dev, | |
1441 | "The limitation is 1-channel for ADC, and 2-channel for DAC on TDM mode.\n"); | |
1442 | return -EINVAL; | |
1443 | } | |
1444 | ||
1445 | if (((tx_mask & 0xf) && (tx_mask & 0xf0)) || | |
1446 | ((rx_mask & 0xf) && (rx_mask & 0xf0)) || | |
1447 | ((tx_mask & 0xf) && (rx_mask & 0xf0)) || | |
1448 | ((rx_mask & 0xf) && (tx_mask & 0xf0))) { | |
1449 | dev_err(nau8825->dev, | |
1450 | "Slot assignment of DAC and ADC need to set same interval.\n"); | |
1451 | return -EINVAL; | |
1452 | } | |
1453 | ||
1454 | /* The offset of fixed 4 slots for 8 slots support */ | |
1455 | if (rx_mask & 0xf0) { | |
1456 | regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2, | |
1457 | NAU8825_I2S_PCM_TS_EN_MASK, NAU8825_I2S_PCM_TS_EN); | |
1458 | regmap_read(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1, &value); | |
1459 | ctrl_val |= NAU8825_TDM_OFFSET_EN; | |
1460 | ctrl_offset = 4 * slot_width; | |
1461 | if (!(value & NAU8825_I2S_PCMB_MASK)) | |
1462 | ctrl_offset += 1; | |
1463 | dac_s = (rx_mask & 0xf0) >> 4; | |
1464 | adc_s = fls((tx_mask & 0xf0) >> 4); | |
1465 | } else { | |
1466 | dac_s = rx_mask & 0xf; | |
1467 | adc_s = fls(tx_mask & 0xf); | |
1468 | } | |
1469 | ||
1470 | ctrl_val |= NAU8825_TDM_MODE; | |
1471 | ||
1472 | switch (dac_s) { | |
1473 | case 0x3: | |
1474 | ctrl_val |= 1 << NAU8825_TDM_DACR_RX_SFT; | |
1475 | break; | |
1476 | case 0x5: | |
1477 | ctrl_val |= 2 << NAU8825_TDM_DACR_RX_SFT; | |
1478 | break; | |
1479 | case 0x6: | |
1480 | ctrl_val |= 1 << NAU8825_TDM_DACL_RX_SFT; | |
1481 | ctrl_val |= 2 << NAU8825_TDM_DACR_RX_SFT; | |
1482 | break; | |
1483 | case 0x9: | |
1484 | ctrl_val |= 3 << NAU8825_TDM_DACR_RX_SFT; | |
1485 | break; | |
1486 | case 0xa: | |
1487 | ctrl_val |= 1 << NAU8825_TDM_DACL_RX_SFT; | |
1488 | ctrl_val |= 3 << NAU8825_TDM_DACR_RX_SFT; | |
1489 | break; | |
1490 | case 0xc: | |
1491 | ctrl_val |= 2 << NAU8825_TDM_DACL_RX_SFT; | |
1492 | ctrl_val |= 3 << NAU8825_TDM_DACR_RX_SFT; | |
1493 | break; | |
1494 | default: | |
1495 | return -EINVAL; | |
1496 | } | |
1497 | ||
1498 | ctrl_val |= adc_s - 1; | |
1499 | ||
1500 | regmap_update_bits(nau8825->regmap, NAU8825_REG_TDM_CTRL, | |
1501 | NAU8825_TDM_MODE | NAU8825_TDM_OFFSET_EN | | |
1502 | NAU8825_TDM_DACL_RX_MASK | NAU8825_TDM_DACR_RX_MASK | | |
1503 | NAU8825_TDM_TX_MASK, ctrl_val); | |
1504 | regmap_update_bits(nau8825->regmap, NAU8825_REG_LEFT_TIME_SLOT, | |
1505 | NAU8825_TSLOT_L0_MASK, ctrl_offset); | |
1506 | ||
1507 | return 0; | |
1508 | } | |
1509 | ||
34ca27f3 | 1510 | static const struct snd_soc_dai_ops nau8825_dai_ops = { |
bed41de0 | 1511 | .startup = nau8825_dai_startup, |
34ca27f3 AP |
1512 | .hw_params = nau8825_hw_params, |
1513 | .set_fmt = nau8825_set_dai_fmt, | |
dacdef1b | 1514 | .set_tdm_slot = nau8825_set_tdm_slot, |
34ca27f3 AP |
1515 | }; |
1516 | ||
1517 | #define NAU8825_RATES SNDRV_PCM_RATE_8000_192000 | |
1518 | #define NAU8825_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ | |
1519 | | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) | |
1520 | ||
1521 | static struct snd_soc_dai_driver nau8825_dai = { | |
1522 | .name = "nau8825-hifi", | |
1523 | .playback = { | |
1524 | .stream_name = "Playback", | |
1525 | .channels_min = 1, | |
1526 | .channels_max = 2, | |
1527 | .rates = NAU8825_RATES, | |
1528 | .formats = NAU8825_FORMATS, | |
1529 | }, | |
1530 | .capture = { | |
1531 | .stream_name = "Capture", | |
1532 | .channels_min = 1, | |
0ca3d2ba | 1533 | .channels_max = 2, /* Only 1 channel of data */ |
34ca27f3 AP |
1534 | .rates = NAU8825_RATES, |
1535 | .formats = NAU8825_FORMATS, | |
1536 | }, | |
1537 | .ops = &nau8825_dai_ops, | |
1538 | }; | |
1539 | ||
1540 | /** | |
1541 | * nau8825_enable_jack_detect - Specify a jack for event reporting | |
1542 | * | |
1543 | * @component: component to register the jack with | |
1544 | * @jack: jack to use to report headset and button events on | |
1545 | * | |
1546 | * After this function has been called the headset insert/remove and button | |
1547 | * events will be routed to the given jack. Jack can be null to stop | |
1548 | * reporting. | |
1549 | */ | |
45101122 | 1550 | int nau8825_enable_jack_detect(struct snd_soc_component *component, |
34ca27f3 AP |
1551 | struct snd_soc_jack *jack) |
1552 | { | |
45101122 | 1553 | struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); |
34ca27f3 AP |
1554 | struct regmap *regmap = nau8825->regmap; |
1555 | ||
1556 | nau8825->jack = jack; | |
1557 | ||
c6167e10 DL |
1558 | if (!nau8825->jack) { |
1559 | regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, | |
1560 | NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | | |
1561 | NAU8825_SPKR_DWN1L, 0); | |
1562 | return 0; | |
1563 | } | |
34ca27f3 AP |
1564 | /* Ground HP Outputs[1:0], needed for headset auto detection |
1565 | * Enable Automatic Mic/Gnd switching reading on insert interrupt[6] | |
1566 | */ | |
1567 | regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, | |
1568 | NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L, | |
1569 | NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L); | |
1570 | ||
34ca27f3 AP |
1571 | return 0; |
1572 | } | |
1573 | EXPORT_SYMBOL_GPL(nau8825_enable_jack_detect); | |
1574 | ||
1575 | ||
1576 | static bool nau8825_is_jack_inserted(struct regmap *regmap) | |
1577 | { | |
bff03e81 JH |
1578 | bool active_high, is_high; |
1579 | int status, jkdet; | |
34ca27f3 | 1580 | |
bff03e81 | 1581 | regmap_read(regmap, NAU8825_REG_JACK_DET_CTRL, &jkdet); |
308e3e0b | 1582 | active_high = jkdet & NAU8825_JACK_POLARITY; |
34ca27f3 | 1583 | regmap_read(regmap, NAU8825_REG_I2C_DEVICE_ID, &status); |
308e3e0b | 1584 | is_high = status & NAU8825_GPIO2JD1; |
bff03e81 JH |
1585 | /* return jack connection status according to jack insertion logic |
1586 | * active high or active low. | |
1587 | */ | |
1588 | return active_high == is_high; | |
34ca27f3 AP |
1589 | } |
1590 | ||
1591 | static void nau8825_restart_jack_detection(struct regmap *regmap) | |
1592 | { | |
1593 | /* this will restart the entire jack detection process including MIC/GND | |
1594 | * switching and create interrupts. We have to go from 0 to 1 and back | |
1595 | * to 0 to restart. | |
1596 | */ | |
1597 | regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, | |
1598 | NAU8825_JACK_DET_RESTART, NAU8825_JACK_DET_RESTART); | |
1599 | regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, | |
1600 | NAU8825_JACK_DET_RESTART, 0); | |
1601 | } | |
1602 | ||
2ec30f60 JH |
1603 | static void nau8825_int_status_clear_all(struct regmap *regmap) |
1604 | { | |
1605 | int active_irq, clear_irq, i; | |
1606 | ||
1607 | /* Reset the intrruption status from rightmost bit if the corres- | |
1608 | * ponding irq event occurs. | |
1609 | */ | |
1610 | regmap_read(regmap, NAU8825_REG_IRQ_STATUS, &active_irq); | |
1611 | for (i = 0; i < NAU8825_REG_DATA_LEN; i++) { | |
1612 | clear_irq = (0x1 << i); | |
1613 | if (active_irq & clear_irq) | |
1614 | regmap_write(regmap, | |
1615 | NAU8825_REG_INT_CLR_KEY_STATUS, clear_irq); | |
1616 | } | |
1617 | } | |
1618 | ||
34ca27f3 AP |
1619 | static void nau8825_eject_jack(struct nau8825 *nau8825) |
1620 | { | |
1621 | struct snd_soc_dapm_context *dapm = nau8825->dapm; | |
1622 | struct regmap *regmap = nau8825->regmap; | |
1623 | ||
b50455fa JH |
1624 | /* Force to cancel the cross talk detection process */ |
1625 | nau8825_xtalk_cancel(nau8825); | |
1626 | ||
34ca27f3 AP |
1627 | snd_soc_dapm_disable_pin(dapm, "SAR"); |
1628 | snd_soc_dapm_disable_pin(dapm, "MICBIAS"); | |
1629 | /* Detach 2kOhm Resistors from MICBIAS to MICGND1/2 */ | |
1630 | regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, | |
1631 | NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 0); | |
1632 | /* ground HPL/HPR, MICGRND1/2 */ | |
1633 | regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 0xf, 0xf); | |
1634 | ||
1635 | snd_soc_dapm_sync(dapm); | |
2ec30f60 JH |
1636 | |
1637 | /* Clear all interruption status */ | |
1638 | nau8825_int_status_clear_all(regmap); | |
1639 | ||
1640 | /* Enable the insertion interruption, disable the ejection inter- | |
1641 | * ruption, and then bypass de-bounce circuit. | |
1642 | */ | |
1643 | regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL, | |
1644 | NAU8825_IRQ_EJECT_DIS | NAU8825_IRQ_INSERT_DIS, | |
1645 | NAU8825_IRQ_EJECT_DIS); | |
1646 | regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, | |
1647 | NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_EJECT_EN | | |
1648 | NAU8825_IRQ_HEADSET_COMPLETE_EN | NAU8825_IRQ_INSERT_EN, | |
1649 | NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_EJECT_EN | | |
1650 | NAU8825_IRQ_HEADSET_COMPLETE_EN); | |
1651 | regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, | |
1652 | NAU8825_JACK_DET_DB_BYPASS, NAU8825_JACK_DET_DB_BYPASS); | |
1653 | ||
1654 | /* Disable ADC needed for interruptions at audo mode */ | |
1655 | regmap_update_bits(regmap, NAU8825_REG_ENA_CTRL, | |
1656 | NAU8825_ENABLE_ADC, 0); | |
1657 | ||
1658 | /* Close clock for jack type detection at manual mode */ | |
1659 | nau8825_configure_sysclk(nau8825, NAU8825_CLK_DIS, 0); | |
1660 | } | |
1661 | ||
1662 | /* Enable audo mode interruptions with internal clock. */ | |
1663 | static void nau8825_setup_auto_irq(struct nau8825 *nau8825) | |
1664 | { | |
1665 | struct regmap *regmap = nau8825->regmap; | |
1666 | ||
8315d8ad DL |
1667 | /* Enable HSD function */ |
1668 | regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, | |
1669 | NAU8825_HSD_AUTO_MODE, NAU8825_HSD_AUTO_MODE); | |
1670 | ||
2ec30f60 JH |
1671 | /* Enable headset jack type detection complete interruption and |
1672 | * jack ejection interruption. | |
1673 | */ | |
1674 | regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, | |
1675 | NAU8825_IRQ_HEADSET_COMPLETE_EN | NAU8825_IRQ_EJECT_EN, 0); | |
1676 | ||
1677 | /* Enable internal VCO needed for interruptions */ | |
1678 | nau8825_configure_sysclk(nau8825, NAU8825_CLK_INTERNAL, 0); | |
fa0fb073 DL |
1679 | /* Raise up the internal clock for jack detection */ |
1680 | regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER, | |
1681 | NAU8825_CLK_MCLK_SRC_MASK, 0); | |
2ec30f60 JH |
1682 | |
1683 | /* Enable ADC needed for interruptions */ | |
1684 | regmap_update_bits(regmap, NAU8825_REG_ENA_CTRL, | |
1685 | NAU8825_ENABLE_ADC, NAU8825_ENABLE_ADC); | |
1686 | ||
1687 | /* Chip needs one FSCLK cycle in order to generate interruptions, | |
1688 | * as we cannot guarantee one will be provided by the system. Turning | |
1689 | * master mode on then off enables us to generate that FSCLK cycle | |
1690 | * with a minimum of contention on the clock bus. | |
1691 | */ | |
1692 | regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2, | |
1693 | NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_MASTER); | |
1694 | regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2, | |
1695 | NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_SLAVE); | |
1696 | ||
1697 | /* Not bypass de-bounce circuit */ | |
1698 | regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, | |
1699 | NAU8825_JACK_DET_DB_BYPASS, 0); | |
1700 | ||
1701 | /* Unmask all interruptions */ | |
1702 | regmap_write(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL, 0); | |
1703 | ||
1704 | /* Restart the jack detection process at auto mode */ | |
1705 | nau8825_restart_jack_detection(regmap); | |
34ca27f3 AP |
1706 | } |
1707 | ||
1708 | static int nau8825_button_decode(int value) | |
1709 | { | |
1710 | int buttons = 0; | |
1711 | ||
1712 | /* The chip supports up to 8 buttons, but ALSA defines only 6 buttons */ | |
1713 | if (value & BIT(0)) | |
1714 | buttons |= SND_JACK_BTN_0; | |
1715 | if (value & BIT(1)) | |
1716 | buttons |= SND_JACK_BTN_1; | |
1717 | if (value & BIT(2)) | |
1718 | buttons |= SND_JACK_BTN_2; | |
1719 | if (value & BIT(3)) | |
1720 | buttons |= SND_JACK_BTN_3; | |
1721 | if (value & BIT(4)) | |
1722 | buttons |= SND_JACK_BTN_4; | |
1723 | if (value & BIT(5)) | |
1724 | buttons |= SND_JACK_BTN_5; | |
1725 | ||
1726 | return buttons; | |
1727 | } | |
1728 | ||
7a372650 DL |
1729 | static int nau8825_high_imped_detection(struct nau8825 *nau8825) |
1730 | { | |
1731 | struct regmap *regmap = nau8825->regmap; | |
1732 | struct snd_soc_dapm_context *dapm = nau8825->dapm; | |
1733 | unsigned int adc_mg1, adc_mg2; | |
1734 | ||
1735 | /* Initial phase */ | |
1736 | regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, | |
1737 | NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2 | NAU8825_SPKR_DWN1R | | |
1738 | NAU8825_SPKR_DWN1L, NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2); | |
1739 | regmap_update_bits(regmap, NAU8825_REG_ANALOG_CONTROL_1, | |
1740 | NAU8825_TESTDACIN_MASK, NAU8825_TESTDACIN_GND); | |
1741 | regmap_write(regmap, NAU8825_REG_TRIM_SETTINGS, 0x6); | |
1742 | regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, | |
1743 | NAU8825_MICBIAS_LOWNOISE_MASK | NAU8825_MICBIAS_VOLTAGE_MASK, | |
1744 | NAU8825_MICBIAS_LOWNOISE_EN); | |
1745 | regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, | |
1746 | NAU8825_SAR_INPUT_MASK | NAU8825_SAR_TRACKING_GAIN_MASK | | |
1747 | NAU8825_SAR_HV_SEL_MASK | NAU8825_SAR_RES_SEL_MASK | | |
1748 | NAU8825_SAR_COMPARE_TIME_MASK | NAU8825_SAR_SAMPLING_TIME_MASK, | |
1749 | NAU8825_SAR_HV_SEL_VDDMIC | NAU8825_SAR_RES_SEL_70K); | |
1750 | ||
1751 | snd_soc_dapm_force_enable_pin(dapm, "MICBIAS"); | |
1752 | snd_soc_dapm_force_enable_pin(dapm, "SAR"); | |
1753 | snd_soc_dapm_sync(dapm); | |
1754 | ||
1755 | /* Configure settings for first reading of SARADC */ | |
1756 | regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, | |
1757 | NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2 | NAU8825_SPKR_DWN1R | | |
1758 | NAU8825_SPKR_DWN1L, NAU8825_SPKR_ENGND2); | |
1759 | regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, | |
1760 | NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, | |
1761 | NAU8825_MICBIAS_JKR2); | |
1762 | regmap_read(regmap, NAU8825_REG_SARDOUT_RAM_STATUS, &adc_mg1); | |
1763 | ||
1764 | /* Configure settings for second reading of SARADC */ | |
1765 | regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, | |
1766 | NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 0); | |
1767 | regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, | |
1768 | NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2 | NAU8825_SPKR_DWN1R | | |
1769 | NAU8825_SPKR_DWN1L, NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2 | | |
1770 | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L); | |
1771 | regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, | |
1772 | NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2 | NAU8825_SPKR_DWN1R | | |
1773 | NAU8825_SPKR_DWN1L, NAU8825_SPKR_ENGND1); | |
1774 | regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, | |
1775 | NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, | |
1776 | NAU8825_MICBIAS_JKSLV); | |
1777 | regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, | |
1778 | NAU8825_SAR_INPUT_MASK, NAU8825_SAR_INPUT_JKSLV); | |
1779 | regmap_read(regmap, NAU8825_REG_SARDOUT_RAM_STATUS, &adc_mg2); | |
1780 | ||
1781 | /* Disable phase */ | |
1782 | snd_soc_dapm_disable_pin(dapm, "SAR"); | |
1783 | snd_soc_dapm_disable_pin(dapm, "MICBIAS"); | |
1784 | snd_soc_dapm_sync(dapm); | |
1785 | ||
1786 | regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, | |
1787 | NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_LOWNOISE_MASK | | |
1788 | NAU8825_MICBIAS_VOLTAGE_MASK, nau8825->micbias_voltage); | |
1789 | regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, | |
1790 | NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2 | NAU8825_SPKR_DWN1R | | |
1791 | NAU8825_SPKR_DWN1L, NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2 | | |
1792 | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L); | |
1793 | regmap_update_bits(regmap, NAU8825_REG_ANALOG_CONTROL_1, | |
1794 | NAU8825_TESTDACIN_MASK, NAU8825_TESTDACIN_GND); | |
1795 | regmap_write(regmap, NAU8825_REG_TRIM_SETTINGS, 0); | |
1796 | regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, | |
1797 | NAU8825_SAR_TRACKING_GAIN_MASK | NAU8825_SAR_HV_SEL_MASK, | |
1798 | nau8825->sar_voltage << NAU8825_SAR_TRACKING_GAIN_SFT); | |
1799 | regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, | |
1800 | NAU8825_SAR_COMPARE_TIME_MASK | NAU8825_SAR_SAMPLING_TIME_MASK, | |
1801 | (nau8825->sar_compare_time << NAU8825_SAR_COMPARE_TIME_SFT) | | |
1802 | (nau8825->sar_sampling_time << NAU8825_SAR_SAMPLING_TIME_SFT)); | |
1803 | dev_dbg(nau8825->dev, "adc_mg1:%x, adc_mg2:%x\n", adc_mg1, adc_mg2); | |
1804 | ||
1805 | /* Confirmation phase */ | |
1806 | if (adc_mg1 > adc_mg2) { | |
1807 | dev_dbg(nau8825->dev, "OMTP (micgnd1) mic connected\n"); | |
1808 | ||
1809 | /* Unground MICGND1 */ | |
1810 | regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, | |
1811 | NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2, | |
1812 | NAU8825_SPKR_ENGND2); | |
1813 | /* Attach 2kOhm Resistor from MICBIAS to MICGND1 */ | |
1814 | regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, | |
1815 | NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, | |
1816 | NAU8825_MICBIAS_JKR2); | |
1817 | /* Attach SARADC to MICGND1 */ | |
1818 | regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, | |
1819 | NAU8825_SAR_INPUT_MASK, | |
1820 | NAU8825_SAR_INPUT_JKR2); | |
1821 | } else if (adc_mg1 < adc_mg2) { | |
1822 | dev_dbg(nau8825->dev, "CTIA (micgnd2) mic connected\n"); | |
1823 | ||
1824 | /* Unground MICGND2 */ | |
1825 | regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, | |
1826 | NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2, | |
1827 | NAU8825_SPKR_ENGND1); | |
1828 | /* Attach 2kOhm Resistor from MICBIAS to MICGND2 */ | |
1829 | regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, | |
1830 | NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, | |
1831 | NAU8825_MICBIAS_JKSLV); | |
1832 | /* Attach SARADC to MICGND2 */ | |
1833 | regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, | |
1834 | NAU8825_SAR_INPUT_MASK, | |
1835 | NAU8825_SAR_INPUT_JKSLV); | |
1836 | } else { | |
1837 | dev_err(nau8825->dev, "Jack broken.\n"); | |
1838 | return -EINVAL; | |
1839 | } | |
1840 | ||
1841 | return 0; | |
1842 | } | |
1843 | ||
34ca27f3 AP |
1844 | static int nau8825_jack_insert(struct nau8825 *nau8825) |
1845 | { | |
1846 | struct regmap *regmap = nau8825->regmap; | |
1847 | struct snd_soc_dapm_context *dapm = nau8825->dapm; | |
1848 | int jack_status_reg, mic_detected; | |
1849 | int type = 0; | |
1850 | ||
1851 | regmap_read(regmap, NAU8825_REG_GENERAL_STATUS, &jack_status_reg); | |
1852 | mic_detected = (jack_status_reg >> 10) & 3; | |
b50455fa JH |
1853 | /* The JKSLV and JKR2 all detected in high impedance headset */ |
1854 | if (mic_detected == 0x3) | |
1855 | nau8825->high_imped = true; | |
1856 | else | |
1857 | nau8825->high_imped = false; | |
34ca27f3 AP |
1858 | |
1859 | switch (mic_detected) { | |
1860 | case 0: | |
1861 | /* no mic */ | |
1862 | type = SND_JACK_HEADPHONE; | |
1863 | break; | |
1864 | case 1: | |
1865 | dev_dbg(nau8825->dev, "OMTP (micgnd1) mic connected\n"); | |
1866 | type = SND_JACK_HEADSET; | |
1867 | ||
1868 | /* Unground MICGND1 */ | |
1869 | regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 3 << 2, | |
1870 | 1 << 2); | |
1871 | /* Attach 2kOhm Resistor from MICBIAS to MICGND1 */ | |
1872 | regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, | |
1873 | NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, | |
1874 | NAU8825_MICBIAS_JKR2); | |
1875 | /* Attach SARADC to MICGND1 */ | |
1876 | regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, | |
1877 | NAU8825_SAR_INPUT_MASK, | |
1878 | NAU8825_SAR_INPUT_JKR2); | |
1879 | ||
1880 | snd_soc_dapm_force_enable_pin(dapm, "MICBIAS"); | |
1881 | snd_soc_dapm_force_enable_pin(dapm, "SAR"); | |
1882 | snd_soc_dapm_sync(dapm); | |
1883 | break; | |
1884 | case 2: | |
34ca27f3 AP |
1885 | dev_dbg(nau8825->dev, "CTIA (micgnd2) mic connected\n"); |
1886 | type = SND_JACK_HEADSET; | |
1887 | ||
1888 | /* Unground MICGND2 */ | |
1889 | regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 3 << 2, | |
1890 | 2 << 2); | |
1891 | /* Attach 2kOhm Resistor from MICBIAS to MICGND2 */ | |
1892 | regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, | |
1893 | NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, | |
1894 | NAU8825_MICBIAS_JKSLV); | |
1895 | /* Attach SARADC to MICGND2 */ | |
1896 | regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, | |
1897 | NAU8825_SAR_INPUT_MASK, | |
1898 | NAU8825_SAR_INPUT_JKSLV); | |
1899 | ||
1900 | snd_soc_dapm_force_enable_pin(dapm, "MICBIAS"); | |
1901 | snd_soc_dapm_force_enable_pin(dapm, "SAR"); | |
1902 | snd_soc_dapm_sync(dapm); | |
1903 | break; | |
8fe19795 | 1904 | case 3: |
7a372650 DL |
1905 | /* Detection failure case */ |
1906 | dev_warn(nau8825->dev, | |
1907 | "Detection failure. Try the manually mechanism for jack type checking.\n"); | |
1908 | if (!nau8825_high_imped_detection(nau8825)) { | |
1909 | type = SND_JACK_HEADSET; | |
1910 | snd_soc_dapm_force_enable_pin(dapm, "MICBIAS"); | |
1911 | snd_soc_dapm_force_enable_pin(dapm, "SAR"); | |
1912 | snd_soc_dapm_sync(dapm); | |
1913 | } else | |
1914 | type = SND_JACK_HEADPHONE; | |
8fe19795 | 1915 | break; |
34ca27f3 AP |
1916 | } |
1917 | ||
fa0fb073 DL |
1918 | /* Update to the default divider of internal clock for power saving */ |
1919 | regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER, | |
1920 | NAU8825_CLK_MCLK_SRC_MASK, 0xf); | |
1921 | ||
8315d8ad DL |
1922 | /* Disable HSD function */ |
1923 | regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, NAU8825_HSD_AUTO_MODE, 0); | |
1924 | ||
45d5eb3a JH |
1925 | /* Leaving HPOL/R grounded after jack insert by default. They will be |
1926 | * ungrounded as part of the widget power up sequence at the beginning | |
1927 | * of playback to reduce pop. | |
1928 | */ | |
34ca27f3 AP |
1929 | return type; |
1930 | } | |
1931 | ||
1932 | #define NAU8825_BUTTONS (SND_JACK_BTN_0 | SND_JACK_BTN_1 | \ | |
1933 | SND_JACK_BTN_2 | SND_JACK_BTN_3) | |
1934 | ||
1935 | static irqreturn_t nau8825_interrupt(int irq, void *data) | |
1936 | { | |
1937 | struct nau8825 *nau8825 = (struct nau8825 *)data; | |
1938 | struct regmap *regmap = nau8825->regmap; | |
1939 | int active_irq, clear_irq = 0, event = 0, event_mask = 0; | |
1940 | ||
e6cee900 BZ |
1941 | if (regmap_read(regmap, NAU8825_REG_IRQ_STATUS, &active_irq)) { |
1942 | dev_err(nau8825->dev, "failed to read irq status\n"); | |
1943 | return IRQ_NONE; | |
1944 | } | |
34ca27f3 AP |
1945 | |
1946 | if ((active_irq & NAU8825_JACK_EJECTION_IRQ_MASK) == | |
1947 | NAU8825_JACK_EJECTION_DETECTED) { | |
1948 | ||
1949 | nau8825_eject_jack(nau8825); | |
1950 | event_mask |= SND_JACK_HEADSET; | |
1951 | clear_irq = NAU8825_JACK_EJECTION_IRQ_MASK; | |
1952 | } else if (active_irq & NAU8825_KEY_SHORT_PRESS_IRQ) { | |
1953 | int key_status; | |
1954 | ||
1955 | regmap_read(regmap, NAU8825_REG_INT_CLR_KEY_STATUS, | |
1956 | &key_status); | |
1957 | ||
1958 | /* upper 8 bits of the register are for short pressed keys, | |
1959 | * lower 8 bits - for long pressed buttons | |
1960 | */ | |
1961 | nau8825->button_pressed = nau8825_button_decode( | |
1962 | key_status >> 8); | |
1963 | ||
1964 | event |= nau8825->button_pressed; | |
1965 | event_mask |= NAU8825_BUTTONS; | |
1966 | clear_irq = NAU8825_KEY_SHORT_PRESS_IRQ; | |
1967 | } else if (active_irq & NAU8825_KEY_RELEASE_IRQ) { | |
1968 | event_mask = NAU8825_BUTTONS; | |
1969 | clear_irq = NAU8825_KEY_RELEASE_IRQ; | |
1970 | } else if (active_irq & NAU8825_HEADSET_COMPLETION_IRQ) { | |
1971 | if (nau8825_is_jack_inserted(regmap)) { | |
1972 | event |= nau8825_jack_insert(nau8825); | |
226d7449 | 1973 | if (nau8825->xtalk_enable && !nau8825->high_imped) { |
b50455fa JH |
1974 | /* Apply the cross talk suppression in the |
1975 | * headset without high impedance. | |
1976 | */ | |
1977 | if (!nau8825->xtalk_protect) { | |
1978 | /* Raise protection for cross talk de- | |
1979 | * tection if no protection before. | |
1980 | * The driver has to cancel the pro- | |
1981 | * cess and restore changes if process | |
1982 | * is ongoing when ejection. | |
1983 | */ | |
06746c67 | 1984 | int ret; |
b50455fa | 1985 | nau8825->xtalk_protect = true; |
06746c67 | 1986 | ret = nau8825_sema_acquire(nau8825, 0); |
70424d8e | 1987 | if (ret) |
06746c67 | 1988 | nau8825->xtalk_protect = false; |
b50455fa JH |
1989 | } |
1990 | /* Startup cross talk detection process */ | |
fa25b4f5 JH |
1991 | if (nau8825->xtalk_protect) { |
1992 | nau8825->xtalk_state = | |
1993 | NAU8825_XTALK_PREPARE; | |
1994 | schedule_work(&nau8825->xtalk_work); | |
1995 | } | |
b50455fa JH |
1996 | } else { |
1997 | /* The cross talk suppression shouldn't apply | |
1998 | * in the headset with high impedance. Thus, | |
1999 | * relieve the protection raised before. | |
2000 | */ | |
2001 | if (nau8825->xtalk_protect) { | |
2002 | nau8825_sema_release(nau8825); | |
2003 | nau8825->xtalk_protect = false; | |
2004 | } | |
2005 | } | |
34ca27f3 AP |
2006 | } else { |
2007 | dev_warn(nau8825->dev, "Headset completion IRQ fired but no headset connected\n"); | |
2008 | nau8825_eject_jack(nau8825); | |
2009 | } | |
2010 | ||
2011 | event_mask |= SND_JACK_HEADSET; | |
2012 | clear_irq = NAU8825_HEADSET_COMPLETION_IRQ; | |
b50455fa JH |
2013 | /* Record the interruption report event for driver to report |
2014 | * the event later. The jack report will delay until cross | |
2015 | * talk detection process is done. | |
2016 | */ | |
2017 | if (nau8825->xtalk_state == NAU8825_XTALK_PREPARE) { | |
2018 | nau8825->xtalk_event = event; | |
2019 | nau8825->xtalk_event_mask = event_mask; | |
2020 | } | |
2021 | } else if (active_irq & NAU8825_IMPEDANCE_MEAS_IRQ) { | |
fa25b4f5 JH |
2022 | /* crosstalk detection enable and process on going */ |
2023 | if (nau8825->xtalk_enable && nau8825->xtalk_protect) | |
226d7449 | 2024 | schedule_work(&nau8825->xtalk_work); |
b50455fa | 2025 | clear_irq = NAU8825_IMPEDANCE_MEAS_IRQ; |
2ec30f60 JH |
2026 | } else if ((active_irq & NAU8825_JACK_INSERTION_IRQ_MASK) == |
2027 | NAU8825_JACK_INSERTION_DETECTED) { | |
2028 | /* One more step to check GPIO status directly. Thus, the | |
2029 | * driver can confirm the real insertion interruption because | |
2030 | * the intrruption at manual mode has bypassed debounce | |
2031 | * circuit which can get rid of unstable status. | |
2032 | */ | |
2033 | if (nau8825_is_jack_inserted(regmap)) { | |
2034 | /* Turn off insertion interruption at manual mode */ | |
2035 | regmap_update_bits(regmap, | |
2036 | NAU8825_REG_INTERRUPT_DIS_CTRL, | |
2037 | NAU8825_IRQ_INSERT_DIS, | |
2038 | NAU8825_IRQ_INSERT_DIS); | |
2039 | regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, | |
2040 | NAU8825_IRQ_INSERT_EN, NAU8825_IRQ_INSERT_EN); | |
2041 | /* Enable interruption for jack type detection at audo | |
2042 | * mode which can detect microphone and jack type. | |
2043 | */ | |
2044 | nau8825_setup_auto_irq(nau8825); | |
2045 | } | |
34ca27f3 AP |
2046 | } |
2047 | ||
2048 | if (!clear_irq) | |
2049 | clear_irq = active_irq; | |
2050 | /* clears the rightmost interruption */ | |
2051 | regmap_write(regmap, NAU8825_REG_INT_CLR_KEY_STATUS, clear_irq); | |
2052 | ||
b50455fa JH |
2053 | /* Delay jack report until cross talk detection is done. It can avoid |
2054 | * application to do playback preparation when cross talk detection | |
2055 | * process is still working. Otherwise, the resource like clock and | |
2056 | * power will be issued by them at the same time and conflict happens. | |
2057 | */ | |
2058 | if (event_mask && nau8825->xtalk_state == NAU8825_XTALK_DONE) | |
34ca27f3 AP |
2059 | snd_soc_jack_report(nau8825->jack, event, event_mask); |
2060 | ||
2061 | return IRQ_HANDLED; | |
2062 | } | |
2063 | ||
2064 | static void nau8825_setup_buttons(struct nau8825 *nau8825) | |
2065 | { | |
2066 | struct regmap *regmap = nau8825->regmap; | |
2067 | ||
2068 | regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, | |
2069 | NAU8825_SAR_TRACKING_GAIN_MASK, | |
2070 | nau8825->sar_voltage << NAU8825_SAR_TRACKING_GAIN_SFT); | |
2071 | regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, | |
2072 | NAU8825_SAR_COMPARE_TIME_MASK, | |
2073 | nau8825->sar_compare_time << NAU8825_SAR_COMPARE_TIME_SFT); | |
2074 | regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL, | |
2075 | NAU8825_SAR_SAMPLING_TIME_MASK, | |
2076 | nau8825->sar_sampling_time << NAU8825_SAR_SAMPLING_TIME_SFT); | |
2077 | ||
2078 | regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL, | |
2079 | NAU8825_KEYDET_LEVELS_NR_MASK, | |
2080 | (nau8825->sar_threshold_num - 1) << NAU8825_KEYDET_LEVELS_NR_SFT); | |
2081 | regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL, | |
2082 | NAU8825_KEYDET_HYSTERESIS_MASK, | |
2083 | nau8825->sar_hysteresis << NAU8825_KEYDET_HYSTERESIS_SFT); | |
2084 | regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL, | |
2085 | NAU8825_KEYDET_SHORTKEY_DEBOUNCE_MASK, | |
2086 | nau8825->key_debounce << NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT); | |
2087 | ||
2088 | regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_1, | |
2089 | (nau8825->sar_threshold[0] << 8) | nau8825->sar_threshold[1]); | |
2090 | regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_2, | |
2091 | (nau8825->sar_threshold[2] << 8) | nau8825->sar_threshold[3]); | |
2092 | regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_3, | |
2093 | (nau8825->sar_threshold[4] << 8) | nau8825->sar_threshold[5]); | |
2094 | regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_4, | |
2095 | (nau8825->sar_threshold[6] << 8) | nau8825->sar_threshold[7]); | |
2096 | ||
2097 | /* Enable short press and release interruptions */ | |
2098 | regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, | |
2099 | NAU8825_IRQ_KEY_SHORT_PRESS_EN | NAU8825_IRQ_KEY_RELEASE_EN, | |
2100 | 0); | |
2101 | } | |
2102 | ||
2103 | static void nau8825_init_regs(struct nau8825 *nau8825) | |
2104 | { | |
2105 | struct regmap *regmap = nau8825->regmap; | |
2106 | ||
45d5eb3a JH |
2107 | /* Latch IIC LSB value */ |
2108 | regmap_write(regmap, NAU8825_REG_IIC_ADDR_SET, 0x0001); | |
34ca27f3 AP |
2109 | /* Enable Bias/Vmid */ |
2110 | regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ, | |
2111 | NAU8825_BIAS_VMID, NAU8825_BIAS_VMID); | |
2112 | regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST, | |
2113 | NAU8825_GLOBAL_BIAS_EN, NAU8825_GLOBAL_BIAS_EN); | |
2114 | ||
2115 | /* VMID Tieoff */ | |
2116 | regmap_update_bits(regmap, NAU8825_REG_BIAS_ADJ, | |
2117 | NAU8825_BIAS_VMID_SEL_MASK, | |
2118 | nau8825->vref_impedance << NAU8825_BIAS_VMID_SEL_SFT); | |
2119 | /* Disable Boost Driver, Automatic Short circuit protection enable */ | |
2120 | regmap_update_bits(regmap, NAU8825_REG_BOOST, | |
45d5eb3a JH |
2121 | NAU8825_PRECHARGE_DIS | NAU8825_HP_BOOST_DIS | |
2122 | NAU8825_HP_BOOST_G_DIS | NAU8825_SHORT_SHUTDOWN_EN, | |
2123 | NAU8825_PRECHARGE_DIS | NAU8825_HP_BOOST_DIS | | |
2124 | NAU8825_HP_BOOST_G_DIS | NAU8825_SHORT_SHUTDOWN_EN); | |
34ca27f3 AP |
2125 | |
2126 | regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL, | |
2127 | NAU8825_JKDET_OUTPUT_EN, | |
2128 | nau8825->jkdet_enable ? 0 : NAU8825_JKDET_OUTPUT_EN); | |
2129 | regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL, | |
2130 | NAU8825_JKDET_PULL_EN, | |
2131 | nau8825->jkdet_pull_enable ? 0 : NAU8825_JKDET_PULL_EN); | |
2132 | regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL, | |
2133 | NAU8825_JKDET_PULL_UP, | |
2134 | nau8825->jkdet_pull_up ? NAU8825_JKDET_PULL_UP : 0); | |
2135 | regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, | |
2136 | NAU8825_JACK_POLARITY, | |
2137 | /* jkdet_polarity - 1 is for active-low */ | |
2138 | nau8825->jkdet_polarity ? 0 : NAU8825_JACK_POLARITY); | |
2139 | ||
2140 | regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, | |
2141 | NAU8825_JACK_INSERT_DEBOUNCE_MASK, | |
2142 | nau8825->jack_insert_debounce << NAU8825_JACK_INSERT_DEBOUNCE_SFT); | |
2143 | regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, | |
2144 | NAU8825_JACK_EJECT_DEBOUNCE_MASK, | |
2145 | nau8825->jack_eject_debounce << NAU8825_JACK_EJECT_DEBOUNCE_SFT); | |
2146 | ||
cbb9f8cc JH |
2147 | /* Pull up IRQ pin */ |
2148 | regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, | |
2149 | NAU8825_IRQ_PIN_PULLUP | NAU8825_IRQ_PIN_PULL_EN, | |
2150 | NAU8825_IRQ_PIN_PULLUP | NAU8825_IRQ_PIN_PULL_EN); | |
34ca27f3 AP |
2151 | /* Mask unneeded IRQs: 1 - disable, 0 - enable */ |
2152 | regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 0x7ff, 0x7ff); | |
2153 | ||
2154 | regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS, | |
2155 | NAU8825_MICBIAS_VOLTAGE_MASK, nau8825->micbias_voltage); | |
2156 | ||
2157 | if (nau8825->sar_threshold_num) | |
2158 | nau8825_setup_buttons(nau8825); | |
2159 | ||
2160 | /* Default oversampling/decimations settings are unusable | |
2161 | * (audible hiss). Set it to something better. | |
2162 | */ | |
2163 | regmap_update_bits(regmap, NAU8825_REG_ADC_RATE, | |
5f1516d5 JH |
2164 | NAU8825_ADC_SYNC_DOWN_MASK | NAU8825_ADC_SINC4_EN, |
2165 | NAU8825_ADC_SYNC_DOWN_64); | |
34ca27f3 | 2166 | regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1, |
d6d19745 | 2167 | NAU8825_DAC_OVERSAMPLE_MASK, NAU8825_DAC_OVERSAMPLE_64); |
45d5eb3a | 2168 | /* Disable DACR/L power */ |
955b503b DL |
2169 | if (nau8825->sw_id == NAU8825_SOFTWARE_ID_NAU8825) |
2170 | regmap_update_bits(regmap, NAU8825_REG_CHARGE_PUMP, | |
2171 | NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, | |
2172 | NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL); | |
45d5eb3a JH |
2173 | /* Enable TESTDAC. This sets the analog DAC inputs to a '0' input |
2174 | * signal to avoid any glitches due to power up transients in both | |
2175 | * the analog and digital DAC circuit. | |
2176 | */ | |
2177 | regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ, | |
2178 | NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN); | |
2179 | /* CICCLP off */ | |
2180 | regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1, | |
2181 | NAU8825_DAC_CLIP_OFF, NAU8825_DAC_CLIP_OFF); | |
2182 | ||
2183 | /* Class AB bias current to 2x, DAC Capacitor enable MSB/LSB */ | |
2184 | regmap_update_bits(regmap, NAU8825_REG_ANALOG_CONTROL_2, | |
2185 | NAU8825_HP_NON_CLASSG_CURRENT_2xADJ | | |
2186 | NAU8825_DAC_CAPACITOR_MSB | NAU8825_DAC_CAPACITOR_LSB, | |
2187 | NAU8825_HP_NON_CLASSG_CURRENT_2xADJ | | |
2188 | NAU8825_DAC_CAPACITOR_MSB | NAU8825_DAC_CAPACITOR_LSB); | |
2189 | /* Class G timer 64ms */ | |
2190 | regmap_update_bits(regmap, NAU8825_REG_CLASSG_CTRL, | |
2191 | NAU8825_CLASSG_TIMER_MASK, | |
2192 | 0x20 << NAU8825_CLASSG_TIMER_SFT); | |
2193 | /* DAC clock delay 2ns, VREF */ | |
2194 | regmap_update_bits(regmap, NAU8825_REG_RDAC, | |
2195 | NAU8825_RDAC_CLK_DELAY_MASK | NAU8825_RDAC_VREF_MASK, | |
2196 | (0x2 << NAU8825_RDAC_CLK_DELAY_SFT) | | |
2197 | (0x3 << NAU8825_RDAC_VREF_SFT)); | |
3f039169 JH |
2198 | /* Config L/R channel */ |
2199 | regmap_update_bits(nau8825->regmap, NAU8825_REG_DACL_CTRL, | |
2200 | NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_L); | |
2201 | regmap_update_bits(nau8825->regmap, NAU8825_REG_DACR_CTRL, | |
2202 | NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_R); | |
93dfec75 JH |
2203 | /* Disable short Frame Sync detection logic */ |
2204 | regmap_update_bits(regmap, NAU8825_REG_LEFT_TIME_SLOT, | |
2205 | NAU8825_DIS_FS_SHORT_DET, NAU8825_DIS_FS_SHORT_DET); | |
ed857072 DL |
2206 | /* ADCDAT IO drive strength control */ |
2207 | regmap_update_bits(regmap, NAU8825_REG_CHARGE_PUMP, | |
2208 | NAU8825_ADCOUT_DS_MASK, | |
2209 | nau8825->adcout_ds << NAU8825_ADCOUT_DS_SFT); | |
34ca27f3 AP |
2210 | } |
2211 | ||
2212 | static const struct regmap_config nau8825_regmap_config = { | |
2ec30f60 JH |
2213 | .val_bits = NAU8825_REG_DATA_LEN, |
2214 | .reg_bits = NAU8825_REG_ADDR_LEN, | |
34ca27f3 AP |
2215 | |
2216 | .max_register = NAU8825_REG_MAX, | |
2217 | .readable_reg = nau8825_readable_reg, | |
2218 | .writeable_reg = nau8825_writeable_reg, | |
2219 | .volatile_reg = nau8825_volatile_reg, | |
2220 | ||
2221 | .cache_type = REGCACHE_RBTREE, | |
2222 | .reg_defaults = nau8825_reg_defaults, | |
2223 | .num_reg_defaults = ARRAY_SIZE(nau8825_reg_defaults), | |
2224 | }; | |
2225 | ||
45101122 | 2226 | static int nau8825_component_probe(struct snd_soc_component *component) |
34ca27f3 | 2227 | { |
45101122 KM |
2228 | struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); |
2229 | struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); | |
34ca27f3 AP |
2230 | |
2231 | nau8825->dapm = dapm; | |
2232 | ||
34ca27f3 AP |
2233 | return 0; |
2234 | } | |
2235 | ||
45101122 | 2236 | static void nau8825_component_remove(struct snd_soc_component *component) |
b50455fa | 2237 | { |
45101122 | 2238 | struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); |
b50455fa JH |
2239 | |
2240 | /* Cancel and reset cross tak suppresstion detection funciton */ | |
2241 | nau8825_xtalk_cancel(nau8825); | |
b50455fa JH |
2242 | } |
2243 | ||
c86ba612 BZ |
2244 | /** |
2245 | * nau8825_calc_fll_param - Calculate FLL parameters. | |
2246 | * @fll_in: external clock provided to codec. | |
2247 | * @fs: sampling rate. | |
2248 | * @fll_param: Pointer to structure of FLL parameters. | |
2249 | * | |
2250 | * Calculate FLL parameters to configure codec. | |
2251 | * | |
2252 | * Returns 0 for success or negative error code. | |
2253 | */ | |
2254 | static int nau8825_calc_fll_param(unsigned int fll_in, unsigned int fs, | |
2255 | struct nau8825_fll *fll_param) | |
2256 | { | |
407c71b6 JH |
2257 | u64 fvco, fvco_max; |
2258 | unsigned int fref, i, fvco_sel; | |
c86ba612 BZ |
2259 | |
2260 | /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing | |
2261 | * freq_in by 1, 2, 4, or 8 using FLL pre-scalar. | |
2262 | * FREF = freq_in / NAU8825_FLL_REF_DIV_MASK | |
2263 | */ | |
2264 | for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) { | |
2265 | fref = fll_in / fll_pre_scalar[i].param; | |
2266 | if (fref <= NAU_FREF_MAX) | |
2267 | break; | |
2268 | } | |
2269 | if (i == ARRAY_SIZE(fll_pre_scalar)) | |
2270 | return -EINVAL; | |
2271 | fll_param->clk_ref_div = fll_pre_scalar[i].val; | |
2272 | ||
2273 | /* Choose the FLL ratio based on FREF */ | |
2274 | for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) { | |
2275 | if (fref >= fll_ratio[i].param) | |
2276 | break; | |
2277 | } | |
2278 | if (i == ARRAY_SIZE(fll_ratio)) | |
2279 | return -EINVAL; | |
2280 | fll_param->ratio = fll_ratio[i].val; | |
2281 | ||
2282 | /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs. | |
407c71b6 | 2283 | * FDCO must be within the 90MHz - 124MHz or the FFL cannot be |
c86ba612 BZ |
2284 | * guaranteed across the full range of operation. |
2285 | * FDCO = freq_out * 2 * mclk_src_scaling | |
2286 | */ | |
407c71b6 JH |
2287 | fvco_max = 0; |
2288 | fvco_sel = ARRAY_SIZE(mclk_src_scaling); | |
c86ba612 | 2289 | for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) { |
da13ed1d | 2290 | fvco = 256ULL * fs * 2 * mclk_src_scaling[i].param; |
407c71b6 JH |
2291 | if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX && |
2292 | fvco_max < fvco) { | |
2293 | fvco_max = fvco; | |
2294 | fvco_sel = i; | |
2295 | } | |
c86ba612 | 2296 | } |
407c71b6 | 2297 | if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel) |
c86ba612 | 2298 | return -EINVAL; |
407c71b6 | 2299 | fll_param->mclk_src = mclk_src_scaling[fvco_sel].val; |
c86ba612 BZ |
2300 | |
2301 | /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional | |
2302 | * input based on FDCO, FREF and FLL ratio. | |
2303 | */ | |
6d64c33f DL |
2304 | fvco = div_u64(fvco_max << fll_param->fll_frac_num, fref * fll_param->ratio); |
2305 | fll_param->fll_int = (fvco >> fll_param->fll_frac_num) & 0x3FF; | |
2306 | if (fll_param->fll_frac_num == 16) | |
2307 | fll_param->fll_frac = fvco & 0xFFFF; | |
2308 | else | |
2309 | fll_param->fll_frac = fvco & 0xFFFFFF; | |
c86ba612 BZ |
2310 | return 0; |
2311 | } | |
2312 | ||
2313 | static void nau8825_fll_apply(struct nau8825 *nau8825, | |
2314 | struct nau8825_fll *fll_param) | |
2315 | { | |
2316 | regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER, | |
407c71b6 JH |
2317 | NAU8825_CLK_SRC_MASK | NAU8825_CLK_MCLK_SRC_MASK, |
2318 | NAU8825_CLK_SRC_MCLK | fll_param->mclk_src); | |
aee02c75 | 2319 | /* Make DSP operate at high speed for better performance. */ |
c86ba612 | 2320 | regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1, |
aee02c75 JH |
2321 | NAU8825_FLL_RATIO_MASK | NAU8825_ICTRL_LATCH_MASK, |
2322 | fll_param->ratio | (0x6 << NAU8825_ICTRL_LATCH_SFT)); | |
6d64c33f DL |
2323 | /* FLL 16/24 bit fractional input */ |
2324 | if (fll_param->fll_frac_num == 16) | |
2325 | regmap_write(nau8825->regmap, NAU8825_REG_FLL2, | |
2326 | fll_param->fll_frac); | |
2327 | else { | |
2328 | regmap_write(nau8825->regmap, NAU8825_REG_FLL2_LOWER, | |
2329 | fll_param->fll_frac & 0xffff); | |
2330 | regmap_write(nau8825->regmap, NAU8825_REG_FLL2_UPPER, | |
2331 | (fll_param->fll_frac >> 16) & 0xff); | |
2332 | } | |
c86ba612 BZ |
2333 | /* FLL 10-bit integer input */ |
2334 | regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL3, | |
2335 | NAU8825_FLL_INTEGER_MASK, fll_param->fll_int); | |
2336 | /* FLL pre-scaler */ | |
2337 | regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL4, | |
a1792cda JH |
2338 | NAU8825_FLL_REF_DIV_MASK, |
2339 | fll_param->clk_ref_div << NAU8825_FLL_REF_DIV_SFT); | |
c86ba612 BZ |
2340 | /* select divided VCO input */ |
2341 | regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5, | |
407c71b6 JH |
2342 | NAU8825_FLL_CLK_SW_MASK, NAU8825_FLL_CLK_SW_REF); |
2343 | /* Disable free-running mode */ | |
2344 | regmap_update_bits(nau8825->regmap, | |
2345 | NAU8825_REG_FLL6, NAU8825_DCO_EN, 0); | |
2346 | if (fll_param->fll_frac) { | |
aee02c75 | 2347 | /* set FLL loop filter enable and cutoff frequency at 500Khz */ |
407c71b6 JH |
2348 | regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5, |
2349 | NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN | | |
2350 | NAU8825_FLL_FTR_SW_MASK, | |
2351 | NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN | | |
2352 | NAU8825_FLL_FTR_SW_FILTER); | |
2353 | regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6, | |
aee02c75 JH |
2354 | NAU8825_SDM_EN | NAU8825_CUTOFF500, |
2355 | NAU8825_SDM_EN | NAU8825_CUTOFF500); | |
407c71b6 | 2356 | } else { |
aee02c75 | 2357 | /* disable FLL loop filter and cutoff frequency */ |
407c71b6 JH |
2358 | regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5, |
2359 | NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN | | |
2360 | NAU8825_FLL_FTR_SW_MASK, NAU8825_FLL_FTR_SW_ACCU); | |
aee02c75 JH |
2361 | regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6, |
2362 | NAU8825_SDM_EN | NAU8825_CUTOFF500, 0); | |
407c71b6 | 2363 | } |
c86ba612 BZ |
2364 | } |
2365 | ||
2366 | /* freq_out must be 256*Fs in order to achieve the best performance */ | |
45101122 | 2367 | static int nau8825_set_pll(struct snd_soc_component *component, int pll_id, int source, |
c86ba612 BZ |
2368 | unsigned int freq_in, unsigned int freq_out) |
2369 | { | |
45101122 | 2370 | struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); |
c86ba612 BZ |
2371 | struct nau8825_fll fll_param; |
2372 | int ret, fs; | |
2373 | ||
6d64c33f DL |
2374 | if (nau8825->sw_id == NAU8825_SOFTWARE_ID_NAU8825) |
2375 | fll_param.fll_frac_num = 16; | |
2376 | else | |
2377 | fll_param.fll_frac_num = 24; | |
2378 | ||
c86ba612 BZ |
2379 | fs = freq_out / 256; |
2380 | ret = nau8825_calc_fll_param(freq_in, fs, &fll_param); | |
2381 | if (ret < 0) { | |
45101122 | 2382 | dev_err(component->dev, "Unsupported input clock %d\n", freq_in); |
c86ba612 BZ |
2383 | return ret; |
2384 | } | |
45101122 | 2385 | dev_dbg(component->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n", |
c86ba612 BZ |
2386 | fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac, |
2387 | fll_param.fll_int, fll_param.clk_ref_div); | |
2388 | ||
2389 | nau8825_fll_apply(nau8825, &fll_param); | |
2390 | mdelay(2); | |
2391 | regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER, | |
2392 | NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO); | |
2393 | return 0; | |
2394 | } | |
2395 | ||
70543c30 JH |
2396 | static int nau8825_mclk_prepare(struct nau8825 *nau8825, unsigned int freq) |
2397 | { | |
a3966b25 | 2398 | int ret; |
70543c30 JH |
2399 | |
2400 | nau8825->mclk = devm_clk_get(nau8825->dev, "mclk"); | |
2401 | if (IS_ERR(nau8825->mclk)) { | |
2402 | dev_info(nau8825->dev, "No 'mclk' clock found, assume MCLK is managed externally"); | |
2403 | return 0; | |
2404 | } | |
2405 | ||
2406 | if (!nau8825->mclk_freq) { | |
2407 | ret = clk_prepare_enable(nau8825->mclk); | |
2408 | if (ret) { | |
2409 | dev_err(nau8825->dev, "Unable to prepare codec mclk\n"); | |
2410 | return ret; | |
2411 | } | |
2412 | } | |
2413 | ||
2414 | if (nau8825->mclk_freq != freq) { | |
2415 | freq = clk_round_rate(nau8825->mclk, freq); | |
2416 | ret = clk_set_rate(nau8825->mclk, freq); | |
2417 | if (ret) { | |
2418 | dev_err(nau8825->dev, "Unable to set mclk rate\n"); | |
2419 | return ret; | |
2420 | } | |
2421 | nau8825->mclk_freq = freq; | |
2422 | } | |
2423 | ||
2424 | return 0; | |
2425 | } | |
2426 | ||
2ec30f60 JH |
2427 | static void nau8825_configure_mclk_as_sysclk(struct regmap *regmap) |
2428 | { | |
2429 | regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER, | |
2430 | NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_MCLK); | |
2431 | regmap_update_bits(regmap, NAU8825_REG_FLL6, | |
2432 | NAU8825_DCO_EN, 0); | |
aee02c75 JH |
2433 | /* Make DSP operate as default setting for power saving. */ |
2434 | regmap_update_bits(regmap, NAU8825_REG_FLL1, | |
2435 | NAU8825_ICTRL_LATCH_MASK, 0); | |
2ec30f60 JH |
2436 | } |
2437 | ||
34ca27f3 AP |
2438 | static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id, |
2439 | unsigned int freq) | |
2440 | { | |
2441 | struct regmap *regmap = nau8825->regmap; | |
2442 | int ret; | |
2443 | ||
2444 | switch (clk_id) { | |
2ec30f60 JH |
2445 | case NAU8825_CLK_DIS: |
2446 | /* Clock provided externally and disable internal VCO clock */ | |
2447 | nau8825_configure_mclk_as_sysclk(regmap); | |
2448 | if (nau8825->mclk_freq) { | |
2449 | clk_disable_unprepare(nau8825->mclk); | |
2450 | nau8825->mclk_freq = 0; | |
2451 | } | |
2452 | ||
2453 | break; | |
34ca27f3 | 2454 | case NAU8825_CLK_MCLK: |
3dfcd346 | 2455 | /* Acquire the semaphore to synchronize the playback and |
b50455fa JH |
2456 | * interrupt handler. In order to avoid the playback inter- |
2457 | * fered by cross talk process, the driver make the playback | |
2458 | * preparation halted until cross talk process finish. | |
2459 | */ | |
2263fddc | 2460 | nau8825_sema_acquire(nau8825, 3 * HZ); |
2ec30f60 | 2461 | nau8825_configure_mclk_as_sysclk(regmap); |
3a561035 JH |
2462 | /* MCLK not changed by clock tree */ |
2463 | regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER, | |
2464 | NAU8825_CLK_MCLK_SRC_MASK, 0); | |
3dfcd346 | 2465 | /* Release the semaphore. */ |
b50455fa JH |
2466 | nau8825_sema_release(nau8825); |
2467 | ||
70543c30 JH |
2468 | ret = nau8825_mclk_prepare(nau8825, freq); |
2469 | if (ret) | |
2470 | return ret; | |
34ca27f3 AP |
2471 | |
2472 | break; | |
2473 | case NAU8825_CLK_INTERNAL: | |
2ec30f60 JH |
2474 | if (nau8825_is_jack_inserted(nau8825->regmap)) { |
2475 | regmap_update_bits(regmap, NAU8825_REG_FLL6, | |
2476 | NAU8825_DCO_EN, NAU8825_DCO_EN); | |
2477 | regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER, | |
2478 | NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO); | |
aee02c75 JH |
2479 | /* Decrease the VCO frequency and make DSP operate |
2480 | * as default setting for power saving. | |
2481 | */ | |
2ec30f60 JH |
2482 | regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER, |
2483 | NAU8825_CLK_MCLK_SRC_MASK, 0xf); | |
2484 | regmap_update_bits(regmap, NAU8825_REG_FLL1, | |
aee02c75 | 2485 | NAU8825_ICTRL_LATCH_MASK | |
2ec30f60 JH |
2486 | NAU8825_FLL_RATIO_MASK, 0x10); |
2487 | regmap_update_bits(regmap, NAU8825_REG_FLL6, | |
2488 | NAU8825_SDM_EN, NAU8825_SDM_EN); | |
2489 | } else { | |
2490 | /* The clock turns off intentionally for power saving | |
2491 | * when no headset connected. | |
2492 | */ | |
2493 | nau8825_configure_mclk_as_sysclk(regmap); | |
2494 | dev_warn(nau8825->dev, "Disable clock for power saving when no headset connected\n"); | |
2495 | } | |
70543c30 JH |
2496 | if (nau8825->mclk_freq) { |
2497 | clk_disable_unprepare(nau8825->mclk); | |
2498 | nau8825->mclk_freq = 0; | |
2499 | } | |
2500 | ||
2501 | break; | |
2502 | case NAU8825_CLK_FLL_MCLK: | |
3dfcd346 | 2503 | /* Acquire the semaphore to synchronize the playback and |
b50455fa JH |
2504 | * interrupt handler. In order to avoid the playback inter- |
2505 | * fered by cross talk process, the driver make the playback | |
2506 | * preparation halted until cross talk process finish. | |
2507 | */ | |
2263fddc | 2508 | nau8825_sema_acquire(nau8825, 3 * HZ); |
aee02c75 JH |
2509 | /* Higher FLL reference input frequency can only set lower |
2510 | * gain error, such as 0000 for input reference from MCLK | |
2511 | * 12.288Mhz. | |
2512 | */ | |
70543c30 | 2513 | regmap_update_bits(regmap, NAU8825_REG_FLL3, |
aee02c75 JH |
2514 | NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK, |
2515 | NAU8825_FLL_CLK_SRC_MCLK | 0); | |
3dfcd346 | 2516 | /* Release the semaphore. */ |
b50455fa JH |
2517 | nau8825_sema_release(nau8825); |
2518 | ||
70543c30 JH |
2519 | ret = nau8825_mclk_prepare(nau8825, freq); |
2520 | if (ret) | |
2521 | return ret; | |
2522 | ||
2523 | break; | |
2524 | case NAU8825_CLK_FLL_BLK: | |
3dfcd346 | 2525 | /* Acquire the semaphore to synchronize the playback and |
b50455fa JH |
2526 | * interrupt handler. In order to avoid the playback inter- |
2527 | * fered by cross talk process, the driver make the playback | |
2528 | * preparation halted until cross talk process finish. | |
2529 | */ | |
2263fddc | 2530 | nau8825_sema_acquire(nau8825, 3 * HZ); |
aee02c75 JH |
2531 | /* If FLL reference input is from low frequency source, |
2532 | * higher error gain can apply such as 0xf which has | |
2533 | * the most sensitive gain error correction threshold, | |
2534 | * Therefore, FLL has the most accurate DCO to | |
2535 | * target frequency. | |
2536 | */ | |
70543c30 | 2537 | regmap_update_bits(regmap, NAU8825_REG_FLL3, |
aee02c75 JH |
2538 | NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK, |
2539 | NAU8825_FLL_CLK_SRC_BLK | | |
2540 | (0xf << NAU8825_GAIN_ERR_SFT)); | |
3dfcd346 | 2541 | /* Release the semaphore. */ |
b50455fa JH |
2542 | nau8825_sema_release(nau8825); |
2543 | ||
70543c30 JH |
2544 | if (nau8825->mclk_freq) { |
2545 | clk_disable_unprepare(nau8825->mclk); | |
2546 | nau8825->mclk_freq = 0; | |
2547 | } | |
34ca27f3 | 2548 | |
70543c30 JH |
2549 | break; |
2550 | case NAU8825_CLK_FLL_FS: | |
3dfcd346 | 2551 | /* Acquire the semaphore to synchronize the playback and |
b50455fa JH |
2552 | * interrupt handler. In order to avoid the playback inter- |
2553 | * fered by cross talk process, the driver make the playback | |
2554 | * preparation halted until cross talk process finish. | |
2555 | */ | |
2263fddc | 2556 | nau8825_sema_acquire(nau8825, 3 * HZ); |
aee02c75 JH |
2557 | /* If FLL reference input is from low frequency source, |
2558 | * higher error gain can apply such as 0xf which has | |
2559 | * the most sensitive gain error correction threshold, | |
2560 | * Therefore, FLL has the most accurate DCO to | |
2561 | * target frequency. | |
2562 | */ | |
70543c30 | 2563 | regmap_update_bits(regmap, NAU8825_REG_FLL3, |
aee02c75 JH |
2564 | NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK, |
2565 | NAU8825_FLL_CLK_SRC_FS | | |
2566 | (0xf << NAU8825_GAIN_ERR_SFT)); | |
3dfcd346 | 2567 | /* Release the semaphore. */ |
b50455fa JH |
2568 | nau8825_sema_release(nau8825); |
2569 | ||
34ca27f3 AP |
2570 | if (nau8825->mclk_freq) { |
2571 | clk_disable_unprepare(nau8825->mclk); | |
2572 | nau8825->mclk_freq = 0; | |
2573 | } | |
2574 | ||
2575 | break; | |
2576 | default: | |
2577 | dev_err(nau8825->dev, "Invalid clock id (%d)\n", clk_id); | |
2578 | return -EINVAL; | |
2579 | } | |
2580 | ||
2581 | dev_dbg(nau8825->dev, "Sysclk is %dHz and clock id is %d\n", freq, | |
2582 | clk_id); | |
2583 | return 0; | |
2584 | } | |
2585 | ||
45101122 | 2586 | static int nau8825_set_sysclk(struct snd_soc_component *component, int clk_id, |
34ca27f3 AP |
2587 | int source, unsigned int freq, int dir) |
2588 | { | |
45101122 | 2589 | struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); |
34ca27f3 AP |
2590 | |
2591 | return nau8825_configure_sysclk(nau8825, clk_id, freq); | |
2592 | } | |
2593 | ||
2ec30f60 JH |
2594 | static int nau8825_resume_setup(struct nau8825 *nau8825) |
2595 | { | |
2596 | struct regmap *regmap = nau8825->regmap; | |
2597 | ||
2598 | /* Close clock when jack type detection at manual mode */ | |
2599 | nau8825_configure_sysclk(nau8825, NAU8825_CLK_DIS, 0); | |
2600 | ||
2601 | /* Clear all interruption status */ | |
2602 | nau8825_int_status_clear_all(regmap); | |
2603 | ||
2604 | /* Enable both insertion and ejection interruptions, and then | |
2605 | * bypass de-bounce circuit. | |
2606 | */ | |
2607 | regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, | |
2608 | NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_HEADSET_COMPLETE_EN | | |
2609 | NAU8825_IRQ_EJECT_EN | NAU8825_IRQ_INSERT_EN, | |
2610 | NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_HEADSET_COMPLETE_EN); | |
2611 | regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL, | |
2612 | NAU8825_JACK_DET_DB_BYPASS, NAU8825_JACK_DET_DB_BYPASS); | |
2613 | regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL, | |
2614 | NAU8825_IRQ_INSERT_DIS | NAU8825_IRQ_EJECT_DIS, 0); | |
2615 | ||
2616 | return 0; | |
2617 | } | |
2618 | ||
45101122 | 2619 | static int nau8825_set_bias_level(struct snd_soc_component *component, |
34ca27f3 AP |
2620 | enum snd_soc_bias_level level) |
2621 | { | |
45101122 | 2622 | struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); |
34ca27f3 AP |
2623 | int ret; |
2624 | ||
2625 | switch (level) { | |
2626 | case SND_SOC_BIAS_ON: | |
2627 | break; | |
2628 | ||
2629 | case SND_SOC_BIAS_PREPARE: | |
2630 | break; | |
2631 | ||
2632 | case SND_SOC_BIAS_STANDBY: | |
45101122 | 2633 | if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { |
34ca27f3 AP |
2634 | if (nau8825->mclk_freq) { |
2635 | ret = clk_prepare_enable(nau8825->mclk); | |
2636 | if (ret) { | |
45101122 | 2637 | dev_err(nau8825->dev, "Unable to prepare component mclk\n"); |
34ca27f3 AP |
2638 | return ret; |
2639 | } | |
2640 | } | |
2ec30f60 JH |
2641 | /* Setup codec configuration after resume */ |
2642 | nau8825_resume_setup(nau8825); | |
34ca27f3 | 2643 | } |
34ca27f3 AP |
2644 | break; |
2645 | ||
2646 | case SND_SOC_BIAS_OFF: | |
8fe19795 JH |
2647 | /* Reset the configuration of jack type for detection */ |
2648 | /* Detach 2kOhm Resistors from MICBIAS to MICGND1/2 */ | |
2649 | regmap_update_bits(nau8825->regmap, NAU8825_REG_MIC_BIAS, | |
2650 | NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 0); | |
2651 | /* ground HPL/HPR, MICGRND1/2 */ | |
2652 | regmap_update_bits(nau8825->regmap, | |
2653 | NAU8825_REG_HSD_CTRL, 0xf, 0xf); | |
b50455fa JH |
2654 | /* Cancel and reset cross talk detection funciton */ |
2655 | nau8825_xtalk_cancel(nau8825); | |
2ec30f60 JH |
2656 | /* Turn off all interruptions before system shutdown. Keep the |
2657 | * interruption quiet before resume setup completes. | |
2658 | */ | |
2659 | regmap_write(nau8825->regmap, | |
2660 | NAU8825_REG_INTERRUPT_DIS_CTRL, 0xffff); | |
2661 | /* Disable ADC needed for interruptions at audo mode */ | |
2662 | regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL, | |
2663 | NAU8825_ENABLE_ADC, 0); | |
34ca27f3 AP |
2664 | if (nau8825->mclk_freq) |
2665 | clk_disable_unprepare(nau8825->mclk); | |
34ca27f3 AP |
2666 | break; |
2667 | } | |
2668 | return 0; | |
2669 | } | |
2670 | ||
45101122 | 2671 | static int __maybe_unused nau8825_suspend(struct snd_soc_component *component) |
e6cee900 | 2672 | { |
45101122 | 2673 | struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); |
e6cee900 BZ |
2674 | |
2675 | disable_irq(nau8825->irq); | |
45101122 | 2676 | snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF); |
8fe19795 JH |
2677 | /* Power down codec power; don't suppoet button wakeup */ |
2678 | snd_soc_dapm_disable_pin(nau8825->dapm, "SAR"); | |
2679 | snd_soc_dapm_disable_pin(nau8825->dapm, "MICBIAS"); | |
2680 | snd_soc_dapm_sync(nau8825->dapm); | |
e6cee900 BZ |
2681 | regcache_cache_only(nau8825->regmap, true); |
2682 | regcache_mark_dirty(nau8825->regmap); | |
2683 | ||
2684 | return 0; | |
2685 | } | |
2686 | ||
45101122 | 2687 | static int __maybe_unused nau8825_resume(struct snd_soc_component *component) |
e6cee900 | 2688 | { |
45101122 | 2689 | struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component); |
06746c67 | 2690 | int ret; |
e6cee900 | 2691 | |
e6cee900 BZ |
2692 | regcache_cache_only(nau8825->regmap, false); |
2693 | regcache_sync(nau8825->regmap); | |
ca6ac305 | 2694 | nau8825->xtalk_protect = true; |
06746c67 | 2695 | ret = nau8825_sema_acquire(nau8825, 0); |
70424d8e | 2696 | if (ret) |
06746c67 | 2697 | nau8825->xtalk_protect = false; |
e6cee900 BZ |
2698 | enable_irq(nau8825->irq); |
2699 | ||
e6cee900 BZ |
2700 | return 0; |
2701 | } | |
e6cee900 | 2702 | |
c6167e10 DL |
2703 | static int nau8825_set_jack(struct snd_soc_component *component, |
2704 | struct snd_soc_jack *jack, void *data) | |
2705 | { | |
2706 | return nau8825_enable_jack_detect(component, jack); | |
2707 | } | |
2708 | ||
45101122 KM |
2709 | static const struct snd_soc_component_driver nau8825_component_driver = { |
2710 | .probe = nau8825_component_probe, | |
2711 | .remove = nau8825_component_remove, | |
2712 | .set_sysclk = nau8825_set_sysclk, | |
2713 | .set_pll = nau8825_set_pll, | |
2714 | .set_bias_level = nau8825_set_bias_level, | |
2715 | .suspend = nau8825_suspend, | |
2716 | .resume = nau8825_resume, | |
2717 | .controls = nau8825_controls, | |
2718 | .num_controls = ARRAY_SIZE(nau8825_controls), | |
2719 | .dapm_widgets = nau8825_dapm_widgets, | |
2720 | .num_dapm_widgets = ARRAY_SIZE(nau8825_dapm_widgets), | |
2721 | .dapm_routes = nau8825_dapm_routes, | |
2722 | .num_dapm_routes = ARRAY_SIZE(nau8825_dapm_routes), | |
c6167e10 | 2723 | .set_jack = nau8825_set_jack, |
45101122 KM |
2724 | .suspend_bias_off = 1, |
2725 | .idle_bias_on = 1, | |
2726 | .use_pmdown_time = 1, | |
2727 | .endianness = 1, | |
34ca27f3 AP |
2728 | }; |
2729 | ||
2730 | static void nau8825_reset_chip(struct regmap *regmap) | |
2731 | { | |
2732 | regmap_write(regmap, NAU8825_REG_RESET, 0x00); | |
2733 | regmap_write(regmap, NAU8825_REG_RESET, 0x00); | |
2734 | } | |
2735 | ||
218d2ce2 BZ |
2736 | static void nau8825_print_device_properties(struct nau8825 *nau8825) |
2737 | { | |
2738 | int i; | |
2739 | struct device *dev = nau8825->dev; | |
2740 | ||
2741 | dev_dbg(dev, "jkdet-enable: %d\n", nau8825->jkdet_enable); | |
2742 | dev_dbg(dev, "jkdet-pull-enable: %d\n", nau8825->jkdet_pull_enable); | |
2743 | dev_dbg(dev, "jkdet-pull-up: %d\n", nau8825->jkdet_pull_up); | |
2744 | dev_dbg(dev, "jkdet-polarity: %d\n", nau8825->jkdet_polarity); | |
2745 | dev_dbg(dev, "micbias-voltage: %d\n", nau8825->micbias_voltage); | |
2746 | dev_dbg(dev, "vref-impedance: %d\n", nau8825->vref_impedance); | |
2747 | ||
2748 | dev_dbg(dev, "sar-threshold-num: %d\n", nau8825->sar_threshold_num); | |
2749 | for (i = 0; i < nau8825->sar_threshold_num; i++) | |
2750 | dev_dbg(dev, "sar-threshold[%d]=%d\n", i, | |
2751 | nau8825->sar_threshold[i]); | |
2752 | ||
2753 | dev_dbg(dev, "sar-hysteresis: %d\n", nau8825->sar_hysteresis); | |
2754 | dev_dbg(dev, "sar-voltage: %d\n", nau8825->sar_voltage); | |
2755 | dev_dbg(dev, "sar-compare-time: %d\n", nau8825->sar_compare_time); | |
2756 | dev_dbg(dev, "sar-sampling-time: %d\n", nau8825->sar_sampling_time); | |
2757 | dev_dbg(dev, "short-key-debounce: %d\n", nau8825->key_debounce); | |
2758 | dev_dbg(dev, "jack-insert-debounce: %d\n", | |
2759 | nau8825->jack_insert_debounce); | |
2760 | dev_dbg(dev, "jack-eject-debounce: %d\n", | |
2761 | nau8825->jack_eject_debounce); | |
226d7449 JH |
2762 | dev_dbg(dev, "crosstalk-enable: %d\n", |
2763 | nau8825->xtalk_enable); | |
ed857072 | 2764 | dev_dbg(dev, "adcout-drive-strong: %d\n", nau8825->adcout_ds); |
fc0b096c | 2765 | dev_dbg(dev, "adc-delay-ms: %d\n", nau8825->adc_delay); |
218d2ce2 BZ |
2766 | } |
2767 | ||
34ca27f3 AP |
2768 | static int nau8825_read_device_properties(struct device *dev, |
2769 | struct nau8825 *nau8825) { | |
403d2fef | 2770 | int ret; |
34ca27f3 AP |
2771 | |
2772 | nau8825->jkdet_enable = device_property_read_bool(dev, | |
2773 | "nuvoton,jkdet-enable"); | |
2774 | nau8825->jkdet_pull_enable = device_property_read_bool(dev, | |
2775 | "nuvoton,jkdet-pull-enable"); | |
2776 | nau8825->jkdet_pull_up = device_property_read_bool(dev, | |
2777 | "nuvoton,jkdet-pull-up"); | |
403d2fef | 2778 | ret = device_property_read_u32(dev, "nuvoton,jkdet-polarity", |
34ca27f3 | 2779 | &nau8825->jkdet_polarity); |
403d2fef JH |
2780 | if (ret) |
2781 | nau8825->jkdet_polarity = 1; | |
2782 | ret = device_property_read_u32(dev, "nuvoton,micbias-voltage", | |
34ca27f3 | 2783 | &nau8825->micbias_voltage); |
403d2fef JH |
2784 | if (ret) |
2785 | nau8825->micbias_voltage = 6; | |
2786 | ret = device_property_read_u32(dev, "nuvoton,vref-impedance", | |
34ca27f3 | 2787 | &nau8825->vref_impedance); |
403d2fef JH |
2788 | if (ret) |
2789 | nau8825->vref_impedance = 2; | |
2790 | ret = device_property_read_u32(dev, "nuvoton,sar-threshold-num", | |
34ca27f3 | 2791 | &nau8825->sar_threshold_num); |
403d2fef JH |
2792 | if (ret) |
2793 | nau8825->sar_threshold_num = 4; | |
2794 | ret = device_property_read_u32_array(dev, "nuvoton,sar-threshold", | |
34ca27f3 | 2795 | nau8825->sar_threshold, nau8825->sar_threshold_num); |
403d2fef JH |
2796 | if (ret) { |
2797 | nau8825->sar_threshold[0] = 0x08; | |
2798 | nau8825->sar_threshold[1] = 0x12; | |
2799 | nau8825->sar_threshold[2] = 0x26; | |
2800 | nau8825->sar_threshold[3] = 0x73; | |
2801 | } | |
2802 | ret = device_property_read_u32(dev, "nuvoton,sar-hysteresis", | |
34ca27f3 | 2803 | &nau8825->sar_hysteresis); |
403d2fef JH |
2804 | if (ret) |
2805 | nau8825->sar_hysteresis = 0; | |
2806 | ret = device_property_read_u32(dev, "nuvoton,sar-voltage", | |
34ca27f3 | 2807 | &nau8825->sar_voltage); |
403d2fef JH |
2808 | if (ret) |
2809 | nau8825->sar_voltage = 6; | |
2810 | ret = device_property_read_u32(dev, "nuvoton,sar-compare-time", | |
34ca27f3 | 2811 | &nau8825->sar_compare_time); |
403d2fef JH |
2812 | if (ret) |
2813 | nau8825->sar_compare_time = 1; | |
2814 | ret = device_property_read_u32(dev, "nuvoton,sar-sampling-time", | |
34ca27f3 | 2815 | &nau8825->sar_sampling_time); |
403d2fef JH |
2816 | if (ret) |
2817 | nau8825->sar_sampling_time = 1; | |
2818 | ret = device_property_read_u32(dev, "nuvoton,short-key-debounce", | |
34ca27f3 | 2819 | &nau8825->key_debounce); |
403d2fef JH |
2820 | if (ret) |
2821 | nau8825->key_debounce = 3; | |
2822 | ret = device_property_read_u32(dev, "nuvoton,jack-insert-debounce", | |
34ca27f3 | 2823 | &nau8825->jack_insert_debounce); |
403d2fef JH |
2824 | if (ret) |
2825 | nau8825->jack_insert_debounce = 7; | |
2826 | ret = device_property_read_u32(dev, "nuvoton,jack-eject-debounce", | |
34ca27f3 | 2827 | &nau8825->jack_eject_debounce); |
403d2fef JH |
2828 | if (ret) |
2829 | nau8825->jack_eject_debounce = 0; | |
226d7449 JH |
2830 | nau8825->xtalk_enable = device_property_read_bool(dev, |
2831 | "nuvoton,crosstalk-enable"); | |
ed857072 | 2832 | nau8825->adcout_ds = device_property_read_bool(dev, "nuvoton,adcout-drive-strong"); |
fc0b096c DL |
2833 | ret = device_property_read_u32(dev, "nuvoton,adc-delay-ms", &nau8825->adc_delay); |
2834 | if (ret) | |
2835 | nau8825->adc_delay = 125; | |
5f3d94eb | 2836 | if (nau8825->adc_delay < 125 || nau8825->adc_delay > 500) |
fc0b096c | 2837 | dev_warn(dev, "Please set the suitable delay time!\n"); |
34ca27f3 | 2838 | |
71d322fd CR |
2839 | nau8825->mclk = devm_clk_get_optional(dev, "mclk"); |
2840 | if (IS_ERR(nau8825->mclk)) | |
2841 | return PTR_ERR(nau8825->mclk); | |
2842 | if (!nau8825->mclk) | |
34ca27f3 | 2843 | /* The MCLK is managed externally or not used at all */ |
34ca27f3 | 2844 | dev_info(dev, "No 'mclk' clock found, assume MCLK is managed externally"); |
34ca27f3 AP |
2845 | |
2846 | return 0; | |
2847 | } | |
2848 | ||
2849 | static int nau8825_setup_irq(struct nau8825 *nau8825) | |
2850 | { | |
34ca27f3 AP |
2851 | int ret; |
2852 | ||
34ca27f3 AP |
2853 | ret = devm_request_threaded_irq(nau8825->dev, nau8825->irq, NULL, |
2854 | nau8825_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT, | |
2855 | "nau8825", nau8825); | |
2856 | ||
2857 | if (ret) { | |
2858 | dev_err(nau8825->dev, "Cannot request irq %d (%d)\n", | |
2859 | nau8825->irq, ret); | |
2860 | return ret; | |
2861 | } | |
2862 | ||
2863 | return 0; | |
2864 | } | |
2865 | ||
7325ed4d | 2866 | static int nau8825_i2c_probe(struct i2c_client *i2c) |
34ca27f3 AP |
2867 | { |
2868 | struct device *dev = &i2c->dev; | |
2869 | struct nau8825 *nau8825 = dev_get_platdata(&i2c->dev); | |
2870 | int ret, value; | |
2871 | ||
2872 | if (!nau8825) { | |
2873 | nau8825 = devm_kzalloc(dev, sizeof(*nau8825), GFP_KERNEL); | |
2874 | if (!nau8825) | |
2875 | return -ENOMEM; | |
2876 | ret = nau8825_read_device_properties(dev, nau8825); | |
2877 | if (ret) | |
2878 | return ret; | |
2879 | } | |
2880 | ||
2881 | i2c_set_clientdata(i2c, nau8825); | |
2882 | ||
2883 | nau8825->regmap = devm_regmap_init_i2c(i2c, &nau8825_regmap_config); | |
2884 | if (IS_ERR(nau8825->regmap)) | |
2885 | return PTR_ERR(nau8825->regmap); | |
2886 | nau8825->dev = dev; | |
2887 | nau8825->irq = i2c->irq; | |
3dfcd346 | 2888 | /* Initiate parameters, semaphore and work queue which are needed in |
b50455fa JH |
2889 | * cross talk suppression measurment function. |
2890 | */ | |
2891 | nau8825->xtalk_state = NAU8825_XTALK_DONE; | |
2892 | nau8825->xtalk_protect = false; | |
fa25b4f5 | 2893 | nau8825->xtalk_baktab_initialized = false; |
b50455fa JH |
2894 | sema_init(&nau8825->xtalk_sem, 1); |
2895 | INIT_WORK(&nau8825->xtalk_work, nau8825_xtalk_work); | |
34ca27f3 | 2896 | |
218d2ce2 BZ |
2897 | nau8825_print_device_properties(nau8825); |
2898 | ||
34ca27f3 AP |
2899 | nau8825_reset_chip(nau8825->regmap); |
2900 | ret = regmap_read(nau8825->regmap, NAU8825_REG_I2C_DEVICE_ID, &value); | |
2901 | if (ret < 0) { | |
2902 | dev_err(dev, "Failed to read device id from the NAU8825: %d\n", | |
2903 | ret); | |
2904 | return ret; | |
2905 | } | |
b81a2cc9 DL |
2906 | nau8825->sw_id = value & NAU8825_SOFTWARE_ID_MASK; |
2907 | switch (nau8825->sw_id) { | |
2908 | case NAU8825_SOFTWARE_ID_NAU8825: | |
2909 | break; | |
2910 | case NAU8825_SOFTWARE_ID_NAU8825C: | |
2911 | ret = regmap_register_patch(nau8825->regmap, nau8825_regmap_patch, | |
2912 | ARRAY_SIZE(nau8825_regmap_patch)); | |
2913 | if (ret) { | |
2914 | dev_err(dev, "Failed to register Rev C patch: %d\n", ret); | |
2915 | return ret; | |
2916 | } | |
2917 | break; | |
2918 | default: | |
34ca27f3 AP |
2919 | dev_err(dev, "Not a NAU8825 chip\n"); |
2920 | return -ENODEV; | |
2921 | } | |
2922 | ||
2923 | nau8825_init_regs(nau8825); | |
2924 | ||
2925 | if (i2c->irq) | |
2926 | nau8825_setup_irq(nau8825); | |
2927 | ||
45101122 KM |
2928 | return devm_snd_soc_register_component(&i2c->dev, |
2929 | &nau8825_component_driver, | |
34ca27f3 AP |
2930 | &nau8825_dai, 1); |
2931 | } | |
2932 | ||
ed5c2f5f UKK |
2933 | static void nau8825_i2c_remove(struct i2c_client *client) |
2934 | {} | |
34ca27f3 AP |
2935 | |
2936 | static const struct i2c_device_id nau8825_i2c_ids[] = { | |
ba2a2c37 | 2937 | { "nau8825" }, |
34ca27f3 AP |
2938 | { } |
2939 | }; | |
ffd72505 | 2940 | MODULE_DEVICE_TABLE(i2c, nau8825_i2c_ids); |
34ca27f3 AP |
2941 | |
2942 | #ifdef CONFIG_OF | |
2943 | static const struct of_device_id nau8825_of_ids[] = { | |
2944 | { .compatible = "nuvoton,nau8825", }, | |
2945 | {} | |
2946 | }; | |
2947 | MODULE_DEVICE_TABLE(of, nau8825_of_ids); | |
2948 | #endif | |
2949 | ||
b3681308 FY |
2950 | #ifdef CONFIG_ACPI |
2951 | static const struct acpi_device_id nau8825_acpi_match[] = { | |
2952 | { "10508825", 0 }, | |
2953 | {}, | |
2954 | }; | |
2955 | MODULE_DEVICE_TABLE(acpi, nau8825_acpi_match); | |
2956 | #endif | |
2957 | ||
34ca27f3 AP |
2958 | static struct i2c_driver nau8825_driver = { |
2959 | .driver = { | |
2960 | .name = "nau8825", | |
34ca27f3 | 2961 | .of_match_table = of_match_ptr(nau8825_of_ids), |
b3681308 | 2962 | .acpi_match_table = ACPI_PTR(nau8825_acpi_match), |
34ca27f3 | 2963 | }, |
9abcd240 | 2964 | .probe = nau8825_i2c_probe, |
34ca27f3 AP |
2965 | .remove = nau8825_i2c_remove, |
2966 | .id_table = nau8825_i2c_ids, | |
2967 | }; | |
2968 | module_i2c_driver(nau8825_driver); | |
2969 | ||
2970 | MODULE_DESCRIPTION("ASoC nau8825 driver"); | |
2971 | MODULE_AUTHOR("Anatol Pomozov <anatol@chromium.org>"); | |
2972 | MODULE_LICENSE("GPL"); |