[linux-block.git] / sound / soc / codecs / nau8824.h

/*
 * NAU88L24 ALSA SoC audio driver
 *
 * Copyright 2016 Nuvoton Technology Corp.
 * Author: John Hsu <KCHSU0@nuvoton.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef __NAU8824_H__
#define __NAU8824_H__

#define NAU8824_REG_RESET			0x00
#define NAU8824_REG_ENA_CTRL			0x01
#define NAU8824_REG_CLK_GATING_ENA		0x02
#define NAU8824_REG_CLK_DIVIDER		0x03
#define NAU8824_REG_FLL1			0x04
#define NAU8824_REG_FLL2			0x05
#define NAU8824_REG_FLL3			0x06
#define NAU8824_REG_FLL4			0x07
#define NAU8824_REG_FLL5			0x08
#define NAU8824_REG_FLL6			0x09
#define NAU8824_REG_FLL_VCO_RSV		0x0A
#define NAU8824_REG_JACK_DET_CTRL		0x0D
#define NAU8824_REG_INTERRUPT_SETTING_1	0x0F
#define NAU8824_REG_IRQ			0x10
#define NAU8824_REG_CLEAR_INT_REG		0x11
#define NAU8824_REG_INTERRUPT_SETTING	0x12
#define NAU8824_REG_SAR_ADC			0x13
#define NAU8824_REG_VDET_COEFFICIENT		0x14
#define NAU8824_REG_VDET_THRESHOLD_1	0x15
#define NAU8824_REG_VDET_THRESHOLD_2	0x16
#define NAU8824_REG_VDET_THRESHOLD_3	0x17
#define NAU8824_REG_VDET_THRESHOLD_4	0x18
#define NAU8824_REG_GPIO_SEL			0x1A
#define NAU8824_REG_PORT0_I2S_PCM_CTRL_1	0x1C
#define NAU8824_REG_PORT0_I2S_PCM_CTRL_2	0x1D
#define NAU8824_REG_PORT0_LEFT_TIME_SLOT	0x1E
#define NAU8824_REG_PORT0_RIGHT_TIME_SLOT	0x1F
#define NAU8824_REG_TDM_CTRL			0x20
#define NAU8824_REG_ADC_HPF_FILTER		0x23
#define NAU8824_REG_ADC_FILTER_CTRL		0x24
#define NAU8824_REG_DAC_FILTER_CTRL_1	0x25
#define NAU8824_REG_DAC_FILTER_CTRL_2	0x26
#define NAU8824_REG_NOTCH_FILTER_1		0x27
#define NAU8824_REG_NOTCH_FILTER_2		0x28
#define NAU8824_REG_EQ1_LOW			0x29
#define NAU8824_REG_EQ2_EQ3			0x2A
#define NAU8824_REG_EQ4_EQ5			0x2B
#define NAU8824_REG_ADC_CH0_DGAIN_CTRL	0x2D
#define NAU8824_REG_ADC_CH1_DGAIN_CTRL	0x2E
#define NAU8824_REG_ADC_CH2_DGAIN_CTRL	0x2F
#define NAU8824_REG_ADC_CH3_DGAIN_CTRL	0x30
#define NAU8824_REG_DAC_MUTE_CTRL		0x31
#define NAU8824_REG_DAC_CH0_DGAIN_CTRL	0x32
#define NAU8824_REG_DAC_CH1_DGAIN_CTRL	0x33
#define NAU8824_REG_ADC_TO_DAC_ST		0x34
#define NAU8824_REG_DRC_KNEE_IP12_ADC_CH01	0x38
#define NAU8824_REG_DRC_KNEE_IP34_ADC_CH01	0x39
#define NAU8824_REG_DRC_SLOPE_ADC_CH01	0x3A
#define NAU8824_REG_DRC_ATKDCY_ADC_CH01	0x3B
#define NAU8824_REG_DRC_KNEE_IP12_ADC_CH23	0x3C
#define NAU8824_REG_DRC_KNEE_IP34_ADC_CH23	0x3D
#define NAU8824_REG_DRC_SLOPE_ADC_CH23	0x3E
#define NAU8824_REG_DRC_ATKDCY_ADC_CH23	0x3F
#define NAU8824_REG_DRC_GAINL_ADC0		0x40
#define NAU8824_REG_DRC_GAINL_ADC1		0x41
#define NAU8824_REG_DRC_GAINL_ADC2		0x42
#define NAU8824_REG_DRC_GAINL_ADC3		0x43
#define NAU8824_REG_DRC_KNEE_IP12_DAC	0x45
#define NAU8824_REG_DRC_KNEE_IP34_DAC	0x46
#define NAU8824_REG_DRC_SLOPE_DAC		0x47
#define NAU8824_REG_DRC_ATKDCY_DAC		0x48
#define NAU8824_REG_DRC_GAIN_DAC_CH0	0x49
#define NAU8824_REG_DRC_GAIN_DAC_CH1	0x4A
#define NAU8824_REG_MODE			0x4C
#define NAU8824_REG_MODE1			0x4D
#define NAU8824_REG_MODE2			0x4E
#define NAU8824_REG_CLASSG			0x50
#define NAU8824_REG_OTP_EFUSE			0x51
#define NAU8824_REG_OTPDOUT_1		0x53
#define NAU8824_REG_OTPDOUT_2		0x54
#define NAU8824_REG_MISC_CTRL			0x55
#define NAU8824_REG_I2C_TIMEOUT		0x56
#define NAU8824_REG_TEST_MODE		0x57
#define NAU8824_REG_I2C_DEVICE_ID		0x58
#define NAU8824_REG_SAR_ADC_DATA_OUT	0x59
#define NAU8824_REG_BIAS_ADJ			0x66
#define NAU8824_REG_PGA_GAIN			0x67
#define NAU8824_REG_TRIM_SETTINGS		0x68
#define NAU8824_REG_ANALOG_CONTROL_1	0x69
#define NAU8824_REG_ANALOG_CONTROL_2	0x6A
#define NAU8824_REG_ENABLE_LO			0x6B
#define NAU8824_REG_GAIN_LO			0x6C
#define NAU8824_REG_CLASSD_GAIN_1		0x6D
#define NAU8824_REG_CLASSD_GAIN_2		0x6E
#define NAU8824_REG_ANALOG_ADC_1		0x71
#define NAU8824_REG_ANALOG_ADC_2		0x72
#define NAU8824_REG_RDAC			0x73
#define NAU8824_REG_MIC_BIAS			0x74
#define NAU8824_REG_HS_VOLUME_CONTROL	0x75
#define NAU8824_REG_BOOST			0x76
#define NAU8824_REG_FEPGA			0x77
#define NAU8824_REG_FEPGA_II			0x78
#define NAU8824_REG_FEPGA_SE			0x79
#define NAU8824_REG_FEPGA_ATTENUATION	0x7A
#define NAU8824_REG_ATT_PORT0		0x7B
#define NAU8824_REG_ATT_PORT1		0x7C
#define NAU8824_REG_POWER_UP_CONTROL	0x7F
#define NAU8824_REG_CHARGE_PUMP_CONTROL	0x80
#define NAU8824_REG_CHARGE_PUMP_INPUT	0x81
#define NAU8824_REG_MAX			NAU8824_REG_CHARGE_PUMP_INPUT
/* 16-bit control register address, and 16-bits control register data */
#define NAU8824_REG_ADDR_LEN		16
#define NAU8824_REG_DATA_LEN		16


/* ENA_CTRL (0x1) */
#define NAU8824_DMIC_LCH_EDGE_CH23	(0x1 << 12)
#define NAU8824_DMIC_LCH_EDGE_CH01	(0x1 << 11)
#define NAU8824_JD_SLEEP_MODE		(0x1 << 10)
#define NAU8824_ADC_CH3_DMIC_SFT	9
#define NAU8824_ADC_CH3_DMIC_EN	(0x1 << NAU8824_ADC_CH3_DMIC_SFT)
#define NAU8824_ADC_CH2_DMIC_SFT	8
#define NAU8824_ADC_CH2_DMIC_EN	(0x1 << NAU8824_ADC_CH2_DMIC_SFT)
#define NAU8824_ADC_CH1_DMIC_SFT	7
#define NAU8824_ADC_CH1_DMIC_EN	(0x1 << NAU8824_ADC_CH1_DMIC_SFT)
#define NAU8824_ADC_CH0_DMIC_SFT	6
#define NAU8824_ADC_CH0_DMIC_EN	(0x1 << NAU8824_ADC_CH0_DMIC_SFT)
#define NAU8824_DAC_CH1_EN		(0x1 << 5)
#define NAU8824_DAC_CH0_EN		(0x1 << 4)
#define NAU8824_ADC_CH3_EN		(0x1 << 3)
#define NAU8824_ADC_CH2_EN		(0x1 << 2)
#define NAU8824_ADC_CH1_EN		(0x1 << 1)
#define NAU8824_ADC_CH0_EN		0x1

/* CLK_GATING_ENA (0x02) */
#define NAU8824_CLK_ADC_CH23_EN	(0x1 << 15)
#define NAU8824_CLK_ADC_CH01_EN	(0x1 << 14)
#define NAU8824_CLK_DAC_CH1_EN	(0x1 << 13)
#define NAU8824_CLK_DAC_CH0_EN	(0x1 << 12)
#define NAU8824_CLK_I2S_EN		(0x1 << 7)
#define NAU8824_CLK_GAIN_EN		(0x1 << 5)
#define NAU8824_CLK_SAR_EN		(0x1 << 3)
#define NAU8824_CLK_DMIC_CH23_EN	(0x1 << 1)

/* CLK_DIVIDER (0x3) */
#define NAU8824_CLK_SRC_SFT		15
#define NAU8824_CLK_SRC_MASK		(1 << NAU8824_CLK_SRC_SFT)
#define NAU8824_CLK_SRC_VCO		(1 << NAU8824_CLK_SRC_SFT)
#define NAU8824_CLK_SRC_MCLK		(0 << NAU8824_CLK_SRC_SFT)
#define NAU8824_CLK_MCLK_SRC_MASK	(0xf << 0)
#define NAU8824_CLK_DMIC_SRC_SFT	10
#define NAU8824_CLK_DMIC_SRC_MASK	(0x7 << NAU8824_CLK_DMIC_SRC_SFT)
#define NAU8824_CLK_ADC_SRC_SFT	6
#define NAU8824_CLK_ADC_SRC_MASK	(0x3 << NAU8824_CLK_ADC_SRC_SFT)
#define NAU8824_CLK_DAC_SRC_SFT	4
#define NAU8824_CLK_DAC_SRC_MASK	(0x3 << NAU8824_CLK_DAC_SRC_SFT)

/* FLL1 (0x04) */
#define NAU8824_FLL_RATIO_MASK	(0x7f << 0)

/* FLL3 (0x06) */
#define NAU8824_FLL_INTEGER_MASK	(0x3ff << 0)
#define NAU8824_FLL_CLK_SRC_SFT	10
#define NAU8824_FLL_CLK_SRC_MASK	(0x3 << NAU8824_FLL_CLK_SRC_SFT)
#define NAU8824_FLL_CLK_SRC_MCLK	(0 << NAU8824_FLL_CLK_SRC_SFT)
#define NAU8824_FLL_CLK_SRC_BLK	(0x2 << NAU8824_FLL_CLK_SRC_SFT)
#define NAU8824_FLL_CLK_SRC_FS		(0x3 << NAU8824_FLL_CLK_SRC_SFT)

/* FLL4 (0x07) */
#define NAU8824_FLL_REF_DIV_SFT	10
#define NAU8824_FLL_REF_DIV_MASK	(0x3 << NAU8824_FLL_REF_DIV_SFT)

/* FLL5 (0x08) */
#define NAU8824_FLL_PDB_DAC_EN	(0x1 << 15)
#define NAU8824_FLL_LOOP_FTR_EN	(0x1 << 14)
#define NAU8824_FLL_CLK_SW_MASK	(0x1 << 13)
#define NAU8824_FLL_CLK_SW_N2		(0x1 << 13)
#define NAU8824_FLL_CLK_SW_REF	(0x0 << 13)
#define NAU8824_FLL_FTR_SW_MASK	(0x1 << 12)
#define NAU8824_FLL_FTR_SW_ACCU	(0x1 << 12)
#define NAU8824_FLL_FTR_SW_FILTER	(0x0 << 12)

/* FLL6 (0x9) */
#define NAU8824_DCO_EN			(0x1 << 15)
#define NAU8824_SDM_EN			(0x1 << 14)

/* IRQ (0x10) */
#define NAU8824_SHORT_CIRCUIT_IRQ		(0x1 << 7)
#define NAU8824_IMPEDANCE_MEAS_IRQ		(0x1 << 6)
#define NAU8824_KEY_RELEASE_IRQ		(0x1 << 5)
#define NAU8824_KEY_LONG_PRESS_IRQ		(0x1 << 4)
#define NAU8824_KEY_SHORT_PRESS_IRQ		(0x1 << 3)
#define NAU8824_JACK_EJECTION_DETECTED	(0x1 << 1)
#define NAU8824_JACK_INSERTION_DETECTED	0x1

/* JACK_DET_CTRL (0x0D) */
#define NAU8824_JACK_EJECT_DT_SFT	2
#define NAU8824_JACK_EJECT_DT_MASK (0x3 << NAU8824_JACK_EJECT_DT_SFT)
#define NAU8824_JACK_LOGIC		0x1


/* INTERRUPT_SETTING_1 (0x0F) */
#define NAU8824_IRQ_EJECT_EN		(0x1 << 9)
#define NAU8824_IRQ_INSERT_EN		(0x1 << 8)

/* INTERRUPT_SETTING (0x12) */
#define NAU8824_IRQ_KEY_RELEASE_DIS		(0x1 << 5)
#define NAU8824_IRQ_KEY_SHORT_PRESS_DIS	(0x1 << 3)
#define NAU8824_IRQ_EJECT_DIS			(0x1 << 1)
#define NAU8824_IRQ_INSERT_DIS		0x1

/* SAR_ADC (0x13) */
#define NAU8824_SAR_ADC_EN_SFT		12
#define NAU8824_SAR_TRACKING_GAIN_SFT	8
#define NAU8824_SAR_TRACKING_GAIN_MASK	(0x7 << NAU8824_SAR_TRACKING_GAIN_SFT)
#define NAU8824_SAR_COMPARE_TIME_SFT	2
#define NAU8824_SAR_COMPARE_TIME_MASK	(3 << 2)
#define NAU8824_SAR_SAMPLING_TIME_SFT	0
#define NAU8824_SAR_SAMPLING_TIME_MASK	(3 << 0)

/* VDET_COEFFICIENT (0x14) */
#define NAU8824_SHORTKEY_DEBOUNCE_SFT	12
#define NAU8824_SHORTKEY_DEBOUNCE_MASK	(0x3 << NAU8824_SHORTKEY_DEBOUNCE_SFT)
#define NAU8824_LEVELS_NR_SFT			8
#define NAU8824_LEVELS_NR_MASK		(0x7 << 8)
#define NAU8824_HYSTERESIS_SFT		0
#define NAU8824_HYSTERESIS_MASK		0xf

/* PORT0_I2S_PCM_CTRL_1 (0x1C) */
#define NAU8824_I2S_BP_SFT		7
#define NAU8824_I2S_BP_MASK		(1 << NAU8824_I2S_BP_SFT)
#define NAU8824_I2S_BP_INV		(1 << NAU8824_I2S_BP_SFT)
#define NAU8824_I2S_PCMB_SFT		6
#define NAU8824_I2S_PCMB_EN		(1 << NAU8824_I2S_PCMB_SFT)
#define NAU8824_I2S_DL_SFT		2
#define NAU8824_I2S_DL_MASK		(0x3 << NAU8824_I2S_DL_SFT)
#define NAU8824_I2S_DL_16		(0 << NAU8824_I2S_DL_SFT)
#define NAU8824_I2S_DL_20		(1 << NAU8824_I2S_DL_SFT)
#define NAU8824_I2S_DL_24		(2 << NAU8824_I2S_DL_SFT)
#define NAU8824_I2S_DL_32		(3 << NAU8824_I2S_DL_SFT)
#define NAU8824_I2S_DF_MASK		0x3
#define NAU8824_I2S_DF_RIGTH		0
#define NAU8824_I2S_DF_LEFT		1
#define NAU8824_I2S_DF_I2S		2
#define NAU8824_I2S_DF_PCM_AB		3


/* PORT0_I2S_PCM_CTRL_2 (0x1D) */
#define NAU8824_I2S_LRC_DIV_SFT	12
#define NAU8824_I2S_LRC_DIV_MASK	(0x3 << NAU8824_I2S_LRC_DIV_SFT)
#define NAU8824_I2S_MS_SFT		3
#define NAU8824_I2S_MS_MASK		(1 << NAU8824_I2S_MS_SFT)
#define NAU8824_I2S_MS_MASTER		(1 << NAU8824_I2S_MS_SFT)
#define NAU8824_I2S_MS_SLAVE		(0 << NAU8824_I2S_MS_SFT)
#define NAU8824_I2S_BLK_DIV_MASK	0x7

/* PORT0_LEFT_TIME_SLOT (0x1E) */
#define NAU8824_TSLOT_L_MASK	0x3ff

/* TDM_CTRL (0x20) */
#define NAU8824_TDM_MODE		(0x1 << 15)
#define NAU8824_TDM_OFFSET_EN		(0x1 << 14)
#define NAU8824_TDM_DACL_RX_SFT	6
#define NAU8824_TDM_DACL_RX_MASK	(0x3 << NAU8824_TDM_DACL_RX_SFT)
#define NAU8824_TDM_DACR_RX_SFT	4
#define NAU8824_TDM_DACR_RX_MASK	(0x3 << NAU8824_TDM_DACR_RX_SFT)
#define NAU8824_TDM_TX_MASK		0xf

/* ADC_FILTER_CTRL (0x24) */
#define NAU8824_ADC_SYNC_DOWN_MASK	0x3
#define NAU8824_ADC_SYNC_DOWN_32	0
#define NAU8824_ADC_SYNC_DOWN_64	1
#define NAU8824_ADC_SYNC_DOWN_128	2
#define NAU8824_ADC_SYNC_DOWN_256	3

/* DAC_FILTER_CTRL_1 (0x25) */
#define NAU8824_DAC_CICCLP_OFF	(0x1 << 7)
#define NAU8824_DAC_OVERSAMPLE_MASK	0x7
#define NAU8824_DAC_OVERSAMPLE_64	0
#define NAU8824_DAC_OVERSAMPLE_256	1
#define NAU8824_DAC_OVERSAMPLE_128	2
#define NAU8824_DAC_OVERSAMPLE_32	4

/* DAC_MUTE_CTRL (0x31) */
#define NAU8824_DAC_CH01_MIX		0x3
#define NAU8824_DAC_ZC_EN		(0x1 << 11)

/* DAC_CH0_DGAIN_CTRL (0x32) */
#define NAU8824_DAC_CH0_SEL_SFT	9
#define NAU8824_DAC_CH0_SEL_MASK	(0x1 << NAU8824_DAC_CH0_SEL_SFT)
#define NAU8824_DAC_CH0_SEL_I2S0	(0x0 << NAU8824_DAC_CH0_SEL_SFT)
#define NAU8824_DAC_CH0_SEL_I2S1	(0x1 << NAU8824_DAC_CH0_SEL_SFT)
#define NAU8824_DAC_CH0_VOL_MASK	0x1ff

/* DAC_CH1_DGAIN_CTRL (0x33) */
#define NAU8824_DAC_CH1_SEL_SFT	9
#define NAU8824_DAC_CH1_SEL_MASK	(0x1 << NAU8824_DAC_CH1_SEL_SFT)
#define NAU8824_DAC_CH1_SEL_I2S0	(0x0 << NAU8824_DAC_CH1_SEL_SFT)
#define NAU8824_DAC_CH1_SEL_I2S1	(0x1 << NAU8824_DAC_CH1_SEL_SFT)
#define NAU8824_DAC_CH1_VOL_MASK	0x1ff

/* CLASSG (0x50) */
#define NAU8824_CLASSG_TIMER_SFT	8
#define NAU8824_CLASSG_TIMER_MASK	(0x3f << NAU8824_CLASSG_TIMER_SFT)
#define NAU8824_CLASSG_LDAC_EN_SFT	2
#define NAU8824_CLASSG_RDAC_EN_SFT	1
#define NAU8824_CLASSG_EN_SFT		0

/* SAR_ADC_DATA_OUT (0x59) */
#define NAU8824_SAR_ADC_DATA_MASK	0xff

/* BIAS_ADJ (0x66) */
#define NAU8824_VMID			(1 << 6)
#define NAU8824_VMID_SEL_SFT		4
#define NAU8824_VMID_SEL_MASK		(3 << NAU8824_VMID_SEL_SFT)
#define NAU8824_DMIC2_EN_SFT		3
#define NAU8824_DMIC1_EN_SFT		2

/* TRIM_SETTINGS (0x68) */
#define NAU8824_DRV_CURR_INC		(1 << 15)

/* ANALOG_CONTROL_1 (0x69) */
#define NAU8824_DMIC_CLK_DRV_STRG	(1 << 3)
#define NAU8824_DMIC_CLK_SLEW_FAST	(0x7)

/* ANALOG_CONTROL_2 (0x6A) */
#define NAU8824_CLASSD_CLAMP_DIS_SFT	3
#define NAU8824_CLASSD_CLAMP_DIS	(0x1 << NAU8824_CLASSD_CLAMP_DIS_SFT)

/* ENABLE_LO (0x6B) */
#define NAU8824_TEST_DAC_SFT		14
#define NAU8824_TEST_DAC_EN		(0x3 << NAU8824_TEST_DAC_SFT)
#define NAU8824_DACL_HPR_EN_SFT	3
#define NAU8824_DACL_HPR_EN		(0x1 << NAU8824_DACL_HPR_EN_SFT)
#define NAU8824_DACR_HPR_EN_SFT	2
#define NAU8824_DACR_HPR_EN		(0x1 << NAU8824_DACR_HPR_EN_SFT)
#define NAU8824_DACR_HPL_EN_SFT	1
#define NAU8824_DACR_HPL_EN		(0x1 << NAU8824_DACR_HPL_EN_SFT)
#define NAU8824_DACL_HPL_EN_SFT	0
#define NAU8824_DACL_HPL_EN		0x1

/* CLASSD_GAIN_1 (0x6D) */
#define NAU8824_CLASSD_GAIN_1R_SFT	8
#define NAU8824_CLASSD_GAIN_1R_MASK	(0x1f << NAU8824_CLASSD_GAIN_1R_SFT)
#define NAU8824_CLASSD_EN_SFT		7
#define NAU8824_CLASSD_EN		(0x1 << NAU8824_CLASSD_EN_SFT)
#define NAU8824_CLASSD_GAIN_1L_MASK	0x1f

/* CLASSD_GAIN_2 (0x6E) */
#define NAU8824_CLASSD_GAIN_2R_SFT	8
#define NAU8824_CLASSD_GAIN_2R_MASK	(0x1f << NAU8824_CLASSD_GAIN_1R_SFT)
#define NAU8824_CLASSD_EN_SFT		7
#define NAU8824_CLASSD_EN		(0x1 << NAU8824_CLASSD_EN_SFT)
#define NAU8824_CLASSD_GAIN_2L_MASK	0x1f

/* ANALOG_ADC_2 (0x72) */
#define NAU8824_ADCR_EN_SFT		7
#define NAU8824_ADCL_EN_SFT		6

/* RDAC (0x73) */
#define NAU8824_DACR_EN_SFT		13
#define NAU8824_DACL_EN_SFT		12
#define NAU8824_DACR_CLK_SFT		9
#define NAU8824_DACL_CLK_SFT		8
#define NAU8824_RDAC_CLK_DELAY_SFT	4
#define NAU8824_RDAC_CLK_DELAY_MASK	(0x7 << NAU8824_RDAC_CLK_DELAY_SFT)
#define NAU8824_RDAC_VREF_SFT		2
#define NAU8824_RDAC_VREF_MASK	(0x3 << NAU8824_RDAC_VREF_SFT)

/* MIC_BIAS (0x74) */
#define NAU8824_MICBIAS_JKSLV		(1 << 14)
#define NAU8824_MICBIAS_JKR2		(1 << 12)
#define NAU8824_MICBIAS_POWERUP_SFT	8
#define NAU8824_MICBIAS_VOLTAGE_SFT	0
#define NAU8824_MICBIAS_VOLTAGE_MASK	0x7

/* BOOST (0x76) */
#define NAU8824_PRECHARGE_DIS			(0x1 << 13)
#define NAU8824_GLOBAL_BIAS_EN		(0x1 << 12)
#define NAU8824_HP_BOOST_DIS_SFT		9
#define NAU8824_HP_BOOST_DIS		(0x1 << NAU8824_HP_BOOST_DIS_SFT)
#define NAU8824_HP_BOOST_G_DIS_SFT		8
#define NAU8824_HP_BOOST_G_DIS		(0x1 << NAU8824_HP_BOOST_G_DIS_SFT)
#define NAU8824_SHORT_SHUTDOWN_DIG_EN	(1 << 7)
#define NAU8824_SHORT_SHUTDOWN_EN		(1 << 6)

/* FEPGA (0x77) */
#define NAU8824_FEPGA_MODER_SHORT_SFT	7
#define NAU8824_FEPGA_MODER_SHORT_EN	(0x1 << NAU8824_FEPGA_MODER_SHORT_SFT)
#define NAU8824_FEPGA_MODER_MIC2_SFT		5
#define NAU8824_FEPGA_MODER_MIC2_EN	(0x1 << NAU8824_FEPGA_MODER_MIC2_SFT)
#define NAU8824_FEPGA_MODER_HSMIC_SFT	4
#define NAU8824_FEPGA_MODER_HSMIC_EN	(0x1 << NAU8824_FEPGA_MODER_HSMIC_SFT)
#define NAU8824_FEPGA_MODEL_SHORT_SFT	3
#define NAU8824_FEPGA_MODEL_SHORT_EN	(0x1 << NAU8824_FEPGA_MODEL_SHORT_SFT)
#define NAU8824_FEPGA_MODEL_MIC1_SFT		1
#define NAU8824_FEPGA_MODEL_MIC1_EN	(0x1 << NAU8824_FEPGA_MODEL_MIC1_SFT)
#define NAU8824_FEPGA_MODEL_HSMIC_SFT	0
#define NAU8824_FEPGA_MODEL_HSMIC_EN	(0x1 << NAU8824_FEPGA_MODEL_HSMIC_SFT)

/* FEPGA_II (0x78) */
#define NAU8824_FEPGA_GAINR_SFT	5
#define NAU8824_FEPGA_GAINR_MASK	(0x1f << NAU8824_FEPGA_GAINR_SFT)
#define NAU8824_FEPGA_GAINL_SFT	0
#define NAU8824_FEPGA_GAINL_MASK	0x1f

/* CHARGE_PUMP_CONTROL (0x80) */
#define NAU8824_JAMNODCLOW		(0x1 << 15)
#define NAU8824_SPKR_PULL_DOWN	(0x1 << 13)
#define NAU8824_SPKL_PULL_DOWN	(0x1 << 12)
#define NAU8824_POWER_DOWN_DACR	(0x1 << 9)
#define NAU8824_POWER_DOWN_DACL	(0x1 << 8)
#define NAU8824_CHARGE_PUMP_EN_SFT	5
#define NAU8824_CHARGE_PUMP_EN	(0x1 << NAU8824_CHARGE_PUMP_EN_SFT)


#define NAU8824_CODEC_DAI "nau8824-hifi"

/* System Clock Source */
enum {
	NAU8824_CLK_DIS,
	NAU8824_CLK_MCLK,
	NAU8824_CLK_INTERNAL,
	NAU8824_CLK_FLL_MCLK,
	NAU8824_CLK_FLL_BLK,
	NAU8824_CLK_FLL_FS,
};

struct nau8824 {
	struct device *dev;
	struct regmap *regmap;
	struct snd_soc_dapm_context *dapm;
	struct snd_soc_jack *jack;
	struct work_struct jdet_work;
	struct semaphore jd_sem;
	int fs;
	int irq;
	int micbias_voltage;
	int vref_impedance;
	int jkdet_polarity;
	int sar_threshold_num;
	int sar_threshold[8];
	int sar_hysteresis;
	int sar_voltage;
	int sar_compare_time;
	int sar_sampling_time;
	int key_debounce;
	int jack_eject_debounce;
};

struct nau8824_fll {
	int mclk_src;
	int ratio;
	int fll_frac;
	int fll_int;
	int clk_ref_div;
};

struct nau8824_fll_attr {
	unsigned int param;
	unsigned int val;
};

struct nau8824_osr_attr {
	unsigned int osr;
	unsigned int clk_src;
};


int nau8824_enable_jack_detect(struct snd_soc_component *component,
	struct snd_soc_jack *jack);

#endif				/* _NAU8824_H */
Commit	Line	Data
dfeabded JH	1	/*
	2	* NAU88L24 ALSA SoC audio driver
	3	*
	4	* Copyright 2016 Nuvoton Technology Corp.
	5	* Author: John Hsu <KCHSU0@nuvoton.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#ifndef __NAU8824_H__
	13	#define __NAU8824_H__
	14
	15	#define NAU8824_REG_RESET 0x00
	16	#define NAU8824_REG_ENA_CTRL 0x01
	17	#define NAU8824_REG_CLK_GATING_ENA 0x02
	18	#define NAU8824_REG_CLK_DIVIDER 0x03
	19	#define NAU8824_REG_FLL1 0x04
	20	#define NAU8824_REG_FLL2 0x05
	21	#define NAU8824_REG_FLL3 0x06
	22	#define NAU8824_REG_FLL4 0x07
	23	#define NAU8824_REG_FLL5 0x08
	24	#define NAU8824_REG_FLL6 0x09
	25	#define NAU8824_REG_FLL_VCO_RSV 0x0A
	26	#define NAU8824_REG_JACK_DET_CTRL 0x0D
	27	#define NAU8824_REG_INTERRUPT_SETTING_1 0x0F
	28	#define NAU8824_REG_IRQ 0x10
	29	#define NAU8824_REG_CLEAR_INT_REG 0x11
	30	#define NAU8824_REG_INTERRUPT_SETTING 0x12
	31	#define NAU8824_REG_SAR_ADC 0x13
	32	#define NAU8824_REG_VDET_COEFFICIENT 0x14
	33	#define NAU8824_REG_VDET_THRESHOLD_1 0x15
	34	#define NAU8824_REG_VDET_THRESHOLD_2 0x16
	35	#define NAU8824_REG_VDET_THRESHOLD_3 0x17
	36	#define NAU8824_REG_VDET_THRESHOLD_4 0x18
	37	#define NAU8824_REG_GPIO_SEL 0x1A
	38	#define NAU8824_REG_PORT0_I2S_PCM_CTRL_1 0x1C
	39	#define NAU8824_REG_PORT0_I2S_PCM_CTRL_2 0x1D
	40	#define NAU8824_REG_PORT0_LEFT_TIME_SLOT 0x1E
	41	#define NAU8824_REG_PORT0_RIGHT_TIME_SLOT 0x1F
	42	#define NAU8824_REG_TDM_CTRL 0x20
	43	#define NAU8824_REG_ADC_HPF_FILTER 0x23
	44	#define NAU8824_REG_ADC_FILTER_CTRL 0x24
	45	#define NAU8824_REG_DAC_FILTER_CTRL_1 0x25
	46	#define NAU8824_REG_DAC_FILTER_CTRL_2 0x26
	47	#define NAU8824_REG_NOTCH_FILTER_1 0x27
	48	#define NAU8824_REG_NOTCH_FILTER_2 0x28
	49	#define NAU8824_REG_EQ1_LOW 0x29
	50	#define NAU8824_REG_EQ2_EQ3 0x2A
	51	#define NAU8824_REG_EQ4_EQ5 0x2B
	52	#define NAU8824_REG_ADC_CH0_DGAIN_CTRL 0x2D
	53	#define NAU8824_REG_ADC_CH1_DGAIN_CTRL 0x2E
	54	#define NAU8824_REG_ADC_CH2_DGAIN_CTRL 0x2F
	55	#define NAU8824_REG_ADC_CH3_DGAIN_CTRL 0x30
	56	#define NAU8824_REG_DAC_MUTE_CTRL 0x31
	57	#define NAU8824_REG_DAC_CH0_DGAIN_CTRL 0x32
	58	#define NAU8824_REG_DAC_CH1_DGAIN_CTRL 0x33
	59	#define NAU8824_REG_ADC_TO_DAC_ST 0x34
	60	#define NAU8824_REG_DRC_KNEE_IP12_ADC_CH01 0x38
	61	#define NAU8824_REG_DRC_KNEE_IP34_ADC_CH01 0x39
	62	#define NAU8824_REG_DRC_SLOPE_ADC_CH01 0x3A
	63	#define NAU8824_REG_DRC_ATKDCY_ADC_CH01 0x3B
	64	#define NAU8824_REG_DRC_KNEE_IP12_ADC_CH23 0x3C
65	#define NAU8824_REG_DRC_KNEE_IP34_ADC_CH23 0x3D
66	#define NAU8824_REG_DRC_SLOPE_ADC_CH23 0x3E
67	#define NAU8824_REG_DRC_ATKDCY_ADC_CH23 0x3F
68	#define NAU8824_REG_DRC_GAINL_ADC0 0x40
69	#define NAU8824_REG_DRC_GAINL_ADC1 0x41
70	#define NAU8824_REG_DRC_GAINL_ADC2 0x42
71	#define NAU8824_REG_DRC_GAINL_ADC3 0x43
72	#define NAU8824_REG_DRC_KNEE_IP12_DAC 0x45
73	#define NAU8824_REG_DRC_KNEE_IP34_DAC 0x46
74	#define NAU8824_REG_DRC_SLOPE_DAC 0x47
75	#define NAU8824_REG_DRC_ATKDCY_DAC 0x48
76	#define NAU8824_REG_DRC_GAIN_DAC_CH0 0x49
77	#define NAU8824_REG_DRC_GAIN_DAC_CH1 0x4A
78	#define NAU8824_REG_MODE 0x4C
79	#define NAU8824_REG_MODE1 0x4D
80	#define NAU8824_REG_MODE2 0x4E
81	#define NAU8824_REG_CLASSG 0x50
82	#define NAU8824_REG_OTP_EFUSE 0x51
83	#define NAU8824_REG_OTPDOUT_1 0x53
84	#define NAU8824_REG_OTPDOUT_2 0x54
85	#define NAU8824_REG_MISC_CTRL 0x55
86	#define NAU8824_REG_I2C_TIMEOUT 0x56
87	#define NAU8824_REG_TEST_MODE 0x57
88	#define NAU8824_REG_I2C_DEVICE_ID 0x58
89	#define NAU8824_REG_SAR_ADC_DATA_OUT 0x59
90	#define NAU8824_REG_BIAS_ADJ 0x66
91	#define NAU8824_REG_PGA_GAIN 0x67
92	#define NAU8824_REG_TRIM_SETTINGS 0x68
93	#define NAU8824_REG_ANALOG_CONTROL_1 0x69
94	#define NAU8824_REG_ANALOG_CONTROL_2 0x6A
95	#define NAU8824_REG_ENABLE_LO 0x6B
96	#define NAU8824_REG_GAIN_LO 0x6C
97	#define NAU8824_REG_CLASSD_GAIN_1 0x6D
98	#define NAU8824_REG_CLASSD_GAIN_2 0x6E
99	#define NAU8824_REG_ANALOG_ADC_1 0x71
100	#define NAU8824_REG_ANALOG_ADC_2 0x72
101	#define NAU8824_REG_RDAC 0x73
102	#define NAU8824_REG_MIC_BIAS 0x74
103	#define NAU8824_REG_HS_VOLUME_CONTROL 0x75
104	#define NAU8824_REG_BOOST 0x76
105	#define NAU8824_REG_FEPGA 0x77
106	#define NAU8824_REG_FEPGA_II 0x78
107	#define NAU8824_REG_FEPGA_SE 0x79
108	#define NAU8824_REG_FEPGA_ATTENUATION 0x7A
109	#define NAU8824_REG_ATT_PORT0 0x7B
110	#define NAU8824_REG_ATT_PORT1 0x7C
111	#define NAU8824_REG_POWER_UP_CONTROL 0x7F
112	#define NAU8824_REG_CHARGE_PUMP_CONTROL 0x80
113	#define NAU8824_REG_CHARGE_PUMP_INPUT 0x81
114	#define NAU8824_REG_MAX NAU8824_REG_CHARGE_PUMP_INPUT
115	/* 16-bit control register address, and 16-bits control register data */
116	#define NAU8824_REG_ADDR_LEN 16
117	#define NAU8824_REG_DATA_LEN 16
118
119
120	/* ENA_CTRL (0x1) */
121	#define NAU8824_DMIC_LCH_EDGE_CH23 (0x1 << 12)
122	#define NAU8824_DMIC_LCH_EDGE_CH01 (0x1 << 11)
123	#define NAU8824_JD_SLEEP_MODE (0x1 << 10)
124	#define NAU8824_ADC_CH3_DMIC_SFT 9
125	#define NAU8824_ADC_CH3_DMIC_EN (0x1 << NAU8824_ADC_CH3_DMIC_SFT)
126	#define NAU8824_ADC_CH2_DMIC_SFT 8
127	#define NAU8824_ADC_CH2_DMIC_EN (0x1 << NAU8824_ADC_CH2_DMIC_SFT)
128	#define NAU8824_ADC_CH1_DMIC_SFT 7
129	#define NAU8824_ADC_CH1_DMIC_EN (0x1 << NAU8824_ADC_CH1_DMIC_SFT)
130	#define NAU8824_ADC_CH0_DMIC_SFT 6
131	#define NAU8824_ADC_CH0_DMIC_EN (0x1 << NAU8824_ADC_CH0_DMIC_SFT)
132	#define NAU8824_DAC_CH1_EN (0x1 << 5)
133	#define NAU8824_DAC_CH0_EN (0x1 << 4)
134	#define NAU8824_ADC_CH3_EN (0x1 << 3)
135	#define NAU8824_ADC_CH2_EN (0x1 << 2)
136	#define NAU8824_ADC_CH1_EN (0x1 << 1)
137	#define NAU8824_ADC_CH0_EN 0x1
138
139	/* CLK_GATING_ENA (0x02) */
140	#define NAU8824_CLK_ADC_CH23_EN (0x1 << 15)
141	#define NAU8824_CLK_ADC_CH01_EN (0x1 << 14)
142	#define NAU8824_CLK_DAC_CH1_EN (0x1 << 13)
143	#define NAU8824_CLK_DAC_CH0_EN (0x1 << 12)
144	#define NAU8824_CLK_I2S_EN (0x1 << 7)
145	#define NAU8824_CLK_GAIN_EN (0x1 << 5)
146	#define NAU8824_CLK_SAR_EN (0x1 << 3)
147	#define NAU8824_CLK_DMIC_CH23_EN (0x1 << 1)
148
149	/* CLK_DIVIDER (0x3) */
150	#define NAU8824_CLK_SRC_SFT 15
151	#define NAU8824_CLK_SRC_MASK (1 << NAU8824_CLK_SRC_SFT)
152	#define NAU8824_CLK_SRC_VCO (1 << NAU8824_CLK_SRC_SFT)
153	#define NAU8824_CLK_SRC_MCLK (0 << NAU8824_CLK_SRC_SFT)
154	#define NAU8824_CLK_MCLK_SRC_MASK (0xf << 0)
155	#define NAU8824_CLK_DMIC_SRC_SFT 10
156	#define NAU8824_CLK_DMIC_SRC_MASK (0x7 << NAU8824_CLK_DMIC_SRC_SFT)
157	#define NAU8824_CLK_ADC_SRC_SFT 6
158	#define NAU8824_CLK_ADC_SRC_MASK (0x3 << NAU8824_CLK_ADC_SRC_SFT)
159	#define NAU8824_CLK_DAC_SRC_SFT 4
160	#define NAU8824_CLK_DAC_SRC_MASK (0x3 << NAU8824_CLK_DAC_SRC_SFT)
161
162	/* FLL1 (0x04) */
163	#define NAU8824_FLL_RATIO_MASK (0x7f << 0)
164
165	/* FLL3 (0x06) */
166	#define NAU8824_FLL_INTEGER_MASK (0x3ff << 0)
167	#define NAU8824_FLL_CLK_SRC_SFT 10
168	#define NAU8824_FLL_CLK_SRC_MASK (0x3 << NAU8824_FLL_CLK_SRC_SFT)
169	#define NAU8824_FLL_CLK_SRC_MCLK (0 << NAU8824_FLL_CLK_SRC_SFT)
170	#define NAU8824_FLL_CLK_SRC_BLK (0x2 << NAU8824_FLL_CLK_SRC_SFT)
171	#define NAU8824_FLL_CLK_SRC_FS (0x3 << NAU8824_FLL_CLK_SRC_SFT)
172
173	/* FLL4 (0x07) */
174	#define NAU8824_FLL_REF_DIV_SFT 10
175	#define NAU8824_FLL_REF_DIV_MASK (0x3 << NAU8824_FLL_REF_DIV_SFT)
176
177	/* FLL5 (0x08) */
178	#define NAU8824_FLL_PDB_DAC_EN (0x1 << 15)
179	#define NAU8824_FLL_LOOP_FTR_EN (0x1 << 14)
180	#define NAU8824_FLL_CLK_SW_MASK (0x1 << 13)
181	#define NAU8824_FLL_CLK_SW_N2 (0x1 << 13)
182	#define NAU8824_FLL_CLK_SW_REF (0x0 << 13)
183	#define NAU8824_FLL_FTR_SW_MASK (0x1 << 12)
184	#define NAU8824_FLL_FTR_SW_ACCU (0x1 << 12)
185	#define NAU8824_FLL_FTR_SW_FILTER (0x0 << 12)
186
187	/* FLL6 (0x9) */
188	#define NAU8824_DCO_EN (0x1 << 15)
189	#define NAU8824_SDM_EN (0x1 << 14)
190
191	/* IRQ (0x10) */
192	#define NAU8824_SHORT_CIRCUIT_IRQ (0x1 << 7)
193	#define NAU8824_IMPEDANCE_MEAS_IRQ (0x1 << 6)
194	#define NAU8824_KEY_RELEASE_IRQ (0x1 << 5)
195	#define NAU8824_KEY_LONG_PRESS_IRQ (0x1 << 4)
196	#define NAU8824_KEY_SHORT_PRESS_IRQ (0x1 << 3)
197	#define NAU8824_JACK_EJECTION_DETECTED (0x1 << 1)
198	#define NAU8824_JACK_INSERTION_DETECTED 0x1
199
200	/* JACK_DET_CTRL (0x0D) */
201	#define NAU8824_JACK_EJECT_DT_SFT 2
202	#define NAU8824_JACK_EJECT_DT_MASK (0x3 << NAU8824_JACK_EJECT_DT_SFT)
203	#define NAU8824_JACK_LOGIC 0x1
204
205
206	/* INTERRUPT_SETTING_1 (0x0F) */
207	#define NAU8824_IRQ_EJECT_EN (0x1 << 9)
208	#define NAU8824_IRQ_INSERT_EN (0x1 << 8)
209
210	/* INTERRUPT_SETTING (0x12) */
211	#define NAU8824_IRQ_KEY_RELEASE_DIS (0x1 << 5)
212	#define NAU8824_IRQ_KEY_SHORT_PRESS_DIS (0x1 << 3)
213	#define NAU8824_IRQ_EJECT_DIS (0x1 << 1)
214	#define NAU8824_IRQ_INSERT_DIS 0x1
215
216	/* SAR_ADC (0x13) */
217	#define NAU8824_SAR_ADC_EN_SFT 12
218	#define NAU8824_SAR_TRACKING_GAIN_SFT 8
219	#define NAU8824_SAR_TRACKING_GAIN_MASK (0x7 << NAU8824_SAR_TRACKING_GAIN_SFT)
220	#define NAU8824_SAR_COMPARE_TIME_SFT 2
221	#define NAU8824_SAR_COMPARE_TIME_MASK (3 << 2)
222	#define NAU8824_SAR_SAMPLING_TIME_SFT 0
223	#define NAU8824_SAR_SAMPLING_TIME_MASK (3 << 0)
224
225	/* VDET_COEFFICIENT (0x14) */
226	#define NAU8824_SHORTKEY_DEBOUNCE_SFT 12
227	#define NAU8824_SHORTKEY_DEBOUNCE_MASK (0x3 << NAU8824_SHORTKEY_DEBOUNCE_SFT)
228	#define NAU8824_LEVELS_NR_SFT 8
229	#define NAU8824_LEVELS_NR_MASK (0x7 << 8)
230	#define NAU8824_HYSTERESIS_SFT 0
231	#define NAU8824_HYSTERESIS_MASK 0xf
232
233	/* PORT0_I2S_PCM_CTRL_1 (0x1C) */
234	#define NAU8824_I2S_BP_SFT 7
235	#define NAU8824_I2S_BP_MASK (1 << NAU8824_I2S_BP_SFT)
236	#define NAU8824_I2S_BP_INV (1 << NAU8824_I2S_BP_SFT)
237	#define NAU8824_I2S_PCMB_SFT 6
238	#define NAU8824_I2S_PCMB_EN (1 << NAU8824_I2S_PCMB_SFT)
239	#define NAU8824_I2S_DL_SFT 2
240	#define NAU8824_I2S_DL_MASK (0x3 << NAU8824_I2S_DL_SFT)
241	#define NAU8824_I2S_DL_16 (0 << NAU8824_I2S_DL_SFT)
242	#define NAU8824_I2S_DL_20 (1 << NAU8824_I2S_DL_SFT)
243	#define NAU8824_I2S_DL_24 (2 << NAU8824_I2S_DL_SFT)
244	#define NAU8824_I2S_DL_32 (3 << NAU8824_I2S_DL_SFT)
245	#define NAU8824_I2S_DF_MASK 0x3
246	#define NAU8824_I2S_DF_RIGTH 0
247	#define NAU8824_I2S_DF_LEFT 1
248	#define NAU8824_I2S_DF_I2S 2
249	#define NAU8824_I2S_DF_PCM_AB 3
250
251
252	/* PORT0_I2S_PCM_CTRL_2 (0x1D) */
253	#define NAU8824_I2S_LRC_DIV_SFT 12
254	#define NAU8824_I2S_LRC_DIV_MASK (0x3 << NAU8824_I2S_LRC_DIV_SFT)
255	#define NAU8824_I2S_MS_SFT 3
256	#define NAU8824_I2S_MS_MASK (1 << NAU8824_I2S_MS_SFT)
257	#define NAU8824_I2S_MS_MASTER (1 << NAU8824_I2S_MS_SFT)
258	#define NAU8824_I2S_MS_SLAVE (0 << NAU8824_I2S_MS_SFT)
259	#define NAU8824_I2S_BLK_DIV_MASK 0x7
260
fa101430 JH	261	/* PORT0_LEFT_TIME_SLOT (0x1E) */
	262	#define NAU8824_TSLOT_L_MASK 0x3ff
	263
	264	/* TDM_CTRL (0x20) */
	265	#define NAU8824_TDM_MODE (0x1 << 15)
	266	#define NAU8824_TDM_OFFSET_EN (0x1 << 14)
	267	#define NAU8824_TDM_DACL_RX_SFT 6
	268	#define NAU8824_TDM_DACL_RX_MASK (0x3 << NAU8824_TDM_DACL_RX_SFT)
	269	#define NAU8824_TDM_DACR_RX_SFT 4
	270	#define NAU8824_TDM_DACR_RX_MASK (0x3 << NAU8824_TDM_DACR_RX_SFT)
	271	#define NAU8824_TDM_TX_MASK 0xf
	272
dfeabded JH	273	/* ADC_FILTER_CTRL (0x24) */
	274	#define NAU8824_ADC_SYNC_DOWN_MASK 0x3
	275	#define NAU8824_ADC_SYNC_DOWN_32 0
	276	#define NAU8824_ADC_SYNC_DOWN_64 1
	277	#define NAU8824_ADC_SYNC_DOWN_128 2
	278	#define NAU8824_ADC_SYNC_DOWN_256 3
	279
	280	/* DAC_FILTER_CTRL_1 (0x25) */
	281	#define NAU8824_DAC_CICCLP_OFF (0x1 << 7)
	282	#define NAU8824_DAC_OVERSAMPLE_MASK 0x7
	283	#define NAU8824_DAC_OVERSAMPLE_64 0
	284	#define NAU8824_DAC_OVERSAMPLE_256 1
	285	#define NAU8824_DAC_OVERSAMPLE_128 2
	286	#define NAU8824_DAC_OVERSAMPLE_32 4
	287
	288	/* DAC_MUTE_CTRL (0x31) */
	289	#define NAU8824_DAC_CH01_MIX 0x3
	290	#define NAU8824_DAC_ZC_EN (0x1 << 11)
	291
	292	/* DAC_CH0_DGAIN_CTRL (0x32) */
	293	#define NAU8824_DAC_CH0_SEL_SFT 9
	294	#define NAU8824_DAC_CH0_SEL_MASK (0x1 << NAU8824_DAC_CH0_SEL_SFT)
	295	#define NAU8824_DAC_CH0_SEL_I2S0 (0x0 << NAU8824_DAC_CH0_SEL_SFT)
	296	#define NAU8824_DAC_CH0_SEL_I2S1 (0x1 << NAU8824_DAC_CH0_SEL_SFT)
	297	#define NAU8824_DAC_CH0_VOL_MASK 0x1ff
	298
	299	/* DAC_CH1_DGAIN_CTRL (0x33) */
	300	#define NAU8824_DAC_CH1_SEL_SFT 9
	301	#define NAU8824_DAC_CH1_SEL_MASK (0x1 << NAU8824_DAC_CH1_SEL_SFT)
	302	#define NAU8824_DAC_CH1_SEL_I2S0 (0x0 << NAU8824_DAC_CH1_SEL_SFT)
	303	#define NAU8824_DAC_CH1_SEL_I2S1 (0x1 << NAU8824_DAC_CH1_SEL_SFT)
	304	#define NAU8824_DAC_CH1_VOL_MASK 0x1ff
	305
	306	/* CLASSG (0x50) */
	307	#define NAU8824_CLASSG_TIMER_SFT 8
	308	#define NAU8824_CLASSG_TIMER_MASK (0x3f << NAU8824_CLASSG_TIMER_SFT)
	309	#define NAU8824_CLASSG_LDAC_EN_SFT 2
	310	#define NAU8824_CLASSG_RDAC_EN_SFT 1
	311	#define NAU8824_CLASSG_EN_SFT 0
	312
	313	/* SAR_ADC_DATA_OUT (0x59) */
	314	#define NAU8824_SAR_ADC_DATA_MASK 0xff
	315
	316	/* BIAS_ADJ (0x66) */
	317	#define NAU8824_VMID (1 << 6)
	318	#define NAU8824_VMID_SEL_SFT 4
	319	#define NAU8824_VMID_SEL_MASK (3 << NAU8824_VMID_SEL_SFT)
	320	#define NAU8824_DMIC2_EN_SFT 3
	321	#define NAU8824_DMIC1_EN_SFT 2
	322
	323	/* TRIM_SETTINGS (0x68) */
	324	#define NAU8824_DRV_CURR_INC (1 << 15)
	325
	326	/* ANALOG_CONTROL_1 (0x69) */
	327	#define NAU8824_DMIC_CLK_DRV_STRG (1 << 3)
	328	#define NAU8824_DMIC_CLK_SLEW_FAST (0x7)
	329
	330	/* ANALOG_CONTROL_2 (0x6A) */
	331	#define NAU8824_CLASSD_CLAMP_DIS_SFT 3
	332	#define NAU8824_CLASSD_CLAMP_DIS (0x1 << NAU8824_CLASSD_CLAMP_DIS_SFT)
	333
	334	/* ENABLE_LO (0x6B) */
	335	#define NAU8824_TEST_DAC_SFT 14
	336	#define NAU8824_TEST_DAC_EN (0x3 << NAU8824_TEST_DAC_SFT)
337	#define NAU8824_DACL_HPR_EN_SFT 3
338	#define NAU8824_DACL_HPR_EN (0x1 << NAU8824_DACL_HPR_EN_SFT)
339	#define NAU8824_DACR_HPR_EN_SFT 2
340	#define NAU8824_DACR_HPR_EN (0x1 << NAU8824_DACR_HPR_EN_SFT)
341	#define NAU8824_DACR_HPL_EN_SFT 1
342	#define NAU8824_DACR_HPL_EN (0x1 << NAU8824_DACR_HPL_EN_SFT)
343	#define NAU8824_DACL_HPL_EN_SFT 0
344	#define NAU8824_DACL_HPL_EN 0x1
345
346	/* CLASSD_GAIN_1 (0x6D) */
347	#define NAU8824_CLASSD_GAIN_1R_SFT 8
348	#define NAU8824_CLASSD_GAIN_1R_MASK (0x1f << NAU8824_CLASSD_GAIN_1R_SFT)
349	#define NAU8824_CLASSD_EN_SFT 7
350	#define NAU8824_CLASSD_EN (0x1 << NAU8824_CLASSD_EN_SFT)
351	#define NAU8824_CLASSD_GAIN_1L_MASK 0x1f
352
353	/* CLASSD_GAIN_2 (0x6E) */
354	#define NAU8824_CLASSD_GAIN_2R_SFT 8
355	#define NAU8824_CLASSD_GAIN_2R_MASK (0x1f << NAU8824_CLASSD_GAIN_1R_SFT)
356	#define NAU8824_CLASSD_EN_SFT 7
357	#define NAU8824_CLASSD_EN (0x1 << NAU8824_CLASSD_EN_SFT)
358	#define NAU8824_CLASSD_GAIN_2L_MASK 0x1f
359
360	/* ANALOG_ADC_2 (0x72) */
361	#define NAU8824_ADCR_EN_SFT 7
362	#define NAU8824_ADCL_EN_SFT 6
363
364	/* RDAC (0x73) */
365	#define NAU8824_DACR_EN_SFT 13
366	#define NAU8824_DACL_EN_SFT 12
367	#define NAU8824_DACR_CLK_SFT 9
368	#define NAU8824_DACL_CLK_SFT 8
369	#define NAU8824_RDAC_CLK_DELAY_SFT 4
370	#define NAU8824_RDAC_CLK_DELAY_MASK (0x7 << NAU8824_RDAC_CLK_DELAY_SFT)
371	#define NAU8824_RDAC_VREF_SFT 2
372	#define NAU8824_RDAC_VREF_MASK (0x3 << NAU8824_RDAC_VREF_SFT)
373
374	/* MIC_BIAS (0x74) */
375	#define NAU8824_MICBIAS_JKSLV (1 << 14)
376	#define NAU8824_MICBIAS_JKR2 (1 << 12)
377	#define NAU8824_MICBIAS_POWERUP_SFT 8
378	#define NAU8824_MICBIAS_VOLTAGE_SFT 0
379	#define NAU8824_MICBIAS_VOLTAGE_MASK 0x7
380
381	/* BOOST (0x76) */
382	#define NAU8824_PRECHARGE_DIS (0x1 << 13)
383	#define NAU8824_GLOBAL_BIAS_EN (0x1 << 12)
384	#define NAU8824_HP_BOOST_DIS_SFT 9
385	#define NAU8824_HP_BOOST_DIS (0x1 << NAU8824_HP_BOOST_DIS_SFT)
386	#define NAU8824_HP_BOOST_G_DIS_SFT 8
387	#define NAU8824_HP_BOOST_G_DIS (0x1 << NAU8824_HP_BOOST_G_DIS_SFT)
388	#define NAU8824_SHORT_SHUTDOWN_DIG_EN (1 << 7)
389	#define NAU8824_SHORT_SHUTDOWN_EN (1 << 6)
390
391	/* FEPGA (0x77) */
392	#define NAU8824_FEPGA_MODER_SHORT_SFT 7
393	#define NAU8824_FEPGA_MODER_SHORT_EN (0x1 << NAU8824_FEPGA_MODER_SHORT_SFT)
394	#define NAU8824_FEPGA_MODER_MIC2_SFT 5
395	#define NAU8824_FEPGA_MODER_MIC2_EN (0x1 << NAU8824_FEPGA_MODER_MIC2_SFT)
396	#define NAU8824_FEPGA_MODER_HSMIC_SFT 4
397	#define NAU8824_FEPGA_MODER_HSMIC_EN (0x1 << NAU8824_FEPGA_MODER_HSMIC_SFT)
398	#define NAU8824_FEPGA_MODEL_SHORT_SFT 3
399	#define NAU8824_FEPGA_MODEL_SHORT_EN (0x1 << NAU8824_FEPGA_MODEL_SHORT_SFT)
400	#define NAU8824_FEPGA_MODEL_MIC1_SFT 1
401	#define NAU8824_FEPGA_MODEL_MIC1_EN (0x1 << NAU8824_FEPGA_MODEL_MIC1_SFT)
402	#define NAU8824_FEPGA_MODEL_HSMIC_SFT 0
403	#define NAU8824_FEPGA_MODEL_HSMIC_EN (0x1 << NAU8824_FEPGA_MODEL_HSMIC_SFT)
404
405	/* FEPGA_II (0x78) */
406	#define NAU8824_FEPGA_GAINR_SFT 5
407	#define NAU8824_FEPGA_GAINR_MASK (0x1f << NAU8824_FEPGA_GAINR_SFT)
408	#define NAU8824_FEPGA_GAINL_SFT 0
409	#define NAU8824_FEPGA_GAINL_MASK 0x1f
410
411	/* CHARGE_PUMP_CONTROL (0x80) */
412	#define NAU8824_JAMNODCLOW (0x1 << 15)
413	#define NAU8824_SPKR_PULL_DOWN (0x1 << 13)
414	#define NAU8824_SPKL_PULL_DOWN (0x1 << 12)
415	#define NAU8824_POWER_DOWN_DACR (0x1 << 9)
416	#define NAU8824_POWER_DOWN_DACL (0x1 << 8)
417	#define NAU8824_CHARGE_PUMP_EN_SFT 5
418	#define NAU8824_CHARGE_PUMP_EN (0x1 << NAU8824_CHARGE_PUMP_EN_SFT)
419
420
421	#define NAU8824_CODEC_DAI "nau8824-hifi"
422
423	/* System Clock Source */
424	enum {
425	NAU8824_CLK_DIS,
426	NAU8824_CLK_MCLK,
427	NAU8824_CLK_INTERNAL,
428	NAU8824_CLK_FLL_MCLK,
429	NAU8824_CLK_FLL_BLK,
430	NAU8824_CLK_FLL_FS,
431	};
432
433	struct nau8824 {
434	struct device *dev;
435	struct regmap *regmap;
436	struct snd_soc_dapm_context *dapm;
437	struct snd_soc_jack *jack;
438	struct work_struct jdet_work;
439	struct semaphore jd_sem;
440	int fs;
441	int irq;
442	int micbias_voltage;
443	int vref_impedance;
444	int jkdet_polarity;
445	int sar_threshold_num;
446	int sar_threshold[8];
447	int sar_hysteresis;
448	int sar_voltage;
449	int sar_compare_time;
450	int sar_sampling_time;
451	int key_debounce;
452	int jack_eject_debounce;
453	};
454
455	struct nau8824_fll {
456	int mclk_src;
457	int ratio;
458	int fll_frac;
459	int fll_int;
460	int clk_ref_div;
461	};
462
463	struct nau8824_fll_attr {
464	unsigned int param;
465	unsigned int val;
466	};
467
468	struct nau8824_osr_attr {
469	unsigned int osr;
470	unsigned int clk_src;
471	};
472
473
12a72f91	474	int nau8824_enable_jack_detect(struct snd_soc_component *component,
dfeabded JH	475	struct snd_soc_jack *jack);
	476
	477	#endif /* _NAU8824_H */
	478