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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
c1644e3d JH |
2 | /* |
3 | * NAU85L40 ALSA SoC audio driver | |
4 | * | |
5 | * Copyright 2016 Nuvoton Technology Corp. | |
6 | * Author: John Hsu <KCHSU0@nuvoton.com> | |
c1644e3d JH |
7 | */ |
8 | ||
9 | #include <linux/module.h> | |
10 | #include <linux/moduleparam.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/pm.h> | |
14 | #include <linux/i2c.h> | |
15 | #include <linux/regmap.h> | |
16 | #include <linux/regulator/consumer.h> | |
17 | #include <linux/spi/spi.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/of_device.h> | |
20 | #include <sound/core.h> | |
21 | #include <sound/pcm.h> | |
22 | #include <sound/pcm_params.h> | |
23 | #include <sound/soc.h> | |
24 | #include <sound/soc-dapm.h> | |
25 | #include <sound/initval.h> | |
26 | #include <sound/tlv.h> | |
27 | #include "nau8540.h" | |
28 | ||
29 | ||
30 | #define NAU_FREF_MAX 13500000 | |
31 | #define NAU_FVCO_MAX 100000000 | |
32 | #define NAU_FVCO_MIN 90000000 | |
33 | ||
34 | /* the maximum frequency of CLK_ADC */ | |
35 | #define CLK_ADC_MAX 6144000 | |
36 | ||
37 | /* scaling for mclk from sysclk_src output */ | |
38 | static const struct nau8540_fll_attr mclk_src_scaling[] = { | |
babd6585 JH |
39 | { 1, 0x0 }, |
40 | { 2, 0x2 }, | |
41 | { 4, 0x3 }, | |
42 | { 8, 0x4 }, | |
43 | { 16, 0x5 }, | |
44 | { 32, 0x6 }, | |
45 | { 3, 0x7 }, | |
46 | { 6, 0xa }, | |
47 | { 12, 0xb }, | |
48 | { 24, 0xc }, | |
c1644e3d JH |
49 | }; |
50 | ||
51 | /* ratio for input clk freq */ | |
52 | static const struct nau8540_fll_attr fll_ratio[] = { | |
babd6585 JH |
53 | { 512000, 0x01 }, |
54 | { 256000, 0x02 }, | |
55 | { 128000, 0x04 }, | |
56 | { 64000, 0x08 }, | |
57 | { 32000, 0x10 }, | |
58 | { 8000, 0x20 }, | |
59 | { 4000, 0x40 }, | |
c1644e3d JH |
60 | }; |
61 | ||
62 | static const struct nau8540_fll_attr fll_pre_scalar[] = { | |
babd6585 JH |
63 | { 1, 0x0 }, |
64 | { 2, 0x1 }, | |
65 | { 4, 0x2 }, | |
66 | { 8, 0x3 }, | |
c1644e3d JH |
67 | }; |
68 | ||
69 | /* over sampling rate */ | |
70 | static const struct nau8540_osr_attr osr_adc_sel[] = { | |
babd6585 JH |
71 | { 32, 3 }, /* OSR 32, SRC 1/8 */ |
72 | { 64, 2 }, /* OSR 64, SRC 1/4 */ | |
73 | { 128, 1 }, /* OSR 128, SRC 1/2 */ | |
74 | { 256, 0 }, /* OSR 256, SRC 1 */ | |
c1644e3d JH |
75 | }; |
76 | ||
77 | static const struct reg_default nau8540_reg_defaults[] = { | |
babd6585 JH |
78 | {NAU8540_REG_POWER_MANAGEMENT, 0x0000}, |
79 | {NAU8540_REG_CLOCK_CTRL, 0x0000}, | |
80 | {NAU8540_REG_CLOCK_SRC, 0x0000}, | |
81 | {NAU8540_REG_FLL1, 0x0001}, | |
82 | {NAU8540_REG_FLL2, 0x3126}, | |
83 | {NAU8540_REG_FLL3, 0x0008}, | |
84 | {NAU8540_REG_FLL4, 0x0010}, | |
85 | {NAU8540_REG_FLL5, 0xC000}, | |
86 | {NAU8540_REG_FLL6, 0x6000}, | |
87 | {NAU8540_REG_FLL_VCO_RSV, 0xF13C}, | |
88 | {NAU8540_REG_PCM_CTRL0, 0x000B}, | |
89 | {NAU8540_REG_PCM_CTRL1, 0x3010}, | |
90 | {NAU8540_REG_PCM_CTRL2, 0x0800}, | |
91 | {NAU8540_REG_PCM_CTRL3, 0x0000}, | |
92 | {NAU8540_REG_PCM_CTRL4, 0x000F}, | |
93 | {NAU8540_REG_ALC_CONTROL_1, 0x0000}, | |
94 | {NAU8540_REG_ALC_CONTROL_2, 0x700B}, | |
95 | {NAU8540_REG_ALC_CONTROL_3, 0x0022}, | |
96 | {NAU8540_REG_ALC_CONTROL_4, 0x1010}, | |
97 | {NAU8540_REG_ALC_CONTROL_5, 0x1010}, | |
98 | {NAU8540_REG_NOTCH_FIL1_CH1, 0x0000}, | |
99 | {NAU8540_REG_NOTCH_FIL2_CH1, 0x0000}, | |
100 | {NAU8540_REG_NOTCH_FIL1_CH2, 0x0000}, | |
101 | {NAU8540_REG_NOTCH_FIL2_CH2, 0x0000}, | |
102 | {NAU8540_REG_NOTCH_FIL1_CH3, 0x0000}, | |
103 | {NAU8540_REG_NOTCH_FIL2_CH3, 0x0000}, | |
104 | {NAU8540_REG_NOTCH_FIL1_CH4, 0x0000}, | |
105 | {NAU8540_REG_NOTCH_FIL2_CH4, 0x0000}, | |
106 | {NAU8540_REG_HPF_FILTER_CH12, 0x0000}, | |
107 | {NAU8540_REG_HPF_FILTER_CH34, 0x0000}, | |
108 | {NAU8540_REG_ADC_SAMPLE_RATE, 0x0002}, | |
109 | {NAU8540_REG_DIGITAL_GAIN_CH1, 0x0400}, | |
110 | {NAU8540_REG_DIGITAL_GAIN_CH2, 0x0400}, | |
111 | {NAU8540_REG_DIGITAL_GAIN_CH3, 0x0400}, | |
112 | {NAU8540_REG_DIGITAL_GAIN_CH4, 0x0400}, | |
113 | {NAU8540_REG_DIGITAL_MUX, 0x00E4}, | |
114 | {NAU8540_REG_GPIO_CTRL, 0x0000}, | |
115 | {NAU8540_REG_MISC_CTRL, 0x0000}, | |
116 | {NAU8540_REG_I2C_CTRL, 0xEFFF}, | |
117 | {NAU8540_REG_VMID_CTRL, 0x0000}, | |
118 | {NAU8540_REG_MUTE, 0x0000}, | |
119 | {NAU8540_REG_ANALOG_ADC1, 0x0011}, | |
120 | {NAU8540_REG_ANALOG_ADC2, 0x0020}, | |
121 | {NAU8540_REG_ANALOG_PWR, 0x0000}, | |
122 | {NAU8540_REG_MIC_BIAS, 0x0004}, | |
123 | {NAU8540_REG_REFERENCE, 0x0000}, | |
124 | {NAU8540_REG_FEPGA1, 0x0000}, | |
125 | {NAU8540_REG_FEPGA2, 0x0000}, | |
126 | {NAU8540_REG_FEPGA3, 0x0101}, | |
127 | {NAU8540_REG_FEPGA4, 0x0101}, | |
128 | {NAU8540_REG_PWR, 0x0000}, | |
c1644e3d JH |
129 | }; |
130 | ||
131 | static bool nau8540_readable_reg(struct device *dev, unsigned int reg) | |
132 | { | |
babd6585 JH |
133 | switch (reg) { |
134 | case NAU8540_REG_POWER_MANAGEMENT ... NAU8540_REG_FLL_VCO_RSV: | |
135 | case NAU8540_REG_PCM_CTRL0 ... NAU8540_REG_PCM_CTRL4: | |
136 | case NAU8540_REG_ALC_CONTROL_1 ... NAU8540_REG_ALC_CONTROL_5: | |
137 | case NAU8540_REG_ALC_GAIN_CH12 ... NAU8540_REG_ADC_SAMPLE_RATE: | |
138 | case NAU8540_REG_DIGITAL_GAIN_CH1 ... NAU8540_REG_DIGITAL_MUX: | |
139 | case NAU8540_REG_P2P_CH1 ... NAU8540_REG_I2C_CTRL: | |
140 | case NAU8540_REG_I2C_DEVICE_ID: | |
141 | case NAU8540_REG_VMID_CTRL ... NAU8540_REG_MUTE: | |
142 | case NAU8540_REG_ANALOG_ADC1 ... NAU8540_REG_PWR: | |
143 | return true; | |
144 | default: | |
145 | return false; | |
146 | } | |
c1644e3d JH |
147 | |
148 | } | |
149 | ||
150 | static bool nau8540_writeable_reg(struct device *dev, unsigned int reg) | |
151 | { | |
babd6585 JH |
152 | switch (reg) { |
153 | case NAU8540_REG_SW_RESET ... NAU8540_REG_FLL_VCO_RSV: | |
154 | case NAU8540_REG_PCM_CTRL0 ... NAU8540_REG_PCM_CTRL4: | |
155 | case NAU8540_REG_ALC_CONTROL_1 ... NAU8540_REG_ALC_CONTROL_5: | |
156 | case NAU8540_REG_NOTCH_FIL1_CH1 ... NAU8540_REG_ADC_SAMPLE_RATE: | |
157 | case NAU8540_REG_DIGITAL_GAIN_CH1 ... NAU8540_REG_DIGITAL_MUX: | |
158 | case NAU8540_REG_GPIO_CTRL ... NAU8540_REG_I2C_CTRL: | |
159 | case NAU8540_REG_RST: | |
160 | case NAU8540_REG_VMID_CTRL ... NAU8540_REG_MUTE: | |
161 | case NAU8540_REG_ANALOG_ADC1 ... NAU8540_REG_PWR: | |
162 | return true; | |
163 | default: | |
164 | return false; | |
165 | } | |
c1644e3d JH |
166 | } |
167 | ||
168 | static bool nau8540_volatile_reg(struct device *dev, unsigned int reg) | |
169 | { | |
babd6585 JH |
170 | switch (reg) { |
171 | case NAU8540_REG_SW_RESET: | |
172 | case NAU8540_REG_ALC_GAIN_CH12 ... NAU8540_REG_ALC_STATUS: | |
173 | case NAU8540_REG_P2P_CH1 ... NAU8540_REG_PEAK_CH4: | |
174 | case NAU8540_REG_I2C_DEVICE_ID: | |
175 | case NAU8540_REG_RST: | |
176 | return true; | |
177 | default: | |
178 | return false; | |
179 | } | |
c1644e3d JH |
180 | } |
181 | ||
182 | ||
183 | static const DECLARE_TLV_DB_MINMAX(adc_vol_tlv, -12800, 3600); | |
184 | static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600); | |
185 | ||
186 | static const struct snd_kcontrol_new nau8540_snd_controls[] = { | |
babd6585 JH |
187 | SOC_SINGLE_TLV("Mic1 Volume", NAU8540_REG_DIGITAL_GAIN_CH1, |
188 | 0, 0x520, 0, adc_vol_tlv), | |
189 | SOC_SINGLE_TLV("Mic2 Volume", NAU8540_REG_DIGITAL_GAIN_CH2, | |
190 | 0, 0x520, 0, adc_vol_tlv), | |
191 | SOC_SINGLE_TLV("Mic3 Volume", NAU8540_REG_DIGITAL_GAIN_CH3, | |
192 | 0, 0x520, 0, adc_vol_tlv), | |
193 | SOC_SINGLE_TLV("Mic4 Volume", NAU8540_REG_DIGITAL_GAIN_CH4, | |
194 | 0, 0x520, 0, adc_vol_tlv), | |
195 | ||
196 | SOC_SINGLE_TLV("Frontend PGA1 Volume", NAU8540_REG_FEPGA3, | |
197 | 0, 0x25, 0, fepga_gain_tlv), | |
198 | SOC_SINGLE_TLV("Frontend PGA2 Volume", NAU8540_REG_FEPGA3, | |
199 | 8, 0x25, 0, fepga_gain_tlv), | |
200 | SOC_SINGLE_TLV("Frontend PGA3 Volume", NAU8540_REG_FEPGA4, | |
201 | 0, 0x25, 0, fepga_gain_tlv), | |
202 | SOC_SINGLE_TLV("Frontend PGA4 Volume", NAU8540_REG_FEPGA4, | |
203 | 8, 0x25, 0, fepga_gain_tlv), | |
c1644e3d JH |
204 | }; |
205 | ||
206 | static const char * const adc_channel[] = { | |
babd6585 | 207 | "ADC channel 1", "ADC channel 2", "ADC channel 3", "ADC channel 4" |
c1644e3d JH |
208 | }; |
209 | static SOC_ENUM_SINGLE_DECL( | |
babd6585 | 210 | digital_ch4_enum, NAU8540_REG_DIGITAL_MUX, 6, adc_channel); |
c1644e3d JH |
211 | |
212 | static const struct snd_kcontrol_new digital_ch4_mux = | |
babd6585 | 213 | SOC_DAPM_ENUM("Digital CH4 Select", digital_ch4_enum); |
c1644e3d JH |
214 | |
215 | static SOC_ENUM_SINGLE_DECL( | |
babd6585 | 216 | digital_ch3_enum, NAU8540_REG_DIGITAL_MUX, 4, adc_channel); |
c1644e3d JH |
217 | |
218 | static const struct snd_kcontrol_new digital_ch3_mux = | |
babd6585 | 219 | SOC_DAPM_ENUM("Digital CH3 Select", digital_ch3_enum); |
c1644e3d JH |
220 | |
221 | static SOC_ENUM_SINGLE_DECL( | |
babd6585 | 222 | digital_ch2_enum, NAU8540_REG_DIGITAL_MUX, 2, adc_channel); |
c1644e3d JH |
223 | |
224 | static const struct snd_kcontrol_new digital_ch2_mux = | |
babd6585 | 225 | SOC_DAPM_ENUM("Digital CH2 Select", digital_ch2_enum); |
c1644e3d JH |
226 | |
227 | static SOC_ENUM_SINGLE_DECL( | |
babd6585 | 228 | digital_ch1_enum, NAU8540_REG_DIGITAL_MUX, 0, adc_channel); |
c1644e3d JH |
229 | |
230 | static const struct snd_kcontrol_new digital_ch1_mux = | |
babd6585 | 231 | SOC_DAPM_ENUM("Digital CH1 Select", digital_ch1_enum); |
c1644e3d | 232 | |
6573c051 JH |
233 | static int adc_power_control(struct snd_soc_dapm_widget *w, |
234 | struct snd_kcontrol *k, int event) | |
235 | { | |
415bc3a0 KM |
236 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); |
237 | struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component); | |
6573c051 JH |
238 | |
239 | if (SND_SOC_DAPM_EVENT_ON(event)) { | |
240 | msleep(300); | |
241 | /* DO12 and DO34 pad output enable */ | |
242 | regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1, | |
243 | NAU8540_I2S_DO12_TRI, 0); | |
244 | regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2, | |
245 | NAU8540_I2S_DO34_TRI, 0); | |
246 | } else if (SND_SOC_DAPM_EVENT_OFF(event)) { | |
247 | regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1, | |
248 | NAU8540_I2S_DO12_TRI, NAU8540_I2S_DO12_TRI); | |
249 | regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2, | |
250 | NAU8540_I2S_DO34_TRI, NAU8540_I2S_DO34_TRI); | |
251 | } | |
252 | return 0; | |
253 | } | |
254 | ||
e4d0db60 JH |
255 | static int aiftx_power_control(struct snd_soc_dapm_widget *w, |
256 | struct snd_kcontrol *k, int event) | |
257 | { | |
415bc3a0 KM |
258 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); |
259 | struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component); | |
e4d0db60 JH |
260 | |
261 | if (SND_SOC_DAPM_EVENT_OFF(event)) { | |
262 | regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0001); | |
263 | regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0000); | |
264 | } | |
265 | return 0; | |
266 | } | |
267 | ||
c1644e3d | 268 | static const struct snd_soc_dapm_widget nau8540_dapm_widgets[] = { |
babd6585 JH |
269 | SND_SOC_DAPM_SUPPLY("MICBIAS2", NAU8540_REG_MIC_BIAS, 11, 0, NULL, 0), |
270 | SND_SOC_DAPM_SUPPLY("MICBIAS1", NAU8540_REG_MIC_BIAS, 10, 0, NULL, 0), | |
271 | ||
272 | SND_SOC_DAPM_INPUT("MIC1"), | |
273 | SND_SOC_DAPM_INPUT("MIC2"), | |
274 | SND_SOC_DAPM_INPUT("MIC3"), | |
275 | SND_SOC_DAPM_INPUT("MIC4"), | |
276 | ||
277 | SND_SOC_DAPM_PGA("Frontend PGA1", NAU8540_REG_PWR, 12, 0, NULL, 0), | |
278 | SND_SOC_DAPM_PGA("Frontend PGA2", NAU8540_REG_PWR, 13, 0, NULL, 0), | |
279 | SND_SOC_DAPM_PGA("Frontend PGA3", NAU8540_REG_PWR, 14, 0, NULL, 0), | |
280 | SND_SOC_DAPM_PGA("Frontend PGA4", NAU8540_REG_PWR, 15, 0, NULL, 0), | |
281 | ||
6573c051 JH |
282 | SND_SOC_DAPM_ADC_E("ADC1", NULL, |
283 | NAU8540_REG_POWER_MANAGEMENT, 0, 0, adc_power_control, | |
284 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), | |
285 | SND_SOC_DAPM_ADC_E("ADC2", NULL, | |
286 | NAU8540_REG_POWER_MANAGEMENT, 1, 0, adc_power_control, | |
287 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), | |
288 | SND_SOC_DAPM_ADC_E("ADC3", NULL, | |
289 | NAU8540_REG_POWER_MANAGEMENT, 2, 0, adc_power_control, | |
290 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), | |
291 | SND_SOC_DAPM_ADC_E("ADC4", NULL, | |
292 | NAU8540_REG_POWER_MANAGEMENT, 3, 0, adc_power_control, | |
293 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), | |
babd6585 JH |
294 | |
295 | SND_SOC_DAPM_PGA("ADC CH1", NAU8540_REG_ANALOG_PWR, 0, 0, NULL, 0), | |
296 | SND_SOC_DAPM_PGA("ADC CH2", NAU8540_REG_ANALOG_PWR, 1, 0, NULL, 0), | |
297 | SND_SOC_DAPM_PGA("ADC CH3", NAU8540_REG_ANALOG_PWR, 2, 0, NULL, 0), | |
298 | SND_SOC_DAPM_PGA("ADC CH4", NAU8540_REG_ANALOG_PWR, 3, 0, NULL, 0), | |
299 | ||
300 | SND_SOC_DAPM_MUX("Digital CH4 Mux", | |
301 | SND_SOC_NOPM, 0, 0, &digital_ch4_mux), | |
302 | SND_SOC_DAPM_MUX("Digital CH3 Mux", | |
303 | SND_SOC_NOPM, 0, 0, &digital_ch3_mux), | |
304 | SND_SOC_DAPM_MUX("Digital CH2 Mux", | |
305 | SND_SOC_NOPM, 0, 0, &digital_ch2_mux), | |
306 | SND_SOC_DAPM_MUX("Digital CH1 Mux", | |
307 | SND_SOC_NOPM, 0, 0, &digital_ch1_mux), | |
308 | ||
e4d0db60 JH |
309 | SND_SOC_DAPM_AIF_OUT_E("AIFTX", "Capture", 0, SND_SOC_NOPM, 0, 0, |
310 | aiftx_power_control, SND_SOC_DAPM_POST_PMD), | |
c1644e3d JH |
311 | }; |
312 | ||
313 | static const struct snd_soc_dapm_route nau8540_dapm_routes[] = { | |
babd6585 JH |
314 | {"Frontend PGA1", NULL, "MIC1"}, |
315 | {"Frontend PGA2", NULL, "MIC2"}, | |
316 | {"Frontend PGA3", NULL, "MIC3"}, | |
317 | {"Frontend PGA4", NULL, "MIC4"}, | |
318 | ||
319 | {"ADC1", NULL, "Frontend PGA1"}, | |
320 | {"ADC2", NULL, "Frontend PGA2"}, | |
321 | {"ADC3", NULL, "Frontend PGA3"}, | |
322 | {"ADC4", NULL, "Frontend PGA4"}, | |
323 | ||
324 | {"ADC CH1", NULL, "ADC1"}, | |
325 | {"ADC CH2", NULL, "ADC2"}, | |
326 | {"ADC CH3", NULL, "ADC3"}, | |
327 | {"ADC CH4", NULL, "ADC4"}, | |
328 | ||
329 | {"ADC1", NULL, "MICBIAS1"}, | |
330 | {"ADC2", NULL, "MICBIAS1"}, | |
331 | {"ADC3", NULL, "MICBIAS2"}, | |
332 | {"ADC4", NULL, "MICBIAS2"}, | |
333 | ||
334 | {"Digital CH1 Mux", "ADC channel 1", "ADC CH1"}, | |
335 | {"Digital CH1 Mux", "ADC channel 2", "ADC CH2"}, | |
336 | {"Digital CH1 Mux", "ADC channel 3", "ADC CH3"}, | |
337 | {"Digital CH1 Mux", "ADC channel 4", "ADC CH4"}, | |
338 | ||
339 | {"Digital CH2 Mux", "ADC channel 1", "ADC CH1"}, | |
340 | {"Digital CH2 Mux", "ADC channel 2", "ADC CH2"}, | |
341 | {"Digital CH2 Mux", "ADC channel 3", "ADC CH3"}, | |
342 | {"Digital CH2 Mux", "ADC channel 4", "ADC CH4"}, | |
343 | ||
344 | {"Digital CH3 Mux", "ADC channel 1", "ADC CH1"}, | |
345 | {"Digital CH3 Mux", "ADC channel 2", "ADC CH2"}, | |
346 | {"Digital CH3 Mux", "ADC channel 3", "ADC CH3"}, | |
347 | {"Digital CH3 Mux", "ADC channel 4", "ADC CH4"}, | |
348 | ||
349 | {"Digital CH4 Mux", "ADC channel 1", "ADC CH1"}, | |
350 | {"Digital CH4 Mux", "ADC channel 2", "ADC CH2"}, | |
351 | {"Digital CH4 Mux", "ADC channel 3", "ADC CH3"}, | |
352 | {"Digital CH4 Mux", "ADC channel 4", "ADC CH4"}, | |
353 | ||
354 | {"AIFTX", NULL, "Digital CH1 Mux"}, | |
355 | {"AIFTX", NULL, "Digital CH2 Mux"}, | |
356 | {"AIFTX", NULL, "Digital CH3 Mux"}, | |
357 | {"AIFTX", NULL, "Digital CH4 Mux"}, | |
c1644e3d JH |
358 | }; |
359 | ||
360 | static int nau8540_clock_check(struct nau8540 *nau8540, int rate, int osr) | |
361 | { | |
babd6585 JH |
362 | if (osr >= ARRAY_SIZE(osr_adc_sel)) |
363 | return -EINVAL; | |
c1644e3d | 364 | |
babd6585 JH |
365 | if (rate * osr > CLK_ADC_MAX) { |
366 | dev_err(nau8540->dev, "exceed the maximum frequency of CLK_ADC\n"); | |
367 | return -EINVAL; | |
368 | } | |
c1644e3d | 369 | |
babd6585 | 370 | return 0; |
c1644e3d JH |
371 | } |
372 | ||
373 | static int nau8540_hw_params(struct snd_pcm_substream *substream, | |
babd6585 | 374 | struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) |
c1644e3d | 375 | { |
415bc3a0 KM |
376 | struct snd_soc_component *component = dai->component; |
377 | struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component); | |
babd6585 JH |
378 | unsigned int val_len = 0, osr; |
379 | ||
380 | /* CLK_ADC = OSR * FS | |
381 | * ADC clock frequency is defined as Over Sampling Rate (OSR) | |
382 | * multiplied by the audio sample rate (Fs). Note that the OSR and Fs | |
383 | * values must be selected such that the maximum frequency is less | |
384 | * than 6.144 MHz. | |
385 | */ | |
386 | regmap_read(nau8540->regmap, NAU8540_REG_ADC_SAMPLE_RATE, &osr); | |
387 | osr &= NAU8540_ADC_OSR_MASK; | |
388 | if (nau8540_clock_check(nau8540, params_rate(params), osr)) | |
389 | return -EINVAL; | |
390 | regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC, | |
391 | NAU8540_CLK_ADC_SRC_MASK, | |
392 | osr_adc_sel[osr].clk_src << NAU8540_CLK_ADC_SRC_SFT); | |
393 | ||
394 | switch (params_width(params)) { | |
395 | case 16: | |
396 | val_len |= NAU8540_I2S_DL_16; | |
397 | break; | |
398 | case 20: | |
399 | val_len |= NAU8540_I2S_DL_20; | |
400 | break; | |
401 | case 24: | |
402 | val_len |= NAU8540_I2S_DL_24; | |
403 | break; | |
404 | case 32: | |
405 | val_len |= NAU8540_I2S_DL_32; | |
406 | break; | |
407 | default: | |
408 | return -EINVAL; | |
409 | } | |
410 | ||
411 | regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0, | |
412 | NAU8540_I2S_DL_MASK, val_len); | |
413 | ||
414 | return 0; | |
c1644e3d JH |
415 | } |
416 | ||
417 | static int nau8540_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) | |
418 | { | |
415bc3a0 KM |
419 | struct snd_soc_component *component = dai->component; |
420 | struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component); | |
babd6585 JH |
421 | unsigned int ctrl1_val = 0, ctrl2_val = 0; |
422 | ||
423 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
424 | case SND_SOC_DAIFMT_CBM_CFM: | |
425 | ctrl2_val |= NAU8540_I2S_MS_MASTER; | |
426 | break; | |
427 | case SND_SOC_DAIFMT_CBS_CFS: | |
428 | break; | |
429 | default: | |
430 | return -EINVAL; | |
431 | } | |
432 | ||
433 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
434 | case SND_SOC_DAIFMT_NB_NF: | |
435 | break; | |
436 | case SND_SOC_DAIFMT_IB_NF: | |
437 | ctrl1_val |= NAU8540_I2S_BP_INV; | |
438 | break; | |
439 | default: | |
440 | return -EINVAL; | |
441 | } | |
442 | ||
443 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
444 | case SND_SOC_DAIFMT_I2S: | |
445 | ctrl1_val |= NAU8540_I2S_DF_I2S; | |
446 | break; | |
447 | case SND_SOC_DAIFMT_LEFT_J: | |
448 | ctrl1_val |= NAU8540_I2S_DF_LEFT; | |
449 | break; | |
450 | case SND_SOC_DAIFMT_RIGHT_J: | |
451 | ctrl1_val |= NAU8540_I2S_DF_RIGTH; | |
452 | break; | |
453 | case SND_SOC_DAIFMT_DSP_A: | |
454 | ctrl1_val |= NAU8540_I2S_DF_PCM_AB; | |
455 | break; | |
456 | case SND_SOC_DAIFMT_DSP_B: | |
457 | ctrl1_val |= NAU8540_I2S_DF_PCM_AB; | |
458 | ctrl1_val |= NAU8540_I2S_PCMB_EN; | |
459 | break; | |
460 | default: | |
461 | return -EINVAL; | |
462 | } | |
463 | ||
464 | regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0, | |
465 | NAU8540_I2S_DL_MASK | NAU8540_I2S_DF_MASK | | |
466 | NAU8540_I2S_BP_INV | NAU8540_I2S_PCMB_EN, ctrl1_val); | |
467 | regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1, | |
468 | NAU8540_I2S_MS_MASK | NAU8540_I2S_DO12_OE, ctrl2_val); | |
469 | regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2, | |
470 | NAU8540_I2S_DO34_OE, 0); | |
471 | ||
472 | return 0; | |
c1644e3d JH |
473 | } |
474 | ||
475 | /** | |
476 | * nau8540_set_tdm_slot - configure DAI TX TDM. | |
477 | * @dai: DAI | |
478 | * @tx_mask: bitmask representing active TX slots. Ex. | |
479 | * 0xf for normal 4 channel TDM. | |
480 | * 0xf0 for shifted 4 channel TDM | |
481 | * @rx_mask: no used. | |
482 | * @slots: Number of slots in use. | |
483 | * @slot_width: Width in bits for each slot. | |
484 | * | |
485 | * Configures a DAI for TDM operation. Only support 4 slots TDM. | |
486 | */ | |
487 | static int nau8540_set_tdm_slot(struct snd_soc_dai *dai, | |
babd6585 | 488 | unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width) |
c1644e3d | 489 | { |
415bc3a0 KM |
490 | struct snd_soc_component *component = dai->component; |
491 | struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component); | |
babd6585 JH |
492 | unsigned int ctrl2_val = 0, ctrl4_val = 0; |
493 | ||
494 | if (slots > 4 || ((tx_mask & 0xf0) && (tx_mask & 0xf))) | |
495 | return -EINVAL; | |
496 | ||
497 | ctrl4_val |= (NAU8540_TDM_MODE | NAU8540_TDM_OFFSET_EN); | |
498 | if (tx_mask & 0xf0) { | |
499 | ctrl2_val = 4 * slot_width; | |
500 | ctrl4_val |= (tx_mask >> 4); | |
501 | } else { | |
502 | ctrl4_val |= tx_mask; | |
503 | } | |
504 | regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL4, | |
505 | NAU8540_TDM_MODE | NAU8540_TDM_OFFSET_EN | | |
506 | NAU8540_TDM_TX_MASK, ctrl4_val); | |
507 | regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1, | |
508 | NAU8540_I2S_DO12_OE, NAU8540_I2S_DO12_OE); | |
509 | regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2, | |
510 | NAU8540_I2S_DO34_OE | NAU8540_I2S_TSLOT_L_MASK, | |
511 | NAU8540_I2S_DO34_OE | ctrl2_val); | |
512 | ||
513 | return 0; | |
c1644e3d JH |
514 | } |
515 | ||
516 | ||
517 | static const struct snd_soc_dai_ops nau8540_dai_ops = { | |
babd6585 JH |
518 | .hw_params = nau8540_hw_params, |
519 | .set_fmt = nau8540_set_fmt, | |
520 | .set_tdm_slot = nau8540_set_tdm_slot, | |
c1644e3d JH |
521 | }; |
522 | ||
523 | #define NAU8540_RATES SNDRV_PCM_RATE_8000_48000 | |
524 | #define NAU8540_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ | |
babd6585 | 525 | | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) |
c1644e3d JH |
526 | |
527 | static struct snd_soc_dai_driver nau8540_dai = { | |
babd6585 JH |
528 | .name = "nau8540-hifi", |
529 | .capture = { | |
530 | .stream_name = "Capture", | |
531 | .channels_min = 1, | |
532 | .channels_max = 4, | |
533 | .rates = NAU8540_RATES, | |
534 | .formats = NAU8540_FORMATS, | |
535 | }, | |
536 | .ops = &nau8540_dai_ops, | |
c1644e3d JH |
537 | }; |
538 | ||
539 | /** | |
540 | * nau8540_calc_fll_param - Calculate FLL parameters. | |
541 | * @fll_in: external clock provided to codec. | |
542 | * @fs: sampling rate. | |
543 | * @fll_param: Pointer to structure of FLL parameters. | |
544 | * | |
545 | * Calculate FLL parameters to configure codec. | |
546 | * | |
547 | * Returns 0 for success or negative error code. | |
548 | */ | |
549 | static int nau8540_calc_fll_param(unsigned int fll_in, | |
babd6585 | 550 | unsigned int fs, struct nau8540_fll *fll_param) |
c1644e3d | 551 | { |
babd6585 JH |
552 | u64 fvco, fvco_max; |
553 | unsigned int fref, i, fvco_sel; | |
554 | ||
555 | /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing | |
556 | * freq_in by 1, 2, 4, or 8 using FLL pre-scalar. | |
557 | * FREF = freq_in / NAU8540_FLL_REF_DIV_MASK | |
558 | */ | |
559 | for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) { | |
560 | fref = fll_in / fll_pre_scalar[i].param; | |
561 | if (fref <= NAU_FREF_MAX) | |
562 | break; | |
563 | } | |
564 | if (i == ARRAY_SIZE(fll_pre_scalar)) | |
565 | return -EINVAL; | |
566 | fll_param->clk_ref_div = fll_pre_scalar[i].val; | |
567 | ||
568 | /* Choose the FLL ratio based on FREF */ | |
569 | for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) { | |
570 | if (fref >= fll_ratio[i].param) | |
571 | break; | |
572 | } | |
573 | if (i == ARRAY_SIZE(fll_ratio)) | |
574 | return -EINVAL; | |
575 | fll_param->ratio = fll_ratio[i].val; | |
576 | ||
577 | /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs. | |
578 | * FDCO must be within the 90MHz - 124MHz or the FFL cannot be | |
579 | * guaranteed across the full range of operation. | |
580 | * FDCO = freq_out * 2 * mclk_src_scaling | |
581 | */ | |
582 | fvco_max = 0; | |
583 | fvco_sel = ARRAY_SIZE(mclk_src_scaling); | |
584 | for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) { | |
cd7fdc45 | 585 | fvco = 256ULL * fs * 2 * mclk_src_scaling[i].param; |
babd6585 JH |
586 | if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX && |
587 | fvco_max < fvco) { | |
588 | fvco_max = fvco; | |
589 | fvco_sel = i; | |
590 | } | |
591 | } | |
592 | if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel) | |
593 | return -EINVAL; | |
594 | fll_param->mclk_src = mclk_src_scaling[fvco_sel].val; | |
595 | ||
596 | /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional | |
597 | * input based on FDCO, FREF and FLL ratio. | |
598 | */ | |
599 | fvco = div_u64(fvco_max << 16, fref * fll_param->ratio); | |
600 | fll_param->fll_int = (fvco >> 16) & 0x3FF; | |
601 | fll_param->fll_frac = fvco & 0xFFFF; | |
602 | return 0; | |
c1644e3d JH |
603 | } |
604 | ||
605 | static void nau8540_fll_apply(struct regmap *regmap, | |
babd6585 | 606 | struct nau8540_fll *fll_param) |
c1644e3d | 607 | { |
babd6585 JH |
608 | regmap_update_bits(regmap, NAU8540_REG_CLOCK_SRC, |
609 | NAU8540_CLK_SRC_MASK | NAU8540_CLK_MCLK_SRC_MASK, | |
610 | NAU8540_CLK_SRC_MCLK | fll_param->mclk_src); | |
611 | regmap_update_bits(regmap, NAU8540_REG_FLL1, | |
fe83b1b7 JH |
612 | NAU8540_FLL_RATIO_MASK | NAU8540_ICTRL_LATCH_MASK, |
613 | fll_param->ratio | (0x6 << NAU8540_ICTRL_LATCH_SFT)); | |
babd6585 JH |
614 | /* FLL 16-bit fractional input */ |
615 | regmap_write(regmap, NAU8540_REG_FLL2, fll_param->fll_frac); | |
616 | /* FLL 10-bit integer input */ | |
617 | regmap_update_bits(regmap, NAU8540_REG_FLL3, | |
618 | NAU8540_FLL_INTEGER_MASK, fll_param->fll_int); | |
619 | /* FLL pre-scaler */ | |
620 | regmap_update_bits(regmap, NAU8540_REG_FLL4, | |
621 | NAU8540_FLL_REF_DIV_MASK, | |
622 | fll_param->clk_ref_div << NAU8540_FLL_REF_DIV_SFT); | |
623 | regmap_update_bits(regmap, NAU8540_REG_FLL5, | |
624 | NAU8540_FLL_CLK_SW_MASK, NAU8540_FLL_CLK_SW_REF); | |
625 | regmap_update_bits(regmap, | |
626 | NAU8540_REG_FLL6, NAU8540_DCO_EN, 0); | |
627 | if (fll_param->fll_frac) { | |
628 | regmap_update_bits(regmap, NAU8540_REG_FLL5, | |
629 | NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN | | |
630 | NAU8540_FLL_FTR_SW_MASK, | |
631 | NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN | | |
632 | NAU8540_FLL_FTR_SW_FILTER); | |
633 | regmap_update_bits(regmap, NAU8540_REG_FLL6, | |
fe83b1b7 JH |
634 | NAU8540_SDM_EN | NAU8540_CUTOFF500, |
635 | NAU8540_SDM_EN | NAU8540_CUTOFF500); | |
babd6585 JH |
636 | } else { |
637 | regmap_update_bits(regmap, NAU8540_REG_FLL5, | |
638 | NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN | | |
639 | NAU8540_FLL_FTR_SW_MASK, NAU8540_FLL_FTR_SW_ACCU); | |
fe83b1b7 JH |
640 | regmap_update_bits(regmap, NAU8540_REG_FLL6, |
641 | NAU8540_SDM_EN | NAU8540_CUTOFF500, 0); | |
babd6585 | 642 | } |
c1644e3d JH |
643 | } |
644 | ||
645 | /* freq_out must be 256*Fs in order to achieve the best performance */ | |
415bc3a0 | 646 | static int nau8540_set_pll(struct snd_soc_component *component, int pll_id, int source, |
babd6585 | 647 | unsigned int freq_in, unsigned int freq_out) |
c1644e3d | 648 | { |
415bc3a0 | 649 | struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component); |
babd6585 JH |
650 | struct nau8540_fll fll_param; |
651 | int ret, fs; | |
652 | ||
653 | switch (pll_id) { | |
654 | case NAU8540_CLK_FLL_MCLK: | |
655 | regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3, | |
fe83b1b7 JH |
656 | NAU8540_FLL_CLK_SRC_MASK | NAU8540_GAIN_ERR_MASK, |
657 | NAU8540_FLL_CLK_SRC_MCLK | 0); | |
babd6585 JH |
658 | break; |
659 | ||
660 | case NAU8540_CLK_FLL_BLK: | |
661 | regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3, | |
fe83b1b7 JH |
662 | NAU8540_FLL_CLK_SRC_MASK | NAU8540_GAIN_ERR_MASK, |
663 | NAU8540_FLL_CLK_SRC_BLK | | |
664 | (0xf << NAU8540_GAIN_ERR_SFT)); | |
babd6585 JH |
665 | break; |
666 | ||
667 | case NAU8540_CLK_FLL_FS: | |
668 | regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3, | |
fe83b1b7 JH |
669 | NAU8540_FLL_CLK_SRC_MASK | NAU8540_GAIN_ERR_MASK, |
670 | NAU8540_FLL_CLK_SRC_FS | | |
671 | (0xf << NAU8540_GAIN_ERR_SFT)); | |
babd6585 JH |
672 | break; |
673 | ||
674 | default: | |
675 | dev_err(nau8540->dev, "Invalid clock id (%d)\n", pll_id); | |
676 | return -EINVAL; | |
677 | } | |
678 | dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n", | |
679 | freq_out, pll_id); | |
680 | ||
681 | fs = freq_out / 256; | |
682 | ret = nau8540_calc_fll_param(freq_in, fs, &fll_param); | |
683 | if (ret < 0) { | |
684 | dev_err(nau8540->dev, "Unsupported input clock %d\n", freq_in); | |
685 | return ret; | |
686 | } | |
687 | dev_dbg(nau8540->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n", | |
688 | fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac, | |
689 | fll_param.fll_int, fll_param.clk_ref_div); | |
690 | ||
691 | nau8540_fll_apply(nau8540->regmap, &fll_param); | |
692 | mdelay(2); | |
693 | regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC, | |
694 | NAU8540_CLK_SRC_MASK, NAU8540_CLK_SRC_VCO); | |
695 | ||
696 | return 0; | |
c1644e3d JH |
697 | } |
698 | ||
415bc3a0 | 699 | static int nau8540_set_sysclk(struct snd_soc_component *component, |
babd6585 | 700 | int clk_id, int source, unsigned int freq, int dir) |
c1644e3d | 701 | { |
415bc3a0 | 702 | struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component); |
babd6585 JH |
703 | |
704 | switch (clk_id) { | |
705 | case NAU8540_CLK_DIS: | |
706 | case NAU8540_CLK_MCLK: | |
707 | regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC, | |
708 | NAU8540_CLK_SRC_MASK, NAU8540_CLK_SRC_MCLK); | |
709 | regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6, | |
710 | NAU8540_DCO_EN, 0); | |
711 | break; | |
712 | ||
713 | case NAU8540_CLK_INTERNAL: | |
714 | regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6, | |
715 | NAU8540_DCO_EN, NAU8540_DCO_EN); | |
716 | regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC, | |
717 | NAU8540_CLK_SRC_MASK, NAU8540_CLK_SRC_VCO); | |
718 | break; | |
719 | ||
720 | default: | |
721 | dev_err(nau8540->dev, "Invalid clock id (%d)\n", clk_id); | |
722 | return -EINVAL; | |
723 | } | |
724 | ||
725 | dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n", | |
726 | freq, clk_id); | |
727 | ||
728 | return 0; | |
c1644e3d JH |
729 | } |
730 | ||
731 | static void nau8540_reset_chip(struct regmap *regmap) | |
732 | { | |
babd6585 JH |
733 | regmap_write(regmap, NAU8540_REG_SW_RESET, 0x00); |
734 | regmap_write(regmap, NAU8540_REG_SW_RESET, 0x00); | |
c1644e3d JH |
735 | } |
736 | ||
737 | static void nau8540_init_regs(struct nau8540 *nau8540) | |
738 | { | |
babd6585 JH |
739 | struct regmap *regmap = nau8540->regmap; |
740 | ||
741 | /* Enable Bias/VMID/VMID Tieoff */ | |
742 | regmap_update_bits(regmap, NAU8540_REG_VMID_CTRL, | |
743 | NAU8540_VMID_EN | NAU8540_VMID_SEL_MASK, | |
744 | NAU8540_VMID_EN | (0x2 << NAU8540_VMID_SEL_SFT)); | |
745 | regmap_update_bits(regmap, NAU8540_REG_REFERENCE, | |
746 | NAU8540_PRECHARGE_DIS | NAU8540_GLOBAL_BIAS_EN, | |
747 | NAU8540_PRECHARGE_DIS | NAU8540_GLOBAL_BIAS_EN); | |
748 | mdelay(2); | |
749 | regmap_update_bits(regmap, NAU8540_REG_MIC_BIAS, | |
750 | NAU8540_PU_PRE, NAU8540_PU_PRE); | |
751 | regmap_update_bits(regmap, NAU8540_REG_CLOCK_CTRL, | |
752 | NAU8540_CLK_ADC_EN | NAU8540_CLK_I2S_EN, | |
753 | NAU8540_CLK_ADC_EN | NAU8540_CLK_I2S_EN); | |
e4d0db60 JH |
754 | /* ADC OSR selection, CLK_ADC = Fs * OSR; |
755 | * Channel time alignment enable. | |
756 | */ | |
babd6585 | 757 | regmap_update_bits(regmap, NAU8540_REG_ADC_SAMPLE_RATE, |
e4d0db60 JH |
758 | NAU8540_CH_SYNC | NAU8540_ADC_OSR_MASK, |
759 | NAU8540_CH_SYNC | NAU8540_ADC_OSR_64); | |
14323ff8 JH |
760 | /* PGA input mode selection */ |
761 | regmap_update_bits(regmap, NAU8540_REG_FEPGA1, | |
762 | NAU8540_FEPGA1_MODCH2_SHT | NAU8540_FEPGA1_MODCH1_SHT, | |
763 | NAU8540_FEPGA1_MODCH2_SHT | NAU8540_FEPGA1_MODCH1_SHT); | |
764 | regmap_update_bits(regmap, NAU8540_REG_FEPGA2, | |
765 | NAU8540_FEPGA2_MODCH4_SHT | NAU8540_FEPGA2_MODCH3_SHT, | |
766 | NAU8540_FEPGA2_MODCH4_SHT | NAU8540_FEPGA2_MODCH3_SHT); | |
6573c051 JH |
767 | /* DO12 and DO34 pad output disable */ |
768 | regmap_update_bits(regmap, NAU8540_REG_PCM_CTRL1, | |
769 | NAU8540_I2S_DO12_TRI, NAU8540_I2S_DO12_TRI); | |
770 | regmap_update_bits(regmap, NAU8540_REG_PCM_CTRL2, | |
771 | NAU8540_I2S_DO34_TRI, NAU8540_I2S_DO34_TRI); | |
c1644e3d JH |
772 | } |
773 | ||
415bc3a0 | 774 | static int __maybe_unused nau8540_suspend(struct snd_soc_component *component) |
c1644e3d | 775 | { |
415bc3a0 | 776 | struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component); |
c1644e3d | 777 | |
babd6585 JH |
778 | regcache_cache_only(nau8540->regmap, true); |
779 | regcache_mark_dirty(nau8540->regmap); | |
c1644e3d | 780 | |
babd6585 | 781 | return 0; |
c1644e3d JH |
782 | } |
783 | ||
415bc3a0 | 784 | static int __maybe_unused nau8540_resume(struct snd_soc_component *component) |
c1644e3d | 785 | { |
415bc3a0 | 786 | struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component); |
c1644e3d | 787 | |
babd6585 JH |
788 | regcache_cache_only(nau8540->regmap, false); |
789 | regcache_sync(nau8540->regmap); | |
c1644e3d | 790 | |
babd6585 | 791 | return 0; |
c1644e3d JH |
792 | } |
793 | ||
415bc3a0 KM |
794 | static const struct snd_soc_component_driver nau8540_component_driver = { |
795 | .set_sysclk = nau8540_set_sysclk, | |
796 | .set_pll = nau8540_set_pll, | |
797 | .suspend = nau8540_suspend, | |
798 | .resume = nau8540_resume, | |
799 | .controls = nau8540_snd_controls, | |
800 | .num_controls = ARRAY_SIZE(nau8540_snd_controls), | |
801 | .dapm_widgets = nau8540_dapm_widgets, | |
802 | .num_dapm_widgets = ARRAY_SIZE(nau8540_dapm_widgets), | |
803 | .dapm_routes = nau8540_dapm_routes, | |
804 | .num_dapm_routes = ARRAY_SIZE(nau8540_dapm_routes), | |
805 | .suspend_bias_off = 1, | |
806 | .idle_bias_on = 1, | |
807 | .use_pmdown_time = 1, | |
808 | .endianness = 1, | |
809 | .non_legacy_dai_naming = 1, | |
c1644e3d JH |
810 | }; |
811 | ||
812 | static const struct regmap_config nau8540_regmap_config = { | |
babd6585 JH |
813 | .val_bits = 16, |
814 | .reg_bits = 16, | |
c1644e3d | 815 | |
babd6585 JH |
816 | .max_register = NAU8540_REG_MAX, |
817 | .readable_reg = nau8540_readable_reg, | |
818 | .writeable_reg = nau8540_writeable_reg, | |
819 | .volatile_reg = nau8540_volatile_reg, | |
c1644e3d | 820 | |
babd6585 JH |
821 | .cache_type = REGCACHE_RBTREE, |
822 | .reg_defaults = nau8540_reg_defaults, | |
823 | .num_reg_defaults = ARRAY_SIZE(nau8540_reg_defaults), | |
c1644e3d JH |
824 | }; |
825 | ||
826 | static int nau8540_i2c_probe(struct i2c_client *i2c, | |
babd6585 | 827 | const struct i2c_device_id *id) |
c1644e3d | 828 | { |
babd6585 JH |
829 | struct device *dev = &i2c->dev; |
830 | struct nau8540 *nau8540 = dev_get_platdata(dev); | |
831 | int ret, value; | |
832 | ||
833 | if (!nau8540) { | |
834 | nau8540 = devm_kzalloc(dev, sizeof(*nau8540), GFP_KERNEL); | |
835 | if (!nau8540) | |
836 | return -ENOMEM; | |
837 | } | |
838 | i2c_set_clientdata(i2c, nau8540); | |
839 | ||
840 | nau8540->regmap = devm_regmap_init_i2c(i2c, &nau8540_regmap_config); | |
841 | if (IS_ERR(nau8540->regmap)) | |
842 | return PTR_ERR(nau8540->regmap); | |
843 | ret = regmap_read(nau8540->regmap, NAU8540_REG_I2C_DEVICE_ID, &value); | |
844 | if (ret < 0) { | |
845 | dev_err(dev, "Failed to read device id from the NAU85L40: %d\n", | |
846 | ret); | |
847 | return ret; | |
848 | } | |
849 | ||
850 | nau8540->dev = dev; | |
851 | nau8540_reset_chip(nau8540->regmap); | |
852 | nau8540_init_regs(nau8540); | |
853 | ||
415bc3a0 KM |
854 | return devm_snd_soc_register_component(dev, |
855 | &nau8540_component_driver, &nau8540_dai, 1); | |
c1644e3d JH |
856 | } |
857 | ||
c1644e3d | 858 | static const struct i2c_device_id nau8540_i2c_ids[] = { |
babd6585 JH |
859 | { "nau8540", 0 }, |
860 | { } | |
c1644e3d JH |
861 | }; |
862 | MODULE_DEVICE_TABLE(i2c, nau8540_i2c_ids); | |
863 | ||
864 | #ifdef CONFIG_OF | |
865 | static const struct of_device_id nau8540_of_ids[] = { | |
babd6585 JH |
866 | { .compatible = "nuvoton,nau8540", }, |
867 | {} | |
c1644e3d JH |
868 | }; |
869 | MODULE_DEVICE_TABLE(of, nau8540_of_ids); | |
870 | #endif | |
871 | ||
872 | static struct i2c_driver nau8540_i2c_driver = { | |
babd6585 JH |
873 | .driver = { |
874 | .name = "nau8540", | |
875 | .of_match_table = of_match_ptr(nau8540_of_ids), | |
876 | }, | |
877 | .probe = nau8540_i2c_probe, | |
babd6585 | 878 | .id_table = nau8540_i2c_ids, |
c1644e3d JH |
879 | }; |
880 | module_i2c_driver(nau8540_i2c_driver); | |
881 | ||
882 | MODULE_DESCRIPTION("ASoC NAU85L40 driver"); | |
883 | MODULE_AUTHOR("John Hsu <KCHSU0@nuvoton.com>"); | |
884 | MODULE_LICENSE("GPL v2"); |