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Merge airlied/drm-next into drm-intel-next-queued
[linux-2.6-block.git] / sound / soc / codecs / max98927.c
CommitLineData
7c0c2000
RL		 1/*
2 * max98927.c -- MAX98927 ALSA Soc Audio driver
3 *
4eee2024 4 * Copyright (C) 2016-2017 Maxim Integrated Products
7c0c2000
RL		 5 * Author: Ryan Lee <ryans.lee@maximintegrated.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#include <linux/acpi.h>
14#include <linux/i2c.h>
15#include <linux/module.h>
16#include <linux/regmap.h>
17#include <linux/slab.h>
18#include <linux/cdev.h>
19#include <sound/pcm.h>
20#include <sound/pcm_params.h>
21#include <sound/soc.h>
22#include <linux/gpio.h>
23#include <linux/of_gpio.h>
24#include <sound/tlv.h>
25#include "max98927.h"
26
27static struct reg_default max98927_reg[] = {
28 {MAX98927_R0001_INT_RAW1, 0x00},
29 {MAX98927_R0002_INT_RAW2, 0x00},
30 {MAX98927_R0003_INT_RAW3, 0x00},
31 {MAX98927_R0004_INT_STATE1, 0x00},
32 {MAX98927_R0005_INT_STATE2, 0x00},
33 {MAX98927_R0006_INT_STATE3, 0x00},
34 {MAX98927_R0007_INT_FLAG1, 0x00},
35 {MAX98927_R0008_INT_FLAG2, 0x00},
36 {MAX98927_R0009_INT_FLAG3, 0x00},
37 {MAX98927_R000A_INT_EN1, 0x00},
38 {MAX98927_R000B_INT_EN2, 0x00},
39 {MAX98927_R000C_INT_EN3, 0x00},
40 {MAX98927_R000D_INT_FLAG_CLR1, 0x00},
41 {MAX98927_R000E_INT_FLAG_CLR2, 0x00},
42 {MAX98927_R000F_INT_FLAG_CLR3, 0x00},
43 {MAX98927_R0010_IRQ_CTRL, 0x00},
44 {MAX98927_R0011_CLK_MON, 0x00},
45 {MAX98927_R0012_WDOG_CTRL, 0x00},
46 {MAX98927_R0013_WDOG_RST, 0x00},
848844b8
RL		 47 {MAX98927_R0014_MEAS_ADC_THERM_WARN_THRESH, 0x75},
48 {MAX98927_R0015_MEAS_ADC_THERM_SHDN_THRESH, 0x8c},
49 {MAX98927_R0016_MEAS_ADC_THERM_HYSTERESIS, 0x08},
7c0c2000
RL		 50 {MAX98927_R0017_PIN_CFG, 0x55},
51 {MAX98927_R0018_PCM_RX_EN_A, 0x00},
52 {MAX98927_R0019_PCM_RX_EN_B, 0x00},
53 {MAX98927_R001A_PCM_TX_EN_A, 0x00},
54 {MAX98927_R001B_PCM_TX_EN_B, 0x00},
55 {MAX98927_R001C_PCM_TX_HIZ_CTRL_A, 0x00},
56 {MAX98927_R001D_PCM_TX_HIZ_CTRL_B, 0x00},
57 {MAX98927_R001E_PCM_TX_CH_SRC_A, 0x00},
58 {MAX98927_R001F_PCM_TX_CH_SRC_B, 0x00},
59 {MAX98927_R0020_PCM_MODE_CFG, 0x40},
60 {MAX98927_R0021_PCM_MASTER_MODE, 0x00},
61 {MAX98927_R0022_PCM_CLK_SETUP, 0x22},
62 {MAX98927_R0023_PCM_SR_SETUP1, 0x00},
63 {MAX98927_R0024_PCM_SR_SETUP2, 0x00},
64 {MAX98927_R0025_PCM_TO_SPK_MONOMIX_A, 0x00},
65 {MAX98927_R0026_PCM_TO_SPK_MONOMIX_B, 0x00},
66 {MAX98927_R0027_ICC_RX_EN_A, 0x00},
67 {MAX98927_R0028_ICC_RX_EN_B, 0x00},
68 {MAX98927_R002B_ICC_TX_EN_A, 0x00},
69 {MAX98927_R002C_ICC_TX_EN_B, 0x00},
70 {MAX98927_R002E_ICC_HIZ_MANUAL_MODE, 0x00},
71 {MAX98927_R002F_ICC_TX_HIZ_EN_A, 0x00},
72 {MAX98927_R0030_ICC_TX_HIZ_EN_B, 0x00},
73 {MAX98927_R0031_ICC_LNK_EN, 0x00},
74 {MAX98927_R0032_PDM_TX_EN, 0x00},
75 {MAX98927_R0033_PDM_TX_HIZ_CTRL, 0x00},
76 {MAX98927_R0034_PDM_TX_CTRL, 0x00},
77 {MAX98927_R0035_PDM_RX_CTRL, 0x00},
78 {MAX98927_R0036_AMP_VOL_CTRL, 0x00},
79 {MAX98927_R0037_AMP_DSP_CFG, 0x02},
80 {MAX98927_R0038_TONE_GEN_DC_CFG, 0x00},
81 {MAX98927_R0039_DRE_CTRL, 0x01},
82 {MAX98927_R003A_AMP_EN, 0x00},
83 {MAX98927_R003B_SPK_SRC_SEL, 0x00},
84 {MAX98927_R003C_SPK_GAIN, 0x00},
848844b8 85 {MAX98927_R003D_SSM_CFG, 0x04},
7c0c2000
RL		 86 {MAX98927_R003E_MEAS_EN, 0x00},
87 {MAX98927_R003F_MEAS_DSP_CFG, 0x04},
88 {MAX98927_R0040_BOOST_CTRL0, 0x00},
89 {MAX98927_R0041_BOOST_CTRL3, 0x00},
90 {MAX98927_R0042_BOOST_CTRL1, 0x00},
91 {MAX98927_R0043_MEAS_ADC_CFG, 0x00},
848844b8 92 {MAX98927_R0044_MEAS_ADC_BASE_MSB, 0x01},
7c0c2000
RL		 93 {MAX98927_R0045_MEAS_ADC_BASE_LSB, 0x00},
94 {MAX98927_R0046_ADC_CH0_DIVIDE, 0x00},
95 {MAX98927_R0047_ADC_CH1_DIVIDE, 0x00},
96 {MAX98927_R0048_ADC_CH2_DIVIDE, 0x00},
97 {MAX98927_R0049_ADC_CH0_FILT_CFG, 0x00},
98 {MAX98927_R004A_ADC_CH1_FILT_CFG, 0x00},
99 {MAX98927_R004B_ADC_CH2_FILT_CFG, 0x00},
100 {MAX98927_R004C_MEAS_ADC_CH0_READ, 0x00},
101 {MAX98927_R004D_MEAS_ADC_CH1_READ, 0x00},
102 {MAX98927_R004E_MEAS_ADC_CH2_READ, 0x00},
103 {MAX98927_R0051_BROWNOUT_STATUS, 0x00},
104 {MAX98927_R0052_BROWNOUT_EN, 0x00},
105 {MAX98927_R0053_BROWNOUT_INFINITE_HOLD, 0x00},
106 {MAX98927_R0054_BROWNOUT_INFINITE_HOLD_CLR, 0x00},
107 {MAX98927_R0055_BROWNOUT_LVL_HOLD, 0x00},
108 {MAX98927_R005A_BROWNOUT_LVL1_THRESH, 0x00},
109 {MAX98927_R005B_BROWNOUT_LVL2_THRESH, 0x00},
110 {MAX98927_R005C_BROWNOUT_LVL3_THRESH, 0x00},
111 {MAX98927_R005D_BROWNOUT_LVL4_THRESH, 0x00},
112 {MAX98927_R005E_BROWNOUT_THRESH_HYSTERYSIS, 0x00},
113 {MAX98927_R005F_BROWNOUT_AMP_LIMITER_ATK_REL, 0x00},
114 {MAX98927_R0060_BROWNOUT_AMP_GAIN_ATK_REL, 0x00},
115 {MAX98927_R0061_BROWNOUT_AMP1_CLIP_MODE, 0x00},
116 {MAX98927_R0072_BROWNOUT_LVL1_CUR_LIMIT, 0x00},
117 {MAX98927_R0073_BROWNOUT_LVL1_AMP1_CTRL1, 0x00},
118 {MAX98927_R0074_BROWNOUT_LVL1_AMP1_CTRL2, 0x00},
119 {MAX98927_R0075_BROWNOUT_LVL1_AMP1_CTRL3, 0x00},
120 {MAX98927_R0076_BROWNOUT_LVL2_CUR_LIMIT, 0x00},
121 {MAX98927_R0077_BROWNOUT_LVL2_AMP1_CTRL1, 0x00},
122 {MAX98927_R0078_BROWNOUT_LVL2_AMP1_CTRL2, 0x00},
123 {MAX98927_R0079_BROWNOUT_LVL2_AMP1_CTRL3, 0x00},
124 {MAX98927_R007A_BROWNOUT_LVL3_CUR_LIMIT, 0x00},
125 {MAX98927_R007B_BROWNOUT_LVL3_AMP1_CTRL1, 0x00},
126 {MAX98927_R007C_BROWNOUT_LVL3_AMP1_CTRL2, 0x00},
127 {MAX98927_R007D_BROWNOUT_LVL3_AMP1_CTRL3, 0x00},
128 {MAX98927_R007E_BROWNOUT_LVL4_CUR_LIMIT, 0x00},
129 {MAX98927_R007F_BROWNOUT_LVL4_AMP1_CTRL1, 0x00},
130 {MAX98927_R0080_BROWNOUT_LVL4_AMP1_CTRL2, 0x00},
131 {MAX98927_R0081_BROWNOUT_LVL4_AMP1_CTRL3, 0x00},
132 {MAX98927_R0082_ENV_TRACK_VOUT_HEADROOM, 0x00},
133 {MAX98927_R0083_ENV_TRACK_BOOST_VOUT_DELAY, 0x00},
134 {MAX98927_R0084_ENV_TRACK_REL_RATE, 0x00},
135 {MAX98927_R0085_ENV_TRACK_HOLD_RATE, 0x00},
136 {MAX98927_R0086_ENV_TRACK_CTRL, 0x00},
137 {MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ, 0x00},
138 {MAX98927_R00FF_GLOBAL_SHDN, 0x00},
139 {MAX98927_R0100_SOFT_RESET, 0x00},
140 {MAX98927_R01FF_REV_ID, 0x40},
141};
142
143static int max98927_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
144{
145 struct snd_soc_codec *codec = codec_dai->codec;
146 struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec);
147 unsigned int mode = 0;
148 unsigned int format = 0;
4eee2024 149 bool use_pdm = false;
7c0c2000
RL		 150 unsigned int invert = 0;
151
152 dev_dbg(codec->dev, "%s: fmt 0x%08X\n", __func__, fmt);
153
154 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
155 case SND_SOC_DAIFMT_CBS_CFS:
156 mode = MAX98927_PCM_MASTER_MODE_SLAVE;
157 break;
158 case SND_SOC_DAIFMT_CBM_CFM:
159 max98927->master = true;
160 mode = MAX98927_PCM_MASTER_MODE_MASTER;
161 break;
162 default:
01c6f1b5 163 dev_err(codec->dev, "DAI clock mode unsupported\n");
7c0c2000
RL		 164 return -EINVAL;
165 }
166
167 regmap_update_bits(max98927->regmap,
168 MAX98927_R0021_PCM_MASTER_MODE,
169 MAX98927_PCM_MASTER_MODE_MASK,
170 mode);
171
172 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
173 case SND_SOC_DAIFMT_NB_NF:
174 break;
175 case SND_SOC_DAIFMT_IB_NF:
176 invert = MAX98927_PCM_MODE_CFG_PCM_BCLKEDGE;
177 break;
178 default:
01c6f1b5 179 dev_err(codec->dev, "DAI invert mode unsupported\n");
7c0c2000
RL		 180 return -EINVAL;
181 }
182
183 regmap_update_bits(max98927->regmap,
184 MAX98927_R0020_PCM_MODE_CFG,
185 MAX98927_PCM_MODE_CFG_PCM_BCLKEDGE,
186 invert);
187
188 /* interface format */
189 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
190 case SND_SOC_DAIFMT_I2S:
7c0c2000
RL		 191 format = MAX98927_PCM_FORMAT_I2S;
192 break;
193 case SND_SOC_DAIFMT_LEFT_J:
7c0c2000
RL		 194 format = MAX98927_PCM_FORMAT_LJ;
195 break;
4eee2024
RL		 196 case SND_SOC_DAIFMT_DSP_A:
197 format = MAX98927_PCM_FORMAT_TDM_MODE1;
198 break;
199 case SND_SOC_DAIFMT_DSP_B:
200 format = MAX98927_PCM_FORMAT_TDM_MODE0;
201 break;
7c0c2000 202 case SND_SOC_DAIFMT_PDM:
4eee2024 203 use_pdm = true;
7c0c2000
RL		 204 break;
205 default:
206 return -EINVAL;
207 }
4eee2024 208 max98927->iface = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
7c0c2000 209
4eee2024
RL		 210 if (!use_pdm) {
211 /* pcm channel configuration */
7c0c2000
RL		 212 regmap_update_bits(max98927->regmap,
213 MAX98927_R0018_PCM_RX_EN_A,
214 MAX98927_PCM_RX_CH0_EN | MAX98927_PCM_RX_CH1_EN,
215 MAX98927_PCM_RX_CH0_EN | MAX98927_PCM_RX_CH1_EN);
216
217 regmap_update_bits(max98927->regmap,
218 MAX98927_R0020_PCM_MODE_CFG,
219 MAX98927_PCM_MODE_CFG_FORMAT_MASK,
220 format << MAX98927_PCM_MODE_CFG_FORMAT_SHIFT);
221
222 regmap_update_bits(max98927->regmap,
223 MAX98927_R003B_SPK_SRC_SEL,
224 MAX98927_SPK_SRC_MASK, 0);
225
7c0c2000 226 regmap_update_bits(max98927->regmap,
4eee2024
RL		 227 MAX98927_R0035_PDM_RX_CTRL,
228 MAX98927_PDM_RX_EN_MASK, 0);
229 } else {
230 /* pdm channel configuration */
7c0c2000
RL		 231 regmap_update_bits(max98927->regmap,
232 MAX98927_R0035_PDM_RX_CTRL,
233 MAX98927_PDM_RX_EN_MASK, 1);
234
235 regmap_update_bits(max98927->regmap,
236 MAX98927_R003B_SPK_SRC_SEL,
237 MAX98927_SPK_SRC_MASK, 3);
4eee2024 238
7c0c2000 239 regmap_update_bits(max98927->regmap,
4eee2024
RL		 240 MAX98927_R0018_PCM_RX_EN_A,
241 MAX98927_PCM_RX_CH0_EN | MAX98927_PCM_RX_CH1_EN, 0);
242 }
7c0c2000
RL		 243 return 0;
244}
245
246/* codec MCLK rate in master mode */
247static const int rate_table[] = {
248 5644800, 6000000, 6144000, 6500000,
249 9600000, 11289600, 12000000, 12288000,
250 13000000, 19200000,
251};
252
d4a8bce8
RL		 253/* BCLKs per LRCLK */
254static const int bclk_sel_table[] = {
255 32, 48, 64, 96, 128, 192, 256, 384, 512,
256};
257
258static int max98927_get_bclk_sel(int bclk)
259{
260 int i;
261 /* match BCLKs per LRCLK */
262 for (i = 0; i < ARRAY_SIZE(bclk_sel_table); i++) {
263 if (bclk_sel_table[i] == bclk)
264 return i + 2;
265 }
266 return 0;
267}
7c0c2000
RL		 268static int max98927_set_clock(struct max98927_priv *max98927,
269 struct snd_pcm_hw_params *params)
270{
271 struct snd_soc_codec *codec = max98927->codec;
272 /* BCLK/LRCLK ratio calculation */
273 int blr_clk_ratio = params_channels(params) * max98927->ch_size;
274 int value;
275
276 if (max98927->master) {
277 int i;
278 /* match rate to closest value */
279 for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
280 if (rate_table[i] >= max98927->sysclk)
281 break;
282 }
283 if (i == ARRAY_SIZE(rate_table)) {
284 dev_err(codec->dev, "failed to find proper clock rate.\n");
285 return -EINVAL;
286 }
287 regmap_update_bits(max98927->regmap,
288 MAX98927_R0021_PCM_MASTER_MODE,
289 MAX98927_PCM_MASTER_MODE_MCLK_MASK,
290 i << MAX98927_PCM_MASTER_MODE_MCLK_RATE_SHIFT);
291 }
292
d4a8bce8
RL		 293 if (!max98927->tdm_mode) {
294 /* BCLK configuration */
295 value = max98927_get_bclk_sel(blr_clk_ratio);
296 if (!value) {
297 dev_err(codec->dev, "format unsupported %d\n",
298 params_format(params));
299 return -EINVAL;
300 }
301
302 regmap_update_bits(max98927->regmap,
303 MAX98927_R0022_PCM_CLK_SETUP,
304 MAX98927_PCM_CLK_SETUP_BSEL_MASK,
305 value);
7c0c2000 306 }
7c0c2000
RL		 307 return 0;
308}
309
310static int max98927_dai_hw_params(struct snd_pcm_substream *substream,
311 struct snd_pcm_hw_params *params,
312 struct snd_soc_dai *dai)
313{
314 struct snd_soc_codec *codec = dai->codec;
315 struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec);
316 unsigned int sampling_rate = 0;
317 unsigned int chan_sz = 0;
318
319 /* pcm mode configuration */
320 switch (snd_pcm_format_width(params_format(params))) {
321 case 16:
322 chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_16;
323 break;
324 case 24:
325 chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_24;
326 break;
327 case 32:
328 chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_32;
329 break;
330 default:
01c6f1b5 331 dev_err(codec->dev, "format unsupported %d\n",
7c0c2000
RL		 332 params_format(params));
333 goto err;
334 }
335
336 max98927->ch_size = snd_pcm_format_width(params_format(params));
337
338 regmap_update_bits(max98927->regmap,
339 MAX98927_R0020_PCM_MODE_CFG,
340 MAX98927_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
341
342 dev_dbg(codec->dev, "format supported %d",
343 params_format(params));
344
345 /* sampling rate configuration */
346 switch (params_rate(params)) {
347 case 8000:
348 sampling_rate = MAX98927_PCM_SR_SET1_SR_8000;
349 break;
350 case 11025:
351 sampling_rate = MAX98927_PCM_SR_SET1_SR_11025;
352 break;
353 case 12000:
354 sampling_rate = MAX98927_PCM_SR_SET1_SR_12000;
355 break;
356 case 16000:
357 sampling_rate = MAX98927_PCM_SR_SET1_SR_16000;
358 break;
359 case 22050:
360 sampling_rate = MAX98927_PCM_SR_SET1_SR_22050;
361 break;
362 case 24000:
363 sampling_rate = MAX98927_PCM_SR_SET1_SR_24000;
364 break;
365 case 32000:
366 sampling_rate = MAX98927_PCM_SR_SET1_SR_32000;
367 break;
368 case 44100:
369 sampling_rate = MAX98927_PCM_SR_SET1_SR_44100;
370 break;
371 case 48000:
372 sampling_rate = MAX98927_PCM_SR_SET1_SR_48000;
373 break;
374 default:
375 dev_err(codec->dev, "rate %d not supported\n",
376 params_rate(params));
377 goto err;
378 }
379 /* set DAI_SR to correct LRCLK frequency */
380 regmap_update_bits(max98927->regmap,
381 MAX98927_R0023_PCM_SR_SETUP1,
382 MAX98927_PCM_SR_SET1_SR_MASK,
383 sampling_rate);
384 regmap_update_bits(max98927->regmap,
385 MAX98927_R0024_PCM_SR_SETUP2,
386 MAX98927_PCM_SR_SET2_SR_MASK,
387 sampling_rate << MAX98927_PCM_SR_SET2_SR_SHIFT);
388
389 /* set sampling rate of IV */
390 if (max98927->interleave_mode &&
391 sampling_rate > MAX98927_PCM_SR_SET1_SR_16000)
392 regmap_update_bits(max98927->regmap,
393 MAX98927_R0024_PCM_SR_SETUP2,
394 MAX98927_PCM_SR_SET2_IVADC_SR_MASK,
395 sampling_rate - 3);
396 else
397 regmap_update_bits(max98927->regmap,
398 MAX98927_R0024_PCM_SR_SETUP2,
399 MAX98927_PCM_SR_SET2_IVADC_SR_MASK,
400 sampling_rate);
401 return max98927_set_clock(max98927, params);
402err:
403 return -EINVAL;
404}
405
d4a8bce8
RL		 406static int max98927_dai_tdm_slot(struct snd_soc_dai *dai,
407 unsigned int tx_mask, unsigned int rx_mask,
408 int slots, int slot_width)
409{
410 struct snd_soc_codec *codec = dai->codec;
411 struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec);
412 int bsel = 0;
413 unsigned int chan_sz = 0;
414
415 max98927->tdm_mode = true;
416
417 /* BCLK configuration */
418 bsel = max98927_get_bclk_sel(slots * slot_width);
419 if (bsel == 0) {
420 dev_err(codec->dev, "BCLK %d not supported\n",
421 slots * slot_width);
422 return -EINVAL;
423 }
424
425 regmap_update_bits(max98927->regmap,
426 MAX98927_R0022_PCM_CLK_SETUP,
427 MAX98927_PCM_CLK_SETUP_BSEL_MASK,
428 bsel);
429
430 /* Channel size configuration */
431 switch (slot_width) {
432 case 16:
433 chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_16;
434 break;
435 case 24:
436 chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_24;
437 break;
438 case 32:
439 chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_32;
440 break;
441 default:
442 dev_err(codec->dev, "format unsupported %d\n",
443 slot_width);
444 return -EINVAL;
445 }
446
447 regmap_update_bits(max98927->regmap,
448 MAX98927_R0020_PCM_MODE_CFG,
449 MAX98927_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
450
451 /* Rx slot configuration */
452 regmap_write(max98927->regmap,
453 MAX98927_R0018_PCM_RX_EN_A,
454 rx_mask & 0xFF);
455 regmap_write(max98927->regmap,
456 MAX98927_R0019_PCM_RX_EN_B,
457 (rx_mask & 0xFF00) >> 8);
458
459 /* Tx slot configuration */
460 regmap_write(max98927->regmap,
461 MAX98927_R001A_PCM_TX_EN_A,
462 tx_mask & 0xFF);
463 regmap_write(max98927->regmap,
464 MAX98927_R001B_PCM_TX_EN_B,
465 (tx_mask & 0xFF00) >> 8);
466
467 /* Tx slot Hi-Z configuration */
468 regmap_write(max98927->regmap,
469 MAX98927_R001C_PCM_TX_HIZ_CTRL_A,
470 ~tx_mask & 0xFF);
471 regmap_write(max98927->regmap,
472 MAX98927_R001D_PCM_TX_HIZ_CTRL_B,
473 (~tx_mask & 0xFF00) >> 8);
474
475 return 0;
476}
477
7c0c2000
RL		 478#define MAX98927_RATES SNDRV_PCM_RATE_8000_48000
479
480#define MAX98927_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
481 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
482
483static int max98927_dai_set_sysclk(struct snd_soc_dai *dai,
484 int clk_id, unsigned int freq, int dir)
485{
486 struct snd_soc_codec *codec = dai->codec;
487 struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec);
488
489 max98927->sysclk = freq;
490 return 0;
491}
492
493static const struct snd_soc_dai_ops max98927_dai_ops = {
494 .set_sysclk = max98927_dai_set_sysclk,
495 .set_fmt = max98927_dai_set_fmt,
496 .hw_params = max98927_dai_hw_params,
d4a8bce8 497 .set_tdm_slot = max98927_dai_tdm_slot,
7c0c2000
RL		 498};
499
500static int max98927_dac_event(struct snd_soc_dapm_widget *w,
501 struct snd_kcontrol *kcontrol, int event)
502{
503 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
504 struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec);
505
506 switch (event) {
d4a8bce8
RL		 507 case SND_SOC_DAPM_PRE_PMU:
508 max98927->tdm_mode = 0;
509 break;
7c0c2000
RL		 510 case SND_SOC_DAPM_POST_PMU:
511 regmap_update_bits(max98927->regmap,
512 MAX98927_R003A_AMP_EN,
513 MAX98927_AMP_EN_MASK, 1);
7c0c2000
RL		 514 regmap_update_bits(max98927->regmap,
515 MAX98927_R00FF_GLOBAL_SHDN,
516 MAX98927_GLOBAL_EN_MASK, 1);
517 break;
518 case SND_SOC_DAPM_POST_PMD:
519 regmap_update_bits(max98927->regmap,
520 MAX98927_R00FF_GLOBAL_SHDN,
521 MAX98927_GLOBAL_EN_MASK, 0);
522 regmap_update_bits(max98927->regmap,
523 MAX98927_R003A_AMP_EN,
524 MAX98927_AMP_EN_MASK, 0);
7c0c2000
RL		 525 break;
526 default:
527 return 0;
528 }
529 return 0;
530}
531
532static const char * const max98927_switch_text[] = {
533 "Left", "Right", "LeftRight"};
534
535static const struct soc_enum dai_sel_enum =
536 SOC_ENUM_SINGLE(MAX98927_R0025_PCM_TO_SPK_MONOMIX_A,
537 MAX98927_PCM_TO_SPK_MONOMIX_CFG_SHIFT,
538 3, max98927_switch_text);
539
540static const struct snd_kcontrol_new max98927_dai_controls =
541 SOC_DAPM_ENUM("DAI Sel", dai_sel_enum);
542
607f7777
RL		 543static const struct snd_kcontrol_new max98927_vi_control =
544 SOC_DAPM_SINGLE("Switch", MAX98927_R003F_MEAS_DSP_CFG, 2, 1, 0);
545
7c0c2000 546static const struct snd_soc_dapm_widget max98927_dapm_widgets[] = {
7c0c2000
RL		 547 SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback", MAX98927_R003A_AMP_EN,
548 0, 0, max98927_dac_event,
549 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
550 SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0,
551 &max98927_dai_controls),
552 SND_SOC_DAPM_OUTPUT("BE_OUT"),
607f7777
RL		 553 SND_SOC_DAPM_AIF_OUT("Voltage Sense", "HiFi Capture", 0,
554 MAX98927_R003E_MEAS_EN, 0, 0),
555 SND_SOC_DAPM_AIF_OUT("Current Sense", "HiFi Capture", 0,
556 MAX98927_R003E_MEAS_EN, 1, 0),
557 SND_SOC_DAPM_SWITCH("VI Sense", SND_SOC_NOPM, 0, 0,
558 &max98927_vi_control),
559 SND_SOC_DAPM_SIGGEN("VMON"),
560 SND_SOC_DAPM_SIGGEN("IMON"),
7c0c2000
RL		 561};
562
563static DECLARE_TLV_DB_SCALE(max98927_spk_tlv, 300, 300, 0);
564static DECLARE_TLV_DB_SCALE(max98927_digital_tlv, -1600, 25, 0);
565
566static bool max98927_readable_register(struct device *dev, unsigned int reg)
567{
568 switch (reg) {
569 case MAX98927_R0001_INT_RAW1 ... MAX98927_R0028_ICC_RX_EN_B:
570 case MAX98927_R002B_ICC_TX_EN_A ... MAX98927_R002C_ICC_TX_EN_B:
571 case MAX98927_R002E_ICC_HIZ_MANUAL_MODE
572 ... MAX98927_R004E_MEAS_ADC_CH2_READ:
573 case MAX98927_R0051_BROWNOUT_STATUS
574 ... MAX98927_R0055_BROWNOUT_LVL_HOLD:
575 case MAX98927_R005A_BROWNOUT_LVL1_THRESH
576 ... MAX98927_R0061_BROWNOUT_AMP1_CLIP_MODE:
577 case MAX98927_R0072_BROWNOUT_LVL1_CUR_LIMIT
578 ... MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ:
579 case MAX98927_R00FF_GLOBAL_SHDN:
580 case MAX98927_R0100_SOFT_RESET:
581 case MAX98927_R01FF_REV_ID:
582 return true;
583 default:
584 return false;
585 }
586};
587
588static bool max98927_volatile_reg(struct device *dev, unsigned int reg)
589{
590 switch (reg) {
591 case MAX98927_R0001_INT_RAW1 ... MAX98927_R0009_INT_FLAG3:
9c1743eb
RL		 592 case MAX98927_R004C_MEAS_ADC_CH0_READ:
593 case MAX98927_R004D_MEAS_ADC_CH1_READ:
594 case MAX98927_R004E_MEAS_ADC_CH2_READ:
595 case MAX98927_R0051_BROWNOUT_STATUS:
596 case MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ:
597 case MAX98927_R01FF_REV_ID:
598 case MAX98927_R0100_SOFT_RESET:
7c0c2000
RL		 599 return true;
600 default:
601 return false;
602 }
603}
604
605static const char * const max98927_boost_voltage_text[] = {
606 "6.5V", "6.625V", "6.75V", "6.875V", "7V", "7.125V", "7.25V", "7.375V",
607 "7.5V", "7.625V", "7.75V", "7.875V", "8V", "8.125V", "8.25V", "8.375V",
608 "8.5V", "8.625V", "8.75V", "8.875V", "9V", "9.125V", "9.25V", "9.375V",
609 "9.5V", "9.625V", "9.75V", "9.875V", "10V"
610};
611
612static SOC_ENUM_SINGLE_DECL(max98927_boost_voltage,
613 MAX98927_R0040_BOOST_CTRL0, 0,
614 max98927_boost_voltage_text);
615
616static const char * const max98927_current_limit_text[] = {
617 "1.00A", "1.10A", "1.20A", "1.30A", "1.40A", "1.50A", "1.60A", "1.70A",
618 "1.80A", "1.90A", "2.00A", "2.10A", "2.20A", "2.30A", "2.40A", "2.50A",
619 "2.60A", "2.70A", "2.80A", "2.90A", "3.00A", "3.10A", "3.20A", "3.30A",
620 "3.40A", "3.50A", "3.60A", "3.70A", "3.80A", "3.90A", "4.00A", "4.10A"
621};
622
623static SOC_ENUM_SINGLE_DECL(max98927_current_limit,
624 MAX98927_R0042_BOOST_CTRL1, 1,
625 max98927_current_limit_text);
626
627static const struct snd_kcontrol_new max98927_snd_controls[] = {
628 SOC_SINGLE_TLV("Speaker Volume", MAX98927_R003C_SPK_GAIN,
629 0, 6, 0,
630 max98927_spk_tlv),
631 SOC_SINGLE_TLV("Digital Volume", MAX98927_R0036_AMP_VOL_CTRL,
632 0, (1<<MAX98927_AMP_VOL_WIDTH)-1, 0,
633 max98927_digital_tlv),
634 SOC_SINGLE("Amp DSP Switch", MAX98927_R0052_BROWNOUT_EN,
635 MAX98927_BROWNOUT_DSP_SHIFT, 1, 0),
636 SOC_SINGLE("Ramp Switch", MAX98927_R0037_AMP_DSP_CFG,
637 MAX98927_AMP_DSP_CFG_RMP_SHIFT, 1, 0),
638 SOC_SINGLE("DRE Switch", MAX98927_R0039_DRE_CTRL,
639 MAX98927_DRE_EN_SHIFT, 1, 0),
640 SOC_SINGLE("Volume Location Switch", MAX98927_R0036_AMP_VOL_CTRL,
641 MAX98927_AMP_VOL_SEL_SHIFT, 1, 0),
642 SOC_ENUM("Boost Output Voltage", max98927_boost_voltage),
643 SOC_ENUM("Current Limit", max98927_current_limit),
644};
645
646static const struct snd_soc_dapm_route max98927_audio_map[] = {
607f7777 647 /* Plabyack */
7c0c2000
RL		 648 {"DAI Sel Mux", "Left", "Amp Enable"},
649 {"DAI Sel Mux", "Right", "Amp Enable"},
650 {"DAI Sel Mux", "LeftRight", "Amp Enable"},
651 {"BE_OUT", NULL, "DAI Sel Mux"},
607f7777
RL		 652 /* Capture */
653 { "VI Sense", "Switch", "VMON" },
654 { "VI Sense", "Switch", "IMON" },
655 { "Voltage Sense", NULL, "VI Sense" },
656 { "Current Sense", NULL, "VI Sense" },
7c0c2000
RL		 657};
658
659static struct snd_soc_dai_driver max98927_dai[] = {
660 {
661 .name = "max98927-aif1",
662 .playback = {
663 .stream_name = "HiFi Playback",
664 .channels_min = 1,
665 .channels_max = 2,
666 .rates = MAX98927_RATES,
667 .formats = MAX98927_FORMATS,
668 },
669 .capture = {
670 .stream_name = "HiFi Capture",
671 .channels_min = 1,
672 .channels_max = 2,
673 .rates = MAX98927_RATES,
674 .formats = MAX98927_FORMATS,
675 },
676 .ops = &max98927_dai_ops,
677 }
678};
679
680static int max98927_probe(struct snd_soc_codec *codec)
681{
682 struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec);
683
684 max98927->codec = codec;
685 codec->control_data = max98927->regmap;
7c0c2000
RL		 686
687 /* Software Reset */
688 regmap_write(max98927->regmap,
689 MAX98927_R0100_SOFT_RESET, MAX98927_SOFT_RESET);
690
691 /* IV default slot configuration */
692 regmap_write(max98927->regmap,
693 MAX98927_R001C_PCM_TX_HIZ_CTRL_A,
694 0xFF);
695 regmap_write(max98927->regmap,
696 MAX98927_R001D_PCM_TX_HIZ_CTRL_B,
697 0xFF);
698 regmap_write(max98927->regmap,
699 MAX98927_R0025_PCM_TO_SPK_MONOMIX_A,
700 0x80);
701 regmap_write(max98927->regmap,
702 MAX98927_R0026_PCM_TO_SPK_MONOMIX_B,
703 0x1);
704 /* Set inital volume (+13dB) */
705 regmap_write(max98927->regmap,
706 MAX98927_R0036_AMP_VOL_CTRL,
707 0x38);
708 regmap_write(max98927->regmap,
709 MAX98927_R003C_SPK_GAIN,
710 0x05);
711 /* Enable DC blocker */
712 regmap_write(max98927->regmap,
713 MAX98927_R0037_AMP_DSP_CFG,
714 0x03);
715 /* Enable IMON VMON DC blocker */
716 regmap_write(max98927->regmap,
717 MAX98927_R003F_MEAS_DSP_CFG,
718 0xF7);
719 /* Boost Output Voltage & Current limit */
720 regmap_write(max98927->regmap,
721 MAX98927_R0040_BOOST_CTRL0,
722 0x1C);
723 regmap_write(max98927->regmap,
724 MAX98927_R0042_BOOST_CTRL1,
725 0x3E);
726 /* Measurement ADC config */
727 regmap_write(max98927->regmap,
728 MAX98927_R0043_MEAS_ADC_CFG,
729 0x04);
730 regmap_write(max98927->regmap,
731 MAX98927_R0044_MEAS_ADC_BASE_MSB,
732 0x00);
733 regmap_write(max98927->regmap,
734 MAX98927_R0045_MEAS_ADC_BASE_LSB,
735 0x24);
736 /* Brownout Level */
737 regmap_write(max98927->regmap,
738 MAX98927_R007F_BROWNOUT_LVL4_AMP1_CTRL1,
739 0x06);
740 /* Envelope Tracking configuration */
741 regmap_write(max98927->regmap,
742 MAX98927_R0082_ENV_TRACK_VOUT_HEADROOM,
743 0x08);
744 regmap_write(max98927->regmap,
745 MAX98927_R0086_ENV_TRACK_CTRL,
746 0x01);
747 regmap_write(max98927->regmap,
748 MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ,
749 0x10);
750
751 /* voltage, current slot configuration */
752 regmap_write(max98927->regmap,
753 MAX98927_R001E_PCM_TX_CH_SRC_A,
754 (max98927->i_l_slot<<MAX98927_PCM_TX_CH_SRC_A_I_SHIFT|
755 max98927->v_l_slot)&0xFF);
756
757 if (max98927->v_l_slot < 8) {
758 regmap_update_bits(max98927->regmap,
759 MAX98927_R001C_PCM_TX_HIZ_CTRL_A,
760 1 << max98927->v_l_slot, 0);
761 regmap_update_bits(max98927->regmap,
762 MAX98927_R001A_PCM_TX_EN_A,
763 1 << max98927->v_l_slot,
764 1 << max98927->v_l_slot);
765 } else {
766 regmap_update_bits(max98927->regmap,
767 MAX98927_R001D_PCM_TX_HIZ_CTRL_B,
768 1 << (max98927->v_l_slot - 8), 0);
769 regmap_update_bits(max98927->regmap,
770 MAX98927_R001B_PCM_TX_EN_B,
771 1 << (max98927->v_l_slot - 8),
772 1 << (max98927->v_l_slot - 8));
773 }
774
775 if (max98927->i_l_slot < 8) {
776 regmap_update_bits(max98927->regmap,
777 MAX98927_R001C_PCM_TX_HIZ_CTRL_A,
778 1 << max98927->i_l_slot, 0);
779 regmap_update_bits(max98927->regmap,
780 MAX98927_R001A_PCM_TX_EN_A,
781 1 << max98927->i_l_slot,
782 1 << max98927->i_l_slot);
783 } else {
784 regmap_update_bits(max98927->regmap,
785 MAX98927_R001D_PCM_TX_HIZ_CTRL_B,
786 1 << (max98927->i_l_slot - 8), 0);
787 regmap_update_bits(max98927->regmap,
788 MAX98927_R001B_PCM_TX_EN_B,
789 1 << (max98927->i_l_slot - 8),
790 1 << (max98927->i_l_slot - 8));
791 }
792
793 /* Set interleave mode */
794 if (max98927->interleave_mode)
795 regmap_update_bits(max98927->regmap,
796 MAX98927_R001F_PCM_TX_CH_SRC_B,
797 MAX98927_PCM_TX_CH_INTERLEAVE_MASK,
798 MAX98927_PCM_TX_CH_INTERLEAVE_MASK);
799 return 0;
800}
801
f81991dd
RL		 802#ifdef CONFIG_PM_SLEEP
803static int max98927_suspend(struct device *dev)
804{
805 struct max98927_priv *max98927 = dev_get_drvdata(dev);
806
807 regcache_cache_only(max98927->regmap, true);
808 regcache_mark_dirty(max98927->regmap);
809 return 0;
810}
811static int max98927_resume(struct device *dev)
812{
813 struct max98927_priv *max98927 = dev_get_drvdata(dev);
814
815 regmap_write(max98927->regmap,
816 MAX98927_R0100_SOFT_RESET, MAX98927_SOFT_RESET);
817 regcache_cache_only(max98927->regmap, false);
818 regcache_sync(max98927->regmap);
819 return 0;
820}
821#endif
822
823static const struct dev_pm_ops max98927_pm = {
824 SET_SYSTEM_SLEEP_PM_OPS(max98927_suspend, max98927_resume)
825};
826
7c0c2000
RL		 827static const struct snd_soc_codec_driver soc_codec_dev_max98927 = {
828 .probe = max98927_probe,
829 .component_driver = {
830 .controls = max98927_snd_controls,
831 .num_controls = ARRAY_SIZE(max98927_snd_controls),
832 .dapm_widgets = max98927_dapm_widgets,
833 .num_dapm_widgets = ARRAY_SIZE(max98927_dapm_widgets),
834 .dapm_routes = max98927_audio_map,
835 .num_dapm_routes = ARRAY_SIZE(max98927_audio_map),
836 },
837};
838
839static const struct regmap_config max98927_regmap = {
840 .reg_bits = 16,
841 .val_bits = 8,
842 .max_register = MAX98927_R01FF_REV_ID,
843 .reg_defaults = max98927_reg,
844 .num_reg_defaults = ARRAY_SIZE(max98927_reg),
845 .readable_reg = max98927_readable_register,
846 .volatile_reg = max98927_volatile_reg,
847 .cache_type = REGCACHE_RBTREE,
848};
849
850static void max98927_slot_config(struct i2c_client *i2c,
851 struct max98927_priv *max98927)
852{
853 int value;
dea11050 854 struct device *dev = &i2c->dev;
7c0c2000 855
dea11050 856 if (!device_property_read_u32(dev, "vmon-slot-no", &value))
7c0c2000
RL		 857 max98927->v_l_slot = value & 0xF;
858 else
859 max98927->v_l_slot = 0;
dea11050
RL		 860
861 if (!device_property_read_u32(dev, "imon-slot-no", &value))
7c0c2000
RL		 862 max98927->i_l_slot = value & 0xF;
863 else
864 max98927->i_l_slot = 1;
865}
866
867static int max98927_i2c_probe(struct i2c_client *i2c,
868 const struct i2c_device_id *id)
869{
870
871 int ret = 0, value;
872 int reg = 0;
873 struct max98927_priv *max98927 = NULL;
874
875 max98927 = devm_kzalloc(&i2c->dev,
876 sizeof(*max98927), GFP_KERNEL);
877
878 if (!max98927) {
879 ret = -ENOMEM;
880 return ret;
881 }
882 i2c_set_clientdata(i2c, max98927);
883
884 /* update interleave mode info */
885 if (!of_property_read_u32(i2c->dev.of_node,
886 "interleave_mode", &value)) {
887 if (value > 0)
888 max98927->interleave_mode = 1;
889 else
890 max98927->interleave_mode = 0;
891 } else
892 max98927->interleave_mode = 0;
893
894 /* regmap initialization */
895 max98927->regmap
896 = devm_regmap_init_i2c(i2c, &max98927_regmap);
897 if (IS_ERR(max98927->regmap)) {
898 ret = PTR_ERR(max98927->regmap);
899 dev_err(&i2c->dev,
900 "Failed to allocate regmap: %d\n", ret);
901 return ret;
902 }
903
904 /* Check Revision ID */
905 ret = regmap_read(max98927->regmap,
906 MAX98927_R01FF_REV_ID, &reg);
907 if (ret < 0) {
908 dev_err(&i2c->dev,
909 "Failed to read: 0x%02X\n", MAX98927_R01FF_REV_ID);
910 return ret;
911 }
912 dev_info(&i2c->dev, "MAX98927 revisionID: 0x%02X\n", reg);
913
914 /* voltage/current slot configuration */
915 max98927_slot_config(i2c, max98927);
916
917 /* codec registeration */
918 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_max98927,
919 max98927_dai, ARRAY_SIZE(max98927_dai));
920 if (ret < 0)
921 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
922
923 return ret;
924}
925
926static int max98927_i2c_remove(struct i2c_client *client)
927{
928 snd_soc_unregister_codec(&client->dev);
929 return 0;
930}
931
932static const struct i2c_device_id max98927_i2c_id[] = {
933 { "max98927", 0},
934 { },
935};
936
937MODULE_DEVICE_TABLE(i2c, max98927_i2c_id);
938
939#if defined(CONFIG_OF)
940static const struct of_device_id max98927_of_match[] = {
941 { .compatible = "maxim,max98927", },
942 { }
943};
944MODULE_DEVICE_TABLE(of, max98927_of_match);
945#endif
946
947#ifdef CONFIG_ACPI
948static const struct acpi_device_id max98927_acpi_match[] = {
949 { "MX98927", 0 },
950 {},
951};
952MODULE_DEVICE_TABLE(acpi, max98927_acpi_match);
953#endif
954
955static struct i2c_driver max98927_i2c_driver = {
956 .driver = {
957 .name = "max98927",
958 .of_match_table = of_match_ptr(max98927_of_match),
959 .acpi_match_table = ACPI_PTR(max98927_acpi_match),
f81991dd 960 .pm = &max98927_pm,
7c0c2000
RL		 961 },
962 .probe = max98927_i2c_probe,
963 .remove = max98927_i2c_remove,
964 .id_table = max98927_i2c_id,
965};
966
967module_i2c_driver(max98927_i2c_driver)
968
969MODULE_DESCRIPTION("ALSA SoC MAX98927 driver");
970MODULE_AUTHOR("Ryan Lee <ryans.lee@maximintegrated.com>");
971MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)