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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
685e4215 JW |
2 | /* |
3 | * max98090.c -- MAX98090 ALSA SoC Audio driver | |
4 | * | |
5 | * Copyright 2011-2012 Maxim Integrated Products | |
685e4215 JW |
6 | */ |
7 | ||
8 | #include <linux/delay.h> | |
9 | #include <linux/i2c.h> | |
10 | #include <linux/module.h> | |
6e1f29d4 | 11 | #include <linux/of.h> |
685e4215 | 12 | #include <linux/pm.h> |
685e4215 JW |
13 | #include <linux/regmap.h> |
14 | #include <linux/slab.h> | |
4b8a1ca4 TBS |
15 | #include <linux/acpi.h> |
16 | #include <linux/clk.h> | |
685e4215 JW |
17 | #include <sound/jack.h> |
18 | #include <sound/pcm.h> | |
19 | #include <sound/pcm_params.h> | |
20 | #include <sound/soc.h> | |
21 | #include <sound/tlv.h> | |
4b8a1ca4 | 22 | #include <sound/max98090.h> |
685e4215 JW |
23 | #include "max98090.h" |
24 | ||
685e4215 | 25 | /* Allows for sparsely populated register maps */ |
8610d09a | 26 | static const struct reg_default max98090_reg[] = { |
685e4215 JW |
27 | { 0x00, 0x00 }, /* 00 Software Reset */ |
28 | { 0x03, 0x04 }, /* 03 Interrupt Masks */ | |
29 | { 0x04, 0x00 }, /* 04 System Clock Quick */ | |
30 | { 0x05, 0x00 }, /* 05 Sample Rate Quick */ | |
31 | { 0x06, 0x00 }, /* 06 DAI Interface Quick */ | |
32 | { 0x07, 0x00 }, /* 07 DAC Path Quick */ | |
33 | { 0x08, 0x00 }, /* 08 Mic/Direct to ADC Quick */ | |
34 | { 0x09, 0x00 }, /* 09 Line to ADC Quick */ | |
35 | { 0x0A, 0x00 }, /* 0A Analog Mic Loop Quick */ | |
36 | { 0x0B, 0x00 }, /* 0B Analog Line Loop Quick */ | |
37 | { 0x0C, 0x00 }, /* 0C Reserved */ | |
38 | { 0x0D, 0x00 }, /* 0D Input Config */ | |
39 | { 0x0E, 0x1B }, /* 0E Line Input Level */ | |
40 | { 0x0F, 0x00 }, /* 0F Line Config */ | |
41 | ||
42 | { 0x10, 0x14 }, /* 10 Mic1 Input Level */ | |
43 | { 0x11, 0x14 }, /* 11 Mic2 Input Level */ | |
44 | { 0x12, 0x00 }, /* 12 Mic Bias Voltage */ | |
45 | { 0x13, 0x00 }, /* 13 Digital Mic Config */ | |
46 | { 0x14, 0x00 }, /* 14 Digital Mic Mode */ | |
47 | { 0x15, 0x00 }, /* 15 Left ADC Mixer */ | |
48 | { 0x16, 0x00 }, /* 16 Right ADC Mixer */ | |
49 | { 0x17, 0x03 }, /* 17 Left ADC Level */ | |
50 | { 0x18, 0x03 }, /* 18 Right ADC Level */ | |
51 | { 0x19, 0x00 }, /* 19 ADC Biquad Level */ | |
52 | { 0x1A, 0x00 }, /* 1A ADC Sidetone */ | |
53 | { 0x1B, 0x00 }, /* 1B System Clock */ | |
54 | { 0x1C, 0x00 }, /* 1C Clock Mode */ | |
55 | { 0x1D, 0x00 }, /* 1D Any Clock 1 */ | |
56 | { 0x1E, 0x00 }, /* 1E Any Clock 2 */ | |
57 | { 0x1F, 0x00 }, /* 1F Any Clock 3 */ | |
58 | ||
59 | { 0x20, 0x00 }, /* 20 Any Clock 4 */ | |
60 | { 0x21, 0x00 }, /* 21 Master Mode */ | |
61 | { 0x22, 0x00 }, /* 22 Interface Format */ | |
62 | { 0x23, 0x00 }, /* 23 TDM Format 1*/ | |
63 | { 0x24, 0x00 }, /* 24 TDM Format 2*/ | |
64 | { 0x25, 0x00 }, /* 25 I/O Configuration */ | |
65 | { 0x26, 0x80 }, /* 26 Filter Config */ | |
66 | { 0x27, 0x00 }, /* 27 DAI Playback Level */ | |
67 | { 0x28, 0x00 }, /* 28 EQ Playback Level */ | |
68 | { 0x29, 0x00 }, /* 29 Left HP Mixer */ | |
69 | { 0x2A, 0x00 }, /* 2A Right HP Mixer */ | |
70 | { 0x2B, 0x00 }, /* 2B HP Control */ | |
71 | { 0x2C, 0x1A }, /* 2C Left HP Volume */ | |
72 | { 0x2D, 0x1A }, /* 2D Right HP Volume */ | |
73 | { 0x2E, 0x00 }, /* 2E Left Spk Mixer */ | |
74 | { 0x2F, 0x00 }, /* 2F Right Spk Mixer */ | |
75 | ||
76 | { 0x30, 0x00 }, /* 30 Spk Control */ | |
77 | { 0x31, 0x2C }, /* 31 Left Spk Volume */ | |
78 | { 0x32, 0x2C }, /* 32 Right Spk Volume */ | |
79 | { 0x33, 0x00 }, /* 33 ALC Timing */ | |
80 | { 0x34, 0x00 }, /* 34 ALC Compressor */ | |
81 | { 0x35, 0x00 }, /* 35 ALC Expander */ | |
82 | { 0x36, 0x00 }, /* 36 ALC Gain */ | |
83 | { 0x37, 0x00 }, /* 37 Rcv/Line OutL Mixer */ | |
84 | { 0x38, 0x00 }, /* 38 Rcv/Line OutL Control */ | |
85 | { 0x39, 0x15 }, /* 39 Rcv/Line OutL Volume */ | |
86 | { 0x3A, 0x00 }, /* 3A Line OutR Mixer */ | |
87 | { 0x3B, 0x00 }, /* 3B Line OutR Control */ | |
88 | { 0x3C, 0x15 }, /* 3C Line OutR Volume */ | |
89 | { 0x3D, 0x00 }, /* 3D Jack Detect */ | |
90 | { 0x3E, 0x00 }, /* 3E Input Enable */ | |
91 | { 0x3F, 0x00 }, /* 3F Output Enable */ | |
92 | ||
93 | { 0x40, 0x00 }, /* 40 Level Control */ | |
94 | { 0x41, 0x00 }, /* 41 DSP Filter Enable */ | |
95 | { 0x42, 0x00 }, /* 42 Bias Control */ | |
96 | { 0x43, 0x00 }, /* 43 DAC Control */ | |
97 | { 0x44, 0x06 }, /* 44 ADC Control */ | |
98 | { 0x45, 0x00 }, /* 45 Device Shutdown */ | |
99 | { 0x46, 0x00 }, /* 46 Equalizer Band 1 Coefficient B0 */ | |
100 | { 0x47, 0x00 }, /* 47 Equalizer Band 1 Coefficient B0 */ | |
101 | { 0x48, 0x00 }, /* 48 Equalizer Band 1 Coefficient B0 */ | |
102 | { 0x49, 0x00 }, /* 49 Equalizer Band 1 Coefficient B1 */ | |
103 | { 0x4A, 0x00 }, /* 4A Equalizer Band 1 Coefficient B1 */ | |
104 | { 0x4B, 0x00 }, /* 4B Equalizer Band 1 Coefficient B1 */ | |
105 | { 0x4C, 0x00 }, /* 4C Equalizer Band 1 Coefficient B2 */ | |
106 | { 0x4D, 0x00 }, /* 4D Equalizer Band 1 Coefficient B2 */ | |
107 | { 0x4E, 0x00 }, /* 4E Equalizer Band 1 Coefficient B2 */ | |
108 | { 0x4F, 0x00 }, /* 4F Equalizer Band 1 Coefficient A1 */ | |
109 | ||
110 | { 0x50, 0x00 }, /* 50 Equalizer Band 1 Coefficient A1 */ | |
111 | { 0x51, 0x00 }, /* 51 Equalizer Band 1 Coefficient A1 */ | |
112 | { 0x52, 0x00 }, /* 52 Equalizer Band 1 Coefficient A2 */ | |
113 | { 0x53, 0x00 }, /* 53 Equalizer Band 1 Coefficient A2 */ | |
114 | { 0x54, 0x00 }, /* 54 Equalizer Band 1 Coefficient A2 */ | |
115 | { 0x55, 0x00 }, /* 55 Equalizer Band 2 Coefficient B0 */ | |
116 | { 0x56, 0x00 }, /* 56 Equalizer Band 2 Coefficient B0 */ | |
117 | { 0x57, 0x00 }, /* 57 Equalizer Band 2 Coefficient B0 */ | |
118 | { 0x58, 0x00 }, /* 58 Equalizer Band 2 Coefficient B1 */ | |
119 | { 0x59, 0x00 }, /* 59 Equalizer Band 2 Coefficient B1 */ | |
120 | { 0x5A, 0x00 }, /* 5A Equalizer Band 2 Coefficient B1 */ | |
121 | { 0x5B, 0x00 }, /* 5B Equalizer Band 2 Coefficient B2 */ | |
122 | { 0x5C, 0x00 }, /* 5C Equalizer Band 2 Coefficient B2 */ | |
123 | { 0x5D, 0x00 }, /* 5D Equalizer Band 2 Coefficient B2 */ | |
124 | { 0x5E, 0x00 }, /* 5E Equalizer Band 2 Coefficient A1 */ | |
125 | { 0x5F, 0x00 }, /* 5F Equalizer Band 2 Coefficient A1 */ | |
126 | ||
127 | { 0x60, 0x00 }, /* 60 Equalizer Band 2 Coefficient A1 */ | |
128 | { 0x61, 0x00 }, /* 61 Equalizer Band 2 Coefficient A2 */ | |
129 | { 0x62, 0x00 }, /* 62 Equalizer Band 2 Coefficient A2 */ | |
130 | { 0x63, 0x00 }, /* 63 Equalizer Band 2 Coefficient A2 */ | |
131 | { 0x64, 0x00 }, /* 64 Equalizer Band 3 Coefficient B0 */ | |
132 | { 0x65, 0x00 }, /* 65 Equalizer Band 3 Coefficient B0 */ | |
133 | { 0x66, 0x00 }, /* 66 Equalizer Band 3 Coefficient B0 */ | |
134 | { 0x67, 0x00 }, /* 67 Equalizer Band 3 Coefficient B1 */ | |
135 | { 0x68, 0x00 }, /* 68 Equalizer Band 3 Coefficient B1 */ | |
136 | { 0x69, 0x00 }, /* 69 Equalizer Band 3 Coefficient B1 */ | |
137 | { 0x6A, 0x00 }, /* 6A Equalizer Band 3 Coefficient B2 */ | |
138 | { 0x6B, 0x00 }, /* 6B Equalizer Band 3 Coefficient B2 */ | |
139 | { 0x6C, 0x00 }, /* 6C Equalizer Band 3 Coefficient B2 */ | |
140 | { 0x6D, 0x00 }, /* 6D Equalizer Band 3 Coefficient A1 */ | |
141 | { 0x6E, 0x00 }, /* 6E Equalizer Band 3 Coefficient A1 */ | |
142 | { 0x6F, 0x00 }, /* 6F Equalizer Band 3 Coefficient A1 */ | |
143 | ||
144 | { 0x70, 0x00 }, /* 70 Equalizer Band 3 Coefficient A2 */ | |
145 | { 0x71, 0x00 }, /* 71 Equalizer Band 3 Coefficient A2 */ | |
146 | { 0x72, 0x00 }, /* 72 Equalizer Band 3 Coefficient A2 */ | |
147 | { 0x73, 0x00 }, /* 73 Equalizer Band 4 Coefficient B0 */ | |
148 | { 0x74, 0x00 }, /* 74 Equalizer Band 4 Coefficient B0 */ | |
149 | { 0x75, 0x00 }, /* 75 Equalizer Band 4 Coefficient B0 */ | |
150 | { 0x76, 0x00 }, /* 76 Equalizer Band 4 Coefficient B1 */ | |
151 | { 0x77, 0x00 }, /* 77 Equalizer Band 4 Coefficient B1 */ | |
152 | { 0x78, 0x00 }, /* 78 Equalizer Band 4 Coefficient B1 */ | |
153 | { 0x79, 0x00 }, /* 79 Equalizer Band 4 Coefficient B2 */ | |
154 | { 0x7A, 0x00 }, /* 7A Equalizer Band 4 Coefficient B2 */ | |
155 | { 0x7B, 0x00 }, /* 7B Equalizer Band 4 Coefficient B2 */ | |
156 | { 0x7C, 0x00 }, /* 7C Equalizer Band 4 Coefficient A1 */ | |
157 | { 0x7D, 0x00 }, /* 7D Equalizer Band 4 Coefficient A1 */ | |
158 | { 0x7E, 0x00 }, /* 7E Equalizer Band 4 Coefficient A1 */ | |
159 | { 0x7F, 0x00 }, /* 7F Equalizer Band 4 Coefficient A2 */ | |
160 | ||
161 | { 0x80, 0x00 }, /* 80 Equalizer Band 4 Coefficient A2 */ | |
162 | { 0x81, 0x00 }, /* 81 Equalizer Band 4 Coefficient A2 */ | |
163 | { 0x82, 0x00 }, /* 82 Equalizer Band 5 Coefficient B0 */ | |
164 | { 0x83, 0x00 }, /* 83 Equalizer Band 5 Coefficient B0 */ | |
165 | { 0x84, 0x00 }, /* 84 Equalizer Band 5 Coefficient B0 */ | |
166 | { 0x85, 0x00 }, /* 85 Equalizer Band 5 Coefficient B1 */ | |
167 | { 0x86, 0x00 }, /* 86 Equalizer Band 5 Coefficient B1 */ | |
168 | { 0x87, 0x00 }, /* 87 Equalizer Band 5 Coefficient B1 */ | |
169 | { 0x88, 0x00 }, /* 88 Equalizer Band 5 Coefficient B2 */ | |
170 | { 0x89, 0x00 }, /* 89 Equalizer Band 5 Coefficient B2 */ | |
171 | { 0x8A, 0x00 }, /* 8A Equalizer Band 5 Coefficient B2 */ | |
172 | { 0x8B, 0x00 }, /* 8B Equalizer Band 5 Coefficient A1 */ | |
173 | { 0x8C, 0x00 }, /* 8C Equalizer Band 5 Coefficient A1 */ | |
174 | { 0x8D, 0x00 }, /* 8D Equalizer Band 5 Coefficient A1 */ | |
175 | { 0x8E, 0x00 }, /* 8E Equalizer Band 5 Coefficient A2 */ | |
176 | { 0x8F, 0x00 }, /* 8F Equalizer Band 5 Coefficient A2 */ | |
177 | ||
178 | { 0x90, 0x00 }, /* 90 Equalizer Band 5 Coefficient A2 */ | |
179 | { 0x91, 0x00 }, /* 91 Equalizer Band 6 Coefficient B0 */ | |
180 | { 0x92, 0x00 }, /* 92 Equalizer Band 6 Coefficient B0 */ | |
181 | { 0x93, 0x00 }, /* 93 Equalizer Band 6 Coefficient B0 */ | |
182 | { 0x94, 0x00 }, /* 94 Equalizer Band 6 Coefficient B1 */ | |
183 | { 0x95, 0x00 }, /* 95 Equalizer Band 6 Coefficient B1 */ | |
184 | { 0x96, 0x00 }, /* 96 Equalizer Band 6 Coefficient B1 */ | |
185 | { 0x97, 0x00 }, /* 97 Equalizer Band 6 Coefficient B2 */ | |
186 | { 0x98, 0x00 }, /* 98 Equalizer Band 6 Coefficient B2 */ | |
187 | { 0x99, 0x00 }, /* 99 Equalizer Band 6 Coefficient B2 */ | |
188 | { 0x9A, 0x00 }, /* 9A Equalizer Band 6 Coefficient A1 */ | |
189 | { 0x9B, 0x00 }, /* 9B Equalizer Band 6 Coefficient A1 */ | |
190 | { 0x9C, 0x00 }, /* 9C Equalizer Band 6 Coefficient A1 */ | |
191 | { 0x9D, 0x00 }, /* 9D Equalizer Band 6 Coefficient A2 */ | |
192 | { 0x9E, 0x00 }, /* 9E Equalizer Band 6 Coefficient A2 */ | |
193 | { 0x9F, 0x00 }, /* 9F Equalizer Band 6 Coefficient A2 */ | |
194 | ||
195 | { 0xA0, 0x00 }, /* A0 Equalizer Band 7 Coefficient B0 */ | |
196 | { 0xA1, 0x00 }, /* A1 Equalizer Band 7 Coefficient B0 */ | |
197 | { 0xA2, 0x00 }, /* A2 Equalizer Band 7 Coefficient B0 */ | |
198 | { 0xA3, 0x00 }, /* A3 Equalizer Band 7 Coefficient B1 */ | |
199 | { 0xA4, 0x00 }, /* A4 Equalizer Band 7 Coefficient B1 */ | |
200 | { 0xA5, 0x00 }, /* A5 Equalizer Band 7 Coefficient B1 */ | |
201 | { 0xA6, 0x00 }, /* A6 Equalizer Band 7 Coefficient B2 */ | |
202 | { 0xA7, 0x00 }, /* A7 Equalizer Band 7 Coefficient B2 */ | |
203 | { 0xA8, 0x00 }, /* A8 Equalizer Band 7 Coefficient B2 */ | |
204 | { 0xA9, 0x00 }, /* A9 Equalizer Band 7 Coefficient A1 */ | |
205 | { 0xAA, 0x00 }, /* AA Equalizer Band 7 Coefficient A1 */ | |
206 | { 0xAB, 0x00 }, /* AB Equalizer Band 7 Coefficient A1 */ | |
207 | { 0xAC, 0x00 }, /* AC Equalizer Band 7 Coefficient A2 */ | |
208 | { 0xAD, 0x00 }, /* AD Equalizer Band 7 Coefficient A2 */ | |
209 | { 0xAE, 0x00 }, /* AE Equalizer Band 7 Coefficient A2 */ | |
210 | { 0xAF, 0x00 }, /* AF ADC Biquad Coefficient B0 */ | |
211 | ||
212 | { 0xB0, 0x00 }, /* B0 ADC Biquad Coefficient B0 */ | |
213 | { 0xB1, 0x00 }, /* B1 ADC Biquad Coefficient B0 */ | |
214 | { 0xB2, 0x00 }, /* B2 ADC Biquad Coefficient B1 */ | |
215 | { 0xB3, 0x00 }, /* B3 ADC Biquad Coefficient B1 */ | |
216 | { 0xB4, 0x00 }, /* B4 ADC Biquad Coefficient B1 */ | |
217 | { 0xB5, 0x00 }, /* B5 ADC Biquad Coefficient B2 */ | |
218 | { 0xB6, 0x00 }, /* B6 ADC Biquad Coefficient B2 */ | |
219 | { 0xB7, 0x00 }, /* B7 ADC Biquad Coefficient B2 */ | |
220 | { 0xB8, 0x00 }, /* B8 ADC Biquad Coefficient A1 */ | |
221 | { 0xB9, 0x00 }, /* B9 ADC Biquad Coefficient A1 */ | |
222 | { 0xBA, 0x00 }, /* BA ADC Biquad Coefficient A1 */ | |
223 | { 0xBB, 0x00 }, /* BB ADC Biquad Coefficient A2 */ | |
224 | { 0xBC, 0x00 }, /* BC ADC Biquad Coefficient A2 */ | |
225 | { 0xBD, 0x00 }, /* BD ADC Biquad Coefficient A2 */ | |
226 | { 0xBE, 0x00 }, /* BE Digital Mic 3 Volume */ | |
227 | { 0xBF, 0x00 }, /* BF Digital Mic 4 Volume */ | |
228 | ||
229 | { 0xC0, 0x00 }, /* C0 Digital Mic 34 Biquad Pre Atten */ | |
230 | { 0xC1, 0x00 }, /* C1 Record TDM Slot */ | |
231 | { 0xC2, 0x00 }, /* C2 Sample Rate */ | |
232 | { 0xC3, 0x00 }, /* C3 Digital Mic 34 Biquad Coefficient C3 */ | |
233 | { 0xC4, 0x00 }, /* C4 Digital Mic 34 Biquad Coefficient C4 */ | |
234 | { 0xC5, 0x00 }, /* C5 Digital Mic 34 Biquad Coefficient C5 */ | |
235 | { 0xC6, 0x00 }, /* C6 Digital Mic 34 Biquad Coefficient C6 */ | |
236 | { 0xC7, 0x00 }, /* C7 Digital Mic 34 Biquad Coefficient C7 */ | |
237 | { 0xC8, 0x00 }, /* C8 Digital Mic 34 Biquad Coefficient C8 */ | |
238 | { 0xC9, 0x00 }, /* C9 Digital Mic 34 Biquad Coefficient C9 */ | |
239 | { 0xCA, 0x00 }, /* CA Digital Mic 34 Biquad Coefficient CA */ | |
240 | { 0xCB, 0x00 }, /* CB Digital Mic 34 Biquad Coefficient CB */ | |
241 | { 0xCC, 0x00 }, /* CC Digital Mic 34 Biquad Coefficient CC */ | |
242 | { 0xCD, 0x00 }, /* CD Digital Mic 34 Biquad Coefficient CD */ | |
243 | { 0xCE, 0x00 }, /* CE Digital Mic 34 Biquad Coefficient CE */ | |
244 | { 0xCF, 0x00 }, /* CF Digital Mic 34 Biquad Coefficient CF */ | |
245 | ||
246 | { 0xD0, 0x00 }, /* D0 Digital Mic 34 Biquad Coefficient D0 */ | |
247 | { 0xD1, 0x00 }, /* D1 Digital Mic 34 Biquad Coefficient D1 */ | |
248 | }; | |
249 | ||
250 | static bool max98090_volatile_register(struct device *dev, unsigned int reg) | |
251 | { | |
252 | switch (reg) { | |
25b4ab43 | 253 | case M98090_REG_SOFTWARE_RESET: |
685e4215 JW |
254 | case M98090_REG_DEVICE_STATUS: |
255 | case M98090_REG_JACK_STATUS: | |
256 | case M98090_REG_REVISION_ID: | |
257 | return true; | |
258 | default: | |
259 | return false; | |
260 | } | |
261 | } | |
262 | ||
263 | static bool max98090_readable_register(struct device *dev, unsigned int reg) | |
264 | { | |
265 | switch (reg) { | |
62d6d47c AL |
266 | case M98090_REG_DEVICE_STATUS ... M98090_REG_INTERRUPT_S: |
267 | case M98090_REG_LINE_INPUT_CONFIG ... 0xD1: | |
e126a646 | 268 | case M98090_REG_REVISION_ID: |
685e4215 JW |
269 | return true; |
270 | default: | |
271 | return false; | |
272 | } | |
273 | } | |
274 | ||
275 | static int max98090_reset(struct max98090_priv *max98090) | |
276 | { | |
277 | int ret; | |
278 | ||
279 | /* Reset the codec by writing to this write-only reset register */ | |
280 | ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET, | |
281 | M98090_SWRESET_MASK); | |
282 | if (ret < 0) { | |
4c66b9d1 | 283 | dev_err(max98090->component->dev, |
685e4215 JW |
284 | "Failed to reset codec: %d\n", ret); |
285 | return ret; | |
286 | } | |
287 | ||
288 | msleep(20); | |
289 | return ret; | |
290 | } | |
291 | ||
8896bc3e | 292 | static const DECLARE_TLV_DB_RANGE(max98090_micboost_tlv, |
685e4215 | 293 | 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0), |
8896bc3e LPC |
294 | 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0) |
295 | ); | |
685e4215 JW |
296 | |
297 | static const DECLARE_TLV_DB_SCALE(max98090_mic_tlv, 0, 100, 0); | |
298 | ||
299 | static const DECLARE_TLV_DB_SCALE(max98090_line_single_ended_tlv, | |
300 | -600, 600, 0); | |
301 | ||
8896bc3e | 302 | static const DECLARE_TLV_DB_RANGE(max98090_line_tlv, |
685e4215 | 303 | 0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0), |
8896bc3e LPC |
304 | 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0) |
305 | ); | |
685e4215 JW |
306 | |
307 | static const DECLARE_TLV_DB_SCALE(max98090_avg_tlv, 0, 600, 0); | |
308 | static const DECLARE_TLV_DB_SCALE(max98090_av_tlv, -1200, 100, 0); | |
309 | ||
310 | static const DECLARE_TLV_DB_SCALE(max98090_dvg_tlv, 0, 600, 0); | |
311 | static const DECLARE_TLV_DB_SCALE(max98090_dv_tlv, -1500, 100, 0); | |
312 | ||
685e4215 JW |
313 | static const DECLARE_TLV_DB_SCALE(max98090_alcmakeup_tlv, 0, 100, 0); |
314 | static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv, -3100, 100, 0); | |
315 | static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv, -6600, 100, 0); | |
729af1ce | 316 | static const DECLARE_TLV_DB_SCALE(max98090_sdg_tlv, 50, 200, 0); |
685e4215 | 317 | |
8896bc3e | 318 | static const DECLARE_TLV_DB_RANGE(max98090_mixout_tlv, |
685e4215 | 319 | 0, 1, TLV_DB_SCALE_ITEM(-1200, 250, 0), |
8896bc3e LPC |
320 | 2, 3, TLV_DB_SCALE_ITEM(-600, 600, 0) |
321 | ); | |
685e4215 | 322 | |
8896bc3e | 323 | static const DECLARE_TLV_DB_RANGE(max98090_hp_tlv, |
685e4215 JW |
324 | 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0), |
325 | 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0), | |
326 | 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0), | |
327 | 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0), | |
8896bc3e LPC |
328 | 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0) |
329 | ); | |
685e4215 | 330 | |
8896bc3e | 331 | static const DECLARE_TLV_DB_RANGE(max98090_spk_tlv, |
685e4215 JW |
332 | 0, 4, TLV_DB_SCALE_ITEM(-4800, 400, 0), |
333 | 5, 10, TLV_DB_SCALE_ITEM(-2900, 300, 0), | |
334 | 11, 14, TLV_DB_SCALE_ITEM(-1200, 200, 0), | |
335 | 15, 29, TLV_DB_SCALE_ITEM(-500, 100, 0), | |
8896bc3e LPC |
336 | 30, 39, TLV_DB_SCALE_ITEM(950, 50, 0) |
337 | ); | |
685e4215 | 338 | |
8896bc3e | 339 | static const DECLARE_TLV_DB_RANGE(max98090_rcv_lout_tlv, |
685e4215 JW |
340 | 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0), |
341 | 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0), | |
342 | 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0), | |
343 | 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0), | |
8896bc3e LPC |
344 | 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0) |
345 | ); | |
685e4215 JW |
346 | |
347 | static int max98090_get_enab_tlv(struct snd_kcontrol *kcontrol, | |
348 | struct snd_ctl_elem_value *ucontrol) | |
349 | { | |
4c66b9d1 KM |
350 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
351 | struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); | |
685e4215 JW |
352 | struct soc_mixer_control *mc = |
353 | (struct soc_mixer_control *)kcontrol->private_value; | |
354 | unsigned int mask = (1 << fls(mc->max)) - 1; | |
1227f601 | 355 | unsigned int val = snd_soc_component_read(component, mc->reg); |
685e4215 JW |
356 | unsigned int *select; |
357 | ||
358 | switch (mc->reg) { | |
359 | case M98090_REG_MIC1_INPUT_LEVEL: | |
360 | select = &(max98090->pa1en); | |
361 | break; | |
362 | case M98090_REG_MIC2_INPUT_LEVEL: | |
363 | select = &(max98090->pa2en); | |
364 | break; | |
365 | case M98090_REG_ADC_SIDETONE: | |
366 | select = &(max98090->sidetone); | |
367 | break; | |
368 | default: | |
369 | return -EINVAL; | |
370 | } | |
371 | ||
372 | val = (val >> mc->shift) & mask; | |
373 | ||
374 | if (val >= 1) { | |
375 | /* If on, return the volume */ | |
376 | val = val - 1; | |
377 | *select = val; | |
378 | } else { | |
379 | /* If off, return last stored value */ | |
380 | val = *select; | |
381 | } | |
382 | ||
383 | ucontrol->value.integer.value[0] = val; | |
384 | return 0; | |
385 | } | |
386 | ||
387 | static int max98090_put_enab_tlv(struct snd_kcontrol *kcontrol, | |
388 | struct snd_ctl_elem_value *ucontrol) | |
389 | { | |
4c66b9d1 KM |
390 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
391 | struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); | |
685e4215 JW |
392 | struct soc_mixer_control *mc = |
393 | (struct soc_mixer_control *)kcontrol->private_value; | |
394 | unsigned int mask = (1 << fls(mc->max)) - 1; | |
f7a34446 AK |
395 | int sel_unchecked = ucontrol->value.integer.value[0]; |
396 | unsigned int sel; | |
1227f601 | 397 | unsigned int val = snd_soc_component_read(component, mc->reg); |
685e4215 | 398 | unsigned int *select; |
a0746cbd | 399 | int change; |
685e4215 JW |
400 | |
401 | switch (mc->reg) { | |
402 | case M98090_REG_MIC1_INPUT_LEVEL: | |
403 | select = &(max98090->pa1en); | |
404 | break; | |
405 | case M98090_REG_MIC2_INPUT_LEVEL: | |
406 | select = &(max98090->pa2en); | |
407 | break; | |
408 | case M98090_REG_ADC_SIDETONE: | |
409 | select = &(max98090->sidetone); | |
410 | break; | |
411 | default: | |
412 | return -EINVAL; | |
413 | } | |
414 | ||
415 | val = (val >> mc->shift) & mask; | |
416 | ||
f7a34446 | 417 | if (sel_unchecked < 0 || sel_unchecked > mc->max) |
2fbe467b | 418 | return -EINVAL; |
f7a34446 | 419 | sel = sel_unchecked; |
2fbe467b | 420 | |
a0746cbd | 421 | change = *select != sel; |
685e4215 JW |
422 | *select = sel; |
423 | ||
424 | /* Setting a volume is only valid if it is already On */ | |
425 | if (val >= 1) { | |
426 | sel = sel + 1; | |
427 | } else { | |
428 | /* Write what was already there */ | |
429 | sel = val; | |
430 | } | |
431 | ||
4c66b9d1 | 432 | snd_soc_component_update_bits(component, mc->reg, |
685e4215 JW |
433 | mask << mc->shift, |
434 | sel << mc->shift); | |
435 | ||
a0746cbd | 436 | return change; |
685e4215 JW |
437 | } |
438 | ||
4ca74feb | 439 | static const char *max98090_perf_pwr_text[] = |
685e4215 | 440 | { "High Performance", "Low Power" }; |
4ca74feb | 441 | static const char *max98090_pwr_perf_text[] = |
685e4215 JW |
442 | { "Low Power", "High Performance" }; |
443 | ||
2907cbcc TI |
444 | static SOC_ENUM_SINGLE_DECL(max98090_vcmbandgap_enum, |
445 | M98090_REG_BIAS_CONTROL, | |
446 | M98090_VCM_MODE_SHIFT, | |
447 | max98090_pwr_perf_text); | |
685e4215 | 448 | |
4ca74feb | 449 | static const char *max98090_osr128_text[] = { "64*fs", "128*fs" }; |
685e4215 | 450 | |
2907cbcc TI |
451 | static SOC_ENUM_SINGLE_DECL(max98090_osr128_enum, |
452 | M98090_REG_ADC_CONTROL, | |
453 | M98090_OSR128_SHIFT, | |
454 | max98090_osr128_text); | |
685e4215 JW |
455 | |
456 | static const char *max98090_mode_text[] = { "Voice", "Music" }; | |
457 | ||
2907cbcc TI |
458 | static SOC_ENUM_SINGLE_DECL(max98090_mode_enum, |
459 | M98090_REG_FILTER_CONFIG, | |
460 | M98090_MODE_SHIFT, | |
461 | max98090_mode_text); | |
685e4215 | 462 | |
2907cbcc TI |
463 | static SOC_ENUM_SINGLE_DECL(max98090_filter_dmic34mode_enum, |
464 | M98090_REG_FILTER_CONFIG, | |
465 | M98090_FLT_DMIC34MODE_SHIFT, | |
466 | max98090_mode_text); | |
685e4215 | 467 | |
4ca74feb | 468 | static const char *max98090_drcatk_text[] = |
685e4215 JW |
469 | { "0.5ms", "1ms", "5ms", "10ms", "25ms", "50ms", "100ms", "200ms" }; |
470 | ||
2907cbcc TI |
471 | static SOC_ENUM_SINGLE_DECL(max98090_drcatk_enum, |
472 | M98090_REG_DRC_TIMING, | |
473 | M98090_DRCATK_SHIFT, | |
474 | max98090_drcatk_text); | |
685e4215 | 475 | |
4ca74feb | 476 | static const char *max98090_drcrls_text[] = |
685e4215 JW |
477 | { "8s", "4s", "2s", "1s", "0.5s", "0.25s", "0.125s", "0.0625s" }; |
478 | ||
2907cbcc TI |
479 | static SOC_ENUM_SINGLE_DECL(max98090_drcrls_enum, |
480 | M98090_REG_DRC_TIMING, | |
481 | M98090_DRCRLS_SHIFT, | |
482 | max98090_drcrls_text); | |
685e4215 | 483 | |
4ca74feb | 484 | static const char *max98090_alccmp_text[] = |
685e4215 JW |
485 | { "1:1", "1:1.5", "1:2", "1:4", "1:INF" }; |
486 | ||
2907cbcc TI |
487 | static SOC_ENUM_SINGLE_DECL(max98090_alccmp_enum, |
488 | M98090_REG_DRC_COMPRESSOR, | |
489 | M98090_DRCCMP_SHIFT, | |
490 | max98090_alccmp_text); | |
685e4215 | 491 | |
4ca74feb | 492 | static const char *max98090_drcexp_text[] = { "1:1", "2:1", "3:1" }; |
685e4215 | 493 | |
2907cbcc TI |
494 | static SOC_ENUM_SINGLE_DECL(max98090_drcexp_enum, |
495 | M98090_REG_DRC_EXPANDER, | |
496 | M98090_DRCEXP_SHIFT, | |
497 | max98090_drcexp_text); | |
685e4215 | 498 | |
2907cbcc TI |
499 | static SOC_ENUM_SINGLE_DECL(max98090_dac_perfmode_enum, |
500 | M98090_REG_DAC_CONTROL, | |
501 | M98090_PERFMODE_SHIFT, | |
502 | max98090_perf_pwr_text); | |
685e4215 | 503 | |
2907cbcc TI |
504 | static SOC_ENUM_SINGLE_DECL(max98090_dachp_enum, |
505 | M98090_REG_DAC_CONTROL, | |
506 | M98090_DACHP_SHIFT, | |
507 | max98090_pwr_perf_text); | |
685e4215 | 508 | |
2907cbcc TI |
509 | static SOC_ENUM_SINGLE_DECL(max98090_adchp_enum, |
510 | M98090_REG_ADC_CONTROL, | |
511 | M98090_ADCHP_SHIFT, | |
512 | max98090_pwr_perf_text); | |
685e4215 JW |
513 | |
514 | static const struct snd_kcontrol_new max98090_snd_controls[] = { | |
4b8a1ca4 | 515 | SOC_ENUM("MIC Bias VCM Bandgap", max98090_vcmbandgap_enum), |
685e4215 | 516 | |
4b8a1ca4 TBS |
517 | SOC_SINGLE("DMIC MIC Comp Filter Config", M98090_REG_DIGITAL_MIC_CONFIG, |
518 | M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0), | |
685e4215 JW |
519 | |
520 | SOC_SINGLE_EXT_TLV("MIC1 Boost Volume", | |
521 | M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT, | |
522 | M98090_MIC_PA1EN_NUM - 1, 0, max98090_get_enab_tlv, | |
523 | max98090_put_enab_tlv, max98090_micboost_tlv), | |
524 | ||
525 | SOC_SINGLE_EXT_TLV("MIC2 Boost Volume", | |
526 | M98090_REG_MIC2_INPUT_LEVEL, M98090_MIC_PA2EN_SHIFT, | |
527 | M98090_MIC_PA2EN_NUM - 1, 0, max98090_get_enab_tlv, | |
528 | max98090_put_enab_tlv, max98090_micboost_tlv), | |
529 | ||
530 | SOC_SINGLE_TLV("MIC1 Volume", M98090_REG_MIC1_INPUT_LEVEL, | |
531 | M98090_MIC_PGAM1_SHIFT, M98090_MIC_PGAM1_NUM - 1, 1, | |
532 | max98090_mic_tlv), | |
533 | ||
534 | SOC_SINGLE_TLV("MIC2 Volume", M98090_REG_MIC2_INPUT_LEVEL, | |
535 | M98090_MIC_PGAM2_SHIFT, M98090_MIC_PGAM2_NUM - 1, 1, | |
536 | max98090_mic_tlv), | |
537 | ||
538 | SOC_SINGLE_RANGE_TLV("LINEA Single Ended Volume", | |
539 | M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG135_SHIFT, 0, | |
540 | M98090_MIXG135_NUM - 1, 1, max98090_line_single_ended_tlv), | |
541 | ||
542 | SOC_SINGLE_RANGE_TLV("LINEB Single Ended Volume", | |
543 | M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG246_SHIFT, 0, | |
544 | M98090_MIXG246_NUM - 1, 1, max98090_line_single_ended_tlv), | |
545 | ||
546 | SOC_SINGLE_RANGE_TLV("LINEA Volume", M98090_REG_LINE_INPUT_LEVEL, | |
547 | M98090_LINAPGA_SHIFT, 0, M98090_LINAPGA_NUM - 1, 1, | |
548 | max98090_line_tlv), | |
549 | ||
550 | SOC_SINGLE_RANGE_TLV("LINEB Volume", M98090_REG_LINE_INPUT_LEVEL, | |
551 | M98090_LINBPGA_SHIFT, 0, M98090_LINBPGA_NUM - 1, 1, | |
552 | max98090_line_tlv), | |
553 | ||
554 | SOC_SINGLE("LINEA Ext Resistor Gain Mode", M98090_REG_INPUT_MODE, | |
555 | M98090_EXTBUFA_SHIFT, M98090_EXTBUFA_NUM - 1, 0), | |
556 | SOC_SINGLE("LINEB Ext Resistor Gain Mode", M98090_REG_INPUT_MODE, | |
557 | M98090_EXTBUFB_SHIFT, M98090_EXTBUFB_NUM - 1, 0), | |
558 | ||
559 | SOC_SINGLE_TLV("ADCL Boost Volume", M98090_REG_LEFT_ADC_LEVEL, | |
560 | M98090_AVLG_SHIFT, M98090_AVLG_NUM - 1, 0, | |
561 | max98090_avg_tlv), | |
562 | SOC_SINGLE_TLV("ADCR Boost Volume", M98090_REG_RIGHT_ADC_LEVEL, | |
563 | M98090_AVRG_SHIFT, M98090_AVLG_NUM - 1, 0, | |
564 | max98090_avg_tlv), | |
565 | ||
566 | SOC_SINGLE_TLV("ADCL Volume", M98090_REG_LEFT_ADC_LEVEL, | |
567 | M98090_AVL_SHIFT, M98090_AVL_NUM - 1, 1, | |
568 | max98090_av_tlv), | |
569 | SOC_SINGLE_TLV("ADCR Volume", M98090_REG_RIGHT_ADC_LEVEL, | |
570 | M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1, | |
571 | max98090_av_tlv), | |
572 | ||
4b8a1ca4 TBS |
573 | SOC_ENUM("ADC Oversampling Rate", max98090_osr128_enum), |
574 | SOC_SINGLE("ADC Quantizer Dither", M98090_REG_ADC_CONTROL, | |
575 | M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0), | |
576 | SOC_ENUM("ADC High Performance Mode", max98090_adchp_enum), | |
577 | ||
578 | SOC_SINGLE("DAC Mono Mode", M98090_REG_IO_CONFIGURATION, | |
579 | M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0), | |
580 | SOC_SINGLE("SDIN Mode", M98090_REG_IO_CONFIGURATION, | |
581 | M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0), | |
582 | SOC_SINGLE("SDOUT Mode", M98090_REG_IO_CONFIGURATION, | |
583 | M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0), | |
584 | SOC_SINGLE("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION, | |
585 | M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1), | |
586 | SOC_ENUM("Filter Mode", max98090_mode_enum), | |
587 | SOC_SINGLE("Record Path DC Blocking", M98090_REG_FILTER_CONFIG, | |
588 | M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0), | |
589 | SOC_SINGLE("Playback Path DC Blocking", M98090_REG_FILTER_CONFIG, | |
590 | M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0), | |
685e4215 JW |
591 | SOC_SINGLE_TLV("Digital BQ Volume", M98090_REG_ADC_BIQUAD_LEVEL, |
592 | M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv), | |
593 | SOC_SINGLE_EXT_TLV("Digital Sidetone Volume", | |
594 | M98090_REG_ADC_SIDETONE, M98090_DVST_SHIFT, | |
595 | M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv, | |
729af1ce | 596 | max98090_put_enab_tlv, max98090_sdg_tlv), |
685e4215 JW |
597 | SOC_SINGLE_TLV("Digital Coarse Volume", M98090_REG_DAI_PLAYBACK_LEVEL, |
598 | M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0, | |
599 | max98090_dvg_tlv), | |
600 | SOC_SINGLE_TLV("Digital Volume", M98090_REG_DAI_PLAYBACK_LEVEL, | |
601 | M98090_DV_SHIFT, M98090_DV_NUM - 1, 1, | |
602 | max98090_dv_tlv), | |
4b8a1ca4 TBS |
603 | SND_SOC_BYTES("EQ Coefficients", M98090_REG_EQUALIZER_BASE, 105), |
604 | SOC_SINGLE("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE, | |
605 | M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0), | |
606 | SOC_SINGLE("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE, | |
607 | M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0), | |
608 | SOC_SINGLE("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE, | |
609 | M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0), | |
685e4215 JW |
610 | SOC_SINGLE("Digital EQ Clipping Detection", M98090_REG_DAI_PLAYBACK_LEVEL_EQ, |
611 | M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1, | |
612 | 1), | |
613 | SOC_SINGLE_TLV("Digital EQ Volume", M98090_REG_DAI_PLAYBACK_LEVEL_EQ, | |
614 | M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1, | |
615 | max98090_dv_tlv), | |
616 | ||
4b8a1ca4 TBS |
617 | SOC_SINGLE("ALC Enable", M98090_REG_DRC_TIMING, |
618 | M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0), | |
619 | SOC_ENUM("ALC Attack Time", max98090_drcatk_enum), | |
620 | SOC_ENUM("ALC Release Time", max98090_drcrls_enum), | |
685e4215 JW |
621 | SOC_SINGLE_TLV("ALC Make Up Volume", M98090_REG_DRC_GAIN, |
622 | M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0, | |
623 | max98090_alcmakeup_tlv), | |
4b8a1ca4 TBS |
624 | SOC_ENUM("ALC Compression Ratio", max98090_alccmp_enum), |
625 | SOC_ENUM("ALC Expansion Ratio", max98090_drcexp_enum), | |
626 | SOC_SINGLE_TLV("ALC Compression Threshold Volume", | |
685e4215 | 627 | M98090_REG_DRC_COMPRESSOR, M98090_DRCTHC_SHIFT, |
4b8a1ca4 TBS |
628 | M98090_DRCTHC_NUM - 1, 1, max98090_alccomp_tlv), |
629 | SOC_SINGLE_TLV("ALC Expansion Threshold Volume", | |
685e4215 | 630 | M98090_REG_DRC_EXPANDER, M98090_DRCTHE_SHIFT, |
4b8a1ca4 | 631 | M98090_DRCTHE_NUM - 1, 1, max98090_drcexp_tlv), |
685e4215 | 632 | |
4b8a1ca4 TBS |
633 | SOC_ENUM("DAC HP Playback Performance Mode", |
634 | max98090_dac_perfmode_enum), | |
635 | SOC_ENUM("DAC High Performance Mode", max98090_dachp_enum), | |
685e4215 JW |
636 | |
637 | SOC_SINGLE_TLV("Headphone Left Mixer Volume", | |
638 | M98090_REG_HP_CONTROL, M98090_MIXHPLG_SHIFT, | |
639 | M98090_MIXHPLG_NUM - 1, 1, max98090_mixout_tlv), | |
640 | SOC_SINGLE_TLV("Headphone Right Mixer Volume", | |
641 | M98090_REG_HP_CONTROL, M98090_MIXHPRG_SHIFT, | |
642 | M98090_MIXHPRG_NUM - 1, 1, max98090_mixout_tlv), | |
643 | ||
644 | SOC_SINGLE_TLV("Speaker Left Mixer Volume", | |
645 | M98090_REG_SPK_CONTROL, M98090_MIXSPLG_SHIFT, | |
646 | M98090_MIXSPLG_NUM - 1, 1, max98090_mixout_tlv), | |
647 | SOC_SINGLE_TLV("Speaker Right Mixer Volume", | |
648 | M98090_REG_SPK_CONTROL, M98090_MIXSPRG_SHIFT, | |
649 | M98090_MIXSPRG_NUM - 1, 1, max98090_mixout_tlv), | |
650 | ||
651 | SOC_SINGLE_TLV("Receiver Left Mixer Volume", | |
652 | M98090_REG_RCV_LOUTL_CONTROL, M98090_MIXRCVLG_SHIFT, | |
653 | M98090_MIXRCVLG_NUM - 1, 1, max98090_mixout_tlv), | |
654 | SOC_SINGLE_TLV("Receiver Right Mixer Volume", | |
655 | M98090_REG_LOUTR_CONTROL, M98090_MIXRCVRG_SHIFT, | |
656 | M98090_MIXRCVRG_NUM - 1, 1, max98090_mixout_tlv), | |
657 | ||
658 | SOC_DOUBLE_R_TLV("Headphone Volume", M98090_REG_LEFT_HP_VOLUME, | |
659 | M98090_REG_RIGHT_HP_VOLUME, M98090_HPVOLL_SHIFT, | |
660 | M98090_HPVOLL_NUM - 1, 0, max98090_hp_tlv), | |
661 | ||
662 | SOC_DOUBLE_R_RANGE_TLV("Speaker Volume", | |
663 | M98090_REG_LEFT_SPK_VOLUME, M98090_REG_RIGHT_SPK_VOLUME, | |
664 | M98090_SPVOLL_SHIFT, 24, M98090_SPVOLL_NUM - 1 + 24, | |
665 | 0, max98090_spk_tlv), | |
666 | ||
667 | SOC_DOUBLE_R_TLV("Receiver Volume", M98090_REG_RCV_LOUTL_VOLUME, | |
668 | M98090_REG_LOUTR_VOLUME, M98090_RCVLVOL_SHIFT, | |
669 | M98090_RCVLVOL_NUM - 1, 0, max98090_rcv_lout_tlv), | |
670 | ||
671 | SOC_SINGLE("Headphone Left Switch", M98090_REG_LEFT_HP_VOLUME, | |
672 | M98090_HPLM_SHIFT, 1, 1), | |
673 | SOC_SINGLE("Headphone Right Switch", M98090_REG_RIGHT_HP_VOLUME, | |
674 | M98090_HPRM_SHIFT, 1, 1), | |
675 | ||
676 | SOC_SINGLE("Speaker Left Switch", M98090_REG_LEFT_SPK_VOLUME, | |
677 | M98090_SPLM_SHIFT, 1, 1), | |
678 | SOC_SINGLE("Speaker Right Switch", M98090_REG_RIGHT_SPK_VOLUME, | |
679 | M98090_SPRM_SHIFT, 1, 1), | |
680 | ||
681 | SOC_SINGLE("Receiver Left Switch", M98090_REG_RCV_LOUTL_VOLUME, | |
682 | M98090_RCVLM_SHIFT, 1, 1), | |
683 | SOC_SINGLE("Receiver Right Switch", M98090_REG_LOUTR_VOLUME, | |
684 | M98090_RCVRM_SHIFT, 1, 1), | |
685 | ||
686 | SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL, | |
687 | M98090_ZDENN_SHIFT, M98090_ZDENN_NUM - 1, 1), | |
688 | SOC_SINGLE("Enhanced Vol Smoothing", M98090_REG_LEVEL_CONTROL, | |
689 | M98090_VS2ENN_SHIFT, M98090_VS2ENN_NUM - 1, 1), | |
690 | SOC_SINGLE("Volume Adjustment Smoothing", M98090_REG_LEVEL_CONTROL, | |
691 | M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1), | |
692 | ||
4b8a1ca4 TBS |
693 | SND_SOC_BYTES("Biquad Coefficients", M98090_REG_RECORD_BIQUAD_BASE, 15), |
694 | SOC_SINGLE("Biquad Switch", M98090_REG_DSP_FILTER_ENABLE, | |
695 | M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0), | |
685e4215 JW |
696 | }; |
697 | ||
698 | static const struct snd_kcontrol_new max98091_snd_controls[] = { | |
699 | ||
700 | SOC_SINGLE("DMIC34 Zeropad", M98090_REG_SAMPLE_RATE, | |
701 | M98090_DMIC34_ZEROPAD_SHIFT, | |
702 | M98090_DMIC34_ZEROPAD_NUM - 1, 0), | |
703 | ||
4b8a1ca4 TBS |
704 | SOC_ENUM("Filter DMIC34 Mode", max98090_filter_dmic34mode_enum), |
705 | SOC_SINGLE("DMIC34 DC Blocking", M98090_REG_FILTER_CONFIG, | |
685e4215 | 706 | M98090_FLT_DMIC34HPF_SHIFT, |
4b8a1ca4 | 707 | M98090_FLT_DMIC34HPF_NUM - 1, 0), |
685e4215 JW |
708 | |
709 | SOC_SINGLE_TLV("DMIC3 Boost Volume", M98090_REG_DMIC3_VOLUME, | |
710 | M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0, | |
711 | max98090_avg_tlv), | |
712 | SOC_SINGLE_TLV("DMIC4 Boost Volume", M98090_REG_DMIC4_VOLUME, | |
713 | M98090_DMIC_AV4G_SHIFT, M98090_DMIC_AV4G_NUM - 1, 0, | |
714 | max98090_avg_tlv), | |
715 | ||
716 | SOC_SINGLE_TLV("DMIC3 Volume", M98090_REG_DMIC3_VOLUME, | |
717 | M98090_DMIC_AV3_SHIFT, M98090_DMIC_AV3_NUM - 1, 1, | |
718 | max98090_av_tlv), | |
719 | SOC_SINGLE_TLV("DMIC4 Volume", M98090_REG_DMIC4_VOLUME, | |
720 | M98090_DMIC_AV4_SHIFT, M98090_DMIC_AV4_NUM - 1, 1, | |
721 | max98090_av_tlv), | |
722 | ||
723 | SND_SOC_BYTES("DMIC34 Biquad Coefficients", | |
724 | M98090_REG_DMIC34_BIQUAD_BASE, 15), | |
4b8a1ca4 TBS |
725 | SOC_SINGLE("DMIC34 Biquad Switch", M98090_REG_DSP_FILTER_ENABLE, |
726 | M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0), | |
685e4215 JW |
727 | |
728 | SOC_SINGLE_TLV("DMIC34 BQ PreAttenuation Volume", | |
729 | M98090_REG_DMIC34_BQ_PREATTEN, M98090_AV34BQ_SHIFT, | |
730 | M98090_AV34BQ_NUM - 1, 1, max98090_dv_tlv), | |
731 | }; | |
732 | ||
733 | static int max98090_micinput_event(struct snd_soc_dapm_widget *w, | |
734 | struct snd_kcontrol *kcontrol, int event) | |
735 | { | |
4c66b9d1 KM |
736 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); |
737 | struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); | |
685e4215 | 738 | |
1227f601 | 739 | unsigned int val = snd_soc_component_read(component, w->reg); |
685e4215 JW |
740 | |
741 | if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) | |
742 | val = (val & M98090_MIC_PA1EN_MASK) >> M98090_MIC_PA1EN_SHIFT; | |
743 | else | |
744 | val = (val & M98090_MIC_PA2EN_MASK) >> M98090_MIC_PA2EN_SHIFT; | |
745 | ||
685e4215 JW |
746 | if (val >= 1) { |
747 | if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) { | |
748 | max98090->pa1en = val - 1; /* Update for volatile */ | |
749 | } else { | |
750 | max98090->pa2en = val - 1; /* Update for volatile */ | |
751 | } | |
752 | } | |
753 | ||
754 | switch (event) { | |
755 | case SND_SOC_DAPM_POST_PMU: | |
756 | /* If turning on, set to most recently selected volume */ | |
757 | if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) | |
758 | val = max98090->pa1en + 1; | |
759 | else | |
760 | val = max98090->pa2en + 1; | |
761 | break; | |
762 | case SND_SOC_DAPM_POST_PMD: | |
763 | /* If turning off, turn off */ | |
764 | val = 0; | |
765 | break; | |
766 | default: | |
767 | return -EINVAL; | |
768 | } | |
769 | ||
770 | if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) | |
4c66b9d1 | 771 | snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA1EN_MASK, |
685e4215 JW |
772 | val << M98090_MIC_PA1EN_SHIFT); |
773 | else | |
4c66b9d1 | 774 | snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA2EN_MASK, |
685e4215 JW |
775 | val << M98090_MIC_PA2EN_SHIFT); |
776 | ||
777 | return 0; | |
778 | } | |
779 | ||
4b8a1ca4 TBS |
780 | static int max98090_shdn_event(struct snd_soc_dapm_widget *w, |
781 | struct snd_kcontrol *kcontrol, int event) | |
782 | { | |
783 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); | |
784 | struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); | |
785 | ||
786 | if (event & SND_SOC_DAPM_POST_PMU) | |
787 | max98090->shdn_pending = true; | |
788 | ||
789 | return 0; | |
790 | ||
791 | } | |
792 | ||
685e4215 JW |
793 | static const char *mic1_mux_text[] = { "IN12", "IN56" }; |
794 | ||
2907cbcc TI |
795 | static SOC_ENUM_SINGLE_DECL(mic1_mux_enum, |
796 | M98090_REG_INPUT_MODE, | |
797 | M98090_EXTMIC1_SHIFT, | |
798 | mic1_mux_text); | |
685e4215 JW |
799 | |
800 | static const struct snd_kcontrol_new max98090_mic1_mux = | |
801 | SOC_DAPM_ENUM("MIC1 Mux", mic1_mux_enum); | |
802 | ||
803 | static const char *mic2_mux_text[] = { "IN34", "IN56" }; | |
804 | ||
2907cbcc TI |
805 | static SOC_ENUM_SINGLE_DECL(mic2_mux_enum, |
806 | M98090_REG_INPUT_MODE, | |
807 | M98090_EXTMIC2_SHIFT, | |
808 | mic2_mux_text); | |
685e4215 JW |
809 | |
810 | static const struct snd_kcontrol_new max98090_mic2_mux = | |
811 | SOC_DAPM_ENUM("MIC2 Mux", mic2_mux_enum); | |
812 | ||
fd5f940f AB |
813 | static const char *dmic_mux_text[] = { "ADC", "DMIC" }; |
814 | ||
ba513116 | 815 | static SOC_ENUM_SINGLE_VIRT_DECL(dmic_mux_enum, dmic_mux_text); |
fd5f940f AB |
816 | |
817 | static const struct snd_kcontrol_new max98090_dmic_mux = | |
aae1137b | 818 | SOC_DAPM_ENUM("DMIC Mux", dmic_mux_enum); |
fd5f940f | 819 | |
685e4215 JW |
820 | /* LINEA mixer switch */ |
821 | static const struct snd_kcontrol_new max98090_linea_mixer_controls[] = { | |
822 | SOC_DAPM_SINGLE("IN1 Switch", M98090_REG_LINE_INPUT_CONFIG, | |
823 | M98090_IN1SEEN_SHIFT, 1, 0), | |
824 | SOC_DAPM_SINGLE("IN3 Switch", M98090_REG_LINE_INPUT_CONFIG, | |
825 | M98090_IN3SEEN_SHIFT, 1, 0), | |
826 | SOC_DAPM_SINGLE("IN5 Switch", M98090_REG_LINE_INPUT_CONFIG, | |
827 | M98090_IN5SEEN_SHIFT, 1, 0), | |
828 | SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LINE_INPUT_CONFIG, | |
829 | M98090_IN34DIFF_SHIFT, 1, 0), | |
830 | }; | |
831 | ||
832 | /* LINEB mixer switch */ | |
833 | static const struct snd_kcontrol_new max98090_lineb_mixer_controls[] = { | |
834 | SOC_DAPM_SINGLE("IN2 Switch", M98090_REG_LINE_INPUT_CONFIG, | |
835 | M98090_IN2SEEN_SHIFT, 1, 0), | |
836 | SOC_DAPM_SINGLE("IN4 Switch", M98090_REG_LINE_INPUT_CONFIG, | |
837 | M98090_IN4SEEN_SHIFT, 1, 0), | |
838 | SOC_DAPM_SINGLE("IN6 Switch", M98090_REG_LINE_INPUT_CONFIG, | |
839 | M98090_IN6SEEN_SHIFT, 1, 0), | |
840 | SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LINE_INPUT_CONFIG, | |
841 | M98090_IN56DIFF_SHIFT, 1, 0), | |
842 | }; | |
843 | ||
844 | /* Left ADC mixer switch */ | |
845 | static const struct snd_kcontrol_new max98090_left_adc_mixer_controls[] = { | |
846 | SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_LEFT_ADC_MIXER, | |
847 | M98090_MIXADL_IN12DIFF_SHIFT, 1, 0), | |
848 | SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LEFT_ADC_MIXER, | |
849 | M98090_MIXADL_IN34DIFF_SHIFT, 1, 0), | |
850 | SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LEFT_ADC_MIXER, | |
851 | M98090_MIXADL_IN65DIFF_SHIFT, 1, 0), | |
852 | SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_ADC_MIXER, | |
853 | M98090_MIXADL_LINEA_SHIFT, 1, 0), | |
854 | SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_ADC_MIXER, | |
855 | M98090_MIXADL_LINEB_SHIFT, 1, 0), | |
856 | SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_ADC_MIXER, | |
857 | M98090_MIXADL_MIC1_SHIFT, 1, 0), | |
858 | SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_ADC_MIXER, | |
859 | M98090_MIXADL_MIC2_SHIFT, 1, 0), | |
860 | }; | |
861 | ||
862 | /* Right ADC mixer switch */ | |
863 | static const struct snd_kcontrol_new max98090_right_adc_mixer_controls[] = { | |
864 | SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_RIGHT_ADC_MIXER, | |
865 | M98090_MIXADR_IN12DIFF_SHIFT, 1, 0), | |
866 | SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_RIGHT_ADC_MIXER, | |
867 | M98090_MIXADR_IN34DIFF_SHIFT, 1, 0), | |
868 | SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_RIGHT_ADC_MIXER, | |
869 | M98090_MIXADR_IN65DIFF_SHIFT, 1, 0), | |
870 | SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_ADC_MIXER, | |
871 | M98090_MIXADR_LINEA_SHIFT, 1, 0), | |
872 | SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_ADC_MIXER, | |
873 | M98090_MIXADR_LINEB_SHIFT, 1, 0), | |
874 | SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_ADC_MIXER, | |
875 | M98090_MIXADR_MIC1_SHIFT, 1, 0), | |
876 | SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_ADC_MIXER, | |
877 | M98090_MIXADR_MIC2_SHIFT, 1, 0), | |
878 | }; | |
879 | ||
880 | static const char *lten_mux_text[] = { "Normal", "Loopthrough" }; | |
881 | ||
2907cbcc TI |
882 | static SOC_ENUM_SINGLE_DECL(ltenl_mux_enum, |
883 | M98090_REG_IO_CONFIGURATION, | |
884 | M98090_LTEN_SHIFT, | |
885 | lten_mux_text); | |
685e4215 | 886 | |
2907cbcc TI |
887 | static SOC_ENUM_SINGLE_DECL(ltenr_mux_enum, |
888 | M98090_REG_IO_CONFIGURATION, | |
889 | M98090_LTEN_SHIFT, | |
890 | lten_mux_text); | |
685e4215 JW |
891 | |
892 | static const struct snd_kcontrol_new max98090_ltenl_mux = | |
4b8a1ca4 | 893 | SOC_DAPM_ENUM("LTENL Mux", ltenl_mux_enum); |
685e4215 JW |
894 | |
895 | static const struct snd_kcontrol_new max98090_ltenr_mux = | |
4b8a1ca4 | 896 | SOC_DAPM_ENUM("LTENR Mux", ltenr_mux_enum); |
685e4215 JW |
897 | |
898 | static const char *lben_mux_text[] = { "Normal", "Loopback" }; | |
899 | ||
2907cbcc TI |
900 | static SOC_ENUM_SINGLE_DECL(lbenl_mux_enum, |
901 | M98090_REG_IO_CONFIGURATION, | |
902 | M98090_LBEN_SHIFT, | |
903 | lben_mux_text); | |
685e4215 | 904 | |
2907cbcc TI |
905 | static SOC_ENUM_SINGLE_DECL(lbenr_mux_enum, |
906 | M98090_REG_IO_CONFIGURATION, | |
907 | M98090_LBEN_SHIFT, | |
908 | lben_mux_text); | |
685e4215 JW |
909 | |
910 | static const struct snd_kcontrol_new max98090_lbenl_mux = | |
4b8a1ca4 | 911 | SOC_DAPM_ENUM("LBENL Mux", lbenl_mux_enum); |
685e4215 JW |
912 | |
913 | static const struct snd_kcontrol_new max98090_lbenr_mux = | |
4b8a1ca4 | 914 | SOC_DAPM_ENUM("LBENR Mux", lbenr_mux_enum); |
685e4215 JW |
915 | |
916 | static const char *stenl_mux_text[] = { "Normal", "Sidetone Left" }; | |
917 | ||
918 | static const char *stenr_mux_text[] = { "Normal", "Sidetone Right" }; | |
919 | ||
2907cbcc TI |
920 | static SOC_ENUM_SINGLE_DECL(stenl_mux_enum, |
921 | M98090_REG_ADC_SIDETONE, | |
922 | M98090_DSTSL_SHIFT, | |
923 | stenl_mux_text); | |
685e4215 | 924 | |
2907cbcc TI |
925 | static SOC_ENUM_SINGLE_DECL(stenr_mux_enum, |
926 | M98090_REG_ADC_SIDETONE, | |
927 | M98090_DSTSR_SHIFT, | |
928 | stenr_mux_text); | |
685e4215 JW |
929 | |
930 | static const struct snd_kcontrol_new max98090_stenl_mux = | |
931 | SOC_DAPM_ENUM("STENL Mux", stenl_mux_enum); | |
932 | ||
933 | static const struct snd_kcontrol_new max98090_stenr_mux = | |
934 | SOC_DAPM_ENUM("STENR Mux", stenr_mux_enum); | |
935 | ||
936 | /* Left speaker mixer switch */ | |
937 | static const struct | |
938 | snd_kcontrol_new max98090_left_speaker_mixer_controls[] = { | |
939 | SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_SPK_MIXER, | |
940 | M98090_MIXSPL_DACL_SHIFT, 1, 0), | |
941 | SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_SPK_MIXER, | |
942 | M98090_MIXSPL_DACR_SHIFT, 1, 0), | |
943 | SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_SPK_MIXER, | |
944 | M98090_MIXSPL_LINEA_SHIFT, 1, 0), | |
945 | SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_SPK_MIXER, | |
946 | M98090_MIXSPL_LINEB_SHIFT, 1, 0), | |
947 | SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_SPK_MIXER, | |
948 | M98090_MIXSPL_MIC1_SHIFT, 1, 0), | |
949 | SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_SPK_MIXER, | |
950 | M98090_MIXSPL_MIC2_SHIFT, 1, 0), | |
951 | }; | |
952 | ||
953 | /* Right speaker mixer switch */ | |
954 | static const struct | |
955 | snd_kcontrol_new max98090_right_speaker_mixer_controls[] = { | |
956 | SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_SPK_MIXER, | |
957 | M98090_MIXSPR_DACL_SHIFT, 1, 0), | |
958 | SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_SPK_MIXER, | |
959 | M98090_MIXSPR_DACR_SHIFT, 1, 0), | |
960 | SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_SPK_MIXER, | |
961 | M98090_MIXSPR_LINEA_SHIFT, 1, 0), | |
962 | SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_SPK_MIXER, | |
963 | M98090_MIXSPR_LINEB_SHIFT, 1, 0), | |
964 | SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_SPK_MIXER, | |
965 | M98090_MIXSPR_MIC1_SHIFT, 1, 0), | |
966 | SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_SPK_MIXER, | |
967 | M98090_MIXSPR_MIC2_SHIFT, 1, 0), | |
968 | }; | |
969 | ||
970 | /* Left headphone mixer switch */ | |
971 | static const struct snd_kcontrol_new max98090_left_hp_mixer_controls[] = { | |
972 | SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_HP_MIXER, | |
973 | M98090_MIXHPL_DACL_SHIFT, 1, 0), | |
974 | SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_HP_MIXER, | |
975 | M98090_MIXHPL_DACR_SHIFT, 1, 0), | |
976 | SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_HP_MIXER, | |
977 | M98090_MIXHPL_LINEA_SHIFT, 1, 0), | |
978 | SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_HP_MIXER, | |
979 | M98090_MIXHPL_LINEB_SHIFT, 1, 0), | |
980 | SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_HP_MIXER, | |
981 | M98090_MIXHPL_MIC1_SHIFT, 1, 0), | |
982 | SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_HP_MIXER, | |
983 | M98090_MIXHPL_MIC2_SHIFT, 1, 0), | |
984 | }; | |
985 | ||
986 | /* Right headphone mixer switch */ | |
987 | static const struct snd_kcontrol_new max98090_right_hp_mixer_controls[] = { | |
988 | SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_HP_MIXER, | |
989 | M98090_MIXHPR_DACL_SHIFT, 1, 0), | |
990 | SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_HP_MIXER, | |
991 | M98090_MIXHPR_DACR_SHIFT, 1, 0), | |
992 | SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_HP_MIXER, | |
993 | M98090_MIXHPR_LINEA_SHIFT, 1, 0), | |
994 | SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_HP_MIXER, | |
995 | M98090_MIXHPR_LINEB_SHIFT, 1, 0), | |
996 | SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_HP_MIXER, | |
997 | M98090_MIXHPR_MIC1_SHIFT, 1, 0), | |
998 | SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_HP_MIXER, | |
999 | M98090_MIXHPR_MIC2_SHIFT, 1, 0), | |
1000 | }; | |
1001 | ||
1002 | /* Left receiver mixer switch */ | |
1003 | static const struct snd_kcontrol_new max98090_left_rcv_mixer_controls[] = { | |
1004 | SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RCV_LOUTL_MIXER, | |
1005 | M98090_MIXRCVL_DACL_SHIFT, 1, 0), | |
1006 | SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RCV_LOUTL_MIXER, | |
1007 | M98090_MIXRCVL_DACR_SHIFT, 1, 0), | |
1008 | SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RCV_LOUTL_MIXER, | |
1009 | M98090_MIXRCVL_LINEA_SHIFT, 1, 0), | |
1010 | SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RCV_LOUTL_MIXER, | |
1011 | M98090_MIXRCVL_LINEB_SHIFT, 1, 0), | |
1012 | SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RCV_LOUTL_MIXER, | |
1013 | M98090_MIXRCVL_MIC1_SHIFT, 1, 0), | |
1014 | SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RCV_LOUTL_MIXER, | |
1015 | M98090_MIXRCVL_MIC2_SHIFT, 1, 0), | |
1016 | }; | |
1017 | ||
1018 | /* Right receiver mixer switch */ | |
1019 | static const struct snd_kcontrol_new max98090_right_rcv_mixer_controls[] = { | |
1020 | SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LOUTR_MIXER, | |
1021 | M98090_MIXRCVR_DACL_SHIFT, 1, 0), | |
1022 | SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LOUTR_MIXER, | |
1023 | M98090_MIXRCVR_DACR_SHIFT, 1, 0), | |
1024 | SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LOUTR_MIXER, | |
1025 | M98090_MIXRCVR_LINEA_SHIFT, 1, 0), | |
1026 | SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LOUTR_MIXER, | |
1027 | M98090_MIXRCVR_LINEB_SHIFT, 1, 0), | |
1028 | SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LOUTR_MIXER, | |
1029 | M98090_MIXRCVR_MIC1_SHIFT, 1, 0), | |
1030 | SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LOUTR_MIXER, | |
1031 | M98090_MIXRCVR_MIC2_SHIFT, 1, 0), | |
1032 | }; | |
1033 | ||
1034 | static const char *linmod_mux_text[] = { "Left Only", "Left and Right" }; | |
1035 | ||
2907cbcc TI |
1036 | static SOC_ENUM_SINGLE_DECL(linmod_mux_enum, |
1037 | M98090_REG_LOUTR_MIXER, | |
1038 | M98090_LINMOD_SHIFT, | |
1039 | linmod_mux_text); | |
685e4215 JW |
1040 | |
1041 | static const struct snd_kcontrol_new max98090_linmod_mux = | |
1042 | SOC_DAPM_ENUM("LINMOD Mux", linmod_mux_enum); | |
1043 | ||
1044 | static const char *mixhpsel_mux_text[] = { "DAC Only", "HP Mixer" }; | |
1045 | ||
1046 | /* | |
1047 | * This is a mux as it selects the HP output, but to DAPM it is a Mixer enable | |
1048 | */ | |
2907cbcc TI |
1049 | static SOC_ENUM_SINGLE_DECL(mixhplsel_mux_enum, |
1050 | M98090_REG_HP_CONTROL, | |
1051 | M98090_MIXHPLSEL_SHIFT, | |
1052 | mixhpsel_mux_text); | |
685e4215 JW |
1053 | |
1054 | static const struct snd_kcontrol_new max98090_mixhplsel_mux = | |
1055 | SOC_DAPM_ENUM("MIXHPLSEL Mux", mixhplsel_mux_enum); | |
1056 | ||
2907cbcc TI |
1057 | static SOC_ENUM_SINGLE_DECL(mixhprsel_mux_enum, |
1058 | M98090_REG_HP_CONTROL, | |
1059 | M98090_MIXHPRSEL_SHIFT, | |
1060 | mixhpsel_mux_text); | |
685e4215 JW |
1061 | |
1062 | static const struct snd_kcontrol_new max98090_mixhprsel_mux = | |
1063 | SOC_DAPM_ENUM("MIXHPRSEL Mux", mixhprsel_mux_enum); | |
1064 | ||
1065 | static const struct snd_soc_dapm_widget max98090_dapm_widgets[] = { | |
685e4215 JW |
1066 | SND_SOC_DAPM_INPUT("MIC1"), |
1067 | SND_SOC_DAPM_INPUT("MIC2"), | |
1068 | SND_SOC_DAPM_INPUT("DMICL"), | |
1069 | SND_SOC_DAPM_INPUT("DMICR"), | |
1070 | SND_SOC_DAPM_INPUT("IN1"), | |
1071 | SND_SOC_DAPM_INPUT("IN2"), | |
1072 | SND_SOC_DAPM_INPUT("IN3"), | |
1073 | SND_SOC_DAPM_INPUT("IN4"), | |
1074 | SND_SOC_DAPM_INPUT("IN5"), | |
1075 | SND_SOC_DAPM_INPUT("IN6"), | |
1076 | SND_SOC_DAPM_INPUT("IN12"), | |
1077 | SND_SOC_DAPM_INPUT("IN34"), | |
1078 | SND_SOC_DAPM_INPUT("IN56"), | |
1079 | ||
1080 | SND_SOC_DAPM_SUPPLY("MICBIAS", M98090_REG_INPUT_ENABLE, | |
4b8a1ca4 | 1081 | M98090_MBEN_SHIFT, 0, NULL, 0), |
685e4215 JW |
1082 | SND_SOC_DAPM_SUPPLY("SHDN", M98090_REG_DEVICE_SHUTDOWN, |
1083 | M98090_SHDNN_SHIFT, 0, NULL, 0), | |
1084 | SND_SOC_DAPM_SUPPLY("SDIEN", M98090_REG_IO_CONFIGURATION, | |
4b8a1ca4 | 1085 | M98090_SDIEN_SHIFT, 0, NULL, 0), |
685e4215 | 1086 | SND_SOC_DAPM_SUPPLY("SDOEN", M98090_REG_IO_CONFIGURATION, |
4b8a1ca4 | 1087 | M98090_SDOEN_SHIFT, 0, NULL, 0), |
685e4215 | 1088 | SND_SOC_DAPM_SUPPLY("DMICL_ENA", M98090_REG_DIGITAL_MIC_ENABLE, |
4b8a1ca4 TBS |
1089 | M98090_DIGMICL_SHIFT, 0, max98090_shdn_event, |
1090 | SND_SOC_DAPM_POST_PMU), | |
685e4215 | 1091 | SND_SOC_DAPM_SUPPLY("DMICR_ENA", M98090_REG_DIGITAL_MIC_ENABLE, |
4b8a1ca4 TBS |
1092 | M98090_DIGMICR_SHIFT, 0, max98090_shdn_event, |
1093 | SND_SOC_DAPM_POST_PMU), | |
685e4215 | 1094 | SND_SOC_DAPM_SUPPLY("AHPF", M98090_REG_FILTER_CONFIG, |
4b8a1ca4 | 1095 | M98090_AHPF_SHIFT, 0, NULL, 0), |
685e4215 JW |
1096 | |
1097 | /* | |
1098 | * Note: Sysclk and misc power supplies are taken care of by SHDN | |
1099 | */ | |
1100 | ||
1101 | SND_SOC_DAPM_MUX("MIC1 Mux", SND_SOC_NOPM, | |
1102 | 0, 0, &max98090_mic1_mux), | |
1103 | ||
1104 | SND_SOC_DAPM_MUX("MIC2 Mux", SND_SOC_NOPM, | |
1105 | 0, 0, &max98090_mic2_mux), | |
1106 | ||
aae1137b | 1107 | SND_SOC_DAPM_MUX("DMIC Mux", SND_SOC_NOPM, 0, 0, &max98090_dmic_mux), |
fd5f940f | 1108 | |
685e4215 JW |
1109 | SND_SOC_DAPM_PGA_E("MIC1 Input", M98090_REG_MIC1_INPUT_LEVEL, |
1110 | M98090_MIC_PA1EN_SHIFT, 0, NULL, 0, max98090_micinput_event, | |
1111 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), | |
1112 | ||
1113 | SND_SOC_DAPM_PGA_E("MIC2 Input", M98090_REG_MIC2_INPUT_LEVEL, | |
1114 | M98090_MIC_PA2EN_SHIFT, 0, NULL, 0, max98090_micinput_event, | |
1115 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), | |
1116 | ||
1117 | SND_SOC_DAPM_MIXER("LINEA Mixer", SND_SOC_NOPM, 0, 0, | |
1118 | &max98090_linea_mixer_controls[0], | |
1119 | ARRAY_SIZE(max98090_linea_mixer_controls)), | |
1120 | ||
1121 | SND_SOC_DAPM_MIXER("LINEB Mixer", SND_SOC_NOPM, 0, 0, | |
1122 | &max98090_lineb_mixer_controls[0], | |
1123 | ARRAY_SIZE(max98090_lineb_mixer_controls)), | |
1124 | ||
4b8a1ca4 TBS |
1125 | SND_SOC_DAPM_PGA("LINEA Input", M98090_REG_INPUT_ENABLE, |
1126 | M98090_LINEAEN_SHIFT, 0, NULL, 0), | |
1127 | SND_SOC_DAPM_PGA("LINEB Input", M98090_REG_INPUT_ENABLE, | |
1128 | M98090_LINEBEN_SHIFT, 0, NULL, 0), | |
685e4215 JW |
1129 | |
1130 | SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0, | |
1131 | &max98090_left_adc_mixer_controls[0], | |
1132 | ARRAY_SIZE(max98090_left_adc_mixer_controls)), | |
1133 | ||
1134 | SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0, | |
1135 | &max98090_right_adc_mixer_controls[0], | |
1136 | ARRAY_SIZE(max98090_right_adc_mixer_controls)), | |
1137 | ||
e5b94083 | 1138 | SND_SOC_DAPM_ADC_E("ADCL", NULL, M98090_REG_INPUT_ENABLE, |
4b8a1ca4 TBS |
1139 | M98090_ADLEN_SHIFT, 0, max98090_shdn_event, |
1140 | SND_SOC_DAPM_POST_PMU), | |
e5b94083 | 1141 | SND_SOC_DAPM_ADC_E("ADCR", NULL, M98090_REG_INPUT_ENABLE, |
4b8a1ca4 TBS |
1142 | M98090_ADREN_SHIFT, 0, max98090_shdn_event, |
1143 | SND_SOC_DAPM_POST_PMU), | |
685e4215 JW |
1144 | |
1145 | SND_SOC_DAPM_AIF_OUT("AIFOUTL", "HiFi Capture", 0, | |
1146 | SND_SOC_NOPM, 0, 0), | |
1147 | SND_SOC_DAPM_AIF_OUT("AIFOUTR", "HiFi Capture", 1, | |
1148 | SND_SOC_NOPM, 0, 0), | |
1149 | ||
1150 | SND_SOC_DAPM_MUX("LBENL Mux", SND_SOC_NOPM, | |
1151 | 0, 0, &max98090_lbenl_mux), | |
1152 | ||
1153 | SND_SOC_DAPM_MUX("LBENR Mux", SND_SOC_NOPM, | |
1154 | 0, 0, &max98090_lbenr_mux), | |
1155 | ||
1156 | SND_SOC_DAPM_MUX("LTENL Mux", SND_SOC_NOPM, | |
1157 | 0, 0, &max98090_ltenl_mux), | |
1158 | ||
1159 | SND_SOC_DAPM_MUX("LTENR Mux", SND_SOC_NOPM, | |
1160 | 0, 0, &max98090_ltenr_mux), | |
1161 | ||
1162 | SND_SOC_DAPM_MUX("STENL Mux", SND_SOC_NOPM, | |
1163 | 0, 0, &max98090_stenl_mux), | |
1164 | ||
1165 | SND_SOC_DAPM_MUX("STENR Mux", SND_SOC_NOPM, | |
1166 | 0, 0, &max98090_stenr_mux), | |
1167 | ||
1168 | SND_SOC_DAPM_AIF_IN("AIFINL", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0), | |
1169 | SND_SOC_DAPM_AIF_IN("AIFINR", "HiFi Playback", 1, SND_SOC_NOPM, 0, 0), | |
1170 | ||
4b8a1ca4 TBS |
1171 | SND_SOC_DAPM_DAC("DACL", NULL, M98090_REG_OUTPUT_ENABLE, |
1172 | M98090_DALEN_SHIFT, 0), | |
1173 | SND_SOC_DAPM_DAC("DACR", NULL, M98090_REG_OUTPUT_ENABLE, | |
1174 | M98090_DAREN_SHIFT, 0), | |
685e4215 JW |
1175 | |
1176 | SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0, | |
1177 | &max98090_left_hp_mixer_controls[0], | |
1178 | ARRAY_SIZE(max98090_left_hp_mixer_controls)), | |
1179 | ||
1180 | SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0, | |
1181 | &max98090_right_hp_mixer_controls[0], | |
1182 | ARRAY_SIZE(max98090_right_hp_mixer_controls)), | |
1183 | ||
1184 | SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0, | |
1185 | &max98090_left_speaker_mixer_controls[0], | |
1186 | ARRAY_SIZE(max98090_left_speaker_mixer_controls)), | |
1187 | ||
1188 | SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0, | |
1189 | &max98090_right_speaker_mixer_controls[0], | |
1190 | ARRAY_SIZE(max98090_right_speaker_mixer_controls)), | |
1191 | ||
1192 | SND_SOC_DAPM_MIXER("Left Receiver Mixer", SND_SOC_NOPM, 0, 0, | |
1193 | &max98090_left_rcv_mixer_controls[0], | |
1194 | ARRAY_SIZE(max98090_left_rcv_mixer_controls)), | |
1195 | ||
1196 | SND_SOC_DAPM_MIXER("Right Receiver Mixer", SND_SOC_NOPM, 0, 0, | |
1197 | &max98090_right_rcv_mixer_controls[0], | |
1198 | ARRAY_SIZE(max98090_right_rcv_mixer_controls)), | |
1199 | ||
ecb2795c JH |
1200 | SND_SOC_DAPM_MUX("LINMOD Mux", SND_SOC_NOPM, 0, 0, |
1201 | &max98090_linmod_mux), | |
685e4215 | 1202 | |
ecb2795c JH |
1203 | SND_SOC_DAPM_MUX("MIXHPLSEL Mux", SND_SOC_NOPM, 0, 0, |
1204 | &max98090_mixhplsel_mux), | |
685e4215 | 1205 | |
ecb2795c JH |
1206 | SND_SOC_DAPM_MUX("MIXHPRSEL Mux", SND_SOC_NOPM, 0, 0, |
1207 | &max98090_mixhprsel_mux), | |
685e4215 | 1208 | |
4b8a1ca4 TBS |
1209 | SND_SOC_DAPM_PGA("HP Left Out", M98090_REG_OUTPUT_ENABLE, |
1210 | M98090_HPLEN_SHIFT, 0, NULL, 0), | |
1211 | SND_SOC_DAPM_PGA("HP Right Out", M98090_REG_OUTPUT_ENABLE, | |
1212 | M98090_HPREN_SHIFT, 0, NULL, 0), | |
1213 | ||
1214 | SND_SOC_DAPM_PGA("SPK Left Out", M98090_REG_OUTPUT_ENABLE, | |
1215 | M98090_SPLEN_SHIFT, 0, NULL, 0), | |
1216 | SND_SOC_DAPM_PGA("SPK Right Out", M98090_REG_OUTPUT_ENABLE, | |
1217 | M98090_SPREN_SHIFT, 0, NULL, 0), | |
1218 | ||
1219 | SND_SOC_DAPM_PGA("RCV Left Out", M98090_REG_OUTPUT_ENABLE, | |
1220 | M98090_RCVLEN_SHIFT, 0, NULL, 0), | |
1221 | SND_SOC_DAPM_PGA("RCV Right Out", M98090_REG_OUTPUT_ENABLE, | |
1222 | M98090_RCVREN_SHIFT, 0, NULL, 0), | |
685e4215 JW |
1223 | |
1224 | SND_SOC_DAPM_OUTPUT("HPL"), | |
1225 | SND_SOC_DAPM_OUTPUT("HPR"), | |
1226 | SND_SOC_DAPM_OUTPUT("SPKL"), | |
1227 | SND_SOC_DAPM_OUTPUT("SPKR"), | |
1228 | SND_SOC_DAPM_OUTPUT("RCVL"), | |
1229 | SND_SOC_DAPM_OUTPUT("RCVR"), | |
1230 | }; | |
1231 | ||
1232 | static const struct snd_soc_dapm_widget max98091_dapm_widgets[] = { | |
685e4215 JW |
1233 | SND_SOC_DAPM_INPUT("DMIC3"), |
1234 | SND_SOC_DAPM_INPUT("DMIC4"), | |
1235 | ||
1236 | SND_SOC_DAPM_SUPPLY("DMIC3_ENA", M98090_REG_DIGITAL_MIC_ENABLE, | |
4b8a1ca4 | 1237 | M98090_DIGMIC3_SHIFT, 0, NULL, 0), |
685e4215 | 1238 | SND_SOC_DAPM_SUPPLY("DMIC4_ENA", M98090_REG_DIGITAL_MIC_ENABLE, |
4b8a1ca4 | 1239 | M98090_DIGMIC4_SHIFT, 0, NULL, 0), |
685e4215 JW |
1240 | }; |
1241 | ||
1242 | static const struct snd_soc_dapm_route max98090_dapm_routes[] = { | |
685e4215 JW |
1243 | {"MIC1 Input", NULL, "MIC1"}, |
1244 | {"MIC2 Input", NULL, "MIC2"}, | |
1245 | ||
4cf703a7 JN |
1246 | {"DMICL", NULL, "DMICL_ENA"}, |
1247 | {"DMICL", NULL, "DMICR_ENA"}, | |
1248 | {"DMICR", NULL, "DMICL_ENA"}, | |
1249 | {"DMICR", NULL, "DMICR_ENA"}, | |
685e4215 JW |
1250 | {"DMICL", NULL, "AHPF"}, |
1251 | {"DMICR", NULL, "AHPF"}, | |
1252 | ||
1253 | /* MIC1 input mux */ | |
1254 | {"MIC1 Mux", "IN12", "IN12"}, | |
1255 | {"MIC1 Mux", "IN56", "IN56"}, | |
1256 | ||
1257 | /* MIC2 input mux */ | |
1258 | {"MIC2 Mux", "IN34", "IN34"}, | |
1259 | {"MIC2 Mux", "IN56", "IN56"}, | |
1260 | ||
1261 | {"MIC1 Input", NULL, "MIC1 Mux"}, | |
1262 | {"MIC2 Input", NULL, "MIC2 Mux"}, | |
1263 | ||
1264 | /* Left ADC input mixer */ | |
1265 | {"Left ADC Mixer", "IN12 Switch", "IN12"}, | |
1266 | {"Left ADC Mixer", "IN34 Switch", "IN34"}, | |
1267 | {"Left ADC Mixer", "IN56 Switch", "IN56"}, | |
1268 | {"Left ADC Mixer", "LINEA Switch", "LINEA Input"}, | |
1269 | {"Left ADC Mixer", "LINEB Switch", "LINEB Input"}, | |
1270 | {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1271 | {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1272 | ||
1273 | /* Right ADC input mixer */ | |
1274 | {"Right ADC Mixer", "IN12 Switch", "IN12"}, | |
1275 | {"Right ADC Mixer", "IN34 Switch", "IN34"}, | |
1276 | {"Right ADC Mixer", "IN56 Switch", "IN56"}, | |
1277 | {"Right ADC Mixer", "LINEA Switch", "LINEA Input"}, | |
1278 | {"Right ADC Mixer", "LINEB Switch", "LINEB Input"}, | |
1279 | {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1280 | {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1281 | ||
1282 | /* Line A input mixer */ | |
1283 | {"LINEA Mixer", "IN1 Switch", "IN1"}, | |
1284 | {"LINEA Mixer", "IN3 Switch", "IN3"}, | |
1285 | {"LINEA Mixer", "IN5 Switch", "IN5"}, | |
1286 | {"LINEA Mixer", "IN34 Switch", "IN34"}, | |
1287 | ||
1288 | /* Line B input mixer */ | |
1289 | {"LINEB Mixer", "IN2 Switch", "IN2"}, | |
1290 | {"LINEB Mixer", "IN4 Switch", "IN4"}, | |
1291 | {"LINEB Mixer", "IN6 Switch", "IN6"}, | |
1292 | {"LINEB Mixer", "IN56 Switch", "IN56"}, | |
1293 | ||
1294 | {"LINEA Input", NULL, "LINEA Mixer"}, | |
1295 | {"LINEB Input", NULL, "LINEB Mixer"}, | |
1296 | ||
1297 | /* Inputs */ | |
1298 | {"ADCL", NULL, "Left ADC Mixer"}, | |
1299 | {"ADCR", NULL, "Right ADC Mixer"}, | |
1300 | {"ADCL", NULL, "SHDN"}, | |
1301 | {"ADCR", NULL, "SHDN"}, | |
1302 | ||
fd5f940f AB |
1303 | {"DMIC Mux", "ADC", "ADCL"}, |
1304 | {"DMIC Mux", "ADC", "ADCR"}, | |
1305 | {"DMIC Mux", "DMIC", "DMICL"}, | |
1306 | {"DMIC Mux", "DMIC", "DMICR"}, | |
1307 | ||
1308 | {"LBENL Mux", "Normal", "DMIC Mux"}, | |
685e4215 | 1309 | {"LBENL Mux", "Loopback", "LTENL Mux"}, |
fd5f940f | 1310 | {"LBENR Mux", "Normal", "DMIC Mux"}, |
685e4215 JW |
1311 | {"LBENR Mux", "Loopback", "LTENR Mux"}, |
1312 | ||
1313 | {"AIFOUTL", NULL, "LBENL Mux"}, | |
1314 | {"AIFOUTR", NULL, "LBENR Mux"}, | |
1315 | {"AIFOUTL", NULL, "SHDN"}, | |
1316 | {"AIFOUTR", NULL, "SHDN"}, | |
1317 | {"AIFOUTL", NULL, "SDOEN"}, | |
1318 | {"AIFOUTR", NULL, "SDOEN"}, | |
1319 | ||
1320 | {"LTENL Mux", "Normal", "AIFINL"}, | |
1321 | {"LTENL Mux", "Loopthrough", "LBENL Mux"}, | |
1322 | {"LTENR Mux", "Normal", "AIFINR"}, | |
1323 | {"LTENR Mux", "Loopthrough", "LBENR Mux"}, | |
1324 | ||
1325 | {"DACL", NULL, "LTENL Mux"}, | |
1326 | {"DACR", NULL, "LTENR Mux"}, | |
1327 | ||
1328 | {"STENL Mux", "Sidetone Left", "ADCL"}, | |
1329 | {"STENL Mux", "Sidetone Left", "DMICL"}, | |
1330 | {"STENR Mux", "Sidetone Right", "ADCR"}, | |
1331 | {"STENR Mux", "Sidetone Right", "DMICR"}, | |
48826ee5 | 1332 | {"DACL", NULL, "STENL Mux"}, |
418382f2 | 1333 | {"DACR", NULL, "STENR Mux"}, |
685e4215 JW |
1334 | |
1335 | {"AIFINL", NULL, "SHDN"}, | |
1336 | {"AIFINR", NULL, "SHDN"}, | |
1337 | {"AIFINL", NULL, "SDIEN"}, | |
1338 | {"AIFINR", NULL, "SDIEN"}, | |
1339 | {"DACL", NULL, "SHDN"}, | |
1340 | {"DACR", NULL, "SHDN"}, | |
1341 | ||
1342 | /* Left headphone output mixer */ | |
1343 | {"Left Headphone Mixer", "Left DAC Switch", "DACL"}, | |
1344 | {"Left Headphone Mixer", "Right DAC Switch", "DACR"}, | |
1345 | {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1346 | {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1347 | {"Left Headphone Mixer", "LINEA Switch", "LINEA Input"}, | |
1348 | {"Left Headphone Mixer", "LINEB Switch", "LINEB Input"}, | |
1349 | ||
1350 | /* Right headphone output mixer */ | |
1351 | {"Right Headphone Mixer", "Left DAC Switch", "DACL"}, | |
1352 | {"Right Headphone Mixer", "Right DAC Switch", "DACR"}, | |
1353 | {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1354 | {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1355 | {"Right Headphone Mixer", "LINEA Switch", "LINEA Input"}, | |
1356 | {"Right Headphone Mixer", "LINEB Switch", "LINEB Input"}, | |
1357 | ||
1358 | /* Left speaker output mixer */ | |
1359 | {"Left Speaker Mixer", "Left DAC Switch", "DACL"}, | |
1360 | {"Left Speaker Mixer", "Right DAC Switch", "DACR"}, | |
1361 | {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1362 | {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1363 | {"Left Speaker Mixer", "LINEA Switch", "LINEA Input"}, | |
1364 | {"Left Speaker Mixer", "LINEB Switch", "LINEB Input"}, | |
1365 | ||
1366 | /* Right speaker output mixer */ | |
1367 | {"Right Speaker Mixer", "Left DAC Switch", "DACL"}, | |
1368 | {"Right Speaker Mixer", "Right DAC Switch", "DACR"}, | |
1369 | {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1370 | {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1371 | {"Right Speaker Mixer", "LINEA Switch", "LINEA Input"}, | |
1372 | {"Right Speaker Mixer", "LINEB Switch", "LINEB Input"}, | |
1373 | ||
1374 | /* Left Receiver output mixer */ | |
1375 | {"Left Receiver Mixer", "Left DAC Switch", "DACL"}, | |
1376 | {"Left Receiver Mixer", "Right DAC Switch", "DACR"}, | |
1377 | {"Left Receiver Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1378 | {"Left Receiver Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1379 | {"Left Receiver Mixer", "LINEA Switch", "LINEA Input"}, | |
1380 | {"Left Receiver Mixer", "LINEB Switch", "LINEB Input"}, | |
1381 | ||
1382 | /* Right Receiver output mixer */ | |
1383 | {"Right Receiver Mixer", "Left DAC Switch", "DACL"}, | |
1384 | {"Right Receiver Mixer", "Right DAC Switch", "DACR"}, | |
1385 | {"Right Receiver Mixer", "MIC1 Switch", "MIC1 Input"}, | |
1386 | {"Right Receiver Mixer", "MIC2 Switch", "MIC2 Input"}, | |
1387 | {"Right Receiver Mixer", "LINEA Switch", "LINEA Input"}, | |
1388 | {"Right Receiver Mixer", "LINEB Switch", "LINEB Input"}, | |
1389 | ||
1390 | {"MIXHPLSEL Mux", "HP Mixer", "Left Headphone Mixer"}, | |
1391 | ||
1392 | /* | |
1393 | * Disable this for lowest power if bypassing | |
1394 | * the DAC with an analog signal | |
1395 | */ | |
1396 | {"HP Left Out", NULL, "DACL"}, | |
1397 | {"HP Left Out", NULL, "MIXHPLSEL Mux"}, | |
1398 | ||
1399 | {"MIXHPRSEL Mux", "HP Mixer", "Right Headphone Mixer"}, | |
1400 | ||
1401 | /* | |
1402 | * Disable this for lowest power if bypassing | |
1403 | * the DAC with an analog signal | |
1404 | */ | |
1405 | {"HP Right Out", NULL, "DACR"}, | |
1406 | {"HP Right Out", NULL, "MIXHPRSEL Mux"}, | |
1407 | ||
1408 | {"SPK Left Out", NULL, "Left Speaker Mixer"}, | |
1409 | {"SPK Right Out", NULL, "Right Speaker Mixer"}, | |
1410 | {"RCV Left Out", NULL, "Left Receiver Mixer"}, | |
1411 | ||
1412 | {"LINMOD Mux", "Left and Right", "Right Receiver Mixer"}, | |
1413 | {"LINMOD Mux", "Left Only", "Left Receiver Mixer"}, | |
1414 | {"RCV Right Out", NULL, "LINMOD Mux"}, | |
1415 | ||
1416 | {"HPL", NULL, "HP Left Out"}, | |
1417 | {"HPR", NULL, "HP Right Out"}, | |
1418 | {"SPKL", NULL, "SPK Left Out"}, | |
1419 | {"SPKR", NULL, "SPK Right Out"}, | |
1420 | {"RCVL", NULL, "RCV Left Out"}, | |
1421 | {"RCVR", NULL, "RCV Right Out"}, | |
685e4215 JW |
1422 | }; |
1423 | ||
1424 | static const struct snd_soc_dapm_route max98091_dapm_routes[] = { | |
685e4215 JW |
1425 | /* DMIC inputs */ |
1426 | {"DMIC3", NULL, "DMIC3_ENA"}, | |
1427 | {"DMIC4", NULL, "DMIC4_ENA"}, | |
1428 | {"DMIC3", NULL, "AHPF"}, | |
1429 | {"DMIC4", NULL, "AHPF"}, | |
685e4215 JW |
1430 | }; |
1431 | ||
4c66b9d1 | 1432 | static int max98090_add_widgets(struct snd_soc_component *component) |
685e4215 | 1433 | { |
4c66b9d1 KM |
1434 | struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); |
1435 | struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); | |
685e4215 | 1436 | |
4c66b9d1 | 1437 | snd_soc_add_component_controls(component, max98090_snd_controls, |
685e4215 JW |
1438 | ARRAY_SIZE(max98090_snd_controls)); |
1439 | ||
1440 | if (max98090->devtype == MAX98091) { | |
4c66b9d1 | 1441 | snd_soc_add_component_controls(component, max98091_snd_controls, |
685e4215 JW |
1442 | ARRAY_SIZE(max98091_snd_controls)); |
1443 | } | |
1444 | ||
1445 | snd_soc_dapm_new_controls(dapm, max98090_dapm_widgets, | |
1446 | ARRAY_SIZE(max98090_dapm_widgets)); | |
1447 | ||
1448 | snd_soc_dapm_add_routes(dapm, max98090_dapm_routes, | |
1449 | ARRAY_SIZE(max98090_dapm_routes)); | |
1450 | ||
1451 | if (max98090->devtype == MAX98091) { | |
1452 | snd_soc_dapm_new_controls(dapm, max98091_dapm_widgets, | |
1453 | ARRAY_SIZE(max98091_dapm_widgets)); | |
1454 | ||
1455 | snd_soc_dapm_add_routes(dapm, max98091_dapm_routes, | |
1456 | ARRAY_SIZE(max98091_dapm_routes)); | |
685e4215 JW |
1457 | } |
1458 | ||
1459 | return 0; | |
1460 | } | |
1461 | ||
1462 | static const int pclk_rates[] = { | |
1463 | 12000000, 12000000, 13000000, 13000000, | |
1464 | 16000000, 16000000, 19200000, 19200000 | |
1465 | }; | |
1466 | ||
1467 | static const int lrclk_rates[] = { | |
1468 | 8000, 16000, 8000, 16000, | |
1469 | 8000, 16000, 8000, 16000 | |
1470 | }; | |
1471 | ||
1472 | static const int user_pclk_rates[] = { | |
2c81a10a | 1473 | 13000000, 13000000, 19200000, 19200000, |
685e4215 JW |
1474 | }; |
1475 | ||
1476 | static const int user_lrclk_rates[] = { | |
2c81a10a | 1477 | 44100, 48000, 44100, 48000, |
685e4215 JW |
1478 | }; |
1479 | ||
1480 | static const unsigned long long ni_value[] = { | |
2c81a10a | 1481 | 3528, 768, 441, 8 |
685e4215 JW |
1482 | }; |
1483 | ||
1484 | static const unsigned long long mi_value[] = { | |
2c81a10a | 1485 | 8125, 1625, 1500, 25 |
685e4215 JW |
1486 | }; |
1487 | ||
4c66b9d1 | 1488 | static void max98090_configure_bclk(struct snd_soc_component *component) |
685e4215 | 1489 | { |
4c66b9d1 | 1490 | struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); |
685e4215 JW |
1491 | unsigned long long ni; |
1492 | int i; | |
1493 | ||
1494 | if (!max98090->sysclk) { | |
4c66b9d1 | 1495 | dev_err(component->dev, "No SYSCLK configured\n"); |
685e4215 JW |
1496 | return; |
1497 | } | |
1498 | ||
1499 | if (!max98090->bclk || !max98090->lrclk) { | |
4c66b9d1 | 1500 | dev_err(component->dev, "No audio clocks configured\n"); |
685e4215 JW |
1501 | return; |
1502 | } | |
1503 | ||
1504 | /* Skip configuration when operating as slave */ | |
1227f601 | 1505 | if (!(snd_soc_component_read(component, M98090_REG_MASTER_MODE) & |
685e4215 JW |
1506 | M98090_MAS_MASK)) { |
1507 | return; | |
1508 | } | |
1509 | ||
1510 | /* Check for supported PCLK to LRCLK ratios */ | |
1511 | for (i = 0; i < ARRAY_SIZE(pclk_rates); i++) { | |
1512 | if ((pclk_rates[i] == max98090->sysclk) && | |
1513 | (lrclk_rates[i] == max98090->lrclk)) { | |
4c66b9d1 | 1514 | dev_dbg(component->dev, |
685e4215 JW |
1515 | "Found supported PCLK to LRCLK rates 0x%x\n", |
1516 | i + 0x8); | |
1517 | ||
4c66b9d1 | 1518 | snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE, |
685e4215 JW |
1519 | M98090_FREQ_MASK, |
1520 | (i + 0x8) << M98090_FREQ_SHIFT); | |
4c66b9d1 | 1521 | snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE, |
685e4215 JW |
1522 | M98090_USE_M1_MASK, 0); |
1523 | return; | |
1524 | } | |
1525 | } | |
1526 | ||
1527 | /* Check for user calculated MI and NI ratios */ | |
1528 | for (i = 0; i < ARRAY_SIZE(user_pclk_rates); i++) { | |
1529 | if ((user_pclk_rates[i] == max98090->sysclk) && | |
1530 | (user_lrclk_rates[i] == max98090->lrclk)) { | |
4c66b9d1 | 1531 | dev_dbg(component->dev, |
685e4215 | 1532 | "Found user supported PCLK to LRCLK rates\n"); |
4c66b9d1 | 1533 | dev_dbg(component->dev, "i %d ni %lld mi %lld\n", |
685e4215 JW |
1534 | i, ni_value[i], mi_value[i]); |
1535 | ||
4c66b9d1 | 1536 | snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE, |
685e4215 | 1537 | M98090_FREQ_MASK, 0); |
4c66b9d1 | 1538 | snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE, |
685e4215 JW |
1539 | M98090_USE_M1_MASK, |
1540 | 1 << M98090_USE_M1_SHIFT); | |
1541 | ||
4c66b9d1 | 1542 | snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_MSB, |
685e4215 | 1543 | (ni_value[i] >> 8) & 0x7F); |
4c66b9d1 | 1544 | snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_LSB, |
685e4215 | 1545 | ni_value[i] & 0xFF); |
4c66b9d1 | 1546 | snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_MI_MSB, |
685e4215 | 1547 | (mi_value[i] >> 8) & 0x7F); |
4c66b9d1 | 1548 | snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_MI_LSB, |
685e4215 JW |
1549 | mi_value[i] & 0xFF); |
1550 | ||
1551 | return; | |
1552 | } | |
1553 | } | |
1554 | ||
1555 | /* | |
1556 | * Calculate based on MI = 65536 (not as good as either method above) | |
1557 | */ | |
4c66b9d1 | 1558 | snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE, |
685e4215 | 1559 | M98090_FREQ_MASK, 0); |
4c66b9d1 | 1560 | snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE, |
685e4215 JW |
1561 | M98090_USE_M1_MASK, 0); |
1562 | ||
1563 | /* | |
1564 | * Configure NI when operating as master | |
1565 | * Note: There is a small, but significant audio quality improvement | |
1566 | * by calculating ni and mi. | |
1567 | */ | |
1568 | ni = 65536ULL * (max98090->lrclk < 50000 ? 96ULL : 48ULL) | |
1569 | * (unsigned long long int)max98090->lrclk; | |
1570 | do_div(ni, (unsigned long long int)max98090->sysclk); | |
4c66b9d1 KM |
1571 | dev_info(component->dev, "No better method found\n"); |
1572 | dev_info(component->dev, "Calculating ni %lld with mi 65536\n", ni); | |
1573 | snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_MSB, | |
685e4215 | 1574 | (ni >> 8) & 0x7F); |
4c66b9d1 | 1575 | snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_LSB, ni & 0xFF); |
685e4215 JW |
1576 | } |
1577 | ||
1578 | static int max98090_dai_set_fmt(struct snd_soc_dai *codec_dai, | |
1579 | unsigned int fmt) | |
1580 | { | |
4c66b9d1 KM |
1581 | struct snd_soc_component *component = codec_dai->component; |
1582 | struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); | |
685e4215 | 1583 | struct max98090_cdata *cdata; |
fb180283 | 1584 | u8 regval, tdm_regval; |
685e4215 JW |
1585 | |
1586 | max98090->dai_fmt = fmt; | |
1587 | cdata = &max98090->dai[0]; | |
1588 | ||
1589 | if (fmt != cdata->fmt) { | |
1590 | cdata->fmt = fmt; | |
1591 | ||
1592 | regval = 0; | |
fb180283 | 1593 | tdm_regval = 0; |
573a9a37 MB |
1594 | switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { |
1595 | case SND_SOC_DAIFMT_CBC_CFC: | |
1596 | /* Set to consumer mode PLL - MAS mode off */ | |
4c66b9d1 | 1597 | snd_soc_component_write(component, |
685e4215 | 1598 | M98090_REG_CLOCK_RATIO_NI_MSB, 0x00); |
4c66b9d1 | 1599 | snd_soc_component_write(component, |
685e4215 | 1600 | M98090_REG_CLOCK_RATIO_NI_LSB, 0x00); |
4c66b9d1 | 1601 | snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE, |
685e4215 | 1602 | M98090_USE_M1_MASK, 0); |
541423dd | 1603 | max98090->master = false; |
685e4215 | 1604 | break; |
573a9a37 MB |
1605 | case SND_SOC_DAIFMT_CBP_CFP: |
1606 | /* Set to provider mode */ | |
685e4215 JW |
1607 | if (max98090->tdm_slots == 4) { |
1608 | /* TDM */ | |
1609 | regval |= M98090_MAS_MASK | | |
1610 | M98090_BSEL_64; | |
1611 | } else if (max98090->tdm_slots == 3) { | |
1612 | /* TDM */ | |
1613 | regval |= M98090_MAS_MASK | | |
1614 | M98090_BSEL_48; | |
1615 | } else { | |
1616 | /* Few TDM slots, or No TDM */ | |
1617 | regval |= M98090_MAS_MASK | | |
1618 | M98090_BSEL_32; | |
1619 | } | |
541423dd | 1620 | max98090->master = true; |
685e4215 | 1621 | break; |
685e4215 | 1622 | default: |
4c66b9d1 | 1623 | dev_err(component->dev, "DAI clock mode unsupported"); |
685e4215 JW |
1624 | return -EINVAL; |
1625 | } | |
4c66b9d1 | 1626 | snd_soc_component_write(component, M98090_REG_MASTER_MODE, regval); |
685e4215 JW |
1627 | |
1628 | regval = 0; | |
1629 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1630 | case SND_SOC_DAIFMT_I2S: | |
1631 | regval |= M98090_DLY_MASK; | |
1632 | break; | |
1633 | case SND_SOC_DAIFMT_LEFT_J: | |
1634 | break; | |
1635 | case SND_SOC_DAIFMT_RIGHT_J: | |
1636 | regval |= M98090_RJ_MASK; | |
1637 | break; | |
1638 | case SND_SOC_DAIFMT_DSP_A: | |
fb180283 MK |
1639 | tdm_regval |= M98090_TDM_MASK; |
1640 | break; | |
685e4215 | 1641 | default: |
4c66b9d1 | 1642 | dev_err(component->dev, "DAI format unsupported"); |
685e4215 JW |
1643 | return -EINVAL; |
1644 | } | |
1645 | ||
1646 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1647 | case SND_SOC_DAIFMT_NB_NF: | |
1648 | break; | |
1649 | case SND_SOC_DAIFMT_NB_IF: | |
1650 | regval |= M98090_WCI_MASK; | |
1651 | break; | |
1652 | case SND_SOC_DAIFMT_IB_NF: | |
1653 | regval |= M98090_BCI_MASK; | |
1654 | break; | |
1655 | case SND_SOC_DAIFMT_IB_IF: | |
1656 | regval |= M98090_BCI_MASK|M98090_WCI_MASK; | |
1657 | break; | |
1658 | default: | |
4c66b9d1 | 1659 | dev_err(component->dev, "DAI invert mode unsupported"); |
685e4215 JW |
1660 | return -EINVAL; |
1661 | } | |
1662 | ||
1663 | /* | |
1664 | * This accommodates an inverted logic in the MAX98090 chip | |
1665 | * for Bit Clock Invert (BCI). The inverted logic is only | |
1666 | * seen for the case of TDM mode. The remaining cases have | |
1667 | * normal logic. | |
1668 | */ | |
fb180283 | 1669 | if (tdm_regval) |
685e4215 | 1670 | regval ^= M98090_BCI_MASK; |
685e4215 | 1671 | |
4c66b9d1 | 1672 | snd_soc_component_write(component, |
685e4215 | 1673 | M98090_REG_INTERFACE_FORMAT, regval); |
fb180283 MK |
1674 | |
1675 | regval = 0; | |
1676 | if (tdm_regval) | |
1677 | regval = max98090->tdm_lslot << M98090_TDM_SLOTL_SHIFT | | |
1678 | max98090->tdm_rslot << M98090_TDM_SLOTR_SHIFT | | |
1679 | 0 << M98090_TDM_SLOTDLY_SHIFT; | |
1680 | ||
1681 | snd_soc_component_write(component, M98090_REG_TDM_FORMAT, regval); | |
1682 | snd_soc_component_write(component, M98090_REG_TDM_CONTROL, tdm_regval); | |
685e4215 JW |
1683 | } |
1684 | ||
1685 | return 0; | |
1686 | } | |
1687 | ||
1688 | static int max98090_set_tdm_slot(struct snd_soc_dai *codec_dai, | |
1689 | unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width) | |
1690 | { | |
4c66b9d1 KM |
1691 | struct snd_soc_component *component = codec_dai->component; |
1692 | struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); | |
685e4215 JW |
1693 | |
1694 | if (slots < 0 || slots > 4) | |
1695 | return -EINVAL; | |
1696 | ||
fb180283 MK |
1697 | if (slot_width != 16) |
1698 | return -EINVAL; | |
685e4215 | 1699 | |
fb180283 MK |
1700 | if (rx_mask != tx_mask) |
1701 | return -EINVAL; | |
1702 | ||
1703 | if (!rx_mask) | |
1704 | return -EINVAL; | |
1705 | ||
1706 | max98090->tdm_slots = slots; | |
1707 | max98090->tdm_lslot = ffs(rx_mask) - 1; | |
1708 | max98090->tdm_rslot = fls(rx_mask) - 1; | |
685e4215 JW |
1709 | |
1710 | return 0; | |
1711 | } | |
1712 | ||
4c66b9d1 | 1713 | static int max98090_set_bias_level(struct snd_soc_component *component, |
685e4215 JW |
1714 | enum snd_soc_bias_level level) |
1715 | { | |
4c66b9d1 | 1716 | struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); |
685e4215 JW |
1717 | int ret; |
1718 | ||
1719 | switch (level) { | |
1720 | case SND_SOC_BIAS_ON: | |
685e4215 JW |
1721 | break; |
1722 | ||
1723 | case SND_SOC_BIAS_PREPARE: | |
b10ab7b8 TB |
1724 | /* |
1725 | * SND_SOC_BIAS_PREPARE is called while preparing for a | |
1726 | * transition to ON or away from ON. If current bias_level | |
1727 | * is SND_SOC_BIAS_ON, then it is preparing for a transition | |
1728 | * away from ON. Disable the clock in that case, otherwise | |
1729 | * enable it. | |
1730 | */ | |
29ca43bc LPC |
1731 | if (IS_ERR(max98090->mclk)) |
1732 | break; | |
1733 | ||
4c66b9d1 | 1734 | if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON) { |
29ca43bc | 1735 | clk_disable_unprepare(max98090->mclk); |
9acc7f08 FE |
1736 | } else { |
1737 | ret = clk_prepare_enable(max98090->mclk); | |
1738 | if (ret) | |
1739 | return ret; | |
1740 | } | |
685e4215 JW |
1741 | break; |
1742 | ||
1743 | case SND_SOC_BIAS_STANDBY: | |
4c66b9d1 | 1744 | if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { |
c42c8922 DR |
1745 | ret = regcache_sync(max98090->regmap); |
1746 | if (ret != 0) { | |
4c66b9d1 | 1747 | dev_err(component->dev, |
c42c8922 DR |
1748 | "Failed to sync cache: %d\n", ret); |
1749 | return ret; | |
1750 | } | |
1751 | } | |
1752 | break; | |
1753 | ||
685e4215 JW |
1754 | case SND_SOC_BIAS_OFF: |
1755 | /* Set internal pull-up to lowest power mode */ | |
4c66b9d1 | 1756 | snd_soc_component_update_bits(component, M98090_REG_JACK_DETECT, |
685e4215 JW |
1757 | M98090_JDWK_MASK, M98090_JDWK_MASK); |
1758 | regcache_mark_dirty(max98090->regmap); | |
1759 | break; | |
1760 | } | |
685e4215 JW |
1761 | return 0; |
1762 | } | |
1763 | ||
defcd98b | 1764 | static const int dmic_divisors[] = { 2, 3, 4, 5, 6, 8 }; |
685e4215 JW |
1765 | |
1766 | static const int comp_lrclk_rates[] = { | |
1767 | 8000, 16000, 32000, 44100, 48000, 96000 | |
1768 | }; | |
1769 | ||
defcd98b DR |
1770 | struct dmic_table { |
1771 | int pclk; | |
1772 | struct { | |
1773 | int freq; | |
1774 | int comp[6]; /* One each for 8, 16, 32, 44.1, 48, and 96 kHz */ | |
1775 | } settings[6]; /* One for each dmic divisor. */ | |
685e4215 JW |
1776 | }; |
1777 | ||
defcd98b DR |
1778 | static const struct dmic_table dmic_table[] = { /* One for each pclk freq. */ |
1779 | { | |
1780 | .pclk = 11289600, | |
1781 | .settings = { | |
1782 | { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } }, | |
1783 | { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } }, | |
1784 | { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, | |
1785 | { .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } }, | |
1786 | { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, | |
1787 | { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, | |
1788 | }, | |
1789 | }, | |
1790 | { | |
1791 | .pclk = 12000000, | |
1792 | .settings = { | |
1793 | { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } }, | |
1794 | { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } }, | |
1795 | { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, | |
1796 | { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } }, | |
1797 | { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, | |
1798 | { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, | |
1799 | } | |
1800 | }, | |
1801 | { | |
1802 | .pclk = 12288000, | |
1803 | .settings = { | |
1804 | { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } }, | |
1805 | { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } }, | |
1806 | { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, | |
1807 | { .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } }, | |
1808 | { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, | |
1809 | { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, | |
1810 | } | |
1811 | }, | |
1812 | { | |
1813 | .pclk = 13000000, | |
1814 | .settings = { | |
1815 | { .freq = 2, .comp = { 7, 8, 1, 1, 1, 1 } }, | |
1816 | { .freq = 1, .comp = { 7, 8, 0, 0, 0, 0 } }, | |
1817 | { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } }, | |
1818 | { .freq = 0, .comp = { 7, 8, 4, 4, 5, 5 } }, | |
1819 | { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } }, | |
1820 | { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } }, | |
1821 | } | |
1822 | }, | |
1823 | { | |
1824 | .pclk = 19200000, | |
1825 | .settings = { | |
1826 | { .freq = 2, .comp = { 0, 0, 0, 0, 0, 0 } }, | |
1827 | { .freq = 1, .comp = { 7, 8, 1, 1, 1, 1 } }, | |
1828 | { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } }, | |
1829 | { .freq = 0, .comp = { 7, 8, 2, 2, 3, 3 } }, | |
1830 | { .freq = 0, .comp = { 7, 8, 1, 1, 2, 2 } }, | |
1831 | { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } }, | |
1832 | } | |
1833 | }, | |
1834 | }; | |
1835 | ||
1836 | static int max98090_find_divisor(int target_freq, int pclk) | |
1837 | { | |
1838 | int current_diff = INT_MAX; | |
226a783f | 1839 | int test_diff; |
defcd98b DR |
1840 | int divisor_index = 0; |
1841 | int i; | |
1842 | ||
1843 | for (i = 0; i < ARRAY_SIZE(dmic_divisors); i++) { | |
1844 | test_diff = abs(target_freq - (pclk / dmic_divisors[i])); | |
1845 | if (test_diff < current_diff) { | |
1846 | current_diff = test_diff; | |
1847 | divisor_index = i; | |
1848 | } | |
1849 | } | |
1850 | ||
1851 | return divisor_index; | |
1852 | } | |
1853 | ||
1854 | static int max98090_find_closest_pclk(int pclk) | |
1855 | { | |
1856 | int m1; | |
1857 | int m2; | |
1858 | int i; | |
1859 | ||
1860 | for (i = 0; i < ARRAY_SIZE(dmic_table); i++) { | |
1861 | if (pclk == dmic_table[i].pclk) | |
1862 | return i; | |
1863 | if (pclk < dmic_table[i].pclk) { | |
1864 | if (i == 0) | |
1865 | return i; | |
1866 | m1 = pclk - dmic_table[i-1].pclk; | |
1867 | m2 = dmic_table[i].pclk - pclk; | |
1868 | if (m1 < m2) | |
1869 | return i - 1; | |
1870 | else | |
1871 | return i; | |
1872 | } | |
1873 | } | |
1874 | ||
1875 | return -EINVAL; | |
1876 | } | |
1877 | ||
1878 | static int max98090_configure_dmic(struct max98090_priv *max98090, | |
1879 | int target_dmic_clk, int pclk, int fs) | |
1880 | { | |
1881 | int micclk_index; | |
1882 | int pclk_index; | |
1883 | int dmic_freq; | |
1884 | int dmic_comp; | |
1885 | int i; | |
1886 | ||
1887 | pclk_index = max98090_find_closest_pclk(pclk); | |
1888 | if (pclk_index < 0) | |
1889 | return pclk_index; | |
1890 | ||
1891 | micclk_index = max98090_find_divisor(target_dmic_clk, pclk); | |
1892 | ||
1893 | for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) { | |
1894 | if (fs <= (comp_lrclk_rates[i] + comp_lrclk_rates[i+1]) / 2) | |
1895 | break; | |
1896 | } | |
1897 | ||
1898 | dmic_freq = dmic_table[pclk_index].settings[micclk_index].freq; | |
1899 | dmic_comp = dmic_table[pclk_index].settings[micclk_index].comp[i]; | |
1900 | ||
1901 | regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_ENABLE, | |
1902 | M98090_MICCLK_MASK, | |
1903 | micclk_index << M98090_MICCLK_SHIFT); | |
1904 | ||
1905 | regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_CONFIG, | |
1906 | M98090_DMIC_COMP_MASK | M98090_DMIC_FREQ_MASK, | |
1907 | dmic_comp << M98090_DMIC_COMP_SHIFT | | |
1908 | dmic_freq << M98090_DMIC_FREQ_SHIFT); | |
1909 | ||
1910 | return 0; | |
1911 | } | |
1912 | ||
5628c897 YHH |
1913 | static int max98090_dai_startup(struct snd_pcm_substream *substream, |
1914 | struct snd_soc_dai *dai) | |
1915 | { | |
1916 | struct snd_soc_component *component = dai->component; | |
1917 | struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); | |
1918 | unsigned int fmt = max98090->dai_fmt; | |
1919 | ||
1920 | /* Remove 24-bit format support if it is not in right justified mode. */ | |
1921 | if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_RIGHT_J) { | |
1922 | substream->runtime->hw.formats = SNDRV_PCM_FMTBIT_S16_LE; | |
1923 | snd_pcm_hw_constraint_msbits(substream->runtime, 0, 16, 16); | |
1924 | } | |
1925 | return 0; | |
1926 | } | |
1927 | ||
685e4215 JW |
1928 | static int max98090_dai_hw_params(struct snd_pcm_substream *substream, |
1929 | struct snd_pcm_hw_params *params, | |
1930 | struct snd_soc_dai *dai) | |
1931 | { | |
4c66b9d1 KM |
1932 | struct snd_soc_component *component = dai->component; |
1933 | struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); | |
685e4215 | 1934 | struct max98090_cdata *cdata; |
685e4215 JW |
1935 | |
1936 | cdata = &max98090->dai[0]; | |
1937 | max98090->bclk = snd_soc_params_to_bclk(params); | |
1938 | if (params_channels(params) == 1) | |
1939 | max98090->bclk *= 2; | |
1940 | ||
1941 | max98090->lrclk = params_rate(params); | |
1942 | ||
7821afc4 MB |
1943 | switch (params_width(params)) { |
1944 | case 16: | |
4c66b9d1 | 1945 | snd_soc_component_update_bits(component, M98090_REG_INTERFACE_FORMAT, |
685e4215 JW |
1946 | M98090_WS_MASK, 0); |
1947 | break; | |
1948 | default: | |
1949 | return -EINVAL; | |
1950 | } | |
1951 | ||
541423dd | 1952 | if (max98090->master) |
4c66b9d1 | 1953 | max98090_configure_bclk(component); |
685e4215 JW |
1954 | |
1955 | cdata->rate = max98090->lrclk; | |
1956 | ||
1957 | /* Update filter mode */ | |
1958 | if (max98090->lrclk < 24000) | |
4c66b9d1 | 1959 | snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG, |
685e4215 JW |
1960 | M98090_MODE_MASK, 0); |
1961 | else | |
4c66b9d1 | 1962 | snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG, |
685e4215 JW |
1963 | M98090_MODE_MASK, M98090_MODE_MASK); |
1964 | ||
1965 | /* Update sample rate mode */ | |
1966 | if (max98090->lrclk < 50000) | |
4c66b9d1 | 1967 | snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG, |
685e4215 JW |
1968 | M98090_DHF_MASK, 0); |
1969 | else | |
4c66b9d1 | 1970 | snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG, |
685e4215 JW |
1971 | M98090_DHF_MASK, M98090_DHF_MASK); |
1972 | ||
defcd98b DR |
1973 | max98090_configure_dmic(max98090, max98090->dmic_freq, max98090->pclk, |
1974 | max98090->lrclk); | |
685e4215 JW |
1975 | |
1976 | return 0; | |
1977 | } | |
1978 | ||
1979 | /* | |
1980 | * PLL / Sysclk | |
1981 | */ | |
1982 | static int max98090_dai_set_sysclk(struct snd_soc_dai *dai, | |
1983 | int clk_id, unsigned int freq, int dir) | |
1984 | { | |
4c66b9d1 KM |
1985 | struct snd_soc_component *component = dai->component; |
1986 | struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); | |
685e4215 JW |
1987 | |
1988 | /* Requested clock frequency is already setup */ | |
1989 | if (freq == max98090->sysclk) | |
1990 | return 0; | |
1991 | ||
b10ab7b8 TB |
1992 | if (!IS_ERR(max98090->mclk)) { |
1993 | freq = clk_round_rate(max98090->mclk, freq); | |
1994 | clk_set_rate(max98090->mclk, freq); | |
1995 | } | |
1996 | ||
685e4215 JW |
1997 | /* Setup clocks for slave mode, and using the PLL |
1998 | * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) | |
1999 | * 0x02 (when master clk is 20MHz to 40MHz).. | |
2000 | * 0x03 (when master clk is 40MHz to 60MHz).. | |
2001 | */ | |
ece509c1 | 2002 | if ((freq >= 10000000) && (freq <= 20000000)) { |
4c66b9d1 | 2003 | snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK, |
685e4215 | 2004 | M98090_PSCLK_DIV1); |
defcd98b | 2005 | max98090->pclk = freq; |
ece509c1 | 2006 | } else if ((freq > 20000000) && (freq <= 40000000)) { |
4c66b9d1 | 2007 | snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK, |
685e4215 | 2008 | M98090_PSCLK_DIV2); |
defcd98b | 2009 | max98090->pclk = freq >> 1; |
ece509c1 | 2010 | } else if ((freq > 40000000) && (freq <= 60000000)) { |
4c66b9d1 | 2011 | snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK, |
685e4215 | 2012 | M98090_PSCLK_DIV4); |
defcd98b | 2013 | max98090->pclk = freq >> 2; |
685e4215 | 2014 | } else { |
4c66b9d1 | 2015 | dev_err(component->dev, "Invalid master clock frequency\n"); |
685e4215 JW |
2016 | return -EINVAL; |
2017 | } | |
2018 | ||
2019 | max98090->sysclk = freq; | |
2020 | ||
685e4215 JW |
2021 | return 0; |
2022 | } | |
2023 | ||
18e028e2 KM |
2024 | static int max98090_dai_mute(struct snd_soc_dai *codec_dai, int mute, |
2025 | int direction) | |
685e4215 | 2026 | { |
4c66b9d1 | 2027 | struct snd_soc_component *component = codec_dai->component; |
685e4215 JW |
2028 | int regval; |
2029 | ||
2030 | regval = mute ? M98090_DVM_MASK : 0; | |
4c66b9d1 | 2031 | snd_soc_component_update_bits(component, M98090_REG_DAI_PLAYBACK_LEVEL, |
685e4215 JW |
2032 | M98090_DVM_MASK, regval); |
2033 | ||
2034 | return 0; | |
2035 | } | |
2036 | ||
b8a3ee82 JN |
2037 | static int max98090_dai_trigger(struct snd_pcm_substream *substream, int cmd, |
2038 | struct snd_soc_dai *dai) | |
2039 | { | |
4c66b9d1 KM |
2040 | struct snd_soc_component *component = dai->component; |
2041 | struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); | |
b8a3ee82 JN |
2042 | |
2043 | switch (cmd) { | |
2044 | case SNDRV_PCM_TRIGGER_START: | |
2045 | case SNDRV_PCM_TRIGGER_RESUME: | |
2046 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
5e518edd | 2047 | if (!max98090->master && snd_soc_dai_active(dai) == 1) |
b8a3ee82 JN |
2048 | queue_delayed_work(system_power_efficient_wq, |
2049 | &max98090->pll_det_enable_work, | |
2050 | msecs_to_jiffies(10)); | |
2051 | break; | |
2052 | case SNDRV_PCM_TRIGGER_STOP: | |
2053 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
2054 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
5e518edd | 2055 | if (!max98090->master && snd_soc_dai_active(dai) == 1) |
b8a3ee82 JN |
2056 | schedule_work(&max98090->pll_det_disable_work); |
2057 | break; | |
2058 | default: | |
2059 | break; | |
2060 | } | |
2061 | ||
2062 | return 0; | |
2063 | } | |
2064 | ||
2065 | static void max98090_pll_det_enable_work(struct work_struct *work) | |
2066 | { | |
2067 | struct max98090_priv *max98090 = | |
2068 | container_of(work, struct max98090_priv, | |
2069 | pll_det_enable_work.work); | |
4c66b9d1 | 2070 | struct snd_soc_component *component = max98090->component; |
b8a3ee82 JN |
2071 | unsigned int status, mask; |
2072 | ||
2073 | /* | |
2074 | * Clear status register in order to clear possibly already occurred | |
2075 | * PLL unlock. If PLL hasn't still locked, the status will be set | |
2076 | * again and PLL unlock interrupt will occur. | |
2077 | * Note this will clear all status bits | |
2078 | */ | |
2079 | regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status); | |
2080 | ||
2081 | /* | |
2082 | * Queue jack work in case jack state has just changed but handler | |
2083 | * hasn't run yet | |
2084 | */ | |
2085 | regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask); | |
2086 | status &= mask; | |
2087 | if (status & M98090_JDET_MASK) | |
2088 | queue_delayed_work(system_power_efficient_wq, | |
2089 | &max98090->jack_work, | |
2090 | msecs_to_jiffies(100)); | |
2091 | ||
2092 | /* Enable PLL unlock interrupt */ | |
4c66b9d1 | 2093 | snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S, |
b8a3ee82 JN |
2094 | M98090_IULK_MASK, |
2095 | 1 << M98090_IULK_SHIFT); | |
2096 | } | |
2097 | ||
2098 | static void max98090_pll_det_disable_work(struct work_struct *work) | |
2099 | { | |
2100 | struct max98090_priv *max98090 = | |
2101 | container_of(work, struct max98090_priv, pll_det_disable_work); | |
4c66b9d1 | 2102 | struct snd_soc_component *component = max98090->component; |
b8a3ee82 JN |
2103 | |
2104 | cancel_delayed_work_sync(&max98090->pll_det_enable_work); | |
2105 | ||
2106 | /* Disable PLL unlock interrupt */ | |
4c66b9d1 | 2107 | snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S, |
b8a3ee82 JN |
2108 | M98090_IULK_MASK, 0); |
2109 | } | |
2110 | ||
45dfbf56 | 2111 | static void max98090_pll_work(struct max98090_priv *max98090) |
b8a3ee82 | 2112 | { |
4c66b9d1 | 2113 | struct snd_soc_component *component = max98090->component; |
6f49919d TBS |
2114 | unsigned int pll; |
2115 | int i; | |
b8a3ee82 | 2116 | |
5e518edd | 2117 | if (!snd_soc_component_active(component)) |
b8a3ee82 JN |
2118 | return; |
2119 | ||
4c66b9d1 | 2120 | dev_info_ratelimited(component->dev, "PLL unlocked\n"); |
b8a3ee82 | 2121 | |
acb874a7 TBS |
2122 | /* |
2123 | * As the datasheet suggested, the maximum PLL lock time should be | |
2124 | * 7 msec. The workaround resets the codec softly by toggling SHDN | |
2125 | * off and on if PLL failed to lock for 10 msec. Notably, there is | |
2126 | * no suggested hold time for SHDN off. | |
2127 | */ | |
2128 | ||
b8a3ee82 | 2129 | /* Toggle shutdown OFF then ON */ |
4c66b9d1 | 2130 | snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN, |
b8a3ee82 | 2131 | M98090_SHDNN_MASK, 0); |
4c66b9d1 | 2132 | snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN, |
b8a3ee82 JN |
2133 | M98090_SHDNN_MASK, M98090_SHDNN_MASK); |
2134 | ||
6f49919d TBS |
2135 | for (i = 0; i < 10; ++i) { |
2136 | /* Give PLL time to lock */ | |
2137 | usleep_range(1000, 1200); | |
2138 | ||
2139 | /* Check lock status */ | |
1227f601 | 2140 | pll = snd_soc_component_read( |
6f49919d TBS |
2141 | component, M98090_REG_DEVICE_STATUS); |
2142 | if (!(pll & M98090_ULK_MASK)) | |
2143 | break; | |
2144 | } | |
b8a3ee82 JN |
2145 | } |
2146 | ||
685e4215 JW |
2147 | static void max98090_jack_work(struct work_struct *work) |
2148 | { | |
2149 | struct max98090_priv *max98090 = container_of(work, | |
2150 | struct max98090_priv, | |
2151 | jack_work.work); | |
4c66b9d1 | 2152 | struct snd_soc_component *component = max98090->component; |
685e4215 JW |
2153 | int status = 0; |
2154 | int reg; | |
2155 | ||
2156 | /* Read a second time */ | |
2157 | if (max98090->jack_state == M98090_JACK_STATE_NO_HEADSET) { | |
2158 | ||
2159 | /* Strong pull up allows mic detection */ | |
4c66b9d1 | 2160 | snd_soc_component_update_bits(component, M98090_REG_JACK_DETECT, |
685e4215 JW |
2161 | M98090_JDWK_MASK, 0); |
2162 | ||
2163 | msleep(50); | |
2164 | ||
221034ac | 2165 | snd_soc_component_read(component, M98090_REG_JACK_STATUS); |
685e4215 JW |
2166 | |
2167 | /* Weak pull up allows only insertion detection */ | |
4c66b9d1 | 2168 | snd_soc_component_update_bits(component, M98090_REG_JACK_DETECT, |
685e4215 | 2169 | M98090_JDWK_MASK, M98090_JDWK_MASK); |
685e4215 JW |
2170 | } |
2171 | ||
1227f601 | 2172 | reg = snd_soc_component_read(component, M98090_REG_JACK_STATUS); |
685e4215 JW |
2173 | |
2174 | switch (reg & (M98090_LSNS_MASK | M98090_JKSNS_MASK)) { | |
2175 | case M98090_LSNS_MASK | M98090_JKSNS_MASK: | |
4c66b9d1 | 2176 | dev_dbg(component->dev, "No Headset Detected\n"); |
685e4215 JW |
2177 | |
2178 | max98090->jack_state = M98090_JACK_STATE_NO_HEADSET; | |
2179 | ||
2180 | status |= 0; | |
2181 | ||
2182 | break; | |
2183 | ||
2184 | case 0: | |
2185 | if (max98090->jack_state == | |
2186 | M98090_JACK_STATE_HEADSET) { | |
2187 | ||
4c66b9d1 | 2188 | dev_dbg(component->dev, |
685e4215 JW |
2189 | "Headset Button Down Detected\n"); |
2190 | ||
2191 | /* | |
2192 | * max98090_headset_button_event(codec) | |
2193 | * could be defined, then called here. | |
2194 | */ | |
2195 | ||
2196 | status |= SND_JACK_HEADSET; | |
2197 | status |= SND_JACK_BTN_0; | |
2198 | ||
2199 | break; | |
2200 | } | |
2201 | ||
2202 | /* Line is reported as Headphone */ | |
2203 | /* Nokia Headset is reported as Headphone */ | |
2204 | /* Mono Headphone is reported as Headphone */ | |
4c66b9d1 | 2205 | dev_dbg(component->dev, "Headphone Detected\n"); |
685e4215 JW |
2206 | |
2207 | max98090->jack_state = M98090_JACK_STATE_HEADPHONE; | |
2208 | ||
2209 | status |= SND_JACK_HEADPHONE; | |
2210 | ||
2211 | break; | |
2212 | ||
2213 | case M98090_JKSNS_MASK: | |
4c66b9d1 | 2214 | dev_dbg(component->dev, "Headset Detected\n"); |
685e4215 JW |
2215 | |
2216 | max98090->jack_state = M98090_JACK_STATE_HEADSET; | |
2217 | ||
2218 | status |= SND_JACK_HEADSET; | |
2219 | ||
2220 | break; | |
2221 | ||
2222 | default: | |
4c66b9d1 | 2223 | dev_dbg(component->dev, "Unrecognized Jack Status\n"); |
685e4215 JW |
2224 | break; |
2225 | } | |
2226 | ||
2227 | snd_soc_jack_report(max98090->jack, status, | |
2228 | SND_JACK_HEADSET | SND_JACK_BTN_0); | |
685e4215 JW |
2229 | } |
2230 | ||
2231 | static irqreturn_t max98090_interrupt(int irq, void *data) | |
2232 | { | |
7a7f0ba0 | 2233 | struct max98090_priv *max98090 = data; |
4c66b9d1 | 2234 | struct snd_soc_component *component = max98090->component; |
685e4215 JW |
2235 | int ret; |
2236 | unsigned int mask; | |
2237 | unsigned int active; | |
2238 | ||
7a7f0ba0 | 2239 | /* Treat interrupt before codec is initialized as spurious */ |
4c66b9d1 | 2240 | if (component == NULL) |
7a7f0ba0 JN |
2241 | return IRQ_NONE; |
2242 | ||
4c66b9d1 | 2243 | dev_dbg(component->dev, "***** max98090_interrupt *****\n"); |
685e4215 JW |
2244 | |
2245 | ret = regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask); | |
2246 | ||
2247 | if (ret != 0) { | |
4c66b9d1 | 2248 | dev_err(component->dev, |
685e4215 JW |
2249 | "failed to read M98090_REG_INTERRUPT_S: %d\n", |
2250 | ret); | |
2251 | return IRQ_NONE; | |
2252 | } | |
2253 | ||
2254 | ret = regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &active); | |
2255 | ||
2256 | if (ret != 0) { | |
4c66b9d1 | 2257 | dev_err(component->dev, |
685e4215 JW |
2258 | "failed to read M98090_REG_DEVICE_STATUS: %d\n", |
2259 | ret); | |
2260 | return IRQ_NONE; | |
2261 | } | |
2262 | ||
4c66b9d1 | 2263 | dev_dbg(component->dev, "active=0x%02x mask=0x%02x -> active=0x%02x\n", |
685e4215 JW |
2264 | active, mask, active & mask); |
2265 | ||
2266 | active &= mask; | |
2267 | ||
2268 | if (!active) | |
2269 | return IRQ_NONE; | |
2270 | ||
959b6250 | 2271 | if (active & M98090_CLD_MASK) |
4c66b9d1 | 2272 | dev_err(component->dev, "M98090_CLD_MASK\n"); |
685e4215 | 2273 | |
959b6250 | 2274 | if (active & M98090_SLD_MASK) |
4c66b9d1 | 2275 | dev_dbg(component->dev, "M98090_SLD_MASK\n"); |
685e4215 | 2276 | |
b8a3ee82 | 2277 | if (active & M98090_ULK_MASK) { |
4c66b9d1 | 2278 | dev_dbg(component->dev, "M98090_ULK_MASK\n"); |
45dfbf56 | 2279 | max98090_pll_work(max98090); |
b8a3ee82 | 2280 | } |
685e4215 JW |
2281 | |
2282 | if (active & M98090_JDET_MASK) { | |
4c66b9d1 | 2283 | dev_dbg(component->dev, "M98090_JDET_MASK\n"); |
685e4215 | 2284 | |
4c66b9d1 | 2285 | pm_wakeup_event(component->dev, 100); |
685e4215 | 2286 | |
2df7c6aa MB |
2287 | queue_delayed_work(system_power_efficient_wq, |
2288 | &max98090->jack_work, | |
2289 | msecs_to_jiffies(100)); | |
685e4215 JW |
2290 | } |
2291 | ||
959b6250 | 2292 | if (active & M98090_DRCACT_MASK) |
4c66b9d1 | 2293 | dev_dbg(component->dev, "M98090_DRCACT_MASK\n"); |
685e4215 | 2294 | |
959b6250 | 2295 | if (active & M98090_DRCCLP_MASK) |
4c66b9d1 | 2296 | dev_err(component->dev, "M98090_DRCCLP_MASK\n"); |
685e4215 JW |
2297 | |
2298 | return IRQ_HANDLED; | |
2299 | } | |
2300 | ||
2301 | /** | |
2302 | * max98090_mic_detect - Enable microphone detection via the MAX98090 IRQ | |
2303 | * | |
4c66b9d1 | 2304 | * @component: MAX98090 component |
685e4215 JW |
2305 | * @jack: jack to report detection events on |
2306 | * | |
2307 | * Enable microphone detection via IRQ on the MAX98090. If GPIOs are | |
2308 | * being used to bring out signals to the processor then only platform | |
2309 | * data configuration is needed for MAX98090 and processor GPIOs should | |
2310 | * be configured using snd_soc_jack_add_gpios() instead. | |
2311 | * | |
2312 | * If no jack is supplied detection will be disabled. | |
2313 | */ | |
4c66b9d1 | 2314 | int max98090_mic_detect(struct snd_soc_component *component, |
685e4215 JW |
2315 | struct snd_soc_jack *jack) |
2316 | { | |
4c66b9d1 | 2317 | struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); |
685e4215 | 2318 | |
4c66b9d1 | 2319 | dev_dbg(component->dev, "max98090_mic_detect\n"); |
685e4215 JW |
2320 | |
2321 | max98090->jack = jack; | |
2322 | if (jack) { | |
4c66b9d1 | 2323 | snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S, |
685e4215 JW |
2324 | M98090_IJDET_MASK, |
2325 | 1 << M98090_IJDET_SHIFT); | |
2326 | } else { | |
4c66b9d1 | 2327 | snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S, |
685e4215 JW |
2328 | M98090_IJDET_MASK, |
2329 | 0); | |
2330 | } | |
2331 | ||
2332 | /* Send an initial empty report */ | |
2333 | snd_soc_jack_report(max98090->jack, 0, | |
2334 | SND_JACK_HEADSET | SND_JACK_BTN_0); | |
2335 | ||
2df7c6aa MB |
2336 | queue_delayed_work(system_power_efficient_wq, |
2337 | &max98090->jack_work, | |
2338 | msecs_to_jiffies(100)); | |
685e4215 JW |
2339 | |
2340 | return 0; | |
2341 | } | |
2342 | EXPORT_SYMBOL_GPL(max98090_mic_detect); | |
2343 | ||
2344 | #define MAX98090_RATES SNDRV_PCM_RATE_8000_96000 | |
2345 | #define MAX98090_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) | |
2346 | ||
64793047 | 2347 | static const struct snd_soc_dai_ops max98090_dai_ops = { |
5628c897 | 2348 | .startup = max98090_dai_startup, |
685e4215 JW |
2349 | .set_sysclk = max98090_dai_set_sysclk, |
2350 | .set_fmt = max98090_dai_set_fmt, | |
2351 | .set_tdm_slot = max98090_set_tdm_slot, | |
2352 | .hw_params = max98090_dai_hw_params, | |
18e028e2 | 2353 | .mute_stream = max98090_dai_mute, |
b8a3ee82 | 2354 | .trigger = max98090_dai_trigger, |
18e028e2 | 2355 | .no_capture_mute = 1, |
685e4215 JW |
2356 | }; |
2357 | ||
35ff1051 | 2358 | static struct snd_soc_dai_driver max98090_dai = { |
685e4215 JW |
2359 | .name = "HiFi", |
2360 | .playback = { | |
2361 | .stream_name = "HiFi Playback", | |
2362 | .channels_min = 2, | |
2363 | .channels_max = 2, | |
2364 | .rates = MAX98090_RATES, | |
2365 | .formats = MAX98090_FORMATS, | |
2366 | }, | |
2367 | .capture = { | |
2368 | .stream_name = "HiFi Capture", | |
2369 | .channels_min = 1, | |
2370 | .channels_max = 2, | |
2371 | .rates = MAX98090_RATES, | |
2372 | .formats = MAX98090_FORMATS, | |
2373 | }, | |
2374 | .ops = &max98090_dai_ops, | |
685e4215 JW |
2375 | }; |
2376 | ||
4c66b9d1 | 2377 | static int max98090_probe(struct snd_soc_component *component) |
685e4215 | 2378 | { |
4c66b9d1 | 2379 | struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); |
685e4215 | 2380 | struct max98090_cdata *cdata; |
978b641f | 2381 | enum max98090_type devtype; |
685e4215 | 2382 | int ret = 0; |
bb13f0e0 FY |
2383 | int err; |
2384 | unsigned int micbias; | |
685e4215 | 2385 | |
4c66b9d1 | 2386 | dev_dbg(component->dev, "max98090_probe\n"); |
685e4215 | 2387 | |
4c66b9d1 | 2388 | max98090->mclk = devm_clk_get(component->dev, "mclk"); |
b10ab7b8 TB |
2389 | if (PTR_ERR(max98090->mclk) == -EPROBE_DEFER) |
2390 | return -EPROBE_DEFER; | |
2391 | ||
4c66b9d1 | 2392 | max98090->component = component; |
685e4215 | 2393 | |
685e4215 JW |
2394 | /* Reset the codec, the DSP core, and disable all interrupts */ |
2395 | max98090_reset(max98090); | |
2396 | ||
2397 | /* Initialize private data */ | |
2398 | ||
2399 | max98090->sysclk = (unsigned)-1; | |
defcd98b | 2400 | max98090->pclk = (unsigned)-1; |
541423dd | 2401 | max98090->master = false; |
685e4215 JW |
2402 | |
2403 | cdata = &max98090->dai[0]; | |
2404 | cdata->rate = (unsigned)-1; | |
2405 | cdata->fmt = (unsigned)-1; | |
2406 | ||
2407 | max98090->lin_state = 0; | |
2408 | max98090->pa1en = 0; | |
2409 | max98090->pa2en = 0; | |
685e4215 | 2410 | |
fb180283 MK |
2411 | max98090->tdm_lslot = 0; |
2412 | max98090->tdm_rslot = 1; | |
2413 | ||
1227f601 | 2414 | ret = snd_soc_component_read(component, M98090_REG_REVISION_ID); |
685e4215 | 2415 | if (ret < 0) { |
4c66b9d1 | 2416 | dev_err(component->dev, "Failed to read device revision: %d\n", |
685e4215 JW |
2417 | ret); |
2418 | goto err_access; | |
2419 | } | |
2420 | ||
2421 | if ((ret >= M98090_REVA) && (ret <= M98090_REVA + 0x0f)) { | |
978b641f | 2422 | devtype = MAX98090; |
4c66b9d1 | 2423 | dev_info(component->dev, "MAX98090 REVID=0x%02x\n", ret); |
685e4215 | 2424 | } else if ((ret >= M98091_REVA) && (ret <= M98091_REVA + 0x0f)) { |
978b641f | 2425 | devtype = MAX98091; |
4c66b9d1 | 2426 | dev_info(component->dev, "MAX98091 REVID=0x%02x\n", ret); |
685e4215 | 2427 | } else { |
978b641f | 2428 | devtype = MAX98090; |
4c66b9d1 | 2429 | dev_err(component->dev, "Unrecognized revision 0x%02x\n", ret); |
685e4215 JW |
2430 | } |
2431 | ||
978b641f | 2432 | if (max98090->devtype != devtype) { |
4c66b9d1 | 2433 | dev_warn(component->dev, "Mismatch in DT specified CODEC type.\n"); |
978b641f TB |
2434 | max98090->devtype = devtype; |
2435 | } | |
2436 | ||
685e4215 JW |
2437 | max98090->jack_state = M98090_JACK_STATE_NO_HEADSET; |
2438 | ||
2439 | INIT_DELAYED_WORK(&max98090->jack_work, max98090_jack_work); | |
b8a3ee82 JN |
2440 | INIT_DELAYED_WORK(&max98090->pll_det_enable_work, |
2441 | max98090_pll_det_enable_work); | |
2442 | INIT_WORK(&max98090->pll_det_disable_work, | |
2443 | max98090_pll_det_disable_work); | |
685e4215 JW |
2444 | |
2445 | /* Enable jack detection */ | |
4c66b9d1 | 2446 | snd_soc_component_write(component, M98090_REG_JACK_DETECT, |
685e4215 JW |
2447 | M98090_JDETEN_MASK | M98090_JDEB_25MS); |
2448 | ||
685e4215 JW |
2449 | /* |
2450 | * Clear any old interrupts. | |
2451 | * An old interrupt ocurring prior to installing the ISR | |
2452 | * can keep a new interrupt from generating a trigger. | |
2453 | */ | |
1227f601 | 2454 | snd_soc_component_read(component, M98090_REG_DEVICE_STATUS); |
685e4215 | 2455 | |
4b8a1ca4 | 2456 | /* High Performance is default */ |
4c66b9d1 | 2457 | snd_soc_component_update_bits(component, M98090_REG_DAC_CONTROL, |
685e4215 JW |
2458 | M98090_DACHP_MASK, |
2459 | 1 << M98090_DACHP_SHIFT); | |
4c66b9d1 | 2460 | snd_soc_component_update_bits(component, M98090_REG_DAC_CONTROL, |
685e4215 JW |
2461 | M98090_PERFMODE_MASK, |
2462 | 0 << M98090_PERFMODE_SHIFT); | |
4c66b9d1 | 2463 | snd_soc_component_update_bits(component, M98090_REG_ADC_CONTROL, |
685e4215 JW |
2464 | M98090_ADCHP_MASK, |
2465 | 1 << M98090_ADCHP_SHIFT); | |
2466 | ||
4b8a1ca4 | 2467 | /* Turn on VCM bandgap reference */ |
4c66b9d1 | 2468 | snd_soc_component_write(component, M98090_REG_BIAS_CONTROL, |
685e4215 JW |
2469 | M98090_VCM_MODE_MASK); |
2470 | ||
4c66b9d1 | 2471 | err = device_property_read_u32(component->dev, "maxim,micbias", &micbias); |
bb13f0e0 FY |
2472 | if (err) { |
2473 | micbias = M98090_MBVSEL_2V8; | |
4c66b9d1 | 2474 | dev_info(component->dev, "use default 2.8v micbias\n"); |
1c445a42 | 2475 | } else if (micbias > M98090_MBVSEL_2V8) { |
4c66b9d1 | 2476 | dev_err(component->dev, "micbias out of range 0x%x\n", micbias); |
bb13f0e0 FY |
2477 | micbias = M98090_MBVSEL_2V8; |
2478 | } | |
2479 | ||
4c66b9d1 | 2480 | snd_soc_component_update_bits(component, M98090_REG_MIC_BIAS_VOLTAGE, |
bb13f0e0 | 2481 | M98090_MBVSEL_MASK, micbias); |
a735d992 | 2482 | |
4c66b9d1 | 2483 | max98090_add_widgets(component); |
685e4215 JW |
2484 | |
2485 | err_access: | |
2486 | return ret; | |
2487 | } | |
2488 | ||
4c66b9d1 | 2489 | static void max98090_remove(struct snd_soc_component *component) |
685e4215 | 2490 | { |
4c66b9d1 | 2491 | struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); |
685e4215 JW |
2492 | |
2493 | cancel_delayed_work_sync(&max98090->jack_work); | |
b8a3ee82 JN |
2494 | cancel_delayed_work_sync(&max98090->pll_det_enable_work); |
2495 | cancel_work_sync(&max98090->pll_det_disable_work); | |
4c66b9d1 | 2496 | max98090->component = NULL; |
685e4215 JW |
2497 | } |
2498 | ||
4b8a1ca4 TBS |
2499 | static void max98090_seq_notifier(struct snd_soc_component *component, |
2500 | enum snd_soc_dapm_type event, int subseq) | |
2501 | { | |
2502 | struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); | |
2503 | ||
2504 | if (max98090->shdn_pending) { | |
2505 | snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN, | |
2506 | M98090_SHDNN_MASK, 0); | |
2507 | msleep(40); | |
2508 | snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN, | |
2509 | M98090_SHDNN_MASK, M98090_SHDNN_MASK); | |
2510 | max98090->shdn_pending = false; | |
2511 | } | |
2512 | } | |
2513 | ||
4c66b9d1 KM |
2514 | static const struct snd_soc_component_driver soc_component_dev_max98090 = { |
2515 | .probe = max98090_probe, | |
2516 | .remove = max98090_remove, | |
4b8a1ca4 | 2517 | .seq_notifier = max98090_seq_notifier, |
4c66b9d1 KM |
2518 | .set_bias_level = max98090_set_bias_level, |
2519 | .idle_bias_on = 1, | |
2520 | .use_pmdown_time = 1, | |
2521 | .endianness = 1, | |
685e4215 JW |
2522 | }; |
2523 | ||
2524 | static const struct regmap_config max98090_regmap = { | |
2525 | .reg_bits = 8, | |
2526 | .val_bits = 8, | |
2527 | ||
2528 | .max_register = MAX98090_MAX_REGISTER, | |
2529 | .reg_defaults = max98090_reg, | |
2530 | .num_reg_defaults = ARRAY_SIZE(max98090_reg), | |
2531 | .volatile_reg = max98090_volatile_register, | |
2532 | .readable_reg = max98090_readable_register, | |
2533 | .cache_type = REGCACHE_RBTREE, | |
2534 | }; | |
2535 | ||
4ac8ebb6 SK |
2536 | static const struct i2c_device_id max98090_i2c_id[] = { |
2537 | { "max98090", MAX98090 }, | |
2538 | { "max98091", MAX98091 }, | |
2539 | { } | |
2540 | }; | |
2541 | MODULE_DEVICE_TABLE(i2c, max98090_i2c_id); | |
2542 | ||
2543 | static int max98090_i2c_probe(struct i2c_client *i2c) | |
685e4215 JW |
2544 | { |
2545 | struct max98090_priv *max98090; | |
70f29d38 JN |
2546 | const struct acpi_device_id *acpi_id; |
2547 | kernel_ulong_t driver_data = 0; | |
685e4215 JW |
2548 | int ret; |
2549 | ||
2550 | pr_debug("max98090_i2c_probe\n"); | |
2551 | ||
2552 | max98090 = devm_kzalloc(&i2c->dev, sizeof(struct max98090_priv), | |
2553 | GFP_KERNEL); | |
2554 | if (max98090 == NULL) | |
2555 | return -ENOMEM; | |
2556 | ||
70f29d38 JN |
2557 | if (ACPI_HANDLE(&i2c->dev)) { |
2558 | acpi_id = acpi_match_device(i2c->dev.driver->acpi_match_table, | |
2559 | &i2c->dev); | |
2560 | if (!acpi_id) { | |
2561 | dev_err(&i2c->dev, "No driver data\n"); | |
2562 | return -EINVAL; | |
2563 | } | |
2564 | driver_data = acpi_id->driver_data; | |
4ac8ebb6 SK |
2565 | } else { |
2566 | const struct i2c_device_id *i2c_id = | |
2567 | i2c_match_id(max98090_i2c_id, i2c); | |
70f29d38 JN |
2568 | driver_data = i2c_id->driver_data; |
2569 | } | |
2570 | ||
2571 | max98090->devtype = driver_data; | |
685e4215 | 2572 | i2c_set_clientdata(i2c, max98090); |
685e4215 | 2573 | max98090->pdata = i2c->dev.platform_data; |
685e4215 | 2574 | |
defcd98b DR |
2575 | ret = of_property_read_u32(i2c->dev.of_node, "maxim,dmic-freq", |
2576 | &max98090->dmic_freq); | |
2577 | if (ret < 0) | |
2578 | max98090->dmic_freq = MAX98090_DEFAULT_DMIC_FREQ; | |
2579 | ||
a3a6cc84 | 2580 | max98090->regmap = devm_regmap_init_i2c(i2c, &max98090_regmap); |
685e4215 JW |
2581 | if (IS_ERR(max98090->regmap)) { |
2582 | ret = PTR_ERR(max98090->regmap); | |
2583 | dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret); | |
2584 | goto err_enable; | |
2585 | } | |
2586 | ||
ced1933d | 2587 | ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, |
7a7f0ba0 JN |
2588 | max98090_interrupt, IRQF_TRIGGER_FALLING | IRQF_ONESHOT, |
2589 | "max98090_interrupt", max98090); | |
2590 | if (ret < 0) { | |
2591 | dev_err(&i2c->dev, "request_irq failed: %d\n", | |
2592 | ret); | |
2593 | return ret; | |
2594 | } | |
2595 | ||
4c66b9d1 | 2596 | ret = devm_snd_soc_register_component(&i2c->dev, |
35ff1051 KK |
2597 | &soc_component_dev_max98090, |
2598 | &max98090_dai, 1); | |
685e4215 JW |
2599 | err_enable: |
2600 | return ret; | |
2601 | } | |
2602 | ||
c6b424fe CW |
2603 | static void max98090_i2c_shutdown(struct i2c_client *i2c) |
2604 | { | |
2605 | struct max98090_priv *max98090 = dev_get_drvdata(&i2c->dev); | |
2606 | ||
2607 | /* | |
2608 | * Enable volume smoothing, disable zero cross. This will cause | |
2609 | * a quick 40ms ramp to mute on shutdown. | |
2610 | */ | |
2611 | regmap_write(max98090->regmap, | |
2612 | M98090_REG_LEVEL_CONTROL, M98090_VSENN_MASK); | |
2613 | regmap_write(max98090->regmap, | |
2614 | M98090_REG_DEVICE_SHUTDOWN, 0x00); | |
2615 | msleep(40); | |
2616 | } | |
2617 | ||
ed5c2f5f | 2618 | static void max98090_i2c_remove(struct i2c_client *client) |
685e4215 | 2619 | { |
c6b424fe | 2620 | max98090_i2c_shutdown(client); |
685e4215 JW |
2621 | } |
2622 | ||
641d334b | 2623 | #ifdef CONFIG_PM |
685e4215 JW |
2624 | static int max98090_runtime_resume(struct device *dev) |
2625 | { | |
2626 | struct max98090_priv *max98090 = dev_get_drvdata(dev); | |
2627 | ||
2628 | regcache_cache_only(max98090->regmap, false); | |
2629 | ||
25b4ab43 LG |
2630 | max98090_reset(max98090); |
2631 | ||
685e4215 JW |
2632 | regcache_sync(max98090->regmap); |
2633 | ||
2634 | return 0; | |
2635 | } | |
2636 | ||
2637 | static int max98090_runtime_suspend(struct device *dev) | |
2638 | { | |
2639 | struct max98090_priv *max98090 = dev_get_drvdata(dev); | |
2640 | ||
2641 | regcache_cache_only(max98090->regmap, true); | |
2642 | ||
2643 | return 0; | |
2644 | } | |
3722dc8e | 2645 | #endif |
685e4215 | 2646 | |
121eb444 | 2647 | #ifdef CONFIG_PM_SLEEP |
46b0e97d LG |
2648 | static int max98090_resume(struct device *dev) |
2649 | { | |
2650 | struct max98090_priv *max98090 = dev_get_drvdata(dev); | |
2651 | unsigned int status; | |
2652 | ||
f1c0bc91 LG |
2653 | regcache_mark_dirty(max98090->regmap); |
2654 | ||
46b0e97d LG |
2655 | max98090_reset(max98090); |
2656 | ||
2657 | /* clear IRQ status */ | |
2658 | regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status); | |
2659 | ||
2660 | regcache_sync(max98090->regmap); | |
2661 | ||
2662 | return 0; | |
2663 | } | |
46b0e97d LG |
2664 | #endif |
2665 | ||
3e12af7e | 2666 | static const struct dev_pm_ops max98090_pm = { |
685e4215 JW |
2667 | SET_RUNTIME_PM_OPS(max98090_runtime_suspend, |
2668 | max98090_runtime_resume, NULL) | |
d24a7063 | 2669 | SET_SYSTEM_SLEEP_PM_OPS(NULL, max98090_resume) |
685e4215 JW |
2670 | }; |
2671 | ||
ac792c0a | 2672 | #ifdef CONFIG_OF |
2951f93f SW |
2673 | static const struct of_device_id max98090_of_match[] = { |
2674 | { .compatible = "maxim,max98090", }, | |
053e69d5 | 2675 | { .compatible = "maxim,max98091", }, |
2951f93f SW |
2676 | { } |
2677 | }; | |
2678 | MODULE_DEVICE_TABLE(of, max98090_of_match); | |
ac792c0a | 2679 | #endif |
2951f93f | 2680 | |
70f29d38 | 2681 | #ifdef CONFIG_ACPI |
8610d09a | 2682 | static const struct acpi_device_id max98090_acpi_match[] = { |
70f29d38 JN |
2683 | { "193C9890", MAX98090 }, |
2684 | { } | |
2685 | }; | |
2686 | MODULE_DEVICE_TABLE(acpi, max98090_acpi_match); | |
2687 | #endif | |
2688 | ||
685e4215 JW |
2689 | static struct i2c_driver max98090_i2c_driver = { |
2690 | .driver = { | |
2691 | .name = "max98090", | |
685e4215 | 2692 | .pm = &max98090_pm, |
2951f93f | 2693 | .of_match_table = of_match_ptr(max98090_of_match), |
70f29d38 | 2694 | .acpi_match_table = ACPI_PTR(max98090_acpi_match), |
685e4215 | 2695 | }, |
9abcd240 | 2696 | .probe = max98090_i2c_probe, |
c6b424fe | 2697 | .shutdown = max98090_i2c_shutdown, |
685e4215 JW |
2698 | .remove = max98090_i2c_remove, |
2699 | .id_table = max98090_i2c_id, | |
2700 | }; | |
2701 | ||
2702 | module_i2c_driver(max98090_i2c_driver); | |
2703 | ||
2704 | MODULE_DESCRIPTION("ALSA SoC MAX98090 driver"); | |
2705 | MODULE_AUTHOR("Peter Hsiang, Jesse Marroqin, Jerry Wong"); | |
2706 | MODULE_LICENSE("GPL"); |