projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ASoC: codecs: lpass-tx-macro: add support for SM8550
[linux-block.git] / sound / soc / codecs / lpass-tx-macro.c
CommitLineData
c39667dd
SK		 1// SPDX-License-Identifier: GPL-2.0-only
2// Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
3
4#include <linux/module.h>
5#include <linux/init.h>
6#include <linux/clk.h>
7#include <linux/io.h>
8#include <linux/platform_device.h>
512864c4 9#include <linux/pm_runtime.h>
c39667dd
SK		 10#include <linux/regmap.h>
11#include <sound/soc.h>
12#include <sound/soc-dapm.h>
13#include <sound/tlv.h>
14#include <linux/of_clk.h>
15#include <linux/clk-provider.h>
16
9e3d83c5
SRM		 17#include "lpass-macro-common.h"
18
c39667dd
SK		 19#define CDC_TX_CLK_RST_CTRL_MCLK_CONTROL (0x0000)
20#define CDC_TX_MCLK_EN_MASK BIT(0)
21#define CDC_TX_MCLK_ENABLE BIT(0)
22#define CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL (0x0004)
23#define CDC_TX_FS_CNT_EN_MASK BIT(0)
24#define CDC_TX_FS_CNT_ENABLE BIT(0)
25#define CDC_TX_CLK_RST_CTRL_SWR_CONTROL (0x0008)
26#define CDC_TX_SWR_RESET_MASK BIT(1)
27#define CDC_TX_SWR_RESET_ENABLE BIT(1)
28#define CDC_TX_SWR_CLK_EN_MASK BIT(0)
29#define CDC_TX_SWR_CLK_ENABLE BIT(0)
30#define CDC_TX_TOP_CSR_TOP_CFG0 (0x0080)
31#define CDC_TX_TOP_CSR_ANC_CFG (0x0084)
32#define CDC_TX_TOP_CSR_SWR_CTRL (0x0088)
33#define CDC_TX_TOP_CSR_FREQ_MCLK (0x0090)
34#define CDC_TX_TOP_CSR_DEBUG_BUS (0x0094)
35#define CDC_TX_TOP_CSR_DEBUG_EN (0x0098)
36#define CDC_TX_TOP_CSR_TX_I2S_CTL (0x00A4)
37#define CDC_TX_TOP_CSR_I2S_CLK (0x00A8)
38#define CDC_TX_TOP_CSR_I2S_RESET (0x00AC)
39#define CDC_TX_TOP_CSR_SWR_DMICn_CTL(n) (0x00C0 + n * 0x4)
40#define CDC_TX_TOP_CSR_SWR_DMIC0_CTL (0x00C0)
41#define CDC_TX_SWR_DMIC_CLK_SEL_MASK GENMASK(3, 1)
42#define CDC_TX_TOP_CSR_SWR_DMIC1_CTL (0x00C4)
43#define CDC_TX_TOP_CSR_SWR_DMIC2_CTL (0x00C8)
44#define CDC_TX_TOP_CSR_SWR_DMIC3_CTL (0x00CC)
45#define CDC_TX_TOP_CSR_SWR_AMIC0_CTL (0x00D0)
46#define CDC_TX_TOP_CSR_SWR_AMIC1_CTL (0x00D4)
47#define CDC_TX_INP_MUX_ADC_MUXn_CFG0(n) (0x0100 + 0x8 * n)
48#define CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK GENMASK(3, 0)
710ccba0 49#define CDC_TX_MACRO_DMIC_MUX_SEL_MASK GENMASK(7, 4)
c39667dd
SK		 50#define CDC_TX_INP_MUX_ADC_MUX0_CFG0 (0x0100)
51#define CDC_TX_INP_MUX_ADC_MUXn_CFG1(n) (0x0104 + 0x8 * n)
52#define CDC_TX_INP_MUX_ADC_MUX0_CFG1 (0x0104)
53#define CDC_TX_INP_MUX_ADC_MUX1_CFG0 (0x0108)
54#define CDC_TX_INP_MUX_ADC_MUX1_CFG1 (0x010C)
55#define CDC_TX_INP_MUX_ADC_MUX2_CFG0 (0x0110)
56#define CDC_TX_INP_MUX_ADC_MUX2_CFG1 (0x0114)
57#define CDC_TX_INP_MUX_ADC_MUX3_CFG0 (0x0118)
58#define CDC_TX_INP_MUX_ADC_MUX3_CFG1 (0x011C)
59#define CDC_TX_INP_MUX_ADC_MUX4_CFG0 (0x0120)
60#define CDC_TX_INP_MUX_ADC_MUX4_CFG1 (0x0124)
61#define CDC_TX_INP_MUX_ADC_MUX5_CFG0 (0x0128)
62#define CDC_TX_INP_MUX_ADC_MUX5_CFG1 (0x012C)
63#define CDC_TX_INP_MUX_ADC_MUX6_CFG0 (0x0130)
64#define CDC_TX_INP_MUX_ADC_MUX6_CFG1 (0x0134)
65#define CDC_TX_INP_MUX_ADC_MUX7_CFG0 (0x0138)
66#define CDC_TX_INP_MUX_ADC_MUX7_CFG1 (0x013C)
67#define CDC_TX_ANC0_CLK_RESET_CTL (0x0200)
68#define CDC_TX_ANC0_MODE_1_CTL (0x0204)
69#define CDC_TX_ANC0_MODE_2_CTL (0x0208)
70#define CDC_TX_ANC0_FF_SHIFT (0x020C)
71#define CDC_TX_ANC0_FB_SHIFT (0x0210)
72#define CDC_TX_ANC0_LPF_FF_A_CTL (0x0214)
73#define CDC_TX_ANC0_LPF_FF_B_CTL (0x0218)
74#define CDC_TX_ANC0_LPF_FB_CTL (0x021C)
75#define CDC_TX_ANC0_SMLPF_CTL (0x0220)
76#define CDC_TX_ANC0_DCFLT_SHIFT_CTL (0x0224)
77#define CDC_TX_ANC0_IIR_ADAPT_CTL (0x0228)
78#define CDC_TX_ANC0_IIR_COEFF_1_CTL (0x022C)
79#define CDC_TX_ANC0_IIR_COEFF_2_CTL (0x0230)
80#define CDC_TX_ANC0_FF_A_GAIN_CTL (0x0234)
81#define CDC_TX_ANC0_FF_B_GAIN_CTL (0x0238)
82#define CDC_TX_ANC0_FB_GAIN_CTL (0x023C)
83#define CDC_TXn_TX_PATH_CTL(n) (0x0400 + 0x80 * n)
84#define CDC_TXn_PCM_RATE_MASK GENMASK(3, 0)
85#define CDC_TXn_PGA_MUTE_MASK BIT(4)
86#define CDC_TXn_CLK_EN_MASK BIT(5)
87#define CDC_TX0_TX_PATH_CTL (0x0400)
88#define CDC_TXn_TX_PATH_CFG0(n) (0x0404 + 0x80 * n)
89#define CDC_TX0_TX_PATH_CFG0 (0x0404)
90#define CDC_TXn_PH_EN_MASK BIT(0)
91#define CDC_TXn_ADC_MODE_MASK GENMASK(2, 1)
92#define CDC_TXn_HPF_CUT_FREQ_MASK GENMASK(6, 5)
93#define CDC_TXn_ADC_DMIC_SEL_MASK BIT(7)
94#define CDC_TX0_TX_PATH_CFG1 (0x0408)
95#define CDC_TXn_TX_VOL_CTL(n) (0x040C + 0x80 * n)
96#define CDC_TX0_TX_VOL_CTL (0x040C)
97#define CDC_TX0_TX_PATH_SEC0 (0x0410)
98#define CDC_TX0_TX_PATH_SEC1 (0x0414)
99#define CDC_TXn_TX_PATH_SEC2(n) (0x0418 + 0x80 * n)
100#define CDC_TXn_HPF_F_CHANGE_MASK BIT(1)
101#define CDC_TXn_HPF_ZERO_GATE_MASK BIT(0)
102#define CDC_TX0_TX_PATH_SEC2 (0x0418)
103#define CDC_TX0_TX_PATH_SEC3 (0x041C)
104#define CDC_TX0_TX_PATH_SEC4 (0x0420)
105#define CDC_TX0_TX_PATH_SEC5 (0x0424)
106#define CDC_TX0_TX_PATH_SEC6 (0x0428)
107#define CDC_TX0_TX_PATH_SEC7 (0x042C)
108#define CDC_TX0_MBHC_CTL_EN_MASK BIT(6)
109#define CDC_TX1_TX_PATH_CTL (0x0480)
110#define CDC_TX1_TX_PATH_CFG0 (0x0484)
111#define CDC_TX1_TX_PATH_CFG1 (0x0488)
112#define CDC_TX1_TX_VOL_CTL (0x048C)
113#define CDC_TX1_TX_PATH_SEC0 (0x0490)
114#define CDC_TX1_TX_PATH_SEC1 (0x0494)
115#define CDC_TX1_TX_PATH_SEC2 (0x0498)
116#define CDC_TX1_TX_PATH_SEC3 (0x049C)
117#define CDC_TX1_TX_PATH_SEC4 (0x04A0)
118#define CDC_TX1_TX_PATH_SEC5 (0x04A4)
119#define CDC_TX1_TX_PATH_SEC6 (0x04A8)
120#define CDC_TX2_TX_PATH_CTL (0x0500)
121#define CDC_TX2_TX_PATH_CFG0 (0x0504)
122#define CDC_TX2_TX_PATH_CFG1 (0x0508)
123#define CDC_TX2_TX_VOL_CTL (0x050C)
124#define CDC_TX2_TX_PATH_SEC0 (0x0510)
125#define CDC_TX2_TX_PATH_SEC1 (0x0514)
126#define CDC_TX2_TX_PATH_SEC2 (0x0518)
127#define CDC_TX2_TX_PATH_SEC3 (0x051C)
128#define CDC_TX2_TX_PATH_SEC4 (0x0520)
129#define CDC_TX2_TX_PATH_SEC5 (0x0524)
130#define CDC_TX2_TX_PATH_SEC6 (0x0528)
131#define CDC_TX3_TX_PATH_CTL (0x0580)
132#define CDC_TX3_TX_PATH_CFG0 (0x0584)
133#define CDC_TX3_TX_PATH_CFG1 (0x0588)
134#define CDC_TX3_TX_VOL_CTL (0x058C)
135#define CDC_TX3_TX_PATH_SEC0 (0x0590)
136#define CDC_TX3_TX_PATH_SEC1 (0x0594)
137#define CDC_TX3_TX_PATH_SEC2 (0x0598)
138#define CDC_TX3_TX_PATH_SEC3 (0x059C)
139#define CDC_TX3_TX_PATH_SEC4 (0x05A0)
140#define CDC_TX3_TX_PATH_SEC5 (0x05A4)
141#define CDC_TX3_TX_PATH_SEC6 (0x05A8)
142#define CDC_TX4_TX_PATH_CTL (0x0600)
143#define CDC_TX4_TX_PATH_CFG0 (0x0604)
144#define CDC_TX4_TX_PATH_CFG1 (0x0608)
145#define CDC_TX4_TX_VOL_CTL (0x060C)
146#define CDC_TX4_TX_PATH_SEC0 (0x0610)
147#define CDC_TX4_TX_PATH_SEC1 (0x0614)
148#define CDC_TX4_TX_PATH_SEC2 (0x0618)
149#define CDC_TX4_TX_PATH_SEC3 (0x061C)
150#define CDC_TX4_TX_PATH_SEC4 (0x0620)
151#define CDC_TX4_TX_PATH_SEC5 (0x0624)
152#define CDC_TX4_TX_PATH_SEC6 (0x0628)
153#define CDC_TX5_TX_PATH_CTL (0x0680)
154#define CDC_TX5_TX_PATH_CFG0 (0x0684)
155#define CDC_TX5_TX_PATH_CFG1 (0x0688)
156#define CDC_TX5_TX_VOL_CTL (0x068C)
157#define CDC_TX5_TX_PATH_SEC0 (0x0690)
158#define CDC_TX5_TX_PATH_SEC1 (0x0694)
159#define CDC_TX5_TX_PATH_SEC2 (0x0698)
160#define CDC_TX5_TX_PATH_SEC3 (0x069C)
161#define CDC_TX5_TX_PATH_SEC4 (0x06A0)
162#define CDC_TX5_TX_PATH_SEC5 (0x06A4)
163#define CDC_TX5_TX_PATH_SEC6 (0x06A8)
164#define CDC_TX6_TX_PATH_CTL (0x0700)
165#define CDC_TX6_TX_PATH_CFG0 (0x0704)
166#define CDC_TX6_TX_PATH_CFG1 (0x0708)
167#define CDC_TX6_TX_VOL_CTL (0x070C)
168#define CDC_TX6_TX_PATH_SEC0 (0x0710)
169#define CDC_TX6_TX_PATH_SEC1 (0x0714)
170#define CDC_TX6_TX_PATH_SEC2 (0x0718)
171#define CDC_TX6_TX_PATH_SEC3 (0x071C)
172#define CDC_TX6_TX_PATH_SEC4 (0x0720)
173#define CDC_TX6_TX_PATH_SEC5 (0x0724)
174#define CDC_TX6_TX_PATH_SEC6 (0x0728)
175#define CDC_TX7_TX_PATH_CTL (0x0780)
176#define CDC_TX7_TX_PATH_CFG0 (0x0784)
177#define CDC_TX7_TX_PATH_CFG1 (0x0788)
178#define CDC_TX7_TX_VOL_CTL (0x078C)
179#define CDC_TX7_TX_PATH_SEC0 (0x0790)
180#define CDC_TX7_TX_PATH_SEC1 (0x0794)
181#define CDC_TX7_TX_PATH_SEC2 (0x0798)
182#define CDC_TX7_TX_PATH_SEC3 (0x079C)
183#define CDC_TX7_TX_PATH_SEC4 (0x07A0)
184#define CDC_TX7_TX_PATH_SEC5 (0x07A4)
185#define CDC_TX7_TX_PATH_SEC6 (0x07A8)
186#define TX_MAX_OFFSET (0x07A8)
187
188#define TX_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
189 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
190 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
191#define TX_MACRO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
192 SNDRV_PCM_FMTBIT_S24_LE |\
193 SNDRV_PCM_FMTBIT_S24_3LE)
194
195#define CF_MIN_3DB_4HZ 0x0
196#define CF_MIN_3DB_75HZ 0x1
197#define CF_MIN_3DB_150HZ 0x2
198#define TX_ADC_MAX 5
199#define TX_ADC_TO_DMIC(n) ((n - TX_ADC_MAX)/2)
200#define NUM_DECIMATORS 8
201#define TX_NUM_CLKS_MAX 5
202#define TX_MACRO_DMIC_UNMUTE_DELAY_MS 40
203#define TX_MACRO_AMIC_UNMUTE_DELAY_MS 100
204#define TX_MACRO_DMIC_HPF_DELAY_MS 300
205#define TX_MACRO_AMIC_HPF_DELAY_MS 300
e7621434 206#define MCLK_FREQ 19200000
c39667dd
SK		 207
208enum {
209 TX_MACRO_AIF_INVALID = 0,
210 TX_MACRO_AIF1_CAP,
211 TX_MACRO_AIF2_CAP,
212 TX_MACRO_AIF3_CAP,
213 TX_MACRO_MAX_DAIS
214};
215
216enum {
217 TX_MACRO_DEC0,
218 TX_MACRO_DEC1,
219 TX_MACRO_DEC2,
220 TX_MACRO_DEC3,
221 TX_MACRO_DEC4,
222 TX_MACRO_DEC5,
223 TX_MACRO_DEC6,
224 TX_MACRO_DEC7,
225 TX_MACRO_DEC_MAX,
226};
227
228enum {
229 TX_MACRO_CLK_DIV_2,
230 TX_MACRO_CLK_DIV_3,
231 TX_MACRO_CLK_DIV_4,
232 TX_MACRO_CLK_DIV_6,
233 TX_MACRO_CLK_DIV_8,
234 TX_MACRO_CLK_DIV_16,
235};
236
237enum {
238 MSM_DMIC,
239 SWR_MIC,
240 ANC_FB_TUNE1
241};
242
243struct tx_mute_work {
244 struct tx_macro *tx;
e5e7e398 245 u8 decimator;
c39667dd
SK		 246 struct delayed_work dwork;
247};
248
249struct hpf_work {
250 struct tx_macro *tx;
251 u8 decimator;
252 u8 hpf_cut_off_freq;
253 struct delayed_work dwork;
254};
255
256struct tx_macro {
257 struct device *dev;
258 struct snd_soc_component *component;
259 struct hpf_work tx_hpf_work[NUM_DECIMATORS];
260 struct tx_mute_work tx_mute_dwork[NUM_DECIMATORS];
261 unsigned long active_ch_mask[TX_MACRO_MAX_DAIS];
262 unsigned long active_ch_cnt[TX_MACRO_MAX_DAIS];
1c6a7f52 263 int active_decimator[TX_MACRO_MAX_DAIS];
c39667dd 264 struct regmap *regmap;
512864c4
SK		 265 struct clk *mclk;
266 struct clk *npl;
267 struct clk *macro;
268 struct clk *dcodec;
269 struct clk *fsgen;
c39667dd
SK		 270 struct clk_hw hw;
271 bool dec_active[NUM_DECIMATORS];
c39667dd
SK		 272 int tx_mclk_users;
273 u16 dmic_clk_div;
274 bool bcs_enable;
275 int dec_mode[NUM_DECIMATORS];
9e3d83c5 276 struct lpass_macro *pds;
c39667dd
SK		 277 bool bcs_clk_en;
278};
279#define to_tx_macro(_hw) container_of(_hw, struct tx_macro, hw)
280
281static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
282
7b285c74 283static struct reg_default tx_defaults[] = {
c39667dd
SK		 284 /* TX Macro */
285 { CDC_TX_CLK_RST_CTRL_MCLK_CONTROL, 0x00 },
286 { CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00 },
287 { CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 0x00},
288 { CDC_TX_TOP_CSR_TOP_CFG0, 0x00},
289 { CDC_TX_TOP_CSR_ANC_CFG, 0x00},
290 { CDC_TX_TOP_CSR_SWR_CTRL, 0x00},
291 { CDC_TX_TOP_CSR_FREQ_MCLK, 0x00},
292 { CDC_TX_TOP_CSR_DEBUG_BUS, 0x00},
293 { CDC_TX_TOP_CSR_DEBUG_EN, 0x00},
294 { CDC_TX_TOP_CSR_TX_I2S_CTL, 0x0C},
295 { CDC_TX_TOP_CSR_I2S_CLK, 0x00},
296 { CDC_TX_TOP_CSR_I2S_RESET, 0x00},
297 { CDC_TX_TOP_CSR_SWR_DMIC0_CTL, 0x00},
298 { CDC_TX_TOP_CSR_SWR_DMIC1_CTL, 0x00},
299 { CDC_TX_TOP_CSR_SWR_DMIC2_CTL, 0x00},
300 { CDC_TX_TOP_CSR_SWR_DMIC3_CTL, 0x00},
301 { CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 0x00},
302 { CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 0x00},
303 { CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0x00},
304 { CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0x00},
305 { CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0x00},
306 { CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0x00},
307 { CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0x00},
308 { CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0x00},
309 { CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0x00},
310 { CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0x00},
311 { CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0x00},
312 { CDC_TX_INP_MUX_ADC_MUX4_CFG1, 0x00},
313 { CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0x00},
314 { CDC_TX_INP_MUX_ADC_MUX5_CFG1, 0x00},
315 { CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0x00},
316 { CDC_TX_INP_MUX_ADC_MUX6_CFG1, 0x00},
317 { CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0x00},
318 { CDC_TX_INP_MUX_ADC_MUX7_CFG1, 0x00},
319 { CDC_TX_ANC0_CLK_RESET_CTL, 0x00},
320 { CDC_TX_ANC0_MODE_1_CTL, 0x00},
321 { CDC_TX_ANC0_MODE_2_CTL, 0x00},
322 { CDC_TX_ANC0_FF_SHIFT, 0x00},
323 { CDC_TX_ANC0_FB_SHIFT, 0x00},
324 { CDC_TX_ANC0_LPF_FF_A_CTL, 0x00},
325 { CDC_TX_ANC0_LPF_FF_B_CTL, 0x00},
326 { CDC_TX_ANC0_LPF_FB_CTL, 0x00},
327 { CDC_TX_ANC0_SMLPF_CTL, 0x00},
328 { CDC_TX_ANC0_DCFLT_SHIFT_CTL, 0x00},
329 { CDC_TX_ANC0_IIR_ADAPT_CTL, 0x00},
330 { CDC_TX_ANC0_IIR_COEFF_1_CTL, 0x00},
331 { CDC_TX_ANC0_IIR_COEFF_2_CTL, 0x00},
332 { CDC_TX_ANC0_FF_A_GAIN_CTL, 0x00},
333 { CDC_TX_ANC0_FF_B_GAIN_CTL, 0x00},
334 { CDC_TX_ANC0_FB_GAIN_CTL, 0x00},
335 { CDC_TX0_TX_PATH_CTL, 0x04},
336 { CDC_TX0_TX_PATH_CFG0, 0x10},
337 { CDC_TX0_TX_PATH_CFG1, 0x0B},
338 { CDC_TX0_TX_VOL_CTL, 0x00},
339 { CDC_TX0_TX_PATH_SEC0, 0x00},
340 { CDC_TX0_TX_PATH_SEC1, 0x00},
341 { CDC_TX0_TX_PATH_SEC2, 0x01},
342 { CDC_TX0_TX_PATH_SEC3, 0x3C},
343 { CDC_TX0_TX_PATH_SEC4, 0x20},
344 { CDC_TX0_TX_PATH_SEC5, 0x00},
345 { CDC_TX0_TX_PATH_SEC6, 0x00},
346 { CDC_TX0_TX_PATH_SEC7, 0x25},
347 { CDC_TX1_TX_PATH_CTL, 0x04},
348 { CDC_TX1_TX_PATH_CFG0, 0x10},
349 { CDC_TX1_TX_PATH_CFG1, 0x0B},
350 { CDC_TX1_TX_VOL_CTL, 0x00},
351 { CDC_TX1_TX_PATH_SEC0, 0x00},
352 { CDC_TX1_TX_PATH_SEC1, 0x00},
353 { CDC_TX1_TX_PATH_SEC2, 0x01},
354 { CDC_TX1_TX_PATH_SEC3, 0x3C},
355 { CDC_TX1_TX_PATH_SEC4, 0x20},
356 { CDC_TX1_TX_PATH_SEC5, 0x00},
357 { CDC_TX1_TX_PATH_SEC6, 0x00},
358 { CDC_TX2_TX_PATH_CTL, 0x04},
359 { CDC_TX2_TX_PATH_CFG0, 0x10},
360 { CDC_TX2_TX_PATH_CFG1, 0x0B},
361 { CDC_TX2_TX_VOL_CTL, 0x00},
362 { CDC_TX2_TX_PATH_SEC0, 0x00},
363 { CDC_TX2_TX_PATH_SEC1, 0x00},
364 { CDC_TX2_TX_PATH_SEC2, 0x01},
365 { CDC_TX2_TX_PATH_SEC3, 0x3C},
366 { CDC_TX2_TX_PATH_SEC4, 0x20},
367 { CDC_TX2_TX_PATH_SEC5, 0x00},
368 { CDC_TX2_TX_PATH_SEC6, 0x00},
369 { CDC_TX3_TX_PATH_CTL, 0x04},
370 { CDC_TX3_TX_PATH_CFG0, 0x10},
371 { CDC_TX3_TX_PATH_CFG1, 0x0B},
372 { CDC_TX3_TX_VOL_CTL, 0x00},
373 { CDC_TX3_TX_PATH_SEC0, 0x00},
374 { CDC_TX3_TX_PATH_SEC1, 0x00},
375 { CDC_TX3_TX_PATH_SEC2, 0x01},
376 { CDC_TX3_TX_PATH_SEC3, 0x3C},
377 { CDC_TX3_TX_PATH_SEC4, 0x20},
378 { CDC_TX3_TX_PATH_SEC5, 0x00},
379 { CDC_TX3_TX_PATH_SEC6, 0x00},
380 { CDC_TX4_TX_PATH_CTL, 0x04},
381 { CDC_TX4_TX_PATH_CFG0, 0x10},
382 { CDC_TX4_TX_PATH_CFG1, 0x0B},
383 { CDC_TX4_TX_VOL_CTL, 0x00},
384 { CDC_TX4_TX_PATH_SEC0, 0x00},
385 { CDC_TX4_TX_PATH_SEC1, 0x00},
386 { CDC_TX4_TX_PATH_SEC2, 0x01},
387 { CDC_TX4_TX_PATH_SEC3, 0x3C},
388 { CDC_TX4_TX_PATH_SEC4, 0x20},
389 { CDC_TX4_TX_PATH_SEC5, 0x00},
390 { CDC_TX4_TX_PATH_SEC6, 0x00},
391 { CDC_TX5_TX_PATH_CTL, 0x04},
392 { CDC_TX5_TX_PATH_CFG0, 0x10},
393 { CDC_TX5_TX_PATH_CFG1, 0x0B},
394 { CDC_TX5_TX_VOL_CTL, 0x00},
395 { CDC_TX5_TX_PATH_SEC0, 0x00},
396 { CDC_TX5_TX_PATH_SEC1, 0x00},
397 { CDC_TX5_TX_PATH_SEC2, 0x01},
398 { CDC_TX5_TX_PATH_SEC3, 0x3C},
399 { CDC_TX5_TX_PATH_SEC4, 0x20},
400 { CDC_TX5_TX_PATH_SEC5, 0x00},
401 { CDC_TX5_TX_PATH_SEC6, 0x00},
402 { CDC_TX6_TX_PATH_CTL, 0x04},
403 { CDC_TX6_TX_PATH_CFG0, 0x10},
404 { CDC_TX6_TX_PATH_CFG1, 0x0B},
405 { CDC_TX6_TX_VOL_CTL, 0x00},
406 { CDC_TX6_TX_PATH_SEC0, 0x00},
407 { CDC_TX6_TX_PATH_SEC1, 0x00},
408 { CDC_TX6_TX_PATH_SEC2, 0x01},
409 { CDC_TX6_TX_PATH_SEC3, 0x3C},
410 { CDC_TX6_TX_PATH_SEC4, 0x20},
411 { CDC_TX6_TX_PATH_SEC5, 0x00},
412 { CDC_TX6_TX_PATH_SEC6, 0x00},
413 { CDC_TX7_TX_PATH_CTL, 0x04},
414 { CDC_TX7_TX_PATH_CFG0, 0x10},
415 { CDC_TX7_TX_PATH_CFG1, 0x0B},
416 { CDC_TX7_TX_VOL_CTL, 0x00},
417 { CDC_TX7_TX_PATH_SEC0, 0x00},
418 { CDC_TX7_TX_PATH_SEC1, 0x00},
419 { CDC_TX7_TX_PATH_SEC2, 0x01},
420 { CDC_TX7_TX_PATH_SEC3, 0x3C},
421 { CDC_TX7_TX_PATH_SEC4, 0x20},
422 { CDC_TX7_TX_PATH_SEC5, 0x00},
423 { CDC_TX7_TX_PATH_SEC6, 0x00},
424};
425
426static bool tx_is_volatile_register(struct device *dev, unsigned int reg)
427{
428 /* Update volatile list for tx/tx macros */
429 switch (reg) {
430 case CDC_TX_TOP_CSR_SWR_DMIC0_CTL:
431 case CDC_TX_TOP_CSR_SWR_DMIC1_CTL:
432 case CDC_TX_TOP_CSR_SWR_DMIC2_CTL:
433 case CDC_TX_TOP_CSR_SWR_DMIC3_CTL:
434 return true;
435 }
436 return false;
437}
438
439static bool tx_is_rw_register(struct device *dev, unsigned int reg)
440{
441 switch (reg) {
442 case CDC_TX_CLK_RST_CTRL_MCLK_CONTROL:
443 case CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL:
444 case CDC_TX_CLK_RST_CTRL_SWR_CONTROL:
445 case CDC_TX_TOP_CSR_TOP_CFG0:
446 case CDC_TX_TOP_CSR_ANC_CFG:
447 case CDC_TX_TOP_CSR_SWR_CTRL:
448 case CDC_TX_TOP_CSR_FREQ_MCLK:
449 case CDC_TX_TOP_CSR_DEBUG_BUS:
450 case CDC_TX_TOP_CSR_DEBUG_EN:
451 case CDC_TX_TOP_CSR_TX_I2S_CTL:
452 case CDC_TX_TOP_CSR_I2S_CLK:
453 case CDC_TX_TOP_CSR_I2S_RESET:
454 case CDC_TX_TOP_CSR_SWR_DMIC0_CTL:
455 case CDC_TX_TOP_CSR_SWR_DMIC1_CTL:
456 case CDC_TX_TOP_CSR_SWR_DMIC2_CTL:
457 case CDC_TX_TOP_CSR_SWR_DMIC3_CTL:
458 case CDC_TX_TOP_CSR_SWR_AMIC0_CTL:
459 case CDC_TX_TOP_CSR_SWR_AMIC1_CTL:
460 case CDC_TX_ANC0_CLK_RESET_CTL:
461 case CDC_TX_ANC0_MODE_1_CTL:
462 case CDC_TX_ANC0_MODE_2_CTL:
463 case CDC_TX_ANC0_FF_SHIFT:
464 case CDC_TX_ANC0_FB_SHIFT:
465 case CDC_TX_ANC0_LPF_FF_A_CTL:
466 case CDC_TX_ANC0_LPF_FF_B_CTL:
467 case CDC_TX_ANC0_LPF_FB_CTL:
468 case CDC_TX_ANC0_SMLPF_CTL:
469 case CDC_TX_ANC0_DCFLT_SHIFT_CTL:
470 case CDC_TX_ANC0_IIR_ADAPT_CTL:
471 case CDC_TX_ANC0_IIR_COEFF_1_CTL:
472 case CDC_TX_ANC0_IIR_COEFF_2_CTL:
473 case CDC_TX_ANC0_FF_A_GAIN_CTL:
474 case CDC_TX_ANC0_FF_B_GAIN_CTL:
475 case CDC_TX_ANC0_FB_GAIN_CTL:
476 case CDC_TX_INP_MUX_ADC_MUX0_CFG0:
477 case CDC_TX_INP_MUX_ADC_MUX0_CFG1:
478 case CDC_TX_INP_MUX_ADC_MUX1_CFG0:
479 case CDC_TX_INP_MUX_ADC_MUX1_CFG1:
480 case CDC_TX_INP_MUX_ADC_MUX2_CFG0:
481 case CDC_TX_INP_MUX_ADC_MUX2_CFG1:
482 case CDC_TX_INP_MUX_ADC_MUX3_CFG0:
483 case CDC_TX_INP_MUX_ADC_MUX3_CFG1:
484 case CDC_TX_INP_MUX_ADC_MUX4_CFG0:
485 case CDC_TX_INP_MUX_ADC_MUX4_CFG1:
486 case CDC_TX_INP_MUX_ADC_MUX5_CFG0:
487 case CDC_TX_INP_MUX_ADC_MUX5_CFG1:
488 case CDC_TX_INP_MUX_ADC_MUX6_CFG0:
489 case CDC_TX_INP_MUX_ADC_MUX6_CFG1:
490 case CDC_TX_INP_MUX_ADC_MUX7_CFG0:
491 case CDC_TX_INP_MUX_ADC_MUX7_CFG1:
492 case CDC_TX0_TX_PATH_CTL:
493 case CDC_TX0_TX_PATH_CFG0:
494 case CDC_TX0_TX_PATH_CFG1:
495 case CDC_TX0_TX_VOL_CTL:
496 case CDC_TX0_TX_PATH_SEC0:
497 case CDC_TX0_TX_PATH_SEC1:
498 case CDC_TX0_TX_PATH_SEC2:
499 case CDC_TX0_TX_PATH_SEC3:
500 case CDC_TX0_TX_PATH_SEC4:
501 case CDC_TX0_TX_PATH_SEC5:
502 case CDC_TX0_TX_PATH_SEC6:
503 case CDC_TX0_TX_PATH_SEC7:
504 case CDC_TX1_TX_PATH_CTL:
505 case CDC_TX1_TX_PATH_CFG0:
506 case CDC_TX1_TX_PATH_CFG1:
507 case CDC_TX1_TX_VOL_CTL:
508 case CDC_TX1_TX_PATH_SEC0:
509 case CDC_TX1_TX_PATH_SEC1:
510 case CDC_TX1_TX_PATH_SEC2:
511 case CDC_TX1_TX_PATH_SEC3:
512 case CDC_TX1_TX_PATH_SEC4:
513 case CDC_TX1_TX_PATH_SEC5:
514 case CDC_TX1_TX_PATH_SEC6:
515 case CDC_TX2_TX_PATH_CTL:
516 case CDC_TX2_TX_PATH_CFG0:
517 case CDC_TX2_TX_PATH_CFG1:
518 case CDC_TX2_TX_VOL_CTL:
519 case CDC_TX2_TX_PATH_SEC0:
520 case CDC_TX2_TX_PATH_SEC1:
521 case CDC_TX2_TX_PATH_SEC2:
522 case CDC_TX2_TX_PATH_SEC3:
523 case CDC_TX2_TX_PATH_SEC4:
524 case CDC_TX2_TX_PATH_SEC5:
525 case CDC_TX2_TX_PATH_SEC6:
526 case CDC_TX3_TX_PATH_CTL:
527 case CDC_TX3_TX_PATH_CFG0:
528 case CDC_TX3_TX_PATH_CFG1:
529 case CDC_TX3_TX_VOL_CTL:
530 case CDC_TX3_TX_PATH_SEC0:
531 case CDC_TX3_TX_PATH_SEC1:
532 case CDC_TX3_TX_PATH_SEC2:
533 case CDC_TX3_TX_PATH_SEC3:
534 case CDC_TX3_TX_PATH_SEC4:
535 case CDC_TX3_TX_PATH_SEC5:
536 case CDC_TX3_TX_PATH_SEC6:
537 case CDC_TX4_TX_PATH_CTL:
538 case CDC_TX4_TX_PATH_CFG0:
539 case CDC_TX4_TX_PATH_CFG1:
540 case CDC_TX4_TX_VOL_CTL:
541 case CDC_TX4_TX_PATH_SEC0:
542 case CDC_TX4_TX_PATH_SEC1:
543 case CDC_TX4_TX_PATH_SEC2:
544 case CDC_TX4_TX_PATH_SEC3:
545 case CDC_TX4_TX_PATH_SEC4:
546 case CDC_TX4_TX_PATH_SEC5:
547 case CDC_TX4_TX_PATH_SEC6:
548 case CDC_TX5_TX_PATH_CTL:
549 case CDC_TX5_TX_PATH_CFG0:
550 case CDC_TX5_TX_PATH_CFG1:
551 case CDC_TX5_TX_VOL_CTL:
552 case CDC_TX5_TX_PATH_SEC0:
553 case CDC_TX5_TX_PATH_SEC1:
554 case CDC_TX5_TX_PATH_SEC2:
555 case CDC_TX5_TX_PATH_SEC3:
556 case CDC_TX5_TX_PATH_SEC4:
557 case CDC_TX5_TX_PATH_SEC5:
558 case CDC_TX5_TX_PATH_SEC6:
559 case CDC_TX6_TX_PATH_CTL:
560 case CDC_TX6_TX_PATH_CFG0:
561 case CDC_TX6_TX_PATH_CFG1:
562 case CDC_TX6_TX_VOL_CTL:
563 case CDC_TX6_TX_PATH_SEC0:
564 case CDC_TX6_TX_PATH_SEC1:
565 case CDC_TX6_TX_PATH_SEC2:
566 case CDC_TX6_TX_PATH_SEC3:
567 case CDC_TX6_TX_PATH_SEC4:
568 case CDC_TX6_TX_PATH_SEC5:
569 case CDC_TX6_TX_PATH_SEC6:
570 case CDC_TX7_TX_PATH_CTL:
571 case CDC_TX7_TX_PATH_CFG0:
572 case CDC_TX7_TX_PATH_CFG1:
573 case CDC_TX7_TX_VOL_CTL:
574 case CDC_TX7_TX_PATH_SEC0:
575 case CDC_TX7_TX_PATH_SEC1:
576 case CDC_TX7_TX_PATH_SEC2:
577 case CDC_TX7_TX_PATH_SEC3:
578 case CDC_TX7_TX_PATH_SEC4:
579 case CDC_TX7_TX_PATH_SEC5:
580 case CDC_TX7_TX_PATH_SEC6:
581 return true;
582 }
583
584 return false;
585}
586
587static const struct regmap_config tx_regmap_config = {
588 .name = "tx_macro",
589 .reg_bits = 16,
590 .val_bits = 32,
591 .reg_stride = 4,
592 .cache_type = REGCACHE_FLAT,
593 .max_register = TX_MAX_OFFSET,
594 .reg_defaults = tx_defaults,
595 .num_reg_defaults = ARRAY_SIZE(tx_defaults),
596 .writeable_reg = tx_is_rw_register,
597 .volatile_reg = tx_is_volatile_register,
598 .readable_reg = tx_is_rw_register,
599};
600
601static int tx_macro_mclk_enable(struct tx_macro *tx,
602 bool mclk_enable)
603{
604 struct regmap *regmap = tx->regmap;
605
606 if (mclk_enable) {
607 if (tx->tx_mclk_users == 0) {
608 /* 9.6MHz MCLK, set value 0x00 if other frequency */
609 regmap_update_bits(regmap, CDC_TX_TOP_CSR_FREQ_MCLK, 0x01, 0x01);
610 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_MCLK_CONTROL,
611 CDC_TX_MCLK_EN_MASK,
612 CDC_TX_MCLK_ENABLE);
613 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL,
614 CDC_TX_FS_CNT_EN_MASK,
615 CDC_TX_FS_CNT_ENABLE);
616 regcache_mark_dirty(regmap);
617 regcache_sync(regmap);
618 }
619 tx->tx_mclk_users++;
620 } else {
621 if (tx->tx_mclk_users <= 0) {
622 dev_err(tx->dev, "clock already disabled\n");
623 tx->tx_mclk_users = 0;
624 goto exit;
625 }
626 tx->tx_mclk_users--;
627 if (tx->tx_mclk_users == 0) {
628 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL,
629 CDC_TX_FS_CNT_EN_MASK, 0x0);
630 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_MCLK_CONTROL,
631 CDC_TX_MCLK_EN_MASK, 0x0);
632 }
633 }
634exit:
635 return 0;
636}
637
e5e7e398 638static bool is_amic_enabled(struct snd_soc_component *component, u8 decimator)
c39667dd
SK		 639{
640 u16 adc_mux_reg, adc_reg, adc_n;
641
642 adc_mux_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG1(decimator);
643
644 if (snd_soc_component_read(component, adc_mux_reg) & SWR_MIC) {
645 adc_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG0(decimator);
646 adc_n = snd_soc_component_read_field(component, adc_reg,
647 CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK);
648 if (adc_n < TX_ADC_MAX)
649 return true;
650 }
651
652 return false;
653}
654
655static void tx_macro_tx_hpf_corner_freq_callback(struct work_struct *work)
656{
657 struct delayed_work *hpf_delayed_work;
658 struct hpf_work *hpf_work;
659 struct tx_macro *tx;
660 struct snd_soc_component *component;
661 u16 dec_cfg_reg, hpf_gate_reg;
662 u8 hpf_cut_off_freq;
663
664 hpf_delayed_work = to_delayed_work(work);
665 hpf_work = container_of(hpf_delayed_work, struct hpf_work, dwork);
666 tx = hpf_work->tx;
667 component = tx->component;
668 hpf_cut_off_freq = hpf_work->hpf_cut_off_freq;
669
670 dec_cfg_reg = CDC_TXn_TX_PATH_CFG0(hpf_work->decimator);
671 hpf_gate_reg = CDC_TXn_TX_PATH_SEC2(hpf_work->decimator);
672
673 if (is_amic_enabled(component, hpf_work->decimator)) {
674 snd_soc_component_write_field(component,
675 dec_cfg_reg,
676 CDC_TXn_HPF_CUT_FREQ_MASK,
677 hpf_cut_off_freq);
678 snd_soc_component_update_bits(component, hpf_gate_reg,
679 CDC_TXn_HPF_F_CHANGE_MASK |
680 CDC_TXn_HPF_ZERO_GATE_MASK,
681 0x02);
682 snd_soc_component_update_bits(component, hpf_gate_reg,
683 CDC_TXn_HPF_F_CHANGE_MASK |
684 CDC_TXn_HPF_ZERO_GATE_MASK,
685 0x01);
686 } else {
687 snd_soc_component_write_field(component, dec_cfg_reg,
688 CDC_TXn_HPF_CUT_FREQ_MASK,
689 hpf_cut_off_freq);
690 snd_soc_component_write_field(component, hpf_gate_reg,
691 CDC_TXn_HPF_F_CHANGE_MASK, 0x1);
692 /* Minimum 1 clk cycle delay is required as per HW spec */
693 usleep_range(1000, 1010);
694 snd_soc_component_write_field(component, hpf_gate_reg,
695 CDC_TXn_HPF_F_CHANGE_MASK, 0x0);
696 }
697}
698
699static void tx_macro_mute_update_callback(struct work_struct *work)
700{
701 struct tx_mute_work *tx_mute_dwork;
702 struct snd_soc_component *component;
703 struct tx_macro *tx;
704 struct delayed_work *delayed_work;
705 u8 decimator;
706
707 delayed_work = to_delayed_work(work);
708 tx_mute_dwork = container_of(delayed_work, struct tx_mute_work, dwork);
709 tx = tx_mute_dwork->tx;
710 component = tx->component;
711 decimator = tx_mute_dwork->decimator;
712
713 snd_soc_component_write_field(component, CDC_TXn_TX_PATH_CTL(decimator),
714 CDC_TXn_PGA_MUTE_MASK, 0x0);
715}
716
d207bdea
SK		 717static int tx_macro_mclk_event(struct snd_soc_dapm_widget *w,
718 struct snd_kcontrol *kcontrol, int event)
719{
720 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
721 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
722
723 switch (event) {
724 case SND_SOC_DAPM_PRE_PMU:
725 tx_macro_mclk_enable(tx, true);
726 break;
727 case SND_SOC_DAPM_POST_PMD:
728 tx_macro_mclk_enable(tx, false);
729 break;
730 default:
731 break;
732 }
733
734 return 0;
735}
736
737static int tx_macro_put_dec_enum(struct snd_kcontrol *kcontrol,
738 struct snd_ctl_elem_value *ucontrol)
739{
740 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
741 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
742 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
743 unsigned int val, dmic;
744 u16 mic_sel_reg;
745 u16 dmic_clk_reg;
746 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
747
748 val = ucontrol->value.enumerated.item[0];
749
750 switch (e->reg) {
751 case CDC_TX_INP_MUX_ADC_MUX0_CFG0:
752 mic_sel_reg = CDC_TX0_TX_PATH_CFG0;
753 break;
754 case CDC_TX_INP_MUX_ADC_MUX1_CFG0:
755 mic_sel_reg = CDC_TX1_TX_PATH_CFG0;
756 break;
757 case CDC_TX_INP_MUX_ADC_MUX2_CFG0:
758 mic_sel_reg = CDC_TX2_TX_PATH_CFG0;
759 break;
760 case CDC_TX_INP_MUX_ADC_MUX3_CFG0:
761 mic_sel_reg = CDC_TX3_TX_PATH_CFG0;
762 break;
763 case CDC_TX_INP_MUX_ADC_MUX4_CFG0:
764 mic_sel_reg = CDC_TX4_TX_PATH_CFG0;
765 break;
766 case CDC_TX_INP_MUX_ADC_MUX5_CFG0:
767 mic_sel_reg = CDC_TX5_TX_PATH_CFG0;
768 break;
769 case CDC_TX_INP_MUX_ADC_MUX6_CFG0:
770 mic_sel_reg = CDC_TX6_TX_PATH_CFG0;
771 break;
772 case CDC_TX_INP_MUX_ADC_MUX7_CFG0:
773 mic_sel_reg = CDC_TX7_TX_PATH_CFG0;
774 break;
775 }
776
777 if (val != 0) {
710ccba0
SK		 778 if (widget->shift) { /* MSM DMIC */
779 snd_soc_component_write_field(component, mic_sel_reg,
780 CDC_TXn_ADC_DMIC_SEL_MASK, 1);
781 } else if (val < 5) {
d207bdea
SK		 782 snd_soc_component_write_field(component, mic_sel_reg,
783 CDC_TXn_ADC_DMIC_SEL_MASK, 0);
784 } else {
785 snd_soc_component_write_field(component, mic_sel_reg,
786 CDC_TXn_ADC_DMIC_SEL_MASK, 1);
787 dmic = TX_ADC_TO_DMIC(val);
788 dmic_clk_reg = CDC_TX_TOP_CSR_SWR_DMICn_CTL(dmic);
789 snd_soc_component_write_field(component, dmic_clk_reg,
790 CDC_TX_SWR_DMIC_CLK_SEL_MASK,
791 tx->dmic_clk_div);
792 }
793 }
794
795 return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
796}
797
798static int tx_macro_tx_mixer_get(struct snd_kcontrol *kcontrol,
799 struct snd_ctl_elem_value *ucontrol)
800{
801 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
802 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
803 struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value;
804 u32 dai_id = widget->shift;
805 u32 dec_id = mc->shift;
806 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
807
808 if (test_bit(dec_id, &tx->active_ch_mask[dai_id]))
809 ucontrol->value.integer.value[0] = 1;
810 else
811 ucontrol->value.integer.value[0] = 0;
812
813 return 0;
814}
815
816static int tx_macro_tx_mixer_put(struct snd_kcontrol *kcontrol,
817 struct snd_ctl_elem_value *ucontrol)
818{
819 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
820 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
821 struct snd_soc_dapm_update *update = NULL;
822 struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value;
823 u32 dai_id = widget->shift;
824 u32 dec_id = mc->shift;
825 u32 enable = ucontrol->value.integer.value[0];
826 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
827
828 if (enable) {
c1057a08
SK		 829 if (tx->active_decimator[dai_id] == dec_id)
830 return 0;
831
d207bdea
SK		 832 set_bit(dec_id, &tx->active_ch_mask[dai_id]);
833 tx->active_ch_cnt[dai_id]++;
834 tx->active_decimator[dai_id] = dec_id;
835 } else {
c1057a08
SK		 836 if (tx->active_decimator[dai_id] == -1)
837 return 0;
838
d207bdea
SK		 839 tx->active_ch_cnt[dai_id]--;
840 clear_bit(dec_id, &tx->active_ch_mask[dai_id]);
841 tx->active_decimator[dai_id] = -1;
842 }
843 snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, update);
844
c1057a08 845 return 1;
d207bdea
SK		 846}
847
848static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w,
849 struct snd_kcontrol *kcontrol, int event)
850{
851 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
e5e7e398 852 u8 decimator;
d207bdea
SK		 853 u16 tx_vol_ctl_reg, dec_cfg_reg, hpf_gate_reg, tx_gain_ctl_reg;
854 u8 hpf_cut_off_freq;
855 int hpf_delay = TX_MACRO_DMIC_HPF_DELAY_MS;
856 int unmute_delay = TX_MACRO_DMIC_UNMUTE_DELAY_MS;
857 u16 adc_mux_reg, adc_reg, adc_n, dmic;
858 u16 dmic_clk_reg;
859 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
860
861 decimator = w->shift;
862 tx_vol_ctl_reg = CDC_TXn_TX_PATH_CTL(decimator);
863 hpf_gate_reg = CDC_TXn_TX_PATH_SEC2(decimator);
864 dec_cfg_reg = CDC_TXn_TX_PATH_CFG0(decimator);
865 tx_gain_ctl_reg = CDC_TXn_TX_VOL_CTL(decimator);
866
867 switch (event) {
868 case SND_SOC_DAPM_PRE_PMU:
869 adc_mux_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG1(decimator);
870 if (snd_soc_component_read(component, adc_mux_reg) & SWR_MIC) {
871 adc_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG0(decimator);
872 adc_n = snd_soc_component_read(component, adc_reg) &
873 CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK;
874 if (adc_n >= TX_ADC_MAX) {
875 dmic = TX_ADC_TO_DMIC(adc_n);
876 dmic_clk_reg = CDC_TX_TOP_CSR_SWR_DMICn_CTL(dmic);
877
878 snd_soc_component_write_field(component, dmic_clk_reg,
879 CDC_TX_SWR_DMIC_CLK_SEL_MASK,
880 tx->dmic_clk_div);
881 }
882 }
883 snd_soc_component_write_field(component, dec_cfg_reg,
884 CDC_TXn_ADC_MODE_MASK,
885 tx->dec_mode[decimator]);
886 /* Enable TX PGA Mute */
887 snd_soc_component_write_field(component, tx_vol_ctl_reg,
888 CDC_TXn_PGA_MUTE_MASK, 0x1);
889 break;
890 case SND_SOC_DAPM_POST_PMU:
891 snd_soc_component_write_field(component, tx_vol_ctl_reg,
892 CDC_TXn_CLK_EN_MASK, 0x1);
893 if (!is_amic_enabled(component, decimator)) {
894 snd_soc_component_update_bits(component, hpf_gate_reg, 0x01, 0x00);
895 /* Minimum 1 clk cycle delay is required as per HW spec */
896 usleep_range(1000, 1010);
897 }
898 hpf_cut_off_freq = snd_soc_component_read_field(component, dec_cfg_reg,
899 CDC_TXn_HPF_CUT_FREQ_MASK);
900
901 tx->tx_hpf_work[decimator].hpf_cut_off_freq =
902 hpf_cut_off_freq;
903
904 if (hpf_cut_off_freq != CF_MIN_3DB_150HZ)
905 snd_soc_component_write_field(component, dec_cfg_reg,
906 CDC_TXn_HPF_CUT_FREQ_MASK,
907 CF_MIN_3DB_150HZ);
908
909 if (is_amic_enabled(component, decimator)) {
910 hpf_delay = TX_MACRO_AMIC_HPF_DELAY_MS;
911 unmute_delay = TX_MACRO_AMIC_UNMUTE_DELAY_MS;
912 }
913 /* schedule work queue to Remove Mute */
914 queue_delayed_work(system_freezable_wq,
915 &tx->tx_mute_dwork[decimator].dwork,
916 msecs_to_jiffies(unmute_delay));
917 if (tx->tx_hpf_work[decimator].hpf_cut_off_freq != CF_MIN_3DB_150HZ) {
918 queue_delayed_work(system_freezable_wq,
919 &tx->tx_hpf_work[decimator].dwork,
920 msecs_to_jiffies(hpf_delay));
921 snd_soc_component_update_bits(component, hpf_gate_reg,
922 CDC_TXn_HPF_F_CHANGE_MASK |
923 CDC_TXn_HPF_ZERO_GATE_MASK,
924 0x02);
925 if (!is_amic_enabled(component, decimator))
926 snd_soc_component_update_bits(component, hpf_gate_reg,
927 CDC_TXn_HPF_F_CHANGE_MASK |
928 CDC_TXn_HPF_ZERO_GATE_MASK,
929 0x00);
930 snd_soc_component_update_bits(component, hpf_gate_reg,
931 CDC_TXn_HPF_F_CHANGE_MASK |
932 CDC_TXn_HPF_ZERO_GATE_MASK,
933 0x01);
934
935 /*
936 * 6ms delay is required as per HW spec
937 */
938 usleep_range(6000, 6010);
939 }
940 /* apply gain after decimator is enabled */
941 snd_soc_component_write(component, tx_gain_ctl_reg,
942 snd_soc_component_read(component,
943 tx_gain_ctl_reg));
944 if (tx->bcs_enable) {
945 snd_soc_component_update_bits(component, dec_cfg_reg,
946 0x01, 0x01);
947 tx->bcs_clk_en = true;
948 }
949 break;
950 case SND_SOC_DAPM_PRE_PMD:
951 hpf_cut_off_freq =
952 tx->tx_hpf_work[decimator].hpf_cut_off_freq;
953 snd_soc_component_write_field(component, tx_vol_ctl_reg,
954 CDC_TXn_PGA_MUTE_MASK, 0x1);
955 if (cancel_delayed_work_sync(
956 &tx->tx_hpf_work[decimator].dwork)) {
957 if (hpf_cut_off_freq != CF_MIN_3DB_150HZ) {
958 snd_soc_component_write_field(
959 component, dec_cfg_reg,
960 CDC_TXn_HPF_CUT_FREQ_MASK,
961 hpf_cut_off_freq);
962 if (is_amic_enabled(component, decimator))
963 snd_soc_component_update_bits(component,
964 hpf_gate_reg,
965 CDC_TXn_HPF_F_CHANGE_MASK |
966 CDC_TXn_HPF_ZERO_GATE_MASK,
967 0x02);
968 else
969 snd_soc_component_update_bits(component,
970 hpf_gate_reg,
971 CDC_TXn_HPF_F_CHANGE_MASK |
972 CDC_TXn_HPF_ZERO_GATE_MASK,
973 0x03);
974
975 /*
976 * Minimum 1 clk cycle delay is required
977 * as per HW spec
978 */
979 usleep_range(1000, 1010);
980 snd_soc_component_update_bits(component, hpf_gate_reg,
981 CDC_TXn_HPF_F_CHANGE_MASK |
982 CDC_TXn_HPF_ZERO_GATE_MASK,
983 0x1);
984 }
985 }
986 cancel_delayed_work_sync(&tx->tx_mute_dwork[decimator].dwork);
987 break;
988 case SND_SOC_DAPM_POST_PMD:
989 snd_soc_component_write_field(component, tx_vol_ctl_reg,
990 CDC_TXn_CLK_EN_MASK, 0x0);
991 snd_soc_component_write_field(component, dec_cfg_reg,
992 CDC_TXn_ADC_MODE_MASK, 0x0);
993 snd_soc_component_write_field(component, tx_vol_ctl_reg,
994 CDC_TXn_PGA_MUTE_MASK, 0x0);
995 if (tx->bcs_enable) {
996 snd_soc_component_write_field(component, dec_cfg_reg,
997 CDC_TXn_PH_EN_MASK, 0x0);
998 snd_soc_component_write_field(component,
999 CDC_TX0_TX_PATH_SEC7,
1000 CDC_TX0_MBHC_CTL_EN_MASK,
1001 0x0);
1002 tx->bcs_clk_en = false;
1003 }
1004 break;
1005 }
1006 return 0;
1007}
1008
c39667dd
SK		 1009static int tx_macro_dec_mode_get(struct snd_kcontrol *kcontrol,
1010 struct snd_ctl_elem_value *ucontrol)
1011{
1012 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1013 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1014 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1015 int path = e->shift_l;
1016
1017 ucontrol->value.integer.value[0] = tx->dec_mode[path];
1018
1019 return 0;
1020}
1021
1022static int tx_macro_dec_mode_put(struct snd_kcontrol *kcontrol,
1023 struct snd_ctl_elem_value *ucontrol)
1024{
1025 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1026 int value = ucontrol->value.integer.value[0];
1027 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1028 int path = e->shift_l;
1029 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1030
c1057a08
SK		 1031 if (tx->dec_mode[path] == value)
1032 return 0;
1033
c39667dd
SK		 1034 tx->dec_mode[path] = value;
1035
c1057a08 1036 return 1;
c39667dd
SK		 1037}
1038
1039static int tx_macro_get_bcs(struct snd_kcontrol *kcontrol,
1040 struct snd_ctl_elem_value *ucontrol)
1041{
1042 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1043 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1044
1045 ucontrol->value.integer.value[0] = tx->bcs_enable;
1046
1047 return 0;
1048}
1049
1050static int tx_macro_set_bcs(struct snd_kcontrol *kcontrol,
1051 struct snd_ctl_elem_value *ucontrol)
1052{
1053 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1054 int value = ucontrol->value.integer.value[0];
1055 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1056
1057 tx->bcs_enable = value;
1058
1059 return 0;
1060}
1061
1062static int tx_macro_hw_params(struct snd_pcm_substream *substream,
1063 struct snd_pcm_hw_params *params,
1064 struct snd_soc_dai *dai)
1065{
1066 struct snd_soc_component *component = dai->component;
e5e7e398
RVVR		 1067 u32 sample_rate;
1068 u8 decimator;
c39667dd
SK		 1069 int tx_fs_rate;
1070 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1071
1072 sample_rate = params_rate(params);
1073 switch (sample_rate) {
1074 case 8000:
1075 tx_fs_rate = 0;
1076 break;
1077 case 16000:
1078 tx_fs_rate = 1;
1079 break;
1080 case 32000:
1081 tx_fs_rate = 3;
1082 break;
1083 case 48000:
1084 tx_fs_rate = 4;
1085 break;
1086 case 96000:
1087 tx_fs_rate = 5;
1088 break;
1089 case 192000:
1090 tx_fs_rate = 6;
1091 break;
1092 case 384000:
1093 tx_fs_rate = 7;
1094 break;
1095 default:
1096 dev_err(component->dev, "%s: Invalid TX sample rate: %d\n",
1097 __func__, params_rate(params));
1098 return -EINVAL;
1099 }
1100
1101 for_each_set_bit(decimator, &tx->active_ch_mask[dai->id], TX_MACRO_DEC_MAX)
1102 snd_soc_component_update_bits(component, CDC_TXn_TX_PATH_CTL(decimator),
1103 CDC_TXn_PCM_RATE_MASK,
1104 tx_fs_rate);
1105 return 0;
1106}
1107
1108static int tx_macro_get_channel_map(struct snd_soc_dai *dai,
1109 unsigned int *tx_num, unsigned int *tx_slot,
1110 unsigned int *rx_num, unsigned int *rx_slot)
1111{
1112 struct snd_soc_component *component = dai->component;
1113 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1114
1115 switch (dai->id) {
1116 case TX_MACRO_AIF1_CAP:
1117 case TX_MACRO_AIF2_CAP:
1118 case TX_MACRO_AIF3_CAP:
1119 *tx_slot = tx->active_ch_mask[dai->id];
1120 *tx_num = tx->active_ch_cnt[dai->id];
1121 break;
1122 default:
1123 break;
1124 }
1125 return 0;
1126}
1127
1128static int tx_macro_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
1129{
1130 struct snd_soc_component *component = dai->component;
1131 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
e5e7e398 1132 u8 decimator;
c39667dd 1133
1c6a7f52
SK		 1134 /* active decimator not set yet */
1135 if (tx->active_decimator[dai->id] == -1)
1136 return 0;
1137
c39667dd
SK		 1138 decimator = tx->active_decimator[dai->id];
1139
1140 if (mute)
1141 snd_soc_component_write_field(component,
1142 CDC_TXn_TX_PATH_CTL(decimator),
1143 CDC_TXn_PGA_MUTE_MASK, 0x1);
1144 else
1145 snd_soc_component_update_bits(component,
1146 CDC_TXn_TX_PATH_CTL(decimator),
1147 CDC_TXn_PGA_MUTE_MASK, 0x0);
1148
1149 return 0;
1150}
1151
81df40a0 1152static const struct snd_soc_dai_ops tx_macro_dai_ops = {
c39667dd
SK		 1153 .hw_params = tx_macro_hw_params,
1154 .get_channel_map = tx_macro_get_channel_map,
1155 .mute_stream = tx_macro_digital_mute,
1156};
1157
1158static struct snd_soc_dai_driver tx_macro_dai[] = {
1159 {
1160 .name = "tx_macro_tx1",
1161 .id = TX_MACRO_AIF1_CAP,
1162 .capture = {
1163 .stream_name = "TX_AIF1 Capture",
1164 .rates = TX_MACRO_RATES,
1165 .formats = TX_MACRO_FORMATS,
1166 .rate_max = 192000,
1167 .rate_min = 8000,
1168 .channels_min = 1,
1169 .channels_max = 8,
1170 },
1171 .ops = &tx_macro_dai_ops,
1172 },
1173 {
1174 .name = "tx_macro_tx2",
1175 .id = TX_MACRO_AIF2_CAP,
1176 .capture = {
1177 .stream_name = "TX_AIF2 Capture",
1178 .rates = TX_MACRO_RATES,
1179 .formats = TX_MACRO_FORMATS,
1180 .rate_max = 192000,
1181 .rate_min = 8000,
1182 .channels_min = 1,
1183 .channels_max = 8,
1184 },
1185 .ops = &tx_macro_dai_ops,
1186 },
1187 {
1188 .name = "tx_macro_tx3",
1189 .id = TX_MACRO_AIF3_CAP,
1190 .capture = {
1191 .stream_name = "TX_AIF3 Capture",
1192 .rates = TX_MACRO_RATES,
1193 .formats = TX_MACRO_FORMATS,
1194 .rate_max = 192000,
1195 .rate_min = 8000,
1196 .channels_min = 1,
1197 .channels_max = 8,
1198 },
1199 .ops = &tx_macro_dai_ops,
1200 },
1201};
1202
d207bdea
SK		 1203static const char * const adc_mux_text[] = {
1204 "MSM_DMIC", "SWR_MIC", "ANC_FB_TUNE1"
1205};
1206
1207static SOC_ENUM_SINGLE_DECL(tx_dec0_enum, CDC_TX_INP_MUX_ADC_MUX0_CFG1,
1208 0, adc_mux_text);
1209static SOC_ENUM_SINGLE_DECL(tx_dec1_enum, CDC_TX_INP_MUX_ADC_MUX1_CFG1,
1210 0, adc_mux_text);
1211static SOC_ENUM_SINGLE_DECL(tx_dec2_enum, CDC_TX_INP_MUX_ADC_MUX2_CFG1,
1212 0, adc_mux_text);
1213static SOC_ENUM_SINGLE_DECL(tx_dec3_enum, CDC_TX_INP_MUX_ADC_MUX3_CFG1,
1214 0, adc_mux_text);
1215static SOC_ENUM_SINGLE_DECL(tx_dec4_enum, CDC_TX_INP_MUX_ADC_MUX4_CFG1,
1216 0, adc_mux_text);
1217static SOC_ENUM_SINGLE_DECL(tx_dec5_enum, CDC_TX_INP_MUX_ADC_MUX5_CFG1,
1218 0, adc_mux_text);
1219static SOC_ENUM_SINGLE_DECL(tx_dec6_enum, CDC_TX_INP_MUX_ADC_MUX6_CFG1,
1220 0, adc_mux_text);
1221static SOC_ENUM_SINGLE_DECL(tx_dec7_enum, CDC_TX_INP_MUX_ADC_MUX7_CFG1,
1222 0, adc_mux_text);
1223
1224static const struct snd_kcontrol_new tx_dec0_mux = SOC_DAPM_ENUM("tx_dec0", tx_dec0_enum);
1225static const struct snd_kcontrol_new tx_dec1_mux = SOC_DAPM_ENUM("tx_dec1", tx_dec1_enum);
1226static const struct snd_kcontrol_new tx_dec2_mux = SOC_DAPM_ENUM("tx_dec2", tx_dec2_enum);
1227static const struct snd_kcontrol_new tx_dec3_mux = SOC_DAPM_ENUM("tx_dec3", tx_dec3_enum);
1228static const struct snd_kcontrol_new tx_dec4_mux = SOC_DAPM_ENUM("tx_dec4", tx_dec4_enum);
1229static const struct snd_kcontrol_new tx_dec5_mux = SOC_DAPM_ENUM("tx_dec5", tx_dec5_enum);
1230static const struct snd_kcontrol_new tx_dec6_mux = SOC_DAPM_ENUM("tx_dec6", tx_dec6_enum);
1231static const struct snd_kcontrol_new tx_dec7_mux = SOC_DAPM_ENUM("tx_dec7", tx_dec7_enum);
1232
1233static const char * const smic_mux_text[] = {
1234 "ZERO", "ADC0", "ADC1", "ADC2", "ADC3", "SWR_DMIC0",
1235 "SWR_DMIC1", "SWR_DMIC2", "SWR_DMIC3", "SWR_DMIC4",
1236 "SWR_DMIC5", "SWR_DMIC6", "SWR_DMIC7"
1237};
1238
1239static SOC_ENUM_SINGLE_DECL(tx_smic0_enum, CDC_TX_INP_MUX_ADC_MUX0_CFG0,
1240 0, smic_mux_text);
1241
1242static SOC_ENUM_SINGLE_DECL(tx_smic1_enum, CDC_TX_INP_MUX_ADC_MUX1_CFG0,
1243 0, smic_mux_text);
1244
1245static SOC_ENUM_SINGLE_DECL(tx_smic2_enum, CDC_TX_INP_MUX_ADC_MUX2_CFG0,
1246 0, smic_mux_text);
1247
1248static SOC_ENUM_SINGLE_DECL(tx_smic3_enum, CDC_TX_INP_MUX_ADC_MUX3_CFG0,
1249 0, smic_mux_text);
1250
1251static SOC_ENUM_SINGLE_DECL(tx_smic4_enum, CDC_TX_INP_MUX_ADC_MUX4_CFG0,
1252 0, smic_mux_text);
1253
1254static SOC_ENUM_SINGLE_DECL(tx_smic5_enum, CDC_TX_INP_MUX_ADC_MUX5_CFG0,
1255 0, smic_mux_text);
1256
1257static SOC_ENUM_SINGLE_DECL(tx_smic6_enum, CDC_TX_INP_MUX_ADC_MUX6_CFG0,
1258 0, smic_mux_text);
1259
1260static SOC_ENUM_SINGLE_DECL(tx_smic7_enum, CDC_TX_INP_MUX_ADC_MUX7_CFG0,
1261 0, smic_mux_text);
1262
1263static const struct snd_kcontrol_new tx_smic0_mux = SOC_DAPM_ENUM_EXT("tx_smic0", tx_smic0_enum,
1264 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1265static const struct snd_kcontrol_new tx_smic1_mux = SOC_DAPM_ENUM_EXT("tx_smic1", tx_smic1_enum,
1266 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1267static const struct snd_kcontrol_new tx_smic2_mux = SOC_DAPM_ENUM_EXT("tx_smic2", tx_smic2_enum,
1268 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1269static const struct snd_kcontrol_new tx_smic3_mux = SOC_DAPM_ENUM_EXT("tx_smic3", tx_smic3_enum,
1270 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1271static const struct snd_kcontrol_new tx_smic4_mux = SOC_DAPM_ENUM_EXT("tx_smic4", tx_smic4_enum,
1272 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1273static const struct snd_kcontrol_new tx_smic5_mux = SOC_DAPM_ENUM_EXT("tx_smic5", tx_smic5_enum,
1274 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1275static const struct snd_kcontrol_new tx_smic6_mux = SOC_DAPM_ENUM_EXT("tx_smic6", tx_smic6_enum,
1276 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1277static const struct snd_kcontrol_new tx_smic7_mux = SOC_DAPM_ENUM_EXT("tx_smic7", tx_smic7_enum,
1278 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1279
710ccba0
SK		 1280static const char * const dmic_mux_text[] = {
1281 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3",
1282 "DMIC4", "DMIC5", "DMIC6", "DMIC7"
1283};
1284
1285static SOC_ENUM_SINGLE_DECL(tx_dmic0_enum, CDC_TX_INP_MUX_ADC_MUX0_CFG0,
1286 4, dmic_mux_text);
1287
1288static SOC_ENUM_SINGLE_DECL(tx_dmic1_enum, CDC_TX_INP_MUX_ADC_MUX1_CFG0,
1289 4, dmic_mux_text);
1290
1291static SOC_ENUM_SINGLE_DECL(tx_dmic2_enum, CDC_TX_INP_MUX_ADC_MUX2_CFG0,
1292 4, dmic_mux_text);
1293
1294static SOC_ENUM_SINGLE_DECL(tx_dmic3_enum, CDC_TX_INP_MUX_ADC_MUX3_CFG0,
1295 4, dmic_mux_text);
1296
1297static SOC_ENUM_SINGLE_DECL(tx_dmic4_enum, CDC_TX_INP_MUX_ADC_MUX4_CFG0,
1298 4, dmic_mux_text);
1299
1300static SOC_ENUM_SINGLE_DECL(tx_dmic5_enum, CDC_TX_INP_MUX_ADC_MUX5_CFG0,
1301 4, dmic_mux_text);
1302
1303static SOC_ENUM_SINGLE_DECL(tx_dmic6_enum, CDC_TX_INP_MUX_ADC_MUX6_CFG0,
1304 4, dmic_mux_text);
1305
1306static SOC_ENUM_SINGLE_DECL(tx_dmic7_enum, CDC_TX_INP_MUX_ADC_MUX7_CFG0,
1307 4, dmic_mux_text);
1308
1309static const struct snd_kcontrol_new tx_dmic0_mux = SOC_DAPM_ENUM_EXT("tx_dmic0", tx_dmic0_enum,
1310 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1311static const struct snd_kcontrol_new tx_dmic1_mux = SOC_DAPM_ENUM_EXT("tx_dmic1", tx_dmic1_enum,
1312 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1313static const struct snd_kcontrol_new tx_dmic2_mux = SOC_DAPM_ENUM_EXT("tx_dmic2", tx_dmic2_enum,
1314 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1315static const struct snd_kcontrol_new tx_dmic3_mux = SOC_DAPM_ENUM_EXT("tx_dmic3", tx_dmic3_enum,
1316 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1317static const struct snd_kcontrol_new tx_dmic4_mux = SOC_DAPM_ENUM_EXT("tx_dmic4", tx_dmic4_enum,
1318 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1319static const struct snd_kcontrol_new tx_dmic5_mux = SOC_DAPM_ENUM_EXT("tx_dmic5", tx_dmic5_enum,
1320 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1321static const struct snd_kcontrol_new tx_dmic6_mux = SOC_DAPM_ENUM_EXT("tx_dmic6", tx_dmic6_enum,
1322 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1323static const struct snd_kcontrol_new tx_dmic7_mux = SOC_DAPM_ENUM_EXT("tx_dmic7", tx_dmic7_enum,
1324 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1325
c39667dd
SK		 1326static const char * const dec_mode_mux_text[] = {
1327 "ADC_DEFAULT", "ADC_LOW_PWR", "ADC_HIGH_PERF",
1328};
1329
1330static const struct soc_enum dec_mode_mux_enum[] = {
1331 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(dec_mode_mux_text),
1332 dec_mode_mux_text),
1333 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(dec_mode_mux_text),
1334 dec_mode_mux_text),
1335 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(dec_mode_mux_text),
1336 dec_mode_mux_text),
1337 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(dec_mode_mux_text),
1338 dec_mode_mux_text),
1339 SOC_ENUM_SINGLE(SND_SOC_NOPM, 4, ARRAY_SIZE(dec_mode_mux_text),
1340 dec_mode_mux_text),
1341 SOC_ENUM_SINGLE(SND_SOC_NOPM, 5, ARRAY_SIZE(dec_mode_mux_text),
1342 dec_mode_mux_text),
1343 SOC_ENUM_SINGLE(SND_SOC_NOPM, 6, ARRAY_SIZE(dec_mode_mux_text),
1344 dec_mode_mux_text),
1345 SOC_ENUM_SINGLE(SND_SOC_NOPM, 7, ARRAY_SIZE(dec_mode_mux_text),
1346 dec_mode_mux_text),
1347};
1348
d207bdea
SK		 1349static const struct snd_kcontrol_new tx_aif1_cap_mixer[] = {
1350 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0,
1351 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1352 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0,
1353 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1354 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0,
1355 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1356 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0,
1357 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1358 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0,
1359 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1360 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0,
1361 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1362 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0,
1363 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1364 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0,
1365 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1366};
1367
1368static const struct snd_kcontrol_new tx_aif2_cap_mixer[] = {
1369 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0,
1370 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1371 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0,
1372 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1373 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0,
1374 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1375 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0,
1376 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1377 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0,
1378 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1379 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0,
1380 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1381 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0,
1382 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1383 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0,
1384 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1385};
1386
1387static const struct snd_kcontrol_new tx_aif3_cap_mixer[] = {
1388 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0,
1389 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1390 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0,
1391 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1392 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0,
1393 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1394 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0,
1395 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1396 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0,
1397 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1398 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0,
1399 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1400 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0,
1401 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1402 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0,
1403 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1404};
1405
1406static const struct snd_soc_dapm_widget tx_macro_dapm_widgets[] = {
1407 SND_SOC_DAPM_AIF_OUT("TX_AIF1 CAP", "TX_AIF1 Capture", 0,
1408 SND_SOC_NOPM, TX_MACRO_AIF1_CAP, 0),
1409
1410 SND_SOC_DAPM_AIF_OUT("TX_AIF2 CAP", "TX_AIF2 Capture", 0,
1411 SND_SOC_NOPM, TX_MACRO_AIF2_CAP, 0),
1412
1413 SND_SOC_DAPM_AIF_OUT("TX_AIF3 CAP", "TX_AIF3 Capture", 0,
1414 SND_SOC_NOPM, TX_MACRO_AIF3_CAP, 0),
1415
1416 SND_SOC_DAPM_MIXER("TX_AIF1_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF1_CAP, 0,
1417 tx_aif1_cap_mixer, ARRAY_SIZE(tx_aif1_cap_mixer)),
1418
1419 SND_SOC_DAPM_MIXER("TX_AIF2_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF2_CAP, 0,
1420 tx_aif2_cap_mixer, ARRAY_SIZE(tx_aif2_cap_mixer)),
1421
1422 SND_SOC_DAPM_MIXER("TX_AIF3_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF3_CAP, 0,
1423 tx_aif3_cap_mixer, ARRAY_SIZE(tx_aif3_cap_mixer)),
1424
1425 SND_SOC_DAPM_MUX("TX SMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_smic0_mux),
1426 SND_SOC_DAPM_MUX("TX SMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_smic1_mux),
1427 SND_SOC_DAPM_MUX("TX SMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_smic2_mux),
1428 SND_SOC_DAPM_MUX("TX SMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_smic3_mux),
1429 SND_SOC_DAPM_MUX("TX SMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_smic4_mux),
1430 SND_SOC_DAPM_MUX("TX SMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_smic5_mux),
1431 SND_SOC_DAPM_MUX("TX SMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_smic6_mux),
1432 SND_SOC_DAPM_MUX("TX SMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_smic7_mux),
1433
710ccba0
SK		 1434 SND_SOC_DAPM_MUX("TX DMIC MUX0", SND_SOC_NOPM, 4, 0, &tx_dmic0_mux),
1435 SND_SOC_DAPM_MUX("TX DMIC MUX1", SND_SOC_NOPM, 4, 0, &tx_dmic1_mux),
1436 SND_SOC_DAPM_MUX("TX DMIC MUX2", SND_SOC_NOPM, 4, 0, &tx_dmic2_mux),
1437 SND_SOC_DAPM_MUX("TX DMIC MUX3", SND_SOC_NOPM, 4, 0, &tx_dmic3_mux),
1438 SND_SOC_DAPM_MUX("TX DMIC MUX4", SND_SOC_NOPM, 4, 0, &tx_dmic4_mux),
1439 SND_SOC_DAPM_MUX("TX DMIC MUX5", SND_SOC_NOPM, 4, 0, &tx_dmic5_mux),
1440 SND_SOC_DAPM_MUX("TX DMIC MUX6", SND_SOC_NOPM, 4, 0, &tx_dmic6_mux),
1441 SND_SOC_DAPM_MUX("TX DMIC MUX7", SND_SOC_NOPM, 4, 0, &tx_dmic7_mux),
1442
d207bdea
SK		 1443 SND_SOC_DAPM_INPUT("TX SWR_ADC0"),
1444 SND_SOC_DAPM_INPUT("TX SWR_ADC1"),
1445 SND_SOC_DAPM_INPUT("TX SWR_ADC2"),
1446 SND_SOC_DAPM_INPUT("TX SWR_ADC3"),
1447 SND_SOC_DAPM_INPUT("TX SWR_DMIC0"),
1448 SND_SOC_DAPM_INPUT("TX SWR_DMIC1"),
1449 SND_SOC_DAPM_INPUT("TX SWR_DMIC2"),
1450 SND_SOC_DAPM_INPUT("TX SWR_DMIC3"),
1451 SND_SOC_DAPM_INPUT("TX SWR_DMIC4"),
1452 SND_SOC_DAPM_INPUT("TX SWR_DMIC5"),
1453 SND_SOC_DAPM_INPUT("TX SWR_DMIC6"),
1454 SND_SOC_DAPM_INPUT("TX SWR_DMIC7"),
710ccba0
SK		 1455 SND_SOC_DAPM_INPUT("TX DMIC0"),
1456 SND_SOC_DAPM_INPUT("TX DMIC1"),
1457 SND_SOC_DAPM_INPUT("TX DMIC2"),
1458 SND_SOC_DAPM_INPUT("TX DMIC3"),
1459 SND_SOC_DAPM_INPUT("TX DMIC4"),
1460 SND_SOC_DAPM_INPUT("TX DMIC5"),
1461 SND_SOC_DAPM_INPUT("TX DMIC6"),
1462 SND_SOC_DAPM_INPUT("TX DMIC7"),
d207bdea
SK		 1463
1464 SND_SOC_DAPM_MUX_E("TX DEC0 MUX", SND_SOC_NOPM,
1465 TX_MACRO_DEC0, 0,
1466 &tx_dec0_mux, tx_macro_enable_dec,
1467 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1468 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1469
1470 SND_SOC_DAPM_MUX_E("TX DEC1 MUX", SND_SOC_NOPM,
1471 TX_MACRO_DEC1, 0,
1472 &tx_dec1_mux, tx_macro_enable_dec,
1473 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1474 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1475
1476 SND_SOC_DAPM_MUX_E("TX DEC2 MUX", SND_SOC_NOPM,
1477 TX_MACRO_DEC2, 0,
1478 &tx_dec2_mux, tx_macro_enable_dec,
1479 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1480 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1481
1482 SND_SOC_DAPM_MUX_E("TX DEC3 MUX", SND_SOC_NOPM,
1483 TX_MACRO_DEC3, 0,
1484 &tx_dec3_mux, tx_macro_enable_dec,
1485 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1486 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1487
1488 SND_SOC_DAPM_MUX_E("TX DEC4 MUX", SND_SOC_NOPM,
1489 TX_MACRO_DEC4, 0,
1490 &tx_dec4_mux, tx_macro_enable_dec,
1491 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1492 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1493
1494 SND_SOC_DAPM_MUX_E("TX DEC5 MUX", SND_SOC_NOPM,
1495 TX_MACRO_DEC5, 0,
1496 &tx_dec5_mux, tx_macro_enable_dec,
1497 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1498 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1499
1500 SND_SOC_DAPM_MUX_E("TX DEC6 MUX", SND_SOC_NOPM,
1501 TX_MACRO_DEC6, 0,
1502 &tx_dec6_mux, tx_macro_enable_dec,
1503 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1504 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1505
1506 SND_SOC_DAPM_MUX_E("TX DEC7 MUX", SND_SOC_NOPM,
1507 TX_MACRO_DEC7, 0,
1508 &tx_dec7_mux, tx_macro_enable_dec,
1509 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1510 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1511
1512 SND_SOC_DAPM_SUPPLY_S("TX_MCLK", 0, SND_SOC_NOPM, 0, 0,
1513 tx_macro_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1514
1515 SND_SOC_DAPM_SUPPLY_S("TX_SWR_CLK", 0, SND_SOC_NOPM, 0, 0, NULL, 0),
1516
1517 SND_SOC_DAPM_SUPPLY_S("VA_SWR_CLK", 0, SND_SOC_NOPM, 0, 0,
1518 NULL, 0),
1519};
1520
1521static const struct snd_soc_dapm_route tx_audio_map[] = {
1522 {"TX_AIF1 CAP", NULL, "TX_MCLK"},
1523 {"TX_AIF2 CAP", NULL, "TX_MCLK"},
1524 {"TX_AIF3 CAP", NULL, "TX_MCLK"},
1525
1526 {"TX_AIF1 CAP", NULL, "TX_AIF1_CAP Mixer"},
1527 {"TX_AIF2 CAP", NULL, "TX_AIF2_CAP Mixer"},
1528 {"TX_AIF3 CAP", NULL, "TX_AIF3_CAP Mixer"},
1529
1530 {"TX_AIF1_CAP Mixer", "DEC0", "TX DEC0 MUX"},
1531 {"TX_AIF1_CAP Mixer", "DEC1", "TX DEC1 MUX"},
1532 {"TX_AIF1_CAP Mixer", "DEC2", "TX DEC2 MUX"},
1533 {"TX_AIF1_CAP Mixer", "DEC3", "TX DEC3 MUX"},
1534 {"TX_AIF1_CAP Mixer", "DEC4", "TX DEC4 MUX"},
1535 {"TX_AIF1_CAP Mixer", "DEC5", "TX DEC5 MUX"},
1536 {"TX_AIF1_CAP Mixer", "DEC6", "TX DEC6 MUX"},
1537 {"TX_AIF1_CAP Mixer", "DEC7", "TX DEC7 MUX"},
1538
1539 {"TX_AIF2_CAP Mixer", "DEC0", "TX DEC0 MUX"},
1540 {"TX_AIF2_CAP Mixer", "DEC1", "TX DEC1 MUX"},
1541 {"TX_AIF2_CAP Mixer", "DEC2", "TX DEC2 MUX"},
1542 {"TX_AIF2_CAP Mixer", "DEC3", "TX DEC3 MUX"},
1543 {"TX_AIF2_CAP Mixer", "DEC4", "TX DEC4 MUX"},
1544 {"TX_AIF2_CAP Mixer", "DEC5", "TX DEC5 MUX"},
1545 {"TX_AIF2_CAP Mixer", "DEC6", "TX DEC6 MUX"},
1546 {"TX_AIF2_CAP Mixer", "DEC7", "TX DEC7 MUX"},
1547
1548 {"TX_AIF3_CAP Mixer", "DEC0", "TX DEC0 MUX"},
1549 {"TX_AIF3_CAP Mixer", "DEC1", "TX DEC1 MUX"},
1550 {"TX_AIF3_CAP Mixer", "DEC2", "TX DEC2 MUX"},
1551 {"TX_AIF3_CAP Mixer", "DEC3", "TX DEC3 MUX"},
1552 {"TX_AIF3_CAP Mixer", "DEC4", "TX DEC4 MUX"},
1553 {"TX_AIF3_CAP Mixer", "DEC5", "TX DEC5 MUX"},
1554 {"TX_AIF3_CAP Mixer", "DEC6", "TX DEC6 MUX"},
1555 {"TX_AIF3_CAP Mixer", "DEC7", "TX DEC7 MUX"},
1556
1557 {"TX DEC0 MUX", NULL, "TX_MCLK"},
1558 {"TX DEC1 MUX", NULL, "TX_MCLK"},
1559 {"TX DEC2 MUX", NULL, "TX_MCLK"},
1560 {"TX DEC3 MUX", NULL, "TX_MCLK"},
1561 {"TX DEC4 MUX", NULL, "TX_MCLK"},
1562 {"TX DEC5 MUX", NULL, "TX_MCLK"},
1563 {"TX DEC6 MUX", NULL, "TX_MCLK"},
1564 {"TX DEC7 MUX", NULL, "TX_MCLK"},
1565
710ccba0
SK		 1566 {"TX DEC0 MUX", "MSM_DMIC", "TX DMIC MUX0"},
1567 {"TX DMIC MUX0", "DMIC0", "TX DMIC0"},
1568 {"TX DMIC MUX0", "DMIC1", "TX DMIC1"},
1569 {"TX DMIC MUX0", "DMIC2", "TX DMIC2"},
1570 {"TX DMIC MUX0", "DMIC3", "TX DMIC3"},
1571 {"TX DMIC MUX0", "DMIC4", "TX DMIC4"},
1572 {"TX DMIC MUX0", "DMIC5", "TX DMIC5"},
1573 {"TX DMIC MUX0", "DMIC6", "TX DMIC6"},
1574 {"TX DMIC MUX0", "DMIC7", "TX DMIC7"},
1575
d207bdea
SK		 1576 {"TX DEC0 MUX", "SWR_MIC", "TX SMIC MUX0"},
1577 {"TX SMIC MUX0", NULL, "TX_SWR_CLK"},
1578 {"TX SMIC MUX0", "ADC0", "TX SWR_ADC0"},
1579 {"TX SMIC MUX0", "ADC1", "TX SWR_ADC1"},
1580 {"TX SMIC MUX0", "ADC2", "TX SWR_ADC2"},
1581 {"TX SMIC MUX0", "ADC3", "TX SWR_ADC3"},
1582 {"TX SMIC MUX0", "SWR_DMIC0", "TX SWR_DMIC0"},
1583 {"TX SMIC MUX0", "SWR_DMIC1", "TX SWR_DMIC1"},
1584 {"TX SMIC MUX0", "SWR_DMIC2", "TX SWR_DMIC2"},
1585 {"TX SMIC MUX0", "SWR_DMIC3", "TX SWR_DMIC3"},
1586 {"TX SMIC MUX0", "SWR_DMIC4", "TX SWR_DMIC4"},
1587 {"TX SMIC MUX0", "SWR_DMIC5", "TX SWR_DMIC5"},
1588 {"TX SMIC MUX0", "SWR_DMIC6", "TX SWR_DMIC6"},
1589 {"TX SMIC MUX0", "SWR_DMIC7", "TX SWR_DMIC7"},
1590
710ccba0
SK		 1591 {"TX DEC1 MUX", "MSM_DMIC", "TX DMIC MUX1"},
1592 {"TX DMIC MUX1", "DMIC0", "TX DMIC0"},
1593 {"TX DMIC MUX1", "DMIC1", "TX DMIC1"},
1594 {"TX DMIC MUX1", "DMIC2", "TX DMIC2"},
1595 {"TX DMIC MUX1", "DMIC3", "TX DMIC3"},
1596 {"TX DMIC MUX1", "DMIC4", "TX DMIC4"},
1597 {"TX DMIC MUX1", "DMIC5", "TX DMIC5"},
1598 {"TX DMIC MUX1", "DMIC6", "TX DMIC6"},
1599 {"TX DMIC MUX1", "DMIC7", "TX DMIC7"},
1600
d207bdea
SK		 1601 {"TX DEC1 MUX", "SWR_MIC", "TX SMIC MUX1"},
1602 {"TX SMIC MUX1", NULL, "TX_SWR_CLK"},
1603 {"TX SMIC MUX1", "ADC0", "TX SWR_ADC0"},
1604 {"TX SMIC MUX1", "ADC1", "TX SWR_ADC1"},
1605 {"TX SMIC MUX1", "ADC2", "TX SWR_ADC2"},
1606 {"TX SMIC MUX1", "ADC3", "TX SWR_ADC3"},
1607 {"TX SMIC MUX1", "SWR_DMIC0", "TX SWR_DMIC0"},
1608 {"TX SMIC MUX1", "SWR_DMIC1", "TX SWR_DMIC1"},
1609 {"TX SMIC MUX1", "SWR_DMIC2", "TX SWR_DMIC2"},
1610 {"TX SMIC MUX1", "SWR_DMIC3", "TX SWR_DMIC3"},
1611 {"TX SMIC MUX1", "SWR_DMIC4", "TX SWR_DMIC4"},
1612 {"TX SMIC MUX1", "SWR_DMIC5", "TX SWR_DMIC5"},
1613 {"TX SMIC MUX1", "SWR_DMIC6", "TX SWR_DMIC6"},
1614 {"TX SMIC MUX1", "SWR_DMIC7", "TX SWR_DMIC7"},
1615
710ccba0
SK		 1616 {"TX DEC2 MUX", "MSM_DMIC", "TX DMIC MUX2"},
1617 {"TX DMIC MUX2", "DMIC0", "TX DMIC0"},
1618 {"TX DMIC MUX2", "DMIC1", "TX DMIC1"},
1619 {"TX DMIC MUX2", "DMIC2", "TX DMIC2"},
1620 {"TX DMIC MUX2", "DMIC3", "TX DMIC3"},
1621 {"TX DMIC MUX2", "DMIC4", "TX DMIC4"},
1622 {"TX DMIC MUX2", "DMIC5", "TX DMIC5"},
1623 {"TX DMIC MUX2", "DMIC6", "TX DMIC6"},
1624 {"TX DMIC MUX2", "DMIC7", "TX DMIC7"},
1625
d207bdea
SK		 1626 {"TX DEC2 MUX", "SWR_MIC", "TX SMIC MUX2"},
1627 {"TX SMIC MUX2", NULL, "TX_SWR_CLK"},
1628 {"TX SMIC MUX2", "ADC0", "TX SWR_ADC0"},
1629 {"TX SMIC MUX2", "ADC1", "TX SWR_ADC1"},
1630 {"TX SMIC MUX2", "ADC2", "TX SWR_ADC2"},
1631 {"TX SMIC MUX2", "ADC3", "TX SWR_ADC3"},
1632 {"TX SMIC MUX2", "SWR_DMIC0", "TX SWR_DMIC0"},
1633 {"TX SMIC MUX2", "SWR_DMIC1", "TX SWR_DMIC1"},
1634 {"TX SMIC MUX2", "SWR_DMIC2", "TX SWR_DMIC2"},
1635 {"TX SMIC MUX2", "SWR_DMIC3", "TX SWR_DMIC3"},
1636 {"TX SMIC MUX2", "SWR_DMIC4", "TX SWR_DMIC4"},
1637 {"TX SMIC MUX2", "SWR_DMIC5", "TX SWR_DMIC5"},
1638 {"TX SMIC MUX2", "SWR_DMIC6", "TX SWR_DMIC6"},
1639 {"TX SMIC MUX2", "SWR_DMIC7", "TX SWR_DMIC7"},
1640
710ccba0
SK		 1641 {"TX DEC3 MUX", "MSM_DMIC", "TX DMIC MUX3"},
1642 {"TX DMIC MUX3", "DMIC0", "TX DMIC0"},
1643 {"TX DMIC MUX3", "DMIC1", "TX DMIC1"},
1644 {"TX DMIC MUX3", "DMIC2", "TX DMIC2"},
1645 {"TX DMIC MUX3", "DMIC3", "TX DMIC3"},
1646 {"TX DMIC MUX3", "DMIC4", "TX DMIC4"},
1647 {"TX DMIC MUX3", "DMIC5", "TX DMIC5"},
1648 {"TX DMIC MUX3", "DMIC6", "TX DMIC6"},
1649 {"TX DMIC MUX3", "DMIC7", "TX DMIC7"},
1650
d207bdea
SK		 1651 {"TX DEC3 MUX", "SWR_MIC", "TX SMIC MUX3"},
1652 {"TX SMIC MUX3", NULL, "TX_SWR_CLK"},
1653 {"TX SMIC MUX3", "ADC0", "TX SWR_ADC0"},
1654 {"TX SMIC MUX3", "ADC1", "TX SWR_ADC1"},
1655 {"TX SMIC MUX3", "ADC2", "TX SWR_ADC2"},
1656 {"TX SMIC MUX3", "ADC3", "TX SWR_ADC3"},
1657 {"TX SMIC MUX3", "SWR_DMIC0", "TX SWR_DMIC0"},
1658 {"TX SMIC MUX3", "SWR_DMIC1", "TX SWR_DMIC1"},
1659 {"TX SMIC MUX3", "SWR_DMIC2", "TX SWR_DMIC2"},
1660 {"TX SMIC MUX3", "SWR_DMIC3", "TX SWR_DMIC3"},
1661 {"TX SMIC MUX3", "SWR_DMIC4", "TX SWR_DMIC4"},
1662 {"TX SMIC MUX3", "SWR_DMIC5", "TX SWR_DMIC5"},
1663 {"TX SMIC MUX3", "SWR_DMIC6", "TX SWR_DMIC6"},
1664 {"TX SMIC MUX3", "SWR_DMIC7", "TX SWR_DMIC7"},
1665
710ccba0
SK		 1666 {"TX DEC4 MUX", "MSM_DMIC", "TX DMIC MUX4"},
1667 {"TX DMIC MUX4", "DMIC0", "TX DMIC0"},
1668 {"TX DMIC MUX4", "DMIC1", "TX DMIC1"},
1669 {"TX DMIC MUX4", "DMIC2", "TX DMIC2"},
1670 {"TX DMIC MUX4", "DMIC3", "TX DMIC3"},
1671 {"TX DMIC MUX4", "DMIC4", "TX DMIC4"},
1672 {"TX DMIC MUX4", "DMIC5", "TX DMIC5"},
1673 {"TX DMIC MUX4", "DMIC6", "TX DMIC6"},
1674 {"TX DMIC MUX4", "DMIC7", "TX DMIC7"},
1675
d207bdea
SK		 1676 {"TX DEC4 MUX", "SWR_MIC", "TX SMIC MUX4"},
1677 {"TX SMIC MUX4", NULL, "TX_SWR_CLK"},
1678 {"TX SMIC MUX4", "ADC0", "TX SWR_ADC0"},
1679 {"TX SMIC MUX4", "ADC1", "TX SWR_ADC1"},
1680 {"TX SMIC MUX4", "ADC2", "TX SWR_ADC2"},
1681 {"TX SMIC MUX4", "ADC3", "TX SWR_ADC3"},
1682 {"TX SMIC MUX4", "SWR_DMIC0", "TX SWR_DMIC0"},
1683 {"TX SMIC MUX4", "SWR_DMIC1", "TX SWR_DMIC1"},
1684 {"TX SMIC MUX4", "SWR_DMIC2", "TX SWR_DMIC2"},
1685 {"TX SMIC MUX4", "SWR_DMIC3", "TX SWR_DMIC3"},
1686 {"TX SMIC MUX4", "SWR_DMIC4", "TX SWR_DMIC4"},
1687 {"TX SMIC MUX4", "SWR_DMIC5", "TX SWR_DMIC5"},
1688 {"TX SMIC MUX4", "SWR_DMIC6", "TX SWR_DMIC6"},
1689 {"TX SMIC MUX4", "SWR_DMIC7", "TX SWR_DMIC7"},
1690
710ccba0
SK		 1691 {"TX DEC5 MUX", "MSM_DMIC", "TX DMIC MUX5"},
1692 {"TX DMIC MUX5", "DMIC0", "TX DMIC0"},
1693 {"TX DMIC MUX5", "DMIC1", "TX DMIC1"},
1694 {"TX DMIC MUX5", "DMIC2", "TX DMIC2"},
1695 {"TX DMIC MUX5", "DMIC3", "TX DMIC3"},
1696 {"TX DMIC MUX5", "DMIC4", "TX DMIC4"},
1697 {"TX DMIC MUX5", "DMIC5", "TX DMIC5"},
1698 {"TX DMIC MUX5", "DMIC6", "TX DMIC6"},
1699 {"TX DMIC MUX5", "DMIC7", "TX DMIC7"},
1700
d207bdea
SK		 1701 {"TX DEC5 MUX", "SWR_MIC", "TX SMIC MUX5"},
1702 {"TX SMIC MUX5", NULL, "TX_SWR_CLK"},
1703 {"TX SMIC MUX5", "ADC0", "TX SWR_ADC0"},
1704 {"TX SMIC MUX5", "ADC1", "TX SWR_ADC1"},
1705 {"TX SMIC MUX5", "ADC2", "TX SWR_ADC2"},
1706 {"TX SMIC MUX5", "ADC3", "TX SWR_ADC3"},
1707 {"TX SMIC MUX5", "SWR_DMIC0", "TX SWR_DMIC0"},
1708 {"TX SMIC MUX5", "SWR_DMIC1", "TX SWR_DMIC1"},
1709 {"TX SMIC MUX5", "SWR_DMIC2", "TX SWR_DMIC2"},
1710 {"TX SMIC MUX5", "SWR_DMIC3", "TX SWR_DMIC3"},
1711 {"TX SMIC MUX5", "SWR_DMIC4", "TX SWR_DMIC4"},
1712 {"TX SMIC MUX5", "SWR_DMIC5", "TX SWR_DMIC5"},
1713 {"TX SMIC MUX5", "SWR_DMIC6", "TX SWR_DMIC6"},
1714 {"TX SMIC MUX5", "SWR_DMIC7", "TX SWR_DMIC7"},
1715
710ccba0
SK		 1716 {"TX DEC6 MUX", "MSM_DMIC", "TX DMIC MUX6"},
1717 {"TX DMIC MUX6", "DMIC0", "TX DMIC0"},
1718 {"TX DMIC MUX6", "DMIC1", "TX DMIC1"},
1719 {"TX DMIC MUX6", "DMIC2", "TX DMIC2"},
1720 {"TX DMIC MUX6", "DMIC3", "TX DMIC3"},
1721 {"TX DMIC MUX6", "DMIC4", "TX DMIC4"},
1722 {"TX DMIC MUX6", "DMIC5", "TX DMIC5"},
1723 {"TX DMIC MUX6", "DMIC6", "TX DMIC6"},
1724 {"TX DMIC MUX6", "DMIC7", "TX DMIC7"},
1725
d207bdea
SK		 1726 {"TX DEC6 MUX", "SWR_MIC", "TX SMIC MUX6"},
1727 {"TX SMIC MUX6", NULL, "TX_SWR_CLK"},
1728 {"TX SMIC MUX6", "ADC0", "TX SWR_ADC0"},
1729 {"TX SMIC MUX6", "ADC1", "TX SWR_ADC1"},
1730 {"TX SMIC MUX6", "ADC2", "TX SWR_ADC2"},
1731 {"TX SMIC MUX6", "ADC3", "TX SWR_ADC3"},
1732 {"TX SMIC MUX6", "SWR_DMIC0", "TX SWR_DMIC0"},
1733 {"TX SMIC MUX6", "SWR_DMIC1", "TX SWR_DMIC1"},
1734 {"TX SMIC MUX6", "SWR_DMIC2", "TX SWR_DMIC2"},
1735 {"TX SMIC MUX6", "SWR_DMIC3", "TX SWR_DMIC3"},
1736 {"TX SMIC MUX6", "SWR_DMIC4", "TX SWR_DMIC4"},
1737 {"TX SMIC MUX6", "SWR_DMIC5", "TX SWR_DMIC5"},
1738 {"TX SMIC MUX6", "SWR_DMIC6", "TX SWR_DMIC6"},
1739 {"TX SMIC MUX6", "SWR_DMIC7", "TX SWR_DMIC7"},
1740
710ccba0
SK		 1741 {"TX DEC7 MUX", "MSM_DMIC", "TX DMIC MUX7"},
1742 {"TX DMIC MUX7", "DMIC0", "TX DMIC0"},
1743 {"TX DMIC MUX7", "DMIC1", "TX DMIC1"},
1744 {"TX DMIC MUX7", "DMIC2", "TX DMIC2"},
1745 {"TX DMIC MUX7", "DMIC3", "TX DMIC3"},
1746 {"TX DMIC MUX7", "DMIC4", "TX DMIC4"},
1747 {"TX DMIC MUX7", "DMIC5", "TX DMIC5"},
1748 {"TX DMIC MUX7", "DMIC6", "TX DMIC6"},
1749 {"TX DMIC MUX7", "DMIC7", "TX DMIC7"},
1750
d207bdea
SK		 1751 {"TX DEC7 MUX", "SWR_MIC", "TX SMIC MUX7"},
1752 {"TX SMIC MUX7", NULL, "TX_SWR_CLK"},
1753 {"TX SMIC MUX7", "ADC0", "TX SWR_ADC0"},
1754 {"TX SMIC MUX7", "ADC1", "TX SWR_ADC1"},
1755 {"TX SMIC MUX7", "ADC2", "TX SWR_ADC2"},
1756 {"TX SMIC MUX7", "ADC3", "TX SWR_ADC3"},
1757 {"TX SMIC MUX7", "SWR_DMIC0", "TX SWR_DMIC0"},
1758 {"TX SMIC MUX7", "SWR_DMIC1", "TX SWR_DMIC1"},
1759 {"TX SMIC MUX7", "SWR_DMIC2", "TX SWR_DMIC2"},
1760 {"TX SMIC MUX7", "SWR_DMIC3", "TX SWR_DMIC3"},
1761 {"TX SMIC MUX7", "SWR_DMIC4", "TX SWR_DMIC4"},
1762 {"TX SMIC MUX7", "SWR_DMIC5", "TX SWR_DMIC5"},
1763 {"TX SMIC MUX7", "SWR_DMIC6", "TX SWR_DMIC6"},
1764 {"TX SMIC MUX7", "SWR_DMIC7", "TX SWR_DMIC7"},
1765};
1766
c39667dd
SK		 1767static const struct snd_kcontrol_new tx_macro_snd_controls[] = {
1768 SOC_SINGLE_S8_TLV("TX_DEC0 Volume",
1769 CDC_TX0_TX_VOL_CTL,
1770 -84, 40, digital_gain),
1771 SOC_SINGLE_S8_TLV("TX_DEC1 Volume",
1772 CDC_TX1_TX_VOL_CTL,
1773 -84, 40, digital_gain),
1774 SOC_SINGLE_S8_TLV("TX_DEC2 Volume",
1775 CDC_TX2_TX_VOL_CTL,
1776 -84, 40, digital_gain),
1777 SOC_SINGLE_S8_TLV("TX_DEC3 Volume",
1778 CDC_TX3_TX_VOL_CTL,
1779 -84, 40, digital_gain),
1780 SOC_SINGLE_S8_TLV("TX_DEC4 Volume",
1781 CDC_TX4_TX_VOL_CTL,
1782 -84, 40, digital_gain),
1783 SOC_SINGLE_S8_TLV("TX_DEC5 Volume",
1784 CDC_TX5_TX_VOL_CTL,
1785 -84, 40, digital_gain),
1786 SOC_SINGLE_S8_TLV("TX_DEC6 Volume",
1787 CDC_TX6_TX_VOL_CTL,
1788 -84, 40, digital_gain),
1789 SOC_SINGLE_S8_TLV("TX_DEC7 Volume",
1790 CDC_TX7_TX_VOL_CTL,
1791 -84, 40, digital_gain),
1792
1793 SOC_ENUM_EXT("DEC0 MODE", dec_mode_mux_enum[0],
1794 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1795
1796 SOC_ENUM_EXT("DEC1 MODE", dec_mode_mux_enum[1],
1797 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1798
1799 SOC_ENUM_EXT("DEC2 MODE", dec_mode_mux_enum[2],
1800 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1801
1802 SOC_ENUM_EXT("DEC3 MODE", dec_mode_mux_enum[3],
1803 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1804
1805 SOC_ENUM_EXT("DEC4 MODE", dec_mode_mux_enum[4],
1806 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1807
1808 SOC_ENUM_EXT("DEC5 MODE", dec_mode_mux_enum[5],
1809 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1810
1811 SOC_ENUM_EXT("DEC6 MODE", dec_mode_mux_enum[6],
1812 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1813
1814 SOC_ENUM_EXT("DEC7 MODE", dec_mode_mux_enum[7],
1815 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1816
1817 SOC_SINGLE_EXT("DEC0_BCS Switch", SND_SOC_NOPM, 0, 1, 0,
1818 tx_macro_get_bcs, tx_macro_set_bcs),
1819};
1820
1821static int tx_macro_component_probe(struct snd_soc_component *comp)
1822{
1823 struct tx_macro *tx = snd_soc_component_get_drvdata(comp);
1824 int i;
1825
1826 snd_soc_component_init_regmap(comp, tx->regmap);
1827
1828 for (i = 0; i < NUM_DECIMATORS; i++) {
1829 tx->tx_hpf_work[i].tx = tx;
1830 tx->tx_hpf_work[i].decimator = i;
1831 INIT_DELAYED_WORK(&tx->tx_hpf_work[i].dwork,
1832 tx_macro_tx_hpf_corner_freq_callback);
1833 }
1834
1835 for (i = 0; i < NUM_DECIMATORS; i++) {
1836 tx->tx_mute_dwork[i].tx = tx;
1837 tx->tx_mute_dwork[i].decimator = i;
1838 INIT_DELAYED_WORK(&tx->tx_mute_dwork[i].dwork,
1839 tx_macro_mute_update_callback);
1840 }
1841 tx->component = comp;
1842
1843 snd_soc_component_update_bits(comp, CDC_TX0_TX_PATH_SEC7, 0x3F,
1844 0x0A);
864b9b58
SRM		 1845 /* Enable swr mic0 and mic1 clock */
1846 snd_soc_component_update_bits(comp, CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 0xFF, 0x00);
1847 snd_soc_component_update_bits(comp, CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 0xFF, 0x00);
c39667dd
SK		 1848
1849 return 0;
1850}
1851
1852static int swclk_gate_enable(struct clk_hw *hw)
1853{
1854 struct tx_macro *tx = to_tx_macro(hw);
1855 struct regmap *regmap = tx->regmap;
31bd0db8
SK		 1856 int ret;
1857
1858 ret = clk_prepare_enable(tx->mclk);
1859 if (ret) {
1860 dev_err(tx->dev, "failed to enable mclk\n");
1861 return ret;
1862 }
c39667dd
SK		 1863
1864 tx_macro_mclk_enable(tx, true);
c39667dd
SK		 1865
1866 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
1867 CDC_TX_SWR_CLK_EN_MASK,
1868 CDC_TX_SWR_CLK_ENABLE);
c39667dd
SK		 1869 return 0;
1870}
1871
1872static void swclk_gate_disable(struct clk_hw *hw)
1873{
1874 struct tx_macro *tx = to_tx_macro(hw);
1875 struct regmap *regmap = tx->regmap;
1876
1877 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
1878 CDC_TX_SWR_CLK_EN_MASK, 0x0);
1879
1880 tx_macro_mclk_enable(tx, false);
31bd0db8 1881 clk_disable_unprepare(tx->mclk);
c39667dd
SK		 1882}
1883
1884static int swclk_gate_is_enabled(struct clk_hw *hw)
1885{
1886 struct tx_macro *tx = to_tx_macro(hw);
1887 int ret, val;
1888
1889 regmap_read(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, &val);
1890 ret = val & BIT(0);
1891
1892 return ret;
1893}
1894
1895static unsigned long swclk_recalc_rate(struct clk_hw *hw,
1896 unsigned long parent_rate)
1897{
1898 return parent_rate / 2;
1899}
1900
1901static const struct clk_ops swclk_gate_ops = {
1902 .prepare = swclk_gate_enable,
1903 .unprepare = swclk_gate_disable,
1904 .is_enabled = swclk_gate_is_enabled,
1905 .recalc_rate = swclk_recalc_rate,
1906
1907};
1908
db8665a3 1909static int tx_macro_register_mclk_output(struct tx_macro *tx)
c39667dd
SK		 1910{
1911 struct device *dev = tx->dev;
c39667dd
SK		 1912 const char *parent_clk_name = NULL;
1913 const char *clk_name = "lpass-tx-mclk";
1914 struct clk_hw *hw;
1915 struct clk_init_data init;
1916 int ret;
1917
5faf6a1c
KK		 1918 if (tx->npl)
1919 parent_clk_name = __clk_get_name(tx->npl);
1920 else
1921 parent_clk_name = __clk_get_name(tx->mclk);
c39667dd
SK		 1922
1923 init.name = clk_name;
1924 init.ops = &swclk_gate_ops;
1925 init.flags = 0;
1926 init.parent_names = &parent_clk_name;
1927 init.num_parents = 1;
1928 tx->hw.init = &init;
1929 hw = &tx->hw;
db8665a3 1930 ret = devm_clk_hw_register(dev, hw);
c39667dd 1931 if (ret)
db8665a3 1932 return ret;
c39667dd 1933
db8665a3 1934 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
c39667dd
SK		 1935}
1936
1937static const struct snd_soc_component_driver tx_macro_component_drv = {
1938 .name = "RX-MACRO",
1939 .probe = tx_macro_component_probe,
1940 .controls = tx_macro_snd_controls,
1941 .num_controls = ARRAY_SIZE(tx_macro_snd_controls),
d207bdea
SK		 1942 .dapm_widgets = tx_macro_dapm_widgets,
1943 .num_dapm_widgets = ARRAY_SIZE(tx_macro_dapm_widgets),
1944 .dapm_routes = tx_audio_map,
1945 .num_dapm_routes = ARRAY_SIZE(tx_audio_map),
c39667dd
SK		 1946};
1947
1948static int tx_macro_probe(struct platform_device *pdev)
1949{
1950 struct device *dev = &pdev->dev;
7b285c74 1951 struct device_node *np = dev->of_node;
5faf6a1c 1952 kernel_ulong_t flags;
c39667dd
SK		 1953 struct tx_macro *tx;
1954 void __iomem *base;
7b285c74 1955 int ret, reg;
c39667dd 1956
5faf6a1c
KK		 1957 flags = (kernel_ulong_t)device_get_match_data(dev);
1958
c39667dd
SK		 1959 tx = devm_kzalloc(dev, sizeof(*tx), GFP_KERNEL);
1960 if (!tx)
1961 return -ENOMEM;
1962
512864c4
SK		 1963 tx->macro = devm_clk_get_optional(dev, "macro");
1964 if (IS_ERR(tx->macro))
1965 return PTR_ERR(tx->macro);
c39667dd 1966
512864c4
SK		 1967 tx->dcodec = devm_clk_get_optional(dev, "dcodec");
1968 if (IS_ERR(tx->dcodec))
1969 return PTR_ERR(tx->dcodec);
1970
1971 tx->mclk = devm_clk_get(dev, "mclk");
1972 if (IS_ERR(tx->mclk))
1973 return PTR_ERR(tx->mclk);
1974
5faf6a1c
KK		 1975 if (flags & LPASS_MACRO_FLAG_HAS_NPL_CLOCK) {
1976 tx->npl = devm_clk_get(dev, "npl");
1977 if (IS_ERR(tx->npl))
1978 return PTR_ERR(tx->npl);
1979 }
512864c4
SK		 1980
1981 tx->fsgen = devm_clk_get(dev, "fsgen");
1982 if (IS_ERR(tx->fsgen))
1983 return PTR_ERR(tx->fsgen);
c39667dd 1984
9e3d83c5
SRM		 1985 tx->pds = lpass_macro_pds_init(dev);
1986 if (IS_ERR(tx->pds))
1987 return PTR_ERR(tx->pds);
1988
c39667dd 1989 base = devm_platform_ioremap_resource(pdev, 0);
ddfd5345
CJ		 1990 if (IS_ERR(base)) {
1991 ret = PTR_ERR(base);
1992 goto err;
1993 }
c39667dd 1994
7b285c74
SRM		 1995 /* Update defaults for lpass sc7280 */
1996 if (of_device_is_compatible(np, "qcom,sc7280-lpass-tx-macro")) {
1997 for (reg = 0; reg < ARRAY_SIZE(tx_defaults); reg++) {
1998 switch (tx_defaults[reg].reg) {
1999 case CDC_TX_TOP_CSR_SWR_AMIC0_CTL:
2000 case CDC_TX_TOP_CSR_SWR_AMIC1_CTL:
2001 tx_defaults[reg].def = 0x0E;
2002 break;
2003 default:
2004 break;
2005 }
2006 }
2007 }
2008
c39667dd 2009 tx->regmap = devm_regmap_init_mmio(dev, base, &tx_regmap_config);
ddfd5345
CJ		 2010 if (IS_ERR(tx->regmap)) {
2011 ret = PTR_ERR(tx->regmap);
2012 goto err;
2013 }
c39667dd
SK		 2014
2015 dev_set_drvdata(dev, tx);
2016
c39667dd
SK		 2017 tx->dev = dev;
2018
2019 /* set MCLK and NPL rates */
512864c4 2020 clk_set_rate(tx->mclk, MCLK_FREQ);
e7621434 2021 clk_set_rate(tx->npl, MCLK_FREQ);
c39667dd 2022
512864c4 2023 ret = clk_prepare_enable(tx->macro);
c39667dd 2024 if (ret)
512864c4
SK		 2025 goto err;
2026
2027 ret = clk_prepare_enable(tx->dcodec);
2028 if (ret)
2029 goto err_dcodec;
2030
2031 ret = clk_prepare_enable(tx->mclk);
2032 if (ret)
2033 goto err_mclk;
2034
2035 ret = clk_prepare_enable(tx->npl);
2036 if (ret)
2037 goto err_npl;
2038
2039 ret = clk_prepare_enable(tx->fsgen);
2040 if (ret)
2041 goto err_fsgen;
c39667dd 2042
ddffe3b8
SK		 2043 /* reset soundwire block */
2044 regmap_update_bits(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
2045 CDC_TX_SWR_RESET_MASK, CDC_TX_SWR_RESET_ENABLE);
2046
2047 regmap_update_bits(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
2048 CDC_TX_SWR_CLK_EN_MASK,
2049 CDC_TX_SWR_CLK_ENABLE);
2050 regmap_update_bits(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
2051 CDC_TX_SWR_RESET_MASK, 0x0);
2052
c39667dd
SK		 2053 ret = devm_snd_soc_register_component(dev, &tx_macro_component_drv,
2054 tx_macro_dai,
2055 ARRAY_SIZE(tx_macro_dai));
2056 if (ret)
512864c4 2057 goto err_clkout;
c39667dd 2058
1fb83bc5
SK		 2059 pm_runtime_set_autosuspend_delay(dev, 3000);
2060 pm_runtime_use_autosuspend(dev);
2061 pm_runtime_mark_last_busy(dev);
2062 pm_runtime_set_active(dev);
2063 pm_runtime_enable(dev);
2064
1dc34590
SK		 2065 ret = tx_macro_register_mclk_output(tx);
2066 if (ret)
2067 goto err_clkout;
2068
512864c4
SK		 2069 return 0;
2070
2071err_clkout:
2072 clk_disable_unprepare(tx->fsgen);
2073err_fsgen:
2074 clk_disable_unprepare(tx->npl);
2075err_npl:
2076 clk_disable_unprepare(tx->mclk);
2077err_mclk:
2078 clk_disable_unprepare(tx->dcodec);
2079err_dcodec:
2080 clk_disable_unprepare(tx->macro);
2081err:
ddfd5345
CJ		 2082 lpass_macro_pds_exit(tx->pds);
2083
c39667dd
SK		 2084 return ret;
2085}
2086
10b4f1ed 2087static void tx_macro_remove(struct platform_device *pdev)
c39667dd
SK		 2088{
2089 struct tx_macro *tx = dev_get_drvdata(&pdev->dev);
2090
512864c4
SK		 2091 clk_disable_unprepare(tx->macro);
2092 clk_disable_unprepare(tx->dcodec);
2093 clk_disable_unprepare(tx->mclk);
2094 clk_disable_unprepare(tx->npl);
2095 clk_disable_unprepare(tx->fsgen);
c39667dd 2096
1c19601d 2097 lpass_macro_pds_exit(tx->pds);
c39667dd
SK		 2098}
2099
1fb83bc5
SK		 2100static int __maybe_unused tx_macro_runtime_suspend(struct device *dev)
2101{
2102 struct tx_macro *tx = dev_get_drvdata(dev);
2103
2104 regcache_cache_only(tx->regmap, true);
2105 regcache_mark_dirty(tx->regmap);
2106
2107 clk_disable_unprepare(tx->mclk);
2108 clk_disable_unprepare(tx->npl);
2109 clk_disable_unprepare(tx->fsgen);
2110
2111 return 0;
2112}
2113
2114static int __maybe_unused tx_macro_runtime_resume(struct device *dev)
2115{
2116 struct tx_macro *tx = dev_get_drvdata(dev);
2117 int ret;
2118
2119 ret = clk_prepare_enable(tx->mclk);
2120 if (ret) {
2121 dev_err(dev, "unable to prepare mclk\n");
2122 return ret;
2123 }
2124
2125 ret = clk_prepare_enable(tx->npl);
2126 if (ret) {
2127 dev_err(dev, "unable to prepare npl\n");
2128 goto err_npl;
2129 }
2130
2131 ret = clk_prepare_enable(tx->fsgen);
2132 if (ret) {
2133 dev_err(dev, "unable to prepare fsgen\n");
2134 goto err_fsgen;
2135 }
2136
2137 regcache_cache_only(tx->regmap, false);
2138 regcache_sync(tx->regmap);
1fb83bc5
SK		 2139
2140 return 0;
2141err_fsgen:
2142 clk_disable_unprepare(tx->npl);
2143err_npl:
2144 clk_disable_unprepare(tx->mclk);
2145
2146 return ret;
2147}
2148
2149static const struct dev_pm_ops tx_macro_pm_ops = {
2150 SET_RUNTIME_PM_OPS(tx_macro_runtime_suspend, tx_macro_runtime_resume, NULL)
2151};
2152
c39667dd 2153static const struct of_device_id tx_macro_dt_match[] = {
5faf6a1c
KK		 2154 {
2155 .compatible = "qcom,sc7280-lpass-tx-macro",
2156 .data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK,
2157 }, {
2158 .compatible = "qcom,sm8250-lpass-tx-macro",
2159 .data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK,
2160 }, {
2161 .compatible = "qcom,sm8450-lpass-tx-macro",
2162 .data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK,
2163 }, {
2164 .compatible = "qcom,sm8550-lpass-tx-macro",
2165 }, {
2166 .compatible = "qcom,sc8280xp-lpass-tx-macro",
2167 .data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK,
2168 },
c39667dd
SK		 2169 { }
2170};
14c0c423 2171MODULE_DEVICE_TABLE(of, tx_macro_dt_match);
c39667dd
SK		 2172static struct platform_driver tx_macro_driver = {
2173 .driver = {
2174 .name = "tx_macro",
2175 .of_match_table = tx_macro_dt_match,
2176 .suppress_bind_attrs = true,
1fb83bc5 2177 .pm = &tx_macro_pm_ops,
c39667dd
SK		 2178 },
2179 .probe = tx_macro_probe,
10b4f1ed 2180 .remove_new = tx_macro_remove,
c39667dd
SK		 2181};
2182
2183module_platform_driver(tx_macro_driver);
2184
2185MODULE_DESCRIPTION("TX macro driver");
2186MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)