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ASoC: codecs: tx-macro: fix active_decimator array
[linux-block.git] / sound / soc / codecs / lpass-tx-macro.c
CommitLineData
c39667dd
SK		 1// SPDX-License-Identifier: GPL-2.0-only
2// Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
3
4#include <linux/module.h>
5#include <linux/init.h>
6#include <linux/clk.h>
7#include <linux/io.h>
8#include <linux/platform_device.h>
512864c4 9#include <linux/pm_runtime.h>
c39667dd
SK		 10#include <linux/regmap.h>
11#include <sound/soc.h>
12#include <sound/soc-dapm.h>
13#include <sound/tlv.h>
14#include <linux/of_clk.h>
15#include <linux/clk-provider.h>
16
9e3d83c5
SRM		 17#include "lpass-macro-common.h"
18
c39667dd
SK		 19#define CDC_TX_CLK_RST_CTRL_MCLK_CONTROL (0x0000)
20#define CDC_TX_MCLK_EN_MASK BIT(0)
21#define CDC_TX_MCLK_ENABLE BIT(0)
22#define CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL (0x0004)
23#define CDC_TX_FS_CNT_EN_MASK BIT(0)
24#define CDC_TX_FS_CNT_ENABLE BIT(0)
25#define CDC_TX_CLK_RST_CTRL_SWR_CONTROL (0x0008)
26#define CDC_TX_SWR_RESET_MASK BIT(1)
27#define CDC_TX_SWR_RESET_ENABLE BIT(1)
28#define CDC_TX_SWR_CLK_EN_MASK BIT(0)
29#define CDC_TX_SWR_CLK_ENABLE BIT(0)
30#define CDC_TX_TOP_CSR_TOP_CFG0 (0x0080)
31#define CDC_TX_TOP_CSR_ANC_CFG (0x0084)
32#define CDC_TX_TOP_CSR_SWR_CTRL (0x0088)
33#define CDC_TX_TOP_CSR_FREQ_MCLK (0x0090)
34#define CDC_TX_TOP_CSR_DEBUG_BUS (0x0094)
35#define CDC_TX_TOP_CSR_DEBUG_EN (0x0098)
36#define CDC_TX_TOP_CSR_TX_I2S_CTL (0x00A4)
37#define CDC_TX_TOP_CSR_I2S_CLK (0x00A8)
38#define CDC_TX_TOP_CSR_I2S_RESET (0x00AC)
39#define CDC_TX_TOP_CSR_SWR_DMICn_CTL(n) (0x00C0 + n * 0x4)
40#define CDC_TX_TOP_CSR_SWR_DMIC0_CTL (0x00C0)
41#define CDC_TX_SWR_DMIC_CLK_SEL_MASK GENMASK(3, 1)
42#define CDC_TX_TOP_CSR_SWR_DMIC1_CTL (0x00C4)
43#define CDC_TX_TOP_CSR_SWR_DMIC2_CTL (0x00C8)
44#define CDC_TX_TOP_CSR_SWR_DMIC3_CTL (0x00CC)
45#define CDC_TX_TOP_CSR_SWR_AMIC0_CTL (0x00D0)
46#define CDC_TX_TOP_CSR_SWR_AMIC1_CTL (0x00D4)
47#define CDC_TX_INP_MUX_ADC_MUXn_CFG0(n) (0x0100 + 0x8 * n)
48#define CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK GENMASK(3, 0)
49#define CDC_TX_INP_MUX_ADC_MUX0_CFG0 (0x0100)
50#define CDC_TX_INP_MUX_ADC_MUXn_CFG1(n) (0x0104 + 0x8 * n)
51#define CDC_TX_INP_MUX_ADC_MUX0_CFG1 (0x0104)
52#define CDC_TX_INP_MUX_ADC_MUX1_CFG0 (0x0108)
53#define CDC_TX_INP_MUX_ADC_MUX1_CFG1 (0x010C)
54#define CDC_TX_INP_MUX_ADC_MUX2_CFG0 (0x0110)
55#define CDC_TX_INP_MUX_ADC_MUX2_CFG1 (0x0114)
56#define CDC_TX_INP_MUX_ADC_MUX3_CFG0 (0x0118)
57#define CDC_TX_INP_MUX_ADC_MUX3_CFG1 (0x011C)
58#define CDC_TX_INP_MUX_ADC_MUX4_CFG0 (0x0120)
59#define CDC_TX_INP_MUX_ADC_MUX4_CFG1 (0x0124)
60#define CDC_TX_INP_MUX_ADC_MUX5_CFG0 (0x0128)
61#define CDC_TX_INP_MUX_ADC_MUX5_CFG1 (0x012C)
62#define CDC_TX_INP_MUX_ADC_MUX6_CFG0 (0x0130)
63#define CDC_TX_INP_MUX_ADC_MUX6_CFG1 (0x0134)
64#define CDC_TX_INP_MUX_ADC_MUX7_CFG0 (0x0138)
65#define CDC_TX_INP_MUX_ADC_MUX7_CFG1 (0x013C)
66#define CDC_TX_ANC0_CLK_RESET_CTL (0x0200)
67#define CDC_TX_ANC0_MODE_1_CTL (0x0204)
68#define CDC_TX_ANC0_MODE_2_CTL (0x0208)
69#define CDC_TX_ANC0_FF_SHIFT (0x020C)
70#define CDC_TX_ANC0_FB_SHIFT (0x0210)
71#define CDC_TX_ANC0_LPF_FF_A_CTL (0x0214)
72#define CDC_TX_ANC0_LPF_FF_B_CTL (0x0218)
73#define CDC_TX_ANC0_LPF_FB_CTL (0x021C)
74#define CDC_TX_ANC0_SMLPF_CTL (0x0220)
75#define CDC_TX_ANC0_DCFLT_SHIFT_CTL (0x0224)
76#define CDC_TX_ANC0_IIR_ADAPT_CTL (0x0228)
77#define CDC_TX_ANC0_IIR_COEFF_1_CTL (0x022C)
78#define CDC_TX_ANC0_IIR_COEFF_2_CTL (0x0230)
79#define CDC_TX_ANC0_FF_A_GAIN_CTL (0x0234)
80#define CDC_TX_ANC0_FF_B_GAIN_CTL (0x0238)
81#define CDC_TX_ANC0_FB_GAIN_CTL (0x023C)
82#define CDC_TXn_TX_PATH_CTL(n) (0x0400 + 0x80 * n)
83#define CDC_TXn_PCM_RATE_MASK GENMASK(3, 0)
84#define CDC_TXn_PGA_MUTE_MASK BIT(4)
85#define CDC_TXn_CLK_EN_MASK BIT(5)
86#define CDC_TX0_TX_PATH_CTL (0x0400)
87#define CDC_TXn_TX_PATH_CFG0(n) (0x0404 + 0x80 * n)
88#define CDC_TX0_TX_PATH_CFG0 (0x0404)
89#define CDC_TXn_PH_EN_MASK BIT(0)
90#define CDC_TXn_ADC_MODE_MASK GENMASK(2, 1)
91#define CDC_TXn_HPF_CUT_FREQ_MASK GENMASK(6, 5)
92#define CDC_TXn_ADC_DMIC_SEL_MASK BIT(7)
93#define CDC_TX0_TX_PATH_CFG1 (0x0408)
94#define CDC_TXn_TX_VOL_CTL(n) (0x040C + 0x80 * n)
95#define CDC_TX0_TX_VOL_CTL (0x040C)
96#define CDC_TX0_TX_PATH_SEC0 (0x0410)
97#define CDC_TX0_TX_PATH_SEC1 (0x0414)
98#define CDC_TXn_TX_PATH_SEC2(n) (0x0418 + 0x80 * n)
99#define CDC_TXn_HPF_F_CHANGE_MASK BIT(1)
100#define CDC_TXn_HPF_ZERO_GATE_MASK BIT(0)
101#define CDC_TX0_TX_PATH_SEC2 (0x0418)
102#define CDC_TX0_TX_PATH_SEC3 (0x041C)
103#define CDC_TX0_TX_PATH_SEC4 (0x0420)
104#define CDC_TX0_TX_PATH_SEC5 (0x0424)
105#define CDC_TX0_TX_PATH_SEC6 (0x0428)
106#define CDC_TX0_TX_PATH_SEC7 (0x042C)
107#define CDC_TX0_MBHC_CTL_EN_MASK BIT(6)
108#define CDC_TX1_TX_PATH_CTL (0x0480)
109#define CDC_TX1_TX_PATH_CFG0 (0x0484)
110#define CDC_TX1_TX_PATH_CFG1 (0x0488)
111#define CDC_TX1_TX_VOL_CTL (0x048C)
112#define CDC_TX1_TX_PATH_SEC0 (0x0490)
113#define CDC_TX1_TX_PATH_SEC1 (0x0494)
114#define CDC_TX1_TX_PATH_SEC2 (0x0498)
115#define CDC_TX1_TX_PATH_SEC3 (0x049C)
116#define CDC_TX1_TX_PATH_SEC4 (0x04A0)
117#define CDC_TX1_TX_PATH_SEC5 (0x04A4)
118#define CDC_TX1_TX_PATH_SEC6 (0x04A8)
119#define CDC_TX2_TX_PATH_CTL (0x0500)
120#define CDC_TX2_TX_PATH_CFG0 (0x0504)
121#define CDC_TX2_TX_PATH_CFG1 (0x0508)
122#define CDC_TX2_TX_VOL_CTL (0x050C)
123#define CDC_TX2_TX_PATH_SEC0 (0x0510)
124#define CDC_TX2_TX_PATH_SEC1 (0x0514)
125#define CDC_TX2_TX_PATH_SEC2 (0x0518)
126#define CDC_TX2_TX_PATH_SEC3 (0x051C)
127#define CDC_TX2_TX_PATH_SEC4 (0x0520)
128#define CDC_TX2_TX_PATH_SEC5 (0x0524)
129#define CDC_TX2_TX_PATH_SEC6 (0x0528)
130#define CDC_TX3_TX_PATH_CTL (0x0580)
131#define CDC_TX3_TX_PATH_CFG0 (0x0584)
132#define CDC_TX3_TX_PATH_CFG1 (0x0588)
133#define CDC_TX3_TX_VOL_CTL (0x058C)
134#define CDC_TX3_TX_PATH_SEC0 (0x0590)
135#define CDC_TX3_TX_PATH_SEC1 (0x0594)
136#define CDC_TX3_TX_PATH_SEC2 (0x0598)
137#define CDC_TX3_TX_PATH_SEC3 (0x059C)
138#define CDC_TX3_TX_PATH_SEC4 (0x05A0)
139#define CDC_TX3_TX_PATH_SEC5 (0x05A4)
140#define CDC_TX3_TX_PATH_SEC6 (0x05A8)
141#define CDC_TX4_TX_PATH_CTL (0x0600)
142#define CDC_TX4_TX_PATH_CFG0 (0x0604)
143#define CDC_TX4_TX_PATH_CFG1 (0x0608)
144#define CDC_TX4_TX_VOL_CTL (0x060C)
145#define CDC_TX4_TX_PATH_SEC0 (0x0610)
146#define CDC_TX4_TX_PATH_SEC1 (0x0614)
147#define CDC_TX4_TX_PATH_SEC2 (0x0618)
148#define CDC_TX4_TX_PATH_SEC3 (0x061C)
149#define CDC_TX4_TX_PATH_SEC4 (0x0620)
150#define CDC_TX4_TX_PATH_SEC5 (0x0624)
151#define CDC_TX4_TX_PATH_SEC6 (0x0628)
152#define CDC_TX5_TX_PATH_CTL (0x0680)
153#define CDC_TX5_TX_PATH_CFG0 (0x0684)
154#define CDC_TX5_TX_PATH_CFG1 (0x0688)
155#define CDC_TX5_TX_VOL_CTL (0x068C)
156#define CDC_TX5_TX_PATH_SEC0 (0x0690)
157#define CDC_TX5_TX_PATH_SEC1 (0x0694)
158#define CDC_TX5_TX_PATH_SEC2 (0x0698)
159#define CDC_TX5_TX_PATH_SEC3 (0x069C)
160#define CDC_TX5_TX_PATH_SEC4 (0x06A0)
161#define CDC_TX5_TX_PATH_SEC5 (0x06A4)
162#define CDC_TX5_TX_PATH_SEC6 (0x06A8)
163#define CDC_TX6_TX_PATH_CTL (0x0700)
164#define CDC_TX6_TX_PATH_CFG0 (0x0704)
165#define CDC_TX6_TX_PATH_CFG1 (0x0708)
166#define CDC_TX6_TX_VOL_CTL (0x070C)
167#define CDC_TX6_TX_PATH_SEC0 (0x0710)
168#define CDC_TX6_TX_PATH_SEC1 (0x0714)
169#define CDC_TX6_TX_PATH_SEC2 (0x0718)
170#define CDC_TX6_TX_PATH_SEC3 (0x071C)
171#define CDC_TX6_TX_PATH_SEC4 (0x0720)
172#define CDC_TX6_TX_PATH_SEC5 (0x0724)
173#define CDC_TX6_TX_PATH_SEC6 (0x0728)
174#define CDC_TX7_TX_PATH_CTL (0x0780)
175#define CDC_TX7_TX_PATH_CFG0 (0x0784)
176#define CDC_TX7_TX_PATH_CFG1 (0x0788)
177#define CDC_TX7_TX_VOL_CTL (0x078C)
178#define CDC_TX7_TX_PATH_SEC0 (0x0790)
179#define CDC_TX7_TX_PATH_SEC1 (0x0794)
180#define CDC_TX7_TX_PATH_SEC2 (0x0798)
181#define CDC_TX7_TX_PATH_SEC3 (0x079C)
182#define CDC_TX7_TX_PATH_SEC4 (0x07A0)
183#define CDC_TX7_TX_PATH_SEC5 (0x07A4)
184#define CDC_TX7_TX_PATH_SEC6 (0x07A8)
185#define TX_MAX_OFFSET (0x07A8)
186
187#define TX_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
188 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
189 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
190#define TX_MACRO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
191 SNDRV_PCM_FMTBIT_S24_LE |\
192 SNDRV_PCM_FMTBIT_S24_3LE)
193
194#define CF_MIN_3DB_4HZ 0x0
195#define CF_MIN_3DB_75HZ 0x1
196#define CF_MIN_3DB_150HZ 0x2
197#define TX_ADC_MAX 5
198#define TX_ADC_TO_DMIC(n) ((n - TX_ADC_MAX)/2)
199#define NUM_DECIMATORS 8
200#define TX_NUM_CLKS_MAX 5
201#define TX_MACRO_DMIC_UNMUTE_DELAY_MS 40
202#define TX_MACRO_AMIC_UNMUTE_DELAY_MS 100
203#define TX_MACRO_DMIC_HPF_DELAY_MS 300
204#define TX_MACRO_AMIC_HPF_DELAY_MS 300
205#define MCLK_FREQ 9600000
206
207enum {
208 TX_MACRO_AIF_INVALID = 0,
209 TX_MACRO_AIF1_CAP,
210 TX_MACRO_AIF2_CAP,
211 TX_MACRO_AIF3_CAP,
212 TX_MACRO_MAX_DAIS
213};
214
215enum {
216 TX_MACRO_DEC0,
217 TX_MACRO_DEC1,
218 TX_MACRO_DEC2,
219 TX_MACRO_DEC3,
220 TX_MACRO_DEC4,
221 TX_MACRO_DEC5,
222 TX_MACRO_DEC6,
223 TX_MACRO_DEC7,
224 TX_MACRO_DEC_MAX,
225};
226
227enum {
228 TX_MACRO_CLK_DIV_2,
229 TX_MACRO_CLK_DIV_3,
230 TX_MACRO_CLK_DIV_4,
231 TX_MACRO_CLK_DIV_6,
232 TX_MACRO_CLK_DIV_8,
233 TX_MACRO_CLK_DIV_16,
234};
235
236enum {
237 MSM_DMIC,
238 SWR_MIC,
239 ANC_FB_TUNE1
240};
241
242struct tx_mute_work {
243 struct tx_macro *tx;
244 u32 decimator;
245 struct delayed_work dwork;
246};
247
248struct hpf_work {
249 struct tx_macro *tx;
250 u8 decimator;
251 u8 hpf_cut_off_freq;
252 struct delayed_work dwork;
253};
254
255struct tx_macro {
256 struct device *dev;
257 struct snd_soc_component *component;
258 struct hpf_work tx_hpf_work[NUM_DECIMATORS];
259 struct tx_mute_work tx_mute_dwork[NUM_DECIMATORS];
260 unsigned long active_ch_mask[TX_MACRO_MAX_DAIS];
261 unsigned long active_ch_cnt[TX_MACRO_MAX_DAIS];
1c6a7f52 262 int active_decimator[TX_MACRO_MAX_DAIS];
c39667dd 263 struct regmap *regmap;
512864c4
SK		 264 struct clk *mclk;
265 struct clk *npl;
266 struct clk *macro;
267 struct clk *dcodec;
268 struct clk *fsgen;
c39667dd
SK		 269 struct clk_hw hw;
270 bool dec_active[NUM_DECIMATORS];
c39667dd
SK		 271 int tx_mclk_users;
272 u16 dmic_clk_div;
273 bool bcs_enable;
274 int dec_mode[NUM_DECIMATORS];
9e3d83c5 275 struct lpass_macro *pds;
c39667dd
SK		 276 bool bcs_clk_en;
277};
278#define to_tx_macro(_hw) container_of(_hw, struct tx_macro, hw)
279
280static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
281
7b285c74 282static struct reg_default tx_defaults[] = {
c39667dd
SK		 283 /* TX Macro */
284 { CDC_TX_CLK_RST_CTRL_MCLK_CONTROL, 0x00 },
285 { CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00 },
286 { CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 0x00},
287 { CDC_TX_TOP_CSR_TOP_CFG0, 0x00},
288 { CDC_TX_TOP_CSR_ANC_CFG, 0x00},
289 { CDC_TX_TOP_CSR_SWR_CTRL, 0x00},
290 { CDC_TX_TOP_CSR_FREQ_MCLK, 0x00},
291 { CDC_TX_TOP_CSR_DEBUG_BUS, 0x00},
292 { CDC_TX_TOP_CSR_DEBUG_EN, 0x00},
293 { CDC_TX_TOP_CSR_TX_I2S_CTL, 0x0C},
294 { CDC_TX_TOP_CSR_I2S_CLK, 0x00},
295 { CDC_TX_TOP_CSR_I2S_RESET, 0x00},
296 { CDC_TX_TOP_CSR_SWR_DMIC0_CTL, 0x00},
297 { CDC_TX_TOP_CSR_SWR_DMIC1_CTL, 0x00},
298 { CDC_TX_TOP_CSR_SWR_DMIC2_CTL, 0x00},
299 { CDC_TX_TOP_CSR_SWR_DMIC3_CTL, 0x00},
300 { CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 0x00},
301 { CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 0x00},
302 { CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0x00},
303 { CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0x00},
304 { CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0x00},
305 { CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0x00},
306 { CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0x00},
307 { CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0x00},
308 { CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0x00},
309 { CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0x00},
310 { CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0x00},
311 { CDC_TX_INP_MUX_ADC_MUX4_CFG1, 0x00},
312 { CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0x00},
313 { CDC_TX_INP_MUX_ADC_MUX5_CFG1, 0x00},
314 { CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0x00},
315 { CDC_TX_INP_MUX_ADC_MUX6_CFG1, 0x00},
316 { CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0x00},
317 { CDC_TX_INP_MUX_ADC_MUX7_CFG1, 0x00},
318 { CDC_TX_ANC0_CLK_RESET_CTL, 0x00},
319 { CDC_TX_ANC0_MODE_1_CTL, 0x00},
320 { CDC_TX_ANC0_MODE_2_CTL, 0x00},
321 { CDC_TX_ANC0_FF_SHIFT, 0x00},
322 { CDC_TX_ANC0_FB_SHIFT, 0x00},
323 { CDC_TX_ANC0_LPF_FF_A_CTL, 0x00},
324 { CDC_TX_ANC0_LPF_FF_B_CTL, 0x00},
325 { CDC_TX_ANC0_LPF_FB_CTL, 0x00},
326 { CDC_TX_ANC0_SMLPF_CTL, 0x00},
327 { CDC_TX_ANC0_DCFLT_SHIFT_CTL, 0x00},
328 { CDC_TX_ANC0_IIR_ADAPT_CTL, 0x00},
329 { CDC_TX_ANC0_IIR_COEFF_1_CTL, 0x00},
330 { CDC_TX_ANC0_IIR_COEFF_2_CTL, 0x00},
331 { CDC_TX_ANC0_FF_A_GAIN_CTL, 0x00},
332 { CDC_TX_ANC0_FF_B_GAIN_CTL, 0x00},
333 { CDC_TX_ANC0_FB_GAIN_CTL, 0x00},
334 { CDC_TX0_TX_PATH_CTL, 0x04},
335 { CDC_TX0_TX_PATH_CFG0, 0x10},
336 { CDC_TX0_TX_PATH_CFG1, 0x0B},
337 { CDC_TX0_TX_VOL_CTL, 0x00},
338 { CDC_TX0_TX_PATH_SEC0, 0x00},
339 { CDC_TX0_TX_PATH_SEC1, 0x00},
340 { CDC_TX0_TX_PATH_SEC2, 0x01},
341 { CDC_TX0_TX_PATH_SEC3, 0x3C},
342 { CDC_TX0_TX_PATH_SEC4, 0x20},
343 { CDC_TX0_TX_PATH_SEC5, 0x00},
344 { CDC_TX0_TX_PATH_SEC6, 0x00},
345 { CDC_TX0_TX_PATH_SEC7, 0x25},
346 { CDC_TX1_TX_PATH_CTL, 0x04},
347 { CDC_TX1_TX_PATH_CFG0, 0x10},
348 { CDC_TX1_TX_PATH_CFG1, 0x0B},
349 { CDC_TX1_TX_VOL_CTL, 0x00},
350 { CDC_TX1_TX_PATH_SEC0, 0x00},
351 { CDC_TX1_TX_PATH_SEC1, 0x00},
352 { CDC_TX1_TX_PATH_SEC2, 0x01},
353 { CDC_TX1_TX_PATH_SEC3, 0x3C},
354 { CDC_TX1_TX_PATH_SEC4, 0x20},
355 { CDC_TX1_TX_PATH_SEC5, 0x00},
356 { CDC_TX1_TX_PATH_SEC6, 0x00},
357 { CDC_TX2_TX_PATH_CTL, 0x04},
358 { CDC_TX2_TX_PATH_CFG0, 0x10},
359 { CDC_TX2_TX_PATH_CFG1, 0x0B},
360 { CDC_TX2_TX_VOL_CTL, 0x00},
361 { CDC_TX2_TX_PATH_SEC0, 0x00},
362 { CDC_TX2_TX_PATH_SEC1, 0x00},
363 { CDC_TX2_TX_PATH_SEC2, 0x01},
364 { CDC_TX2_TX_PATH_SEC3, 0x3C},
365 { CDC_TX2_TX_PATH_SEC4, 0x20},
366 { CDC_TX2_TX_PATH_SEC5, 0x00},
367 { CDC_TX2_TX_PATH_SEC6, 0x00},
368 { CDC_TX3_TX_PATH_CTL, 0x04},
369 { CDC_TX3_TX_PATH_CFG0, 0x10},
370 { CDC_TX3_TX_PATH_CFG1, 0x0B},
371 { CDC_TX3_TX_VOL_CTL, 0x00},
372 { CDC_TX3_TX_PATH_SEC0, 0x00},
373 { CDC_TX3_TX_PATH_SEC1, 0x00},
374 { CDC_TX3_TX_PATH_SEC2, 0x01},
375 { CDC_TX3_TX_PATH_SEC3, 0x3C},
376 { CDC_TX3_TX_PATH_SEC4, 0x20},
377 { CDC_TX3_TX_PATH_SEC5, 0x00},
378 { CDC_TX3_TX_PATH_SEC6, 0x00},
379 { CDC_TX4_TX_PATH_CTL, 0x04},
380 { CDC_TX4_TX_PATH_CFG0, 0x10},
381 { CDC_TX4_TX_PATH_CFG1, 0x0B},
382 { CDC_TX4_TX_VOL_CTL, 0x00},
383 { CDC_TX4_TX_PATH_SEC0, 0x00},
384 { CDC_TX4_TX_PATH_SEC1, 0x00},
385 { CDC_TX4_TX_PATH_SEC2, 0x01},
386 { CDC_TX4_TX_PATH_SEC3, 0x3C},
387 { CDC_TX4_TX_PATH_SEC4, 0x20},
388 { CDC_TX4_TX_PATH_SEC5, 0x00},
389 { CDC_TX4_TX_PATH_SEC6, 0x00},
390 { CDC_TX5_TX_PATH_CTL, 0x04},
391 { CDC_TX5_TX_PATH_CFG0, 0x10},
392 { CDC_TX5_TX_PATH_CFG1, 0x0B},
393 { CDC_TX5_TX_VOL_CTL, 0x00},
394 { CDC_TX5_TX_PATH_SEC0, 0x00},
395 { CDC_TX5_TX_PATH_SEC1, 0x00},
396 { CDC_TX5_TX_PATH_SEC2, 0x01},
397 { CDC_TX5_TX_PATH_SEC3, 0x3C},
398 { CDC_TX5_TX_PATH_SEC4, 0x20},
399 { CDC_TX5_TX_PATH_SEC5, 0x00},
400 { CDC_TX5_TX_PATH_SEC6, 0x00},
401 { CDC_TX6_TX_PATH_CTL, 0x04},
402 { CDC_TX6_TX_PATH_CFG0, 0x10},
403 { CDC_TX6_TX_PATH_CFG1, 0x0B},
404 { CDC_TX6_TX_VOL_CTL, 0x00},
405 { CDC_TX6_TX_PATH_SEC0, 0x00},
406 { CDC_TX6_TX_PATH_SEC1, 0x00},
407 { CDC_TX6_TX_PATH_SEC2, 0x01},
408 { CDC_TX6_TX_PATH_SEC3, 0x3C},
409 { CDC_TX6_TX_PATH_SEC4, 0x20},
410 { CDC_TX6_TX_PATH_SEC5, 0x00},
411 { CDC_TX6_TX_PATH_SEC6, 0x00},
412 { CDC_TX7_TX_PATH_CTL, 0x04},
413 { CDC_TX7_TX_PATH_CFG0, 0x10},
414 { CDC_TX7_TX_PATH_CFG1, 0x0B},
415 { CDC_TX7_TX_VOL_CTL, 0x00},
416 { CDC_TX7_TX_PATH_SEC0, 0x00},
417 { CDC_TX7_TX_PATH_SEC1, 0x00},
418 { CDC_TX7_TX_PATH_SEC2, 0x01},
419 { CDC_TX7_TX_PATH_SEC3, 0x3C},
420 { CDC_TX7_TX_PATH_SEC4, 0x20},
421 { CDC_TX7_TX_PATH_SEC5, 0x00},
422 { CDC_TX7_TX_PATH_SEC6, 0x00},
423};
424
425static bool tx_is_volatile_register(struct device *dev, unsigned int reg)
426{
427 /* Update volatile list for tx/tx macros */
428 switch (reg) {
429 case CDC_TX_TOP_CSR_SWR_DMIC0_CTL:
430 case CDC_TX_TOP_CSR_SWR_DMIC1_CTL:
431 case CDC_TX_TOP_CSR_SWR_DMIC2_CTL:
432 case CDC_TX_TOP_CSR_SWR_DMIC3_CTL:
433 return true;
434 }
435 return false;
436}
437
438static bool tx_is_rw_register(struct device *dev, unsigned int reg)
439{
440 switch (reg) {
441 case CDC_TX_CLK_RST_CTRL_MCLK_CONTROL:
442 case CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL:
443 case CDC_TX_CLK_RST_CTRL_SWR_CONTROL:
444 case CDC_TX_TOP_CSR_TOP_CFG0:
445 case CDC_TX_TOP_CSR_ANC_CFG:
446 case CDC_TX_TOP_CSR_SWR_CTRL:
447 case CDC_TX_TOP_CSR_FREQ_MCLK:
448 case CDC_TX_TOP_CSR_DEBUG_BUS:
449 case CDC_TX_TOP_CSR_DEBUG_EN:
450 case CDC_TX_TOP_CSR_TX_I2S_CTL:
451 case CDC_TX_TOP_CSR_I2S_CLK:
452 case CDC_TX_TOP_CSR_I2S_RESET:
453 case CDC_TX_TOP_CSR_SWR_DMIC0_CTL:
454 case CDC_TX_TOP_CSR_SWR_DMIC1_CTL:
455 case CDC_TX_TOP_CSR_SWR_DMIC2_CTL:
456 case CDC_TX_TOP_CSR_SWR_DMIC3_CTL:
457 case CDC_TX_TOP_CSR_SWR_AMIC0_CTL:
458 case CDC_TX_TOP_CSR_SWR_AMIC1_CTL:
459 case CDC_TX_ANC0_CLK_RESET_CTL:
460 case CDC_TX_ANC0_MODE_1_CTL:
461 case CDC_TX_ANC0_MODE_2_CTL:
462 case CDC_TX_ANC0_FF_SHIFT:
463 case CDC_TX_ANC0_FB_SHIFT:
464 case CDC_TX_ANC0_LPF_FF_A_CTL:
465 case CDC_TX_ANC0_LPF_FF_B_CTL:
466 case CDC_TX_ANC0_LPF_FB_CTL:
467 case CDC_TX_ANC0_SMLPF_CTL:
468 case CDC_TX_ANC0_DCFLT_SHIFT_CTL:
469 case CDC_TX_ANC0_IIR_ADAPT_CTL:
470 case CDC_TX_ANC0_IIR_COEFF_1_CTL:
471 case CDC_TX_ANC0_IIR_COEFF_2_CTL:
472 case CDC_TX_ANC0_FF_A_GAIN_CTL:
473 case CDC_TX_ANC0_FF_B_GAIN_CTL:
474 case CDC_TX_ANC0_FB_GAIN_CTL:
475 case CDC_TX_INP_MUX_ADC_MUX0_CFG0:
476 case CDC_TX_INP_MUX_ADC_MUX0_CFG1:
477 case CDC_TX_INP_MUX_ADC_MUX1_CFG0:
478 case CDC_TX_INP_MUX_ADC_MUX1_CFG1:
479 case CDC_TX_INP_MUX_ADC_MUX2_CFG0:
480 case CDC_TX_INP_MUX_ADC_MUX2_CFG1:
481 case CDC_TX_INP_MUX_ADC_MUX3_CFG0:
482 case CDC_TX_INP_MUX_ADC_MUX3_CFG1:
483 case CDC_TX_INP_MUX_ADC_MUX4_CFG0:
484 case CDC_TX_INP_MUX_ADC_MUX4_CFG1:
485 case CDC_TX_INP_MUX_ADC_MUX5_CFG0:
486 case CDC_TX_INP_MUX_ADC_MUX5_CFG1:
487 case CDC_TX_INP_MUX_ADC_MUX6_CFG0:
488 case CDC_TX_INP_MUX_ADC_MUX6_CFG1:
489 case CDC_TX_INP_MUX_ADC_MUX7_CFG0:
490 case CDC_TX_INP_MUX_ADC_MUX7_CFG1:
491 case CDC_TX0_TX_PATH_CTL:
492 case CDC_TX0_TX_PATH_CFG0:
493 case CDC_TX0_TX_PATH_CFG1:
494 case CDC_TX0_TX_VOL_CTL:
495 case CDC_TX0_TX_PATH_SEC0:
496 case CDC_TX0_TX_PATH_SEC1:
497 case CDC_TX0_TX_PATH_SEC2:
498 case CDC_TX0_TX_PATH_SEC3:
499 case CDC_TX0_TX_PATH_SEC4:
500 case CDC_TX0_TX_PATH_SEC5:
501 case CDC_TX0_TX_PATH_SEC6:
502 case CDC_TX0_TX_PATH_SEC7:
503 case CDC_TX1_TX_PATH_CTL:
504 case CDC_TX1_TX_PATH_CFG0:
505 case CDC_TX1_TX_PATH_CFG1:
506 case CDC_TX1_TX_VOL_CTL:
507 case CDC_TX1_TX_PATH_SEC0:
508 case CDC_TX1_TX_PATH_SEC1:
509 case CDC_TX1_TX_PATH_SEC2:
510 case CDC_TX1_TX_PATH_SEC3:
511 case CDC_TX1_TX_PATH_SEC4:
512 case CDC_TX1_TX_PATH_SEC5:
513 case CDC_TX1_TX_PATH_SEC6:
514 case CDC_TX2_TX_PATH_CTL:
515 case CDC_TX2_TX_PATH_CFG0:
516 case CDC_TX2_TX_PATH_CFG1:
517 case CDC_TX2_TX_VOL_CTL:
518 case CDC_TX2_TX_PATH_SEC0:
519 case CDC_TX2_TX_PATH_SEC1:
520 case CDC_TX2_TX_PATH_SEC2:
521 case CDC_TX2_TX_PATH_SEC3:
522 case CDC_TX2_TX_PATH_SEC4:
523 case CDC_TX2_TX_PATH_SEC5:
524 case CDC_TX2_TX_PATH_SEC6:
525 case CDC_TX3_TX_PATH_CTL:
526 case CDC_TX3_TX_PATH_CFG0:
527 case CDC_TX3_TX_PATH_CFG1:
528 case CDC_TX3_TX_VOL_CTL:
529 case CDC_TX3_TX_PATH_SEC0:
530 case CDC_TX3_TX_PATH_SEC1:
531 case CDC_TX3_TX_PATH_SEC2:
532 case CDC_TX3_TX_PATH_SEC3:
533 case CDC_TX3_TX_PATH_SEC4:
534 case CDC_TX3_TX_PATH_SEC5:
535 case CDC_TX3_TX_PATH_SEC6:
536 case CDC_TX4_TX_PATH_CTL:
537 case CDC_TX4_TX_PATH_CFG0:
538 case CDC_TX4_TX_PATH_CFG1:
539 case CDC_TX4_TX_VOL_CTL:
540 case CDC_TX4_TX_PATH_SEC0:
541 case CDC_TX4_TX_PATH_SEC1:
542 case CDC_TX4_TX_PATH_SEC2:
543 case CDC_TX4_TX_PATH_SEC3:
544 case CDC_TX4_TX_PATH_SEC4:
545 case CDC_TX4_TX_PATH_SEC5:
546 case CDC_TX4_TX_PATH_SEC6:
547 case CDC_TX5_TX_PATH_CTL:
548 case CDC_TX5_TX_PATH_CFG0:
549 case CDC_TX5_TX_PATH_CFG1:
550 case CDC_TX5_TX_VOL_CTL:
551 case CDC_TX5_TX_PATH_SEC0:
552 case CDC_TX5_TX_PATH_SEC1:
553 case CDC_TX5_TX_PATH_SEC2:
554 case CDC_TX5_TX_PATH_SEC3:
555 case CDC_TX5_TX_PATH_SEC4:
556 case CDC_TX5_TX_PATH_SEC5:
557 case CDC_TX5_TX_PATH_SEC6:
558 case CDC_TX6_TX_PATH_CTL:
559 case CDC_TX6_TX_PATH_CFG0:
560 case CDC_TX6_TX_PATH_CFG1:
561 case CDC_TX6_TX_VOL_CTL:
562 case CDC_TX6_TX_PATH_SEC0:
563 case CDC_TX6_TX_PATH_SEC1:
564 case CDC_TX6_TX_PATH_SEC2:
565 case CDC_TX6_TX_PATH_SEC3:
566 case CDC_TX6_TX_PATH_SEC4:
567 case CDC_TX6_TX_PATH_SEC5:
568 case CDC_TX6_TX_PATH_SEC6:
569 case CDC_TX7_TX_PATH_CTL:
570 case CDC_TX7_TX_PATH_CFG0:
571 case CDC_TX7_TX_PATH_CFG1:
572 case CDC_TX7_TX_VOL_CTL:
573 case CDC_TX7_TX_PATH_SEC0:
574 case CDC_TX7_TX_PATH_SEC1:
575 case CDC_TX7_TX_PATH_SEC2:
576 case CDC_TX7_TX_PATH_SEC3:
577 case CDC_TX7_TX_PATH_SEC4:
578 case CDC_TX7_TX_PATH_SEC5:
579 case CDC_TX7_TX_PATH_SEC6:
580 return true;
581 }
582
583 return false;
584}
585
586static const struct regmap_config tx_regmap_config = {
587 .name = "tx_macro",
588 .reg_bits = 16,
589 .val_bits = 32,
590 .reg_stride = 4,
591 .cache_type = REGCACHE_FLAT,
592 .max_register = TX_MAX_OFFSET,
593 .reg_defaults = tx_defaults,
594 .num_reg_defaults = ARRAY_SIZE(tx_defaults),
595 .writeable_reg = tx_is_rw_register,
596 .volatile_reg = tx_is_volatile_register,
597 .readable_reg = tx_is_rw_register,
598};
599
600static int tx_macro_mclk_enable(struct tx_macro *tx,
601 bool mclk_enable)
602{
603 struct regmap *regmap = tx->regmap;
604
605 if (mclk_enable) {
606 if (tx->tx_mclk_users == 0) {
607 /* 9.6MHz MCLK, set value 0x00 if other frequency */
608 regmap_update_bits(regmap, CDC_TX_TOP_CSR_FREQ_MCLK, 0x01, 0x01);
609 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_MCLK_CONTROL,
610 CDC_TX_MCLK_EN_MASK,
611 CDC_TX_MCLK_ENABLE);
612 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL,
613 CDC_TX_FS_CNT_EN_MASK,
614 CDC_TX_FS_CNT_ENABLE);
615 regcache_mark_dirty(regmap);
616 regcache_sync(regmap);
617 }
618 tx->tx_mclk_users++;
619 } else {
620 if (tx->tx_mclk_users <= 0) {
621 dev_err(tx->dev, "clock already disabled\n");
622 tx->tx_mclk_users = 0;
623 goto exit;
624 }
625 tx->tx_mclk_users--;
626 if (tx->tx_mclk_users == 0) {
627 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL,
628 CDC_TX_FS_CNT_EN_MASK, 0x0);
629 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_MCLK_CONTROL,
630 CDC_TX_MCLK_EN_MASK, 0x0);
631 }
632 }
633exit:
634 return 0;
635}
636
637static bool is_amic_enabled(struct snd_soc_component *component, int decimator)
638{
639 u16 adc_mux_reg, adc_reg, adc_n;
640
641 adc_mux_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG1(decimator);
642
643 if (snd_soc_component_read(component, adc_mux_reg) & SWR_MIC) {
644 adc_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG0(decimator);
645 adc_n = snd_soc_component_read_field(component, adc_reg,
646 CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK);
647 if (adc_n < TX_ADC_MAX)
648 return true;
649 }
650
651 return false;
652}
653
654static void tx_macro_tx_hpf_corner_freq_callback(struct work_struct *work)
655{
656 struct delayed_work *hpf_delayed_work;
657 struct hpf_work *hpf_work;
658 struct tx_macro *tx;
659 struct snd_soc_component *component;
660 u16 dec_cfg_reg, hpf_gate_reg;
661 u8 hpf_cut_off_freq;
662
663 hpf_delayed_work = to_delayed_work(work);
664 hpf_work = container_of(hpf_delayed_work, struct hpf_work, dwork);
665 tx = hpf_work->tx;
666 component = tx->component;
667 hpf_cut_off_freq = hpf_work->hpf_cut_off_freq;
668
669 dec_cfg_reg = CDC_TXn_TX_PATH_CFG0(hpf_work->decimator);
670 hpf_gate_reg = CDC_TXn_TX_PATH_SEC2(hpf_work->decimator);
671
672 if (is_amic_enabled(component, hpf_work->decimator)) {
673 snd_soc_component_write_field(component,
674 dec_cfg_reg,
675 CDC_TXn_HPF_CUT_FREQ_MASK,
676 hpf_cut_off_freq);
677 snd_soc_component_update_bits(component, hpf_gate_reg,
678 CDC_TXn_HPF_F_CHANGE_MASK |
679 CDC_TXn_HPF_ZERO_GATE_MASK,
680 0x02);
681 snd_soc_component_update_bits(component, hpf_gate_reg,
682 CDC_TXn_HPF_F_CHANGE_MASK |
683 CDC_TXn_HPF_ZERO_GATE_MASK,
684 0x01);
685 } else {
686 snd_soc_component_write_field(component, dec_cfg_reg,
687 CDC_TXn_HPF_CUT_FREQ_MASK,
688 hpf_cut_off_freq);
689 snd_soc_component_write_field(component, hpf_gate_reg,
690 CDC_TXn_HPF_F_CHANGE_MASK, 0x1);
691 /* Minimum 1 clk cycle delay is required as per HW spec */
692 usleep_range(1000, 1010);
693 snd_soc_component_write_field(component, hpf_gate_reg,
694 CDC_TXn_HPF_F_CHANGE_MASK, 0x0);
695 }
696}
697
698static void tx_macro_mute_update_callback(struct work_struct *work)
699{
700 struct tx_mute_work *tx_mute_dwork;
701 struct snd_soc_component *component;
702 struct tx_macro *tx;
703 struct delayed_work *delayed_work;
704 u8 decimator;
705
706 delayed_work = to_delayed_work(work);
707 tx_mute_dwork = container_of(delayed_work, struct tx_mute_work, dwork);
708 tx = tx_mute_dwork->tx;
709 component = tx->component;
710 decimator = tx_mute_dwork->decimator;
711
712 snd_soc_component_write_field(component, CDC_TXn_TX_PATH_CTL(decimator),
713 CDC_TXn_PGA_MUTE_MASK, 0x0);
714}
715
d207bdea
SK		 716static int tx_macro_mclk_event(struct snd_soc_dapm_widget *w,
717 struct snd_kcontrol *kcontrol, int event)
718{
719 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
720 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
721
722 switch (event) {
723 case SND_SOC_DAPM_PRE_PMU:
724 tx_macro_mclk_enable(tx, true);
725 break;
726 case SND_SOC_DAPM_POST_PMD:
727 tx_macro_mclk_enable(tx, false);
728 break;
729 default:
730 break;
731 }
732
733 return 0;
734}
735
736static int tx_macro_put_dec_enum(struct snd_kcontrol *kcontrol,
737 struct snd_ctl_elem_value *ucontrol)
738{
739 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
740 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
741 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
742 unsigned int val, dmic;
743 u16 mic_sel_reg;
744 u16 dmic_clk_reg;
745 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
746
747 val = ucontrol->value.enumerated.item[0];
748
749 switch (e->reg) {
750 case CDC_TX_INP_MUX_ADC_MUX0_CFG0:
751 mic_sel_reg = CDC_TX0_TX_PATH_CFG0;
752 break;
753 case CDC_TX_INP_MUX_ADC_MUX1_CFG0:
754 mic_sel_reg = CDC_TX1_TX_PATH_CFG0;
755 break;
756 case CDC_TX_INP_MUX_ADC_MUX2_CFG0:
757 mic_sel_reg = CDC_TX2_TX_PATH_CFG0;
758 break;
759 case CDC_TX_INP_MUX_ADC_MUX3_CFG0:
760 mic_sel_reg = CDC_TX3_TX_PATH_CFG0;
761 break;
762 case CDC_TX_INP_MUX_ADC_MUX4_CFG0:
763 mic_sel_reg = CDC_TX4_TX_PATH_CFG0;
764 break;
765 case CDC_TX_INP_MUX_ADC_MUX5_CFG0:
766 mic_sel_reg = CDC_TX5_TX_PATH_CFG0;
767 break;
768 case CDC_TX_INP_MUX_ADC_MUX6_CFG0:
769 mic_sel_reg = CDC_TX6_TX_PATH_CFG0;
770 break;
771 case CDC_TX_INP_MUX_ADC_MUX7_CFG0:
772 mic_sel_reg = CDC_TX7_TX_PATH_CFG0;
773 break;
774 }
775
776 if (val != 0) {
777 if (val < 5) {
778 snd_soc_component_write_field(component, mic_sel_reg,
779 CDC_TXn_ADC_DMIC_SEL_MASK, 0);
780 } else {
781 snd_soc_component_write_field(component, mic_sel_reg,
782 CDC_TXn_ADC_DMIC_SEL_MASK, 1);
783 dmic = TX_ADC_TO_DMIC(val);
784 dmic_clk_reg = CDC_TX_TOP_CSR_SWR_DMICn_CTL(dmic);
785 snd_soc_component_write_field(component, dmic_clk_reg,
786 CDC_TX_SWR_DMIC_CLK_SEL_MASK,
787 tx->dmic_clk_div);
788 }
789 }
790
791 return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
792}
793
794static int tx_macro_tx_mixer_get(struct snd_kcontrol *kcontrol,
795 struct snd_ctl_elem_value *ucontrol)
796{
797 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
798 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
799 struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value;
800 u32 dai_id = widget->shift;
801 u32 dec_id = mc->shift;
802 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
803
804 if (test_bit(dec_id, &tx->active_ch_mask[dai_id]))
805 ucontrol->value.integer.value[0] = 1;
806 else
807 ucontrol->value.integer.value[0] = 0;
808
809 return 0;
810}
811
812static int tx_macro_tx_mixer_put(struct snd_kcontrol *kcontrol,
813 struct snd_ctl_elem_value *ucontrol)
814{
815 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
816 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
817 struct snd_soc_dapm_update *update = NULL;
818 struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value;
819 u32 dai_id = widget->shift;
820 u32 dec_id = mc->shift;
821 u32 enable = ucontrol->value.integer.value[0];
822 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
823
824 if (enable) {
825 set_bit(dec_id, &tx->active_ch_mask[dai_id]);
826 tx->active_ch_cnt[dai_id]++;
827 tx->active_decimator[dai_id] = dec_id;
828 } else {
829 tx->active_ch_cnt[dai_id]--;
830 clear_bit(dec_id, &tx->active_ch_mask[dai_id]);
831 tx->active_decimator[dai_id] = -1;
832 }
833 snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, update);
834
835 return 0;
836}
837
838static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w,
839 struct snd_kcontrol *kcontrol, int event)
840{
841 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
842 unsigned int decimator;
843 u16 tx_vol_ctl_reg, dec_cfg_reg, hpf_gate_reg, tx_gain_ctl_reg;
844 u8 hpf_cut_off_freq;
845 int hpf_delay = TX_MACRO_DMIC_HPF_DELAY_MS;
846 int unmute_delay = TX_MACRO_DMIC_UNMUTE_DELAY_MS;
847 u16 adc_mux_reg, adc_reg, adc_n, dmic;
848 u16 dmic_clk_reg;
849 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
850
851 decimator = w->shift;
852 tx_vol_ctl_reg = CDC_TXn_TX_PATH_CTL(decimator);
853 hpf_gate_reg = CDC_TXn_TX_PATH_SEC2(decimator);
854 dec_cfg_reg = CDC_TXn_TX_PATH_CFG0(decimator);
855 tx_gain_ctl_reg = CDC_TXn_TX_VOL_CTL(decimator);
856
857 switch (event) {
858 case SND_SOC_DAPM_PRE_PMU:
859 adc_mux_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG1(decimator);
860 if (snd_soc_component_read(component, adc_mux_reg) & SWR_MIC) {
861 adc_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG0(decimator);
862 adc_n = snd_soc_component_read(component, adc_reg) &
863 CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK;
864 if (adc_n >= TX_ADC_MAX) {
865 dmic = TX_ADC_TO_DMIC(adc_n);
866 dmic_clk_reg = CDC_TX_TOP_CSR_SWR_DMICn_CTL(dmic);
867
868 snd_soc_component_write_field(component, dmic_clk_reg,
869 CDC_TX_SWR_DMIC_CLK_SEL_MASK,
870 tx->dmic_clk_div);
871 }
872 }
873 snd_soc_component_write_field(component, dec_cfg_reg,
874 CDC_TXn_ADC_MODE_MASK,
875 tx->dec_mode[decimator]);
876 /* Enable TX PGA Mute */
877 snd_soc_component_write_field(component, tx_vol_ctl_reg,
878 CDC_TXn_PGA_MUTE_MASK, 0x1);
879 break;
880 case SND_SOC_DAPM_POST_PMU:
881 snd_soc_component_write_field(component, tx_vol_ctl_reg,
882 CDC_TXn_CLK_EN_MASK, 0x1);
883 if (!is_amic_enabled(component, decimator)) {
884 snd_soc_component_update_bits(component, hpf_gate_reg, 0x01, 0x00);
885 /* Minimum 1 clk cycle delay is required as per HW spec */
886 usleep_range(1000, 1010);
887 }
888 hpf_cut_off_freq = snd_soc_component_read_field(component, dec_cfg_reg,
889 CDC_TXn_HPF_CUT_FREQ_MASK);
890
891 tx->tx_hpf_work[decimator].hpf_cut_off_freq =
892 hpf_cut_off_freq;
893
894 if (hpf_cut_off_freq != CF_MIN_3DB_150HZ)
895 snd_soc_component_write_field(component, dec_cfg_reg,
896 CDC_TXn_HPF_CUT_FREQ_MASK,
897 CF_MIN_3DB_150HZ);
898
899 if (is_amic_enabled(component, decimator)) {
900 hpf_delay = TX_MACRO_AMIC_HPF_DELAY_MS;
901 unmute_delay = TX_MACRO_AMIC_UNMUTE_DELAY_MS;
902 }
903 /* schedule work queue to Remove Mute */
904 queue_delayed_work(system_freezable_wq,
905 &tx->tx_mute_dwork[decimator].dwork,
906 msecs_to_jiffies(unmute_delay));
907 if (tx->tx_hpf_work[decimator].hpf_cut_off_freq != CF_MIN_3DB_150HZ) {
908 queue_delayed_work(system_freezable_wq,
909 &tx->tx_hpf_work[decimator].dwork,
910 msecs_to_jiffies(hpf_delay));
911 snd_soc_component_update_bits(component, hpf_gate_reg,
912 CDC_TXn_HPF_F_CHANGE_MASK |
913 CDC_TXn_HPF_ZERO_GATE_MASK,
914 0x02);
915 if (!is_amic_enabled(component, decimator))
916 snd_soc_component_update_bits(component, hpf_gate_reg,
917 CDC_TXn_HPF_F_CHANGE_MASK |
918 CDC_TXn_HPF_ZERO_GATE_MASK,
919 0x00);
920 snd_soc_component_update_bits(component, hpf_gate_reg,
921 CDC_TXn_HPF_F_CHANGE_MASK |
922 CDC_TXn_HPF_ZERO_GATE_MASK,
923 0x01);
924
925 /*
926 * 6ms delay is required as per HW spec
927 */
928 usleep_range(6000, 6010);
929 }
930 /* apply gain after decimator is enabled */
931 snd_soc_component_write(component, tx_gain_ctl_reg,
932 snd_soc_component_read(component,
933 tx_gain_ctl_reg));
934 if (tx->bcs_enable) {
935 snd_soc_component_update_bits(component, dec_cfg_reg,
936 0x01, 0x01);
937 tx->bcs_clk_en = true;
938 }
939 break;
940 case SND_SOC_DAPM_PRE_PMD:
941 hpf_cut_off_freq =
942 tx->tx_hpf_work[decimator].hpf_cut_off_freq;
943 snd_soc_component_write_field(component, tx_vol_ctl_reg,
944 CDC_TXn_PGA_MUTE_MASK, 0x1);
945 if (cancel_delayed_work_sync(
946 &tx->tx_hpf_work[decimator].dwork)) {
947 if (hpf_cut_off_freq != CF_MIN_3DB_150HZ) {
948 snd_soc_component_write_field(
949 component, dec_cfg_reg,
950 CDC_TXn_HPF_CUT_FREQ_MASK,
951 hpf_cut_off_freq);
952 if (is_amic_enabled(component, decimator))
953 snd_soc_component_update_bits(component,
954 hpf_gate_reg,
955 CDC_TXn_HPF_F_CHANGE_MASK |
956 CDC_TXn_HPF_ZERO_GATE_MASK,
957 0x02);
958 else
959 snd_soc_component_update_bits(component,
960 hpf_gate_reg,
961 CDC_TXn_HPF_F_CHANGE_MASK |
962 CDC_TXn_HPF_ZERO_GATE_MASK,
963 0x03);
964
965 /*
966 * Minimum 1 clk cycle delay is required
967 * as per HW spec
968 */
969 usleep_range(1000, 1010);
970 snd_soc_component_update_bits(component, hpf_gate_reg,
971 CDC_TXn_HPF_F_CHANGE_MASK |
972 CDC_TXn_HPF_ZERO_GATE_MASK,
973 0x1);
974 }
975 }
976 cancel_delayed_work_sync(&tx->tx_mute_dwork[decimator].dwork);
977 break;
978 case SND_SOC_DAPM_POST_PMD:
979 snd_soc_component_write_field(component, tx_vol_ctl_reg,
980 CDC_TXn_CLK_EN_MASK, 0x0);
981 snd_soc_component_write_field(component, dec_cfg_reg,
982 CDC_TXn_ADC_MODE_MASK, 0x0);
983 snd_soc_component_write_field(component, tx_vol_ctl_reg,
984 CDC_TXn_PGA_MUTE_MASK, 0x0);
985 if (tx->bcs_enable) {
986 snd_soc_component_write_field(component, dec_cfg_reg,
987 CDC_TXn_PH_EN_MASK, 0x0);
988 snd_soc_component_write_field(component,
989 CDC_TX0_TX_PATH_SEC7,
990 CDC_TX0_MBHC_CTL_EN_MASK,
991 0x0);
992 tx->bcs_clk_en = false;
993 }
994 break;
995 }
996 return 0;
997}
998
c39667dd
SK		 999static int tx_macro_dec_mode_get(struct snd_kcontrol *kcontrol,
1000 struct snd_ctl_elem_value *ucontrol)
1001{
1002 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1003 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1004 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1005 int path = e->shift_l;
1006
1007 ucontrol->value.integer.value[0] = tx->dec_mode[path];
1008
1009 return 0;
1010}
1011
1012static int tx_macro_dec_mode_put(struct snd_kcontrol *kcontrol,
1013 struct snd_ctl_elem_value *ucontrol)
1014{
1015 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1016 int value = ucontrol->value.integer.value[0];
1017 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1018 int path = e->shift_l;
1019 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1020
1021 tx->dec_mode[path] = value;
1022
1023 return 0;
1024}
1025
1026static int tx_macro_get_bcs(struct snd_kcontrol *kcontrol,
1027 struct snd_ctl_elem_value *ucontrol)
1028{
1029 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1030 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1031
1032 ucontrol->value.integer.value[0] = tx->bcs_enable;
1033
1034 return 0;
1035}
1036
1037static int tx_macro_set_bcs(struct snd_kcontrol *kcontrol,
1038 struct snd_ctl_elem_value *ucontrol)
1039{
1040 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1041 int value = ucontrol->value.integer.value[0];
1042 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1043
1044 tx->bcs_enable = value;
1045
1046 return 0;
1047}
1048
1049static int tx_macro_hw_params(struct snd_pcm_substream *substream,
1050 struct snd_pcm_hw_params *params,
1051 struct snd_soc_dai *dai)
1052{
1053 struct snd_soc_component *component = dai->component;
1054 u32 decimator, sample_rate;
1055 int tx_fs_rate;
1056 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1057
1058 sample_rate = params_rate(params);
1059 switch (sample_rate) {
1060 case 8000:
1061 tx_fs_rate = 0;
1062 break;
1063 case 16000:
1064 tx_fs_rate = 1;
1065 break;
1066 case 32000:
1067 tx_fs_rate = 3;
1068 break;
1069 case 48000:
1070 tx_fs_rate = 4;
1071 break;
1072 case 96000:
1073 tx_fs_rate = 5;
1074 break;
1075 case 192000:
1076 tx_fs_rate = 6;
1077 break;
1078 case 384000:
1079 tx_fs_rate = 7;
1080 break;
1081 default:
1082 dev_err(component->dev, "%s: Invalid TX sample rate: %d\n",
1083 __func__, params_rate(params));
1084 return -EINVAL;
1085 }
1086
1087 for_each_set_bit(decimator, &tx->active_ch_mask[dai->id], TX_MACRO_DEC_MAX)
1088 snd_soc_component_update_bits(component, CDC_TXn_TX_PATH_CTL(decimator),
1089 CDC_TXn_PCM_RATE_MASK,
1090 tx_fs_rate);
1091 return 0;
1092}
1093
1094static int tx_macro_get_channel_map(struct snd_soc_dai *dai,
1095 unsigned int *tx_num, unsigned int *tx_slot,
1096 unsigned int *rx_num, unsigned int *rx_slot)
1097{
1098 struct snd_soc_component *component = dai->component;
1099 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1100
1101 switch (dai->id) {
1102 case TX_MACRO_AIF1_CAP:
1103 case TX_MACRO_AIF2_CAP:
1104 case TX_MACRO_AIF3_CAP:
1105 *tx_slot = tx->active_ch_mask[dai->id];
1106 *tx_num = tx->active_ch_cnt[dai->id];
1107 break;
1108 default:
1109 break;
1110 }
1111 return 0;
1112}
1113
1114static int tx_macro_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
1115{
1116 struct snd_soc_component *component = dai->component;
1117 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1118 u16 decimator;
1119
1c6a7f52
SK		 1120 /* active decimator not set yet */
1121 if (tx->active_decimator[dai->id] == -1)
1122 return 0;
1123
c39667dd
SK		 1124 decimator = tx->active_decimator[dai->id];
1125
1126 if (mute)
1127 snd_soc_component_write_field(component,
1128 CDC_TXn_TX_PATH_CTL(decimator),
1129 CDC_TXn_PGA_MUTE_MASK, 0x1);
1130 else
1131 snd_soc_component_update_bits(component,
1132 CDC_TXn_TX_PATH_CTL(decimator),
1133 CDC_TXn_PGA_MUTE_MASK, 0x0);
1134
1135 return 0;
1136}
1137
81df40a0 1138static const struct snd_soc_dai_ops tx_macro_dai_ops = {
c39667dd
SK		 1139 .hw_params = tx_macro_hw_params,
1140 .get_channel_map = tx_macro_get_channel_map,
1141 .mute_stream = tx_macro_digital_mute,
1142};
1143
1144static struct snd_soc_dai_driver tx_macro_dai[] = {
1145 {
1146 .name = "tx_macro_tx1",
1147 .id = TX_MACRO_AIF1_CAP,
1148 .capture = {
1149 .stream_name = "TX_AIF1 Capture",
1150 .rates = TX_MACRO_RATES,
1151 .formats = TX_MACRO_FORMATS,
1152 .rate_max = 192000,
1153 .rate_min = 8000,
1154 .channels_min = 1,
1155 .channels_max = 8,
1156 },
1157 .ops = &tx_macro_dai_ops,
1158 },
1159 {
1160 .name = "tx_macro_tx2",
1161 .id = TX_MACRO_AIF2_CAP,
1162 .capture = {
1163 .stream_name = "TX_AIF2 Capture",
1164 .rates = TX_MACRO_RATES,
1165 .formats = TX_MACRO_FORMATS,
1166 .rate_max = 192000,
1167 .rate_min = 8000,
1168 .channels_min = 1,
1169 .channels_max = 8,
1170 },
1171 .ops = &tx_macro_dai_ops,
1172 },
1173 {
1174 .name = "tx_macro_tx3",
1175 .id = TX_MACRO_AIF3_CAP,
1176 .capture = {
1177 .stream_name = "TX_AIF3 Capture",
1178 .rates = TX_MACRO_RATES,
1179 .formats = TX_MACRO_FORMATS,
1180 .rate_max = 192000,
1181 .rate_min = 8000,
1182 .channels_min = 1,
1183 .channels_max = 8,
1184 },
1185 .ops = &tx_macro_dai_ops,
1186 },
1187};
1188
d207bdea
SK		 1189static const char * const adc_mux_text[] = {
1190 "MSM_DMIC", "SWR_MIC", "ANC_FB_TUNE1"
1191};
1192
1193static SOC_ENUM_SINGLE_DECL(tx_dec0_enum, CDC_TX_INP_MUX_ADC_MUX0_CFG1,
1194 0, adc_mux_text);
1195static SOC_ENUM_SINGLE_DECL(tx_dec1_enum, CDC_TX_INP_MUX_ADC_MUX1_CFG1,
1196 0, adc_mux_text);
1197static SOC_ENUM_SINGLE_DECL(tx_dec2_enum, CDC_TX_INP_MUX_ADC_MUX2_CFG1,
1198 0, adc_mux_text);
1199static SOC_ENUM_SINGLE_DECL(tx_dec3_enum, CDC_TX_INP_MUX_ADC_MUX3_CFG1,
1200 0, adc_mux_text);
1201static SOC_ENUM_SINGLE_DECL(tx_dec4_enum, CDC_TX_INP_MUX_ADC_MUX4_CFG1,
1202 0, adc_mux_text);
1203static SOC_ENUM_SINGLE_DECL(tx_dec5_enum, CDC_TX_INP_MUX_ADC_MUX5_CFG1,
1204 0, adc_mux_text);
1205static SOC_ENUM_SINGLE_DECL(tx_dec6_enum, CDC_TX_INP_MUX_ADC_MUX6_CFG1,
1206 0, adc_mux_text);
1207static SOC_ENUM_SINGLE_DECL(tx_dec7_enum, CDC_TX_INP_MUX_ADC_MUX7_CFG1,
1208 0, adc_mux_text);
1209
1210static const struct snd_kcontrol_new tx_dec0_mux = SOC_DAPM_ENUM("tx_dec0", tx_dec0_enum);
1211static const struct snd_kcontrol_new tx_dec1_mux = SOC_DAPM_ENUM("tx_dec1", tx_dec1_enum);
1212static const struct snd_kcontrol_new tx_dec2_mux = SOC_DAPM_ENUM("tx_dec2", tx_dec2_enum);
1213static const struct snd_kcontrol_new tx_dec3_mux = SOC_DAPM_ENUM("tx_dec3", tx_dec3_enum);
1214static const struct snd_kcontrol_new tx_dec4_mux = SOC_DAPM_ENUM("tx_dec4", tx_dec4_enum);
1215static const struct snd_kcontrol_new tx_dec5_mux = SOC_DAPM_ENUM("tx_dec5", tx_dec5_enum);
1216static const struct snd_kcontrol_new tx_dec6_mux = SOC_DAPM_ENUM("tx_dec6", tx_dec6_enum);
1217static const struct snd_kcontrol_new tx_dec7_mux = SOC_DAPM_ENUM("tx_dec7", tx_dec7_enum);
1218
1219static const char * const smic_mux_text[] = {
1220 "ZERO", "ADC0", "ADC1", "ADC2", "ADC3", "SWR_DMIC0",
1221 "SWR_DMIC1", "SWR_DMIC2", "SWR_DMIC3", "SWR_DMIC4",
1222 "SWR_DMIC5", "SWR_DMIC6", "SWR_DMIC7"
1223};
1224
1225static SOC_ENUM_SINGLE_DECL(tx_smic0_enum, CDC_TX_INP_MUX_ADC_MUX0_CFG0,
1226 0, smic_mux_text);
1227
1228static SOC_ENUM_SINGLE_DECL(tx_smic1_enum, CDC_TX_INP_MUX_ADC_MUX1_CFG0,
1229 0, smic_mux_text);
1230
1231static SOC_ENUM_SINGLE_DECL(tx_smic2_enum, CDC_TX_INP_MUX_ADC_MUX2_CFG0,
1232 0, smic_mux_text);
1233
1234static SOC_ENUM_SINGLE_DECL(tx_smic3_enum, CDC_TX_INP_MUX_ADC_MUX3_CFG0,
1235 0, smic_mux_text);
1236
1237static SOC_ENUM_SINGLE_DECL(tx_smic4_enum, CDC_TX_INP_MUX_ADC_MUX4_CFG0,
1238 0, smic_mux_text);
1239
1240static SOC_ENUM_SINGLE_DECL(tx_smic5_enum, CDC_TX_INP_MUX_ADC_MUX5_CFG0,
1241 0, smic_mux_text);
1242
1243static SOC_ENUM_SINGLE_DECL(tx_smic6_enum, CDC_TX_INP_MUX_ADC_MUX6_CFG0,
1244 0, smic_mux_text);
1245
1246static SOC_ENUM_SINGLE_DECL(tx_smic7_enum, CDC_TX_INP_MUX_ADC_MUX7_CFG0,
1247 0, smic_mux_text);
1248
1249static const struct snd_kcontrol_new tx_smic0_mux = SOC_DAPM_ENUM_EXT("tx_smic0", tx_smic0_enum,
1250 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1251static const struct snd_kcontrol_new tx_smic1_mux = SOC_DAPM_ENUM_EXT("tx_smic1", tx_smic1_enum,
1252 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1253static const struct snd_kcontrol_new tx_smic2_mux = SOC_DAPM_ENUM_EXT("tx_smic2", tx_smic2_enum,
1254 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1255static const struct snd_kcontrol_new tx_smic3_mux = SOC_DAPM_ENUM_EXT("tx_smic3", tx_smic3_enum,
1256 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1257static const struct snd_kcontrol_new tx_smic4_mux = SOC_DAPM_ENUM_EXT("tx_smic4", tx_smic4_enum,
1258 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1259static const struct snd_kcontrol_new tx_smic5_mux = SOC_DAPM_ENUM_EXT("tx_smic5", tx_smic5_enum,
1260 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1261static const struct snd_kcontrol_new tx_smic6_mux = SOC_DAPM_ENUM_EXT("tx_smic6", tx_smic6_enum,
1262 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1263static const struct snd_kcontrol_new tx_smic7_mux = SOC_DAPM_ENUM_EXT("tx_smic7", tx_smic7_enum,
1264 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1265
c39667dd
SK		 1266static const char * const dec_mode_mux_text[] = {
1267 "ADC_DEFAULT", "ADC_LOW_PWR", "ADC_HIGH_PERF",
1268};
1269
1270static const struct soc_enum dec_mode_mux_enum[] = {
1271 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(dec_mode_mux_text),
1272 dec_mode_mux_text),
1273 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(dec_mode_mux_text),
1274 dec_mode_mux_text),
1275 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(dec_mode_mux_text),
1276 dec_mode_mux_text),
1277 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(dec_mode_mux_text),
1278 dec_mode_mux_text),
1279 SOC_ENUM_SINGLE(SND_SOC_NOPM, 4, ARRAY_SIZE(dec_mode_mux_text),
1280 dec_mode_mux_text),
1281 SOC_ENUM_SINGLE(SND_SOC_NOPM, 5, ARRAY_SIZE(dec_mode_mux_text),
1282 dec_mode_mux_text),
1283 SOC_ENUM_SINGLE(SND_SOC_NOPM, 6, ARRAY_SIZE(dec_mode_mux_text),
1284 dec_mode_mux_text),
1285 SOC_ENUM_SINGLE(SND_SOC_NOPM, 7, ARRAY_SIZE(dec_mode_mux_text),
1286 dec_mode_mux_text),
1287};
1288
d207bdea
SK		 1289static const struct snd_kcontrol_new tx_aif1_cap_mixer[] = {
1290 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0,
1291 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1292 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0,
1293 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1294 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0,
1295 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1296 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0,
1297 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1298 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0,
1299 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1300 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0,
1301 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1302 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0,
1303 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1304 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0,
1305 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1306};
1307
1308static const struct snd_kcontrol_new tx_aif2_cap_mixer[] = {
1309 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0,
1310 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1311 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0,
1312 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1313 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0,
1314 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1315 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0,
1316 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1317 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0,
1318 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1319 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0,
1320 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1321 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0,
1322 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1323 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0,
1324 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1325};
1326
1327static const struct snd_kcontrol_new tx_aif3_cap_mixer[] = {
1328 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0,
1329 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1330 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0,
1331 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1332 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0,
1333 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1334 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0,
1335 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1336 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0,
1337 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1338 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0,
1339 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1340 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0,
1341 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1342 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0,
1343 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1344};
1345
1346static const struct snd_soc_dapm_widget tx_macro_dapm_widgets[] = {
1347 SND_SOC_DAPM_AIF_OUT("TX_AIF1 CAP", "TX_AIF1 Capture", 0,
1348 SND_SOC_NOPM, TX_MACRO_AIF1_CAP, 0),
1349
1350 SND_SOC_DAPM_AIF_OUT("TX_AIF2 CAP", "TX_AIF2 Capture", 0,
1351 SND_SOC_NOPM, TX_MACRO_AIF2_CAP, 0),
1352
1353 SND_SOC_DAPM_AIF_OUT("TX_AIF3 CAP", "TX_AIF3 Capture", 0,
1354 SND_SOC_NOPM, TX_MACRO_AIF3_CAP, 0),
1355
1356 SND_SOC_DAPM_MIXER("TX_AIF1_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF1_CAP, 0,
1357 tx_aif1_cap_mixer, ARRAY_SIZE(tx_aif1_cap_mixer)),
1358
1359 SND_SOC_DAPM_MIXER("TX_AIF2_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF2_CAP, 0,
1360 tx_aif2_cap_mixer, ARRAY_SIZE(tx_aif2_cap_mixer)),
1361
1362 SND_SOC_DAPM_MIXER("TX_AIF3_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF3_CAP, 0,
1363 tx_aif3_cap_mixer, ARRAY_SIZE(tx_aif3_cap_mixer)),
1364
1365 SND_SOC_DAPM_MUX("TX SMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_smic0_mux),
1366 SND_SOC_DAPM_MUX("TX SMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_smic1_mux),
1367 SND_SOC_DAPM_MUX("TX SMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_smic2_mux),
1368 SND_SOC_DAPM_MUX("TX SMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_smic3_mux),
1369 SND_SOC_DAPM_MUX("TX SMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_smic4_mux),
1370 SND_SOC_DAPM_MUX("TX SMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_smic5_mux),
1371 SND_SOC_DAPM_MUX("TX SMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_smic6_mux),
1372 SND_SOC_DAPM_MUX("TX SMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_smic7_mux),
1373
1374 SND_SOC_DAPM_INPUT("TX SWR_ADC0"),
1375 SND_SOC_DAPM_INPUT("TX SWR_ADC1"),
1376 SND_SOC_DAPM_INPUT("TX SWR_ADC2"),
1377 SND_SOC_DAPM_INPUT("TX SWR_ADC3"),
1378 SND_SOC_DAPM_INPUT("TX SWR_DMIC0"),
1379 SND_SOC_DAPM_INPUT("TX SWR_DMIC1"),
1380 SND_SOC_DAPM_INPUT("TX SWR_DMIC2"),
1381 SND_SOC_DAPM_INPUT("TX SWR_DMIC3"),
1382 SND_SOC_DAPM_INPUT("TX SWR_DMIC4"),
1383 SND_SOC_DAPM_INPUT("TX SWR_DMIC5"),
1384 SND_SOC_DAPM_INPUT("TX SWR_DMIC6"),
1385 SND_SOC_DAPM_INPUT("TX SWR_DMIC7"),
1386
1387 SND_SOC_DAPM_MUX_E("TX DEC0 MUX", SND_SOC_NOPM,
1388 TX_MACRO_DEC0, 0,
1389 &tx_dec0_mux, tx_macro_enable_dec,
1390 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1391 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1392
1393 SND_SOC_DAPM_MUX_E("TX DEC1 MUX", SND_SOC_NOPM,
1394 TX_MACRO_DEC1, 0,
1395 &tx_dec1_mux, tx_macro_enable_dec,
1396 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1397 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1398
1399 SND_SOC_DAPM_MUX_E("TX DEC2 MUX", SND_SOC_NOPM,
1400 TX_MACRO_DEC2, 0,
1401 &tx_dec2_mux, tx_macro_enable_dec,
1402 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1403 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1404
1405 SND_SOC_DAPM_MUX_E("TX DEC3 MUX", SND_SOC_NOPM,
1406 TX_MACRO_DEC3, 0,
1407 &tx_dec3_mux, tx_macro_enable_dec,
1408 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1409 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1410
1411 SND_SOC_DAPM_MUX_E("TX DEC4 MUX", SND_SOC_NOPM,
1412 TX_MACRO_DEC4, 0,
1413 &tx_dec4_mux, tx_macro_enable_dec,
1414 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1415 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1416
1417 SND_SOC_DAPM_MUX_E("TX DEC5 MUX", SND_SOC_NOPM,
1418 TX_MACRO_DEC5, 0,
1419 &tx_dec5_mux, tx_macro_enable_dec,
1420 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1421 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1422
1423 SND_SOC_DAPM_MUX_E("TX DEC6 MUX", SND_SOC_NOPM,
1424 TX_MACRO_DEC6, 0,
1425 &tx_dec6_mux, tx_macro_enable_dec,
1426 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1427 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1428
1429 SND_SOC_DAPM_MUX_E("TX DEC7 MUX", SND_SOC_NOPM,
1430 TX_MACRO_DEC7, 0,
1431 &tx_dec7_mux, tx_macro_enable_dec,
1432 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1433 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1434
1435 SND_SOC_DAPM_SUPPLY_S("TX_MCLK", 0, SND_SOC_NOPM, 0, 0,
1436 tx_macro_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1437
1438 SND_SOC_DAPM_SUPPLY_S("TX_SWR_CLK", 0, SND_SOC_NOPM, 0, 0, NULL, 0),
1439
1440 SND_SOC_DAPM_SUPPLY_S("VA_SWR_CLK", 0, SND_SOC_NOPM, 0, 0,
1441 NULL, 0),
1442};
1443
1444static const struct snd_soc_dapm_route tx_audio_map[] = {
1445 {"TX_AIF1 CAP", NULL, "TX_MCLK"},
1446 {"TX_AIF2 CAP", NULL, "TX_MCLK"},
1447 {"TX_AIF3 CAP", NULL, "TX_MCLK"},
1448
1449 {"TX_AIF1 CAP", NULL, "TX_AIF1_CAP Mixer"},
1450 {"TX_AIF2 CAP", NULL, "TX_AIF2_CAP Mixer"},
1451 {"TX_AIF3 CAP", NULL, "TX_AIF3_CAP Mixer"},
1452
1453 {"TX_AIF1_CAP Mixer", "DEC0", "TX DEC0 MUX"},
1454 {"TX_AIF1_CAP Mixer", "DEC1", "TX DEC1 MUX"},
1455 {"TX_AIF1_CAP Mixer", "DEC2", "TX DEC2 MUX"},
1456 {"TX_AIF1_CAP Mixer", "DEC3", "TX DEC3 MUX"},
1457 {"TX_AIF1_CAP Mixer", "DEC4", "TX DEC4 MUX"},
1458 {"TX_AIF1_CAP Mixer", "DEC5", "TX DEC5 MUX"},
1459 {"TX_AIF1_CAP Mixer", "DEC6", "TX DEC6 MUX"},
1460 {"TX_AIF1_CAP Mixer", "DEC7", "TX DEC7 MUX"},
1461
1462 {"TX_AIF2_CAP Mixer", "DEC0", "TX DEC0 MUX"},
1463 {"TX_AIF2_CAP Mixer", "DEC1", "TX DEC1 MUX"},
1464 {"TX_AIF2_CAP Mixer", "DEC2", "TX DEC2 MUX"},
1465 {"TX_AIF2_CAP Mixer", "DEC3", "TX DEC3 MUX"},
1466 {"TX_AIF2_CAP Mixer", "DEC4", "TX DEC4 MUX"},
1467 {"TX_AIF2_CAP Mixer", "DEC5", "TX DEC5 MUX"},
1468 {"TX_AIF2_CAP Mixer", "DEC6", "TX DEC6 MUX"},
1469 {"TX_AIF2_CAP Mixer", "DEC7", "TX DEC7 MUX"},
1470
1471 {"TX_AIF3_CAP Mixer", "DEC0", "TX DEC0 MUX"},
1472 {"TX_AIF3_CAP Mixer", "DEC1", "TX DEC1 MUX"},
1473 {"TX_AIF3_CAP Mixer", "DEC2", "TX DEC2 MUX"},
1474 {"TX_AIF3_CAP Mixer", "DEC3", "TX DEC3 MUX"},
1475 {"TX_AIF3_CAP Mixer", "DEC4", "TX DEC4 MUX"},
1476 {"TX_AIF3_CAP Mixer", "DEC5", "TX DEC5 MUX"},
1477 {"TX_AIF3_CAP Mixer", "DEC6", "TX DEC6 MUX"},
1478 {"TX_AIF3_CAP Mixer", "DEC7", "TX DEC7 MUX"},
1479
1480 {"TX DEC0 MUX", NULL, "TX_MCLK"},
1481 {"TX DEC1 MUX", NULL, "TX_MCLK"},
1482 {"TX DEC2 MUX", NULL, "TX_MCLK"},
1483 {"TX DEC3 MUX", NULL, "TX_MCLK"},
1484 {"TX DEC4 MUX", NULL, "TX_MCLK"},
1485 {"TX DEC5 MUX", NULL, "TX_MCLK"},
1486 {"TX DEC6 MUX", NULL, "TX_MCLK"},
1487 {"TX DEC7 MUX", NULL, "TX_MCLK"},
1488
1489 {"TX DEC0 MUX", "SWR_MIC", "TX SMIC MUX0"},
1490 {"TX SMIC MUX0", NULL, "TX_SWR_CLK"},
1491 {"TX SMIC MUX0", "ADC0", "TX SWR_ADC0"},
1492 {"TX SMIC MUX0", "ADC1", "TX SWR_ADC1"},
1493 {"TX SMIC MUX0", "ADC2", "TX SWR_ADC2"},
1494 {"TX SMIC MUX0", "ADC3", "TX SWR_ADC3"},
1495 {"TX SMIC MUX0", "SWR_DMIC0", "TX SWR_DMIC0"},
1496 {"TX SMIC MUX0", "SWR_DMIC1", "TX SWR_DMIC1"},
1497 {"TX SMIC MUX0", "SWR_DMIC2", "TX SWR_DMIC2"},
1498 {"TX SMIC MUX0", "SWR_DMIC3", "TX SWR_DMIC3"},
1499 {"TX SMIC MUX0", "SWR_DMIC4", "TX SWR_DMIC4"},
1500 {"TX SMIC MUX0", "SWR_DMIC5", "TX SWR_DMIC5"},
1501 {"TX SMIC MUX0", "SWR_DMIC6", "TX SWR_DMIC6"},
1502 {"TX SMIC MUX0", "SWR_DMIC7", "TX SWR_DMIC7"},
1503
1504 {"TX DEC1 MUX", "SWR_MIC", "TX SMIC MUX1"},
1505 {"TX SMIC MUX1", NULL, "TX_SWR_CLK"},
1506 {"TX SMIC MUX1", "ADC0", "TX SWR_ADC0"},
1507 {"TX SMIC MUX1", "ADC1", "TX SWR_ADC1"},
1508 {"TX SMIC MUX1", "ADC2", "TX SWR_ADC2"},
1509 {"TX SMIC MUX1", "ADC3", "TX SWR_ADC3"},
1510 {"TX SMIC MUX1", "SWR_DMIC0", "TX SWR_DMIC0"},
1511 {"TX SMIC MUX1", "SWR_DMIC1", "TX SWR_DMIC1"},
1512 {"TX SMIC MUX1", "SWR_DMIC2", "TX SWR_DMIC2"},
1513 {"TX SMIC MUX1", "SWR_DMIC3", "TX SWR_DMIC3"},
1514 {"TX SMIC MUX1", "SWR_DMIC4", "TX SWR_DMIC4"},
1515 {"TX SMIC MUX1", "SWR_DMIC5", "TX SWR_DMIC5"},
1516 {"TX SMIC MUX1", "SWR_DMIC6", "TX SWR_DMIC6"},
1517 {"TX SMIC MUX1", "SWR_DMIC7", "TX SWR_DMIC7"},
1518
1519 {"TX DEC2 MUX", "SWR_MIC", "TX SMIC MUX2"},
1520 {"TX SMIC MUX2", NULL, "TX_SWR_CLK"},
1521 {"TX SMIC MUX2", "ADC0", "TX SWR_ADC0"},
1522 {"TX SMIC MUX2", "ADC1", "TX SWR_ADC1"},
1523 {"TX SMIC MUX2", "ADC2", "TX SWR_ADC2"},
1524 {"TX SMIC MUX2", "ADC3", "TX SWR_ADC3"},
1525 {"TX SMIC MUX2", "SWR_DMIC0", "TX SWR_DMIC0"},
1526 {"TX SMIC MUX2", "SWR_DMIC1", "TX SWR_DMIC1"},
1527 {"TX SMIC MUX2", "SWR_DMIC2", "TX SWR_DMIC2"},
1528 {"TX SMIC MUX2", "SWR_DMIC3", "TX SWR_DMIC3"},
1529 {"TX SMIC MUX2", "SWR_DMIC4", "TX SWR_DMIC4"},
1530 {"TX SMIC MUX2", "SWR_DMIC5", "TX SWR_DMIC5"},
1531 {"TX SMIC MUX2", "SWR_DMIC6", "TX SWR_DMIC6"},
1532 {"TX SMIC MUX2", "SWR_DMIC7", "TX SWR_DMIC7"},
1533
1534 {"TX DEC3 MUX", "SWR_MIC", "TX SMIC MUX3"},
1535 {"TX SMIC MUX3", NULL, "TX_SWR_CLK"},
1536 {"TX SMIC MUX3", "ADC0", "TX SWR_ADC0"},
1537 {"TX SMIC MUX3", "ADC1", "TX SWR_ADC1"},
1538 {"TX SMIC MUX3", "ADC2", "TX SWR_ADC2"},
1539 {"TX SMIC MUX3", "ADC3", "TX SWR_ADC3"},
1540 {"TX SMIC MUX3", "SWR_DMIC0", "TX SWR_DMIC0"},
1541 {"TX SMIC MUX3", "SWR_DMIC1", "TX SWR_DMIC1"},
1542 {"TX SMIC MUX3", "SWR_DMIC2", "TX SWR_DMIC2"},
1543 {"TX SMIC MUX3", "SWR_DMIC3", "TX SWR_DMIC3"},
1544 {"TX SMIC MUX3", "SWR_DMIC4", "TX SWR_DMIC4"},
1545 {"TX SMIC MUX3", "SWR_DMIC5", "TX SWR_DMIC5"},
1546 {"TX SMIC MUX3", "SWR_DMIC6", "TX SWR_DMIC6"},
1547 {"TX SMIC MUX3", "SWR_DMIC7", "TX SWR_DMIC7"},
1548
1549 {"TX DEC4 MUX", "SWR_MIC", "TX SMIC MUX4"},
1550 {"TX SMIC MUX4", NULL, "TX_SWR_CLK"},
1551 {"TX SMIC MUX4", "ADC0", "TX SWR_ADC0"},
1552 {"TX SMIC MUX4", "ADC1", "TX SWR_ADC1"},
1553 {"TX SMIC MUX4", "ADC2", "TX SWR_ADC2"},
1554 {"TX SMIC MUX4", "ADC3", "TX SWR_ADC3"},
1555 {"TX SMIC MUX4", "SWR_DMIC0", "TX SWR_DMIC0"},
1556 {"TX SMIC MUX4", "SWR_DMIC1", "TX SWR_DMIC1"},
1557 {"TX SMIC MUX4", "SWR_DMIC2", "TX SWR_DMIC2"},
1558 {"TX SMIC MUX4", "SWR_DMIC3", "TX SWR_DMIC3"},
1559 {"TX SMIC MUX4", "SWR_DMIC4", "TX SWR_DMIC4"},
1560 {"TX SMIC MUX4", "SWR_DMIC5", "TX SWR_DMIC5"},
1561 {"TX SMIC MUX4", "SWR_DMIC6", "TX SWR_DMIC6"},
1562 {"TX SMIC MUX4", "SWR_DMIC7", "TX SWR_DMIC7"},
1563
1564 {"TX DEC5 MUX", "SWR_MIC", "TX SMIC MUX5"},
1565 {"TX SMIC MUX5", NULL, "TX_SWR_CLK"},
1566 {"TX SMIC MUX5", "ADC0", "TX SWR_ADC0"},
1567 {"TX SMIC MUX5", "ADC1", "TX SWR_ADC1"},
1568 {"TX SMIC MUX5", "ADC2", "TX SWR_ADC2"},
1569 {"TX SMIC MUX5", "ADC3", "TX SWR_ADC3"},
1570 {"TX SMIC MUX5", "SWR_DMIC0", "TX SWR_DMIC0"},
1571 {"TX SMIC MUX5", "SWR_DMIC1", "TX SWR_DMIC1"},
1572 {"TX SMIC MUX5", "SWR_DMIC2", "TX SWR_DMIC2"},
1573 {"TX SMIC MUX5", "SWR_DMIC3", "TX SWR_DMIC3"},
1574 {"TX SMIC MUX5", "SWR_DMIC4", "TX SWR_DMIC4"},
1575 {"TX SMIC MUX5", "SWR_DMIC5", "TX SWR_DMIC5"},
1576 {"TX SMIC MUX5", "SWR_DMIC6", "TX SWR_DMIC6"},
1577 {"TX SMIC MUX5", "SWR_DMIC7", "TX SWR_DMIC7"},
1578
1579 {"TX DEC6 MUX", "SWR_MIC", "TX SMIC MUX6"},
1580 {"TX SMIC MUX6", NULL, "TX_SWR_CLK"},
1581 {"TX SMIC MUX6", "ADC0", "TX SWR_ADC0"},
1582 {"TX SMIC MUX6", "ADC1", "TX SWR_ADC1"},
1583 {"TX SMIC MUX6", "ADC2", "TX SWR_ADC2"},
1584 {"TX SMIC MUX6", "ADC3", "TX SWR_ADC3"},
1585 {"TX SMIC MUX6", "SWR_DMIC0", "TX SWR_DMIC0"},
1586 {"TX SMIC MUX6", "SWR_DMIC1", "TX SWR_DMIC1"},
1587 {"TX SMIC MUX6", "SWR_DMIC2", "TX SWR_DMIC2"},
1588 {"TX SMIC MUX6", "SWR_DMIC3", "TX SWR_DMIC3"},
1589 {"TX SMIC MUX6", "SWR_DMIC4", "TX SWR_DMIC4"},
1590 {"TX SMIC MUX6", "SWR_DMIC5", "TX SWR_DMIC5"},
1591 {"TX SMIC MUX6", "SWR_DMIC6", "TX SWR_DMIC6"},
1592 {"TX SMIC MUX6", "SWR_DMIC7", "TX SWR_DMIC7"},
1593
1594 {"TX DEC7 MUX", "SWR_MIC", "TX SMIC MUX7"},
1595 {"TX SMIC MUX7", NULL, "TX_SWR_CLK"},
1596 {"TX SMIC MUX7", "ADC0", "TX SWR_ADC0"},
1597 {"TX SMIC MUX7", "ADC1", "TX SWR_ADC1"},
1598 {"TX SMIC MUX7", "ADC2", "TX SWR_ADC2"},
1599 {"TX SMIC MUX7", "ADC3", "TX SWR_ADC3"},
1600 {"TX SMIC MUX7", "SWR_DMIC0", "TX SWR_DMIC0"},
1601 {"TX SMIC MUX7", "SWR_DMIC1", "TX SWR_DMIC1"},
1602 {"TX SMIC MUX7", "SWR_DMIC2", "TX SWR_DMIC2"},
1603 {"TX SMIC MUX7", "SWR_DMIC3", "TX SWR_DMIC3"},
1604 {"TX SMIC MUX7", "SWR_DMIC4", "TX SWR_DMIC4"},
1605 {"TX SMIC MUX7", "SWR_DMIC5", "TX SWR_DMIC5"},
1606 {"TX SMIC MUX7", "SWR_DMIC6", "TX SWR_DMIC6"},
1607 {"TX SMIC MUX7", "SWR_DMIC7", "TX SWR_DMIC7"},
1608};
1609
c39667dd
SK		 1610static const struct snd_kcontrol_new tx_macro_snd_controls[] = {
1611 SOC_SINGLE_S8_TLV("TX_DEC0 Volume",
1612 CDC_TX0_TX_VOL_CTL,
1613 -84, 40, digital_gain),
1614 SOC_SINGLE_S8_TLV("TX_DEC1 Volume",
1615 CDC_TX1_TX_VOL_CTL,
1616 -84, 40, digital_gain),
1617 SOC_SINGLE_S8_TLV("TX_DEC2 Volume",
1618 CDC_TX2_TX_VOL_CTL,
1619 -84, 40, digital_gain),
1620 SOC_SINGLE_S8_TLV("TX_DEC3 Volume",
1621 CDC_TX3_TX_VOL_CTL,
1622 -84, 40, digital_gain),
1623 SOC_SINGLE_S8_TLV("TX_DEC4 Volume",
1624 CDC_TX4_TX_VOL_CTL,
1625 -84, 40, digital_gain),
1626 SOC_SINGLE_S8_TLV("TX_DEC5 Volume",
1627 CDC_TX5_TX_VOL_CTL,
1628 -84, 40, digital_gain),
1629 SOC_SINGLE_S8_TLV("TX_DEC6 Volume",
1630 CDC_TX6_TX_VOL_CTL,
1631 -84, 40, digital_gain),
1632 SOC_SINGLE_S8_TLV("TX_DEC7 Volume",
1633 CDC_TX7_TX_VOL_CTL,
1634 -84, 40, digital_gain),
1635
1636 SOC_ENUM_EXT("DEC0 MODE", dec_mode_mux_enum[0],
1637 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1638
1639 SOC_ENUM_EXT("DEC1 MODE", dec_mode_mux_enum[1],
1640 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1641
1642 SOC_ENUM_EXT("DEC2 MODE", dec_mode_mux_enum[2],
1643 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1644
1645 SOC_ENUM_EXT("DEC3 MODE", dec_mode_mux_enum[3],
1646 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1647
1648 SOC_ENUM_EXT("DEC4 MODE", dec_mode_mux_enum[4],
1649 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1650
1651 SOC_ENUM_EXT("DEC5 MODE", dec_mode_mux_enum[5],
1652 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1653
1654 SOC_ENUM_EXT("DEC6 MODE", dec_mode_mux_enum[6],
1655 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1656
1657 SOC_ENUM_EXT("DEC7 MODE", dec_mode_mux_enum[7],
1658 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1659
1660 SOC_SINGLE_EXT("DEC0_BCS Switch", SND_SOC_NOPM, 0, 1, 0,
1661 tx_macro_get_bcs, tx_macro_set_bcs),
1662};
1663
1664static int tx_macro_component_probe(struct snd_soc_component *comp)
1665{
1666 struct tx_macro *tx = snd_soc_component_get_drvdata(comp);
1667 int i;
1668
1669 snd_soc_component_init_regmap(comp, tx->regmap);
1670
1671 for (i = 0; i < NUM_DECIMATORS; i++) {
1672 tx->tx_hpf_work[i].tx = tx;
1673 tx->tx_hpf_work[i].decimator = i;
1674 INIT_DELAYED_WORK(&tx->tx_hpf_work[i].dwork,
1675 tx_macro_tx_hpf_corner_freq_callback);
1676 }
1677
1678 for (i = 0; i < NUM_DECIMATORS; i++) {
1679 tx->tx_mute_dwork[i].tx = tx;
1680 tx->tx_mute_dwork[i].decimator = i;
1681 INIT_DELAYED_WORK(&tx->tx_mute_dwork[i].dwork,
1682 tx_macro_mute_update_callback);
1683 }
1684 tx->component = comp;
1685
1686 snd_soc_component_update_bits(comp, CDC_TX0_TX_PATH_SEC7, 0x3F,
1687 0x0A);
864b9b58
SRM		 1688 /* Enable swr mic0 and mic1 clock */
1689 snd_soc_component_update_bits(comp, CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 0xFF, 0x00);
1690 snd_soc_component_update_bits(comp, CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 0xFF, 0x00);
c39667dd
SK		 1691
1692 return 0;
1693}
1694
1695static int swclk_gate_enable(struct clk_hw *hw)
1696{
1697 struct tx_macro *tx = to_tx_macro(hw);
1698 struct regmap *regmap = tx->regmap;
31bd0db8
SK		 1699 int ret;
1700
1701 ret = clk_prepare_enable(tx->mclk);
1702 if (ret) {
1703 dev_err(tx->dev, "failed to enable mclk\n");
1704 return ret;
1705 }
c39667dd
SK		 1706
1707 tx_macro_mclk_enable(tx, true);
d83a7201
SK		 1708 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
1709 CDC_TX_SWR_RESET_MASK, CDC_TX_SWR_RESET_ENABLE);
c39667dd
SK		 1710
1711 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
1712 CDC_TX_SWR_CLK_EN_MASK,
1713 CDC_TX_SWR_CLK_ENABLE);
d83a7201
SK		 1714 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
1715 CDC_TX_SWR_RESET_MASK, 0x0);
c39667dd
SK		 1716
1717 return 0;
1718}
1719
1720static void swclk_gate_disable(struct clk_hw *hw)
1721{
1722 struct tx_macro *tx = to_tx_macro(hw);
1723 struct regmap *regmap = tx->regmap;
1724
1725 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
1726 CDC_TX_SWR_CLK_EN_MASK, 0x0);
1727
1728 tx_macro_mclk_enable(tx, false);
31bd0db8 1729 clk_disable_unprepare(tx->mclk);
c39667dd
SK		 1730}
1731
1732static int swclk_gate_is_enabled(struct clk_hw *hw)
1733{
1734 struct tx_macro *tx = to_tx_macro(hw);
1735 int ret, val;
1736
1737 regmap_read(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, &val);
1738 ret = val & BIT(0);
1739
1740 return ret;
1741}
1742
1743static unsigned long swclk_recalc_rate(struct clk_hw *hw,
1744 unsigned long parent_rate)
1745{
1746 return parent_rate / 2;
1747}
1748
1749static const struct clk_ops swclk_gate_ops = {
1750 .prepare = swclk_gate_enable,
1751 .unprepare = swclk_gate_disable,
1752 .is_enabled = swclk_gate_is_enabled,
1753 .recalc_rate = swclk_recalc_rate,
1754
1755};
1756
db8665a3 1757static int tx_macro_register_mclk_output(struct tx_macro *tx)
c39667dd
SK		 1758{
1759 struct device *dev = tx->dev;
c39667dd
SK		 1760 const char *parent_clk_name = NULL;
1761 const char *clk_name = "lpass-tx-mclk";
1762 struct clk_hw *hw;
1763 struct clk_init_data init;
1764 int ret;
1765
31bd0db8 1766 parent_clk_name = __clk_get_name(tx->npl);
c39667dd
SK		 1767
1768 init.name = clk_name;
1769 init.ops = &swclk_gate_ops;
1770 init.flags = 0;
1771 init.parent_names = &parent_clk_name;
1772 init.num_parents = 1;
1773 tx->hw.init = &init;
1774 hw = &tx->hw;
db8665a3 1775 ret = devm_clk_hw_register(dev, hw);
c39667dd 1776 if (ret)
db8665a3 1777 return ret;
c39667dd 1778
db8665a3 1779 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
c39667dd
SK		 1780}
1781
1782static const struct snd_soc_component_driver tx_macro_component_drv = {
1783 .name = "RX-MACRO",
1784 .probe = tx_macro_component_probe,
1785 .controls = tx_macro_snd_controls,
1786 .num_controls = ARRAY_SIZE(tx_macro_snd_controls),
d207bdea
SK		 1787 .dapm_widgets = tx_macro_dapm_widgets,
1788 .num_dapm_widgets = ARRAY_SIZE(tx_macro_dapm_widgets),
1789 .dapm_routes = tx_audio_map,
1790 .num_dapm_routes = ARRAY_SIZE(tx_audio_map),
c39667dd
SK		 1791};
1792
1793static int tx_macro_probe(struct platform_device *pdev)
1794{
1795 struct device *dev = &pdev->dev;
7b285c74 1796 struct device_node *np = dev->of_node;
c39667dd
SK		 1797 struct tx_macro *tx;
1798 void __iomem *base;
7b285c74 1799 int ret, reg;
c39667dd
SK		 1800
1801 tx = devm_kzalloc(dev, sizeof(*tx), GFP_KERNEL);
1802 if (!tx)
1803 return -ENOMEM;
1804
512864c4
SK		 1805 tx->macro = devm_clk_get_optional(dev, "macro");
1806 if (IS_ERR(tx->macro))
1807 return PTR_ERR(tx->macro);
c39667dd 1808
512864c4
SK		 1809 tx->dcodec = devm_clk_get_optional(dev, "dcodec");
1810 if (IS_ERR(tx->dcodec))
1811 return PTR_ERR(tx->dcodec);
1812
1813 tx->mclk = devm_clk_get(dev, "mclk");
1814 if (IS_ERR(tx->mclk))
1815 return PTR_ERR(tx->mclk);
1816
1817 tx->npl = devm_clk_get(dev, "npl");
1818 if (IS_ERR(tx->npl))
1819 return PTR_ERR(tx->npl);
1820
1821 tx->fsgen = devm_clk_get(dev, "fsgen");
1822 if (IS_ERR(tx->fsgen))
1823 return PTR_ERR(tx->fsgen);
c39667dd 1824
9e3d83c5
SRM		 1825 tx->pds = lpass_macro_pds_init(dev);
1826 if (IS_ERR(tx->pds))
1827 return PTR_ERR(tx->pds);
1828
c39667dd 1829 base = devm_platform_ioremap_resource(pdev, 0);
ddfd5345
CJ		 1830 if (IS_ERR(base)) {
1831 ret = PTR_ERR(base);
1832 goto err;
1833 }
c39667dd 1834
7b285c74
SRM		 1835 /* Update defaults for lpass sc7280 */
1836 if (of_device_is_compatible(np, "qcom,sc7280-lpass-tx-macro")) {
1837 for (reg = 0; reg < ARRAY_SIZE(tx_defaults); reg++) {
1838 switch (tx_defaults[reg].reg) {
1839 case CDC_TX_TOP_CSR_SWR_AMIC0_CTL:
1840 case CDC_TX_TOP_CSR_SWR_AMIC1_CTL:
1841 tx_defaults[reg].def = 0x0E;
1842 break;
1843 default:
1844 break;
1845 }
1846 }
1847 }
1848
c39667dd 1849 tx->regmap = devm_regmap_init_mmio(dev, base, &tx_regmap_config);
ddfd5345
CJ		 1850 if (IS_ERR(tx->regmap)) {
1851 ret = PTR_ERR(tx->regmap);
1852 goto err;
1853 }
c39667dd
SK		 1854
1855 dev_set_drvdata(dev, tx);
1856
c39667dd
SK		 1857 tx->dev = dev;
1858
1859 /* set MCLK and NPL rates */
512864c4
SK		 1860 clk_set_rate(tx->mclk, MCLK_FREQ);
1861 clk_set_rate(tx->npl, 2 * MCLK_FREQ);
c39667dd 1862
512864c4 1863 ret = clk_prepare_enable(tx->macro);
c39667dd 1864 if (ret)
512864c4
SK		 1865 goto err;
1866
1867 ret = clk_prepare_enable(tx->dcodec);
1868 if (ret)
1869 goto err_dcodec;
1870
1871 ret = clk_prepare_enable(tx->mclk);
1872 if (ret)
1873 goto err_mclk;
1874
1875 ret = clk_prepare_enable(tx->npl);
1876 if (ret)
1877 goto err_npl;
1878
1879 ret = clk_prepare_enable(tx->fsgen);
1880 if (ret)
1881 goto err_fsgen;
c39667dd 1882
db8665a3
SK		 1883 ret = tx_macro_register_mclk_output(tx);
1884 if (ret)
512864c4 1885 goto err_clkout;
c39667dd
SK		 1886
1887 ret = devm_snd_soc_register_component(dev, &tx_macro_component_drv,
1888 tx_macro_dai,
1889 ARRAY_SIZE(tx_macro_dai));
1890 if (ret)
512864c4 1891 goto err_clkout;
c39667dd 1892
1fb83bc5
SK		 1893 pm_runtime_set_autosuspend_delay(dev, 3000);
1894 pm_runtime_use_autosuspend(dev);
1895 pm_runtime_mark_last_busy(dev);
1896 pm_runtime_set_active(dev);
1897 pm_runtime_enable(dev);
1898
512864c4
SK		 1899 return 0;
1900
1901err_clkout:
1902 clk_disable_unprepare(tx->fsgen);
1903err_fsgen:
1904 clk_disable_unprepare(tx->npl);
1905err_npl:
1906 clk_disable_unprepare(tx->mclk);
1907err_mclk:
1908 clk_disable_unprepare(tx->dcodec);
1909err_dcodec:
1910 clk_disable_unprepare(tx->macro);
1911err:
ddfd5345
CJ		 1912 lpass_macro_pds_exit(tx->pds);
1913
c39667dd
SK		 1914 return ret;
1915}
1916
1917static int tx_macro_remove(struct platform_device *pdev)
1918{
1919 struct tx_macro *tx = dev_get_drvdata(&pdev->dev);
1920
512864c4
SK		 1921 clk_disable_unprepare(tx->macro);
1922 clk_disable_unprepare(tx->dcodec);
1923 clk_disable_unprepare(tx->mclk);
1924 clk_disable_unprepare(tx->npl);
1925 clk_disable_unprepare(tx->fsgen);
c39667dd 1926
1c19601d
SRM		 1927 lpass_macro_pds_exit(tx->pds);
1928
c39667dd
SK		 1929 return 0;
1930}
1931
1fb83bc5
SK		 1932static int __maybe_unused tx_macro_runtime_suspend(struct device *dev)
1933{
1934 struct tx_macro *tx = dev_get_drvdata(dev);
1935
1936 regcache_cache_only(tx->regmap, true);
1937 regcache_mark_dirty(tx->regmap);
1938
1939 clk_disable_unprepare(tx->mclk);
1940 clk_disable_unprepare(tx->npl);
1941 clk_disable_unprepare(tx->fsgen);
1942
1943 return 0;
1944}
1945
1946static int __maybe_unused tx_macro_runtime_resume(struct device *dev)
1947{
1948 struct tx_macro *tx = dev_get_drvdata(dev);
1949 int ret;
1950
1951 ret = clk_prepare_enable(tx->mclk);
1952 if (ret) {
1953 dev_err(dev, "unable to prepare mclk\n");
1954 return ret;
1955 }
1956
1957 ret = clk_prepare_enable(tx->npl);
1958 if (ret) {
1959 dev_err(dev, "unable to prepare npl\n");
1960 goto err_npl;
1961 }
1962
1963 ret = clk_prepare_enable(tx->fsgen);
1964 if (ret) {
1965 dev_err(dev, "unable to prepare fsgen\n");
1966 goto err_fsgen;
1967 }
1968
1969 regcache_cache_only(tx->regmap, false);
1970 regcache_sync(tx->regmap);
1fb83bc5
SK		 1971
1972 return 0;
1973err_fsgen:
1974 clk_disable_unprepare(tx->npl);
1975err_npl:
1976 clk_disable_unprepare(tx->mclk);
1977
1978 return ret;
1979}
1980
1981static const struct dev_pm_ops tx_macro_pm_ops = {
1982 SET_RUNTIME_PM_OPS(tx_macro_runtime_suspend, tx_macro_runtime_resume, NULL)
1983};
1984
c39667dd 1985static const struct of_device_id tx_macro_dt_match[] = {
9d8c6981 1986 { .compatible = "qcom,sc7280-lpass-tx-macro" },
c39667dd
SK		 1987 { .compatible = "qcom,sm8250-lpass-tx-macro" },
1988 { }
1989};
14c0c423 1990MODULE_DEVICE_TABLE(of, tx_macro_dt_match);
c39667dd
SK		 1991static struct platform_driver tx_macro_driver = {
1992 .driver = {
1993 .name = "tx_macro",
1994 .of_match_table = tx_macro_dt_match,
1995 .suppress_bind_attrs = true,
1fb83bc5 1996 .pm = &tx_macro_pm_ops,
c39667dd
SK		 1997 },
1998 .probe = tx_macro_probe,
1999 .remove = tx_macro_remove,
2000};
2001
2002module_platform_driver(tx_macro_driver);
2003
2004MODULE_DESCRIPTION("TX macro driver");
2005MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)