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ASoC: codecs: wsa-macro: setup soundwire clks correctly
[linux-block.git] / sound / soc / codecs / lpass-tx-macro.c
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c39667dd
SK		 1// SPDX-License-Identifier: GPL-2.0-only
2// Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
3
4#include <linux/module.h>
5#include <linux/init.h>
6#include <linux/clk.h>
7#include <linux/io.h>
8#include <linux/platform_device.h>
512864c4 9#include <linux/pm_runtime.h>
c39667dd
SK		 10#include <linux/regmap.h>
11#include <sound/soc.h>
12#include <sound/soc-dapm.h>
13#include <sound/tlv.h>
14#include <linux/of_clk.h>
15#include <linux/clk-provider.h>
16
17#define CDC_TX_CLK_RST_CTRL_MCLK_CONTROL (0x0000)
18#define CDC_TX_MCLK_EN_MASK BIT(0)
19#define CDC_TX_MCLK_ENABLE BIT(0)
20#define CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL (0x0004)
21#define CDC_TX_FS_CNT_EN_MASK BIT(0)
22#define CDC_TX_FS_CNT_ENABLE BIT(0)
23#define CDC_TX_CLK_RST_CTRL_SWR_CONTROL (0x0008)
24#define CDC_TX_SWR_RESET_MASK BIT(1)
25#define CDC_TX_SWR_RESET_ENABLE BIT(1)
26#define CDC_TX_SWR_CLK_EN_MASK BIT(0)
27#define CDC_TX_SWR_CLK_ENABLE BIT(0)
28#define CDC_TX_TOP_CSR_TOP_CFG0 (0x0080)
29#define CDC_TX_TOP_CSR_ANC_CFG (0x0084)
30#define CDC_TX_TOP_CSR_SWR_CTRL (0x0088)
31#define CDC_TX_TOP_CSR_FREQ_MCLK (0x0090)
32#define CDC_TX_TOP_CSR_DEBUG_BUS (0x0094)
33#define CDC_TX_TOP_CSR_DEBUG_EN (0x0098)
34#define CDC_TX_TOP_CSR_TX_I2S_CTL (0x00A4)
35#define CDC_TX_TOP_CSR_I2S_CLK (0x00A8)
36#define CDC_TX_TOP_CSR_I2S_RESET (0x00AC)
37#define CDC_TX_TOP_CSR_SWR_DMICn_CTL(n) (0x00C0 + n * 0x4)
38#define CDC_TX_TOP_CSR_SWR_DMIC0_CTL (0x00C0)
39#define CDC_TX_SWR_DMIC_CLK_SEL_MASK GENMASK(3, 1)
40#define CDC_TX_TOP_CSR_SWR_DMIC1_CTL (0x00C4)
41#define CDC_TX_TOP_CSR_SWR_DMIC2_CTL (0x00C8)
42#define CDC_TX_TOP_CSR_SWR_DMIC3_CTL (0x00CC)
43#define CDC_TX_TOP_CSR_SWR_AMIC0_CTL (0x00D0)
44#define CDC_TX_TOP_CSR_SWR_AMIC1_CTL (0x00D4)
45#define CDC_TX_INP_MUX_ADC_MUXn_CFG0(n) (0x0100 + 0x8 * n)
46#define CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK GENMASK(3, 0)
47#define CDC_TX_INP_MUX_ADC_MUX0_CFG0 (0x0100)
48#define CDC_TX_INP_MUX_ADC_MUXn_CFG1(n) (0x0104 + 0x8 * n)
49#define CDC_TX_INP_MUX_ADC_MUX0_CFG1 (0x0104)
50#define CDC_TX_INP_MUX_ADC_MUX1_CFG0 (0x0108)
51#define CDC_TX_INP_MUX_ADC_MUX1_CFG1 (0x010C)
52#define CDC_TX_INP_MUX_ADC_MUX2_CFG0 (0x0110)
53#define CDC_TX_INP_MUX_ADC_MUX2_CFG1 (0x0114)
54#define CDC_TX_INP_MUX_ADC_MUX3_CFG0 (0x0118)
55#define CDC_TX_INP_MUX_ADC_MUX3_CFG1 (0x011C)
56#define CDC_TX_INP_MUX_ADC_MUX4_CFG0 (0x0120)
57#define CDC_TX_INP_MUX_ADC_MUX4_CFG1 (0x0124)
58#define CDC_TX_INP_MUX_ADC_MUX5_CFG0 (0x0128)
59#define CDC_TX_INP_MUX_ADC_MUX5_CFG1 (0x012C)
60#define CDC_TX_INP_MUX_ADC_MUX6_CFG0 (0x0130)
61#define CDC_TX_INP_MUX_ADC_MUX6_CFG1 (0x0134)
62#define CDC_TX_INP_MUX_ADC_MUX7_CFG0 (0x0138)
63#define CDC_TX_INP_MUX_ADC_MUX7_CFG1 (0x013C)
64#define CDC_TX_ANC0_CLK_RESET_CTL (0x0200)
65#define CDC_TX_ANC0_MODE_1_CTL (0x0204)
66#define CDC_TX_ANC0_MODE_2_CTL (0x0208)
67#define CDC_TX_ANC0_FF_SHIFT (0x020C)
68#define CDC_TX_ANC0_FB_SHIFT (0x0210)
69#define CDC_TX_ANC0_LPF_FF_A_CTL (0x0214)
70#define CDC_TX_ANC0_LPF_FF_B_CTL (0x0218)
71#define CDC_TX_ANC0_LPF_FB_CTL (0x021C)
72#define CDC_TX_ANC0_SMLPF_CTL (0x0220)
73#define CDC_TX_ANC0_DCFLT_SHIFT_CTL (0x0224)
74#define CDC_TX_ANC0_IIR_ADAPT_CTL (0x0228)
75#define CDC_TX_ANC0_IIR_COEFF_1_CTL (0x022C)
76#define CDC_TX_ANC0_IIR_COEFF_2_CTL (0x0230)
77#define CDC_TX_ANC0_FF_A_GAIN_CTL (0x0234)
78#define CDC_TX_ANC0_FF_B_GAIN_CTL (0x0238)
79#define CDC_TX_ANC0_FB_GAIN_CTL (0x023C)
80#define CDC_TXn_TX_PATH_CTL(n) (0x0400 + 0x80 * n)
81#define CDC_TXn_PCM_RATE_MASK GENMASK(3, 0)
82#define CDC_TXn_PGA_MUTE_MASK BIT(4)
83#define CDC_TXn_CLK_EN_MASK BIT(5)
84#define CDC_TX0_TX_PATH_CTL (0x0400)
85#define CDC_TXn_TX_PATH_CFG0(n) (0x0404 + 0x80 * n)
86#define CDC_TX0_TX_PATH_CFG0 (0x0404)
87#define CDC_TXn_PH_EN_MASK BIT(0)
88#define CDC_TXn_ADC_MODE_MASK GENMASK(2, 1)
89#define CDC_TXn_HPF_CUT_FREQ_MASK GENMASK(6, 5)
90#define CDC_TXn_ADC_DMIC_SEL_MASK BIT(7)
91#define CDC_TX0_TX_PATH_CFG1 (0x0408)
92#define CDC_TXn_TX_VOL_CTL(n) (0x040C + 0x80 * n)
93#define CDC_TX0_TX_VOL_CTL (0x040C)
94#define CDC_TX0_TX_PATH_SEC0 (0x0410)
95#define CDC_TX0_TX_PATH_SEC1 (0x0414)
96#define CDC_TXn_TX_PATH_SEC2(n) (0x0418 + 0x80 * n)
97#define CDC_TXn_HPF_F_CHANGE_MASK BIT(1)
98#define CDC_TXn_HPF_ZERO_GATE_MASK BIT(0)
99#define CDC_TX0_TX_PATH_SEC2 (0x0418)
100#define CDC_TX0_TX_PATH_SEC3 (0x041C)
101#define CDC_TX0_TX_PATH_SEC4 (0x0420)
102#define CDC_TX0_TX_PATH_SEC5 (0x0424)
103#define CDC_TX0_TX_PATH_SEC6 (0x0428)
104#define CDC_TX0_TX_PATH_SEC7 (0x042C)
105#define CDC_TX0_MBHC_CTL_EN_MASK BIT(6)
106#define CDC_TX1_TX_PATH_CTL (0x0480)
107#define CDC_TX1_TX_PATH_CFG0 (0x0484)
108#define CDC_TX1_TX_PATH_CFG1 (0x0488)
109#define CDC_TX1_TX_VOL_CTL (0x048C)
110#define CDC_TX1_TX_PATH_SEC0 (0x0490)
111#define CDC_TX1_TX_PATH_SEC1 (0x0494)
112#define CDC_TX1_TX_PATH_SEC2 (0x0498)
113#define CDC_TX1_TX_PATH_SEC3 (0x049C)
114#define CDC_TX1_TX_PATH_SEC4 (0x04A0)
115#define CDC_TX1_TX_PATH_SEC5 (0x04A4)
116#define CDC_TX1_TX_PATH_SEC6 (0x04A8)
117#define CDC_TX2_TX_PATH_CTL (0x0500)
118#define CDC_TX2_TX_PATH_CFG0 (0x0504)
119#define CDC_TX2_TX_PATH_CFG1 (0x0508)
120#define CDC_TX2_TX_VOL_CTL (0x050C)
121#define CDC_TX2_TX_PATH_SEC0 (0x0510)
122#define CDC_TX2_TX_PATH_SEC1 (0x0514)
123#define CDC_TX2_TX_PATH_SEC2 (0x0518)
124#define CDC_TX2_TX_PATH_SEC3 (0x051C)
125#define CDC_TX2_TX_PATH_SEC4 (0x0520)
126#define CDC_TX2_TX_PATH_SEC5 (0x0524)
127#define CDC_TX2_TX_PATH_SEC6 (0x0528)
128#define CDC_TX3_TX_PATH_CTL (0x0580)
129#define CDC_TX3_TX_PATH_CFG0 (0x0584)
130#define CDC_TX3_TX_PATH_CFG1 (0x0588)
131#define CDC_TX3_TX_VOL_CTL (0x058C)
132#define CDC_TX3_TX_PATH_SEC0 (0x0590)
133#define CDC_TX3_TX_PATH_SEC1 (0x0594)
134#define CDC_TX3_TX_PATH_SEC2 (0x0598)
135#define CDC_TX3_TX_PATH_SEC3 (0x059C)
136#define CDC_TX3_TX_PATH_SEC4 (0x05A0)
137#define CDC_TX3_TX_PATH_SEC5 (0x05A4)
138#define CDC_TX3_TX_PATH_SEC6 (0x05A8)
139#define CDC_TX4_TX_PATH_CTL (0x0600)
140#define CDC_TX4_TX_PATH_CFG0 (0x0604)
141#define CDC_TX4_TX_PATH_CFG1 (0x0608)
142#define CDC_TX4_TX_VOL_CTL (0x060C)
143#define CDC_TX4_TX_PATH_SEC0 (0x0610)
144#define CDC_TX4_TX_PATH_SEC1 (0x0614)
145#define CDC_TX4_TX_PATH_SEC2 (0x0618)
146#define CDC_TX4_TX_PATH_SEC3 (0x061C)
147#define CDC_TX4_TX_PATH_SEC4 (0x0620)
148#define CDC_TX4_TX_PATH_SEC5 (0x0624)
149#define CDC_TX4_TX_PATH_SEC6 (0x0628)
150#define CDC_TX5_TX_PATH_CTL (0x0680)
151#define CDC_TX5_TX_PATH_CFG0 (0x0684)
152#define CDC_TX5_TX_PATH_CFG1 (0x0688)
153#define CDC_TX5_TX_VOL_CTL (0x068C)
154#define CDC_TX5_TX_PATH_SEC0 (0x0690)
155#define CDC_TX5_TX_PATH_SEC1 (0x0694)
156#define CDC_TX5_TX_PATH_SEC2 (0x0698)
157#define CDC_TX5_TX_PATH_SEC3 (0x069C)
158#define CDC_TX5_TX_PATH_SEC4 (0x06A0)
159#define CDC_TX5_TX_PATH_SEC5 (0x06A4)
160#define CDC_TX5_TX_PATH_SEC6 (0x06A8)
161#define CDC_TX6_TX_PATH_CTL (0x0700)
162#define CDC_TX6_TX_PATH_CFG0 (0x0704)
163#define CDC_TX6_TX_PATH_CFG1 (0x0708)
164#define CDC_TX6_TX_VOL_CTL (0x070C)
165#define CDC_TX6_TX_PATH_SEC0 (0x0710)
166#define CDC_TX6_TX_PATH_SEC1 (0x0714)
167#define CDC_TX6_TX_PATH_SEC2 (0x0718)
168#define CDC_TX6_TX_PATH_SEC3 (0x071C)
169#define CDC_TX6_TX_PATH_SEC4 (0x0720)
170#define CDC_TX6_TX_PATH_SEC5 (0x0724)
171#define CDC_TX6_TX_PATH_SEC6 (0x0728)
172#define CDC_TX7_TX_PATH_CTL (0x0780)
173#define CDC_TX7_TX_PATH_CFG0 (0x0784)
174#define CDC_TX7_TX_PATH_CFG1 (0x0788)
175#define CDC_TX7_TX_VOL_CTL (0x078C)
176#define CDC_TX7_TX_PATH_SEC0 (0x0790)
177#define CDC_TX7_TX_PATH_SEC1 (0x0794)
178#define CDC_TX7_TX_PATH_SEC2 (0x0798)
179#define CDC_TX7_TX_PATH_SEC3 (0x079C)
180#define CDC_TX7_TX_PATH_SEC4 (0x07A0)
181#define CDC_TX7_TX_PATH_SEC5 (0x07A4)
182#define CDC_TX7_TX_PATH_SEC6 (0x07A8)
183#define TX_MAX_OFFSET (0x07A8)
184
185#define TX_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
186 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
187 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
188#define TX_MACRO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
189 SNDRV_PCM_FMTBIT_S24_LE |\
190 SNDRV_PCM_FMTBIT_S24_3LE)
191
192#define CF_MIN_3DB_4HZ 0x0
193#define CF_MIN_3DB_75HZ 0x1
194#define CF_MIN_3DB_150HZ 0x2
195#define TX_ADC_MAX 5
196#define TX_ADC_TO_DMIC(n) ((n - TX_ADC_MAX)/2)
197#define NUM_DECIMATORS 8
198#define TX_NUM_CLKS_MAX 5
199#define TX_MACRO_DMIC_UNMUTE_DELAY_MS 40
200#define TX_MACRO_AMIC_UNMUTE_DELAY_MS 100
201#define TX_MACRO_DMIC_HPF_DELAY_MS 300
202#define TX_MACRO_AMIC_HPF_DELAY_MS 300
203#define MCLK_FREQ 9600000
204
205enum {
206 TX_MACRO_AIF_INVALID = 0,
207 TX_MACRO_AIF1_CAP,
208 TX_MACRO_AIF2_CAP,
209 TX_MACRO_AIF3_CAP,
210 TX_MACRO_MAX_DAIS
211};
212
213enum {
214 TX_MACRO_DEC0,
215 TX_MACRO_DEC1,
216 TX_MACRO_DEC2,
217 TX_MACRO_DEC3,
218 TX_MACRO_DEC4,
219 TX_MACRO_DEC5,
220 TX_MACRO_DEC6,
221 TX_MACRO_DEC7,
222 TX_MACRO_DEC_MAX,
223};
224
225enum {
226 TX_MACRO_CLK_DIV_2,
227 TX_MACRO_CLK_DIV_3,
228 TX_MACRO_CLK_DIV_4,
229 TX_MACRO_CLK_DIV_6,
230 TX_MACRO_CLK_DIV_8,
231 TX_MACRO_CLK_DIV_16,
232};
233
234enum {
235 MSM_DMIC,
236 SWR_MIC,
237 ANC_FB_TUNE1
238};
239
240struct tx_mute_work {
241 struct tx_macro *tx;
242 u32 decimator;
243 struct delayed_work dwork;
244};
245
246struct hpf_work {
247 struct tx_macro *tx;
248 u8 decimator;
249 u8 hpf_cut_off_freq;
250 struct delayed_work dwork;
251};
252
253struct tx_macro {
254 struct device *dev;
255 struct snd_soc_component *component;
256 struct hpf_work tx_hpf_work[NUM_DECIMATORS];
257 struct tx_mute_work tx_mute_dwork[NUM_DECIMATORS];
258 unsigned long active_ch_mask[TX_MACRO_MAX_DAIS];
259 unsigned long active_ch_cnt[TX_MACRO_MAX_DAIS];
260 unsigned long active_decimator[TX_MACRO_MAX_DAIS];
261 struct regmap *regmap;
512864c4
SK		 262 struct clk *mclk;
263 struct clk *npl;
264 struct clk *macro;
265 struct clk *dcodec;
266 struct clk *fsgen;
c39667dd
SK		 267 struct clk_hw hw;
268 bool dec_active[NUM_DECIMATORS];
269 bool reset_swr;
270 int tx_mclk_users;
271 u16 dmic_clk_div;
272 bool bcs_enable;
273 int dec_mode[NUM_DECIMATORS];
274 bool bcs_clk_en;
275};
276#define to_tx_macro(_hw) container_of(_hw, struct tx_macro, hw)
277
278static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
279
7b285c74 280static struct reg_default tx_defaults[] = {
c39667dd
SK		 281 /* TX Macro */
282 { CDC_TX_CLK_RST_CTRL_MCLK_CONTROL, 0x00 },
283 { CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00 },
284 { CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 0x00},
285 { CDC_TX_TOP_CSR_TOP_CFG0, 0x00},
286 { CDC_TX_TOP_CSR_ANC_CFG, 0x00},
287 { CDC_TX_TOP_CSR_SWR_CTRL, 0x00},
288 { CDC_TX_TOP_CSR_FREQ_MCLK, 0x00},
289 { CDC_TX_TOP_CSR_DEBUG_BUS, 0x00},
290 { CDC_TX_TOP_CSR_DEBUG_EN, 0x00},
291 { CDC_TX_TOP_CSR_TX_I2S_CTL, 0x0C},
292 { CDC_TX_TOP_CSR_I2S_CLK, 0x00},
293 { CDC_TX_TOP_CSR_I2S_RESET, 0x00},
294 { CDC_TX_TOP_CSR_SWR_DMIC0_CTL, 0x00},
295 { CDC_TX_TOP_CSR_SWR_DMIC1_CTL, 0x00},
296 { CDC_TX_TOP_CSR_SWR_DMIC2_CTL, 0x00},
297 { CDC_TX_TOP_CSR_SWR_DMIC3_CTL, 0x00},
298 { CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 0x00},
299 { CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 0x00},
300 { CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0x00},
301 { CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0x00},
302 { CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0x00},
303 { CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0x00},
304 { CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0x00},
305 { CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0x00},
306 { CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0x00},
307 { CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0x00},
308 { CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0x00},
309 { CDC_TX_INP_MUX_ADC_MUX4_CFG1, 0x00},
310 { CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0x00},
311 { CDC_TX_INP_MUX_ADC_MUX5_CFG1, 0x00},
312 { CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0x00},
313 { CDC_TX_INP_MUX_ADC_MUX6_CFG1, 0x00},
314 { CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0x00},
315 { CDC_TX_INP_MUX_ADC_MUX7_CFG1, 0x00},
316 { CDC_TX_ANC0_CLK_RESET_CTL, 0x00},
317 { CDC_TX_ANC0_MODE_1_CTL, 0x00},
318 { CDC_TX_ANC0_MODE_2_CTL, 0x00},
319 { CDC_TX_ANC0_FF_SHIFT, 0x00},
320 { CDC_TX_ANC0_FB_SHIFT, 0x00},
321 { CDC_TX_ANC0_LPF_FF_A_CTL, 0x00},
322 { CDC_TX_ANC0_LPF_FF_B_CTL, 0x00},
323 { CDC_TX_ANC0_LPF_FB_CTL, 0x00},
324 { CDC_TX_ANC0_SMLPF_CTL, 0x00},
325 { CDC_TX_ANC0_DCFLT_SHIFT_CTL, 0x00},
326 { CDC_TX_ANC0_IIR_ADAPT_CTL, 0x00},
327 { CDC_TX_ANC0_IIR_COEFF_1_CTL, 0x00},
328 { CDC_TX_ANC0_IIR_COEFF_2_CTL, 0x00},
329 { CDC_TX_ANC0_FF_A_GAIN_CTL, 0x00},
330 { CDC_TX_ANC0_FF_B_GAIN_CTL, 0x00},
331 { CDC_TX_ANC0_FB_GAIN_CTL, 0x00},
332 { CDC_TX0_TX_PATH_CTL, 0x04},
333 { CDC_TX0_TX_PATH_CFG0, 0x10},
334 { CDC_TX0_TX_PATH_CFG1, 0x0B},
335 { CDC_TX0_TX_VOL_CTL, 0x00},
336 { CDC_TX0_TX_PATH_SEC0, 0x00},
337 { CDC_TX0_TX_PATH_SEC1, 0x00},
338 { CDC_TX0_TX_PATH_SEC2, 0x01},
339 { CDC_TX0_TX_PATH_SEC3, 0x3C},
340 { CDC_TX0_TX_PATH_SEC4, 0x20},
341 { CDC_TX0_TX_PATH_SEC5, 0x00},
342 { CDC_TX0_TX_PATH_SEC6, 0x00},
343 { CDC_TX0_TX_PATH_SEC7, 0x25},
344 { CDC_TX1_TX_PATH_CTL, 0x04},
345 { CDC_TX1_TX_PATH_CFG0, 0x10},
346 { CDC_TX1_TX_PATH_CFG1, 0x0B},
347 { CDC_TX1_TX_VOL_CTL, 0x00},
348 { CDC_TX1_TX_PATH_SEC0, 0x00},
349 { CDC_TX1_TX_PATH_SEC1, 0x00},
350 { CDC_TX1_TX_PATH_SEC2, 0x01},
351 { CDC_TX1_TX_PATH_SEC3, 0x3C},
352 { CDC_TX1_TX_PATH_SEC4, 0x20},
353 { CDC_TX1_TX_PATH_SEC5, 0x00},
354 { CDC_TX1_TX_PATH_SEC6, 0x00},
355 { CDC_TX2_TX_PATH_CTL, 0x04},
356 { CDC_TX2_TX_PATH_CFG0, 0x10},
357 { CDC_TX2_TX_PATH_CFG1, 0x0B},
358 { CDC_TX2_TX_VOL_CTL, 0x00},
359 { CDC_TX2_TX_PATH_SEC0, 0x00},
360 { CDC_TX2_TX_PATH_SEC1, 0x00},
361 { CDC_TX2_TX_PATH_SEC2, 0x01},
362 { CDC_TX2_TX_PATH_SEC3, 0x3C},
363 { CDC_TX2_TX_PATH_SEC4, 0x20},
364 { CDC_TX2_TX_PATH_SEC5, 0x00},
365 { CDC_TX2_TX_PATH_SEC6, 0x00},
366 { CDC_TX3_TX_PATH_CTL, 0x04},
367 { CDC_TX3_TX_PATH_CFG0, 0x10},
368 { CDC_TX3_TX_PATH_CFG1, 0x0B},
369 { CDC_TX3_TX_VOL_CTL, 0x00},
370 { CDC_TX3_TX_PATH_SEC0, 0x00},
371 { CDC_TX3_TX_PATH_SEC1, 0x00},
372 { CDC_TX3_TX_PATH_SEC2, 0x01},
373 { CDC_TX3_TX_PATH_SEC3, 0x3C},
374 { CDC_TX3_TX_PATH_SEC4, 0x20},
375 { CDC_TX3_TX_PATH_SEC5, 0x00},
376 { CDC_TX3_TX_PATH_SEC6, 0x00},
377 { CDC_TX4_TX_PATH_CTL, 0x04},
378 { CDC_TX4_TX_PATH_CFG0, 0x10},
379 { CDC_TX4_TX_PATH_CFG1, 0x0B},
380 { CDC_TX4_TX_VOL_CTL, 0x00},
381 { CDC_TX4_TX_PATH_SEC0, 0x00},
382 { CDC_TX4_TX_PATH_SEC1, 0x00},
383 { CDC_TX4_TX_PATH_SEC2, 0x01},
384 { CDC_TX4_TX_PATH_SEC3, 0x3C},
385 { CDC_TX4_TX_PATH_SEC4, 0x20},
386 { CDC_TX4_TX_PATH_SEC5, 0x00},
387 { CDC_TX4_TX_PATH_SEC6, 0x00},
388 { CDC_TX5_TX_PATH_CTL, 0x04},
389 { CDC_TX5_TX_PATH_CFG0, 0x10},
390 { CDC_TX5_TX_PATH_CFG1, 0x0B},
391 { CDC_TX5_TX_VOL_CTL, 0x00},
392 { CDC_TX5_TX_PATH_SEC0, 0x00},
393 { CDC_TX5_TX_PATH_SEC1, 0x00},
394 { CDC_TX5_TX_PATH_SEC2, 0x01},
395 { CDC_TX5_TX_PATH_SEC3, 0x3C},
396 { CDC_TX5_TX_PATH_SEC4, 0x20},
397 { CDC_TX5_TX_PATH_SEC5, 0x00},
398 { CDC_TX5_TX_PATH_SEC6, 0x00},
399 { CDC_TX6_TX_PATH_CTL, 0x04},
400 { CDC_TX6_TX_PATH_CFG0, 0x10},
401 { CDC_TX6_TX_PATH_CFG1, 0x0B},
402 { CDC_TX6_TX_VOL_CTL, 0x00},
403 { CDC_TX6_TX_PATH_SEC0, 0x00},
404 { CDC_TX6_TX_PATH_SEC1, 0x00},
405 { CDC_TX6_TX_PATH_SEC2, 0x01},
406 { CDC_TX6_TX_PATH_SEC3, 0x3C},
407 { CDC_TX6_TX_PATH_SEC4, 0x20},
408 { CDC_TX6_TX_PATH_SEC5, 0x00},
409 { CDC_TX6_TX_PATH_SEC6, 0x00},
410 { CDC_TX7_TX_PATH_CTL, 0x04},
411 { CDC_TX7_TX_PATH_CFG0, 0x10},
412 { CDC_TX7_TX_PATH_CFG1, 0x0B},
413 { CDC_TX7_TX_VOL_CTL, 0x00},
414 { CDC_TX7_TX_PATH_SEC0, 0x00},
415 { CDC_TX7_TX_PATH_SEC1, 0x00},
416 { CDC_TX7_TX_PATH_SEC2, 0x01},
417 { CDC_TX7_TX_PATH_SEC3, 0x3C},
418 { CDC_TX7_TX_PATH_SEC4, 0x20},
419 { CDC_TX7_TX_PATH_SEC5, 0x00},
420 { CDC_TX7_TX_PATH_SEC6, 0x00},
421};
422
423static bool tx_is_volatile_register(struct device *dev, unsigned int reg)
424{
425 /* Update volatile list for tx/tx macros */
426 switch (reg) {
427 case CDC_TX_TOP_CSR_SWR_DMIC0_CTL:
428 case CDC_TX_TOP_CSR_SWR_DMIC1_CTL:
429 case CDC_TX_TOP_CSR_SWR_DMIC2_CTL:
430 case CDC_TX_TOP_CSR_SWR_DMIC3_CTL:
431 return true;
432 }
433 return false;
434}
435
436static bool tx_is_rw_register(struct device *dev, unsigned int reg)
437{
438 switch (reg) {
439 case CDC_TX_CLK_RST_CTRL_MCLK_CONTROL:
440 case CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL:
441 case CDC_TX_CLK_RST_CTRL_SWR_CONTROL:
442 case CDC_TX_TOP_CSR_TOP_CFG0:
443 case CDC_TX_TOP_CSR_ANC_CFG:
444 case CDC_TX_TOP_CSR_SWR_CTRL:
445 case CDC_TX_TOP_CSR_FREQ_MCLK:
446 case CDC_TX_TOP_CSR_DEBUG_BUS:
447 case CDC_TX_TOP_CSR_DEBUG_EN:
448 case CDC_TX_TOP_CSR_TX_I2S_CTL:
449 case CDC_TX_TOP_CSR_I2S_CLK:
450 case CDC_TX_TOP_CSR_I2S_RESET:
451 case CDC_TX_TOP_CSR_SWR_DMIC0_CTL:
452 case CDC_TX_TOP_CSR_SWR_DMIC1_CTL:
453 case CDC_TX_TOP_CSR_SWR_DMIC2_CTL:
454 case CDC_TX_TOP_CSR_SWR_DMIC3_CTL:
455 case CDC_TX_TOP_CSR_SWR_AMIC0_CTL:
456 case CDC_TX_TOP_CSR_SWR_AMIC1_CTL:
457 case CDC_TX_ANC0_CLK_RESET_CTL:
458 case CDC_TX_ANC0_MODE_1_CTL:
459 case CDC_TX_ANC0_MODE_2_CTL:
460 case CDC_TX_ANC0_FF_SHIFT:
461 case CDC_TX_ANC0_FB_SHIFT:
462 case CDC_TX_ANC0_LPF_FF_A_CTL:
463 case CDC_TX_ANC0_LPF_FF_B_CTL:
464 case CDC_TX_ANC0_LPF_FB_CTL:
465 case CDC_TX_ANC0_SMLPF_CTL:
466 case CDC_TX_ANC0_DCFLT_SHIFT_CTL:
467 case CDC_TX_ANC0_IIR_ADAPT_CTL:
468 case CDC_TX_ANC0_IIR_COEFF_1_CTL:
469 case CDC_TX_ANC0_IIR_COEFF_2_CTL:
470 case CDC_TX_ANC0_FF_A_GAIN_CTL:
471 case CDC_TX_ANC0_FF_B_GAIN_CTL:
472 case CDC_TX_ANC0_FB_GAIN_CTL:
473 case CDC_TX_INP_MUX_ADC_MUX0_CFG0:
474 case CDC_TX_INP_MUX_ADC_MUX0_CFG1:
475 case CDC_TX_INP_MUX_ADC_MUX1_CFG0:
476 case CDC_TX_INP_MUX_ADC_MUX1_CFG1:
477 case CDC_TX_INP_MUX_ADC_MUX2_CFG0:
478 case CDC_TX_INP_MUX_ADC_MUX2_CFG1:
479 case CDC_TX_INP_MUX_ADC_MUX3_CFG0:
480 case CDC_TX_INP_MUX_ADC_MUX3_CFG1:
481 case CDC_TX_INP_MUX_ADC_MUX4_CFG0:
482 case CDC_TX_INP_MUX_ADC_MUX4_CFG1:
483 case CDC_TX_INP_MUX_ADC_MUX5_CFG0:
484 case CDC_TX_INP_MUX_ADC_MUX5_CFG1:
485 case CDC_TX_INP_MUX_ADC_MUX6_CFG0:
486 case CDC_TX_INP_MUX_ADC_MUX6_CFG1:
487 case CDC_TX_INP_MUX_ADC_MUX7_CFG0:
488 case CDC_TX_INP_MUX_ADC_MUX7_CFG1:
489 case CDC_TX0_TX_PATH_CTL:
490 case CDC_TX0_TX_PATH_CFG0:
491 case CDC_TX0_TX_PATH_CFG1:
492 case CDC_TX0_TX_VOL_CTL:
493 case CDC_TX0_TX_PATH_SEC0:
494 case CDC_TX0_TX_PATH_SEC1:
495 case CDC_TX0_TX_PATH_SEC2:
496 case CDC_TX0_TX_PATH_SEC3:
497 case CDC_TX0_TX_PATH_SEC4:
498 case CDC_TX0_TX_PATH_SEC5:
499 case CDC_TX0_TX_PATH_SEC6:
500 case CDC_TX0_TX_PATH_SEC7:
501 case CDC_TX1_TX_PATH_CTL:
502 case CDC_TX1_TX_PATH_CFG0:
503 case CDC_TX1_TX_PATH_CFG1:
504 case CDC_TX1_TX_VOL_CTL:
505 case CDC_TX1_TX_PATH_SEC0:
506 case CDC_TX1_TX_PATH_SEC1:
507 case CDC_TX1_TX_PATH_SEC2:
508 case CDC_TX1_TX_PATH_SEC3:
509 case CDC_TX1_TX_PATH_SEC4:
510 case CDC_TX1_TX_PATH_SEC5:
511 case CDC_TX1_TX_PATH_SEC6:
512 case CDC_TX2_TX_PATH_CTL:
513 case CDC_TX2_TX_PATH_CFG0:
514 case CDC_TX2_TX_PATH_CFG1:
515 case CDC_TX2_TX_VOL_CTL:
516 case CDC_TX2_TX_PATH_SEC0:
517 case CDC_TX2_TX_PATH_SEC1:
518 case CDC_TX2_TX_PATH_SEC2:
519 case CDC_TX2_TX_PATH_SEC3:
520 case CDC_TX2_TX_PATH_SEC4:
521 case CDC_TX2_TX_PATH_SEC5:
522 case CDC_TX2_TX_PATH_SEC6:
523 case CDC_TX3_TX_PATH_CTL:
524 case CDC_TX3_TX_PATH_CFG0:
525 case CDC_TX3_TX_PATH_CFG1:
526 case CDC_TX3_TX_VOL_CTL:
527 case CDC_TX3_TX_PATH_SEC0:
528 case CDC_TX3_TX_PATH_SEC1:
529 case CDC_TX3_TX_PATH_SEC2:
530 case CDC_TX3_TX_PATH_SEC3:
531 case CDC_TX3_TX_PATH_SEC4:
532 case CDC_TX3_TX_PATH_SEC5:
533 case CDC_TX3_TX_PATH_SEC6:
534 case CDC_TX4_TX_PATH_CTL:
535 case CDC_TX4_TX_PATH_CFG0:
536 case CDC_TX4_TX_PATH_CFG1:
537 case CDC_TX4_TX_VOL_CTL:
538 case CDC_TX4_TX_PATH_SEC0:
539 case CDC_TX4_TX_PATH_SEC1:
540 case CDC_TX4_TX_PATH_SEC2:
541 case CDC_TX4_TX_PATH_SEC3:
542 case CDC_TX4_TX_PATH_SEC4:
543 case CDC_TX4_TX_PATH_SEC5:
544 case CDC_TX4_TX_PATH_SEC6:
545 case CDC_TX5_TX_PATH_CTL:
546 case CDC_TX5_TX_PATH_CFG0:
547 case CDC_TX5_TX_PATH_CFG1:
548 case CDC_TX5_TX_VOL_CTL:
549 case CDC_TX5_TX_PATH_SEC0:
550 case CDC_TX5_TX_PATH_SEC1:
551 case CDC_TX5_TX_PATH_SEC2:
552 case CDC_TX5_TX_PATH_SEC3:
553 case CDC_TX5_TX_PATH_SEC4:
554 case CDC_TX5_TX_PATH_SEC5:
555 case CDC_TX5_TX_PATH_SEC6:
556 case CDC_TX6_TX_PATH_CTL:
557 case CDC_TX6_TX_PATH_CFG0:
558 case CDC_TX6_TX_PATH_CFG1:
559 case CDC_TX6_TX_VOL_CTL:
560 case CDC_TX6_TX_PATH_SEC0:
561 case CDC_TX6_TX_PATH_SEC1:
562 case CDC_TX6_TX_PATH_SEC2:
563 case CDC_TX6_TX_PATH_SEC3:
564 case CDC_TX6_TX_PATH_SEC4:
565 case CDC_TX6_TX_PATH_SEC5:
566 case CDC_TX6_TX_PATH_SEC6:
567 case CDC_TX7_TX_PATH_CTL:
568 case CDC_TX7_TX_PATH_CFG0:
569 case CDC_TX7_TX_PATH_CFG1:
570 case CDC_TX7_TX_VOL_CTL:
571 case CDC_TX7_TX_PATH_SEC0:
572 case CDC_TX7_TX_PATH_SEC1:
573 case CDC_TX7_TX_PATH_SEC2:
574 case CDC_TX7_TX_PATH_SEC3:
575 case CDC_TX7_TX_PATH_SEC4:
576 case CDC_TX7_TX_PATH_SEC5:
577 case CDC_TX7_TX_PATH_SEC6:
578 return true;
579 }
580
581 return false;
582}
583
584static const struct regmap_config tx_regmap_config = {
585 .name = "tx_macro",
586 .reg_bits = 16,
587 .val_bits = 32,
588 .reg_stride = 4,
589 .cache_type = REGCACHE_FLAT,
590 .max_register = TX_MAX_OFFSET,
591 .reg_defaults = tx_defaults,
592 .num_reg_defaults = ARRAY_SIZE(tx_defaults),
593 .writeable_reg = tx_is_rw_register,
594 .volatile_reg = tx_is_volatile_register,
595 .readable_reg = tx_is_rw_register,
596};
597
598static int tx_macro_mclk_enable(struct tx_macro *tx,
599 bool mclk_enable)
600{
601 struct regmap *regmap = tx->regmap;
602
603 if (mclk_enable) {
604 if (tx->tx_mclk_users == 0) {
605 /* 9.6MHz MCLK, set value 0x00 if other frequency */
606 regmap_update_bits(regmap, CDC_TX_TOP_CSR_FREQ_MCLK, 0x01, 0x01);
607 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_MCLK_CONTROL,
608 CDC_TX_MCLK_EN_MASK,
609 CDC_TX_MCLK_ENABLE);
610 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL,
611 CDC_TX_FS_CNT_EN_MASK,
612 CDC_TX_FS_CNT_ENABLE);
613 regcache_mark_dirty(regmap);
614 regcache_sync(regmap);
615 }
616 tx->tx_mclk_users++;
617 } else {
618 if (tx->tx_mclk_users <= 0) {
619 dev_err(tx->dev, "clock already disabled\n");
620 tx->tx_mclk_users = 0;
621 goto exit;
622 }
623 tx->tx_mclk_users--;
624 if (tx->tx_mclk_users == 0) {
625 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL,
626 CDC_TX_FS_CNT_EN_MASK, 0x0);
627 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_MCLK_CONTROL,
628 CDC_TX_MCLK_EN_MASK, 0x0);
629 }
630 }
631exit:
632 return 0;
633}
634
635static bool is_amic_enabled(struct snd_soc_component *component, int decimator)
636{
637 u16 adc_mux_reg, adc_reg, adc_n;
638
639 adc_mux_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG1(decimator);
640
641 if (snd_soc_component_read(component, adc_mux_reg) & SWR_MIC) {
642 adc_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG0(decimator);
643 adc_n = snd_soc_component_read_field(component, adc_reg,
644 CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK);
645 if (adc_n < TX_ADC_MAX)
646 return true;
647 }
648
649 return false;
650}
651
652static void tx_macro_tx_hpf_corner_freq_callback(struct work_struct *work)
653{
654 struct delayed_work *hpf_delayed_work;
655 struct hpf_work *hpf_work;
656 struct tx_macro *tx;
657 struct snd_soc_component *component;
658 u16 dec_cfg_reg, hpf_gate_reg;
659 u8 hpf_cut_off_freq;
660
661 hpf_delayed_work = to_delayed_work(work);
662 hpf_work = container_of(hpf_delayed_work, struct hpf_work, dwork);
663 tx = hpf_work->tx;
664 component = tx->component;
665 hpf_cut_off_freq = hpf_work->hpf_cut_off_freq;
666
667 dec_cfg_reg = CDC_TXn_TX_PATH_CFG0(hpf_work->decimator);
668 hpf_gate_reg = CDC_TXn_TX_PATH_SEC2(hpf_work->decimator);
669
670 if (is_amic_enabled(component, hpf_work->decimator)) {
671 snd_soc_component_write_field(component,
672 dec_cfg_reg,
673 CDC_TXn_HPF_CUT_FREQ_MASK,
674 hpf_cut_off_freq);
675 snd_soc_component_update_bits(component, hpf_gate_reg,
676 CDC_TXn_HPF_F_CHANGE_MASK |
677 CDC_TXn_HPF_ZERO_GATE_MASK,
678 0x02);
679 snd_soc_component_update_bits(component, hpf_gate_reg,
680 CDC_TXn_HPF_F_CHANGE_MASK |
681 CDC_TXn_HPF_ZERO_GATE_MASK,
682 0x01);
683 } else {
684 snd_soc_component_write_field(component, dec_cfg_reg,
685 CDC_TXn_HPF_CUT_FREQ_MASK,
686 hpf_cut_off_freq);
687 snd_soc_component_write_field(component, hpf_gate_reg,
688 CDC_TXn_HPF_F_CHANGE_MASK, 0x1);
689 /* Minimum 1 clk cycle delay is required as per HW spec */
690 usleep_range(1000, 1010);
691 snd_soc_component_write_field(component, hpf_gate_reg,
692 CDC_TXn_HPF_F_CHANGE_MASK, 0x0);
693 }
694}
695
696static void tx_macro_mute_update_callback(struct work_struct *work)
697{
698 struct tx_mute_work *tx_mute_dwork;
699 struct snd_soc_component *component;
700 struct tx_macro *tx;
701 struct delayed_work *delayed_work;
702 u8 decimator;
703
704 delayed_work = to_delayed_work(work);
705 tx_mute_dwork = container_of(delayed_work, struct tx_mute_work, dwork);
706 tx = tx_mute_dwork->tx;
707 component = tx->component;
708 decimator = tx_mute_dwork->decimator;
709
710 snd_soc_component_write_field(component, CDC_TXn_TX_PATH_CTL(decimator),
711 CDC_TXn_PGA_MUTE_MASK, 0x0);
712}
713
d207bdea
SK		 714static int tx_macro_mclk_event(struct snd_soc_dapm_widget *w,
715 struct snd_kcontrol *kcontrol, int event)
716{
717 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
718 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
719
720 switch (event) {
721 case SND_SOC_DAPM_PRE_PMU:
722 tx_macro_mclk_enable(tx, true);
723 break;
724 case SND_SOC_DAPM_POST_PMD:
725 tx_macro_mclk_enable(tx, false);
726 break;
727 default:
728 break;
729 }
730
731 return 0;
732}
733
734static int tx_macro_put_dec_enum(struct snd_kcontrol *kcontrol,
735 struct snd_ctl_elem_value *ucontrol)
736{
737 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
738 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
739 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
740 unsigned int val, dmic;
741 u16 mic_sel_reg;
742 u16 dmic_clk_reg;
743 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
744
745 val = ucontrol->value.enumerated.item[0];
746
747 switch (e->reg) {
748 case CDC_TX_INP_MUX_ADC_MUX0_CFG0:
749 mic_sel_reg = CDC_TX0_TX_PATH_CFG0;
750 break;
751 case CDC_TX_INP_MUX_ADC_MUX1_CFG0:
752 mic_sel_reg = CDC_TX1_TX_PATH_CFG0;
753 break;
754 case CDC_TX_INP_MUX_ADC_MUX2_CFG0:
755 mic_sel_reg = CDC_TX2_TX_PATH_CFG0;
756 break;
757 case CDC_TX_INP_MUX_ADC_MUX3_CFG0:
758 mic_sel_reg = CDC_TX3_TX_PATH_CFG0;
759 break;
760 case CDC_TX_INP_MUX_ADC_MUX4_CFG0:
761 mic_sel_reg = CDC_TX4_TX_PATH_CFG0;
762 break;
763 case CDC_TX_INP_MUX_ADC_MUX5_CFG0:
764 mic_sel_reg = CDC_TX5_TX_PATH_CFG0;
765 break;
766 case CDC_TX_INP_MUX_ADC_MUX6_CFG0:
767 mic_sel_reg = CDC_TX6_TX_PATH_CFG0;
768 break;
769 case CDC_TX_INP_MUX_ADC_MUX7_CFG0:
770 mic_sel_reg = CDC_TX7_TX_PATH_CFG0;
771 break;
772 }
773
774 if (val != 0) {
775 if (val < 5) {
776 snd_soc_component_write_field(component, mic_sel_reg,
777 CDC_TXn_ADC_DMIC_SEL_MASK, 0);
778 } else {
779 snd_soc_component_write_field(component, mic_sel_reg,
780 CDC_TXn_ADC_DMIC_SEL_MASK, 1);
781 dmic = TX_ADC_TO_DMIC(val);
782 dmic_clk_reg = CDC_TX_TOP_CSR_SWR_DMICn_CTL(dmic);
783 snd_soc_component_write_field(component, dmic_clk_reg,
784 CDC_TX_SWR_DMIC_CLK_SEL_MASK,
785 tx->dmic_clk_div);
786 }
787 }
788
789 return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
790}
791
792static int tx_macro_tx_mixer_get(struct snd_kcontrol *kcontrol,
793 struct snd_ctl_elem_value *ucontrol)
794{
795 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
796 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
797 struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value;
798 u32 dai_id = widget->shift;
799 u32 dec_id = mc->shift;
800 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
801
802 if (test_bit(dec_id, &tx->active_ch_mask[dai_id]))
803 ucontrol->value.integer.value[0] = 1;
804 else
805 ucontrol->value.integer.value[0] = 0;
806
807 return 0;
808}
809
810static int tx_macro_tx_mixer_put(struct snd_kcontrol *kcontrol,
811 struct snd_ctl_elem_value *ucontrol)
812{
813 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
814 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
815 struct snd_soc_dapm_update *update = NULL;
816 struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value;
817 u32 dai_id = widget->shift;
818 u32 dec_id = mc->shift;
819 u32 enable = ucontrol->value.integer.value[0];
820 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
821
822 if (enable) {
823 set_bit(dec_id, &tx->active_ch_mask[dai_id]);
824 tx->active_ch_cnt[dai_id]++;
825 tx->active_decimator[dai_id] = dec_id;
826 } else {
827 tx->active_ch_cnt[dai_id]--;
828 clear_bit(dec_id, &tx->active_ch_mask[dai_id]);
829 tx->active_decimator[dai_id] = -1;
830 }
831 snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, update);
832
833 return 0;
834}
835
836static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w,
837 struct snd_kcontrol *kcontrol, int event)
838{
839 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
840 unsigned int decimator;
841 u16 tx_vol_ctl_reg, dec_cfg_reg, hpf_gate_reg, tx_gain_ctl_reg;
842 u8 hpf_cut_off_freq;
843 int hpf_delay = TX_MACRO_DMIC_HPF_DELAY_MS;
844 int unmute_delay = TX_MACRO_DMIC_UNMUTE_DELAY_MS;
845 u16 adc_mux_reg, adc_reg, adc_n, dmic;
846 u16 dmic_clk_reg;
847 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
848
849 decimator = w->shift;
850 tx_vol_ctl_reg = CDC_TXn_TX_PATH_CTL(decimator);
851 hpf_gate_reg = CDC_TXn_TX_PATH_SEC2(decimator);
852 dec_cfg_reg = CDC_TXn_TX_PATH_CFG0(decimator);
853 tx_gain_ctl_reg = CDC_TXn_TX_VOL_CTL(decimator);
854
855 switch (event) {
856 case SND_SOC_DAPM_PRE_PMU:
857 adc_mux_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG1(decimator);
858 if (snd_soc_component_read(component, adc_mux_reg) & SWR_MIC) {
859 adc_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG0(decimator);
860 adc_n = snd_soc_component_read(component, adc_reg) &
861 CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK;
862 if (adc_n >= TX_ADC_MAX) {
863 dmic = TX_ADC_TO_DMIC(adc_n);
864 dmic_clk_reg = CDC_TX_TOP_CSR_SWR_DMICn_CTL(dmic);
865
866 snd_soc_component_write_field(component, dmic_clk_reg,
867 CDC_TX_SWR_DMIC_CLK_SEL_MASK,
868 tx->dmic_clk_div);
869 }
870 }
871 snd_soc_component_write_field(component, dec_cfg_reg,
872 CDC_TXn_ADC_MODE_MASK,
873 tx->dec_mode[decimator]);
874 /* Enable TX PGA Mute */
875 snd_soc_component_write_field(component, tx_vol_ctl_reg,
876 CDC_TXn_PGA_MUTE_MASK, 0x1);
877 break;
878 case SND_SOC_DAPM_POST_PMU:
879 snd_soc_component_write_field(component, tx_vol_ctl_reg,
880 CDC_TXn_CLK_EN_MASK, 0x1);
881 if (!is_amic_enabled(component, decimator)) {
882 snd_soc_component_update_bits(component, hpf_gate_reg, 0x01, 0x00);
883 /* Minimum 1 clk cycle delay is required as per HW spec */
884 usleep_range(1000, 1010);
885 }
886 hpf_cut_off_freq = snd_soc_component_read_field(component, dec_cfg_reg,
887 CDC_TXn_HPF_CUT_FREQ_MASK);
888
889 tx->tx_hpf_work[decimator].hpf_cut_off_freq =
890 hpf_cut_off_freq;
891
892 if (hpf_cut_off_freq != CF_MIN_3DB_150HZ)
893 snd_soc_component_write_field(component, dec_cfg_reg,
894 CDC_TXn_HPF_CUT_FREQ_MASK,
895 CF_MIN_3DB_150HZ);
896
897 if (is_amic_enabled(component, decimator)) {
898 hpf_delay = TX_MACRO_AMIC_HPF_DELAY_MS;
899 unmute_delay = TX_MACRO_AMIC_UNMUTE_DELAY_MS;
900 }
901 /* schedule work queue to Remove Mute */
902 queue_delayed_work(system_freezable_wq,
903 &tx->tx_mute_dwork[decimator].dwork,
904 msecs_to_jiffies(unmute_delay));
905 if (tx->tx_hpf_work[decimator].hpf_cut_off_freq != CF_MIN_3DB_150HZ) {
906 queue_delayed_work(system_freezable_wq,
907 &tx->tx_hpf_work[decimator].dwork,
908 msecs_to_jiffies(hpf_delay));
909 snd_soc_component_update_bits(component, hpf_gate_reg,
910 CDC_TXn_HPF_F_CHANGE_MASK |
911 CDC_TXn_HPF_ZERO_GATE_MASK,
912 0x02);
913 if (!is_amic_enabled(component, decimator))
914 snd_soc_component_update_bits(component, hpf_gate_reg,
915 CDC_TXn_HPF_F_CHANGE_MASK |
916 CDC_TXn_HPF_ZERO_GATE_MASK,
917 0x00);
918 snd_soc_component_update_bits(component, hpf_gate_reg,
919 CDC_TXn_HPF_F_CHANGE_MASK |
920 CDC_TXn_HPF_ZERO_GATE_MASK,
921 0x01);
922
923 /*
924 * 6ms delay is required as per HW spec
925 */
926 usleep_range(6000, 6010);
927 }
928 /* apply gain after decimator is enabled */
929 snd_soc_component_write(component, tx_gain_ctl_reg,
930 snd_soc_component_read(component,
931 tx_gain_ctl_reg));
932 if (tx->bcs_enable) {
933 snd_soc_component_update_bits(component, dec_cfg_reg,
934 0x01, 0x01);
935 tx->bcs_clk_en = true;
936 }
937 break;
938 case SND_SOC_DAPM_PRE_PMD:
939 hpf_cut_off_freq =
940 tx->tx_hpf_work[decimator].hpf_cut_off_freq;
941 snd_soc_component_write_field(component, tx_vol_ctl_reg,
942 CDC_TXn_PGA_MUTE_MASK, 0x1);
943 if (cancel_delayed_work_sync(
944 &tx->tx_hpf_work[decimator].dwork)) {
945 if (hpf_cut_off_freq != CF_MIN_3DB_150HZ) {
946 snd_soc_component_write_field(
947 component, dec_cfg_reg,
948 CDC_TXn_HPF_CUT_FREQ_MASK,
949 hpf_cut_off_freq);
950 if (is_amic_enabled(component, decimator))
951 snd_soc_component_update_bits(component,
952 hpf_gate_reg,
953 CDC_TXn_HPF_F_CHANGE_MASK |
954 CDC_TXn_HPF_ZERO_GATE_MASK,
955 0x02);
956 else
957 snd_soc_component_update_bits(component,
958 hpf_gate_reg,
959 CDC_TXn_HPF_F_CHANGE_MASK |
960 CDC_TXn_HPF_ZERO_GATE_MASK,
961 0x03);
962
963 /*
964 * Minimum 1 clk cycle delay is required
965 * as per HW spec
966 */
967 usleep_range(1000, 1010);
968 snd_soc_component_update_bits(component, hpf_gate_reg,
969 CDC_TXn_HPF_F_CHANGE_MASK |
970 CDC_TXn_HPF_ZERO_GATE_MASK,
971 0x1);
972 }
973 }
974 cancel_delayed_work_sync(&tx->tx_mute_dwork[decimator].dwork);
975 break;
976 case SND_SOC_DAPM_POST_PMD:
977 snd_soc_component_write_field(component, tx_vol_ctl_reg,
978 CDC_TXn_CLK_EN_MASK, 0x0);
979 snd_soc_component_write_field(component, dec_cfg_reg,
980 CDC_TXn_ADC_MODE_MASK, 0x0);
981 snd_soc_component_write_field(component, tx_vol_ctl_reg,
982 CDC_TXn_PGA_MUTE_MASK, 0x0);
983 if (tx->bcs_enable) {
984 snd_soc_component_write_field(component, dec_cfg_reg,
985 CDC_TXn_PH_EN_MASK, 0x0);
986 snd_soc_component_write_field(component,
987 CDC_TX0_TX_PATH_SEC7,
988 CDC_TX0_MBHC_CTL_EN_MASK,
989 0x0);
990 tx->bcs_clk_en = false;
991 }
992 break;
993 }
994 return 0;
995}
996
c39667dd
SK		 997static int tx_macro_dec_mode_get(struct snd_kcontrol *kcontrol,
998 struct snd_ctl_elem_value *ucontrol)
999{
1000 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1001 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1002 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1003 int path = e->shift_l;
1004
1005 ucontrol->value.integer.value[0] = tx->dec_mode[path];
1006
1007 return 0;
1008}
1009
1010static int tx_macro_dec_mode_put(struct snd_kcontrol *kcontrol,
1011 struct snd_ctl_elem_value *ucontrol)
1012{
1013 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1014 int value = ucontrol->value.integer.value[0];
1015 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1016 int path = e->shift_l;
1017 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1018
1019 tx->dec_mode[path] = value;
1020
1021 return 0;
1022}
1023
1024static int tx_macro_get_bcs(struct snd_kcontrol *kcontrol,
1025 struct snd_ctl_elem_value *ucontrol)
1026{
1027 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1028 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1029
1030 ucontrol->value.integer.value[0] = tx->bcs_enable;
1031
1032 return 0;
1033}
1034
1035static int tx_macro_set_bcs(struct snd_kcontrol *kcontrol,
1036 struct snd_ctl_elem_value *ucontrol)
1037{
1038 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1039 int value = ucontrol->value.integer.value[0];
1040 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1041
1042 tx->bcs_enable = value;
1043
1044 return 0;
1045}
1046
1047static int tx_macro_hw_params(struct snd_pcm_substream *substream,
1048 struct snd_pcm_hw_params *params,
1049 struct snd_soc_dai *dai)
1050{
1051 struct snd_soc_component *component = dai->component;
1052 u32 decimator, sample_rate;
1053 int tx_fs_rate;
1054 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1055
1056 sample_rate = params_rate(params);
1057 switch (sample_rate) {
1058 case 8000:
1059 tx_fs_rate = 0;
1060 break;
1061 case 16000:
1062 tx_fs_rate = 1;
1063 break;
1064 case 32000:
1065 tx_fs_rate = 3;
1066 break;
1067 case 48000:
1068 tx_fs_rate = 4;
1069 break;
1070 case 96000:
1071 tx_fs_rate = 5;
1072 break;
1073 case 192000:
1074 tx_fs_rate = 6;
1075 break;
1076 case 384000:
1077 tx_fs_rate = 7;
1078 break;
1079 default:
1080 dev_err(component->dev, "%s: Invalid TX sample rate: %d\n",
1081 __func__, params_rate(params));
1082 return -EINVAL;
1083 }
1084
1085 for_each_set_bit(decimator, &tx->active_ch_mask[dai->id], TX_MACRO_DEC_MAX)
1086 snd_soc_component_update_bits(component, CDC_TXn_TX_PATH_CTL(decimator),
1087 CDC_TXn_PCM_RATE_MASK,
1088 tx_fs_rate);
1089 return 0;
1090}
1091
1092static int tx_macro_get_channel_map(struct snd_soc_dai *dai,
1093 unsigned int *tx_num, unsigned int *tx_slot,
1094 unsigned int *rx_num, unsigned int *rx_slot)
1095{
1096 struct snd_soc_component *component = dai->component;
1097 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1098
1099 switch (dai->id) {
1100 case TX_MACRO_AIF1_CAP:
1101 case TX_MACRO_AIF2_CAP:
1102 case TX_MACRO_AIF3_CAP:
1103 *tx_slot = tx->active_ch_mask[dai->id];
1104 *tx_num = tx->active_ch_cnt[dai->id];
1105 break;
1106 default:
1107 break;
1108 }
1109 return 0;
1110}
1111
1112static int tx_macro_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
1113{
1114 struct snd_soc_component *component = dai->component;
1115 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1116 u16 decimator;
1117
1118 decimator = tx->active_decimator[dai->id];
1119
1120 if (mute)
1121 snd_soc_component_write_field(component,
1122 CDC_TXn_TX_PATH_CTL(decimator),
1123 CDC_TXn_PGA_MUTE_MASK, 0x1);
1124 else
1125 snd_soc_component_update_bits(component,
1126 CDC_TXn_TX_PATH_CTL(decimator),
1127 CDC_TXn_PGA_MUTE_MASK, 0x0);
1128
1129 return 0;
1130}
1131
81df40a0 1132static const struct snd_soc_dai_ops tx_macro_dai_ops = {
c39667dd
SK		 1133 .hw_params = tx_macro_hw_params,
1134 .get_channel_map = tx_macro_get_channel_map,
1135 .mute_stream = tx_macro_digital_mute,
1136};
1137
1138static struct snd_soc_dai_driver tx_macro_dai[] = {
1139 {
1140 .name = "tx_macro_tx1",
1141 .id = TX_MACRO_AIF1_CAP,
1142 .capture = {
1143 .stream_name = "TX_AIF1 Capture",
1144 .rates = TX_MACRO_RATES,
1145 .formats = TX_MACRO_FORMATS,
1146 .rate_max = 192000,
1147 .rate_min = 8000,
1148 .channels_min = 1,
1149 .channels_max = 8,
1150 },
1151 .ops = &tx_macro_dai_ops,
1152 },
1153 {
1154 .name = "tx_macro_tx2",
1155 .id = TX_MACRO_AIF2_CAP,
1156 .capture = {
1157 .stream_name = "TX_AIF2 Capture",
1158 .rates = TX_MACRO_RATES,
1159 .formats = TX_MACRO_FORMATS,
1160 .rate_max = 192000,
1161 .rate_min = 8000,
1162 .channels_min = 1,
1163 .channels_max = 8,
1164 },
1165 .ops = &tx_macro_dai_ops,
1166 },
1167 {
1168 .name = "tx_macro_tx3",
1169 .id = TX_MACRO_AIF3_CAP,
1170 .capture = {
1171 .stream_name = "TX_AIF3 Capture",
1172 .rates = TX_MACRO_RATES,
1173 .formats = TX_MACRO_FORMATS,
1174 .rate_max = 192000,
1175 .rate_min = 8000,
1176 .channels_min = 1,
1177 .channels_max = 8,
1178 },
1179 .ops = &tx_macro_dai_ops,
1180 },
1181};
1182
d207bdea
SK		 1183static const char * const adc_mux_text[] = {
1184 "MSM_DMIC", "SWR_MIC", "ANC_FB_TUNE1"
1185};
1186
1187static SOC_ENUM_SINGLE_DECL(tx_dec0_enum, CDC_TX_INP_MUX_ADC_MUX0_CFG1,
1188 0, adc_mux_text);
1189static SOC_ENUM_SINGLE_DECL(tx_dec1_enum, CDC_TX_INP_MUX_ADC_MUX1_CFG1,
1190 0, adc_mux_text);
1191static SOC_ENUM_SINGLE_DECL(tx_dec2_enum, CDC_TX_INP_MUX_ADC_MUX2_CFG1,
1192 0, adc_mux_text);
1193static SOC_ENUM_SINGLE_DECL(tx_dec3_enum, CDC_TX_INP_MUX_ADC_MUX3_CFG1,
1194 0, adc_mux_text);
1195static SOC_ENUM_SINGLE_DECL(tx_dec4_enum, CDC_TX_INP_MUX_ADC_MUX4_CFG1,
1196 0, adc_mux_text);
1197static SOC_ENUM_SINGLE_DECL(tx_dec5_enum, CDC_TX_INP_MUX_ADC_MUX5_CFG1,
1198 0, adc_mux_text);
1199static SOC_ENUM_SINGLE_DECL(tx_dec6_enum, CDC_TX_INP_MUX_ADC_MUX6_CFG1,
1200 0, adc_mux_text);
1201static SOC_ENUM_SINGLE_DECL(tx_dec7_enum, CDC_TX_INP_MUX_ADC_MUX7_CFG1,
1202 0, adc_mux_text);
1203
1204static const struct snd_kcontrol_new tx_dec0_mux = SOC_DAPM_ENUM("tx_dec0", tx_dec0_enum);
1205static const struct snd_kcontrol_new tx_dec1_mux = SOC_DAPM_ENUM("tx_dec1", tx_dec1_enum);
1206static const struct snd_kcontrol_new tx_dec2_mux = SOC_DAPM_ENUM("tx_dec2", tx_dec2_enum);
1207static const struct snd_kcontrol_new tx_dec3_mux = SOC_DAPM_ENUM("tx_dec3", tx_dec3_enum);
1208static const struct snd_kcontrol_new tx_dec4_mux = SOC_DAPM_ENUM("tx_dec4", tx_dec4_enum);
1209static const struct snd_kcontrol_new tx_dec5_mux = SOC_DAPM_ENUM("tx_dec5", tx_dec5_enum);
1210static const struct snd_kcontrol_new tx_dec6_mux = SOC_DAPM_ENUM("tx_dec6", tx_dec6_enum);
1211static const struct snd_kcontrol_new tx_dec7_mux = SOC_DAPM_ENUM("tx_dec7", tx_dec7_enum);
1212
1213static const char * const smic_mux_text[] = {
1214 "ZERO", "ADC0", "ADC1", "ADC2", "ADC3", "SWR_DMIC0",
1215 "SWR_DMIC1", "SWR_DMIC2", "SWR_DMIC3", "SWR_DMIC4",
1216 "SWR_DMIC5", "SWR_DMIC6", "SWR_DMIC7"
1217};
1218
1219static SOC_ENUM_SINGLE_DECL(tx_smic0_enum, CDC_TX_INP_MUX_ADC_MUX0_CFG0,
1220 0, smic_mux_text);
1221
1222static SOC_ENUM_SINGLE_DECL(tx_smic1_enum, CDC_TX_INP_MUX_ADC_MUX1_CFG0,
1223 0, smic_mux_text);
1224
1225static SOC_ENUM_SINGLE_DECL(tx_smic2_enum, CDC_TX_INP_MUX_ADC_MUX2_CFG0,
1226 0, smic_mux_text);
1227
1228static SOC_ENUM_SINGLE_DECL(tx_smic3_enum, CDC_TX_INP_MUX_ADC_MUX3_CFG0,
1229 0, smic_mux_text);
1230
1231static SOC_ENUM_SINGLE_DECL(tx_smic4_enum, CDC_TX_INP_MUX_ADC_MUX4_CFG0,
1232 0, smic_mux_text);
1233
1234static SOC_ENUM_SINGLE_DECL(tx_smic5_enum, CDC_TX_INP_MUX_ADC_MUX5_CFG0,
1235 0, smic_mux_text);
1236
1237static SOC_ENUM_SINGLE_DECL(tx_smic6_enum, CDC_TX_INP_MUX_ADC_MUX6_CFG0,
1238 0, smic_mux_text);
1239
1240static SOC_ENUM_SINGLE_DECL(tx_smic7_enum, CDC_TX_INP_MUX_ADC_MUX7_CFG0,
1241 0, smic_mux_text);
1242
1243static const struct snd_kcontrol_new tx_smic0_mux = SOC_DAPM_ENUM_EXT("tx_smic0", tx_smic0_enum,
1244 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1245static const struct snd_kcontrol_new tx_smic1_mux = SOC_DAPM_ENUM_EXT("tx_smic1", tx_smic1_enum,
1246 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1247static const struct snd_kcontrol_new tx_smic2_mux = SOC_DAPM_ENUM_EXT("tx_smic2", tx_smic2_enum,
1248 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1249static const struct snd_kcontrol_new tx_smic3_mux = SOC_DAPM_ENUM_EXT("tx_smic3", tx_smic3_enum,
1250 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1251static const struct snd_kcontrol_new tx_smic4_mux = SOC_DAPM_ENUM_EXT("tx_smic4", tx_smic4_enum,
1252 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1253static const struct snd_kcontrol_new tx_smic5_mux = SOC_DAPM_ENUM_EXT("tx_smic5", tx_smic5_enum,
1254 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1255static const struct snd_kcontrol_new tx_smic6_mux = SOC_DAPM_ENUM_EXT("tx_smic6", tx_smic6_enum,
1256 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1257static const struct snd_kcontrol_new tx_smic7_mux = SOC_DAPM_ENUM_EXT("tx_smic7", tx_smic7_enum,
1258 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1259
c39667dd
SK		 1260static const char * const dec_mode_mux_text[] = {
1261 "ADC_DEFAULT", "ADC_LOW_PWR", "ADC_HIGH_PERF",
1262};
1263
1264static const struct soc_enum dec_mode_mux_enum[] = {
1265 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(dec_mode_mux_text),
1266 dec_mode_mux_text),
1267 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(dec_mode_mux_text),
1268 dec_mode_mux_text),
1269 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(dec_mode_mux_text),
1270 dec_mode_mux_text),
1271 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(dec_mode_mux_text),
1272 dec_mode_mux_text),
1273 SOC_ENUM_SINGLE(SND_SOC_NOPM, 4, ARRAY_SIZE(dec_mode_mux_text),
1274 dec_mode_mux_text),
1275 SOC_ENUM_SINGLE(SND_SOC_NOPM, 5, ARRAY_SIZE(dec_mode_mux_text),
1276 dec_mode_mux_text),
1277 SOC_ENUM_SINGLE(SND_SOC_NOPM, 6, ARRAY_SIZE(dec_mode_mux_text),
1278 dec_mode_mux_text),
1279 SOC_ENUM_SINGLE(SND_SOC_NOPM, 7, ARRAY_SIZE(dec_mode_mux_text),
1280 dec_mode_mux_text),
1281};
1282
d207bdea
SK		 1283static const struct snd_kcontrol_new tx_aif1_cap_mixer[] = {
1284 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0,
1285 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1286 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0,
1287 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1288 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0,
1289 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1290 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0,
1291 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1292 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0,
1293 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1294 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0,
1295 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1296 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0,
1297 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1298 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0,
1299 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1300};
1301
1302static const struct snd_kcontrol_new tx_aif2_cap_mixer[] = {
1303 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0,
1304 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1305 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0,
1306 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1307 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0,
1308 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1309 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0,
1310 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1311 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0,
1312 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1313 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0,
1314 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1315 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0,
1316 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1317 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0,
1318 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1319};
1320
1321static const struct snd_kcontrol_new tx_aif3_cap_mixer[] = {
1322 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0,
1323 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1324 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0,
1325 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1326 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0,
1327 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1328 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0,
1329 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1330 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0,
1331 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1332 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0,
1333 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1334 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0,
1335 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1336 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0,
1337 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1338};
1339
1340static const struct snd_soc_dapm_widget tx_macro_dapm_widgets[] = {
1341 SND_SOC_DAPM_AIF_OUT("TX_AIF1 CAP", "TX_AIF1 Capture", 0,
1342 SND_SOC_NOPM, TX_MACRO_AIF1_CAP, 0),
1343
1344 SND_SOC_DAPM_AIF_OUT("TX_AIF2 CAP", "TX_AIF2 Capture", 0,
1345 SND_SOC_NOPM, TX_MACRO_AIF2_CAP, 0),
1346
1347 SND_SOC_DAPM_AIF_OUT("TX_AIF3 CAP", "TX_AIF3 Capture", 0,
1348 SND_SOC_NOPM, TX_MACRO_AIF3_CAP, 0),
1349
1350 SND_SOC_DAPM_MIXER("TX_AIF1_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF1_CAP, 0,
1351 tx_aif1_cap_mixer, ARRAY_SIZE(tx_aif1_cap_mixer)),
1352
1353 SND_SOC_DAPM_MIXER("TX_AIF2_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF2_CAP, 0,
1354 tx_aif2_cap_mixer, ARRAY_SIZE(tx_aif2_cap_mixer)),
1355
1356 SND_SOC_DAPM_MIXER("TX_AIF3_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF3_CAP, 0,
1357 tx_aif3_cap_mixer, ARRAY_SIZE(tx_aif3_cap_mixer)),
1358
1359 SND_SOC_DAPM_MUX("TX SMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_smic0_mux),
1360 SND_SOC_DAPM_MUX("TX SMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_smic1_mux),
1361 SND_SOC_DAPM_MUX("TX SMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_smic2_mux),
1362 SND_SOC_DAPM_MUX("TX SMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_smic3_mux),
1363 SND_SOC_DAPM_MUX("TX SMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_smic4_mux),
1364 SND_SOC_DAPM_MUX("TX SMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_smic5_mux),
1365 SND_SOC_DAPM_MUX("TX SMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_smic6_mux),
1366 SND_SOC_DAPM_MUX("TX SMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_smic7_mux),
1367
1368 SND_SOC_DAPM_INPUT("TX SWR_ADC0"),
1369 SND_SOC_DAPM_INPUT("TX SWR_ADC1"),
1370 SND_SOC_DAPM_INPUT("TX SWR_ADC2"),
1371 SND_SOC_DAPM_INPUT("TX SWR_ADC3"),
1372 SND_SOC_DAPM_INPUT("TX SWR_DMIC0"),
1373 SND_SOC_DAPM_INPUT("TX SWR_DMIC1"),
1374 SND_SOC_DAPM_INPUT("TX SWR_DMIC2"),
1375 SND_SOC_DAPM_INPUT("TX SWR_DMIC3"),
1376 SND_SOC_DAPM_INPUT("TX SWR_DMIC4"),
1377 SND_SOC_DAPM_INPUT("TX SWR_DMIC5"),
1378 SND_SOC_DAPM_INPUT("TX SWR_DMIC6"),
1379 SND_SOC_DAPM_INPUT("TX SWR_DMIC7"),
1380
1381 SND_SOC_DAPM_MUX_E("TX DEC0 MUX", SND_SOC_NOPM,
1382 TX_MACRO_DEC0, 0,
1383 &tx_dec0_mux, tx_macro_enable_dec,
1384 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1385 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1386
1387 SND_SOC_DAPM_MUX_E("TX DEC1 MUX", SND_SOC_NOPM,
1388 TX_MACRO_DEC1, 0,
1389 &tx_dec1_mux, tx_macro_enable_dec,
1390 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1391 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1392
1393 SND_SOC_DAPM_MUX_E("TX DEC2 MUX", SND_SOC_NOPM,
1394 TX_MACRO_DEC2, 0,
1395 &tx_dec2_mux, tx_macro_enable_dec,
1396 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1397 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1398
1399 SND_SOC_DAPM_MUX_E("TX DEC3 MUX", SND_SOC_NOPM,
1400 TX_MACRO_DEC3, 0,
1401 &tx_dec3_mux, tx_macro_enable_dec,
1402 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1403 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1404
1405 SND_SOC_DAPM_MUX_E("TX DEC4 MUX", SND_SOC_NOPM,
1406 TX_MACRO_DEC4, 0,
1407 &tx_dec4_mux, tx_macro_enable_dec,
1408 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1409 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1410
1411 SND_SOC_DAPM_MUX_E("TX DEC5 MUX", SND_SOC_NOPM,
1412 TX_MACRO_DEC5, 0,
1413 &tx_dec5_mux, tx_macro_enable_dec,
1414 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1415 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1416
1417 SND_SOC_DAPM_MUX_E("TX DEC6 MUX", SND_SOC_NOPM,
1418 TX_MACRO_DEC6, 0,
1419 &tx_dec6_mux, tx_macro_enable_dec,
1420 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1421 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1422
1423 SND_SOC_DAPM_MUX_E("TX DEC7 MUX", SND_SOC_NOPM,
1424 TX_MACRO_DEC7, 0,
1425 &tx_dec7_mux, tx_macro_enable_dec,
1426 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1427 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1428
1429 SND_SOC_DAPM_SUPPLY_S("TX_MCLK", 0, SND_SOC_NOPM, 0, 0,
1430 tx_macro_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1431
1432 SND_SOC_DAPM_SUPPLY_S("TX_SWR_CLK", 0, SND_SOC_NOPM, 0, 0, NULL, 0),
1433
1434 SND_SOC_DAPM_SUPPLY_S("VA_SWR_CLK", 0, SND_SOC_NOPM, 0, 0,
1435 NULL, 0),
1436};
1437
1438static const struct snd_soc_dapm_route tx_audio_map[] = {
1439 {"TX_AIF1 CAP", NULL, "TX_MCLK"},
1440 {"TX_AIF2 CAP", NULL, "TX_MCLK"},
1441 {"TX_AIF3 CAP", NULL, "TX_MCLK"},
1442
1443 {"TX_AIF1 CAP", NULL, "TX_AIF1_CAP Mixer"},
1444 {"TX_AIF2 CAP", NULL, "TX_AIF2_CAP Mixer"},
1445 {"TX_AIF3 CAP", NULL, "TX_AIF3_CAP Mixer"},
1446
1447 {"TX_AIF1_CAP Mixer", "DEC0", "TX DEC0 MUX"},
1448 {"TX_AIF1_CAP Mixer", "DEC1", "TX DEC1 MUX"},
1449 {"TX_AIF1_CAP Mixer", "DEC2", "TX DEC2 MUX"},
1450 {"TX_AIF1_CAP Mixer", "DEC3", "TX DEC3 MUX"},
1451 {"TX_AIF1_CAP Mixer", "DEC4", "TX DEC4 MUX"},
1452 {"TX_AIF1_CAP Mixer", "DEC5", "TX DEC5 MUX"},
1453 {"TX_AIF1_CAP Mixer", "DEC6", "TX DEC6 MUX"},
1454 {"TX_AIF1_CAP Mixer", "DEC7", "TX DEC7 MUX"},
1455
1456 {"TX_AIF2_CAP Mixer", "DEC0", "TX DEC0 MUX"},
1457 {"TX_AIF2_CAP Mixer", "DEC1", "TX DEC1 MUX"},
1458 {"TX_AIF2_CAP Mixer", "DEC2", "TX DEC2 MUX"},
1459 {"TX_AIF2_CAP Mixer", "DEC3", "TX DEC3 MUX"},
1460 {"TX_AIF2_CAP Mixer", "DEC4", "TX DEC4 MUX"},
1461 {"TX_AIF2_CAP Mixer", "DEC5", "TX DEC5 MUX"},
1462 {"TX_AIF2_CAP Mixer", "DEC6", "TX DEC6 MUX"},
1463 {"TX_AIF2_CAP Mixer", "DEC7", "TX DEC7 MUX"},
1464
1465 {"TX_AIF3_CAP Mixer", "DEC0", "TX DEC0 MUX"},
1466 {"TX_AIF3_CAP Mixer", "DEC1", "TX DEC1 MUX"},
1467 {"TX_AIF3_CAP Mixer", "DEC2", "TX DEC2 MUX"},
1468 {"TX_AIF3_CAP Mixer", "DEC3", "TX DEC3 MUX"},
1469 {"TX_AIF3_CAP Mixer", "DEC4", "TX DEC4 MUX"},
1470 {"TX_AIF3_CAP Mixer", "DEC5", "TX DEC5 MUX"},
1471 {"TX_AIF3_CAP Mixer", "DEC6", "TX DEC6 MUX"},
1472 {"TX_AIF3_CAP Mixer", "DEC7", "TX DEC7 MUX"},
1473
1474 {"TX DEC0 MUX", NULL, "TX_MCLK"},
1475 {"TX DEC1 MUX", NULL, "TX_MCLK"},
1476 {"TX DEC2 MUX", NULL, "TX_MCLK"},
1477 {"TX DEC3 MUX", NULL, "TX_MCLK"},
1478 {"TX DEC4 MUX", NULL, "TX_MCLK"},
1479 {"TX DEC5 MUX", NULL, "TX_MCLK"},
1480 {"TX DEC6 MUX", NULL, "TX_MCLK"},
1481 {"TX DEC7 MUX", NULL, "TX_MCLK"},
1482
1483 {"TX DEC0 MUX", "SWR_MIC", "TX SMIC MUX0"},
1484 {"TX SMIC MUX0", NULL, "TX_SWR_CLK"},
1485 {"TX SMIC MUX0", "ADC0", "TX SWR_ADC0"},
1486 {"TX SMIC MUX0", "ADC1", "TX SWR_ADC1"},
1487 {"TX SMIC MUX0", "ADC2", "TX SWR_ADC2"},
1488 {"TX SMIC MUX0", "ADC3", "TX SWR_ADC3"},
1489 {"TX SMIC MUX0", "SWR_DMIC0", "TX SWR_DMIC0"},
1490 {"TX SMIC MUX0", "SWR_DMIC1", "TX SWR_DMIC1"},
1491 {"TX SMIC MUX0", "SWR_DMIC2", "TX SWR_DMIC2"},
1492 {"TX SMIC MUX0", "SWR_DMIC3", "TX SWR_DMIC3"},
1493 {"TX SMIC MUX0", "SWR_DMIC4", "TX SWR_DMIC4"},
1494 {"TX SMIC MUX0", "SWR_DMIC5", "TX SWR_DMIC5"},
1495 {"TX SMIC MUX0", "SWR_DMIC6", "TX SWR_DMIC6"},
1496 {"TX SMIC MUX0", "SWR_DMIC7", "TX SWR_DMIC7"},
1497
1498 {"TX DEC1 MUX", "SWR_MIC", "TX SMIC MUX1"},
1499 {"TX SMIC MUX1", NULL, "TX_SWR_CLK"},
1500 {"TX SMIC MUX1", "ADC0", "TX SWR_ADC0"},
1501 {"TX SMIC MUX1", "ADC1", "TX SWR_ADC1"},
1502 {"TX SMIC MUX1", "ADC2", "TX SWR_ADC2"},
1503 {"TX SMIC MUX1", "ADC3", "TX SWR_ADC3"},
1504 {"TX SMIC MUX1", "SWR_DMIC0", "TX SWR_DMIC0"},
1505 {"TX SMIC MUX1", "SWR_DMIC1", "TX SWR_DMIC1"},
1506 {"TX SMIC MUX1", "SWR_DMIC2", "TX SWR_DMIC2"},
1507 {"TX SMIC MUX1", "SWR_DMIC3", "TX SWR_DMIC3"},
1508 {"TX SMIC MUX1", "SWR_DMIC4", "TX SWR_DMIC4"},
1509 {"TX SMIC MUX1", "SWR_DMIC5", "TX SWR_DMIC5"},
1510 {"TX SMIC MUX1", "SWR_DMIC6", "TX SWR_DMIC6"},
1511 {"TX SMIC MUX1", "SWR_DMIC7", "TX SWR_DMIC7"},
1512
1513 {"TX DEC2 MUX", "SWR_MIC", "TX SMIC MUX2"},
1514 {"TX SMIC MUX2", NULL, "TX_SWR_CLK"},
1515 {"TX SMIC MUX2", "ADC0", "TX SWR_ADC0"},
1516 {"TX SMIC MUX2", "ADC1", "TX SWR_ADC1"},
1517 {"TX SMIC MUX2", "ADC2", "TX SWR_ADC2"},
1518 {"TX SMIC MUX2", "ADC3", "TX SWR_ADC3"},
1519 {"TX SMIC MUX2", "SWR_DMIC0", "TX SWR_DMIC0"},
1520 {"TX SMIC MUX2", "SWR_DMIC1", "TX SWR_DMIC1"},
1521 {"TX SMIC MUX2", "SWR_DMIC2", "TX SWR_DMIC2"},
1522 {"TX SMIC MUX2", "SWR_DMIC3", "TX SWR_DMIC3"},
1523 {"TX SMIC MUX2", "SWR_DMIC4", "TX SWR_DMIC4"},
1524 {"TX SMIC MUX2", "SWR_DMIC5", "TX SWR_DMIC5"},
1525 {"TX SMIC MUX2", "SWR_DMIC6", "TX SWR_DMIC6"},
1526 {"TX SMIC MUX2", "SWR_DMIC7", "TX SWR_DMIC7"},
1527
1528 {"TX DEC3 MUX", "SWR_MIC", "TX SMIC MUX3"},
1529 {"TX SMIC MUX3", NULL, "TX_SWR_CLK"},
1530 {"TX SMIC MUX3", "ADC0", "TX SWR_ADC0"},
1531 {"TX SMIC MUX3", "ADC1", "TX SWR_ADC1"},
1532 {"TX SMIC MUX3", "ADC2", "TX SWR_ADC2"},
1533 {"TX SMIC MUX3", "ADC3", "TX SWR_ADC3"},
1534 {"TX SMIC MUX3", "SWR_DMIC0", "TX SWR_DMIC0"},
1535 {"TX SMIC MUX3", "SWR_DMIC1", "TX SWR_DMIC1"},
1536 {"TX SMIC MUX3", "SWR_DMIC2", "TX SWR_DMIC2"},
1537 {"TX SMIC MUX3", "SWR_DMIC3", "TX SWR_DMIC3"},
1538 {"TX SMIC MUX3", "SWR_DMIC4", "TX SWR_DMIC4"},
1539 {"TX SMIC MUX3", "SWR_DMIC5", "TX SWR_DMIC5"},
1540 {"TX SMIC MUX3", "SWR_DMIC6", "TX SWR_DMIC6"},
1541 {"TX SMIC MUX3", "SWR_DMIC7", "TX SWR_DMIC7"},
1542
1543 {"TX DEC4 MUX", "SWR_MIC", "TX SMIC MUX4"},
1544 {"TX SMIC MUX4", NULL, "TX_SWR_CLK"},
1545 {"TX SMIC MUX4", "ADC0", "TX SWR_ADC0"},
1546 {"TX SMIC MUX4", "ADC1", "TX SWR_ADC1"},
1547 {"TX SMIC MUX4", "ADC2", "TX SWR_ADC2"},
1548 {"TX SMIC MUX4", "ADC3", "TX SWR_ADC3"},
1549 {"TX SMIC MUX4", "SWR_DMIC0", "TX SWR_DMIC0"},
1550 {"TX SMIC MUX4", "SWR_DMIC1", "TX SWR_DMIC1"},
1551 {"TX SMIC MUX4", "SWR_DMIC2", "TX SWR_DMIC2"},
1552 {"TX SMIC MUX4", "SWR_DMIC3", "TX SWR_DMIC3"},
1553 {"TX SMIC MUX4", "SWR_DMIC4", "TX SWR_DMIC4"},
1554 {"TX SMIC MUX4", "SWR_DMIC5", "TX SWR_DMIC5"},
1555 {"TX SMIC MUX4", "SWR_DMIC6", "TX SWR_DMIC6"},
1556 {"TX SMIC MUX4", "SWR_DMIC7", "TX SWR_DMIC7"},
1557
1558 {"TX DEC5 MUX", "SWR_MIC", "TX SMIC MUX5"},
1559 {"TX SMIC MUX5", NULL, "TX_SWR_CLK"},
1560 {"TX SMIC MUX5", "ADC0", "TX SWR_ADC0"},
1561 {"TX SMIC MUX5", "ADC1", "TX SWR_ADC1"},
1562 {"TX SMIC MUX5", "ADC2", "TX SWR_ADC2"},
1563 {"TX SMIC MUX5", "ADC3", "TX SWR_ADC3"},
1564 {"TX SMIC MUX5", "SWR_DMIC0", "TX SWR_DMIC0"},
1565 {"TX SMIC MUX5", "SWR_DMIC1", "TX SWR_DMIC1"},
1566 {"TX SMIC MUX5", "SWR_DMIC2", "TX SWR_DMIC2"},
1567 {"TX SMIC MUX5", "SWR_DMIC3", "TX SWR_DMIC3"},
1568 {"TX SMIC MUX5", "SWR_DMIC4", "TX SWR_DMIC4"},
1569 {"TX SMIC MUX5", "SWR_DMIC5", "TX SWR_DMIC5"},
1570 {"TX SMIC MUX5", "SWR_DMIC6", "TX SWR_DMIC6"},
1571 {"TX SMIC MUX5", "SWR_DMIC7", "TX SWR_DMIC7"},
1572
1573 {"TX DEC6 MUX", "SWR_MIC", "TX SMIC MUX6"},
1574 {"TX SMIC MUX6", NULL, "TX_SWR_CLK"},
1575 {"TX SMIC MUX6", "ADC0", "TX SWR_ADC0"},
1576 {"TX SMIC MUX6", "ADC1", "TX SWR_ADC1"},
1577 {"TX SMIC MUX6", "ADC2", "TX SWR_ADC2"},
1578 {"TX SMIC MUX6", "ADC3", "TX SWR_ADC3"},
1579 {"TX SMIC MUX6", "SWR_DMIC0", "TX SWR_DMIC0"},
1580 {"TX SMIC MUX6", "SWR_DMIC1", "TX SWR_DMIC1"},
1581 {"TX SMIC MUX6", "SWR_DMIC2", "TX SWR_DMIC2"},
1582 {"TX SMIC MUX6", "SWR_DMIC3", "TX SWR_DMIC3"},
1583 {"TX SMIC MUX6", "SWR_DMIC4", "TX SWR_DMIC4"},
1584 {"TX SMIC MUX6", "SWR_DMIC5", "TX SWR_DMIC5"},
1585 {"TX SMIC MUX6", "SWR_DMIC6", "TX SWR_DMIC6"},
1586 {"TX SMIC MUX6", "SWR_DMIC7", "TX SWR_DMIC7"},
1587
1588 {"TX DEC7 MUX", "SWR_MIC", "TX SMIC MUX7"},
1589 {"TX SMIC MUX7", NULL, "TX_SWR_CLK"},
1590 {"TX SMIC MUX7", "ADC0", "TX SWR_ADC0"},
1591 {"TX SMIC MUX7", "ADC1", "TX SWR_ADC1"},
1592 {"TX SMIC MUX7", "ADC2", "TX SWR_ADC2"},
1593 {"TX SMIC MUX7", "ADC3", "TX SWR_ADC3"},
1594 {"TX SMIC MUX7", "SWR_DMIC0", "TX SWR_DMIC0"},
1595 {"TX SMIC MUX7", "SWR_DMIC1", "TX SWR_DMIC1"},
1596 {"TX SMIC MUX7", "SWR_DMIC2", "TX SWR_DMIC2"},
1597 {"TX SMIC MUX7", "SWR_DMIC3", "TX SWR_DMIC3"},
1598 {"TX SMIC MUX7", "SWR_DMIC4", "TX SWR_DMIC4"},
1599 {"TX SMIC MUX7", "SWR_DMIC5", "TX SWR_DMIC5"},
1600 {"TX SMIC MUX7", "SWR_DMIC6", "TX SWR_DMIC6"},
1601 {"TX SMIC MUX7", "SWR_DMIC7", "TX SWR_DMIC7"},
1602};
1603
c39667dd
SK		 1604static const struct snd_kcontrol_new tx_macro_snd_controls[] = {
1605 SOC_SINGLE_S8_TLV("TX_DEC0 Volume",
1606 CDC_TX0_TX_VOL_CTL,
1607 -84, 40, digital_gain),
1608 SOC_SINGLE_S8_TLV("TX_DEC1 Volume",
1609 CDC_TX1_TX_VOL_CTL,
1610 -84, 40, digital_gain),
1611 SOC_SINGLE_S8_TLV("TX_DEC2 Volume",
1612 CDC_TX2_TX_VOL_CTL,
1613 -84, 40, digital_gain),
1614 SOC_SINGLE_S8_TLV("TX_DEC3 Volume",
1615 CDC_TX3_TX_VOL_CTL,
1616 -84, 40, digital_gain),
1617 SOC_SINGLE_S8_TLV("TX_DEC4 Volume",
1618 CDC_TX4_TX_VOL_CTL,
1619 -84, 40, digital_gain),
1620 SOC_SINGLE_S8_TLV("TX_DEC5 Volume",
1621 CDC_TX5_TX_VOL_CTL,
1622 -84, 40, digital_gain),
1623 SOC_SINGLE_S8_TLV("TX_DEC6 Volume",
1624 CDC_TX6_TX_VOL_CTL,
1625 -84, 40, digital_gain),
1626 SOC_SINGLE_S8_TLV("TX_DEC7 Volume",
1627 CDC_TX7_TX_VOL_CTL,
1628 -84, 40, digital_gain),
1629
1630 SOC_ENUM_EXT("DEC0 MODE", dec_mode_mux_enum[0],
1631 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1632
1633 SOC_ENUM_EXT("DEC1 MODE", dec_mode_mux_enum[1],
1634 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1635
1636 SOC_ENUM_EXT("DEC2 MODE", dec_mode_mux_enum[2],
1637 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1638
1639 SOC_ENUM_EXT("DEC3 MODE", dec_mode_mux_enum[3],
1640 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1641
1642 SOC_ENUM_EXT("DEC4 MODE", dec_mode_mux_enum[4],
1643 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1644
1645 SOC_ENUM_EXT("DEC5 MODE", dec_mode_mux_enum[5],
1646 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1647
1648 SOC_ENUM_EXT("DEC6 MODE", dec_mode_mux_enum[6],
1649 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1650
1651 SOC_ENUM_EXT("DEC7 MODE", dec_mode_mux_enum[7],
1652 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1653
1654 SOC_SINGLE_EXT("DEC0_BCS Switch", SND_SOC_NOPM, 0, 1, 0,
1655 tx_macro_get_bcs, tx_macro_set_bcs),
1656};
1657
1658static int tx_macro_component_probe(struct snd_soc_component *comp)
1659{
1660 struct tx_macro *tx = snd_soc_component_get_drvdata(comp);
1661 int i;
1662
1663 snd_soc_component_init_regmap(comp, tx->regmap);
1664
1665 for (i = 0; i < NUM_DECIMATORS; i++) {
1666 tx->tx_hpf_work[i].tx = tx;
1667 tx->tx_hpf_work[i].decimator = i;
1668 INIT_DELAYED_WORK(&tx->tx_hpf_work[i].dwork,
1669 tx_macro_tx_hpf_corner_freq_callback);
1670 }
1671
1672 for (i = 0; i < NUM_DECIMATORS; i++) {
1673 tx->tx_mute_dwork[i].tx = tx;
1674 tx->tx_mute_dwork[i].decimator = i;
1675 INIT_DELAYED_WORK(&tx->tx_mute_dwork[i].dwork,
1676 tx_macro_mute_update_callback);
1677 }
1678 tx->component = comp;
1679
1680 snd_soc_component_update_bits(comp, CDC_TX0_TX_PATH_SEC7, 0x3F,
1681 0x0A);
864b9b58
SRM		 1682 /* Enable swr mic0 and mic1 clock */
1683 snd_soc_component_update_bits(comp, CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 0xFF, 0x00);
1684 snd_soc_component_update_bits(comp, CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 0xFF, 0x00);
c39667dd
SK		 1685
1686 return 0;
1687}
1688
1689static int swclk_gate_enable(struct clk_hw *hw)
1690{
1691 struct tx_macro *tx = to_tx_macro(hw);
1692 struct regmap *regmap = tx->regmap;
1693
1694 tx_macro_mclk_enable(tx, true);
1695 if (tx->reset_swr)
1696 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
1697 CDC_TX_SWR_RESET_MASK,
1698 CDC_TX_SWR_RESET_ENABLE);
1699
1700 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
1701 CDC_TX_SWR_CLK_EN_MASK,
1702 CDC_TX_SWR_CLK_ENABLE);
1703 if (tx->reset_swr)
1704 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
1705 CDC_TX_SWR_RESET_MASK, 0x0);
1706 tx->reset_swr = false;
1707
1708 return 0;
1709}
1710
1711static void swclk_gate_disable(struct clk_hw *hw)
1712{
1713 struct tx_macro *tx = to_tx_macro(hw);
1714 struct regmap *regmap = tx->regmap;
1715
1716 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
1717 CDC_TX_SWR_CLK_EN_MASK, 0x0);
1718
1719 tx_macro_mclk_enable(tx, false);
1720}
1721
1722static int swclk_gate_is_enabled(struct clk_hw *hw)
1723{
1724 struct tx_macro *tx = to_tx_macro(hw);
1725 int ret, val;
1726
1727 regmap_read(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, &val);
1728 ret = val & BIT(0);
1729
1730 return ret;
1731}
1732
1733static unsigned long swclk_recalc_rate(struct clk_hw *hw,
1734 unsigned long parent_rate)
1735{
1736 return parent_rate / 2;
1737}
1738
1739static const struct clk_ops swclk_gate_ops = {
1740 .prepare = swclk_gate_enable,
1741 .unprepare = swclk_gate_disable,
1742 .is_enabled = swclk_gate_is_enabled,
1743 .recalc_rate = swclk_recalc_rate,
1744
1745};
1746
db8665a3 1747static int tx_macro_register_mclk_output(struct tx_macro *tx)
c39667dd
SK		 1748{
1749 struct device *dev = tx->dev;
c39667dd
SK		 1750 const char *parent_clk_name = NULL;
1751 const char *clk_name = "lpass-tx-mclk";
1752 struct clk_hw *hw;
1753 struct clk_init_data init;
1754 int ret;
1755
512864c4 1756 parent_clk_name = __clk_get_name(tx->mclk);
c39667dd
SK		 1757
1758 init.name = clk_name;
1759 init.ops = &swclk_gate_ops;
1760 init.flags = 0;
1761 init.parent_names = &parent_clk_name;
1762 init.num_parents = 1;
1763 tx->hw.init = &init;
1764 hw = &tx->hw;
db8665a3 1765 ret = devm_clk_hw_register(dev, hw);
c39667dd 1766 if (ret)
db8665a3 1767 return ret;
c39667dd 1768
db8665a3 1769 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
c39667dd
SK		 1770}
1771
1772static const struct snd_soc_component_driver tx_macro_component_drv = {
1773 .name = "RX-MACRO",
1774 .probe = tx_macro_component_probe,
1775 .controls = tx_macro_snd_controls,
1776 .num_controls = ARRAY_SIZE(tx_macro_snd_controls),
d207bdea
SK		 1777 .dapm_widgets = tx_macro_dapm_widgets,
1778 .num_dapm_widgets = ARRAY_SIZE(tx_macro_dapm_widgets),
1779 .dapm_routes = tx_audio_map,
1780 .num_dapm_routes = ARRAY_SIZE(tx_audio_map),
c39667dd
SK		 1781};
1782
1783static int tx_macro_probe(struct platform_device *pdev)
1784{
1785 struct device *dev = &pdev->dev;
7b285c74 1786 struct device_node *np = dev->of_node;
c39667dd
SK		 1787 struct tx_macro *tx;
1788 void __iomem *base;
7b285c74 1789 int ret, reg;
c39667dd
SK		 1790
1791 tx = devm_kzalloc(dev, sizeof(*tx), GFP_KERNEL);
1792 if (!tx)
1793 return -ENOMEM;
1794
512864c4
SK		 1795 tx->macro = devm_clk_get_optional(dev, "macro");
1796 if (IS_ERR(tx->macro))
1797 return PTR_ERR(tx->macro);
c39667dd 1798
512864c4
SK		 1799 tx->dcodec = devm_clk_get_optional(dev, "dcodec");
1800 if (IS_ERR(tx->dcodec))
1801 return PTR_ERR(tx->dcodec);
1802
1803 tx->mclk = devm_clk_get(dev, "mclk");
1804 if (IS_ERR(tx->mclk))
1805 return PTR_ERR(tx->mclk);
1806
1807 tx->npl = devm_clk_get(dev, "npl");
1808 if (IS_ERR(tx->npl))
1809 return PTR_ERR(tx->npl);
1810
1811 tx->fsgen = devm_clk_get(dev, "fsgen");
1812 if (IS_ERR(tx->fsgen))
1813 return PTR_ERR(tx->fsgen);
c39667dd
SK		 1814
1815 base = devm_platform_ioremap_resource(pdev, 0);
1816 if (IS_ERR(base))
1817 return PTR_ERR(base);
1818
7b285c74
SRM		 1819 /* Update defaults for lpass sc7280 */
1820 if (of_device_is_compatible(np, "qcom,sc7280-lpass-tx-macro")) {
1821 for (reg = 0; reg < ARRAY_SIZE(tx_defaults); reg++) {
1822 switch (tx_defaults[reg].reg) {
1823 case CDC_TX_TOP_CSR_SWR_AMIC0_CTL:
1824 case CDC_TX_TOP_CSR_SWR_AMIC1_CTL:
1825 tx_defaults[reg].def = 0x0E;
1826 break;
1827 default:
1828 break;
1829 }
1830 }
1831 }
1832
c39667dd 1833 tx->regmap = devm_regmap_init_mmio(dev, base, &tx_regmap_config);
aa505ecc
JJ		 1834 if (IS_ERR(tx->regmap))
1835 return PTR_ERR(tx->regmap);
c39667dd
SK		 1836
1837 dev_set_drvdata(dev, tx);
1838
1839 tx->reset_swr = true;
1840 tx->dev = dev;
1841
1842 /* set MCLK and NPL rates */
512864c4
SK		 1843 clk_set_rate(tx->mclk, MCLK_FREQ);
1844 clk_set_rate(tx->npl, 2 * MCLK_FREQ);
c39667dd 1845
512864c4 1846 ret = clk_prepare_enable(tx->macro);
c39667dd 1847 if (ret)
512864c4
SK		 1848 goto err;
1849
1850 ret = clk_prepare_enable(tx->dcodec);
1851 if (ret)
1852 goto err_dcodec;
1853
1854 ret = clk_prepare_enable(tx->mclk);
1855 if (ret)
1856 goto err_mclk;
1857
1858 ret = clk_prepare_enable(tx->npl);
1859 if (ret)
1860 goto err_npl;
1861
1862 ret = clk_prepare_enable(tx->fsgen);
1863 if (ret)
1864 goto err_fsgen;
c39667dd 1865
db8665a3
SK		 1866 ret = tx_macro_register_mclk_output(tx);
1867 if (ret)
512864c4 1868 goto err_clkout;
c39667dd
SK		 1869
1870 ret = devm_snd_soc_register_component(dev, &tx_macro_component_drv,
1871 tx_macro_dai,
1872 ARRAY_SIZE(tx_macro_dai));
1873 if (ret)
512864c4 1874 goto err_clkout;
c39667dd 1875
512864c4
SK		 1876 return 0;
1877
1878err_clkout:
1879 clk_disable_unprepare(tx->fsgen);
1880err_fsgen:
1881 clk_disable_unprepare(tx->npl);
1882err_npl:
1883 clk_disable_unprepare(tx->mclk);
1884err_mclk:
1885 clk_disable_unprepare(tx->dcodec);
1886err_dcodec:
1887 clk_disable_unprepare(tx->macro);
1888err:
c39667dd
SK		 1889 return ret;
1890}
1891
1892static int tx_macro_remove(struct platform_device *pdev)
1893{
1894 struct tx_macro *tx = dev_get_drvdata(&pdev->dev);
1895
512864c4
SK		 1896 clk_disable_unprepare(tx->macro);
1897 clk_disable_unprepare(tx->dcodec);
1898 clk_disable_unprepare(tx->mclk);
1899 clk_disable_unprepare(tx->npl);
1900 clk_disable_unprepare(tx->fsgen);
c39667dd
SK		 1901
1902 return 0;
1903}
1904
1905static const struct of_device_id tx_macro_dt_match[] = {
9d8c6981 1906 { .compatible = "qcom,sc7280-lpass-tx-macro" },
c39667dd
SK		 1907 { .compatible = "qcom,sm8250-lpass-tx-macro" },
1908 { }
1909};
14c0c423 1910MODULE_DEVICE_TABLE(of, tx_macro_dt_match);
c39667dd
SK		 1911static struct platform_driver tx_macro_driver = {
1912 .driver = {
1913 .name = "tx_macro",
1914 .of_match_table = tx_macro_dt_match,
1915 .suppress_bind_attrs = true,
1916 },
1917 .probe = tx_macro_probe,
1918 .remove = tx_macro_remove,
1919};
1920
1921module_platform_driver(tx_macro_driver);
1922
1923MODULE_DESCRIPTION("TX macro driver");
1924MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)