projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 567e4f98 SC |
1 | /* |
| 2 | * es8328.h -- ES8328 ALSA SoC Audio driver | |
| 3 | */ | |
| 4 | ||
| 5 | #ifndef _ES8328_H | |
| 6 | #define _ES8328_H | |
| 7 | ||
| 8 | #include <linux/regmap.h> | |
| 9 | ||
| 10 | struct device; | |
| 11 | ||
| 12 | extern const struct regmap_config es8328_regmap_config; | |
| 13 | int es8328_probe(struct device *dev, struct regmap *regmap); | |
| 14 | ||
| 15 | #define ES8328_DACLVOL 46 | |
| 16 | #define ES8328_DACRVOL 47 | |
| 17 | #define ES8328_DACCTL 28 | |
| 18 | #define ES8328_RATEMASK (0x1f << 0) | |
| 19 | ||
| 20 | #define ES8328_CONTROL1 0x00 | |
| 21 | #define ES8328_CONTROL1_VMIDSEL_OFF (0 << 0) | |
| 22 | #define ES8328_CONTROL1_VMIDSEL_50k (1 << 0) | |
| 23 | #define ES8328_CONTROL1_VMIDSEL_500k (2 << 0) | |
| 24 | #define ES8328_CONTROL1_VMIDSEL_5k (3 << 0) | |
| 25 | #define ES8328_CONTROL1_VMIDSEL_MASK (7 << 0) | |
| 26 | #define ES8328_CONTROL1_ENREF (1 << 2) | |
| 27 | #define ES8328_CONTROL1_SEQEN (1 << 3) | |
| 28 | #define ES8328_CONTROL1_SAMEFS (1 << 4) | |
| 29 | #define ES8328_CONTROL1_DACMCLK_ADC (0 << 5) | |
| 30 | #define ES8328_CONTROL1_DACMCLK_DAC (1 << 5) | |
| 31 | #define ES8328_CONTROL1_LRCM (1 << 6) | |
| 32 | #define ES8328_CONTROL1_SCP_RESET (1 << 7) | |
| 33 | ||
| 34 | #define ES8328_CONTROL2 0x01 | |
| 35 | #define ES8328_CONTROL2_VREF_BUF_OFF (1 << 0) | |
| 36 | #define ES8328_CONTROL2_VREF_LOWPOWER (1 << 1) | |
| 37 | #define ES8328_CONTROL2_IBIASGEN_OFF (1 << 2) | |
| 38 | #define ES8328_CONTROL2_ANALOG_OFF (1 << 3) | |
| 39 | #define ES8328_CONTROL2_VREF_BUF_LOWPOWER (1 << 4) | |
| 40 | #define ES8328_CONTROL2_VCM_MOD_LOWPOWER (1 << 5) | |
| 41 | #define ES8328_CONTROL2_OVERCURRENT_ON (1 << 6) | |
| 42 | #define ES8328_CONTROL2_THERMAL_SHUTDOWN_ON (1 << 7) | |
| 43 | ||
| 44 | #define ES8328_CHIPPOWER 0x02 | |
| 45 | #define ES8328_CHIPPOWER_DACVREF_OFF 0 | |
| 46 | #define ES8328_CHIPPOWER_ADCVREF_OFF 1 | |
| 47 | #define ES8328_CHIPPOWER_DACDLL_OFF 2 | |
| 48 | #define ES8328_CHIPPOWER_ADCDLL_OFF 3 | |
| 49 | #define ES8328_CHIPPOWER_DACSTM_RESET 4 | |
| 50 | #define ES8328_CHIPPOWER_ADCSTM_RESET 5 | |
| 51 | #define ES8328_CHIPPOWER_DACDIG_OFF 6 | |
| 52 | #define ES8328_CHIPPOWER_ADCDIG_OFF 7 | |
| 53 | ||
| 54 | #define ES8328_ADCPOWER 0x03 | |
| 55 | #define ES8328_ADCPOWER_INT1_LOWPOWER 0 | |
| 56 | #define ES8328_ADCPOWER_FLASH_ADC_LOWPOWER 1 | |
| 57 | #define ES8328_ADCPOWER_ADC_BIAS_GEN_OFF 2 | |
| 58 | #define ES8328_ADCPOWER_MIC_BIAS_OFF 3 | |
| 59 | #define ES8328_ADCPOWER_ADCR_OFF 4 | |
| 60 | #define ES8328_ADCPOWER_ADCL_OFF 5 | |
| 61 | #define ES8328_ADCPOWER_AINR_OFF 6 | |
| 62 | #define ES8328_ADCPOWER_AINL_OFF 7 | |
| 63 | ||
| 64 | #define ES8328_DACPOWER 0x04 | |
| 65 | #define ES8328_DACPOWER_OUT3_ON 0 | |
| 66 | #define ES8328_DACPOWER_MONO_ON 1 | |
| 67 | #define ES8328_DACPOWER_ROUT2_ON 2 | |
| 68 | #define ES8328_DACPOWER_LOUT2_ON 3 | |
| 69 | #define ES8328_DACPOWER_ROUT1_ON 4 | |
| 70 | #define ES8328_DACPOWER_LOUT1_ON 5 | |
| 71 | #define ES8328_DACPOWER_RDAC_OFF 6 | |
| 72 | #define ES8328_DACPOWER_LDAC_OFF 7 | |
| 73 | ||
| 74 | #define ES8328_CHIPLOPOW1 0x05 | |
| 75 | #define ES8328_CHIPLOPOW2 0x06 | |
| 76 | #define ES8328_ANAVOLMANAG 0x07 | |
| 77 | ||
| 78 | #define ES8328_MASTERMODE 0x08 | |
| 79 | #define ES8328_MASTERMODE_BCLKDIV (0 << 0) | |
| 80 | #define ES8328_MASTERMODE_BCLK_INV (1 << 5) | |
| 81 | #define ES8328_MASTERMODE_MCLKDIV2 (1 << 6) | |
| 82 | #define ES8328_MASTERMODE_MSC (1 << 7) | |
| 83 | ||
| 84 | #define ES8328_ADCCONTROL1 0x09 | |
| 85 | #define ES8328_ADCCONTROL2 0x0a | |
| 86 | #define ES8328_ADCCONTROL3 0x0b | |
| 87 | #define ES8328_ADCCONTROL4 0x0c | |
| 88 | #define ES8328_ADCCONTROL5 0x0d | |
| 89 | #define ES8328_ADCCONTROL5_RATEMASK (0x1f << 0) | |
| 90 | ||
| 91 | #define ES8328_ADCCONTROL6 0x0e | |
| 92 | ||
| 93 | #define ES8328_ADCCONTROL7 0x0f | |
| 94 | #define ES8328_ADCCONTROL7_ADC_MUTE (1 << 2) | |
| 95 | #define ES8328_ADCCONTROL7_ADC_LER (1 << 3) | |
| 96 | #define ES8328_ADCCONTROL7_ADC_ZERO_CROSS (1 << 4) | |
| 97 | #define ES8328_ADCCONTROL7_ADC_SOFT_RAMP (1 << 5) | |
| 98 | #define ES8328_ADCCONTROL7_ADC_RAMP_RATE_4 (0 << 6) | |
| 99 | #define ES8328_ADCCONTROL7_ADC_RAMP_RATE_8 (1 << 6) | |
| 100 | #define ES8328_ADCCONTROL7_ADC_RAMP_RATE_16 (2 << 6) | |
| 101 | #define ES8328_ADCCONTROL7_ADC_RAMP_RATE_32 (3 << 6) | |
| 102 | ||
| 103 | #define ES8328_ADCCONTROL8 0x10 | |
| 104 | #define ES8328_ADCCONTROL9 0x11 | |
| 105 | #define ES8328_ADCCONTROL10 0x12 | |
| 106 | #define ES8328_ADCCONTROL11 0x13 | |
| 107 | #define ES8328_ADCCONTROL12 0x14 | |
| 108 | #define ES8328_ADCCONTROL13 0x15 | |
| 109 | #define ES8328_ADCCONTROL14 0x16 | |
| 110 | ||
| 111 | #define ES8328_DACCONTROL1 0x17 | |
| 112 | #define ES8328_DACCONTROL1_DACFORMAT_I2S (0 << 1) | |
| 113 | #define ES8328_DACCONTROL1_DACFORMAT_LJUST (1 << 1) | |
| 114 | #define ES8328_DACCONTROL1_DACFORMAT_RJUST (2 << 1) | |
| 115 | #define ES8328_DACCONTROL1_DACFORMAT_PCM (3 << 1) | |
| 116 | #define ES8328_DACCONTROL1_DACWL_24 (0 << 3) | |
| 117 | #define ES8328_DACCONTROL1_DACWL_20 (1 << 3) | |
| 118 | #define ES8328_DACCONTROL1_DACWL_18 (2 << 3) | |
| 119 | #define ES8328_DACCONTROL1_DACWL_16 (3 << 3) | |
| 120 | #define ES8328_DACCONTROL1_DACWL_32 (4 << 3) | |
| 121 | #define ES8328_DACCONTROL1_DACLRP_I2S_POL_NORMAL (0 << 6) | |
| 122 | #define ES8328_DACCONTROL1_DACLRP_I2S_POL_INV (1 << 6) | |
| 123 | #define ES8328_DACCONTROL1_DACLRP_PCM_MSB_CLK2 (0 << 6) | |
| 124 | #define ES8328_DACCONTROL1_DACLRP_PCM_MSB_CLK1 (1 << 6) | |
| 125 | #define ES8328_DACCONTROL1_LRSWAP (1 << 7) | |
| 126 | ||
| 127 | #define ES8328_DACCONTROL2 0x18 | |
| 128 | #define ES8328_DACCONTROL2_RATEMASK (0x1f << 0) | |
| 129 | #define ES8328_DACCONTROL2_DOUBLESPEED (1 << 5) | |
| 130 | ||
| 131 | #define ES8328_DACCONTROL3 0x19 | |
| 132 | #define ES8328_DACCONTROL3_AUTOMUTE (1 << 2) | |
| 133 | #define ES8328_DACCONTROL3_DACMUTE (1 << 2) | |
| 134 | #define ES8328_DACCONTROL3_LEFTGAINVOL (1 << 3) | |
| 135 | #define ES8328_DACCONTROL3_DACZEROCROSS (1 << 4) | |
| 136 | #define ES8328_DACCONTROL3_DACSOFTRAMP (1 << 5) | |
| 137 | #define ES8328_DACCONTROL3_DACRAMPRATE (3 << 6) | |
| 138 | ||
| 139 | #define ES8328_LDACVOL 0x1a | |
| 140 | #define ES8328_LDACVOL_MASK (0 << 0) | |
| 141 | #define ES8328_LDACVOL_MAX (0xc0) | |
| 142 | ||
| 143 | #define ES8328_RDACVOL 0x1b | |
| 144 | #define ES8328_RDACVOL_MASK (0 << 0) | |
| 145 | #define ES8328_RDACVOL_MAX (0xc0) | |
| 146 | ||
| 147 | #define ES8328_DACVOL_MAX (0xc0) | |
| 148 | ||
| 149 | #define ES8328_DACCONTROL4 0x1a | |
| 150 | #define ES8328_DACCONTROL5 0x1b | |
| 151 | ||
| 152 | #define ES8328_DACCONTROL6 0x1c | |
| 153 | #define ES8328_DACCONTROL6_CLICKFREE (1 << 3) | |
| 154 | #define ES8328_DACCONTROL6_DAC_INVR (1 << 4) | |
| 155 | #define ES8328_DACCONTROL6_DAC_INVL (1 << 5) | |
| 156 | #define ES8328_DACCONTROL6_DEEMPH_OFF (0 << 6) | |
| 157 | #define ES8328_DACCONTROL6_DEEMPH_32k (1 << 6) | |
| 158 | #define ES8328_DACCONTROL6_DEEMPH_44_1k (2 << 6) | |
| 159 | #define ES8328_DACCONTROL6_DEEMPH_48k (3 << 6) | |
| 160 | ||
| 161 | #define ES8328_DACCONTROL7 0x1d | |
| 162 | #define ES8328_DACCONTROL7_VPP_SCALE_3p5 (0 << 0) | |
| 163 | #define ES8328_DACCONTROL7_VPP_SCALE_4p0 (1 << 0) | |
| 164 | #define ES8328_DACCONTROL7_VPP_SCALE_3p0 (2 << 0) | |
| 165 | #define ES8328_DACCONTROL7_VPP_SCALE_2p5 (3 << 0) | |
| 166 | #define ES8328_DACCONTROL7_SHELVING_STRENGTH (1 << 2) /* In eights */ | |
| 167 | #define ES8328_DACCONTROL7_MONO (1 << 5) | |
| 168 | #define ES8328_DACCONTROL7_ZEROR (1 << 6) | |
| 169 | #define ES8328_DACCONTROL7_ZEROL (1 << 7) | |
| 170 | ||
| 171 | /* Shelving filter */ | |
| 172 | #define ES8328_DACCONTROL8 0x1e | |
| 173 | #define ES8328_DACCONTROL9 0x1f | |
| 174 | #define ES8328_DACCONTROL10 0x20 | |
| 175 | #define ES8328_DACCONTROL11 0x21 | |
| 176 | #define ES8328_DACCONTROL12 0x22 | |
| 177 | #define ES8328_DACCONTROL13 0x23 | |
| 178 | #define ES8328_DACCONTROL14 0x24 | |
| 179 | #define ES8328_DACCONTROL15 0x25 | |
| 180 | ||
| 181 | #define ES8328_DACCONTROL16 0x26 | |
| 182 | #define ES8328_DACCONTROL16_RMIXSEL_RIN1 (0 << 0) | |
| 183 | #define ES8328_DACCONTROL16_RMIXSEL_RIN2 (1 << 0) | |
| 184 | #define ES8328_DACCONTROL16_RMIXSEL_RIN3 (2 << 0) | |
| 185 | #define ES8328_DACCONTROL16_RMIXSEL_RADC (3 << 0) | |
| 186 | #define ES8328_DACCONTROL16_LMIXSEL_LIN1 (0 << 3) | |
| 187 | #define ES8328_DACCONTROL16_LMIXSEL_LIN2 (1 << 3) | |
| 188 | #define ES8328_DACCONTROL16_LMIXSEL_LIN3 (2 << 3) | |
| 189 | #define ES8328_DACCONTROL16_LMIXSEL_LADC (3 << 3) | |
| 190 | ||
| 191 | #define ES8328_DACCONTROL17 0x27 | |
| 192 | #define ES8328_DACCONTROL17_LI2LOVOL (7 << 3) | |
| 193 | #define ES8328_DACCONTROL17_LI2LO (1 << 6) | |
| 194 | #define ES8328_DACCONTROL17_LD2LO (1 << 7) | |
| 195 | ||
| 196 | #define ES8328_DACCONTROL18 0x28 | |
| 197 | #define ES8328_DACCONTROL18_RI2LOVOL (7 << 3) | |
| 198 | #define ES8328_DACCONTROL18_RI2LO (1 << 6) | |
| 199 | #define ES8328_DACCONTROL18_RD2LO (1 << 7) | |
| 200 | ||
| 201 | #define ES8328_DACCONTROL19 0x29 | |
| 202 | #define ES8328_DACCONTROL19_LI2ROVOL (7 << 3) | |
| 203 | #define ES8328_DACCONTROL19_LI2RO (1 << 6) | |
| 204 | #define ES8328_DACCONTROL19_LD2RO (1 << 7) | |
| 205 | ||
| 206 | #define ES8328_DACCONTROL20 0x2a | |
| 207 | #define ES8328_DACCONTROL20_RI2ROVOL (7 << 3) | |
| 208 | #define ES8328_DACCONTROL20_RI2RO (1 << 6) | |
| 209 | #define ES8328_DACCONTROL20_RD2RO (1 << 7) | |
| 210 | ||
| 211 | #define ES8328_DACCONTROL21 0x2b | |
| 212 | #define ES8328_DACCONTROL21_LI2MOVOL (7 << 3) | |
| 213 | #define ES8328_DACCONTROL21_LI2MO (1 << 6) | |
| 214 | #define ES8328_DACCONTROL21_LD2MO (1 << 7) | |
| 215 | ||
| 216 | #define ES8328_DACCONTROL22 0x2c | |
| 217 | #define ES8328_DACCONTROL22_RI2MOVOL (7 << 3) | |
| 218 | #define ES8328_DACCONTROL22_RI2MO (1 << 6) | |
| 219 | #define ES8328_DACCONTROL22_RD2MO (1 << 7) | |
| 220 | ||
| 221 | #define ES8328_DACCONTROL23 0x2d | |
| 222 | #define ES8328_DACCONTROL23_MOUTINV (1 << 1) | |
| 223 | #define ES8328_DACCONTROL23_HPSWPOL (1 << 2) | |
| 224 | #define ES8328_DACCONTROL23_HPSWEN (1 << 3) | |
| 225 | #define ES8328_DACCONTROL23_VROI_1p5k (0 << 4) | |
| 226 | #define ES8328_DACCONTROL23_VROI_40k (1 << 4) | |
| 227 | #define ES8328_DACCONTROL23_OUT3_VREF (0 << 5) | |
| 228 | #define ES8328_DACCONTROL23_OUT3_ROUT1 (1 << 5) | |
| 229 | #define ES8328_DACCONTROL23_OUT3_MONOOUT (2 << 5) | |
| 230 | #define ES8328_DACCONTROL23_OUT3_RIGHT_MIXER (3 << 5) | |
| 231 | #define ES8328_DACCONTROL23_ROUT2INV (1 << 7) | |
| 232 | ||
| 233 | /* LOUT1 Amplifier */ | |
| 234 | #define ES8328_LOUT1VOL 0x2e | |
| 235 | #define ES8328_LOUT1VOL_MASK (0 << 5) | |
| 236 | #define ES8328_LOUT1VOL_MAX (0x24) | |
| 237 | ||
| 238 | /* ROUT1 Amplifier */ | |
| 239 | #define ES8328_ROUT1VOL 0x2f | |
| 240 | #define ES8328_ROUT1VOL_MASK (0 << 5) | |
| 241 | #define ES8328_ROUT1VOL_MAX (0x24) | |
| 242 | ||
| 243 | #define ES8328_OUT1VOL_MAX (0x24) | |
| 244 | ||
| 245 | /* LOUT2 Amplifier */ | |
| 246 | #define ES8328_LOUT2VOL 0x30 | |
| 247 | #define ES8328_LOUT2VOL_MASK (0 << 5) | |
| 248 | #define ES8328_LOUT2VOL_MAX (0x24) | |
| 249 | ||
| 250 | /* ROUT2 Amplifier */ | |
| 251 | #define ES8328_ROUT2VOL 0x31 | |
| 252 | #define ES8328_ROUT2VOL_MASK (0 << 5) | |
| 253 | #define ES8328_ROUT2VOL_MAX (0x24) | |
| 254 | ||
| 255 | #define ES8328_OUT2VOL_MAX (0x24) | |
| 256 | ||
| 257 | /* Mono Out Amplifier */ | |
| 258 | #define ES8328_MONOOUTVOL 0x32 | |
| 259 | #define ES8328_MONOOUTVOL_MASK (0 << 5) | |
| 260 | #define ES8328_MONOOUTVOL_MAX (0x24) | |
| 261 | ||
| 262 | #define ES8328_DACCONTROL29 0x33 | |
| 263 | #define ES8328_DACCONTROL30 0x34 | |
| 264 | ||
| 265 | #define ES8328_SYSCLK 0 | |
| 266 | ||
| 267 | #define ES8328_REG_MAX 0x35 | |
| 268 | ||
| 269 | #define ES8328_PLL1 0 | |
| 270 | #define ES8328_PLL2 1 | |
| 271 | ||
| 272 | /* clock inputs */ | |
| 273 | #define ES8328_MCLK 0 | |
| 274 | #define ES8328_PCMCLK 1 | |
| 275 | ||
| 276 | /* clock divider id's */ | |
| 277 | #define ES8328_PCMDIV 0 | |
| 278 | #define ES8328_BCLKDIV 1 | |
| 279 | #define ES8328_VXCLKDIV 2 | |
| 280 | ||
| 281 | /* PCM clock dividers */ | |
| 282 | #define ES8328_PCM_DIV_1 (0 << 6) | |
| 283 | #define ES8328_PCM_DIV_3 (2 << 6) | |
| 284 | #define ES8328_PCM_DIV_5_5 (3 << 6) | |
| 285 | #define ES8328_PCM_DIV_2 (4 << 6) | |
| 286 | #define ES8328_PCM_DIV_4 (5 << 6) | |
| 287 | #define ES8328_PCM_DIV_6 (6 << 6) | |
| 288 | #define ES8328_PCM_DIV_8 (7 << 6) | |
| 289 | ||
| 290 | /* BCLK clock dividers */ | |
| 291 | #define ES8328_BCLK_DIV_1 (0 << 7) | |
| 292 | #define ES8328_BCLK_DIV_2 (1 << 7) | |
| 293 | #define ES8328_BCLK_DIV_4 (2 << 7) | |
| 294 | #define ES8328_BCLK_DIV_8 (3 << 7) | |
| 295 | ||
| 296 | /* VXCLK clock dividers */ | |
| 297 | #define ES8328_VXCLK_DIV_1 (0 << 6) | |
| 298 | #define ES8328_VXCLK_DIV_2 (1 << 6) | |
| 299 | #define ES8328_VXCLK_DIV_4 (2 << 6) | |
| 300 | #define ES8328_VXCLK_DIV_8 (3 << 6) | |
| 301 | #define ES8328_VXCLK_DIV_16 (4 << 6) | |
| 302 | ||
| 303 | #define ES8328_DAI_HIFI 0 | |
| 304 | #define ES8328_DAI_VOICE 1 | |
| 305 | ||
| 306 | #define ES8328_1536FS 1536 | |
| 307 | #define ES8328_1024FS 1024 | |
| 308 | #define ES8328_768FS 768 | |
| 309 | #define ES8328_512FS 512 | |
| 310 | #define ES8328_384FS 384 | |
| 311 | #define ES8328_256FS 256 | |
| 312 | #define ES8328_128FS 128 | |
| 313 | ||
| 314 | #endif |