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567e4f98 SC |
1 | /* |
2 | * es8328.c -- ES8328 ALSA SoC Audio driver | |
3 | * | |
4 | * Copyright 2014 Sutajio Ko-Usagi PTE LTD | |
5 | * | |
6 | * Author: Sean Cross <xobs@kosagi.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/clk.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/of_device.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/pm.h> | |
18 | #include <linux/regmap.h> | |
19 | #include <linux/slab.h> | |
20 | #include <linux/regulator/consumer.h> | |
21 | #include <sound/core.h> | |
22 | #include <sound/initval.h> | |
23 | #include <sound/pcm.h> | |
24 | #include <sound/pcm_params.h> | |
25 | #include <sound/soc.h> | |
26 | #include <sound/tlv.h> | |
27 | #include "es8328.h" | |
28 | ||
29 | #define ES8328_SYSCLK_RATE_1X 11289600 | |
30 | #define ES8328_SYSCLK_RATE_2X 22579200 | |
31 | ||
32 | /* Run the codec at 22.5792 or 11.2896 MHz to support these rates */ | |
33 | static struct { | |
34 | int rate; | |
35 | u8 ratio; | |
36 | } mclk_ratios[] = { | |
37 | { 8000, 9 }, | |
38 | {11025, 7 }, | |
39 | {22050, 4 }, | |
40 | {44100, 2 }, | |
41 | }; | |
42 | ||
43 | /* regulator supplies for sgtl5000, VDDD is an optional external supply */ | |
44 | enum sgtl5000_regulator_supplies { | |
45 | DVDD, | |
46 | AVDD, | |
47 | PVDD, | |
48 | HPVDD, | |
49 | ES8328_SUPPLY_NUM | |
50 | }; | |
51 | ||
52 | /* vddd is optional supply */ | |
53 | static const char * const supply_names[ES8328_SUPPLY_NUM] = { | |
54 | "DVDD", | |
55 | "AVDD", | |
56 | "PVDD", | |
57 | "HPVDD", | |
58 | }; | |
59 | ||
60 | #define ES8328_RATES (SNDRV_PCM_RATE_44100 | \ | |
61 | SNDRV_PCM_RATE_22050 | \ | |
62 | SNDRV_PCM_RATE_11025) | |
63 | #define ES8328_FORMATS (SNDRV_PCM_FMTBIT_S16_LE) | |
64 | ||
65 | struct es8328_priv { | |
66 | struct regmap *regmap; | |
67 | struct clk *clk; | |
68 | int playback_fs; | |
69 | bool deemph; | |
70 | struct regulator_bulk_data supplies[ES8328_SUPPLY_NUM]; | |
71 | }; | |
72 | ||
73 | /* | |
74 | * ES8328 Controls | |
75 | */ | |
76 | ||
77 | static const char * const adcpol_txt[] = {"Normal", "L Invert", "R Invert", | |
78 | "L + R Invert"}; | |
79 | static SOC_ENUM_SINGLE_DECL(adcpol, | |
80 | ES8328_ADCCONTROL6, 6, adcpol_txt); | |
81 | ||
82 | static const DECLARE_TLV_DB_SCALE(play_tlv, -3000, 100, 0); | |
83 | static const DECLARE_TLV_DB_SCALE(dac_adc_tlv, -9600, 50, 0); | |
84 | static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 300, 0); | |
85 | static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0); | |
86 | static const DECLARE_TLV_DB_SCALE(mic_tlv, 0, 300, 0); | |
87 | ||
84ebac4d JK |
88 | static const struct { |
89 | int rate; | |
90 | unsigned int val; | |
91 | } deemph_settings[] = { | |
92 | { 0, ES8328_DACCONTROL6_DEEMPH_OFF }, | |
93 | { 32000, ES8328_DACCONTROL6_DEEMPH_32k }, | |
94 | { 44100, ES8328_DACCONTROL6_DEEMPH_44_1k }, | |
95 | { 48000, ES8328_DACCONTROL6_DEEMPH_48k }, | |
96 | }; | |
567e4f98 SC |
97 | |
98 | static int es8328_set_deemph(struct snd_soc_codec *codec) | |
99 | { | |
100 | struct es8328_priv *es8328 = snd_soc_codec_get_drvdata(codec); | |
101 | int val, i, best; | |
102 | ||
103 | /* | |
104 | * If we're using deemphasis select the nearest available sample | |
105 | * rate. | |
106 | */ | |
107 | if (es8328->deemph) { | |
84ebac4d JK |
108 | best = 0; |
109 | for (i = 1; i < ARRAY_SIZE(deemph_settings); i++) { | |
110 | if (abs(deemph_settings[i].rate - es8328->playback_fs) < | |
111 | abs(deemph_settings[best].rate - es8328->playback_fs)) | |
567e4f98 SC |
112 | best = i; |
113 | } | |
114 | ||
84ebac4d | 115 | val = deemph_settings[best].val; |
567e4f98 | 116 | } else { |
84ebac4d | 117 | val = ES8328_DACCONTROL6_DEEMPH_OFF; |
567e4f98 SC |
118 | } |
119 | ||
120 | dev_dbg(codec->dev, "Set deemphasis %d\n", val); | |
121 | ||
84ebac4d JK |
122 | return snd_soc_update_bits(codec, ES8328_DACCONTROL6, |
123 | ES8328_DACCONTROL6_DEEMPH_MASK, val); | |
567e4f98 SC |
124 | } |
125 | ||
126 | static int es8328_get_deemph(struct snd_kcontrol *kcontrol, | |
127 | struct snd_ctl_elem_value *ucontrol) | |
128 | { | |
129 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); | |
130 | struct es8328_priv *es8328 = snd_soc_codec_get_drvdata(codec); | |
131 | ||
d223b0e7 | 132 | ucontrol->value.integer.value[0] = es8328->deemph; |
567e4f98 SC |
133 | return 0; |
134 | } | |
135 | ||
136 | static int es8328_put_deemph(struct snd_kcontrol *kcontrol, | |
137 | struct snd_ctl_elem_value *ucontrol) | |
138 | { | |
139 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); | |
140 | struct es8328_priv *es8328 = snd_soc_codec_get_drvdata(codec); | |
7ab8a54e | 141 | unsigned int deemph = ucontrol->value.integer.value[0]; |
567e4f98 SC |
142 | int ret; |
143 | ||
144 | if (deemph > 1) | |
145 | return -EINVAL; | |
146 | ||
147 | ret = es8328_set_deemph(codec); | |
148 | if (ret < 0) | |
149 | return ret; | |
150 | ||
151 | es8328->deemph = deemph; | |
152 | ||
153 | return 0; | |
154 | } | |
155 | ||
156 | ||
157 | ||
158 | static const struct snd_kcontrol_new es8328_snd_controls[] = { | |
159 | SOC_DOUBLE_R_TLV("Capture Digital Volume", | |
160 | ES8328_ADCCONTROL8, ES8328_ADCCONTROL9, | |
161 | 0, 0xc0, 1, dac_adc_tlv), | |
162 | SOC_SINGLE("Capture ZC Switch", ES8328_ADCCONTROL7, 6, 1, 0), | |
163 | ||
164 | SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0, | |
165 | es8328_get_deemph, es8328_put_deemph), | |
166 | ||
167 | SOC_ENUM("Capture Polarity", adcpol), | |
168 | ||
169 | SOC_SINGLE_TLV("Left Mixer Left Bypass Volume", | |
170 | ES8328_DACCONTROL17, 3, 7, 1, bypass_tlv), | |
171 | SOC_SINGLE_TLV("Left Mixer Right Bypass Volume", | |
172 | ES8328_DACCONTROL19, 3, 7, 1, bypass_tlv), | |
173 | SOC_SINGLE_TLV("Right Mixer Left Bypass Volume", | |
174 | ES8328_DACCONTROL18, 3, 7, 1, bypass_tlv), | |
175 | SOC_SINGLE_TLV("Right Mixer Right Bypass Volume", | |
176 | ES8328_DACCONTROL20, 3, 7, 1, bypass_tlv), | |
177 | ||
178 | SOC_DOUBLE_R_TLV("PCM Volume", | |
179 | ES8328_LDACVOL, ES8328_RDACVOL, | |
180 | 0, ES8328_DACVOL_MAX, 1, dac_adc_tlv), | |
181 | ||
182 | SOC_DOUBLE_R_TLV("Output 1 Playback Volume", | |
183 | ES8328_LOUT1VOL, ES8328_ROUT1VOL, | |
184 | 0, ES8328_OUT1VOL_MAX, 0, play_tlv), | |
185 | ||
186 | SOC_DOUBLE_R_TLV("Output 2 Playback Volume", | |
187 | ES8328_LOUT2VOL, ES8328_ROUT2VOL, | |
188 | 0, ES8328_OUT2VOL_MAX, 0, play_tlv), | |
189 | ||
190 | SOC_DOUBLE_TLV("Mic PGA Volume", ES8328_ADCCONTROL1, | |
191 | 4, 0, 8, 0, mic_tlv), | |
192 | }; | |
193 | ||
194 | /* | |
195 | * DAPM Controls | |
196 | */ | |
197 | ||
198 | static const char * const es8328_line_texts[] = { | |
199 | "Line 1", "Line 2", "PGA", "Differential"}; | |
200 | ||
201 | static const struct soc_enum es8328_lline_enum = | |
202 | SOC_ENUM_SINGLE(ES8328_DACCONTROL16, 3, | |
203 | ARRAY_SIZE(es8328_line_texts), | |
204 | es8328_line_texts); | |
205 | static const struct snd_kcontrol_new es8328_left_line_controls = | |
206 | SOC_DAPM_ENUM("Route", es8328_lline_enum); | |
207 | ||
208 | static const struct soc_enum es8328_rline_enum = | |
209 | SOC_ENUM_SINGLE(ES8328_DACCONTROL16, 0, | |
210 | ARRAY_SIZE(es8328_line_texts), | |
211 | es8328_line_texts); | |
212 | static const struct snd_kcontrol_new es8328_right_line_controls = | |
213 | SOC_DAPM_ENUM("Route", es8328_lline_enum); | |
214 | ||
215 | /* Left Mixer */ | |
216 | static const struct snd_kcontrol_new es8328_left_mixer_controls[] = { | |
352d52e2 JK |
217 | SOC_DAPM_SINGLE("Playback Switch", ES8328_DACCONTROL17, 7, 1, 0), |
218 | SOC_DAPM_SINGLE("Left Bypass Switch", ES8328_DACCONTROL17, 6, 1, 0), | |
219 | SOC_DAPM_SINGLE("Right Playback Switch", ES8328_DACCONTROL18, 7, 1, 0), | |
220 | SOC_DAPM_SINGLE("Right Bypass Switch", ES8328_DACCONTROL18, 6, 1, 0), | |
567e4f98 SC |
221 | }; |
222 | ||
223 | /* Right Mixer */ | |
224 | static const struct snd_kcontrol_new es8328_right_mixer_controls[] = { | |
352d52e2 JK |
225 | SOC_DAPM_SINGLE("Left Playback Switch", ES8328_DACCONTROL19, 7, 1, 0), |
226 | SOC_DAPM_SINGLE("Left Bypass Switch", ES8328_DACCONTROL19, 6, 1, 0), | |
227 | SOC_DAPM_SINGLE("Playback Switch", ES8328_DACCONTROL20, 7, 1, 0), | |
228 | SOC_DAPM_SINGLE("Right Bypass Switch", ES8328_DACCONTROL20, 6, 1, 0), | |
567e4f98 SC |
229 | }; |
230 | ||
231 | static const char * const es8328_pga_sel[] = { | |
232 | "Line 1", "Line 2", "Line 3", "Differential"}; | |
233 | ||
234 | /* Left PGA Mux */ | |
235 | static const struct soc_enum es8328_lpga_enum = | |
236 | SOC_ENUM_SINGLE(ES8328_ADCCONTROL2, 6, | |
237 | ARRAY_SIZE(es8328_pga_sel), | |
238 | es8328_pga_sel); | |
239 | static const struct snd_kcontrol_new es8328_left_pga_controls = | |
240 | SOC_DAPM_ENUM("Route", es8328_lpga_enum); | |
241 | ||
242 | /* Right PGA Mux */ | |
243 | static const struct soc_enum es8328_rpga_enum = | |
244 | SOC_ENUM_SINGLE(ES8328_ADCCONTROL2, 4, | |
245 | ARRAY_SIZE(es8328_pga_sel), | |
246 | es8328_pga_sel); | |
247 | static const struct snd_kcontrol_new es8328_right_pga_controls = | |
248 | SOC_DAPM_ENUM("Route", es8328_rpga_enum); | |
249 | ||
250 | /* Differential Mux */ | |
251 | static const char * const es8328_diff_sel[] = {"Line 1", "Line 2"}; | |
252 | static SOC_ENUM_SINGLE_DECL(diffmux, | |
253 | ES8328_ADCCONTROL3, 7, es8328_diff_sel); | |
254 | static const struct snd_kcontrol_new es8328_diffmux_controls = | |
255 | SOC_DAPM_ENUM("Route", diffmux); | |
256 | ||
257 | /* Mono ADC Mux */ | |
258 | static const char * const es8328_mono_mux[] = {"Stereo", "Mono (Left)", | |
259 | "Mono (Right)", "Digital Mono"}; | |
260 | static SOC_ENUM_SINGLE_DECL(monomux, | |
261 | ES8328_ADCCONTROL3, 3, es8328_mono_mux); | |
262 | static const struct snd_kcontrol_new es8328_monomux_controls = | |
263 | SOC_DAPM_ENUM("Route", monomux); | |
264 | ||
265 | static const struct snd_soc_dapm_widget es8328_dapm_widgets[] = { | |
266 | SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0, | |
267 | &es8328_diffmux_controls), | |
268 | SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0, | |
269 | &es8328_monomux_controls), | |
270 | SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0, | |
271 | &es8328_monomux_controls), | |
272 | ||
273 | SND_SOC_DAPM_MUX("Left PGA Mux", ES8328_ADCPOWER, | |
274 | ES8328_ADCPOWER_AINL_OFF, 1, | |
275 | &es8328_left_pga_controls), | |
276 | SND_SOC_DAPM_MUX("Right PGA Mux", ES8328_ADCPOWER, | |
277 | ES8328_ADCPOWER_AINR_OFF, 1, | |
278 | &es8328_right_pga_controls), | |
279 | ||
280 | SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0, | |
281 | &es8328_left_line_controls), | |
282 | SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0, | |
283 | &es8328_right_line_controls), | |
284 | ||
285 | SND_SOC_DAPM_ADC("Right ADC", "Right Capture", ES8328_ADCPOWER, | |
286 | ES8328_ADCPOWER_ADCR_OFF, 1), | |
287 | SND_SOC_DAPM_ADC("Left ADC", "Left Capture", ES8328_ADCPOWER, | |
288 | ES8328_ADCPOWER_ADCL_OFF, 1), | |
289 | ||
290 | SND_SOC_DAPM_SUPPLY("Mic Bias", ES8328_ADCPOWER, | |
291 | ES8328_ADCPOWER_MIC_BIAS_OFF, 1, NULL, 0), | |
292 | SND_SOC_DAPM_SUPPLY("Mic Bias Gen", ES8328_ADCPOWER, | |
293 | ES8328_ADCPOWER_ADC_BIAS_GEN_OFF, 1, NULL, 0), | |
294 | ||
295 | SND_SOC_DAPM_SUPPLY("DAC STM", ES8328_CHIPPOWER, | |
296 | ES8328_CHIPPOWER_DACSTM_RESET, 1, NULL, 0), | |
297 | SND_SOC_DAPM_SUPPLY("ADC STM", ES8328_CHIPPOWER, | |
298 | ES8328_CHIPPOWER_ADCSTM_RESET, 1, NULL, 0), | |
299 | ||
300 | SND_SOC_DAPM_SUPPLY("DAC DIG", ES8328_CHIPPOWER, | |
301 | ES8328_CHIPPOWER_DACDIG_OFF, 1, NULL, 0), | |
302 | SND_SOC_DAPM_SUPPLY("ADC DIG", ES8328_CHIPPOWER, | |
303 | ES8328_CHIPPOWER_ADCDIG_OFF, 1, NULL, 0), | |
304 | ||
305 | SND_SOC_DAPM_SUPPLY("DAC DLL", ES8328_CHIPPOWER, | |
306 | ES8328_CHIPPOWER_DACDLL_OFF, 1, NULL, 0), | |
307 | SND_SOC_DAPM_SUPPLY("ADC DLL", ES8328_CHIPPOWER, | |
308 | ES8328_CHIPPOWER_ADCDLL_OFF, 1, NULL, 0), | |
309 | ||
310 | SND_SOC_DAPM_SUPPLY("ADC Vref", ES8328_CHIPPOWER, | |
311 | ES8328_CHIPPOWER_ADCVREF_OFF, 1, NULL, 0), | |
312 | SND_SOC_DAPM_SUPPLY("DAC Vref", ES8328_CHIPPOWER, | |
313 | ES8328_CHIPPOWER_DACVREF_OFF, 1, NULL, 0), | |
314 | ||
315 | SND_SOC_DAPM_DAC("Right DAC", "Right Playback", ES8328_DACPOWER, | |
316 | ES8328_DACPOWER_RDAC_OFF, 1), | |
317 | SND_SOC_DAPM_DAC("Left DAC", "Left Playback", ES8328_DACPOWER, | |
318 | ES8328_DACPOWER_LDAC_OFF, 1), | |
319 | ||
320 | SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0, | |
321 | &es8328_left_mixer_controls[0], | |
322 | ARRAY_SIZE(es8328_left_mixer_controls)), | |
323 | SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0, | |
324 | &es8328_right_mixer_controls[0], | |
325 | ARRAY_SIZE(es8328_right_mixer_controls)), | |
326 | ||
327 | SND_SOC_DAPM_PGA("Right Out 2", ES8328_DACPOWER, | |
328 | ES8328_DACPOWER_ROUT2_ON, 0, NULL, 0), | |
329 | SND_SOC_DAPM_PGA("Left Out 2", ES8328_DACPOWER, | |
330 | ES8328_DACPOWER_LOUT2_ON, 0, NULL, 0), | |
331 | SND_SOC_DAPM_PGA("Right Out 1", ES8328_DACPOWER, | |
332 | ES8328_DACPOWER_ROUT1_ON, 0, NULL, 0), | |
333 | SND_SOC_DAPM_PGA("Left Out 1", ES8328_DACPOWER, | |
334 | ES8328_DACPOWER_LOUT1_ON, 0, NULL, 0), | |
335 | ||
336 | SND_SOC_DAPM_OUTPUT("LOUT1"), | |
337 | SND_SOC_DAPM_OUTPUT("ROUT1"), | |
338 | SND_SOC_DAPM_OUTPUT("LOUT2"), | |
339 | SND_SOC_DAPM_OUTPUT("ROUT2"), | |
340 | ||
341 | SND_SOC_DAPM_INPUT("LINPUT1"), | |
342 | SND_SOC_DAPM_INPUT("LINPUT2"), | |
343 | SND_SOC_DAPM_INPUT("RINPUT1"), | |
344 | SND_SOC_DAPM_INPUT("RINPUT2"), | |
345 | }; | |
346 | ||
347 | static const struct snd_soc_dapm_route es8328_dapm_routes[] = { | |
348 | ||
349 | { "Left Line Mux", "Line 1", "LINPUT1" }, | |
350 | { "Left Line Mux", "Line 2", "LINPUT2" }, | |
351 | { "Left Line Mux", "PGA", "Left PGA Mux" }, | |
352 | { "Left Line Mux", "Differential", "Differential Mux" }, | |
353 | ||
354 | { "Right Line Mux", "Line 1", "RINPUT1" }, | |
355 | { "Right Line Mux", "Line 2", "RINPUT2" }, | |
356 | { "Right Line Mux", "PGA", "Right PGA Mux" }, | |
357 | { "Right Line Mux", "Differential", "Differential Mux" }, | |
358 | ||
359 | { "Left PGA Mux", "Line 1", "LINPUT1" }, | |
360 | { "Left PGA Mux", "Line 2", "LINPUT2" }, | |
361 | { "Left PGA Mux", "Differential", "Differential Mux" }, | |
362 | ||
363 | { "Right PGA Mux", "Line 1", "RINPUT1" }, | |
364 | { "Right PGA Mux", "Line 2", "RINPUT2" }, | |
365 | { "Right PGA Mux", "Differential", "Differential Mux" }, | |
366 | ||
367 | { "Differential Mux", "Line 1", "LINPUT1" }, | |
368 | { "Differential Mux", "Line 1", "RINPUT1" }, | |
369 | { "Differential Mux", "Line 2", "LINPUT2" }, | |
370 | { "Differential Mux", "Line 2", "RINPUT2" }, | |
371 | ||
372 | { "Left ADC Mux", "Stereo", "Left PGA Mux" }, | |
373 | { "Left ADC Mux", "Mono (Left)", "Left PGA Mux" }, | |
374 | { "Left ADC Mux", "Digital Mono", "Left PGA Mux" }, | |
375 | ||
376 | { "Right ADC Mux", "Stereo", "Right PGA Mux" }, | |
377 | { "Right ADC Mux", "Mono (Right)", "Right PGA Mux" }, | |
378 | { "Right ADC Mux", "Digital Mono", "Right PGA Mux" }, | |
379 | ||
380 | { "Left ADC", NULL, "Left ADC Mux" }, | |
381 | { "Right ADC", NULL, "Right ADC Mux" }, | |
382 | ||
383 | { "ADC DIG", NULL, "ADC STM" }, | |
384 | { "ADC DIG", NULL, "ADC Vref" }, | |
385 | { "ADC DIG", NULL, "ADC DLL" }, | |
386 | ||
387 | { "Left ADC", NULL, "ADC DIG" }, | |
388 | { "Right ADC", NULL, "ADC DIG" }, | |
389 | ||
390 | { "Mic Bias", NULL, "Mic Bias Gen" }, | |
391 | ||
392 | { "Left Line Mux", "Line 1", "LINPUT1" }, | |
393 | { "Left Line Mux", "Line 2", "LINPUT2" }, | |
394 | { "Left Line Mux", "PGA", "Left PGA Mux" }, | |
395 | { "Left Line Mux", "Differential", "Differential Mux" }, | |
396 | ||
397 | { "Right Line Mux", "Line 1", "RINPUT1" }, | |
398 | { "Right Line Mux", "Line 2", "RINPUT2" }, | |
399 | { "Right Line Mux", "PGA", "Right PGA Mux" }, | |
400 | { "Right Line Mux", "Differential", "Differential Mux" }, | |
401 | ||
402 | { "Left Out 1", NULL, "Left DAC" }, | |
403 | { "Right Out 1", NULL, "Right DAC" }, | |
404 | { "Left Out 2", NULL, "Left DAC" }, | |
405 | { "Right Out 2", NULL, "Right DAC" }, | |
406 | ||
407 | { "Left Mixer", "Playback Switch", "Left DAC" }, | |
408 | { "Left Mixer", "Left Bypass Switch", "Left Line Mux" }, | |
409 | { "Left Mixer", "Right Playback Switch", "Right DAC" }, | |
410 | { "Left Mixer", "Right Bypass Switch", "Right Line Mux" }, | |
411 | ||
412 | { "Right Mixer", "Left Playback Switch", "Left DAC" }, | |
413 | { "Right Mixer", "Left Bypass Switch", "Left Line Mux" }, | |
414 | { "Right Mixer", "Playback Switch", "Right DAC" }, | |
415 | { "Right Mixer", "Right Bypass Switch", "Right Line Mux" }, | |
416 | ||
417 | { "DAC DIG", NULL, "DAC STM" }, | |
418 | { "DAC DIG", NULL, "DAC Vref" }, | |
419 | { "DAC DIG", NULL, "DAC DLL" }, | |
420 | ||
421 | { "Left DAC", NULL, "DAC DIG" }, | |
422 | { "Right DAC", NULL, "DAC DIG" }, | |
423 | ||
424 | { "Left Out 1", NULL, "Left Mixer" }, | |
425 | { "LOUT1", NULL, "Left Out 1" }, | |
426 | { "Right Out 1", NULL, "Right Mixer" }, | |
427 | { "ROUT1", NULL, "Right Out 1" }, | |
428 | ||
429 | { "Left Out 2", NULL, "Left Mixer" }, | |
430 | { "LOUT2", NULL, "Left Out 2" }, | |
431 | { "Right Out 2", NULL, "Right Mixer" }, | |
432 | { "ROUT2", NULL, "Right Out 2" }, | |
433 | }; | |
434 | ||
435 | static int es8328_mute(struct snd_soc_dai *dai, int mute) | |
436 | { | |
437 | return snd_soc_update_bits(dai->codec, ES8328_DACCONTROL3, | |
438 | ES8328_DACCONTROL3_DACMUTE, | |
439 | mute ? ES8328_DACCONTROL3_DACMUTE : 0); | |
440 | } | |
441 | ||
442 | static int es8328_hw_params(struct snd_pcm_substream *substream, | |
443 | struct snd_pcm_hw_params *params, | |
444 | struct snd_soc_dai *dai) | |
445 | { | |
446 | struct snd_soc_codec *codec = dai->codec; | |
447 | struct es8328_priv *es8328 = snd_soc_codec_get_drvdata(codec); | |
448 | int clk_rate; | |
449 | int i; | |
450 | int reg; | |
451 | u8 ratio; | |
452 | ||
453 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
454 | reg = ES8328_DACCONTROL2; | |
455 | else | |
456 | reg = ES8328_ADCCONTROL5; | |
457 | ||
458 | clk_rate = clk_get_rate(es8328->clk); | |
459 | ||
460 | if ((clk_rate != ES8328_SYSCLK_RATE_1X) && | |
461 | (clk_rate != ES8328_SYSCLK_RATE_2X)) { | |
462 | dev_err(codec->dev, | |
463 | "%s: clock is running at %d Hz, not %d or %d Hz\n", | |
464 | __func__, clk_rate, | |
465 | ES8328_SYSCLK_RATE_1X, ES8328_SYSCLK_RATE_2X); | |
466 | return -EINVAL; | |
467 | } | |
468 | ||
469 | /* find master mode MCLK to sampling frequency ratio */ | |
470 | ratio = mclk_ratios[0].rate; | |
471 | for (i = 1; i < ARRAY_SIZE(mclk_ratios); i++) | |
472 | if (params_rate(params) <= mclk_ratios[i].rate) | |
473 | ratio = mclk_ratios[i].ratio; | |
474 | ||
475 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
476 | es8328->playback_fs = params_rate(params); | |
477 | es8328_set_deemph(codec); | |
478 | } | |
479 | ||
480 | return snd_soc_update_bits(codec, reg, ES8328_RATEMASK, ratio); | |
481 | } | |
482 | ||
483 | static int es8328_set_dai_fmt(struct snd_soc_dai *codec_dai, | |
484 | unsigned int fmt) | |
485 | { | |
486 | struct snd_soc_codec *codec = codec_dai->codec; | |
487 | struct es8328_priv *es8328 = snd_soc_codec_get_drvdata(codec); | |
488 | int clk_rate; | |
489 | u8 mode = ES8328_DACCONTROL1_DACWL_16; | |
490 | ||
491 | /* set master/slave audio interface */ | |
492 | if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBM_CFM) | |
493 | return -EINVAL; | |
494 | ||
495 | /* interface format */ | |
496 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
497 | case SND_SOC_DAIFMT_I2S: | |
498 | mode |= ES8328_DACCONTROL1_DACFORMAT_I2S; | |
499 | break; | |
500 | case SND_SOC_DAIFMT_RIGHT_J: | |
501 | mode |= ES8328_DACCONTROL1_DACFORMAT_RJUST; | |
502 | break; | |
503 | case SND_SOC_DAIFMT_LEFT_J: | |
504 | mode |= ES8328_DACCONTROL1_DACFORMAT_LJUST; | |
505 | break; | |
506 | default: | |
507 | return -EINVAL; | |
508 | } | |
509 | ||
510 | /* clock inversion */ | |
511 | if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF) | |
512 | return -EINVAL; | |
513 | ||
514 | snd_soc_write(codec, ES8328_DACCONTROL1, mode); | |
515 | snd_soc_write(codec, ES8328_ADCCONTROL4, mode); | |
516 | ||
517 | /* Master serial port mode, with BCLK generated automatically */ | |
518 | clk_rate = clk_get_rate(es8328->clk); | |
519 | if (clk_rate == ES8328_SYSCLK_RATE_1X) | |
520 | snd_soc_write(codec, ES8328_MASTERMODE, | |
521 | ES8328_MASTERMODE_MSC); | |
522 | else | |
523 | snd_soc_write(codec, ES8328_MASTERMODE, | |
524 | ES8328_MASTERMODE_MCLKDIV2 | | |
525 | ES8328_MASTERMODE_MSC); | |
526 | ||
527 | return 0; | |
528 | } | |
529 | ||
530 | static int es8328_set_bias_level(struct snd_soc_codec *codec, | |
531 | enum snd_soc_bias_level level) | |
532 | { | |
533 | switch (level) { | |
534 | case SND_SOC_BIAS_ON: | |
535 | break; | |
536 | ||
537 | case SND_SOC_BIAS_PREPARE: | |
538 | /* VREF, VMID=2x50k, digital enabled */ | |
539 | snd_soc_write(codec, ES8328_CHIPPOWER, 0); | |
540 | snd_soc_update_bits(codec, ES8328_CONTROL1, | |
541 | ES8328_CONTROL1_VMIDSEL_MASK | | |
542 | ES8328_CONTROL1_ENREF, | |
543 | ES8328_CONTROL1_VMIDSEL_50k | | |
544 | ES8328_CONTROL1_ENREF); | |
545 | break; | |
546 | ||
547 | case SND_SOC_BIAS_STANDBY: | |
2aff57e3 | 548 | if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) { |
567e4f98 SC |
549 | snd_soc_update_bits(codec, ES8328_CONTROL1, |
550 | ES8328_CONTROL1_VMIDSEL_MASK | | |
551 | ES8328_CONTROL1_ENREF, | |
552 | ES8328_CONTROL1_VMIDSEL_5k | | |
553 | ES8328_CONTROL1_ENREF); | |
554 | ||
555 | /* Charge caps */ | |
556 | msleep(100); | |
557 | } | |
558 | ||
559 | snd_soc_write(codec, ES8328_CONTROL2, | |
560 | ES8328_CONTROL2_OVERCURRENT_ON | | |
561 | ES8328_CONTROL2_THERMAL_SHUTDOWN_ON); | |
562 | ||
563 | /* VREF, VMID=2*500k, digital stopped */ | |
564 | snd_soc_update_bits(codec, ES8328_CONTROL1, | |
565 | ES8328_CONTROL1_VMIDSEL_MASK | | |
566 | ES8328_CONTROL1_ENREF, | |
567 | ES8328_CONTROL1_VMIDSEL_500k | | |
568 | ES8328_CONTROL1_ENREF); | |
569 | break; | |
570 | ||
571 | case SND_SOC_BIAS_OFF: | |
572 | snd_soc_update_bits(codec, ES8328_CONTROL1, | |
573 | ES8328_CONTROL1_VMIDSEL_MASK | | |
574 | ES8328_CONTROL1_ENREF, | |
575 | 0); | |
576 | break; | |
577 | } | |
567e4f98 SC |
578 | return 0; |
579 | } | |
580 | ||
581 | static const struct snd_soc_dai_ops es8328_dai_ops = { | |
582 | .hw_params = es8328_hw_params, | |
583 | .digital_mute = es8328_mute, | |
584 | .set_fmt = es8328_set_dai_fmt, | |
585 | }; | |
586 | ||
587 | static struct snd_soc_dai_driver es8328_dai = { | |
588 | .name = "es8328-hifi-analog", | |
589 | .playback = { | |
590 | .stream_name = "Playback", | |
591 | .channels_min = 2, | |
592 | .channels_max = 2, | |
593 | .rates = ES8328_RATES, | |
594 | .formats = ES8328_FORMATS, | |
595 | }, | |
596 | .capture = { | |
597 | .stream_name = "Capture", | |
598 | .channels_min = 2, | |
599 | .channels_max = 2, | |
600 | .rates = ES8328_RATES, | |
601 | .formats = ES8328_FORMATS, | |
602 | }, | |
603 | .ops = &es8328_dai_ops, | |
604 | }; | |
605 | ||
606 | static int es8328_suspend(struct snd_soc_codec *codec) | |
607 | { | |
608 | struct es8328_priv *es8328; | |
609 | int ret; | |
610 | ||
611 | es8328 = snd_soc_codec_get_drvdata(codec); | |
612 | ||
567e4f98 SC |
613 | clk_disable_unprepare(es8328->clk); |
614 | ||
615 | ret = regulator_bulk_disable(ARRAY_SIZE(es8328->supplies), | |
616 | es8328->supplies); | |
617 | if (ret) { | |
618 | dev_err(codec->dev, "unable to disable regulators\n"); | |
619 | return ret; | |
620 | } | |
621 | return 0; | |
622 | } | |
623 | ||
624 | static int es8328_resume(struct snd_soc_codec *codec) | |
625 | { | |
626 | struct regmap *regmap = dev_get_regmap(codec->dev, NULL); | |
627 | struct es8328_priv *es8328; | |
628 | int ret; | |
629 | ||
630 | es8328 = snd_soc_codec_get_drvdata(codec); | |
631 | ||
632 | ret = clk_prepare_enable(es8328->clk); | |
633 | if (ret) { | |
634 | dev_err(codec->dev, "unable to enable clock\n"); | |
635 | return ret; | |
636 | } | |
637 | ||
638 | ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies), | |
639 | es8328->supplies); | |
640 | if (ret) { | |
641 | dev_err(codec->dev, "unable to enable regulators\n"); | |
642 | return ret; | |
643 | } | |
644 | ||
645 | regcache_mark_dirty(regmap); | |
646 | ret = regcache_sync(regmap); | |
647 | if (ret) { | |
648 | dev_err(codec->dev, "unable to sync regcache\n"); | |
649 | return ret; | |
650 | } | |
651 | ||
567e4f98 SC |
652 | return 0; |
653 | } | |
654 | ||
655 | static int es8328_codec_probe(struct snd_soc_codec *codec) | |
656 | { | |
657 | struct es8328_priv *es8328; | |
658 | int ret; | |
659 | ||
660 | es8328 = snd_soc_codec_get_drvdata(codec); | |
661 | ||
662 | ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies), | |
663 | es8328->supplies); | |
664 | if (ret) { | |
665 | dev_err(codec->dev, "unable to enable regulators\n"); | |
666 | return ret; | |
667 | } | |
668 | ||
669 | /* Setup clocks */ | |
670 | es8328->clk = devm_clk_get(codec->dev, NULL); | |
671 | if (IS_ERR(es8328->clk)) { | |
672 | dev_err(codec->dev, "codec clock missing or invalid\n"); | |
75c3daaa | 673 | ret = PTR_ERR(es8328->clk); |
567e4f98 SC |
674 | goto clk_fail; |
675 | } | |
676 | ||
677 | ret = clk_prepare_enable(es8328->clk); | |
678 | if (ret) { | |
679 | dev_err(codec->dev, "unable to prepare codec clk\n"); | |
680 | goto clk_fail; | |
681 | } | |
682 | ||
683 | return 0; | |
684 | ||
685 | clk_fail: | |
686 | regulator_bulk_disable(ARRAY_SIZE(es8328->supplies), | |
687 | es8328->supplies); | |
688 | return ret; | |
689 | } | |
690 | ||
691 | static int es8328_remove(struct snd_soc_codec *codec) | |
692 | { | |
693 | struct es8328_priv *es8328; | |
694 | ||
695 | es8328 = snd_soc_codec_get_drvdata(codec); | |
696 | ||
697 | if (es8328->clk) | |
698 | clk_disable_unprepare(es8328->clk); | |
699 | ||
700 | regulator_bulk_disable(ARRAY_SIZE(es8328->supplies), | |
701 | es8328->supplies); | |
702 | ||
703 | return 0; | |
704 | } | |
705 | ||
706 | const struct regmap_config es8328_regmap_config = { | |
707 | .reg_bits = 8, | |
708 | .val_bits = 8, | |
709 | .max_register = ES8328_REG_MAX, | |
710 | .cache_type = REGCACHE_RBTREE, | |
711 | }; | |
712 | EXPORT_SYMBOL_GPL(es8328_regmap_config); | |
713 | ||
714 | static struct snd_soc_codec_driver es8328_codec_driver = { | |
715 | .probe = es8328_codec_probe, | |
716 | .suspend = es8328_suspend, | |
717 | .resume = es8328_resume, | |
718 | .remove = es8328_remove, | |
719 | .set_bias_level = es8328_set_bias_level, | |
8d01370f LPC |
720 | .suspend_bias_off = true, |
721 | ||
567e4f98 SC |
722 | .controls = es8328_snd_controls, |
723 | .num_controls = ARRAY_SIZE(es8328_snd_controls), | |
724 | .dapm_widgets = es8328_dapm_widgets, | |
725 | .num_dapm_widgets = ARRAY_SIZE(es8328_dapm_widgets), | |
726 | .dapm_routes = es8328_dapm_routes, | |
727 | .num_dapm_routes = ARRAY_SIZE(es8328_dapm_routes), | |
728 | }; | |
729 | ||
730 | int es8328_probe(struct device *dev, struct regmap *regmap) | |
731 | { | |
732 | struct es8328_priv *es8328; | |
733 | int ret; | |
734 | int i; | |
735 | ||
736 | if (IS_ERR(regmap)) | |
737 | return PTR_ERR(regmap); | |
738 | ||
739 | es8328 = devm_kzalloc(dev, sizeof(*es8328), GFP_KERNEL); | |
740 | if (es8328 == NULL) | |
741 | return -ENOMEM; | |
742 | ||
743 | es8328->regmap = regmap; | |
744 | ||
745 | for (i = 0; i < ARRAY_SIZE(es8328->supplies); i++) | |
746 | es8328->supplies[i].supply = supply_names[i]; | |
747 | ||
748 | ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(es8328->supplies), | |
749 | es8328->supplies); | |
750 | if (ret) { | |
751 | dev_err(dev, "unable to get regulators\n"); | |
752 | return ret; | |
753 | } | |
754 | ||
755 | dev_set_drvdata(dev, es8328); | |
756 | ||
757 | return snd_soc_register_codec(dev, | |
758 | &es8328_codec_driver, &es8328_dai, 1); | |
759 | } | |
760 | EXPORT_SYMBOL_GPL(es8328_probe); | |
761 | ||
762 | MODULE_DESCRIPTION("ASoC ES8328 driver"); | |
763 | MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>"); | |
764 | MODULE_LICENSE("GPL"); |