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1 | // SPDX-License-Identifier: GPL-2.0 |
2 | // | |
3 | // CS42L43 CODEC driver | |
4 | // | |
5 | // Copyright (C) 2022-2023 Cirrus Logic, Inc. and | |
6 | // Cirrus Logic International Semiconductor Ltd. | |
7 | ||
8 | #include <linux/bitops.h> | |
9 | #include <linux/err.h> | |
10 | #include <linux/errno.h> | |
11 | #include <linux/gcd.h> | |
12 | #include <linux/irq.h> | |
13 | #include <linux/jiffies.h> | |
14 | #include <linux/mfd/cs42l43.h> | |
15 | #include <linux/mfd/cs42l43-regs.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/pm_runtime.h> | |
18 | #include <linux/string.h> | |
19 | #include <sound/control.h> | |
20 | #include <sound/pcm.h> | |
21 | #include <sound/pcm_params.h> | |
22 | #include <sound/soc-component.h> | |
23 | #include <sound/soc-dapm.h> | |
24 | #include <sound/soc-dai.h> | |
25 | #include <sound/soc.h> | |
26 | #include <sound/tlv.h> | |
27 | ||
28 | #include "cs42l43.h" | |
29 | ||
30 | #define CS42L43_DECL_MUX(name, reg) \ | |
31 | static SOC_VALUE_ENUM_SINGLE_DECL(cs42l43_##name##_enum, reg, \ | |
32 | 0, CS42L43_MIXER_SRC_MASK, \ | |
33 | cs42l43_mixer_texts, cs42l43_mixer_values); \ | |
34 | static const struct snd_kcontrol_new cs42l43_##name##_mux = \ | |
35 | SOC_DAPM_ENUM("Route", cs42l43_##name##_enum) | |
36 | ||
37 | #define CS42L43_DECL_MIXER(name, reg) \ | |
38 | CS42L43_DECL_MUX(name##_in1, reg); \ | |
39 | CS42L43_DECL_MUX(name##_in2, reg + 0x4); \ | |
40 | CS42L43_DECL_MUX(name##_in3, reg + 0x8); \ | |
41 | CS42L43_DECL_MUX(name##_in4, reg + 0xC) | |
42 | ||
43 | #define CS42L43_DAPM_MUX(name_str, name) \ | |
44 | SND_SOC_DAPM_MUX(name_str " Input", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_mux) | |
45 | ||
46 | #define CS42L43_DAPM_MIXER(name_str, name) \ | |
47 | SND_SOC_DAPM_MUX(name_str " Input 1", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_in1_mux), \ | |
48 | SND_SOC_DAPM_MUX(name_str " Input 2", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_in2_mux), \ | |
49 | SND_SOC_DAPM_MUX(name_str " Input 3", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_in3_mux), \ | |
50 | SND_SOC_DAPM_MUX(name_str " Input 4", SND_SOC_NOPM, 0, 0, &cs42l43_##name##_in4_mux), \ | |
51 | SND_SOC_DAPM_MIXER(name_str " Mixer", SND_SOC_NOPM, 0, 0, NULL, 0) | |
52 | ||
53 | #define CS42L43_BASE_ROUTES(name_str) \ | |
54 | { name_str, "Tone Generator 1", "Tone 1" }, \ | |
55 | { name_str, "Tone Generator 2", "Tone 2" }, \ | |
56 | { name_str, "Decimator 1", "Decimator 1" }, \ | |
57 | { name_str, "Decimator 2", "Decimator 2" }, \ | |
58 | { name_str, "Decimator 3", "Decimator 3" }, \ | |
59 | { name_str, "Decimator 4", "Decimator 4" }, \ | |
60 | { name_str, "ASPRX1", "ASPRX1" }, \ | |
61 | { name_str, "ASPRX2", "ASPRX2" }, \ | |
62 | { name_str, "ASPRX3", "ASPRX3" }, \ | |
63 | { name_str, "ASPRX4", "ASPRX4" }, \ | |
64 | { name_str, "ASPRX5", "ASPRX5" }, \ | |
65 | { name_str, "ASPRX6", "ASPRX6" }, \ | |
66 | { name_str, "DP5RX1", "DP5RX1" }, \ | |
67 | { name_str, "DP5RX2", "DP5RX2" }, \ | |
68 | { name_str, "DP6RX1", "DP6RX1" }, \ | |
69 | { name_str, "DP6RX2", "DP6RX2" }, \ | |
70 | { name_str, "DP7RX1", "DP7RX1" }, \ | |
71 | { name_str, "DP7RX2", "DP7RX2" }, \ | |
72 | { name_str, "ASRC INT1", "ASRC_INT1" }, \ | |
73 | { name_str, "ASRC INT2", "ASRC_INT2" }, \ | |
74 | { name_str, "ASRC INT3", "ASRC_INT3" }, \ | |
75 | { name_str, "ASRC INT4", "ASRC_INT4" }, \ | |
76 | { name_str, "ASRC DEC1", "ASRC_DEC1" }, \ | |
77 | { name_str, "ASRC DEC2", "ASRC_DEC2" }, \ | |
78 | { name_str, "ASRC DEC3", "ASRC_DEC3" }, \ | |
79 | { name_str, "ASRC DEC4", "ASRC_DEC4" }, \ | |
80 | { name_str, "ISRC1 INT1", "ISRC1INT1" }, \ | |
81 | { name_str, "ISRC1 INT2", "ISRC1INT2" }, \ | |
82 | { name_str, "ISRC1 DEC1", "ISRC1DEC1" }, \ | |
83 | { name_str, "ISRC1 DEC2", "ISRC1DEC2" }, \ | |
84 | { name_str, "ISRC2 INT1", "ISRC2INT1" }, \ | |
85 | { name_str, "ISRC2 INT2", "ISRC2INT2" }, \ | |
86 | { name_str, "ISRC2 DEC1", "ISRC2DEC1" }, \ | |
87 | { name_str, "ISRC2 DEC2", "ISRC2DEC2" }, \ | |
88 | { name_str, "EQ1", "EQ" }, \ | |
89 | { name_str, "EQ2", "EQ" } | |
90 | ||
91 | #define CS42L43_MUX_ROUTES(name_str, widget) \ | |
92 | { widget, NULL, name_str " Input" }, \ | |
93 | { name_str " Input", NULL, "Mixer Core" }, \ | |
94 | CS42L43_BASE_ROUTES(name_str " Input") | |
95 | ||
96 | #define CS42L43_MIXER_ROUTES(name_str, widget) \ | |
97 | { name_str " Mixer", NULL, name_str " Input 1" }, \ | |
98 | { name_str " Mixer", NULL, name_str " Input 2" }, \ | |
99 | { name_str " Mixer", NULL, name_str " Input 3" }, \ | |
100 | { name_str " Mixer", NULL, name_str " Input 4" }, \ | |
101 | { widget, NULL, name_str " Mixer" }, \ | |
102 | { name_str " Mixer", NULL, "Mixer Core" }, \ | |
103 | CS42L43_BASE_ROUTES(name_str " Input 1"), \ | |
104 | CS42L43_BASE_ROUTES(name_str " Input 2"), \ | |
105 | CS42L43_BASE_ROUTES(name_str " Input 3"), \ | |
106 | CS42L43_BASE_ROUTES(name_str " Input 4") | |
107 | ||
108 | #define CS42L43_MIXER_VOLUMES(name_str, base) \ | |
109 | SOC_SINGLE_RANGE_TLV(name_str " Input 1 Volume", base, \ | |
110 | CS42L43_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \ | |
111 | cs42l43_mixer_tlv), \ | |
112 | SOC_SINGLE_RANGE_TLV(name_str " Input 2 Volume", base + 4, \ | |
113 | CS42L43_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \ | |
114 | cs42l43_mixer_tlv), \ | |
115 | SOC_SINGLE_RANGE_TLV(name_str " Input 3 Volume", base + 8, \ | |
116 | CS42L43_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \ | |
117 | cs42l43_mixer_tlv), \ | |
118 | SOC_SINGLE_RANGE_TLV(name_str " Input 4 Volume", base + 12, \ | |
119 | CS42L43_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \ | |
120 | cs42l43_mixer_tlv) | |
121 | ||
122 | #define CS42L43_IRQ_ERROR(name) \ | |
123 | static irqreturn_t cs42l43_##name(int irq, void *data) \ | |
124 | { \ | |
125 | struct cs42l43_codec *priv = data; \ | |
126 | dev_err(priv->dev, "Error " #name " IRQ\n"); \ | |
127 | return IRQ_HANDLED; \ | |
128 | } | |
129 | ||
130 | CS42L43_IRQ_ERROR(pll_lost_lock) | |
131 | CS42L43_IRQ_ERROR(spkr_clock_stop) | |
132 | CS42L43_IRQ_ERROR(spkl_clock_stop) | |
133 | CS42L43_IRQ_ERROR(spkr_brown_out) | |
134 | CS42L43_IRQ_ERROR(spkl_brown_out) | |
135 | CS42L43_IRQ_ERROR(spkr_therm_shutdown) | |
136 | CS42L43_IRQ_ERROR(spkl_therm_shutdown) | |
137 | CS42L43_IRQ_ERROR(spkr_therm_warm) | |
138 | CS42L43_IRQ_ERROR(spkl_therm_warm) | |
139 | CS42L43_IRQ_ERROR(spkr_sc_detect) | |
140 | CS42L43_IRQ_ERROR(spkl_sc_detect) | |
141 | CS42L43_IRQ_ERROR(hp_ilimit) | |
142 | ||
143 | #define CS42L43_IRQ_COMPLETE(name) \ | |
144 | static irqreturn_t cs42l43_##name(int irq, void *data) \ | |
145 | { \ | |
146 | struct cs42l43_codec *priv = data; \ | |
147 | dev_dbg(priv->dev, #name " completed\n"); \ | |
148 | complete(&priv->name); \ | |
149 | return IRQ_HANDLED; \ | |
150 | } | |
151 | ||
152 | CS42L43_IRQ_COMPLETE(pll_ready) | |
153 | CS42L43_IRQ_COMPLETE(hp_startup) | |
154 | CS42L43_IRQ_COMPLETE(hp_shutdown) | |
155 | CS42L43_IRQ_COMPLETE(type_detect) | |
156 | CS42L43_IRQ_COMPLETE(spkr_shutdown) | |
157 | CS42L43_IRQ_COMPLETE(spkl_shutdown) | |
158 | CS42L43_IRQ_COMPLETE(spkr_startup) | |
159 | CS42L43_IRQ_COMPLETE(spkl_startup) | |
160 | CS42L43_IRQ_COMPLETE(load_detect) | |
161 | ||
162 | static irqreturn_t cs42l43_mic_shutter(int irq, void *data) | |
163 | { | |
164 | struct cs42l43_codec *priv = data; | |
165 | const char * const controls[] = { | |
166 | "Decimator 1 Switch", | |
167 | "Decimator 2 Switch", | |
168 | "Decimator 3 Switch", | |
169 | "Decimator 4 Switch", | |
170 | }; | |
171 | int i, ret; | |
172 | ||
173 | dev_dbg(priv->dev, "Microphone shutter changed\n"); | |
174 | ||
175 | if (!priv->component) | |
176 | return IRQ_NONE; | |
177 | ||
178 | for (i = 0; i < ARRAY_SIZE(controls); i++) { | |
179 | ret = snd_soc_component_notify_control(priv->component, | |
180 | controls[i]); | |
181 | if (ret) | |
182 | return IRQ_NONE; | |
183 | } | |
184 | ||
185 | return IRQ_HANDLED; | |
186 | } | |
187 | ||
188 | static irqreturn_t cs42l43_spk_shutter(int irq, void *data) | |
189 | { | |
190 | struct cs42l43_codec *priv = data; | |
191 | int ret; | |
192 | ||
193 | dev_dbg(priv->dev, "Speaker shutter changed\n"); | |
194 | ||
195 | if (!priv->component) | |
196 | return IRQ_NONE; | |
197 | ||
198 | ret = snd_soc_component_notify_control(priv->component, | |
199 | "Speaker Digital Switch"); | |
200 | if (ret) | |
201 | return IRQ_NONE; | |
202 | ||
203 | return IRQ_HANDLED; | |
204 | } | |
205 | ||
206 | static const unsigned int cs42l43_sample_rates[] = { | |
207 | 8000, 16000, 24000, 32000, 44100, 48000, 96000, 192000, | |
208 | }; | |
209 | ||
210 | #define CS42L43_CONSUMER_RATE_MASK 0xFF | |
211 | #define CS42L43_PROVIDER_RATE_MASK 0xEF // 44.1k only supported as consumer | |
212 | ||
213 | static const struct snd_pcm_hw_constraint_list cs42l43_constraint = { | |
214 | .count = ARRAY_SIZE(cs42l43_sample_rates), | |
215 | .list = cs42l43_sample_rates, | |
216 | }; | |
217 | ||
218 | static int cs42l43_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) | |
219 | { | |
220 | struct snd_soc_component *component = dai->component; | |
221 | struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); | |
222 | struct cs42l43 *cs42l43 = priv->core; | |
223 | int provider = !!regmap_test_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG2, | |
224 | CS42L43_ASP_MASTER_MODE_MASK); | |
225 | ||
226 | if (provider) | |
227 | priv->constraint.mask = CS42L43_PROVIDER_RATE_MASK; | |
228 | else | |
229 | priv->constraint.mask = CS42L43_CONSUMER_RATE_MASK; | |
230 | ||
231 | return snd_pcm_hw_constraint_list(substream->runtime, 0, | |
232 | SNDRV_PCM_HW_PARAM_RATE, | |
233 | &priv->constraint); | |
234 | } | |
235 | ||
236 | static int cs42l43_convert_sample_rate(unsigned int rate) | |
237 | { | |
238 | switch (rate) { | |
239 | case 8000: | |
240 | return 0x11; | |
241 | case 16000: | |
242 | return 0x12; | |
243 | case 24000: | |
244 | return 0x02; | |
245 | case 32000: | |
246 | return 0x13; | |
247 | case 44100: | |
248 | return 0x0B; | |
249 | case 48000: | |
250 | return 0x03; | |
251 | case 96000: | |
252 | return 0x04; | |
253 | case 192000: | |
254 | return 0x05; | |
255 | default: | |
256 | return -EINVAL; | |
257 | } | |
258 | } | |
259 | ||
260 | static int cs42l43_set_sample_rate(struct snd_pcm_substream *substream, | |
261 | struct snd_pcm_hw_params *params, | |
262 | struct snd_soc_dai *dai) | |
263 | { | |
264 | struct cs42l43_codec *priv = snd_soc_component_get_drvdata(dai->component); | |
265 | struct cs42l43 *cs42l43 = priv->core; | |
266 | int ret; | |
267 | ||
268 | ret = cs42l43_convert_sample_rate(params_rate(params)); | |
269 | if (ret < 0) { | |
270 | dev_err(priv->dev, "Failed to convert sample rate: %d\n", ret); | |
271 | return ret; | |
272 | } | |
273 | ||
274 | //FIXME: For now lets just set sample rate 1, this needs expanded in the future | |
275 | regmap_update_bits(cs42l43->regmap, CS42L43_SAMPLE_RATE1, | |
276 | CS42L43_SAMPLE_RATE_MASK, ret); | |
277 | ||
278 | return 0; | |
279 | } | |
280 | ||
281 | static int cs42l43_asp_hw_params(struct snd_pcm_substream *substream, | |
282 | struct snd_pcm_hw_params *params, | |
283 | struct snd_soc_dai *dai) | |
284 | { | |
285 | struct cs42l43_codec *priv = snd_soc_component_get_drvdata(dai->component); | |
286 | struct cs42l43 *cs42l43 = priv->core; | |
287 | int dsp_mode = !!regmap_test_bits(cs42l43->regmap, CS42L43_ASP_CTRL, | |
288 | CS42L43_ASP_FSYNC_MODE_MASK); | |
289 | int provider = !!regmap_test_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG2, | |
290 | CS42L43_ASP_MASTER_MODE_MASK); | |
291 | int n_chans = params_channels(params); | |
292 | int data_width = params_width(params); | |
293 | int n_slots = n_chans; | |
294 | int slot_width = data_width; | |
295 | int frame, bclk_target, i; | |
296 | unsigned int reg; | |
297 | int *slots; | |
298 | ||
299 | if (priv->n_slots) { | |
300 | n_slots = priv->n_slots; | |
301 | slot_width = priv->slot_width; | |
302 | } | |
303 | ||
304 | if (!dsp_mode && (n_slots & 0x1)) { | |
305 | dev_dbg(priv->dev, "Forcing balanced channels on ASP\n"); | |
306 | n_slots++; | |
307 | } | |
308 | ||
309 | frame = n_slots * slot_width; | |
310 | bclk_target = params_rate(params) * frame; | |
311 | ||
312 | if (provider) { | |
313 | unsigned int gcd_nm = gcd(bclk_target, CS42L43_INTERNAL_SYSCLK); | |
314 | int n = bclk_target / gcd_nm; | |
315 | int m = CS42L43_INTERNAL_SYSCLK / gcd_nm; | |
316 | ||
317 | if (n > (CS42L43_ASP_BCLK_N_MASK >> CS42L43_ASP_BCLK_N_SHIFT) || | |
318 | m > CS42L43_ASP_BCLK_M_MASK) { | |
319 | dev_err(priv->dev, "Can't produce %dHz bclk\n", bclk_target); | |
320 | return -EINVAL; | |
321 | } | |
322 | ||
323 | dev_dbg(priv->dev, "bclk %d/%d = %dHz, with %dx%d frame\n", | |
324 | n, m, bclk_target, n_slots, slot_width); | |
325 | ||
326 | regmap_update_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG1, | |
327 | CS42L43_ASP_BCLK_N_MASK | CS42L43_ASP_BCLK_M_MASK, | |
328 | n << CS42L43_ASP_BCLK_N_SHIFT | | |
329 | m << CS42L43_ASP_BCLK_M_SHIFT); | |
330 | regmap_update_bits(cs42l43->regmap, CS42L43_ASP_FSYNC_CTRL1, | |
331 | CS42L43_ASP_FSYNC_M_MASK, frame); | |
332 | } | |
333 | ||
334 | regmap_update_bits(cs42l43->regmap, CS42L43_ASP_FSYNC_CTRL4, | |
335 | CS42L43_ASP_NUM_BCLKS_PER_FSYNC_MASK, | |
336 | frame << CS42L43_ASP_NUM_BCLKS_PER_FSYNC_SHIFT); | |
337 | ||
338 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { | |
339 | reg = CS42L43_ASP_TX_CH1_CTRL; | |
340 | slots = priv->tx_slots; | |
341 | } else { | |
342 | reg = CS42L43_ASP_RX_CH1_CTRL; | |
343 | slots = priv->rx_slots; | |
344 | } | |
345 | ||
346 | for (i = 0; i < n_chans; i++, reg += 4) { | |
347 | int slot_phase = dsp_mode | (i & CS42L43_ASP_CH_SLOT_PHASE_MASK); | |
348 | int slot_pos; | |
349 | ||
350 | if (dsp_mode) | |
351 | slot_pos = slots[i] * slot_width; | |
352 | else | |
353 | slot_pos = (slots[i] / 2) * slot_width; | |
354 | ||
355 | dev_dbg(priv->dev, "Configure channel %d at slot %d (%d,%d)\n", | |
356 | i, slots[i], slot_pos, slot_phase); | |
357 | ||
358 | regmap_update_bits(cs42l43->regmap, reg, | |
359 | CS42L43_ASP_CH_WIDTH_MASK | | |
360 | CS42L43_ASP_CH_SLOT_MASK | | |
361 | CS42L43_ASP_CH_SLOT_PHASE_MASK, | |
362 | ((data_width - 1) << CS42L43_ASP_CH_WIDTH_SHIFT) | | |
363 | (slot_pos << CS42L43_ASP_CH_SLOT_SHIFT) | | |
364 | slot_phase); | |
365 | } | |
366 | ||
367 | return cs42l43_set_sample_rate(substream, params, dai); | |
368 | } | |
369 | ||
370 | static int cs42l43_asp_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) | |
371 | { | |
372 | struct snd_soc_component *component = dai->component; | |
373 | struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); | |
374 | struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); | |
375 | struct cs42l43 *cs42l43 = priv->core; | |
376 | int provider = regmap_test_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG2, | |
377 | CS42L43_ASP_MASTER_MODE_MASK); | |
378 | struct snd_soc_dapm_route routes[] = { | |
379 | { "BCLK", NULL, "FSYNC" }, | |
380 | }; | |
381 | unsigned int asp_ctrl = 0; | |
382 | unsigned int data_ctrl = 0; | |
383 | unsigned int fsync_ctrl = 0; | |
384 | unsigned int clk_config = 0; | |
385 | ||
386 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
387 | case SND_SOC_DAIFMT_DSP_A: | |
388 | data_ctrl |= 2 << CS42L43_ASP_FSYNC_FRAME_START_DLY_SHIFT; | |
389 | fallthrough; | |
390 | case SND_SOC_DAIFMT_DSP_B: | |
391 | asp_ctrl |= CS42L43_ASP_FSYNC_MODE_MASK; | |
392 | data_ctrl |= CS42L43_ASP_FSYNC_FRAME_START_PHASE_MASK; | |
393 | break; | |
394 | case SND_SOC_DAIFMT_I2S: | |
395 | data_ctrl |= 2 << CS42L43_ASP_FSYNC_FRAME_START_DLY_SHIFT; | |
396 | break; | |
397 | case SND_SOC_DAIFMT_LEFT_J: | |
398 | data_ctrl |= CS42L43_ASP_FSYNC_FRAME_START_PHASE_MASK; | |
399 | break; | |
400 | default: | |
401 | dev_err(priv->dev, "Unsupported DAI format 0x%x\n", | |
402 | fmt & SND_SOC_DAIFMT_FORMAT_MASK); | |
403 | return -EINVAL; | |
404 | } | |
405 | ||
406 | switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { | |
407 | case SND_SOC_DAIFMT_CBC_CFC: | |
408 | if (provider) | |
409 | snd_soc_dapm_del_routes(dapm, routes, ARRAY_SIZE(routes)); | |
410 | break; | |
411 | case SND_SOC_DAIFMT_CBP_CFP: | |
412 | if (!provider) | |
413 | snd_soc_dapm_add_routes(dapm, routes, ARRAY_SIZE(routes)); | |
414 | clk_config |= CS42L43_ASP_MASTER_MODE_MASK; | |
415 | break; | |
416 | default: | |
417 | dev_err(priv->dev, "Unsupported ASP mode 0x%x\n", | |
418 | fmt & SND_SOC_DAIFMT_MASTER_MASK); | |
419 | return -EINVAL; | |
420 | } | |
421 | ||
422 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
423 | case SND_SOC_DAIFMT_NB_NF: | |
424 | clk_config |= CS42L43_ASP_BCLK_INV_MASK; /* Yes BCLK_INV = NB */ | |
425 | break; | |
426 | case SND_SOC_DAIFMT_IB_NF: | |
427 | break; | |
428 | case SND_SOC_DAIFMT_NB_IF: | |
429 | clk_config |= CS42L43_ASP_BCLK_INV_MASK; | |
430 | fsync_ctrl |= CS42L43_ASP_FSYNC_IN_INV_MASK | | |
431 | CS42L43_ASP_FSYNC_OUT_INV_MASK; | |
432 | break; | |
433 | case SND_SOC_DAIFMT_IB_IF: | |
434 | fsync_ctrl |= CS42L43_ASP_FSYNC_IN_INV_MASK | | |
435 | CS42L43_ASP_FSYNC_OUT_INV_MASK; | |
436 | break; | |
437 | default: | |
438 | dev_err(priv->dev, "Unsupported invert mode 0x%x\n", | |
439 | fmt & SND_SOC_DAIFMT_INV_MASK); | |
440 | return -EINVAL; | |
441 | } | |
442 | ||
443 | regmap_update_bits(cs42l43->regmap, CS42L43_ASP_CTRL, | |
444 | CS42L43_ASP_FSYNC_MODE_MASK, | |
445 | asp_ctrl); | |
446 | regmap_update_bits(cs42l43->regmap, CS42L43_ASP_DATA_CTRL, | |
447 | CS42L43_ASP_FSYNC_FRAME_START_DLY_MASK | | |
448 | CS42L43_ASP_FSYNC_FRAME_START_PHASE_MASK, | |
449 | data_ctrl); | |
450 | regmap_update_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG2, | |
451 | CS42L43_ASP_MASTER_MODE_MASK | | |
452 | CS42L43_ASP_BCLK_INV_MASK, | |
453 | clk_config); | |
454 | regmap_update_bits(cs42l43->regmap, CS42L43_ASP_FSYNC_CTRL3, | |
455 | CS42L43_ASP_FSYNC_IN_INV_MASK | | |
456 | CS42L43_ASP_FSYNC_OUT_INV_MASK, | |
457 | fsync_ctrl); | |
458 | ||
459 | return 0; | |
460 | } | |
461 | ||
462 | static void cs42l43_mask_to_slots(struct cs42l43_codec *priv, unsigned int mask, int *slots) | |
463 | { | |
464 | int i; | |
465 | ||
466 | for (i = 0; i < CS42L43_ASP_MAX_CHANNELS; ++i) { | |
467 | int slot = ffs(mask) - 1; | |
468 | ||
469 | if (slot < 0) | |
470 | return; | |
471 | ||
472 | slots[i] = slot; | |
473 | ||
474 | mask &= ~(1 << slot); | |
475 | } | |
476 | ||
477 | if (mask) | |
478 | dev_warn(priv->dev, "Too many channels in TDM mask\n"); | |
479 | } | |
480 | ||
481 | static int cs42l43_asp_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, | |
482 | unsigned int rx_mask, int slots, int slot_width) | |
483 | { | |
484 | struct snd_soc_component *component = dai->component; | |
485 | struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); | |
486 | ||
487 | priv->n_slots = slots; | |
488 | priv->slot_width = slot_width; | |
489 | ||
490 | if (!slots) { | |
491 | tx_mask = CS42L43_DEFAULT_SLOTS; | |
492 | rx_mask = CS42L43_DEFAULT_SLOTS; | |
493 | } | |
494 | ||
495 | cs42l43_mask_to_slots(priv, tx_mask, priv->tx_slots); | |
496 | cs42l43_mask_to_slots(priv, rx_mask, priv->rx_slots); | |
497 | ||
498 | return 0; | |
499 | } | |
500 | ||
501 | static const struct snd_soc_dai_ops cs42l43_asp_ops = { | |
502 | .startup = cs42l43_startup, | |
503 | .hw_params = cs42l43_asp_hw_params, | |
504 | .set_fmt = cs42l43_asp_set_fmt, | |
505 | .set_tdm_slot = cs42l43_asp_set_tdm_slot, | |
506 | }; | |
507 | ||
508 | static int cs42l43_sdw_hw_params(struct snd_pcm_substream *substream, | |
509 | struct snd_pcm_hw_params *params, | |
510 | struct snd_soc_dai *dai) | |
511 | { | |
512 | int ret; | |
513 | ||
514 | ret = cs42l43_sdw_add_peripheral(substream, params, dai); | |
515 | if (ret) | |
516 | return ret; | |
517 | ||
518 | return cs42l43_set_sample_rate(substream, params, dai); | |
519 | }; | |
520 | ||
521 | static const struct snd_soc_dai_ops cs42l43_sdw_ops = { | |
522 | .startup = cs42l43_startup, | |
523 | .set_stream = cs42l43_sdw_set_stream, | |
524 | .hw_params = cs42l43_sdw_hw_params, | |
525 | .hw_free = cs42l43_sdw_remove_peripheral, | |
526 | }; | |
527 | ||
528 | #define CS42L43_ASP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \ | |
529 | SNDRV_PCM_FMTBIT_S32_LE) | |
530 | #define CS42L43_SDW_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) | |
531 | ||
532 | static struct snd_soc_dai_driver cs42l43_dais[] = { | |
533 | { | |
534 | .name = "cs42l43-asp", | |
535 | .ops = &cs42l43_asp_ops, | |
536 | .symmetric_rate = 1, | |
537 | .capture = { | |
538 | .stream_name = "ASP Capture", | |
539 | .channels_min = 1, | |
540 | .channels_max = CS42L43_ASP_MAX_CHANNELS, | |
541 | .rates = SNDRV_PCM_RATE_KNOT, | |
542 | .formats = CS42L43_ASP_FORMATS, | |
543 | }, | |
544 | .playback = { | |
545 | .stream_name = "ASP Playback", | |
546 | .channels_min = 1, | |
547 | .channels_max = CS42L43_ASP_MAX_CHANNELS, | |
548 | .rates = SNDRV_PCM_RATE_KNOT, | |
549 | .formats = CS42L43_ASP_FORMATS, | |
550 | }, | |
551 | }, | |
552 | { | |
553 | .name = "cs42l43-dp1", | |
554 | .id = 1, | |
555 | .ops = &cs42l43_sdw_ops, | |
556 | .capture = { | |
557 | .stream_name = "DP1 Capture", | |
558 | .channels_min = 1, | |
559 | .channels_max = 4, | |
560 | .rates = SNDRV_PCM_RATE_KNOT, | |
561 | .formats = CS42L43_SDW_FORMATS, | |
562 | }, | |
563 | }, | |
564 | { | |
565 | .name = "cs42l43-dp2", | |
566 | .id = 2, | |
567 | .ops = &cs42l43_sdw_ops, | |
568 | .capture = { | |
569 | .stream_name = "DP2 Capture", | |
570 | .channels_min = 1, | |
571 | .channels_max = 2, | |
572 | .rates = SNDRV_PCM_RATE_KNOT, | |
573 | .formats = CS42L43_SDW_FORMATS, | |
574 | }, | |
575 | }, | |
576 | { | |
577 | .name = "cs42l43-dp3", | |
578 | .id = 3, | |
579 | .ops = &cs42l43_sdw_ops, | |
580 | .capture = { | |
581 | .stream_name = "DP3 Capture", | |
582 | .channels_min = 1, | |
583 | .channels_max = 2, | |
584 | .rates = SNDRV_PCM_RATE_KNOT, | |
585 | .formats = CS42L43_SDW_FORMATS, | |
586 | }, | |
587 | }, | |
588 | { | |
589 | .name = "cs42l43-dp4", | |
590 | .id = 4, | |
591 | .ops = &cs42l43_sdw_ops, | |
592 | .capture = { | |
593 | .stream_name = "DP4 Capture", | |
594 | .channels_min = 1, | |
595 | .channels_max = 2, | |
596 | .rates = SNDRV_PCM_RATE_KNOT, | |
597 | .formats = CS42L43_SDW_FORMATS, | |
598 | }, | |
599 | }, | |
600 | { | |
601 | .name = "cs42l43-dp5", | |
602 | .id = 5, | |
603 | .ops = &cs42l43_sdw_ops, | |
604 | .playback = { | |
605 | .stream_name = "DP5 Playback", | |
606 | .channels_min = 1, | |
607 | .channels_max = 2, | |
608 | .rates = SNDRV_PCM_RATE_KNOT, | |
609 | .formats = CS42L43_SDW_FORMATS, | |
610 | }, | |
611 | }, | |
612 | { | |
613 | .name = "cs42l43-dp6", | |
614 | .id = 6, | |
615 | .ops = &cs42l43_sdw_ops, | |
616 | .playback = { | |
617 | .stream_name = "DP6 Playback", | |
618 | .channels_min = 1, | |
619 | .channels_max = 2, | |
620 | .rates = SNDRV_PCM_RATE_KNOT, | |
621 | .formats = CS42L43_SDW_FORMATS, | |
622 | }, | |
623 | }, | |
624 | { | |
625 | .name = "cs42l43-dp7", | |
626 | .id = 7, | |
627 | .ops = &cs42l43_sdw_ops, | |
628 | .playback = { | |
629 | .stream_name = "DP7 Playback", | |
630 | .channels_min = 1, | |
631 | .channels_max = 2, | |
632 | .rates = SNDRV_PCM_RATE_KNOT, | |
633 | .formats = CS42L43_SDW_FORMATS, | |
634 | }, | |
635 | }, | |
636 | }; | |
637 | ||
638 | static const DECLARE_TLV_DB_SCALE(cs42l43_mixer_tlv, -3200, 100, 0); | |
639 | ||
640 | static const char * const cs42l43_ramp_text[] = { | |
641 | "0ms/6dB", "0.5ms/6dB", "1ms/6dB", "2ms/6dB", "4ms/6dB", "8ms/6dB", | |
642 | "15ms/6dB", "30ms/6dB", | |
643 | }; | |
644 | ||
645 | static const char * const cs42l43_adc1_input_text[] = { "IN1", "IN2" }; | |
646 | ||
647 | static SOC_ENUM_SINGLE_DECL(cs42l43_adc1_input, CS42L43_ADC_B_CTRL1, | |
648 | CS42L43_ADC_AIN_SEL_SHIFT, | |
649 | cs42l43_adc1_input_text); | |
650 | ||
651 | static const struct snd_kcontrol_new cs42l43_adc1_input_ctl = | |
652 | SOC_DAPM_ENUM("ADC1 Input", cs42l43_adc1_input); | |
653 | ||
654 | static const char * const cs42l43_dec_mode_text[] = { "ADC", "PDM" }; | |
655 | ||
656 | static SOC_ENUM_SINGLE_VIRT_DECL(cs42l43_dec1_mode, cs42l43_dec_mode_text); | |
657 | static SOC_ENUM_SINGLE_VIRT_DECL(cs42l43_dec2_mode, cs42l43_dec_mode_text); | |
658 | ||
659 | static const struct snd_kcontrol_new cs42l43_dec_mode_ctl[] = { | |
660 | SOC_DAPM_ENUM("Decimator 1 Mode", cs42l43_dec1_mode), | |
661 | SOC_DAPM_ENUM("Decimator 2 Mode", cs42l43_dec2_mode), | |
662 | }; | |
663 | ||
664 | static const char * const cs42l43_pdm_clk_text[] = { | |
665 | "3.072MHz", "1.536MHz", "768kHz", | |
666 | }; | |
667 | ||
668 | static SOC_ENUM_SINGLE_DECL(cs42l43_pdm1_clk, CS42L43_PDM_CONTROL, | |
669 | CS42L43_PDM1_CLK_DIV_SHIFT, cs42l43_pdm_clk_text); | |
670 | static SOC_ENUM_SINGLE_DECL(cs42l43_pdm2_clk, CS42L43_PDM_CONTROL, | |
671 | CS42L43_PDM2_CLK_DIV_SHIFT, cs42l43_pdm_clk_text); | |
672 | ||
673 | static DECLARE_TLV_DB_SCALE(cs42l43_adc_tlv, -600, 600, 0); | |
674 | static DECLARE_TLV_DB_SCALE(cs42l43_dec_tlv, -6400, 50, 0); | |
675 | ||
676 | static const char * const cs42l43_wnf_corner_text[] = { | |
677 | "160Hz", "180Hz", "200Hz", "220Hz", "240Hz", "260Hz", "280Hz", "300Hz", | |
678 | }; | |
679 | ||
680 | static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL1, | |
681 | CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text); | |
682 | static SOC_ENUM_SINGLE_DECL(cs42l43_dec2_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL2, | |
683 | CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text); | |
684 | static SOC_ENUM_SINGLE_DECL(cs42l43_dec3_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL3, | |
685 | CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text); | |
686 | static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_wnf_corner, CS42L43_DECIM_HPF_WNF_CTRL4, | |
687 | CS42L43_DECIM_WNF_CF_SHIFT, cs42l43_wnf_corner_text); | |
688 | ||
689 | static const char * const cs42l43_hpf_corner_text[] = { | |
690 | "3Hz", "12Hz", "48Hz", "96Hz", | |
691 | }; | |
692 | ||
693 | static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL1, | |
694 | CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text); | |
695 | static SOC_ENUM_SINGLE_DECL(cs42l43_dec2_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL2, | |
696 | CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text); | |
697 | static SOC_ENUM_SINGLE_DECL(cs42l43_dec3_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL3, | |
698 | CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text); | |
699 | static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_hpf_corner, CS42L43_DECIM_HPF_WNF_CTRL4, | |
700 | CS42L43_DECIM_HPF_CF_SHIFT, cs42l43_hpf_corner_text); | |
701 | ||
702 | static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_ramp_up, CS42L43_DECIM_VOL_CTRL_CH1_CH2, | |
703 | CS42L43_DECIM1_VI_RAMP_SHIFT, cs42l43_ramp_text); | |
704 | static SOC_ENUM_SINGLE_DECL(cs42l43_dec1_ramp_down, CS42L43_DECIM_VOL_CTRL_CH1_CH2, | |
705 | CS42L43_DECIM1_VD_RAMP_SHIFT, cs42l43_ramp_text); | |
706 | static SOC_ENUM_SINGLE_DECL(cs42l43_dec2_ramp_up, CS42L43_DECIM_VOL_CTRL_CH1_CH2, | |
707 | CS42L43_DECIM2_VI_RAMP_SHIFT, cs42l43_ramp_text); | |
708 | static SOC_ENUM_SINGLE_DECL(cs42l43_dec2_ramp_down, CS42L43_DECIM_VOL_CTRL_CH1_CH2, | |
709 | CS42L43_DECIM2_VD_RAMP_SHIFT, cs42l43_ramp_text); | |
710 | static SOC_ENUM_SINGLE_DECL(cs42l43_dec3_ramp_up, CS42L43_DECIM_VOL_CTRL_CH3_CH4, | |
711 | CS42L43_DECIM3_VI_RAMP_SHIFT, cs42l43_ramp_text); | |
712 | static SOC_ENUM_SINGLE_DECL(cs42l43_dec3_ramp_down, CS42L43_DECIM_VOL_CTRL_CH3_CH4, | |
713 | CS42L43_DECIM3_VD_RAMP_SHIFT, cs42l43_ramp_text); | |
714 | static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_ramp_up, CS42L43_DECIM_VOL_CTRL_CH3_CH4, | |
715 | CS42L43_DECIM4_VI_RAMP_SHIFT, cs42l43_ramp_text); | |
716 | static SOC_ENUM_SINGLE_DECL(cs42l43_dec4_ramp_down, CS42L43_DECIM_VOL_CTRL_CH3_CH4, | |
717 | CS42L43_DECIM4_VD_RAMP_SHIFT, cs42l43_ramp_text); | |
718 | ||
719 | static DECLARE_TLV_DB_SCALE(cs42l43_speaker_tlv, -6400, 50, 0); | |
720 | ||
721 | static SOC_ENUM_SINGLE_DECL(cs42l43_speaker_ramp_up, CS42L43_AMP1_2_VOL_RAMP, | |
722 | CS42L43_AMP1_2_VI_RAMP_SHIFT, cs42l43_ramp_text); | |
723 | ||
724 | static SOC_ENUM_SINGLE_DECL(cs42l43_speaker_ramp_down, CS42L43_AMP1_2_VOL_RAMP, | |
725 | CS42L43_AMP1_2_VD_RAMP_SHIFT, cs42l43_ramp_text); | |
726 | ||
727 | static DECLARE_TLV_DB_SCALE(cs42l43_headphone_tlv, -11450, 50, 1); | |
728 | ||
729 | static const char * const cs42l43_headphone_ramp_text[] = { | |
730 | "1", "2", "4", "6", "8", "11", "12", "16", "22", "24", "33", "36", "44", | |
731 | "48", "66", "72", | |
732 | }; | |
733 | ||
734 | static SOC_ENUM_SINGLE_DECL(cs42l43_headphone_ramp, CS42L43_PGAVOL, | |
735 | CS42L43_HP_PATH_VOL_RAMP_SHIFT, | |
736 | cs42l43_headphone_ramp_text); | |
737 | ||
738 | static const char * const cs42l43_tone_freq_text[] = { | |
739 | "1kHz", "2kHz", "4kHz", "6kHz", "8kHz", | |
740 | }; | |
741 | ||
742 | static SOC_ENUM_SINGLE_DECL(cs42l43_tone1_freq, CS42L43_TONE_CH1_CTRL, | |
743 | CS42L43_TONE_FREQ_SHIFT, cs42l43_tone_freq_text); | |
744 | ||
745 | static SOC_ENUM_SINGLE_DECL(cs42l43_tone2_freq, CS42L43_TONE_CH2_CTRL, | |
746 | CS42L43_TONE_FREQ_SHIFT, cs42l43_tone_freq_text); | |
747 | ||
748 | static const char * const cs42l43_mixer_texts[] = { | |
749 | "None", | |
750 | "Tone Generator 1", "Tone Generator 2", | |
751 | "Decimator 1", "Decimator 2", "Decimator 3", "Decimator 4", | |
752 | "ASPRX1", "ASPRX2", "ASPRX3", "ASPRX4", "ASPRX5", "ASPRX6", | |
753 | "DP5RX1", "DP5RX2", "DP6RX1", "DP6RX2", "DP7RX1", "DP7RX2", | |
754 | "ASRC INT1", "ASRC INT2", "ASRC INT3", "ASRC INT4", | |
755 | "ASRC DEC1", "ASRC DEC2", "ASRC DEC3", "ASRC DEC4", | |
756 | "ISRC1 INT1", "ISRC1 INT2", | |
757 | "ISRC1 DEC1", "ISRC1 DEC2", | |
758 | "ISRC2 INT1", "ISRC2 INT2", | |
759 | "ISRC2 DEC1", "ISRC2 DEC2", | |
760 | "EQ1", "EQ2", | |
761 | }; | |
762 | ||
763 | static const unsigned int cs42l43_mixer_values[] = { | |
764 | 0x00, // None | |
765 | 0x04, 0x05, // Tone Generator 1, 2 | |
766 | 0x10, 0x11, 0x12, 0x13, // Decimator 1, 2, 3, 4 | |
767 | 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, // ASPRX1,2,3,4,5,6 | |
768 | 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, // DP5, 6, 7RX1, 2 | |
769 | 0x40, 0x41, 0x42, 0x43, // ASRC INT1, 2, 3, 4 | |
770 | 0x44, 0x45, 0x46, 0x47, // ASRC DEC1, 2, 3, 4 | |
771 | 0x50, 0x51, // ISRC1 INT1, 2 | |
772 | 0x52, 0x53, // ISRC1 DEC1, 2 | |
773 | 0x54, 0x55, // ISRC2 INT1, 2 | |
774 | 0x56, 0x57, // ISRC2 DEC1, 2 | |
775 | 0x58, 0x59, // EQ1, 2 | |
776 | }; | |
777 | ||
778 | CS42L43_DECL_MUX(asptx1, CS42L43_ASPTX1_INPUT); | |
779 | CS42L43_DECL_MUX(asptx2, CS42L43_ASPTX2_INPUT); | |
780 | CS42L43_DECL_MUX(asptx3, CS42L43_ASPTX3_INPUT); | |
781 | CS42L43_DECL_MUX(asptx4, CS42L43_ASPTX4_INPUT); | |
782 | CS42L43_DECL_MUX(asptx5, CS42L43_ASPTX5_INPUT); | |
783 | CS42L43_DECL_MUX(asptx6, CS42L43_ASPTX6_INPUT); | |
784 | ||
785 | CS42L43_DECL_MUX(dp1tx1, CS42L43_SWIRE_DP1_CH1_INPUT); | |
786 | CS42L43_DECL_MUX(dp1tx2, CS42L43_SWIRE_DP1_CH2_INPUT); | |
787 | CS42L43_DECL_MUX(dp1tx3, CS42L43_SWIRE_DP1_CH3_INPUT); | |
788 | CS42L43_DECL_MUX(dp1tx4, CS42L43_SWIRE_DP1_CH4_INPUT); | |
789 | CS42L43_DECL_MUX(dp2tx1, CS42L43_SWIRE_DP2_CH1_INPUT); | |
790 | CS42L43_DECL_MUX(dp2tx2, CS42L43_SWIRE_DP2_CH2_INPUT); | |
791 | CS42L43_DECL_MUX(dp3tx1, CS42L43_SWIRE_DP3_CH1_INPUT); | |
792 | CS42L43_DECL_MUX(dp3tx2, CS42L43_SWIRE_DP3_CH2_INPUT); | |
793 | CS42L43_DECL_MUX(dp4tx1, CS42L43_SWIRE_DP4_CH1_INPUT); | |
794 | CS42L43_DECL_MUX(dp4tx2, CS42L43_SWIRE_DP4_CH2_INPUT); | |
795 | ||
796 | CS42L43_DECL_MUX(asrcint1, CS42L43_ASRC_INT1_INPUT1); | |
797 | CS42L43_DECL_MUX(asrcint2, CS42L43_ASRC_INT2_INPUT1); | |
798 | CS42L43_DECL_MUX(asrcint3, CS42L43_ASRC_INT3_INPUT1); | |
799 | CS42L43_DECL_MUX(asrcint4, CS42L43_ASRC_INT4_INPUT1); | |
800 | CS42L43_DECL_MUX(asrcdec1, CS42L43_ASRC_DEC1_INPUT1); | |
801 | CS42L43_DECL_MUX(asrcdec2, CS42L43_ASRC_DEC2_INPUT1); | |
802 | CS42L43_DECL_MUX(asrcdec3, CS42L43_ASRC_DEC3_INPUT1); | |
803 | CS42L43_DECL_MUX(asrcdec4, CS42L43_ASRC_DEC4_INPUT1); | |
804 | ||
805 | CS42L43_DECL_MUX(isrc1int1, CS42L43_ISRC1INT1_INPUT1); | |
806 | CS42L43_DECL_MUX(isrc1int2, CS42L43_ISRC1INT2_INPUT1); | |
807 | CS42L43_DECL_MUX(isrc1dec1, CS42L43_ISRC1DEC1_INPUT1); | |
808 | CS42L43_DECL_MUX(isrc1dec2, CS42L43_ISRC1DEC2_INPUT1); | |
809 | CS42L43_DECL_MUX(isrc2int1, CS42L43_ISRC2INT1_INPUT1); | |
810 | CS42L43_DECL_MUX(isrc2int2, CS42L43_ISRC2INT2_INPUT1); | |
811 | CS42L43_DECL_MUX(isrc2dec1, CS42L43_ISRC2DEC1_INPUT1); | |
812 | CS42L43_DECL_MUX(isrc2dec2, CS42L43_ISRC2DEC2_INPUT1); | |
813 | ||
814 | CS42L43_DECL_MUX(spdif1, CS42L43_SPDIF1_INPUT1); | |
815 | CS42L43_DECL_MUX(spdif2, CS42L43_SPDIF2_INPUT1); | |
816 | ||
817 | CS42L43_DECL_MIXER(eq1, CS42L43_EQ1MIX_INPUT1); | |
818 | CS42L43_DECL_MIXER(eq2, CS42L43_EQ2MIX_INPUT1); | |
819 | ||
820 | CS42L43_DECL_MIXER(amp1, CS42L43_AMP1MIX_INPUT1); | |
821 | CS42L43_DECL_MIXER(amp2, CS42L43_AMP2MIX_INPUT1); | |
822 | ||
823 | CS42L43_DECL_MIXER(amp3, CS42L43_AMP3MIX_INPUT1); | |
824 | CS42L43_DECL_MIXER(amp4, CS42L43_AMP4MIX_INPUT1); | |
825 | ||
826 | static int cs42l43_dapm_get_volsw(struct snd_kcontrol *kcontrol, | |
827 | struct snd_ctl_elem_value *ucontrol) | |
828 | { | |
829 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); | |
830 | struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); | |
831 | int ret; | |
832 | ||
833 | snd_soc_dapm_mutex_lock(dapm); | |
834 | ret = snd_soc_get_volsw(kcontrol, ucontrol); | |
835 | snd_soc_dapm_mutex_unlock(dapm); | |
836 | ||
837 | return ret; | |
838 | } | |
839 | ||
840 | static int cs42l43_dapm_put_volsw(struct snd_kcontrol *kcontrol, | |
841 | struct snd_ctl_elem_value *ucontrol) | |
842 | { | |
843 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); | |
844 | struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); | |
845 | int ret; | |
846 | ||
847 | snd_soc_dapm_mutex_lock(dapm); | |
848 | ret = snd_soc_put_volsw(kcontrol, ucontrol); | |
849 | snd_soc_dapm_mutex_unlock(dapm); | |
850 | ||
851 | return ret; | |
852 | } | |
853 | ||
854 | static int cs42l43_dapm_get_enum(struct snd_kcontrol *kcontrol, | |
855 | struct snd_ctl_elem_value *ucontrol) | |
856 | { | |
857 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); | |
858 | struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); | |
859 | int ret; | |
860 | ||
861 | snd_soc_dapm_mutex_lock(dapm); | |
862 | ret = snd_soc_get_enum_double(kcontrol, ucontrol); | |
863 | snd_soc_dapm_mutex_unlock(dapm); | |
864 | ||
865 | return ret; | |
866 | } | |
867 | ||
868 | static int cs42l43_dapm_put_enum(struct snd_kcontrol *kcontrol, | |
869 | struct snd_ctl_elem_value *ucontrol) | |
870 | { | |
871 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); | |
872 | struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); | |
873 | int ret; | |
874 | ||
875 | snd_soc_dapm_mutex_lock(dapm); | |
876 | ret = snd_soc_put_enum_double(kcontrol, ucontrol); | |
877 | snd_soc_dapm_mutex_unlock(dapm); | |
878 | ||
879 | return ret; | |
880 | } | |
881 | ||
882 | static int cs42l43_eq_get(struct snd_kcontrol *kcontrol, | |
883 | struct snd_ctl_elem_value *ucontrol) | |
884 | { | |
885 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); | |
886 | struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); | |
887 | ||
888 | memcpy(ucontrol->value.integer.value, priv->eq_coeffs, sizeof(priv->eq_coeffs)); | |
889 | ||
890 | return 0; | |
891 | } | |
892 | ||
893 | static int cs42l43_eq_put(struct snd_kcontrol *kcontrol, | |
894 | struct snd_ctl_elem_value *ucontrol) | |
895 | { | |
896 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); | |
897 | struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); | |
898 | struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); | |
899 | ||
900 | snd_soc_dapm_mutex_lock(dapm); | |
901 | ||
902 | memcpy(priv->eq_coeffs, ucontrol->value.integer.value, sizeof(priv->eq_coeffs)); | |
903 | ||
904 | snd_soc_dapm_mutex_unlock(dapm); | |
905 | ||
906 | return 0; | |
907 | } | |
908 | ||
909 | static void cs42l43_spk_vu_sync(struct cs42l43_codec *priv) | |
910 | { | |
911 | struct cs42l43 *cs42l43 = priv->core; | |
912 | ||
913 | mutex_lock(&priv->spk_vu_lock); | |
914 | ||
915 | regmap_update_bits(cs42l43->regmap, CS42L43_INTP_VOLUME_CTRL1, | |
916 | CS42L43_AMP1_2_VU_MASK, CS42L43_AMP1_2_VU_MASK); | |
917 | regmap_update_bits(cs42l43->regmap, CS42L43_INTP_VOLUME_CTRL1, | |
918 | CS42L43_AMP1_2_VU_MASK, 0); | |
919 | ||
920 | mutex_unlock(&priv->spk_vu_lock); | |
921 | } | |
922 | ||
923 | static int cs42l43_shutter_get(struct cs42l43_codec *priv, unsigned int shift) | |
924 | { | |
925 | struct cs42l43 *cs42l43 = priv->core; | |
926 | unsigned int val; | |
927 | int ret; | |
928 | ||
929 | ret = pm_runtime_resume_and_get(priv->dev); | |
930 | if (ret) { | |
931 | dev_err(priv->dev, "Failed to resume for shutters: %d\n", ret); | |
932 | return ret; | |
933 | } | |
934 | ||
935 | /* | |
936 | * SHUTTER_CONTROL is a mix of volatile and non-volatile bits, so must | |
937 | * be cached for the non-volatiles, so drop it from the cache here so | |
938 | * we force a read. | |
939 | */ | |
940 | ret = regcache_drop_region(cs42l43->regmap, CS42L43_SHUTTER_CONTROL, | |
941 | CS42L43_SHUTTER_CONTROL); | |
942 | if (ret) { | |
943 | dev_err(priv->dev, "Failed to drop shutter from cache: %d\n", ret); | |
944 | goto error; | |
945 | } | |
946 | ||
947 | ret = regmap_read(cs42l43->regmap, CS42L43_SHUTTER_CONTROL, &val); | |
948 | if (ret) { | |
949 | dev_err(priv->dev, "Failed to check shutter status: %d\n", ret); | |
950 | goto error; | |
951 | } | |
952 | ||
953 | ret = !(val & BIT(shift)); | |
954 | ||
955 | dev_dbg(priv->dev, "%s shutter is %s\n", | |
956 | BIT(shift) == CS42L43_STATUS_MIC_SHUTTER_MUTE_MASK ? "Mic" : "Speaker", | |
957 | ret ? "open" : "closed"); | |
958 | ||
959 | error: | |
960 | pm_runtime_mark_last_busy(priv->dev); | |
961 | pm_runtime_put_autosuspend(priv->dev); | |
962 | ||
963 | return ret; | |
964 | } | |
965 | ||
966 | static int cs42l43_decim_get(struct snd_kcontrol *kcontrol, | |
967 | struct snd_ctl_elem_value *ucontrol) | |
968 | { | |
969 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); | |
970 | struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); | |
971 | int ret; | |
972 | ||
973 | ret = cs42l43_shutter_get(priv, CS42L43_STATUS_MIC_SHUTTER_MUTE_SHIFT); | |
974 | if (ret < 0) | |
975 | return ret; | |
976 | else if (!ret) | |
977 | ucontrol->value.integer.value[0] = ret; | |
978 | else | |
979 | ret = cs42l43_dapm_get_volsw(kcontrol, ucontrol); | |
980 | ||
981 | return ret; | |
982 | } | |
983 | ||
984 | static int cs42l43_spk_get(struct snd_kcontrol *kcontrol, | |
985 | struct snd_ctl_elem_value *ucontrol) | |
986 | { | |
987 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); | |
988 | struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); | |
989 | int ret; | |
990 | ||
991 | ret = cs42l43_shutter_get(priv, CS42L43_STATUS_SPK_SHUTTER_MUTE_SHIFT); | |
992 | if (ret < 0) | |
993 | return ret; | |
994 | else if (!ret) | |
995 | ucontrol->value.integer.value[0] = ret; | |
996 | else | |
997 | ret = snd_soc_get_volsw(kcontrol, ucontrol); | |
998 | ||
999 | return ret; | |
1000 | } | |
1001 | ||
1002 | static int cs42l43_spk_put(struct snd_kcontrol *kcontrol, | |
1003 | struct snd_ctl_elem_value *ucontrol) | |
1004 | { | |
1005 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); | |
1006 | struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); | |
1007 | int ret; | |
1008 | ||
1009 | ret = snd_soc_put_volsw(kcontrol, ucontrol); | |
1010 | if (ret > 0) | |
1011 | cs42l43_spk_vu_sync(priv); | |
1012 | ||
1013 | return ret; | |
1014 | } | |
1015 | ||
1016 | static const struct snd_kcontrol_new cs42l43_controls[] = { | |
1017 | SOC_ENUM_EXT("Jack Override", cs42l43_jack_enum, | |
1018 | cs42l43_jack_get, cs42l43_jack_put), | |
1019 | ||
1020 | SOC_DOUBLE_R_SX_TLV("ADC Volume", CS42L43_ADC_B_CTRL1, CS42L43_ADC_B_CTRL2, | |
1021 | CS42L43_ADC_PGA_GAIN_SHIFT, | |
1022 | 0xF, 5, cs42l43_adc_tlv), | |
1023 | ||
1024 | SOC_DOUBLE("PDM1 Invert Switch", CS42L43_DMIC_PDM_CTRL, | |
1025 | CS42L43_PDM1L_INV_SHIFT, CS42L43_PDM1R_INV_SHIFT, 1, 0), | |
1026 | SOC_DOUBLE("PDM2 Invert Switch", CS42L43_DMIC_PDM_CTRL, | |
1027 | CS42L43_PDM2L_INV_SHIFT, CS42L43_PDM2R_INV_SHIFT, 1, 0), | |
1028 | SOC_ENUM("PDM1 Clock", cs42l43_pdm1_clk), | |
1029 | SOC_ENUM("PDM2 Clock", cs42l43_pdm2_clk), | |
1030 | ||
1031 | SOC_SINGLE("Decimator 1 WNF Switch", CS42L43_DECIM_HPF_WNF_CTRL1, | |
1032 | CS42L43_DECIM_WNF_EN_SHIFT, 1, 0), | |
1033 | SOC_SINGLE("Decimator 2 WNF Switch", CS42L43_DECIM_HPF_WNF_CTRL2, | |
1034 | CS42L43_DECIM_WNF_EN_SHIFT, 1, 0), | |
1035 | SOC_SINGLE("Decimator 3 WNF Switch", CS42L43_DECIM_HPF_WNF_CTRL3, | |
1036 | CS42L43_DECIM_WNF_EN_SHIFT, 1, 0), | |
1037 | SOC_SINGLE("Decimator 4 WNF Switch", CS42L43_DECIM_HPF_WNF_CTRL4, | |
1038 | CS42L43_DECIM_WNF_EN_SHIFT, 1, 0), | |
1039 | ||
1040 | SOC_ENUM("Decimator 1 WNF Corner Frequency", cs42l43_dec1_wnf_corner), | |
1041 | SOC_ENUM("Decimator 2 WNF Corner Frequency", cs42l43_dec2_wnf_corner), | |
1042 | SOC_ENUM("Decimator 3 WNF Corner Frequency", cs42l43_dec3_wnf_corner), | |
1043 | SOC_ENUM("Decimator 4 WNF Corner Frequency", cs42l43_dec4_wnf_corner), | |
1044 | ||
1045 | SOC_SINGLE("Decimator 1 HPF Switch", CS42L43_DECIM_HPF_WNF_CTRL1, | |
1046 | CS42L43_DECIM_HPF_EN_SHIFT, 1, 0), | |
1047 | SOC_SINGLE("Decimator 2 HPF Switch", CS42L43_DECIM_HPF_WNF_CTRL2, | |
1048 | CS42L43_DECIM_HPF_EN_SHIFT, 1, 0), | |
1049 | SOC_SINGLE("Decimator 3 HPF Switch", CS42L43_DECIM_HPF_WNF_CTRL3, | |
1050 | CS42L43_DECIM_HPF_EN_SHIFT, 1, 0), | |
1051 | SOC_SINGLE("Decimator 4 HPF Switch", CS42L43_DECIM_HPF_WNF_CTRL4, | |
1052 | CS42L43_DECIM_HPF_EN_SHIFT, 1, 0), | |
1053 | ||
1054 | SOC_ENUM("Decimator 1 HPF Corner Frequency", cs42l43_dec1_hpf_corner), | |
1055 | SOC_ENUM("Decimator 2 HPF Corner Frequency", cs42l43_dec2_hpf_corner), | |
1056 | SOC_ENUM("Decimator 3 HPF Corner Frequency", cs42l43_dec3_hpf_corner), | |
1057 | SOC_ENUM("Decimator 4 HPF Corner Frequency", cs42l43_dec4_hpf_corner), | |
1058 | ||
1059 | SOC_SINGLE_TLV("Decimator 1 Volume", CS42L43_DECIM_VOL_CTRL_CH1_CH2, | |
1060 | CS42L43_DECIM1_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), | |
1061 | SOC_SINGLE_EXT("Decimator 1 Switch", CS42L43_DECIM_VOL_CTRL_CH1_CH2, | |
1062 | CS42L43_DECIM1_MUTE_SHIFT, 1, 1, | |
1063 | cs42l43_decim_get, cs42l43_dapm_put_volsw), | |
1064 | SOC_SINGLE_TLV("Decimator 2 Volume", CS42L43_DECIM_VOL_CTRL_CH1_CH2, | |
1065 | CS42L43_DECIM2_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), | |
1066 | SOC_SINGLE_EXT("Decimator 2 Switch", CS42L43_DECIM_VOL_CTRL_CH1_CH2, | |
1067 | CS42L43_DECIM2_MUTE_SHIFT, 1, 1, | |
1068 | cs42l43_decim_get, cs42l43_dapm_put_volsw), | |
1069 | SOC_SINGLE_TLV("Decimator 3 Volume", CS42L43_DECIM_VOL_CTRL_CH3_CH4, | |
1070 | CS42L43_DECIM3_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), | |
1071 | SOC_SINGLE_EXT("Decimator 3 Switch", CS42L43_DECIM_VOL_CTRL_CH3_CH4, | |
1072 | CS42L43_DECIM3_MUTE_SHIFT, 1, 1, | |
1073 | cs42l43_decim_get, cs42l43_dapm_put_volsw), | |
1074 | SOC_SINGLE_TLV("Decimator 4 Volume", CS42L43_DECIM_VOL_CTRL_CH3_CH4, | |
1075 | CS42L43_DECIM4_VOL_SHIFT, 0xBF, 0, cs42l43_dec_tlv), | |
1076 | SOC_SINGLE_EXT("Decimator 4 Switch", CS42L43_DECIM_VOL_CTRL_CH3_CH4, | |
1077 | CS42L43_DECIM4_MUTE_SHIFT, 1, 1, | |
1078 | cs42l43_decim_get, cs42l43_dapm_put_volsw), | |
1079 | ||
1080 | SOC_ENUM_EXT("Decimator 1 Ramp Up", cs42l43_dec1_ramp_up, | |
1081 | cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), | |
1082 | SOC_ENUM_EXT("Decimator 1 Ramp Down", cs42l43_dec1_ramp_down, | |
1083 | cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), | |
1084 | SOC_ENUM_EXT("Decimator 2 Ramp Up", cs42l43_dec2_ramp_up, | |
1085 | cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), | |
1086 | SOC_ENUM_EXT("Decimator 2 Ramp Down", cs42l43_dec2_ramp_down, | |
1087 | cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), | |
1088 | SOC_ENUM_EXT("Decimator 3 Ramp Up", cs42l43_dec3_ramp_up, | |
1089 | cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), | |
1090 | SOC_ENUM_EXT("Decimator 3 Ramp Down", cs42l43_dec3_ramp_down, | |
1091 | cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), | |
1092 | SOC_ENUM_EXT("Decimator 4 Ramp Up", cs42l43_dec4_ramp_up, | |
1093 | cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), | |
1094 | SOC_ENUM_EXT("Decimator 4 Ramp Down", cs42l43_dec4_ramp_down, | |
1095 | cs42l43_dapm_get_enum, cs42l43_dapm_put_enum), | |
1096 | ||
1097 | SOC_DOUBLE_R_EXT("Speaker Digital Switch", | |
1098 | CS42L43_INTP_VOLUME_CTRL1, CS42L43_INTP_VOLUME_CTRL2, | |
1099 | CS42L43_AMP_MUTE_SHIFT, 1, 1, | |
1100 | cs42l43_spk_get, cs42l43_spk_put), | |
1101 | ||
1102 | SOC_DOUBLE_R_EXT_TLV("Speaker Digital Volume", | |
1103 | CS42L43_INTP_VOLUME_CTRL1, CS42L43_INTP_VOLUME_CTRL2, | |
1104 | CS42L43_AMP_VOL_SHIFT, | |
1105 | 0xBF, 0, snd_soc_get_volsw, cs42l43_spk_put, | |
1106 | cs42l43_speaker_tlv), | |
1107 | ||
1108 | SOC_ENUM("Speaker Ramp Up", cs42l43_speaker_ramp_up), | |
1109 | SOC_ENUM("Speaker Ramp Down", cs42l43_speaker_ramp_down), | |
1110 | ||
1111 | CS42L43_MIXER_VOLUMES("Speaker L", CS42L43_AMP1MIX_INPUT1), | |
1112 | CS42L43_MIXER_VOLUMES("Speaker R", CS42L43_AMP2MIX_INPUT1), | |
1113 | ||
1114 | SOC_DOUBLE_SX_TLV("Headphone Digital Volume", CS42L43_HPPATHVOL, | |
1115 | CS42L43_AMP3_PATH_VOL_SHIFT, CS42L43_AMP4_PATH_VOL_SHIFT, | |
1116 | 0x11B, 229, cs42l43_headphone_tlv), | |
1117 | ||
1118 | SOC_DOUBLE("Headphone Invert Switch", CS42L43_DACCNFG1, | |
1119 | CS42L43_AMP3_INV_SHIFT, CS42L43_AMP4_INV_SHIFT, 1, 0), | |
1120 | ||
1121 | SOC_SINGLE("Headphone Zero Cross Switch", CS42L43_PGAVOL, | |
1122 | CS42L43_HP_PATH_VOL_ZC_SHIFT, 1, 0), | |
1123 | SOC_SINGLE("Headphone Ramp Switch", CS42L43_PGAVOL, | |
1124 | CS42L43_HP_PATH_VOL_SFT_SHIFT, 1, 0), | |
1125 | SOC_ENUM("Headphone Ramp Rate", cs42l43_headphone_ramp), | |
1126 | ||
1127 | CS42L43_MIXER_VOLUMES("Headphone L", CS42L43_AMP3MIX_INPUT1), | |
1128 | CS42L43_MIXER_VOLUMES("Headphone R", CS42L43_AMP4MIX_INPUT1), | |
1129 | ||
1130 | SOC_ENUM("Tone 1 Frequency", cs42l43_tone1_freq), | |
1131 | SOC_ENUM("Tone 2 Frequency", cs42l43_tone2_freq), | |
1132 | ||
1133 | SOC_DOUBLE_EXT("EQ Switch", | |
1134 | CS42L43_MUTE_EQ_IN0, CS42L43_MUTE_EQ_CH1_SHIFT, | |
1135 | CS42L43_MUTE_EQ_CH2_SHIFT, 1, 1, | |
1136 | cs42l43_dapm_get_volsw, cs42l43_dapm_put_volsw), | |
1137 | ||
1138 | SND_SOC_BYTES_E("EQ Coefficients", 0, CS42L43_N_EQ_COEFFS, | |
1139 | cs42l43_eq_get, cs42l43_eq_put), | |
1140 | ||
1141 | CS42L43_MIXER_VOLUMES("EQ1", CS42L43_EQ1MIX_INPUT1), | |
1142 | CS42L43_MIXER_VOLUMES("EQ2", CS42L43_EQ2MIX_INPUT1), | |
1143 | }; | |
1144 | ||
1145 | static int cs42l43_eq_ev(struct snd_soc_dapm_widget *w, | |
1146 | struct snd_kcontrol *kcontrol, int event) | |
1147 | { | |
1148 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); | |
1149 | struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); | |
1150 | struct cs42l43 *cs42l43 = priv->core; | |
1151 | unsigned int val; | |
1152 | int i, ret; | |
1153 | ||
1154 | switch (event) { | |
1155 | case SND_SOC_DAPM_PRE_PMU: | |
1156 | regmap_update_bits(cs42l43->regmap, CS42L43_MUTE_EQ_IN0, | |
1157 | CS42L43_MUTE_EQ_CH1_MASK | CS42L43_MUTE_EQ_CH2_MASK, | |
1158 | CS42L43_MUTE_EQ_CH1_MASK | CS42L43_MUTE_EQ_CH2_MASK); | |
1159 | ||
1160 | regmap_update_bits(cs42l43->regmap, CS42L43_COEFF_RD_WR0, | |
1161 | CS42L43_WRITE_MODE_MASK, CS42L43_WRITE_MODE_MASK); | |
1162 | ||
1163 | for (i = 0; i < CS42L43_N_EQ_COEFFS; i++) | |
1164 | regmap_write(cs42l43->regmap, CS42L43_COEFF_DATA_IN0, | |
1165 | priv->eq_coeffs[i]); | |
1166 | ||
1167 | regmap_update_bits(cs42l43->regmap, CS42L43_COEFF_RD_WR0, | |
1168 | CS42L43_WRITE_MODE_MASK, 0); | |
1169 | ||
1170 | return 0; | |
1171 | case SND_SOC_DAPM_POST_PMU: | |
1172 | ret = regmap_read_poll_timeout(cs42l43->regmap, CS42L43_INIT_DONE0, | |
1173 | val, (val & CS42L43_INITIALIZE_DONE_MASK), | |
1174 | 2000, 10000); | |
1175 | if (ret) | |
1176 | dev_err(priv->dev, "Failed to start EQs: %d\n", ret); | |
1177 | ||
1178 | regmap_update_bits(cs42l43->regmap, CS42L43_MUTE_EQ_IN0, | |
1179 | CS42L43_MUTE_EQ_CH1_MASK | CS42L43_MUTE_EQ_CH2_MASK, 0); | |
1180 | return ret; | |
1181 | default: | |
1182 | return 0; | |
1183 | } | |
1184 | } | |
1185 | ||
1186 | struct cs42l43_pll_config { | |
1187 | unsigned int freq; | |
1188 | ||
1189 | unsigned int div; | |
1190 | unsigned int mode; | |
1191 | unsigned int cal; | |
1192 | }; | |
1193 | ||
1194 | static const struct cs42l43_pll_config cs42l43_pll_configs[] = { | |
1195 | { 2400000, 0x50000000, 0x1, 0xA4 }, | |
1196 | { 3000000, 0x40000000, 0x1, 0x83 }, | |
1197 | { 3072000, 0x40000000, 0x3, 0x80 }, | |
1198 | }; | |
1199 | ||
1200 | static int cs42l43_set_pll(struct cs42l43_codec *priv, unsigned int src, | |
1201 | unsigned int freq) | |
1202 | { | |
1203 | struct cs42l43 *cs42l43 = priv->core; | |
1204 | ||
1205 | lockdep_assert_held(&cs42l43->pll_lock); | |
1206 | ||
1207 | if (priv->refclk_src == src && priv->refclk_freq == freq) | |
1208 | return 0; | |
1209 | ||
1210 | if (regmap_test_bits(cs42l43->regmap, CS42L43_CTRL_REG, CS42L43_PLL_EN_MASK)) { | |
1211 | dev_err(priv->dev, "PLL active, can't change configuration\n"); | |
1212 | return -EBUSY; | |
1213 | } | |
1214 | ||
1215 | switch (src) { | |
1216 | case CS42L43_SYSCLK_MCLK: | |
1217 | case CS42L43_SYSCLK_SDW: | |
1218 | dev_dbg(priv->dev, "Source PLL from %s at %uHz\n", | |
1219 | src ? "SoundWire" : "MCLK", freq); | |
1220 | ||
1221 | priv->refclk_src = src; | |
1222 | priv->refclk_freq = freq; | |
1223 | ||
1224 | return 0; | |
1225 | default: | |
1226 | dev_err(priv->dev, "Invalid PLL source: 0x%x\n", src); | |
1227 | return -EINVAL; | |
1228 | } | |
1229 | } | |
1230 | ||
1231 | static int cs42l43_enable_pll(struct cs42l43_codec *priv) | |
1232 | { | |
1233 | static const struct reg_sequence enable_seq[] = { | |
1234 | { CS42L43_OSC_DIV_SEL, 0x0, }, | |
1235 | { CS42L43_MCLK_SRC_SEL, CS42L43_OSC_PLL_MCLK_SEL_MASK, 5, }, | |
1236 | }; | |
1237 | struct cs42l43 *cs42l43 = priv->core; | |
1238 | const struct cs42l43_pll_config *config = NULL; | |
1239 | unsigned int div = 0; | |
1240 | unsigned int freq = priv->refclk_freq; | |
1241 | unsigned long time_left; | |
1242 | ||
1243 | lockdep_assert_held(&cs42l43->pll_lock); | |
1244 | ||
1245 | if (priv->refclk_src == CS42L43_SYSCLK_SDW) { | |
1246 | if (!freq) | |
1247 | freq = cs42l43->sdw_freq; | |
1248 | else if (!cs42l43->sdw_freq) | |
1249 | cs42l43->sdw_freq = freq; | |
1250 | } | |
1251 | ||
1252 | dev_dbg(priv->dev, "Enabling PLL at %uHz\n", freq); | |
1253 | ||
1254 | while (freq > cs42l43_pll_configs[ARRAY_SIZE(cs42l43_pll_configs) - 1].freq) { | |
1255 | div++; | |
1256 | freq /= 2; | |
1257 | } | |
1258 | ||
1259 | if (div <= CS42L43_PLL_REFCLK_DIV_MASK) { | |
1260 | int i; | |
1261 | ||
1262 | for (i = 0; i < ARRAY_SIZE(cs42l43_pll_configs); i++) { | |
1263 | if (freq == cs42l43_pll_configs[i].freq) { | |
1264 | config = &cs42l43_pll_configs[i]; | |
1265 | break; | |
1266 | } | |
1267 | } | |
1268 | } | |
1269 | ||
1270 | if (!config) { | |
1271 | dev_err(priv->dev, "No suitable PLL config: 0x%x, %uHz\n", div, freq); | |
1272 | return -EINVAL; | |
1273 | } | |
1274 | ||
1275 | regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL, | |
1276 | CS42L43_PLL_REFCLK_DIV_MASK | CS42L43_PLL_REFCLK_SRC_MASK, | |
1277 | div << CS42L43_PLL_REFCLK_DIV_SHIFT | | |
1278 | priv->refclk_src << CS42L43_PLL_REFCLK_SRC_SHIFT); | |
1279 | regmap_write(cs42l43->regmap, CS42L43_FDIV_FRAC, config->div); | |
1280 | regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG, | |
1281 | CS42L43_PLL_MODE_BYPASS_500_MASK | | |
1282 | CS42L43_PLL_MODE_BYPASS_1029_MASK, | |
1283 | config->mode << CS42L43_PLL_MODE_BYPASS_1029_SHIFT); | |
1284 | regmap_update_bits(cs42l43->regmap, CS42L43_CAL_RATIO, | |
1285 | CS42L43_PLL_CAL_RATIO_MASK, config->cal); | |
1286 | regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL, | |
1287 | CS42L43_PLL_REFCLK_EN_MASK, CS42L43_PLL_REFCLK_EN_MASK); | |
1288 | ||
1289 | reinit_completion(&priv->pll_ready); | |
1290 | ||
1291 | regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG, | |
1292 | CS42L43_PLL_EN_MASK, CS42L43_PLL_EN_MASK); | |
1293 | ||
1294 | time_left = wait_for_completion_timeout(&priv->pll_ready, | |
1295 | msecs_to_jiffies(CS42L43_PLL_TIMEOUT_MS)); | |
1296 | if (!time_left) { | |
1297 | regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG, | |
1298 | CS42L43_PLL_EN_MASK, 0); | |
1299 | regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL, | |
1300 | CS42L43_PLL_REFCLK_EN_MASK, 0); | |
1301 | ||
1302 | dev_err(priv->dev, "Timeout out waiting for PLL\n"); | |
1303 | return -ETIMEDOUT; | |
1304 | } | |
1305 | ||
1306 | if (priv->refclk_src == CS42L43_SYSCLK_SDW) | |
1307 | cs42l43->sdw_pll_active = true; | |
1308 | ||
1309 | dev_dbg(priv->dev, "PLL locked in %ums\n", 200 - jiffies_to_msecs(time_left)); | |
1310 | ||
1311 | /* | |
1312 | * Reads are not allowed over Soundwire without OSC_DIV2_EN or the PLL, | |
1313 | * but you can not change to PLL with OSC_DIV2_EN set. So ensure the whole | |
1314 | * change over happens under the regmap lock to prevent any reads. | |
1315 | */ | |
1316 | regmap_multi_reg_write(cs42l43->regmap, enable_seq, ARRAY_SIZE(enable_seq)); | |
1317 | ||
1318 | return 0; | |
1319 | } | |
1320 | ||
1321 | static int cs42l43_disable_pll(struct cs42l43_codec *priv) | |
1322 | { | |
1323 | static const struct reg_sequence disable_seq[] = { | |
1324 | { CS42L43_MCLK_SRC_SEL, 0x0, 5, }, | |
1325 | { CS42L43_OSC_DIV_SEL, CS42L43_OSC_DIV2_EN_MASK, }, | |
1326 | }; | |
1327 | struct cs42l43 *cs42l43 = priv->core; | |
1328 | ||
1329 | dev_dbg(priv->dev, "Disabling PLL\n"); | |
1330 | ||
1331 | lockdep_assert_held(&cs42l43->pll_lock); | |
1332 | ||
1333 | regmap_multi_reg_write(cs42l43->regmap, disable_seq, ARRAY_SIZE(disable_seq)); | |
1334 | regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG, CS42L43_PLL_EN_MASK, 0); | |
1335 | regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL, | |
1336 | CS42L43_PLL_REFCLK_EN_MASK, 0); | |
1337 | ||
1338 | cs42l43->sdw_pll_active = false; | |
1339 | ||
1340 | return 0; | |
1341 | } | |
1342 | ||
1343 | static int cs42l43_pll_ev(struct snd_soc_dapm_widget *w, | |
1344 | struct snd_kcontrol *kcontrol, int event) | |
1345 | { | |
1346 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); | |
1347 | struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); | |
1348 | struct cs42l43 *cs42l43 = priv->core; | |
1349 | int ret; | |
1350 | ||
1351 | mutex_lock(&cs42l43->pll_lock); | |
1352 | ||
1353 | switch (event) { | |
1354 | case SND_SOC_DAPM_PRE_PMU: | |
1355 | if (priv->refclk_src == CS42L43_SYSCLK_MCLK) { | |
1356 | ret = clk_prepare_enable(priv->mclk); | |
1357 | if (ret) { | |
1358 | dev_err(priv->dev, "Failed to enable MCLK: %d\n", ret); | |
1359 | break; | |
1360 | } | |
1361 | } | |
1362 | ||
1363 | ret = cs42l43_enable_pll(priv); | |
1364 | break; | |
1365 | case SND_SOC_DAPM_POST_PMD: | |
1366 | ret = cs42l43_disable_pll(priv); | |
1367 | ||
1368 | if (priv->refclk_src == CS42L43_SYSCLK_MCLK) | |
1369 | clk_disable_unprepare(priv->mclk); | |
1370 | break; | |
1371 | default: | |
a7404843 | 1372 | ret = 0; |
fc918cbe CK |
1373 | break; |
1374 | } | |
1375 | ||
1376 | mutex_unlock(&cs42l43->pll_lock); | |
1377 | ||
1378 | return ret; | |
1379 | } | |
1380 | ||
1381 | static int cs42l43_dapm_wait_completion(struct completion *pmu, struct completion *pmd, | |
1382 | int event, int timeout_ms) | |
1383 | { | |
1384 | unsigned long time_left; | |
1385 | ||
1386 | switch (event) { | |
1387 | case SND_SOC_DAPM_PRE_PMU: | |
1388 | reinit_completion(pmu); | |
1389 | return 0; | |
1390 | case SND_SOC_DAPM_PRE_PMD: | |
1391 | reinit_completion(pmd); | |
1392 | return 0; | |
1393 | case SND_SOC_DAPM_POST_PMU: | |
1394 | time_left = wait_for_completion_timeout(pmu, msecs_to_jiffies(timeout_ms)); | |
1395 | break; | |
1396 | case SND_SOC_DAPM_POST_PMD: | |
1397 | time_left = wait_for_completion_timeout(pmd, msecs_to_jiffies(timeout_ms)); | |
1398 | break; | |
1399 | default: | |
1400 | return 0; | |
1401 | } | |
1402 | ||
1403 | if (!time_left) | |
1404 | return -ETIMEDOUT; | |
1405 | else | |
1406 | return 0; | |
1407 | } | |
1408 | ||
1409 | static int cs42l43_spkr_ev(struct snd_soc_dapm_widget *w, | |
1410 | struct snd_kcontrol *kcontrol, int event) | |
1411 | { | |
1412 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); | |
1413 | struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); | |
1414 | ||
1415 | return cs42l43_dapm_wait_completion(&priv->spkr_startup, | |
1416 | &priv->spkr_shutdown, event, | |
1417 | CS42L43_SPK_TIMEOUT_MS); | |
1418 | } | |
1419 | ||
1420 | static int cs42l43_spkl_ev(struct snd_soc_dapm_widget *w, | |
1421 | struct snd_kcontrol *kcontrol, int event) | |
1422 | { | |
1423 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); | |
1424 | struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); | |
1425 | ||
1426 | return cs42l43_dapm_wait_completion(&priv->spkl_startup, | |
1427 | &priv->spkl_shutdown, event, | |
1428 | CS42L43_SPK_TIMEOUT_MS); | |
1429 | } | |
1430 | ||
1431 | static int cs42l43_hp_ev(struct snd_soc_dapm_widget *w, | |
1432 | struct snd_kcontrol *kcontrol, int event) | |
1433 | { | |
1434 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); | |
1435 | struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); | |
1436 | struct cs42l43 *cs42l43 = priv->core; | |
1437 | unsigned int mask = 1 << w->shift; | |
1438 | unsigned int val = 0; | |
1439 | int ret; | |
1440 | ||
1441 | switch (event) { | |
1442 | case SND_SOC_DAPM_PRE_PMU: | |
1443 | val = mask; | |
1444 | fallthrough; | |
1445 | case SND_SOC_DAPM_PRE_PMD: | |
1446 | priv->hp_ena &= ~mask; | |
1447 | priv->hp_ena |= val; | |
1448 | ||
1449 | ret = cs42l43_dapm_wait_completion(&priv->hp_startup, | |
1450 | &priv->hp_shutdown, event, | |
1451 | CS42L43_HP_TIMEOUT_MS); | |
1452 | if (ret) | |
1453 | return ret; | |
1454 | ||
1455 | if (!priv->load_detect_running) | |
1456 | regmap_update_bits(cs42l43->regmap, CS42L43_BLOCK_EN8, | |
1457 | mask, val); | |
1458 | break; | |
1459 | case SND_SOC_DAPM_POST_PMU: | |
1460 | case SND_SOC_DAPM_POST_PMD: | |
1461 | if (priv->load_detect_running) | |
1462 | break; | |
1463 | ||
1464 | ret = cs42l43_dapm_wait_completion(&priv->hp_startup, | |
1465 | &priv->hp_shutdown, event, | |
1466 | CS42L43_HP_TIMEOUT_MS); | |
1467 | if (ret) | |
1468 | return ret; | |
1469 | break; | |
1470 | default: | |
1471 | break; | |
1472 | } | |
1473 | ||
1474 | return 0; | |
1475 | } | |
1476 | ||
1477 | static int cs42l43_mic_ev(struct snd_soc_dapm_widget *w, | |
1478 | struct snd_kcontrol *kcontrol, int event) | |
1479 | { | |
1480 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); | |
1481 | struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); | |
1482 | struct cs42l43 *cs42l43 = priv->core; | |
1483 | unsigned int reg, ramp, mute; | |
1484 | unsigned int *val; | |
1485 | int ret; | |
1486 | ||
1487 | switch (w->shift) { | |
1488 | case CS42L43_ADC1_EN_SHIFT: | |
1489 | case CS42L43_PDM1_DIN_L_EN_SHIFT: | |
1490 | reg = CS42L43_DECIM_VOL_CTRL_CH1_CH2; | |
1491 | ramp = CS42L43_DECIM1_VD_RAMP_MASK; | |
1492 | mute = CS42L43_DECIM1_MUTE_MASK; | |
1493 | val = &priv->decim_cache[0]; | |
1494 | break; | |
1495 | case CS42L43_ADC2_EN_SHIFT: | |
1496 | case CS42L43_PDM1_DIN_R_EN_SHIFT: | |
1497 | reg = CS42L43_DECIM_VOL_CTRL_CH1_CH2; | |
1498 | ramp = CS42L43_DECIM2_VD_RAMP_MASK; | |
1499 | mute = CS42L43_DECIM2_MUTE_MASK; | |
1500 | val = &priv->decim_cache[1]; | |
1501 | break; | |
1502 | case CS42L43_PDM2_DIN_L_EN_SHIFT: | |
1503 | reg = CS42L43_DECIM_VOL_CTRL_CH3_CH4; | |
1504 | ramp = CS42L43_DECIM3_VD_RAMP_MASK; | |
1505 | mute = CS42L43_DECIM3_MUTE_MASK; | |
1506 | val = &priv->decim_cache[2]; | |
1507 | break; | |
1508 | case CS42L43_PDM2_DIN_R_EN_SHIFT: | |
1509 | reg = CS42L43_DECIM_VOL_CTRL_CH3_CH4; | |
1510 | ramp = CS42L43_DECIM4_VD_RAMP_MASK; | |
1511 | mute = CS42L43_DECIM4_MUTE_MASK; | |
1512 | val = &priv->decim_cache[3]; | |
1513 | break; | |
1514 | default: | |
1515 | dev_err(priv->dev, "Invalid microphone shift: %d\n", w->shift); | |
1516 | return -EINVAL; | |
1517 | } | |
1518 | ||
1519 | switch (event) { | |
1520 | case SND_SOC_DAPM_PRE_PMU: | |
1521 | ret = regmap_read(cs42l43->regmap, reg, val); | |
1522 | if (ret) { | |
1523 | dev_err(priv->dev, | |
1524 | "Failed to cache decimator settings: %d\n", | |
1525 | ret); | |
1526 | return ret; | |
1527 | } | |
1528 | ||
1529 | regmap_update_bits(cs42l43->regmap, reg, mute | ramp, mute); | |
1530 | break; | |
1531 | case SND_SOC_DAPM_POST_PMU: | |
1532 | regmap_update_bits(cs42l43->regmap, reg, mute | ramp, *val); | |
1533 | break; | |
1534 | default: | |
1535 | break; | |
1536 | } | |
1537 | ||
1538 | return 0; | |
1539 | } | |
1540 | ||
1541 | static int cs42l43_adc_ev(struct snd_soc_dapm_widget *w, | |
1542 | struct snd_kcontrol *kcontrol, int event) | |
1543 | { | |
1544 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); | |
1545 | struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); | |
1546 | struct cs42l43 *cs42l43 = priv->core; | |
1547 | unsigned int mask = 1 << w->shift; | |
1548 | unsigned int val = 0; | |
1549 | int ret; | |
1550 | ||
1551 | ret = cs42l43_mic_ev(w, kcontrol, event); | |
1552 | if (ret) | |
1553 | return ret; | |
1554 | ||
1555 | switch (event) { | |
1556 | case SND_SOC_DAPM_PRE_PMU: | |
1557 | val = mask; | |
1558 | fallthrough; | |
1559 | case SND_SOC_DAPM_PRE_PMD: | |
1560 | priv->adc_ena &= ~mask; | |
1561 | priv->adc_ena |= val; | |
1562 | ||
1563 | if (!priv->load_detect_running) | |
1564 | regmap_update_bits(cs42l43->regmap, CS42L43_BLOCK_EN3, | |
1565 | mask, val); | |
1566 | fallthrough; | |
1567 | default: | |
1568 | return 0; | |
1569 | } | |
1570 | } | |
1571 | ||
1572 | static const struct snd_soc_dapm_widget cs42l43_widgets[] = { | |
1573 | SND_SOC_DAPM_SUPPLY("PLL", SND_SOC_NOPM, 0, 0, cs42l43_pll_ev, | |
1574 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), | |
1575 | ||
1576 | SND_SOC_DAPM_INPUT("ADC1_IN1_P"), | |
1577 | SND_SOC_DAPM_INPUT("ADC1_IN1_N"), | |
1578 | SND_SOC_DAPM_INPUT("ADC1_IN2_P"), | |
1579 | SND_SOC_DAPM_INPUT("ADC1_IN2_N"), | |
1580 | SND_SOC_DAPM_INPUT("ADC2_IN_P"), | |
1581 | SND_SOC_DAPM_INPUT("ADC2_IN_N"), | |
1582 | ||
1583 | SND_SOC_DAPM_INPUT("PDM1_DIN"), | |
1584 | SND_SOC_DAPM_INPUT("PDM2_DIN"), | |
1585 | ||
1586 | SND_SOC_DAPM_MUX("ADC1 Input", SND_SOC_NOPM, 0, 0, &cs42l43_adc1_input_ctl), | |
1587 | ||
1588 | SND_SOC_DAPM_PGA_E("ADC1", SND_SOC_NOPM, CS42L43_ADC1_EN_SHIFT, 0, NULL, 0, | |
1589 | cs42l43_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | | |
1590 | SND_SOC_DAPM_PRE_PMD), | |
1591 | SND_SOC_DAPM_PGA_E("ADC2", SND_SOC_NOPM, CS42L43_ADC2_EN_SHIFT, 0, NULL, 0, | |
1592 | cs42l43_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | | |
1593 | SND_SOC_DAPM_PRE_PMD), | |
1594 | ||
1595 | SND_SOC_DAPM_PGA_E("PDM1L", CS42L43_BLOCK_EN3, CS42L43_PDM1_DIN_L_EN_SHIFT, | |
1596 | 0, NULL, 0, cs42l43_mic_ev, | |
1597 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), | |
1598 | SND_SOC_DAPM_PGA_E("PDM1R", CS42L43_BLOCK_EN3, CS42L43_PDM1_DIN_R_EN_SHIFT, | |
1599 | 0, NULL, 0, cs42l43_mic_ev, | |
1600 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), | |
1601 | SND_SOC_DAPM_PGA_E("PDM2L", CS42L43_BLOCK_EN3, CS42L43_PDM2_DIN_L_EN_SHIFT, | |
1602 | 0, NULL, 0, cs42l43_mic_ev, | |
1603 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), | |
1604 | SND_SOC_DAPM_PGA_E("PDM2R", CS42L43_BLOCK_EN3, CS42L43_PDM2_DIN_R_EN_SHIFT, | |
1605 | 0, NULL, 0, cs42l43_mic_ev, | |
1606 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), | |
1607 | ||
1608 | SND_SOC_DAPM_MUX("Decimator 1 Mode", SND_SOC_NOPM, 0, 0, | |
1609 | &cs42l43_dec_mode_ctl[0]), | |
1610 | SND_SOC_DAPM_MUX("Decimator 2 Mode", SND_SOC_NOPM, 0, 0, | |
1611 | &cs42l43_dec_mode_ctl[1]), | |
1612 | ||
1613 | SND_SOC_DAPM_PGA("Decimator 1", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1614 | SND_SOC_DAPM_PGA("Decimator 2", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1615 | SND_SOC_DAPM_PGA("Decimator 3", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1616 | SND_SOC_DAPM_PGA("Decimator 4", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1617 | ||
1618 | SND_SOC_DAPM_SUPPLY_S("FSYNC", 0, CS42L43_ASP_CTRL, CS42L43_ASP_FSYNC_EN_SHIFT, | |
1619 | 0, NULL, 0), | |
1620 | SND_SOC_DAPM_SUPPLY_S("BCLK", 1, CS42L43_ASP_CTRL, CS42L43_ASP_BCLK_EN_SHIFT, | |
1621 | 0, NULL, 0), | |
1622 | ||
1623 | SND_SOC_DAPM_AIF_OUT("ASPTX1", NULL, 0, | |
1624 | CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH1_EN_SHIFT, 0), | |
1625 | SND_SOC_DAPM_AIF_OUT("ASPTX2", NULL, 1, | |
1626 | CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH2_EN_SHIFT, 0), | |
1627 | SND_SOC_DAPM_AIF_OUT("ASPTX3", NULL, 2, | |
1628 | CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH3_EN_SHIFT, 0), | |
1629 | SND_SOC_DAPM_AIF_OUT("ASPTX4", NULL, 3, | |
1630 | CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH4_EN_SHIFT, 0), | |
1631 | SND_SOC_DAPM_AIF_OUT("ASPTX5", NULL, 4, | |
1632 | CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH5_EN_SHIFT, 0), | |
1633 | SND_SOC_DAPM_AIF_OUT("ASPTX6", NULL, 5, | |
1634 | CS42L43_ASP_TX_EN, CS42L43_ASP_TX_CH6_EN_SHIFT, 0), | |
1635 | ||
1636 | SND_SOC_DAPM_AIF_IN("ASPRX1", NULL, 0, | |
1637 | CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH1_EN_SHIFT, 0), | |
1638 | SND_SOC_DAPM_AIF_IN("ASPRX2", NULL, 1, | |
1639 | CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH2_EN_SHIFT, 0), | |
1640 | SND_SOC_DAPM_AIF_IN("ASPRX3", NULL, 2, | |
1641 | CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH3_EN_SHIFT, 0), | |
1642 | SND_SOC_DAPM_AIF_IN("ASPRX4", NULL, 3, | |
1643 | CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH4_EN_SHIFT, 0), | |
1644 | SND_SOC_DAPM_AIF_IN("ASPRX5", NULL, 4, | |
1645 | CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH5_EN_SHIFT, 0), | |
1646 | SND_SOC_DAPM_AIF_IN("ASPRX6", NULL, 5, | |
1647 | CS42L43_ASP_RX_EN, CS42L43_ASP_RX_CH6_EN_SHIFT, 0), | |
1648 | ||
1649 | SND_SOC_DAPM_AIF_OUT("DP1TX1", NULL, 0, SND_SOC_NOPM, 0, 0), | |
1650 | SND_SOC_DAPM_AIF_OUT("DP1TX2", NULL, 1, SND_SOC_NOPM, 0, 0), | |
1651 | SND_SOC_DAPM_AIF_OUT("DP1TX3", NULL, 2, SND_SOC_NOPM, 0, 0), | |
1652 | SND_SOC_DAPM_AIF_OUT("DP1TX4", NULL, 3, SND_SOC_NOPM, 0, 0), | |
1653 | ||
1654 | SND_SOC_DAPM_AIF_OUT("DP2TX1", NULL, 0, SND_SOC_NOPM, 0, 0), | |
1655 | SND_SOC_DAPM_AIF_OUT("DP2TX2", NULL, 1, SND_SOC_NOPM, 0, 0), | |
1656 | ||
1657 | SND_SOC_DAPM_AIF_OUT("DP3TX1", NULL, 0, SND_SOC_NOPM, 0, 0), | |
1658 | SND_SOC_DAPM_AIF_OUT("DP3TX2", NULL, 1, SND_SOC_NOPM, 0, 0), | |
1659 | ||
1660 | SND_SOC_DAPM_AIF_OUT("DP4TX1", NULL, 0, SND_SOC_NOPM, 0, 0), | |
1661 | SND_SOC_DAPM_AIF_OUT("DP4TX2", NULL, 1, SND_SOC_NOPM, 0, 0), | |
1662 | ||
1663 | SND_SOC_DAPM_AIF_IN("DP5RX1", NULL, 0, SND_SOC_NOPM, 0, 0), | |
1664 | SND_SOC_DAPM_AIF_IN("DP5RX2", NULL, 1, SND_SOC_NOPM, 0, 0), | |
1665 | ||
1666 | SND_SOC_DAPM_AIF_IN("DP6RX1", NULL, 0, SND_SOC_NOPM, 0, 0), | |
1667 | SND_SOC_DAPM_AIF_IN("DP6RX2", NULL, 1, SND_SOC_NOPM, 0, 0), | |
1668 | ||
1669 | SND_SOC_DAPM_AIF_IN("DP7RX1", NULL, 0, SND_SOC_NOPM, 0, 0), | |
1670 | SND_SOC_DAPM_AIF_IN("DP7RX2", NULL, 1, SND_SOC_NOPM, 0, 0), | |
1671 | ||
1672 | SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-amp", 0, 0), | |
1673 | ||
1674 | SND_SOC_DAPM_PGA_E("AMP1", CS42L43_BLOCK_EN10, CS42L43_AMP1_EN_SHIFT, 0, NULL, 0, | |
1675 | cs42l43_spkl_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | | |
1676 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), | |
1677 | SND_SOC_DAPM_PGA_E("AMP2", CS42L43_BLOCK_EN10, CS42L43_AMP2_EN_SHIFT, 0, NULL, 0, | |
1678 | cs42l43_spkr_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | | |
1679 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), | |
1680 | ||
1681 | SND_SOC_DAPM_OUTPUT("AMP1_OUT_P"), | |
1682 | SND_SOC_DAPM_OUTPUT("AMP1_OUT_N"), | |
1683 | SND_SOC_DAPM_OUTPUT("AMP2_OUT_P"), | |
1684 | SND_SOC_DAPM_OUTPUT("AMP2_OUT_N"), | |
1685 | ||
1686 | SND_SOC_DAPM_PGA("SPDIF", CS42L43_BLOCK_EN11, CS42L43_SPDIF_EN_SHIFT, | |
1687 | 0, NULL, 0), | |
1688 | SND_SOC_DAPM_OUTPUT("SPDIF_TX"), | |
1689 | ||
1690 | SND_SOC_DAPM_PGA_E("HP", SND_SOC_NOPM, CS42L43_HP_EN_SHIFT, 0, NULL, 0, | |
1691 | cs42l43_hp_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | | |
1692 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), | |
1693 | SND_SOC_DAPM_OUTPUT("AMP3_OUT"), | |
1694 | SND_SOC_DAPM_OUTPUT("AMP4_OUT"), | |
1695 | ||
1696 | SND_SOC_DAPM_SIGGEN("Tone"), | |
1697 | SND_SOC_DAPM_SUPPLY("Tone Generator", CS42L43_BLOCK_EN9, CS42L43_TONE_EN_SHIFT, | |
1698 | 0, NULL, 0), | |
1699 | SND_SOC_DAPM_REG(snd_soc_dapm_pga, "Tone 1", CS42L43_TONE_CH1_CTRL, | |
1700 | CS42L43_TONE_SEL_SHIFT, CS42L43_TONE_SEL_MASK, 0xA, 0), | |
1701 | SND_SOC_DAPM_REG(snd_soc_dapm_pga, "Tone 2", CS42L43_TONE_CH2_CTRL, | |
1702 | CS42L43_TONE_SEL_SHIFT, CS42L43_TONE_SEL_MASK, 0xA, 0), | |
1703 | ||
1704 | SND_SOC_DAPM_SUPPLY("ISRC1", CS42L43_BLOCK_EN5, CS42L43_ISRC1_BANK_EN_SHIFT, | |
1705 | 0, NULL, 0), | |
1706 | SND_SOC_DAPM_SUPPLY("ISRC2", CS42L43_BLOCK_EN5, CS42L43_ISRC2_BANK_EN_SHIFT, | |
1707 | 0, NULL, 0), | |
1708 | ||
1709 | SND_SOC_DAPM_PGA("ISRC1INT2", CS42L43_ISRC1_CTRL, | |
1710 | CS42L43_ISRC_INT2_EN_SHIFT, 0, NULL, 0), | |
1711 | SND_SOC_DAPM_PGA("ISRC1INT1", CS42L43_ISRC1_CTRL, | |
1712 | CS42L43_ISRC_INT1_EN_SHIFT, 0, NULL, 0), | |
1713 | SND_SOC_DAPM_PGA("ISRC1DEC2", CS42L43_ISRC1_CTRL, | |
1714 | CS42L43_ISRC_DEC2_EN_SHIFT, 0, NULL, 0), | |
1715 | SND_SOC_DAPM_PGA("ISRC1DEC1", CS42L43_ISRC1_CTRL, | |
1716 | CS42L43_ISRC_DEC1_EN_SHIFT, 0, NULL, 0), | |
1717 | ||
1718 | SND_SOC_DAPM_PGA("ISRC2INT2", CS42L43_ISRC2_CTRL, | |
1719 | CS42L43_ISRC_INT2_EN_SHIFT, 0, NULL, 0), | |
1720 | SND_SOC_DAPM_PGA("ISRC2INT1", CS42L43_ISRC2_CTRL, | |
1721 | CS42L43_ISRC_INT1_EN_SHIFT, 0, NULL, 0), | |
1722 | SND_SOC_DAPM_PGA("ISRC2DEC2", CS42L43_ISRC2_CTRL, | |
1723 | CS42L43_ISRC_DEC2_EN_SHIFT, 0, NULL, 0), | |
1724 | SND_SOC_DAPM_PGA("ISRC2DEC1", CS42L43_ISRC2_CTRL, | |
1725 | CS42L43_ISRC_DEC1_EN_SHIFT, 0, NULL, 0), | |
1726 | ||
1727 | SND_SOC_DAPM_SUPPLY("ASRC_INT", CS42L43_BLOCK_EN4, | |
1728 | CS42L43_ASRC_INT_BANK_EN_SHIFT, 0, NULL, 0), | |
1729 | SND_SOC_DAPM_SUPPLY("ASRC_DEC", CS42L43_BLOCK_EN4, | |
1730 | CS42L43_ASRC_DEC_BANK_EN_SHIFT, 0, NULL, 0), | |
1731 | ||
1732 | SND_SOC_DAPM_PGA("ASRC_INT1", CS42L43_ASRC_INT_ENABLES, | |
1733 | CS42L43_ASRC_INT1_EN_SHIFT, 0, NULL, 0), | |
1734 | SND_SOC_DAPM_PGA("ASRC_INT2", CS42L43_ASRC_INT_ENABLES, | |
1735 | CS42L43_ASRC_INT2_EN_SHIFT, 0, NULL, 0), | |
1736 | SND_SOC_DAPM_PGA("ASRC_INT3", CS42L43_ASRC_INT_ENABLES, | |
1737 | CS42L43_ASRC_INT3_EN_SHIFT, 0, NULL, 0), | |
1738 | SND_SOC_DAPM_PGA("ASRC_INT4", CS42L43_ASRC_INT_ENABLES, | |
1739 | CS42L43_ASRC_INT4_EN_SHIFT, 0, NULL, 0), | |
1740 | SND_SOC_DAPM_PGA("ASRC_DEC1", CS42L43_ASRC_DEC_ENABLES, | |
1741 | CS42L43_ASRC_DEC1_EN_SHIFT, 0, NULL, 0), | |
1742 | SND_SOC_DAPM_PGA("ASRC_DEC2", CS42L43_ASRC_DEC_ENABLES, | |
1743 | CS42L43_ASRC_DEC2_EN_SHIFT, 0, NULL, 0), | |
1744 | SND_SOC_DAPM_PGA("ASRC_DEC3", CS42L43_ASRC_DEC_ENABLES, | |
1745 | CS42L43_ASRC_DEC3_EN_SHIFT, 0, NULL, 0), | |
1746 | SND_SOC_DAPM_PGA("ASRC_DEC4", CS42L43_ASRC_DEC_ENABLES, | |
1747 | CS42L43_ASRC_DEC4_EN_SHIFT, 0, NULL, 0), | |
1748 | ||
1749 | SND_SOC_DAPM_SUPPLY("EQ Clock", CS42L43_BLOCK_EN7, CS42L43_EQ_EN_SHIFT, | |
1750 | 0, NULL, 0), | |
1751 | SND_SOC_DAPM_PGA_E("EQ", CS42L43_START_EQZ0, CS42L43_START_FILTER_SHIFT, | |
1752 | 0, NULL, 0, cs42l43_eq_ev, | |
1753 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), | |
1754 | ||
1755 | SND_SOC_DAPM_SUPPLY("Mixer Core", CS42L43_BLOCK_EN6, CS42L43_MIXER_EN_SHIFT, | |
1756 | 0, NULL, 0), | |
1757 | CS42L43_DAPM_MUX("ASPTX1", asptx1), | |
1758 | CS42L43_DAPM_MUX("ASPTX2", asptx2), | |
1759 | CS42L43_DAPM_MUX("ASPTX3", asptx3), | |
1760 | CS42L43_DAPM_MUX("ASPTX4", asptx4), | |
1761 | CS42L43_DAPM_MUX("ASPTX5", asptx5), | |
1762 | CS42L43_DAPM_MUX("ASPTX6", asptx6), | |
1763 | ||
1764 | CS42L43_DAPM_MUX("DP1TX1", dp1tx1), | |
1765 | CS42L43_DAPM_MUX("DP1TX2", dp1tx2), | |
1766 | CS42L43_DAPM_MUX("DP1TX3", dp1tx3), | |
1767 | CS42L43_DAPM_MUX("DP1TX4", dp1tx4), | |
1768 | CS42L43_DAPM_MUX("DP2TX1", dp2tx1), | |
1769 | CS42L43_DAPM_MUX("DP2TX2", dp2tx2), | |
1770 | CS42L43_DAPM_MUX("DP3TX1", dp3tx1), | |
1771 | CS42L43_DAPM_MUX("DP3TX2", dp3tx2), | |
1772 | CS42L43_DAPM_MUX("DP4TX1", dp4tx1), | |
1773 | CS42L43_DAPM_MUX("DP4TX2", dp4tx2), | |
1774 | ||
1775 | CS42L43_DAPM_MUX("ASRC INT1", asrcint1), | |
1776 | CS42L43_DAPM_MUX("ASRC INT2", asrcint2), | |
1777 | CS42L43_DAPM_MUX("ASRC INT3", asrcint3), | |
1778 | CS42L43_DAPM_MUX("ASRC INT4", asrcint4), | |
1779 | CS42L43_DAPM_MUX("ASRC DEC1", asrcdec1), | |
1780 | CS42L43_DAPM_MUX("ASRC DEC2", asrcdec2), | |
1781 | CS42L43_DAPM_MUX("ASRC DEC3", asrcdec3), | |
1782 | CS42L43_DAPM_MUX("ASRC DEC4", asrcdec4), | |
1783 | ||
1784 | CS42L43_DAPM_MUX("ISRC1INT1", isrc1int1), | |
1785 | CS42L43_DAPM_MUX("ISRC1INT2", isrc1int2), | |
1786 | CS42L43_DAPM_MUX("ISRC1DEC1", isrc1dec1), | |
1787 | CS42L43_DAPM_MUX("ISRC1DEC2", isrc1dec2), | |
1788 | CS42L43_DAPM_MUX("ISRC2INT1", isrc2int1), | |
1789 | CS42L43_DAPM_MUX("ISRC2INT2", isrc2int2), | |
1790 | CS42L43_DAPM_MUX("ISRC2DEC1", isrc2dec1), | |
1791 | CS42L43_DAPM_MUX("ISRC2DEC2", isrc2dec2), | |
1792 | ||
1793 | CS42L43_DAPM_MUX("SPDIF1", spdif1), | |
1794 | CS42L43_DAPM_MUX("SPDIF2", spdif2), | |
1795 | ||
1796 | CS42L43_DAPM_MIXER("EQ1", eq1), | |
1797 | CS42L43_DAPM_MIXER("EQ2", eq2), | |
1798 | ||
1799 | CS42L43_DAPM_MIXER("Speaker L", amp1), | |
1800 | CS42L43_DAPM_MIXER("Speaker R", amp2), | |
1801 | ||
1802 | CS42L43_DAPM_MIXER("Headphone L", amp3), | |
1803 | CS42L43_DAPM_MIXER("Headphone R", amp4), | |
1804 | }; | |
1805 | ||
1806 | static const struct snd_soc_dapm_route cs42l43_routes[] = { | |
1807 | { "ADC1_IN1_P", NULL, "PLL" }, | |
1808 | { "ADC1_IN1_N", NULL, "PLL" }, | |
1809 | { "ADC1_IN2_P", NULL, "PLL" }, | |
1810 | { "ADC1_IN2_N", NULL, "PLL" }, | |
1811 | { "ADC2_IN_P", NULL, "PLL" }, | |
1812 | { "ADC2_IN_N", NULL, "PLL" }, | |
1813 | { "PDM1_DIN", NULL, "PLL" }, | |
1814 | { "PDM2_DIN", NULL, "PLL" }, | |
1815 | { "AMP1_OUT_P", NULL, "PLL" }, | |
1816 | { "AMP1_OUT_N", NULL, "PLL" }, | |
1817 | { "AMP2_OUT_P", NULL, "PLL" }, | |
1818 | { "AMP2_OUT_N", NULL, "PLL" }, | |
1819 | { "SPDIF_TX", NULL, "PLL" }, | |
1820 | { "HP", NULL, "PLL" }, | |
1821 | { "AMP3_OUT", NULL, "PLL" }, | |
1822 | { "AMP4_OUT", NULL, "PLL" }, | |
1823 | { "Tone 1", NULL, "PLL" }, | |
1824 | { "Tone 2", NULL, "PLL" }, | |
1825 | { "ASP Playback", NULL, "PLL" }, | |
1826 | { "ASP Capture", NULL, "PLL" }, | |
1827 | { "DP1 Capture", NULL, "PLL" }, | |
1828 | { "DP2 Capture", NULL, "PLL" }, | |
1829 | { "DP3 Capture", NULL, "PLL" }, | |
1830 | { "DP4 Capture", NULL, "PLL" }, | |
1831 | { "DP5 Playback", NULL, "PLL" }, | |
1832 | { "DP6 Playback", NULL, "PLL" }, | |
1833 | { "DP7 Playback", NULL, "PLL" }, | |
1834 | ||
1835 | { "ADC1 Input", "IN1", "ADC1_IN1_P" }, | |
1836 | { "ADC1 Input", "IN1", "ADC1_IN1_N" }, | |
1837 | { "ADC1 Input", "IN2", "ADC1_IN2_P" }, | |
1838 | { "ADC1 Input", "IN2", "ADC1_IN2_N" }, | |
1839 | ||
1840 | { "ADC1", NULL, "ADC1 Input" }, | |
1841 | { "ADC2", NULL, "ADC2_IN_P" }, | |
1842 | { "ADC2", NULL, "ADC2_IN_N" }, | |
1843 | ||
1844 | { "PDM1L", NULL, "PDM1_DIN" }, | |
1845 | { "PDM1R", NULL, "PDM1_DIN" }, | |
1846 | { "PDM2L", NULL, "PDM2_DIN" }, | |
1847 | { "PDM2R", NULL, "PDM2_DIN" }, | |
1848 | ||
1849 | { "Decimator 1 Mode", "PDM", "PDM1L" }, | |
1850 | { "Decimator 1 Mode", "ADC", "ADC1" }, | |
1851 | { "Decimator 2 Mode", "PDM", "PDM1R" }, | |
1852 | { "Decimator 2 Mode", "ADC", "ADC2" }, | |
1853 | ||
1854 | { "Decimator 1", NULL, "Decimator 1 Mode" }, | |
1855 | { "Decimator 2", NULL, "Decimator 2 Mode" }, | |
1856 | { "Decimator 3", NULL, "PDM2L" }, | |
1857 | { "Decimator 4", NULL, "PDM2R" }, | |
1858 | ||
1859 | { "ASP Capture", NULL, "ASPTX1" }, | |
1860 | { "ASP Capture", NULL, "ASPTX2" }, | |
1861 | { "ASP Capture", NULL, "ASPTX3" }, | |
1862 | { "ASP Capture", NULL, "ASPTX4" }, | |
1863 | { "ASP Capture", NULL, "ASPTX5" }, | |
1864 | { "ASP Capture", NULL, "ASPTX6" }, | |
1865 | { "ASPTX1", NULL, "BCLK" }, | |
1866 | { "ASPTX2", NULL, "BCLK" }, | |
1867 | { "ASPTX3", NULL, "BCLK" }, | |
1868 | { "ASPTX4", NULL, "BCLK" }, | |
1869 | { "ASPTX5", NULL, "BCLK" }, | |
1870 | { "ASPTX6", NULL, "BCLK" }, | |
1871 | ||
1872 | { "ASPRX1", NULL, "ASP Playback" }, | |
1873 | { "ASPRX2", NULL, "ASP Playback" }, | |
1874 | { "ASPRX3", NULL, "ASP Playback" }, | |
1875 | { "ASPRX4", NULL, "ASP Playback" }, | |
1876 | { "ASPRX5", NULL, "ASP Playback" }, | |
1877 | { "ASPRX6", NULL, "ASP Playback" }, | |
1878 | { "ASPRX1", NULL, "BCLK" }, | |
1879 | { "ASPRX2", NULL, "BCLK" }, | |
1880 | { "ASPRX3", NULL, "BCLK" }, | |
1881 | { "ASPRX4", NULL, "BCLK" }, | |
1882 | { "ASPRX5", NULL, "BCLK" }, | |
1883 | { "ASPRX6", NULL, "BCLK" }, | |
1884 | ||
1885 | { "DP1 Capture", NULL, "DP1TX1" }, | |
1886 | { "DP1 Capture", NULL, "DP1TX2" }, | |
1887 | { "DP1 Capture", NULL, "DP1TX3" }, | |
1888 | { "DP1 Capture", NULL, "DP1TX4" }, | |
1889 | ||
1890 | { "DP2 Capture", NULL, "DP2TX1" }, | |
1891 | { "DP2 Capture", NULL, "DP2TX2" }, | |
1892 | ||
1893 | { "DP3 Capture", NULL, "DP3TX1" }, | |
1894 | { "DP3 Capture", NULL, "DP3TX2" }, | |
1895 | ||
1896 | { "DP4 Capture", NULL, "DP4TX1" }, | |
1897 | { "DP4 Capture", NULL, "DP4TX2" }, | |
1898 | ||
1899 | { "DP5RX1", NULL, "DP5 Playback" }, | |
1900 | { "DP5RX2", NULL, "DP5 Playback" }, | |
1901 | ||
1902 | { "DP6RX1", NULL, "DP6 Playback" }, | |
1903 | { "DP6RX2", NULL, "DP6 Playback" }, | |
1904 | ||
1905 | { "DP7RX1", NULL, "DP7 Playback" }, | |
1906 | { "DP7RX2", NULL, "DP7 Playback" }, | |
1907 | ||
1908 | { "AMP1", NULL, "vdd-amp" }, | |
1909 | { "AMP2", NULL, "vdd-amp" }, | |
1910 | ||
1911 | { "AMP1_OUT_P", NULL, "AMP1" }, | |
1912 | { "AMP1_OUT_N", NULL, "AMP1" }, | |
1913 | { "AMP2_OUT_P", NULL, "AMP2" }, | |
1914 | { "AMP2_OUT_N", NULL, "AMP2" }, | |
1915 | ||
1916 | { "SPDIF_TX", NULL, "SPDIF" }, | |
1917 | ||
1918 | { "AMP3_OUT", NULL, "HP" }, | |
1919 | { "AMP4_OUT", NULL, "HP" }, | |
1920 | ||
1921 | { "Tone 1", NULL, "Tone" }, | |
1922 | { "Tone 1", NULL, "Tone Generator" }, | |
1923 | { "Tone 2", NULL, "Tone" }, | |
1924 | { "Tone 2", NULL, "Tone Generator" }, | |
1925 | ||
1926 | { "ISRC1INT2", NULL, "ISRC1" }, | |
1927 | { "ISRC1INT1", NULL, "ISRC1" }, | |
1928 | { "ISRC1DEC2", NULL, "ISRC1" }, | |
1929 | { "ISRC1DEC1", NULL, "ISRC1" }, | |
1930 | ||
1931 | { "ISRC2INT2", NULL, "ISRC2" }, | |
1932 | { "ISRC2INT1", NULL, "ISRC2" }, | |
1933 | { "ISRC2DEC2", NULL, "ISRC2" }, | |
1934 | { "ISRC2DEC1", NULL, "ISRC2" }, | |
1935 | ||
1936 | { "ASRC_INT1", NULL, "ASRC_INT" }, | |
1937 | { "ASRC_INT2", NULL, "ASRC_INT" }, | |
1938 | { "ASRC_INT3", NULL, "ASRC_INT" }, | |
1939 | { "ASRC_INT4", NULL, "ASRC_INT" }, | |
1940 | { "ASRC_DEC1", NULL, "ASRC_DEC" }, | |
1941 | { "ASRC_DEC2", NULL, "ASRC_DEC" }, | |
1942 | { "ASRC_DEC3", NULL, "ASRC_DEC" }, | |
1943 | { "ASRC_DEC4", NULL, "ASRC_DEC" }, | |
1944 | ||
1945 | { "EQ", NULL, "EQ Clock" }, | |
1946 | ||
1947 | CS42L43_MUX_ROUTES("ASPTX1", "ASPTX1"), | |
1948 | CS42L43_MUX_ROUTES("ASPTX2", "ASPTX2"), | |
1949 | CS42L43_MUX_ROUTES("ASPTX3", "ASPTX3"), | |
1950 | CS42L43_MUX_ROUTES("ASPTX4", "ASPTX4"), | |
1951 | CS42L43_MUX_ROUTES("ASPTX5", "ASPTX5"), | |
1952 | CS42L43_MUX_ROUTES("ASPTX6", "ASPTX6"), | |
1953 | ||
1954 | CS42L43_MUX_ROUTES("DP1TX1", "DP1TX1"), | |
1955 | CS42L43_MUX_ROUTES("DP1TX2", "DP1TX2"), | |
1956 | CS42L43_MUX_ROUTES("DP1TX3", "DP1TX3"), | |
1957 | CS42L43_MUX_ROUTES("DP1TX4", "DP1TX4"), | |
1958 | CS42L43_MUX_ROUTES("DP2TX1", "DP2TX1"), | |
1959 | CS42L43_MUX_ROUTES("DP2TX2", "DP2TX2"), | |
1960 | CS42L43_MUX_ROUTES("DP3TX1", "DP3TX1"), | |
1961 | CS42L43_MUX_ROUTES("DP3TX2", "DP3TX2"), | |
1962 | CS42L43_MUX_ROUTES("DP4TX1", "DP4TX1"), | |
1963 | CS42L43_MUX_ROUTES("DP4TX2", "DP4TX2"), | |
1964 | ||
1965 | CS42L43_MUX_ROUTES("ASRC INT1", "ASRC_INT1"), | |
1966 | CS42L43_MUX_ROUTES("ASRC INT2", "ASRC_INT2"), | |
1967 | CS42L43_MUX_ROUTES("ASRC INT3", "ASRC_INT3"), | |
1968 | CS42L43_MUX_ROUTES("ASRC INT4", "ASRC_INT4"), | |
1969 | CS42L43_MUX_ROUTES("ASRC DEC1", "ASRC_DEC1"), | |
1970 | CS42L43_MUX_ROUTES("ASRC DEC2", "ASRC_DEC2"), | |
1971 | CS42L43_MUX_ROUTES("ASRC DEC3", "ASRC_DEC3"), | |
1972 | CS42L43_MUX_ROUTES("ASRC DEC4", "ASRC_DEC4"), | |
1973 | ||
1974 | CS42L43_MUX_ROUTES("ISRC1INT1", "ISRC1INT1"), | |
1975 | CS42L43_MUX_ROUTES("ISRC1INT2", "ISRC1INT2"), | |
1976 | CS42L43_MUX_ROUTES("ISRC1DEC1", "ISRC1DEC1"), | |
1977 | CS42L43_MUX_ROUTES("ISRC1DEC2", "ISRC1DEC2"), | |
1978 | CS42L43_MUX_ROUTES("ISRC2INT1", "ISRC2INT1"), | |
1979 | CS42L43_MUX_ROUTES("ISRC2INT2", "ISRC2INT2"), | |
1980 | CS42L43_MUX_ROUTES("ISRC2DEC1", "ISRC2DEC1"), | |
1981 | CS42L43_MUX_ROUTES("ISRC2DEC2", "ISRC2DEC2"), | |
1982 | ||
1983 | CS42L43_MUX_ROUTES("SPDIF1", "SPDIF"), | |
1984 | CS42L43_MUX_ROUTES("SPDIF2", "SPDIF"), | |
1985 | ||
1986 | CS42L43_MIXER_ROUTES("EQ1", "EQ"), | |
1987 | CS42L43_MIXER_ROUTES("EQ2", "EQ"), | |
1988 | ||
1989 | CS42L43_MIXER_ROUTES("Speaker L", "AMP1"), | |
1990 | CS42L43_MIXER_ROUTES("Speaker R", "AMP2"), | |
1991 | ||
1992 | CS42L43_MIXER_ROUTES("Headphone L", "HP"), | |
1993 | CS42L43_MIXER_ROUTES("Headphone R", "HP"), | |
1994 | }; | |
1995 | ||
1996 | static int cs42l43_set_sysclk(struct snd_soc_component *component, int clk_id, | |
1997 | int src, unsigned int freq, int dir) | |
1998 | { | |
1999 | struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); | |
2000 | struct cs42l43 *cs42l43 = priv->core; | |
2001 | int ret; | |
2002 | ||
2003 | mutex_lock(&cs42l43->pll_lock); | |
2004 | ret = cs42l43_set_pll(priv, src, freq); | |
2005 | mutex_unlock(&cs42l43->pll_lock); | |
2006 | ||
2007 | return ret; | |
2008 | } | |
2009 | ||
2010 | static int cs42l43_component_probe(struct snd_soc_component *component) | |
2011 | { | |
2012 | struct cs42l43_codec *priv = snd_soc_component_get_drvdata(component); | |
2013 | struct cs42l43 *cs42l43 = priv->core; | |
2014 | ||
2015 | snd_soc_component_init_regmap(component, cs42l43->regmap); | |
2016 | ||
2017 | cs42l43_mask_to_slots(priv, CS42L43_DEFAULT_SLOTS, priv->tx_slots); | |
2018 | cs42l43_mask_to_slots(priv, CS42L43_DEFAULT_SLOTS, priv->rx_slots); | |
2019 | ||
2020 | priv->component = component; | |
2021 | priv->constraint = cs42l43_constraint; | |
2022 | ||
2023 | return 0; | |
2024 | } | |
2025 | ||
2026 | static const struct snd_soc_component_driver cs42l43_component_drv = { | |
2027 | .name = "cs42l43-codec", | |
2028 | ||
2029 | .probe = cs42l43_component_probe, | |
2030 | .set_sysclk = cs42l43_set_sysclk, | |
2031 | .set_jack = cs42l43_set_jack, | |
2032 | ||
2033 | .endianness = 1, | |
2034 | ||
2035 | .controls = cs42l43_controls, | |
2036 | .num_controls = ARRAY_SIZE(cs42l43_controls), | |
2037 | .dapm_widgets = cs42l43_widgets, | |
2038 | .num_dapm_widgets = ARRAY_SIZE(cs42l43_widgets), | |
2039 | .dapm_routes = cs42l43_routes, | |
2040 | .num_dapm_routes = ARRAY_SIZE(cs42l43_routes), | |
2041 | }; | |
2042 | ||
2043 | struct cs42l43_irq { | |
2044 | unsigned int irq; | |
2045 | const char *name; | |
2046 | irq_handler_t handler; | |
2047 | }; | |
2048 | ||
2049 | static const struct cs42l43_irq cs42l43_irqs[] = { | |
2050 | { CS42L43_PLL_LOST_LOCK, "pll lost lock", cs42l43_pll_lost_lock }, | |
2051 | { CS42L43_PLL_READY, "pll ready", cs42l43_pll_ready }, | |
2052 | { CS42L43_HP_STARTUP_DONE, "hp startup", cs42l43_hp_startup }, | |
2053 | { CS42L43_HP_SHUTDOWN_DONE, "hp shutdown", cs42l43_hp_shutdown }, | |
2054 | { CS42L43_HSDET_DONE, "type detect", cs42l43_type_detect }, | |
2055 | { CS42L43_TIPSENSE_UNPLUG_PDET, "tip sense unplug", cs42l43_tip_sense }, | |
2056 | { CS42L43_TIPSENSE_PLUG_PDET, "tip sense plug", cs42l43_tip_sense }, | |
2057 | { CS42L43_DC_DETECT1_TRUE, "button press", cs42l43_button_press }, | |
2058 | { CS42L43_DC_DETECT1_FALSE, "button release", cs42l43_button_release }, | |
2059 | { CS42L43_HSBIAS_CLAMPED, "hsbias detect clamp", cs42l43_bias_detect_clamp }, | |
2060 | { CS42L43_AMP2_CLK_STOP_FAULT, "spkr clock stop", cs42l43_spkr_clock_stop }, | |
2061 | { CS42L43_AMP1_CLK_STOP_FAULT, "spkl clock stop", cs42l43_spkl_clock_stop }, | |
2062 | { CS42L43_AMP2_VDDSPK_FAULT, "spkr brown out", cs42l43_spkr_brown_out }, | |
2063 | { CS42L43_AMP1_VDDSPK_FAULT, "spkl brown out", cs42l43_spkl_brown_out }, | |
2064 | { CS42L43_AMP2_SHUTDOWN_DONE, "spkr shutdown", cs42l43_spkr_shutdown }, | |
2065 | { CS42L43_AMP1_SHUTDOWN_DONE, "spkl shutdown", cs42l43_spkl_shutdown }, | |
2066 | { CS42L43_AMP2_STARTUP_DONE, "spkr startup", cs42l43_spkr_startup }, | |
2067 | { CS42L43_AMP1_STARTUP_DONE, "spkl startup", cs42l43_spkl_startup }, | |
2068 | { CS42L43_AMP2_THERM_SHDN, "spkr thermal shutdown", cs42l43_spkr_therm_shutdown }, | |
2069 | { CS42L43_AMP1_THERM_SHDN, "spkl thermal shutdown", cs42l43_spkl_therm_shutdown }, | |
2070 | { CS42L43_AMP2_THERM_WARN, "spkr thermal warning", cs42l43_spkr_therm_warm }, | |
2071 | { CS42L43_AMP1_THERM_WARN, "spkl thermal warning", cs42l43_spkl_therm_warm }, | |
2072 | { CS42L43_AMP2_SCDET, "spkr short circuit", cs42l43_spkr_sc_detect }, | |
2073 | { CS42L43_AMP1_SCDET, "spkl short circuit", cs42l43_spkl_sc_detect }, | |
2074 | { CS42L43_HP_ILIMIT, "hp ilimit", cs42l43_hp_ilimit }, | |
2075 | { CS42L43_HP_LOADDET_DONE, "load detect done", cs42l43_load_detect }, | |
2076 | }; | |
2077 | ||
2078 | static int cs42l43_request_irq(struct cs42l43_codec *priv, | |
2079 | struct irq_domain *dom, const char * const name, | |
2080 | unsigned int irq, irq_handler_t handler) | |
2081 | { | |
2082 | int ret; | |
2083 | ||
2084 | ret = irq_create_mapping(dom, irq); | |
2085 | if (ret < 0) | |
2086 | return dev_err_probe(priv->dev, ret, "Failed to map IRQ %s\n", name); | |
2087 | ||
2088 | dev_dbg(priv->dev, "Request IRQ %d for %s\n", ret, name); | |
2089 | ||
2090 | ret = devm_request_threaded_irq(priv->dev, ret, NULL, handler, IRQF_ONESHOT, | |
2091 | name, priv); | |
2092 | if (ret) | |
2093 | return dev_err_probe(priv->dev, ret, "Failed to request IRQ %s\n", name); | |
2094 | ||
2095 | return 0; | |
2096 | } | |
2097 | ||
2098 | static int cs42l43_shutter_irq(struct cs42l43_codec *priv, | |
2099 | struct irq_domain *dom, unsigned int shutter, | |
2100 | const char * const open_name, | |
2101 | const char * const close_name, | |
2102 | irq_handler_t handler) | |
2103 | { | |
2104 | unsigned int open_irq, close_irq; | |
2105 | int ret; | |
2106 | ||
2107 | switch (shutter) { | |
2108 | case 0x1: | |
2109 | dev_warn(priv->dev, "Manual shutters, notifications not available\n"); | |
2110 | return 0; | |
2111 | case 0x2: | |
2112 | open_irq = CS42L43_GPIO1_RISE; | |
2113 | close_irq = CS42L43_GPIO1_FALL; | |
2114 | break; | |
2115 | case 0x4: | |
2116 | open_irq = CS42L43_GPIO2_RISE; | |
2117 | close_irq = CS42L43_GPIO2_FALL; | |
2118 | break; | |
2119 | case 0x8: | |
2120 | open_irq = CS42L43_GPIO3_RISE; | |
2121 | close_irq = CS42L43_GPIO3_FALL; | |
2122 | break; | |
2123 | default: | |
2124 | return 0; | |
2125 | } | |
2126 | ||
2127 | ret = cs42l43_request_irq(priv, dom, close_name, close_irq, handler); | |
2128 | if (ret) | |
2129 | return ret; | |
2130 | ||
2131 | return cs42l43_request_irq(priv, dom, open_name, open_irq, handler); | |
2132 | } | |
2133 | ||
2134 | static int cs42l43_codec_probe(struct platform_device *pdev) | |
2135 | { | |
2136 | struct cs42l43 *cs42l43 = dev_get_drvdata(pdev->dev.parent); | |
2137 | struct cs42l43_codec *priv; | |
2138 | struct irq_domain *dom; | |
2139 | unsigned int val; | |
2140 | int i, ret; | |
2141 | ||
2142 | dom = irq_find_matching_fwnode(dev_fwnode(cs42l43->dev), DOMAIN_BUS_ANY); | |
2143 | if (!dom) | |
2144 | return -EPROBE_DEFER; | |
2145 | ||
2146 | priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); | |
2147 | if (!priv) | |
2148 | return -ENOMEM; | |
2149 | ||
2150 | priv->dev = &pdev->dev; | |
2151 | priv->core = cs42l43; | |
2152 | ||
2153 | platform_set_drvdata(pdev, priv); | |
2154 | ||
2155 | mutex_init(&priv->jack_lock); | |
2156 | mutex_init(&priv->spk_vu_lock); | |
2157 | ||
2158 | init_completion(&priv->hp_startup); | |
2159 | init_completion(&priv->hp_shutdown); | |
2160 | init_completion(&priv->spkr_shutdown); | |
2161 | init_completion(&priv->spkl_shutdown); | |
2162 | init_completion(&priv->spkr_startup); | |
2163 | init_completion(&priv->spkl_startup); | |
2164 | init_completion(&priv->pll_ready); | |
2165 | init_completion(&priv->type_detect); | |
2166 | init_completion(&priv->load_detect); | |
2167 | ||
2168 | INIT_DELAYED_WORK(&priv->tip_sense_work, cs42l43_tip_sense_work); | |
2169 | INIT_DELAYED_WORK(&priv->bias_sense_timeout, cs42l43_bias_sense_timeout); | |
2170 | INIT_DELAYED_WORK(&priv->button_press_work, cs42l43_button_press_work); | |
2171 | INIT_WORK(&priv->button_release_work, cs42l43_button_release_work); | |
2172 | ||
2173 | pm_runtime_set_autosuspend_delay(priv->dev, 100); | |
2174 | pm_runtime_use_autosuspend(priv->dev); | |
2175 | pm_runtime_set_active(priv->dev); | |
2176 | pm_runtime_get_noresume(priv->dev); | |
2177 | devm_pm_runtime_enable(priv->dev); | |
2178 | ||
2179 | for (i = 0; i < ARRAY_SIZE(cs42l43_irqs); i++) { | |
2180 | ret = cs42l43_request_irq(priv, dom, cs42l43_irqs[i].name, | |
2181 | cs42l43_irqs[i].irq, cs42l43_irqs[i].handler); | |
2182 | if (ret) | |
2183 | goto err_pm; | |
2184 | } | |
2185 | ||
2186 | ret = regmap_read(cs42l43->regmap, CS42L43_SHUTTER_CONTROL, &val); | |
2187 | if (ret) { | |
2188 | dev_err(priv->dev, "Failed to check shutter source: %d\n", ret); | |
2189 | goto err_pm; | |
2190 | } | |
2191 | ||
2192 | ret = cs42l43_shutter_irq(priv, dom, val & CS42L43_MIC_SHUTTER_CFG_MASK, | |
2193 | "mic shutter open", "mic shutter close", | |
2194 | cs42l43_mic_shutter); | |
2195 | if (ret) | |
2196 | goto err_pm; | |
2197 | ||
2198 | ret = cs42l43_shutter_irq(priv, dom, (val & CS42L43_SPK_SHUTTER_CFG_MASK) >> | |
2199 | CS42L43_SPK_SHUTTER_CFG_SHIFT, | |
2200 | "spk shutter open", "spk shutter close", | |
2201 | cs42l43_spk_shutter); | |
2202 | if (ret) | |
2203 | goto err_pm; | |
2204 | ||
2205 | // Don't use devm as we need to get against the MFD device | |
2206 | priv->mclk = clk_get_optional(cs42l43->dev, "mclk"); | |
2207 | if (IS_ERR(priv->mclk)) { | |
2208 | dev_err_probe(priv->dev, PTR_ERR(priv->mclk), "Failed to get mclk\n"); | |
2209 | goto err_pm; | |
2210 | } | |
2211 | ||
2212 | ret = devm_snd_soc_register_component(priv->dev, &cs42l43_component_drv, | |
2213 | cs42l43_dais, ARRAY_SIZE(cs42l43_dais)); | |
2214 | if (ret) { | |
2215 | dev_err_probe(priv->dev, ret, "Failed to register component\n"); | |
2216 | goto err_clk; | |
2217 | } | |
2218 | ||
2219 | pm_runtime_mark_last_busy(priv->dev); | |
2220 | pm_runtime_put_autosuspend(priv->dev); | |
2221 | ||
2222 | return 0; | |
2223 | ||
2224 | err_clk: | |
2225 | clk_put(priv->mclk); | |
2226 | err_pm: | |
2227 | pm_runtime_put_sync(priv->dev); | |
2228 | ||
2229 | return ret; | |
2230 | } | |
2231 | ||
2232 | static int cs42l43_codec_remove(struct platform_device *pdev) | |
2233 | { | |
2234 | struct cs42l43_codec *priv = platform_get_drvdata(pdev); | |
2235 | ||
2236 | clk_put(priv->mclk); | |
2237 | ||
2238 | return 0; | |
2239 | } | |
2240 | ||
2b59332e | 2241 | static int cs42l43_codec_runtime_resume(struct device *dev) |
fc918cbe CK |
2242 | { |
2243 | struct cs42l43_codec *priv = dev_get_drvdata(dev); | |
2244 | ||
2245 | dev_dbg(priv->dev, "Runtime resume\n"); | |
2246 | ||
2247 | // Toggle the speaker volume update incase the speaker volume was synced | |
2248 | cs42l43_spk_vu_sync(priv); | |
2249 | ||
2250 | return 0; | |
2251 | } | |
2252 | ||
2b59332e CK |
2253 | DEFINE_RUNTIME_DEV_PM_OPS(cs42l43_codec_pm_ops, NULL, |
2254 | cs42l43_codec_runtime_resume, NULL); | |
fc918cbe CK |
2255 | |
2256 | static const struct platform_device_id cs42l43_codec_id_table[] = { | |
2257 | { "cs42l43-codec", }, | |
2258 | {} | |
2259 | }; | |
2260 | MODULE_DEVICE_TABLE(platform, cs42l43_codec_id_table); | |
2261 | ||
2262 | static struct platform_driver cs42l43_codec_driver = { | |
2263 | .driver = { | |
2264 | .name = "cs42l43-codec", | |
2265 | .pm = &cs42l43_codec_pm_ops, | |
2266 | }, | |
2267 | ||
2268 | .probe = cs42l43_codec_probe, | |
2269 | .remove = cs42l43_codec_remove, | |
2270 | .id_table = cs42l43_codec_id_table, | |
2271 | }; | |
2272 | module_platform_driver(cs42l43_codec_driver); | |
2273 | ||
2274 | MODULE_IMPORT_NS(SND_SOC_CS42L43); | |
2275 | ||
2276 | MODULE_DESCRIPTION("CS42L43 CODEC Driver"); | |
2277 | MODULE_AUTHOR("Charles Keepax <ckeepax@opensource.cirrus.com>"); | |
2278 | MODULE_LICENSE("GPL"); |