[linux-block.git] / sound / soc / codecs / cs42l42-sdw.c

// SPDX-License-Identifier: GPL-2.0-only
// cs42l42-sdw.c -- CS42L42 ALSA SoC audio driver SoundWire driver
//
// Copyright (C) 2022 Cirrus Logic, Inc. and
//                    Cirrus Logic International Semiconductor Ltd.

#include <linux/acpi.h>
#include <linux/device.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/of_irq.h>
#include <linux/pm_runtime.h>
#include <linux/soundwire/sdw.h>
#include <linux/soundwire/sdw_registers.h>
#include <linux/soundwire/sdw_type.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/sdw.h>
#include <sound/soc.h>

#include "cs42l42.h"

#define CS42L42_SDW_CAPTURE_PORT	1
#define CS42L42_SDW_PLAYBACK_PORT	2

/* Register addresses are offset when sent over SoundWire */
#define CS42L42_SDW_ADDR_OFFSET		0x8000

#define CS42L42_SDW_MEM_ACCESS_STATUS	0xd0
#define CS42L42_SDW_MEM_READ_DATA	0xd8

#define CS42L42_SDW_LAST_LATE		BIT(3)
#define CS42L42_SDW_CMD_IN_PROGRESS	BIT(2)
#define CS42L42_SDW_RDATA_RDY		BIT(0)

#define CS42L42_DELAYED_READ_POLL_US	1
#define CS42L42_DELAYED_READ_TIMEOUT_US	100

static const struct snd_soc_dapm_route cs42l42_sdw_audio_map[] = {
	/* Playback Path */
	{ "HP", NULL, "MIXER" },
	{ "MIXER", NULL, "DACSRC" },
	{ "DACSRC", NULL, "Playback" },

	/* Capture Path */
	{ "ADCSRC", NULL, "HS" },
	{ "Capture", NULL, "ADCSRC" },
};

static int cs42l42_sdw_dai_startup(struct snd_pcm_substream *substream,
				   struct snd_soc_dai *dai)
{
	struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(dai->component);

	if (!cs42l42->init_done)
		return -ENODEV;

	return 0;
}

static int cs42l42_sdw_dai_hw_params(struct snd_pcm_substream *substream,
				     struct snd_pcm_hw_params *params,
				     struct snd_soc_dai *dai)
{
	struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(dai->component);
	struct sdw_stream_runtime *sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
	struct sdw_stream_config stream_config = {0};
	struct sdw_port_config port_config = {0};
	int ret;

	if (!sdw_stream)
		return -EINVAL;

	/* Needed for PLL configuration when we are notified of new bus config */
	cs42l42->sample_rate = params_rate(params);

	snd_sdw_params_to_config(substream, params, &stream_config, &port_config);

	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		port_config.num = CS42L42_SDW_PLAYBACK_PORT;
	else
		port_config.num = CS42L42_SDW_CAPTURE_PORT;

	ret = sdw_stream_add_slave(cs42l42->sdw_peripheral, &stream_config, &port_config, 1,
				   sdw_stream);
	if (ret) {
		dev_err(dai->dev, "Failed to add sdw stream: %d\n", ret);
		return ret;
	}

	cs42l42_src_config(dai->component, params_rate(params));

	return 0;
}

static int cs42l42_sdw_dai_prepare(struct snd_pcm_substream *substream,
				   struct snd_soc_dai *dai)
{
	struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(dai->component);

	dev_dbg(dai->dev, "dai_prepare: sclk=%u rate=%u\n", cs42l42->sclk, cs42l42->sample_rate);

	if (!cs42l42->sclk || !cs42l42->sample_rate)
		return -EINVAL;

	/*
	 * At this point we know the sample rate from hw_params, and the SWIRE_CLK from bus_config()
	 * callback. This could only fail if the ACPI or machine driver are misconfigured to allow
	 * an unsupported SWIRE_CLK and sample_rate combination.
	 */

	return cs42l42_pll_config(dai->component, cs42l42->sclk, cs42l42->sample_rate);
}

static int cs42l42_sdw_dai_hw_free(struct snd_pcm_substream *substream,
				   struct snd_soc_dai *dai)
{
	struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(dai->component);
	struct sdw_stream_runtime *sdw_stream = snd_soc_dai_get_dma_data(dai, substream);

	sdw_stream_remove_slave(cs42l42->sdw_peripheral, sdw_stream);
	cs42l42->sample_rate = 0;

	return 0;
}

static int cs42l42_sdw_port_prep(struct sdw_slave *slave,
				 struct sdw_prepare_ch *prepare_ch,
				 enum sdw_port_prep_ops state)
{
	struct cs42l42_private *cs42l42 = dev_get_drvdata(&slave->dev);
	unsigned int pdn_mask;

	if (prepare_ch->num == CS42L42_SDW_PLAYBACK_PORT)
		pdn_mask = CS42L42_HP_PDN_MASK;
	else
		pdn_mask = CS42L42_ADC_PDN_MASK;

	if (state == SDW_OPS_PORT_PRE_PREP) {
		dev_dbg(cs42l42->dev, "Prep Port pdn_mask:%x\n", pdn_mask);
		regmap_clear_bits(cs42l42->regmap, CS42L42_PWR_CTL1, pdn_mask);
		usleep_range(CS42L42_HP_ADC_EN_TIME_US, CS42L42_HP_ADC_EN_TIME_US + 1000);
	} else if (state == SDW_OPS_PORT_POST_DEPREP) {
		dev_dbg(cs42l42->dev, "Deprep Port pdn_mask:%x\n", pdn_mask);
		regmap_set_bits(cs42l42->regmap, CS42L42_PWR_CTL1, pdn_mask);
	}

	return 0;
}

static int cs42l42_sdw_dai_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
					  int direction)
{
	if (!sdw_stream)
		return 0;

	if (direction == SNDRV_PCM_STREAM_PLAYBACK)
		dai->playback_dma_data = sdw_stream;
	else
		dai->capture_dma_data = sdw_stream;

	return 0;
}

static void cs42l42_sdw_dai_shutdown(struct snd_pcm_substream *substream,
				     struct snd_soc_dai *dai)
{
	snd_soc_dai_set_dma_data(dai, substream, NULL);
}

static const struct snd_soc_dai_ops cs42l42_sdw_dai_ops = {
	.startup	= cs42l42_sdw_dai_startup,
	.shutdown	= cs42l42_sdw_dai_shutdown,
	.hw_params	= cs42l42_sdw_dai_hw_params,
	.prepare	= cs42l42_sdw_dai_prepare,
	.hw_free	= cs42l42_sdw_dai_hw_free,
	.mute_stream	= cs42l42_mute_stream,
	.set_stream	= cs42l42_sdw_dai_set_sdw_stream,
};

static struct snd_soc_dai_driver cs42l42_sdw_dai = {
	.name = "cs42l42-sdw",
	.playback = {
		.stream_name = "Playback",
		.channels_min = 1,
		.channels_max = 2,
		/* Restrict which rates and formats are supported */
		.rates = SNDRV_PCM_RATE_8000_96000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE |
			   SNDRV_PCM_FMTBIT_S24_LE |
			   SNDRV_PCM_FMTBIT_S32_LE,
	},
	.capture = {
		.stream_name = "Capture",
		.channels_min = 1,
		.channels_max = 1,
		/* Restrict which rates and formats are supported */
		.rates = SNDRV_PCM_RATE_8000_96000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE |
			   SNDRV_PCM_FMTBIT_S24_LE |
			   SNDRV_PCM_FMTBIT_S32_LE,
	},
	.symmetric_rate = 1,
	.ops = &cs42l42_sdw_dai_ops,
};

static int cs42l42_sdw_poll_status(struct sdw_slave *peripheral, u8 mask, u8 match)
{
	int ret, sdwret;

	ret = read_poll_timeout(sdw_read_no_pm, sdwret,
				(sdwret < 0) || ((sdwret & mask) == match),
				CS42L42_DELAYED_READ_POLL_US, CS42L42_DELAYED_READ_TIMEOUT_US,
				false, peripheral, CS42L42_SDW_MEM_ACCESS_STATUS);
	if (ret == 0)
		ret = sdwret;

	if (ret < 0)
		dev_err(&peripheral->dev, "MEM_ACCESS_STATUS & %#x for %#x fail: %d\n",
			mask, match, ret);

	return ret;
}

static int cs42l42_sdw_read(void *context, unsigned int reg, unsigned int *val)
{
	struct sdw_slave *peripheral = context;
	u8 data;
	int ret;

	reg += CS42L42_SDW_ADDR_OFFSET;

	ret = cs42l42_sdw_poll_status(peripheral, CS42L42_SDW_CMD_IN_PROGRESS, 0);
	if (ret < 0)
		return ret;

	ret = sdw_read_no_pm(peripheral, reg);
	if (ret < 0) {
		dev_err(&peripheral->dev, "Failed to issue read @0x%x: %d\n", reg, ret);
		return ret;
	}

	data = (u8)ret;	/* possible non-delayed read value */
	ret = sdw_read_no_pm(peripheral, CS42L42_SDW_MEM_ACCESS_STATUS);
	if (ret < 0) {
		dev_err(&peripheral->dev, "Failed to read MEM_ACCESS_STATUS: %d\n", ret);
		return ret;
	}

	/* If read was not delayed we already have the result */
	if ((ret & CS42L42_SDW_LAST_LATE) == 0) {
		*val = data;
		return 0;
	}

	/* Poll for delayed read completion */
	if ((ret & CS42L42_SDW_RDATA_RDY) == 0) {
		ret = cs42l42_sdw_poll_status(peripheral,
					      CS42L42_SDW_RDATA_RDY, CS42L42_SDW_RDATA_RDY);
		if (ret < 0)
			return ret;
	}

	ret = sdw_read_no_pm(peripheral, CS42L42_SDW_MEM_READ_DATA);
	if (ret < 0) {
		dev_err(&peripheral->dev, "Failed to read READ_DATA: %d\n", ret);
		return ret;
	}

	*val = (u8)ret;

	return 0;
}

static int cs42l42_sdw_write(void *context, unsigned int reg, unsigned int val)
{
	struct sdw_slave *peripheral = context;
	int ret;

	ret = cs42l42_sdw_poll_status(peripheral, CS42L42_SDW_CMD_IN_PROGRESS, 0);
	if (ret < 0)
		return ret;

	return sdw_write_no_pm(peripheral, reg + CS42L42_SDW_ADDR_OFFSET, (u8)val);
}

/* Initialise cs42l42 using SoundWire - this is only called once, during initialisation */
static void cs42l42_sdw_init(struct sdw_slave *peripheral)
{
	struct cs42l42_private *cs42l42 = dev_get_drvdata(&peripheral->dev);
	int ret;

	regcache_cache_only(cs42l42->regmap, false);

	ret = cs42l42_init(cs42l42);
	if (ret < 0) {
		regcache_cache_only(cs42l42->regmap, true);
		goto err;
	}

	/* Write out any cached changes that happened between probe and attach */
	ret = regcache_sync(cs42l42->regmap);
	if (ret < 0)
		dev_warn(cs42l42->dev, "Failed to sync cache: %d\n", ret);

	/* Disable internal logic that makes clock-stop conditional */
	regmap_clear_bits(cs42l42->regmap, CS42L42_PWR_CTL3, CS42L42_SW_CLK_STP_STAT_SEL_MASK);

err:
	/* This cancels the pm_runtime_get_noresume() call from cs42l42_sdw_probe(). */
	pm_runtime_put_autosuspend(cs42l42->dev);
}

static int cs42l42_sdw_read_prop(struct sdw_slave *peripheral)
{
	struct cs42l42_private *cs42l42 = dev_get_drvdata(&peripheral->dev);
	struct sdw_slave_prop *prop = &peripheral->prop;
	struct sdw_dpn_prop *ports;

	ports = devm_kcalloc(cs42l42->dev, 2, sizeof(*ports), GFP_KERNEL);
	if (!ports)
		return -ENOMEM;

	prop->source_ports = BIT(CS42L42_SDW_CAPTURE_PORT);
	prop->sink_ports = BIT(CS42L42_SDW_PLAYBACK_PORT);
	prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
	prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;

	/* DP1 - capture */
	ports[0].num = CS42L42_SDW_CAPTURE_PORT,
	ports[0].type = SDW_DPN_FULL,
	ports[0].ch_prep_timeout = 10,
	prop->src_dpn_prop = &ports[0];

	/* DP2 - playback */
	ports[1].num = CS42L42_SDW_PLAYBACK_PORT,
	ports[1].type = SDW_DPN_FULL,
	ports[1].ch_prep_timeout = 10,
	prop->sink_dpn_prop = &ports[1];

	return 0;
}

static int cs42l42_sdw_update_status(struct sdw_slave *peripheral,
				     enum sdw_slave_status status)
{
	struct cs42l42_private *cs42l42 = dev_get_drvdata(&peripheral->dev);

	switch (status) {
	case SDW_SLAVE_ATTACHED:
		dev_dbg(cs42l42->dev, "ATTACHED\n");
		/*
		 * Initialise codec, this only needs to be done once.
		 * When resuming from suspend, resume callback will handle re-init of codec,
		 * using regcache_sync().
		 */
		if (!cs42l42->init_done)
			cs42l42_sdw_init(peripheral);
		break;
	case SDW_SLAVE_UNATTACHED:
		dev_dbg(cs42l42->dev, "UNATTACHED\n");
		break;
	default:
		break;
	}

	return 0;
}

static int cs42l42_sdw_bus_config(struct sdw_slave *peripheral,
				  struct sdw_bus_params *params)
{
	struct cs42l42_private *cs42l42 = dev_get_drvdata(&peripheral->dev);
	unsigned int new_sclk = params->curr_dr_freq / 2;

	/* The cs42l42 cannot support a glitchless SWIRE_CLK change. */
	if ((new_sclk != cs42l42->sclk) && cs42l42->stream_use) {
		dev_warn(cs42l42->dev, "Rejected SCLK change while audio active\n");
		return -EBUSY;
	}

	cs42l42->sclk = new_sclk;

	dev_dbg(cs42l42->dev, "bus_config: sclk=%u c=%u r=%u\n",
		cs42l42->sclk, params->col, params->row);

	return 0;
}

static const struct sdw_slave_ops cs42l42_sdw_ops = {
/* No interrupt callback because only hardware INT is supported for Jack Detect in the CS42L42 */
	.read_prop = cs42l42_sdw_read_prop,
	.update_status = cs42l42_sdw_update_status,
	.bus_config = cs42l42_sdw_bus_config,
	.port_prep = cs42l42_sdw_port_prep,
};

static int __maybe_unused cs42l42_sdw_runtime_suspend(struct device *dev)
{
	struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);

	dev_dbg(dev, "Runtime suspend\n");

	if (!cs42l42->init_done)
		return 0;

	/* The host controller could suspend, which would mean no register access */
	regcache_cache_only(cs42l42->regmap, true);

	return 0;
}

static const struct reg_sequence __maybe_unused cs42l42_soft_reboot_seq[] = {
	REG_SEQ0(CS42L42_SOFT_RESET_REBOOT, 0x1e),
};

static int __maybe_unused cs42l42_sdw_handle_unattach(struct cs42l42_private *cs42l42)
{
	struct sdw_slave *peripheral = cs42l42->sdw_peripheral;

	if (!peripheral->unattach_request)
		return 0;

	/* Cannot access registers until master re-attaches. */
	dev_dbg(&peripheral->dev, "Wait for initialization_complete\n");
	if (!wait_for_completion_timeout(&peripheral->initialization_complete,
					 msecs_to_jiffies(5000))) {
		dev_err(&peripheral->dev, "initialization_complete timed out\n");
		return -ETIMEDOUT;
	}

	peripheral->unattach_request = 0;

	/*
	 * After a bus reset there must be a reconfiguration reset to
	 * reinitialize the internal state of CS42L42.
	 */
	regmap_multi_reg_write_bypassed(cs42l42->regmap,
					cs42l42_soft_reboot_seq,
					ARRAY_SIZE(cs42l42_soft_reboot_seq));
	usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2);
	regcache_mark_dirty(cs42l42->regmap);

	return 0;
}

static int __maybe_unused cs42l42_sdw_runtime_resume(struct device *dev)
{
	struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
	int ret;

	dev_dbg(dev, "Runtime resume\n");

	if (!cs42l42->init_done)
		return 0;

	ret = cs42l42_sdw_handle_unattach(cs42l42);
	if (ret < 0)
		return ret;

	regcache_cache_only(cs42l42->regmap, false);

	/* Sync LATCH_TO_VP first so the VP domain registers sync correctly */
	regcache_sync_region(cs42l42->regmap, CS42L42_MIC_DET_CTL1, CS42L42_MIC_DET_CTL1);
	regcache_sync(cs42l42->regmap);

	return 0;
}

static int __maybe_unused cs42l42_sdw_resume(struct device *dev)
{
	struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
	int ret;

	dev_dbg(dev, "System resume\n");

	/* Power-up so it can re-enumerate */
	ret = cs42l42_resume(dev);
	if (ret)
		return ret;

	/* Wait for re-attach */
	ret = cs42l42_sdw_handle_unattach(cs42l42);
	if (ret < 0)
		return ret;

	cs42l42_resume_restore(dev);

	return 0;
}

static int cs42l42_sdw_probe(struct sdw_slave *peripheral, const struct sdw_device_id *id)
{
	struct snd_soc_component_driver *component_drv;
	struct device *dev = &peripheral->dev;
	struct cs42l42_private *cs42l42;
	struct regmap_config *regmap_conf;
	struct regmap *regmap;
	int irq, ret;

	cs42l42 = devm_kzalloc(dev, sizeof(*cs42l42), GFP_KERNEL);
	if (!cs42l42)
		return -ENOMEM;

	if (has_acpi_companion(dev))
		irq = acpi_dev_gpio_irq_get(ACPI_COMPANION(dev), 0);
	else
		irq = of_irq_get(dev->of_node, 0);

	if (irq == -ENOENT)
		irq = 0;
	else if (irq < 0)
		return dev_err_probe(dev, irq, "Failed to get IRQ\n");

	regmap_conf = devm_kmemdup(dev, &cs42l42_regmap, sizeof(cs42l42_regmap), GFP_KERNEL);
	if (!regmap_conf)
		return -ENOMEM;
	regmap_conf->reg_bits = 16;
	regmap_conf->num_ranges = 0;
	regmap_conf->reg_read = cs42l42_sdw_read;
	regmap_conf->reg_write = cs42l42_sdw_write;

	regmap = devm_regmap_init(dev, NULL, peripheral, regmap_conf);
	if (IS_ERR(regmap))
		return dev_err_probe(dev, PTR_ERR(regmap), "Failed to allocate register map\n");

	/* Start in cache-only until device is enumerated */
	regcache_cache_only(regmap, true);

	component_drv = devm_kmemdup(dev,
				     &cs42l42_soc_component,
				     sizeof(cs42l42_soc_component),
				     GFP_KERNEL);
	if (!component_drv)
		return -ENOMEM;

	component_drv->dapm_routes = cs42l42_sdw_audio_map;
	component_drv->num_dapm_routes = ARRAY_SIZE(cs42l42_sdw_audio_map);

	cs42l42->dev = dev;
	cs42l42->regmap = regmap;
	cs42l42->sdw_peripheral = peripheral;
	cs42l42->irq = irq;
	cs42l42->devid = CS42L42_CHIP_ID;

	/*
	 * pm_runtime is needed to control bus manager suspend, and to
	 * recover from an unattach_request when the manager suspends.
	 */
	pm_runtime_set_autosuspend_delay(cs42l42->dev, 3000);
	pm_runtime_use_autosuspend(cs42l42->dev);
	pm_runtime_mark_last_busy(cs42l42->dev);
	pm_runtime_set_active(cs42l42->dev);
	pm_runtime_get_noresume(cs42l42->dev);
	pm_runtime_enable(cs42l42->dev);

	ret = cs42l42_common_probe(cs42l42, component_drv, &cs42l42_sdw_dai);
	if (ret < 0)
		return ret;

	return 0;
}

static int cs42l42_sdw_remove(struct sdw_slave *peripheral)
{
	struct cs42l42_private *cs42l42 = dev_get_drvdata(&peripheral->dev);

	cs42l42_common_remove(cs42l42);
	pm_runtime_disable(cs42l42->dev);

	return 0;
}

static const struct dev_pm_ops cs42l42_sdw_pm = {
	SET_SYSTEM_SLEEP_PM_OPS(cs42l42_suspend, cs42l42_sdw_resume)
	SET_RUNTIME_PM_OPS(cs42l42_sdw_runtime_suspend, cs42l42_sdw_runtime_resume, NULL)
};

static const struct sdw_device_id cs42l42_sdw_id[] = {
	SDW_SLAVE_ENTRY(0x01FA, 0x4242, 0),
	{},
};
MODULE_DEVICE_TABLE(sdw, cs42l42_sdw_id);

static struct sdw_driver cs42l42_sdw_driver = {
	.driver = {
		.name = "cs42l42-sdw",
		.pm = &cs42l42_sdw_pm,
	},
	.probe = cs42l42_sdw_probe,
	.remove = cs42l42_sdw_remove,
	.ops = &cs42l42_sdw_ops,
	.id_table = cs42l42_sdw_id,
};

module_sdw_driver(cs42l42_sdw_driver);

MODULE_DESCRIPTION("ASoC CS42L42 SoundWire driver");
MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>");
MODULE_LICENSE("GPL");
MODULE_IMPORT_NS(SND_SOC_CS42L42_CORE);
Commit	Line	Data
90f6a2a2 RF	1	// SPDX-License-Identifier: GPL-2.0-only
	2	// cs42l42-sdw.c -- CS42L42 ALSA SoC audio driver SoundWire driver
	3	//
	4	// Copyright (C) 2022 Cirrus Logic, Inc. and
	5	// Cirrus Logic International Semiconductor Ltd.
	6
	7	#include <linux/acpi.h>
	8	#include <linux/device.h>
	9	#include <linux/iopoll.h>
	10	#include <linux/module.h>
	11	#include <linux/mod_devicetable.h>
	12	#include <linux/of_irq.h>
	13	#include <linux/pm_runtime.h>
	14	#include <linux/soundwire/sdw.h>
	15	#include <linux/soundwire/sdw_registers.h>
	16	#include <linux/soundwire/sdw_type.h>
	17	#include <sound/pcm.h>
	18	#include <sound/pcm_params.h>
	19	#include <sound/sdw.h>
	20	#include <sound/soc.h>
	21
	22	#include "cs42l42.h"
	23
	24	#define CS42L42_SDW_CAPTURE_PORT 1
	25	#define CS42L42_SDW_PLAYBACK_PORT 2
	26
	27	/* Register addresses are offset when sent over SoundWire */
	28	#define CS42L42_SDW_ADDR_OFFSET 0x8000
	29
	30	#define CS42L42_SDW_MEM_ACCESS_STATUS 0xd0
	31	#define CS42L42_SDW_MEM_READ_DATA 0xd8
	32
	33	#define CS42L42_SDW_LAST_LATE BIT(3)
	34	#define CS42L42_SDW_CMD_IN_PROGRESS BIT(2)
	35	#define CS42L42_SDW_RDATA_RDY BIT(0)
	36
	37	#define CS42L42_DELAYED_READ_POLL_US 1
	38	#define CS42L42_DELAYED_READ_TIMEOUT_US 100
	39
	40	static const struct snd_soc_dapm_route cs42l42_sdw_audio_map[] = {
	41	/* Playback Path */
	42	{ "HP", NULL, "MIXER" },
	43	{ "MIXER", NULL, "DACSRC" },
	44	{ "DACSRC", NULL, "Playback" },
	45
	46	/* Capture Path */
	47	{ "ADCSRC", NULL, "HS" },
	48	{ "Capture", NULL, "ADCSRC" },
	49	};
	50
	51	static int cs42l42_sdw_dai_startup(struct snd_pcm_substream *substream,
	52	struct snd_soc_dai *dai)
	53	{
	54	struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(dai->component);
	55
	56	if (!cs42l42->init_done)
	57	return -ENODEV;
	58
	59	return 0;
	60	}
	61
	62	static int cs42l42_sdw_dai_hw_params(struct snd_pcm_substream *substream,
	63	struct snd_pcm_hw_params *params,
	64	struct snd_soc_dai *dai)
65	{
66	struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(dai->component);
67	struct sdw_stream_runtime *sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
68	struct sdw_stream_config stream_config = {0};
69	struct sdw_port_config port_config = {0};
70	int ret;
71
72	if (!sdw_stream)
73	return -EINVAL;
74
75	/* Needed for PLL configuration when we are notified of new bus config */
76	cs42l42->sample_rate = params_rate(params);
77
78	snd_sdw_params_to_config(substream, params, &stream_config, &port_config);
79
80	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
81	port_config.num = CS42L42_SDW_PLAYBACK_PORT;
82	else
83	port_config.num = CS42L42_SDW_CAPTURE_PORT;
84
85	ret = sdw_stream_add_slave(cs42l42->sdw_peripheral, &stream_config, &port_config, 1,
86	sdw_stream);
87	if (ret) {
88	dev_err(dai->dev, "Failed to add sdw stream: %d\n", ret);
89	return ret;
90	}
91
92	cs42l42_src_config(dai->component, params_rate(params));
93
94	return 0;
95	}
96
97	static int cs42l42_sdw_dai_prepare(struct snd_pcm_substream *substream,
98	struct snd_soc_dai *dai)
99	{
100	struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(dai->component);
101
102	dev_dbg(dai->dev, "dai_prepare: sclk=%u rate=%u\n", cs42l42->sclk, cs42l42->sample_rate);
103
104	if (!cs42l42->sclk \|\| !cs42l42->sample_rate)
105	return -EINVAL;
106
107	/*
108	* At this point we know the sample rate from hw_params, and the SWIRE_CLK from bus_config()
109	* callback. This could only fail if the ACPI or machine driver are misconfigured to allow
110	* an unsupported SWIRE_CLK and sample_rate combination.
111	*/
112
113	return cs42l42_pll_config(dai->component, cs42l42->sclk, cs42l42->sample_rate);
114	}
115
116	static int cs42l42_sdw_dai_hw_free(struct snd_pcm_substream *substream,
117	struct snd_soc_dai *dai)
118	{
119	struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(dai->component);
120	struct sdw_stream_runtime *sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
121
122	sdw_stream_remove_slave(cs42l42->sdw_peripheral, sdw_stream);
123	cs42l42->sample_rate = 0;
124
125	return 0;
126	}
127
128	static int cs42l42_sdw_port_prep(struct sdw_slave *slave,
129	struct sdw_prepare_ch *prepare_ch,
130	enum sdw_port_prep_ops state)
131	{
132	struct cs42l42_private *cs42l42 = dev_get_drvdata(&slave->dev);
133	unsigned int pdn_mask;
134
135	if (prepare_ch->num == CS42L42_SDW_PLAYBACK_PORT)
136	pdn_mask = CS42L42_HP_PDN_MASK;
137	else
138	pdn_mask = CS42L42_ADC_PDN_MASK;
139
140	if (state == SDW_OPS_PORT_PRE_PREP) {
141	dev_dbg(cs42l42->dev, "Prep Port pdn_mask:%x\n", pdn_mask);
142	regmap_clear_bits(cs42l42->regmap, CS42L42_PWR_CTL1, pdn_mask);
143	usleep_range(CS42L42_HP_ADC_EN_TIME_US, CS42L42_HP_ADC_EN_TIME_US + 1000);
144	} else if (state == SDW_OPS_PORT_POST_DEPREP) {
145	dev_dbg(cs42l42->dev, "Deprep Port pdn_mask:%x\n", pdn_mask);
146	regmap_set_bits(cs42l42->regmap, CS42L42_PWR_CTL1, pdn_mask);
147	}
148
149	return 0;
150	}
151
152	static int cs42l42_sdw_dai_set_sdw_stream(struct snd_soc_dai dai, void sdw_stream,
153	int direction)
154	{
155	if (!sdw_stream)
156	return 0;
157
158	if (direction == SNDRV_PCM_STREAM_PLAYBACK)
159	dai->playback_dma_data = sdw_stream;
160	else
161	dai->capture_dma_data = sdw_stream;
162
163	return 0;
164	}
165
166	static void cs42l42_sdw_dai_shutdown(struct snd_pcm_substream *substream,
167	struct snd_soc_dai *dai)
168	{
169	snd_soc_dai_set_dma_data(dai, substream, NULL);
170	}
171
172	static const struct snd_soc_dai_ops cs42l42_sdw_dai_ops = {
173	.startup = cs42l42_sdw_dai_startup,
174	.shutdown = cs42l42_sdw_dai_shutdown,
175	.hw_params = cs42l42_sdw_dai_hw_params,
176	.prepare = cs42l42_sdw_dai_prepare,
177	.hw_free = cs42l42_sdw_dai_hw_free,
178	.mute_stream = cs42l42_mute_stream,
179	.set_stream = cs42l42_sdw_dai_set_sdw_stream,
180	};
181
182	static struct snd_soc_dai_driver cs42l42_sdw_dai = {
183	.name = "cs42l42-sdw",
184	.playback = {
185	.stream_name = "Playback",
186	.channels_min = 1,
187	.channels_max = 2,
188	/* Restrict which rates and formats are supported */
189	.rates = SNDRV_PCM_RATE_8000_96000,
190	.formats = SNDRV_PCM_FMTBIT_S16_LE \|
191	SNDRV_PCM_FMTBIT_S24_LE \|
192	SNDRV_PCM_FMTBIT_S32_LE,
193	},
194	.capture = {
195	.stream_name = "Capture",
196	.channels_min = 1,
197	.channels_max = 1,
198	/* Restrict which rates and formats are supported */
199	.rates = SNDRV_PCM_RATE_8000_96000,
200	.formats = SNDRV_PCM_FMTBIT_S16_LE \|
201	SNDRV_PCM_FMTBIT_S24_LE \|
202	SNDRV_PCM_FMTBIT_S32_LE,
203	},
204	.symmetric_rate = 1,
205	.ops = &cs42l42_sdw_dai_ops,
206	};
207
208	static int cs42l42_sdw_poll_status(struct sdw_slave *peripheral, u8 mask, u8 match)
209	{
210	int ret, sdwret;
211
212	ret = read_poll_timeout(sdw_read_no_pm, sdwret,
213	(sdwret < 0) \|\| ((sdwret & mask) == match),
214	CS42L42_DELAYED_READ_POLL_US, CS42L42_DELAYED_READ_TIMEOUT_US,
215	false, peripheral, CS42L42_SDW_MEM_ACCESS_STATUS);
216	if (ret == 0)
217	ret = sdwret;
218
219	if (ret < 0)
220	dev_err(&peripheral->dev, "MEM_ACCESS_STATUS & %#x for %#x fail: %d\n",
221	mask, match, ret);
222
223	return ret;
224	}
225
226	static int cs42l42_sdw_read(void context, unsigned int reg, unsigned int val)
227	{
228	struct sdw_slave *peripheral = context;
229	u8 data;
230	int ret;
231
232	reg += CS42L42_SDW_ADDR_OFFSET;
233
234	ret = cs42l42_sdw_poll_status(peripheral, CS42L42_SDW_CMD_IN_PROGRESS, 0);
235	if (ret < 0)
236	return ret;
237
238	ret = sdw_read_no_pm(peripheral, reg);
239	if (ret < 0) {
240	dev_err(&peripheral->dev, "Failed to issue read @0x%x: %d\n", reg, ret);
241	return ret;
242	}
243
244	data = (u8)ret; /* possible non-delayed read value */
245	ret = sdw_read_no_pm(peripheral, CS42L42_SDW_MEM_ACCESS_STATUS);
246	if (ret < 0) {
247	dev_err(&peripheral->dev, "Failed to read MEM_ACCESS_STATUS: %d\n", ret);
248	return ret;
249	}
250
251	/* If read was not delayed we already have the result */
252	if ((ret & CS42L42_SDW_LAST_LATE) == 0) {
253	*val = data;
254	return 0;
255	}
256
257	/* Poll for delayed read completion */
258	if ((ret & CS42L42_SDW_RDATA_RDY) == 0) {
259	ret = cs42l42_sdw_poll_status(peripheral,
260	CS42L42_SDW_RDATA_RDY, CS42L42_SDW_RDATA_RDY);
261	if (ret < 0)
262	return ret;
263	}
264
265	ret = sdw_read_no_pm(peripheral, CS42L42_SDW_MEM_READ_DATA);
266	if (ret < 0) {
267	dev_err(&peripheral->dev, "Failed to read READ_DATA: %d\n", ret);
268	return ret;
269	}
270
271	*val = (u8)ret;
272
273	return 0;
274	}
275
276	static int cs42l42_sdw_write(void *context, unsigned int reg, unsigned int val)
277	{
278	struct sdw_slave *peripheral = context;
279	int ret;
280
281	ret = cs42l42_sdw_poll_status(peripheral, CS42L42_SDW_CMD_IN_PROGRESS, 0);
282	if (ret < 0)
283	return ret;
284
285	return sdw_write_no_pm(peripheral, reg + CS42L42_SDW_ADDR_OFFSET, (u8)val);
286	}
287
288	/* Initialise cs42l42 using SoundWire - this is only called once, during initialisation */
289	static void cs42l42_sdw_init(struct sdw_slave *peripheral)
290	{
291	struct cs42l42_private *cs42l42 = dev_get_drvdata(&peripheral->dev);
292	int ret;
293
294	regcache_cache_only(cs42l42->regmap, false);
295
296	ret = cs42l42_init(cs42l42);
297	if (ret < 0) {
298	regcache_cache_only(cs42l42->regmap, true);
299	goto err;
300	}
301
302	/* Write out any cached changes that happened between probe and attach */
303	ret = regcache_sync(cs42l42->regmap);
304	if (ret < 0)
305	dev_warn(cs42l42->dev, "Failed to sync cache: %d\n", ret);
306
307	/* Disable internal logic that makes clock-stop conditional */
308	regmap_clear_bits(cs42l42->regmap, CS42L42_PWR_CTL3, CS42L42_SW_CLK_STP_STAT_SEL_MASK);
309
310	err:
311	/* This cancels the pm_runtime_get_noresume() call from cs42l42_sdw_probe(). */
312	pm_runtime_put_autosuspend(cs42l42->dev);
313	}
314
315	static int cs42l42_sdw_read_prop(struct sdw_slave *peripheral)
316	{
317	struct cs42l42_private *cs42l42 = dev_get_drvdata(&peripheral->dev);
318	struct sdw_slave_prop *prop = &peripheral->prop;
319	struct sdw_dpn_prop *ports;
320
321	ports = devm_kcalloc(cs42l42->dev, 2, sizeof(*ports), GFP_KERNEL);
322	if (!ports)
323	return -ENOMEM;
324
325	prop->source_ports = BIT(CS42L42_SDW_CAPTURE_PORT);
326	prop->sink_ports = BIT(CS42L42_SDW_PLAYBACK_PORT);
327	prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
328	prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH \| SDW_SCP_INT1_PARITY;
329
330	/* DP1 - capture */
331	ports[0].num = CS42L42_SDW_CAPTURE_PORT,
332	ports[0].type = SDW_DPN_FULL,
333	ports[0].ch_prep_timeout = 10,
334	prop->src_dpn_prop = &ports[0];
335
336	/* DP2 - playback */
337	ports[1].num = CS42L42_SDW_PLAYBACK_PORT,
338	ports[1].type = SDW_DPN_FULL,
339	ports[1].ch_prep_timeout = 10,
340	prop->sink_dpn_prop = &ports[1];
341
342	return 0;
343	}
344
345	static int cs42l42_sdw_update_status(struct sdw_slave *peripheral,
346	enum sdw_slave_status status)
347	{
348	struct cs42l42_private *cs42l42 = dev_get_drvdata(&peripheral->dev);
349
350	switch (status) {
351	case SDW_SLAVE_ATTACHED:
352	dev_dbg(cs42l42->dev, "ATTACHED\n");
353	/*
354	* Initialise codec, this only needs to be done once.
355	* When resuming from suspend, resume callback will handle re-init of codec,
356	* using regcache_sync().
357	*/
358	if (!cs42l42->init_done)
359	cs42l42_sdw_init(peripheral);
360	break;
361	case SDW_SLAVE_UNATTACHED:
362	dev_dbg(cs42l42->dev, "UNATTACHED\n");
363	break;
364	default:
365	break;
366	}
367
368	return 0;
369	}
370
371	static int cs42l42_sdw_bus_config(struct sdw_slave *peripheral,
372	struct sdw_bus_params *params)
373	{
374	struct cs42l42_private *cs42l42 = dev_get_drvdata(&peripheral->dev);
375	unsigned int new_sclk = params->curr_dr_freq / 2;
376
377	/* The cs42l42 cannot support a glitchless SWIRE_CLK change. */
378	if ((new_sclk != cs42l42->sclk) && cs42l42->stream_use) {
379	dev_warn(cs42l42->dev, "Rejected SCLK change while audio active\n");
380	return -EBUSY;
381	}
382
383	cs42l42->sclk = new_sclk;
384
385	dev_dbg(cs42l42->dev, "bus_config: sclk=%u c=%u r=%u\n",
386	cs42l42->sclk, params->col, params->row);
387
388	return 0;
389	}
390
391	static const struct sdw_slave_ops cs42l42_sdw_ops = {
392	/* No interrupt callback because only hardware INT is supported for Jack Detect in the CS42L42 */
393	.read_prop = cs42l42_sdw_read_prop,
394	.update_status = cs42l42_sdw_update_status,
395	.bus_config = cs42l42_sdw_bus_config,
396	.port_prep = cs42l42_sdw_port_prep,
397	};
398
399	static int __maybe_unused cs42l42_sdw_runtime_suspend(struct device *dev)
400	{
401	struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
402
403	dev_dbg(dev, "Runtime suspend\n");
404
405	if (!cs42l42->init_done)
406	return 0;
407
408	/* The host controller could suspend, which would mean no register access */
409	regcache_cache_only(cs42l42->regmap, true);
410
411	return 0;
412	}
413
414	static const struct reg_sequence __maybe_unused cs42l42_soft_reboot_seq[] = {
415	REG_SEQ0(CS42L42_SOFT_RESET_REBOOT, 0x1e),
416	};
417
418	static int __maybe_unused cs42l42_sdw_handle_unattach(struct cs42l42_private *cs42l42)
419	{
420	struct sdw_slave *peripheral = cs42l42->sdw_peripheral;
421
422	if (!peripheral->unattach_request)
423	return 0;
424
425	/* Cannot access registers until master re-attaches. */
426	dev_dbg(&peripheral->dev, "Wait for initialization_complete\n");
427	if (!wait_for_completion_timeout(&peripheral->initialization_complete,
428	msecs_to_jiffies(5000))) {
429	dev_err(&peripheral->dev, "initialization_complete timed out\n");
430	return -ETIMEDOUT;
431	}
432
433	peripheral->unattach_request = 0;
434
435	/*
436	* After a bus reset there must be a reconfiguration reset to
437	* reinitialize the internal state of CS42L42.
438	*/
439	regmap_multi_reg_write_bypassed(cs42l42->regmap,
440	cs42l42_soft_reboot_seq,
441	ARRAY_SIZE(cs42l42_soft_reboot_seq));
442	usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2);
443	regcache_mark_dirty(cs42l42->regmap);
444
445	return 0;
446	}
447
448	static int __maybe_unused cs42l42_sdw_runtime_resume(struct device *dev)
449	{
450	struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
451	int ret;
452
453	dev_dbg(dev, "Runtime resume\n");
454
455	if (!cs42l42->init_done)
456	return 0;
457
458	ret = cs42l42_sdw_handle_unattach(cs42l42);
459	if (ret < 0)
460	return ret;
461
462	regcache_cache_only(cs42l42->regmap, false);
463
464	/* Sync LATCH_TO_VP first so the VP domain registers sync correctly */
465	regcache_sync_region(cs42l42->regmap, CS42L42_MIC_DET_CTL1, CS42L42_MIC_DET_CTL1);
466	regcache_sync(cs42l42->regmap);
467
468	return 0;
469	}
470
471	static int __maybe_unused cs42l42_sdw_resume(struct device *dev)
472	{
473	struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
474	int ret;
475
476	dev_dbg(dev, "System resume\n");
477
478	/* Power-up so it can re-enumerate */
479	ret = cs42l42_resume(dev);
480	if (ret)
481	return ret;
482
483	/* Wait for re-attach */
484	ret = cs42l42_sdw_handle_unattach(cs42l42);
485	if (ret < 0)
486	return ret;
487
488	cs42l42_resume_restore(dev);
489
490	return 0;
491	}
492
493	static int cs42l42_sdw_probe(struct sdw_slave peripheral, const struct sdw_device_id id)
494	{
495	struct snd_soc_component_driver *component_drv;
496	struct device *dev = &peripheral->dev;
497	struct cs42l42_private *cs42l42;
498	struct regmap_config *regmap_conf;
499	struct regmap *regmap;
500	int irq, ret;
501
502	cs42l42 = devm_kzalloc(dev, sizeof(*cs42l42), GFP_KERNEL);
503	if (!cs42l42)
504	return -ENOMEM;
505
506	if (has_acpi_companion(dev))
507	irq = acpi_dev_gpio_irq_get(ACPI_COMPANION(dev), 0);
508	else
509	irq = of_irq_get(dev->of_node, 0);
510
511	if (irq == -ENOENT)
512	irq = 0;
513	else if (irq < 0)
514	return dev_err_probe(dev, irq, "Failed to get IRQ\n");
515
516	regmap_conf = devm_kmemdup(dev, &cs42l42_regmap, sizeof(cs42l42_regmap), GFP_KERNEL);
517	if (!regmap_conf)
518	return -ENOMEM;
519	regmap_conf->reg_bits = 16;
520	regmap_conf->num_ranges = 0;
521	regmap_conf->reg_read = cs42l42_sdw_read;
522	regmap_conf->reg_write = cs42l42_sdw_write;
523
524	regmap = devm_regmap_init(dev, NULL, peripheral, regmap_conf);
525	if (IS_ERR(regmap))
526	return dev_err_probe(dev, PTR_ERR(regmap), "Failed to allocate register map\n");
527
528	/* Start in cache-only until device is enumerated */
529	regcache_cache_only(regmap, true);
530
531	component_drv = devm_kmemdup(dev,
532	&cs42l42_soc_component,
533	sizeof(cs42l42_soc_component),
534	GFP_KERNEL);
535	if (!component_drv)
536	return -ENOMEM;
537
538	component_drv->dapm_routes = cs42l42_sdw_audio_map;
539	component_drv->num_dapm_routes = ARRAY_SIZE(cs42l42_sdw_audio_map);
540
541	cs42l42->dev = dev;
542	cs42l42->regmap = regmap;
543	cs42l42->sdw_peripheral = peripheral;
544	cs42l42->irq = irq;
545	cs42l42->devid = CS42L42_CHIP_ID;
546
547	/*
548	* pm_runtime is needed to control bus manager suspend, and to
549	* recover from an unattach_request when the manager suspends.
550	*/
551	pm_runtime_set_autosuspend_delay(cs42l42->dev, 3000);
552	pm_runtime_use_autosuspend(cs42l42->dev);
553	pm_runtime_mark_last_busy(cs42l42->dev);
554	pm_runtime_set_active(cs42l42->dev);
555	pm_runtime_get_noresume(cs42l42->dev);
556	pm_runtime_enable(cs42l42->dev);
557
558	ret = cs42l42_common_probe(cs42l42, component_drv, &cs42l42_sdw_dai);
559	if (ret < 0)
560	return ret;
561
562	return 0;
563	}
564
565	static int cs42l42_sdw_remove(struct sdw_slave *peripheral)
566	{
567	struct cs42l42_private *cs42l42 = dev_get_drvdata(&peripheral->dev);
568
569	cs42l42_common_remove(cs42l42);
570	pm_runtime_disable(cs42l42->dev);
571
572	return 0;
573	}
574
575	static const struct dev_pm_ops cs42l42_sdw_pm = {
576	SET_SYSTEM_SLEEP_PM_OPS(cs42l42_suspend, cs42l42_sdw_resume)
577	SET_RUNTIME_PM_OPS(cs42l42_sdw_runtime_suspend, cs42l42_sdw_runtime_resume, NULL)
578	};
579
580	static const struct sdw_device_id cs42l42_sdw_id[] = {
581	SDW_SLAVE_ENTRY(0x01FA, 0x4242, 0),
582	{},
583	};
584	MODULE_DEVICE_TABLE(sdw, cs42l42_sdw_id);
585
586	static struct sdw_driver cs42l42_sdw_driver = {
587	.driver = {
588	.name = "cs42l42-sdw",
589	.pm = &cs42l42_sdw_pm,
590	},
591	.probe = cs42l42_sdw_probe,
592	.remove = cs42l42_sdw_remove,
593	.ops = &cs42l42_sdw_ops,
594	.id_table = cs42l42_sdw_id,
595	};
596
597	module_sdw_driver(cs42l42_sdw_driver);
598
599	MODULE_DESCRIPTION("ASoC CS42L42 SoundWire driver");
600	MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>");
601	MODULE_LICENSE("GPL");
602	MODULE_IMPORT_NS(SND_SOC_CS42L42_CORE);