Commit | Line | Data |
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b0c813ce TT |
1 | /* |
2 | * CS4270 ALSA SoC (ASoC) codec driver | |
3 | * | |
4 | * Author: Timur Tabi <timur@freescale.com> | |
5 | * | |
ff7bf02f TT |
6 | * Copyright 2007-2009 Freescale Semiconductor, Inc. This file is licensed |
7 | * under the terms of the GNU General Public License version 2. This | |
8 | * program is licensed "as is" without any warranty of any kind, whether | |
9 | * express or implied. | |
b0c813ce TT |
10 | * |
11 | * This is an ASoC device driver for the Cirrus Logic CS4270 codec. | |
12 | * | |
13 | * Current features/limitations: | |
14 | * | |
b191f63c DM |
15 | * - Software mode is supported. Stand-alone mode is not supported. |
16 | * - Only I2C is supported, not SPI | |
17 | * - Support for master and slave mode | |
18 | * - The machine driver's 'startup' function must call | |
19 | * cs4270_set_dai_sysclk() with the value of MCLK. | |
20 | * - Only I2S and left-justified modes are supported | |
5e7c0344 | 21 | * - Power management is supported |
b0c813ce TT |
22 | */ |
23 | ||
340d79a1 | 24 | #include <linux/mod_devicetable.h> |
b0c813ce | 25 | #include <linux/module.h> |
5a0e3ad6 | 26 | #include <linux/slab.h> |
b0c813ce TT |
27 | #include <sound/core.h> |
28 | #include <sound/soc.h> | |
29 | #include <sound/initval.h> | |
30 | #include <linux/i2c.h> | |
5e7c0344 | 31 | #include <linux/delay.h> |
ffbfd336 | 32 | #include <linux/regulator/consumer.h> |
f98acd8a | 33 | #include <linux/gpio/consumer.h> |
b0c813ce | 34 | |
99a4b91a CK |
35 | #define CS4270_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \ |
36 | SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \ | |
37 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE) | |
8432395f | 38 | |
8432395f TT |
39 | /* CS4270 registers addresses */ |
40 | #define CS4270_CHIPID 0x01 /* Chip ID */ | |
41 | #define CS4270_PWRCTL 0x02 /* Power Control */ | |
42 | #define CS4270_MODE 0x03 /* Mode Control */ | |
43 | #define CS4270_FORMAT 0x04 /* Serial Format, ADC/DAC Control */ | |
44 | #define CS4270_TRANS 0x05 /* Transition Control */ | |
45 | #define CS4270_MUTE 0x06 /* Mute Control */ | |
46 | #define CS4270_VOLA 0x07 /* DAC Channel A Volume Control */ | |
47 | #define CS4270_VOLB 0x08 /* DAC Channel B Volume Control */ | |
48 | ||
49 | #define CS4270_FIRSTREG 0x01 | |
50 | #define CS4270_LASTREG 0x08 | |
51 | #define CS4270_NUMREGS (CS4270_LASTREG - CS4270_FIRSTREG + 1) | |
80ab8817 | 52 | #define CS4270_I2C_INCR 0x80 |
9dbd627b | 53 | |
8432395f TT |
54 | /* Bit masks for the CS4270 registers */ |
55 | #define CS4270_CHIPID_ID 0xF0 | |
56 | #define CS4270_CHIPID_REV 0x0F | |
57 | #define CS4270_PWRCTL_FREEZE 0x80 | |
58 | #define CS4270_PWRCTL_PDN_ADC 0x20 | |
59 | #define CS4270_PWRCTL_PDN_DAC 0x02 | |
60 | #define CS4270_PWRCTL_PDN 0x01 | |
5e7c0344 DM |
61 | #define CS4270_PWRCTL_PDN_ALL \ |
62 | (CS4270_PWRCTL_PDN_ADC | CS4270_PWRCTL_PDN_DAC | CS4270_PWRCTL_PDN) | |
8432395f TT |
63 | #define CS4270_MODE_SPEED_MASK 0x30 |
64 | #define CS4270_MODE_1X 0x00 | |
65 | #define CS4270_MODE_2X 0x10 | |
66 | #define CS4270_MODE_4X 0x20 | |
67 | #define CS4270_MODE_SLAVE 0x30 | |
68 | #define CS4270_MODE_DIV_MASK 0x0E | |
69 | #define CS4270_MODE_DIV1 0x00 | |
70 | #define CS4270_MODE_DIV15 0x02 | |
71 | #define CS4270_MODE_DIV2 0x04 | |
72 | #define CS4270_MODE_DIV3 0x06 | |
73 | #define CS4270_MODE_DIV4 0x08 | |
74 | #define CS4270_MODE_POPGUARD 0x01 | |
75 | #define CS4270_FORMAT_FREEZE_A 0x80 | |
76 | #define CS4270_FORMAT_FREEZE_B 0x40 | |
77 | #define CS4270_FORMAT_LOOPBACK 0x20 | |
78 | #define CS4270_FORMAT_DAC_MASK 0x18 | |
79 | #define CS4270_FORMAT_DAC_LJ 0x00 | |
80 | #define CS4270_FORMAT_DAC_I2S 0x08 | |
81 | #define CS4270_FORMAT_DAC_RJ16 0x18 | |
82 | #define CS4270_FORMAT_DAC_RJ24 0x10 | |
83 | #define CS4270_FORMAT_ADC_MASK 0x01 | |
84 | #define CS4270_FORMAT_ADC_LJ 0x00 | |
85 | #define CS4270_FORMAT_ADC_I2S 0x01 | |
86 | #define CS4270_TRANS_ONE_VOL 0x80 | |
87 | #define CS4270_TRANS_SOFT 0x40 | |
88 | #define CS4270_TRANS_ZERO 0x20 | |
89 | #define CS4270_TRANS_INV_ADC_A 0x08 | |
90 | #define CS4270_TRANS_INV_ADC_B 0x10 | |
91 | #define CS4270_TRANS_INV_DAC_A 0x02 | |
92 | #define CS4270_TRANS_INV_DAC_B 0x04 | |
93 | #define CS4270_TRANS_DEEMPH 0x01 | |
94 | #define CS4270_MUTE_AUTO 0x20 | |
95 | #define CS4270_MUTE_ADC_A 0x08 | |
96 | #define CS4270_MUTE_ADC_B 0x10 | |
97 | #define CS4270_MUTE_POLARITY 0x04 | |
98 | #define CS4270_MUTE_DAC_A 0x01 | |
99 | #define CS4270_MUTE_DAC_B 0x02 | |
100 | ||
11b8fca5 TT |
101 | /* Power-on default values for the registers |
102 | * | |
103 | * This array contains the power-on default values of the registers, with the | |
104 | * exception of the "CHIPID" register (01h). The lower four bits of that | |
105 | * register contain the hardware revision, so it is treated as volatile. | |
11b8fca5 | 106 | */ |
1ca65175 MB |
107 | static const struct reg_default cs4270_reg_defaults[] = { |
108 | { 2, 0x00 }, | |
109 | { 3, 0x30 }, | |
110 | { 4, 0x00 }, | |
111 | { 5, 0x60 }, | |
112 | { 6, 0x20 }, | |
113 | { 7, 0x00 }, | |
114 | { 8, 0x00 }, | |
11b8fca5 TT |
115 | }; |
116 | ||
ffbfd336 DM |
117 | static const char *supply_names[] = { |
118 | "va", "vd", "vlc" | |
119 | }; | |
120 | ||
0db4d070 TT |
121 | /* Private data for the CS4270 */ |
122 | struct cs4270_private { | |
1ca65175 | 123 | struct regmap *regmap; |
0db4d070 TT |
124 | unsigned int mclk; /* Input frequency of the MCLK pin */ |
125 | unsigned int mode; /* The mode (I2S or left-justified) */ | |
4eae080d | 126 | unsigned int slave_mode; |
1a4ba05e | 127 | unsigned int manual_mute; |
ffbfd336 DM |
128 | |
129 | /* power domain regulators */ | |
130 | struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)]; | |
ccfc5316 MW |
131 | |
132 | /* reset gpio */ | |
133 | struct gpio_desc *reset_gpio; | |
0db4d070 TT |
134 | }; |
135 | ||
782fbaba MB |
136 | static const struct snd_soc_dapm_widget cs4270_dapm_widgets[] = { |
137 | SND_SOC_DAPM_INPUT("AINL"), | |
138 | SND_SOC_DAPM_INPUT("AINR"), | |
139 | ||
140 | SND_SOC_DAPM_OUTPUT("AOUTL"), | |
141 | SND_SOC_DAPM_OUTPUT("AOUTR"), | |
142 | }; | |
143 | ||
144 | static const struct snd_soc_dapm_route cs4270_dapm_routes[] = { | |
aa5f9209 | 145 | { "Capture", NULL, "AINL" }, |
146 | { "Capture", NULL, "AINR" }, | |
782fbaba | 147 | |
aa5f9209 | 148 | { "AOUTL", NULL, "Playback" }, |
149 | { "AOUTR", NULL, "Playback" }, | |
782fbaba MB |
150 | }; |
151 | ||
ff7bf02f TT |
152 | /** |
153 | * struct cs4270_mode_ratios - clock ratio tables | |
154 | * @ratio: the ratio of MCLK to the sample rate | |
155 | * @speed_mode: the Speed Mode bits to set in the Mode Control register for | |
156 | * this ratio | |
157 | * @mclk: the Ratio Select bits to set in the Mode Control register for this | |
158 | * ratio | |
8432395f TT |
159 | * |
160 | * The data for this chart is taken from Table 5 of the CS4270 reference | |
161 | * manual. | |
162 | * | |
163 | * This table is used to determine how to program the Mode Control register. | |
164 | * It is also used by cs4270_set_dai_sysclk() to tell ALSA which sampling | |
165 | * rates the CS4270 currently supports. | |
166 | * | |
ff7bf02f | 167 | * @speed_mode is the corresponding bit pattern to be written to the |
8432395f TT |
168 | * MODE bits of the Mode Control Register |
169 | * | |
ff7bf02f | 170 | * @mclk is the corresponding bit pattern to be wirten to the MCLK bits of |
8432395f TT |
171 | * the Mode Control Register. |
172 | * | |
173 | * In situations where a single ratio is represented by multiple speed | |
174 | * modes, we favor the slowest speed. E.g, for a ratio of 128, we pick | |
175 | * double-speed instead of quad-speed. However, the CS4270 errata states | |
ff7bf02f | 176 | * that divide-By-1.5 can cause failures, so we avoid that mode where |
8432395f TT |
177 | * possible. |
178 | * | |
ff7bf02f TT |
179 | * Errata: There is an errata for the CS4270 where divide-by-1.5 does not |
180 | * work if Vd is 3.3V. If this effects you, select the | |
8432395f TT |
181 | * CONFIG_SND_SOC_CS4270_VD33_ERRATA Kconfig option, and the driver will |
182 | * never select any sample rates that require divide-by-1.5. | |
183 | */ | |
ff7bf02f | 184 | struct cs4270_mode_ratios { |
8432395f TT |
185 | unsigned int ratio; |
186 | u8 speed_mode; | |
187 | u8 mclk; | |
ff7bf02f TT |
188 | }; |
189 | ||
d9fb7fbd | 190 | static struct cs4270_mode_ratios cs4270_mode_ratios[] = { |
8432395f TT |
191 | {64, CS4270_MODE_4X, CS4270_MODE_DIV1}, |
192 | #ifndef CONFIG_SND_SOC_CS4270_VD33_ERRATA | |
193 | {96, CS4270_MODE_4X, CS4270_MODE_DIV15}, | |
194 | #endif | |
195 | {128, CS4270_MODE_2X, CS4270_MODE_DIV1}, | |
196 | {192, CS4270_MODE_4X, CS4270_MODE_DIV3}, | |
197 | {256, CS4270_MODE_1X, CS4270_MODE_DIV1}, | |
198 | {384, CS4270_MODE_2X, CS4270_MODE_DIV3}, | |
199 | {512, CS4270_MODE_1X, CS4270_MODE_DIV2}, | |
200 | {768, CS4270_MODE_1X, CS4270_MODE_DIV3}, | |
201 | {1024, CS4270_MODE_1X, CS4270_MODE_DIV4} | |
202 | }; | |
203 | ||
204 | /* The number of MCLK/LRCK ratios supported by the CS4270 */ | |
205 | #define NUM_MCLK_RATIOS ARRAY_SIZE(cs4270_mode_ratios) | |
9dbd627b | 206 | |
1ca65175 | 207 | static bool cs4270_reg_is_readable(struct device *dev, unsigned int reg) |
11b8fca5 TT |
208 | { |
209 | return (reg >= CS4270_FIRSTREG) && (reg <= CS4270_LASTREG); | |
210 | } | |
211 | ||
1ca65175 | 212 | static bool cs4270_reg_is_volatile(struct device *dev, unsigned int reg) |
11b8fca5 TT |
213 | { |
214 | /* Unreadable registers are considered volatile */ | |
215 | if ((reg < CS4270_FIRSTREG) || (reg > CS4270_LASTREG)) | |
c34c4515 | 216 | return true; |
11b8fca5 TT |
217 | |
218 | return reg == CS4270_CHIPID; | |
219 | } | |
220 | ||
ff7bf02f TT |
221 | /** |
222 | * cs4270_set_dai_sysclk - determine the CS4270 samples rates. | |
223 | * @codec_dai: the codec DAI | |
224 | * @clk_id: the clock ID (ignored) | |
225 | * @freq: the MCLK input frequency | |
226 | * @dir: the clock direction (ignored) | |
9dbd627b | 227 | * |
ff7bf02f TT |
228 | * This function is used to tell the codec driver what the input MCLK |
229 | * frequency is. | |
9dbd627b TT |
230 | * |
231 | * The value of MCLK is used to determine which sample rates are supported | |
232 | * by the CS4270. The ratio of MCLK / Fs must be equal to one of nine | |
ff7bf02f | 233 | * supported values - 64, 96, 128, 192, 256, 384, 512, 768, and 1024. |
9dbd627b TT |
234 | * |
235 | * This function calculates the nine ratios and determines which ones match | |
236 | * a standard sample rate. If there's a match, then it is added to the list | |
ff7bf02f | 237 | * of supported sample rates. |
9dbd627b TT |
238 | * |
239 | * This function must be called by the machine driver's 'startup' function, | |
240 | * otherwise the list of supported sample rates will not be available in | |
241 | * time for ALSA. | |
6aababdf DM |
242 | * |
243 | * For setups with variable MCLKs, pass 0 as 'freq' argument. This will cause | |
244 | * theoretically possible sample rates to be enabled. Call it again with a | |
245 | * proper value set one the external clock is set (most probably you would do | |
246 | * that from a machine's driver 'hw_param' hook. | |
9dbd627b | 247 | */ |
e550e17f | 248 | static int cs4270_set_dai_sysclk(struct snd_soc_dai *codec_dai, |
9dbd627b TT |
249 | int clk_id, unsigned int freq, int dir) |
250 | { | |
70c9a803 KM |
251 | struct snd_soc_component *component = codec_dai->component; |
252 | struct cs4270_private *cs4270 = snd_soc_component_get_drvdata(component); | |
9dbd627b TT |
253 | |
254 | cs4270->mclk = freq; | |
9dbd627b TT |
255 | return 0; |
256 | } | |
257 | ||
ff7bf02f TT |
258 | /** |
259 | * cs4270_set_dai_fmt - configure the codec for the selected audio format | |
260 | * @codec_dai: the codec DAI | |
261 | * @format: a SND_SOC_DAIFMT_x value indicating the data format | |
9dbd627b TT |
262 | * |
263 | * This function takes a bitmask of SND_SOC_DAIFMT_x bits and programs the | |
264 | * codec accordingly. | |
265 | * | |
266 | * Currently, this function only supports SND_SOC_DAIFMT_I2S and | |
267 | * SND_SOC_DAIFMT_LEFT_J. The CS4270 codec also supports right-justified | |
268 | * data for playback only, but ASoC currently does not support different | |
269 | * formats for playback vs. record. | |
270 | */ | |
e550e17f | 271 | static int cs4270_set_dai_fmt(struct snd_soc_dai *codec_dai, |
9dbd627b TT |
272 | unsigned int format) |
273 | { | |
70c9a803 KM |
274 | struct snd_soc_component *component = codec_dai->component; |
275 | struct cs4270_private *cs4270 = snd_soc_component_get_drvdata(component); | |
9dbd627b | 276 | |
4eae080d | 277 | /* set DAI format */ |
9dbd627b TT |
278 | switch (format & SND_SOC_DAIFMT_FORMAT_MASK) { |
279 | case SND_SOC_DAIFMT_I2S: | |
280 | case SND_SOC_DAIFMT_LEFT_J: | |
281 | cs4270->mode = format & SND_SOC_DAIFMT_FORMAT_MASK; | |
282 | break; | |
283 | default: | |
70c9a803 | 284 | dev_err(component->dev, "invalid dai format\n"); |
ac60155f | 285 | return -EINVAL; |
9dbd627b TT |
286 | } |
287 | ||
4eae080d DM |
288 | /* set master/slave audio interface */ |
289 | switch (format & SND_SOC_DAIFMT_MASTER_MASK) { | |
290 | case SND_SOC_DAIFMT_CBS_CFS: | |
291 | cs4270->slave_mode = 1; | |
292 | break; | |
293 | case SND_SOC_DAIFMT_CBM_CFM: | |
294 | cs4270->slave_mode = 0; | |
295 | break; | |
4eae080d | 296 | default: |
ff09d49a | 297 | /* all other modes are unsupported by the hardware */ |
70c9a803 | 298 | dev_err(component->dev, "Unknown master/slave configuration\n"); |
ac60155f | 299 | return -EINVAL; |
4eae080d DM |
300 | } |
301 | ||
ac60155f | 302 | return 0; |
9dbd627b TT |
303 | } |
304 | ||
ff7bf02f TT |
305 | /** |
306 | * cs4270_hw_params - program the CS4270 with the given hardware parameters. | |
307 | * @substream: the audio stream | |
308 | * @params: the hardware parameters to set | |
309 | * @dai: the SOC DAI (ignored) | |
b0c813ce | 310 | * |
ff7bf02f TT |
311 | * This function programs the hardware with the values provided. |
312 | * Specifically, the sample rate and the data format. | |
313 | * | |
314 | * The .ops functions are used to provide board-specific data, like input | |
315 | * frequencies, to this driver. This function takes that information, | |
b0c813ce TT |
316 | * combines it with the hardware parameters provided, and programs the |
317 | * hardware accordingly. | |
318 | */ | |
319 | static int cs4270_hw_params(struct snd_pcm_substream *substream, | |
dee89c4d MB |
320 | struct snd_pcm_hw_params *params, |
321 | struct snd_soc_dai *dai) | |
b0c813ce | 322 | { |
70c9a803 KM |
323 | struct snd_soc_component *component = dai->component; |
324 | struct cs4270_private *cs4270 = snd_soc_component_get_drvdata(component); | |
e34ba212 | 325 | int ret; |
b0c813ce TT |
326 | unsigned int i; |
327 | unsigned int rate; | |
328 | unsigned int ratio; | |
329 | int reg; | |
330 | ||
331 | /* Figure out which MCLK/LRCK ratio to use */ | |
332 | ||
333 | rate = params_rate(params); /* Sampling rate, in Hz */ | |
334 | ratio = cs4270->mclk / rate; /* MCLK/LRCK ratio */ | |
335 | ||
9dbd627b | 336 | for (i = 0; i < NUM_MCLK_RATIOS; i++) { |
8432395f | 337 | if (cs4270_mode_ratios[i].ratio == ratio) |
b0c813ce TT |
338 | break; |
339 | } | |
340 | ||
9dbd627b | 341 | if (i == NUM_MCLK_RATIOS) { |
b0c813ce | 342 | /* We did not find a matching ratio */ |
70c9a803 | 343 | dev_err(component->dev, "could not find matching ratio\n"); |
b0c813ce TT |
344 | return -EINVAL; |
345 | } | |
346 | ||
d5e9ba1d | 347 | /* Set the sample rate */ |
b0c813ce | 348 | |
a11f8a1c | 349 | reg = snd_soc_component_read(component, CS4270_MODE); |
b0c813ce | 350 | reg &= ~(CS4270_MODE_SPEED_MASK | CS4270_MODE_DIV_MASK); |
4eae080d DM |
351 | reg |= cs4270_mode_ratios[i].mclk; |
352 | ||
353 | if (cs4270->slave_mode) | |
354 | reg |= CS4270_MODE_SLAVE; | |
355 | else | |
356 | reg |= cs4270_mode_ratios[i].speed_mode; | |
b0c813ce | 357 | |
70c9a803 | 358 | ret = snd_soc_component_write(component, CS4270_MODE, reg); |
b0c813ce | 359 | if (ret < 0) { |
70c9a803 | 360 | dev_err(component->dev, "i2c write failed\n"); |
b0c813ce TT |
361 | return ret; |
362 | } | |
363 | ||
d5e9ba1d | 364 | /* Set the DAI format */ |
b0c813ce | 365 | |
a11f8a1c | 366 | reg = snd_soc_component_read(component, CS4270_FORMAT); |
b0c813ce TT |
367 | reg &= ~(CS4270_FORMAT_DAC_MASK | CS4270_FORMAT_ADC_MASK); |
368 | ||
369 | switch (cs4270->mode) { | |
370 | case SND_SOC_DAIFMT_I2S: | |
371 | reg |= CS4270_FORMAT_DAC_I2S | CS4270_FORMAT_ADC_I2S; | |
372 | break; | |
373 | case SND_SOC_DAIFMT_LEFT_J: | |
374 | reg |= CS4270_FORMAT_DAC_LJ | CS4270_FORMAT_ADC_LJ; | |
375 | break; | |
376 | default: | |
70c9a803 | 377 | dev_err(component->dev, "unknown dai format\n"); |
b0c813ce TT |
378 | return -EINVAL; |
379 | } | |
380 | ||
70c9a803 | 381 | ret = snd_soc_component_write(component, CS4270_FORMAT, reg); |
b0c813ce | 382 | if (ret < 0) { |
70c9a803 | 383 | dev_err(component->dev, "i2c write failed\n"); |
b0c813ce TT |
384 | return ret; |
385 | } | |
386 | ||
b0c813ce TT |
387 | return ret; |
388 | } | |
389 | ||
ff7bf02f | 390 | /** |
1a4ba05e | 391 | * cs4270_dai_mute - enable/disable the CS4270 external mute |
ff7bf02f TT |
392 | * @dai: the SOC DAI |
393 | * @mute: 0 = disable mute, 1 = enable mute | |
80cd7309 | 394 | * @direction: (ignored) |
b0c813ce TT |
395 | * |
396 | * This function toggles the mute bits in the MUTE register. The CS4270's | |
397 | * mute capability is intended for external muting circuitry, so if the | |
398 | * board does not have the MUTEA or MUTEB pins connected to such circuitry, | |
399 | * then this function will do nothing. | |
400 | */ | |
03c0f1b5 | 401 | static int cs4270_dai_mute(struct snd_soc_dai *dai, int mute, int direction) |
b0c813ce | 402 | { |
70c9a803 KM |
403 | struct snd_soc_component *component = dai->component; |
404 | struct cs4270_private *cs4270 = snd_soc_component_get_drvdata(component); | |
b0c813ce TT |
405 | int reg6; |
406 | ||
a11f8a1c | 407 | reg6 = snd_soc_component_read(component, CS4270_MUTE); |
b0c813ce TT |
408 | |
409 | if (mute) | |
d5e9ba1d | 410 | reg6 |= CS4270_MUTE_DAC_A | CS4270_MUTE_DAC_B; |
1a4ba05e | 411 | else { |
d5e9ba1d | 412 | reg6 &= ~(CS4270_MUTE_DAC_A | CS4270_MUTE_DAC_B); |
1a4ba05e DM |
413 | reg6 |= cs4270->manual_mute; |
414 | } | |
b0c813ce | 415 | |
70c9a803 | 416 | return snd_soc_component_write(component, CS4270_MUTE, reg6); |
b0c813ce | 417 | } |
b0c813ce | 418 | |
1a4ba05e DM |
419 | /** |
420 | * cs4270_soc_put_mute - put callback for the 'Master Playback switch' | |
421 | * alsa control. | |
422 | * @kcontrol: mixer control | |
423 | * @ucontrol: control element information | |
424 | * | |
425 | * This function basically passes the arguments on to the generic | |
426 | * snd_soc_put_volsw() function and saves the mute information in | |
427 | * our private data structure. This is because we want to prevent | |
428 | * cs4270_dai_mute() neglecting the user's decision to manually | |
429 | * mute the codec's output. | |
430 | * | |
431 | * Returns 0 for success. | |
432 | */ | |
433 | static int cs4270_soc_put_mute(struct snd_kcontrol *kcontrol, | |
434 | struct snd_ctl_elem_value *ucontrol) | |
435 | { | |
70c9a803 KM |
436 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
437 | struct cs4270_private *cs4270 = snd_soc_component_get_drvdata(component); | |
1a4ba05e DM |
438 | int left = !ucontrol->value.integer.value[0]; |
439 | int right = !ucontrol->value.integer.value[1]; | |
440 | ||
441 | cs4270->manual_mute = (left ? CS4270_MUTE_DAC_A : 0) | | |
442 | (right ? CS4270_MUTE_DAC_B : 0); | |
443 | ||
444 | return snd_soc_put_volsw(kcontrol, ucontrol); | |
445 | } | |
446 | ||
b0c813ce TT |
447 | /* A list of non-DAPM controls that the CS4270 supports */ |
448 | static const struct snd_kcontrol_new cs4270_snd_controls[] = { | |
449 | SOC_DOUBLE_R("Master Playback Volume", | |
d5e9ba1d TT |
450 | CS4270_VOLA, CS4270_VOLB, 0, 0xFF, 1), |
451 | SOC_SINGLE("Digital Sidetone Switch", CS4270_FORMAT, 5, 1, 0), | |
452 | SOC_SINGLE("Soft Ramp Switch", CS4270_TRANS, 6, 1, 0), | |
453 | SOC_SINGLE("Zero Cross Switch", CS4270_TRANS, 5, 1, 0), | |
7e1aa1dc | 454 | SOC_SINGLE("De-emphasis filter", CS4270_TRANS, 0, 1, 0), |
d5e9ba1d TT |
455 | SOC_SINGLE("Popguard Switch", CS4270_MODE, 0, 1, 1), |
456 | SOC_SINGLE("Auto-Mute Switch", CS4270_MUTE, 5, 1, 0), | |
1a4ba05e DM |
457 | SOC_DOUBLE("Master Capture Switch", CS4270_MUTE, 3, 4, 1, 1), |
458 | SOC_DOUBLE_EXT("Master Playback Switch", CS4270_MUTE, 0, 1, 1, 1, | |
459 | snd_soc_get_volsw, cs4270_soc_put_mute), | |
b0c813ce TT |
460 | }; |
461 | ||
85e7652d | 462 | static const struct snd_soc_dai_ops cs4270_dai_ops = { |
6335d055 EM |
463 | .hw_params = cs4270_hw_params, |
464 | .set_sysclk = cs4270_set_dai_sysclk, | |
465 | .set_fmt = cs4270_set_dai_fmt, | |
03c0f1b5 KM |
466 | .mute_stream = cs4270_dai_mute, |
467 | .no_capture_mute = 1, | |
6335d055 EM |
468 | }; |
469 | ||
5c75848a | 470 | static struct snd_soc_dai_driver cs4270_dai = { |
f0fba2ad | 471 | .name = "cs4270-hifi", |
0db4d070 TT |
472 | .playback = { |
473 | .stream_name = "Playback", | |
f76fe059 | 474 | .channels_min = 2, |
0db4d070 | 475 | .channels_max = 2, |
f0fba2ad LG |
476 | .rates = SNDRV_PCM_RATE_CONTINUOUS, |
477 | .rate_min = 4000, | |
478 | .rate_max = 216000, | |
0db4d070 TT |
479 | .formats = CS4270_FORMATS, |
480 | }, | |
481 | .capture = { | |
482 | .stream_name = "Capture", | |
f76fe059 | 483 | .channels_min = 2, |
0db4d070 | 484 | .channels_max = 2, |
f0fba2ad LG |
485 | .rates = SNDRV_PCM_RATE_CONTINUOUS, |
486 | .rate_min = 4000, | |
487 | .rate_max = 216000, | |
0db4d070 TT |
488 | .formats = CS4270_FORMATS, |
489 | }, | |
6335d055 | 490 | .ops = &cs4270_dai_ops, |
0db4d070 | 491 | }; |
0db4d070 | 492 | |
ff7bf02f TT |
493 | /** |
494 | * cs4270_probe - ASoC probe function | |
7fdc1512 | 495 | * @component: ASoC component |
ff7bf02f TT |
496 | * |
497 | * This function is called when ASoC has all the pieces it needs to | |
498 | * instantiate a sound driver. | |
04eb093c | 499 | */ |
70c9a803 | 500 | static int cs4270_probe(struct snd_soc_component *component) |
04eb093c | 501 | { |
70c9a803 | 502 | struct cs4270_private *cs4270 = snd_soc_component_get_drvdata(component); |
b61d6d40 | 503 | int ret; |
04eb093c | 504 | |
d5e9ba1d TT |
505 | /* Disable auto-mute. This feature appears to be buggy. In some |
506 | * situations, auto-mute will not deactivate when it should, so we want | |
507 | * this feature disabled by default. An application (e.g. alsactl) can | |
508 | * re-enabled it by using the controls. | |
509 | */ | |
70c9a803 | 510 | ret = snd_soc_component_update_bits(component, CS4270_MUTE, CS4270_MUTE_AUTO, 0); |
d5e9ba1d | 511 | if (ret < 0) { |
70c9a803 | 512 | dev_err(component->dev, "i2c write failed\n"); |
d5e9ba1d TT |
513 | return ret; |
514 | } | |
515 | ||
516 | /* Disable automatic volume control. The hardware enables, and it | |
517 | * causes volume change commands to be delayed, sometimes until after | |
518 | * playback has started. An application (e.g. alsactl) can | |
519 | * re-enabled it by using the controls. | |
520 | */ | |
70c9a803 | 521 | ret = snd_soc_component_update_bits(component, CS4270_TRANS, |
11b8fca5 | 522 | CS4270_TRANS_SOFT | CS4270_TRANS_ZERO, 0); |
d5e9ba1d | 523 | if (ret < 0) { |
70c9a803 | 524 | dev_err(component->dev, "i2c write failed\n"); |
d5e9ba1d TT |
525 | return ret; |
526 | } | |
527 | ||
f0fba2ad LG |
528 | ret = regulator_bulk_enable(ARRAY_SIZE(cs4270->supplies), |
529 | cs4270->supplies); | |
b0c813ce | 530 | |
b0c813ce TT |
531 | return ret; |
532 | } | |
533 | ||
ff7bf02f | 534 | /** |
f0fba2ad | 535 | * cs4270_remove - ASoC remove function |
7fdc1512 | 536 | * @component: ASoC component |
ff7bf02f | 537 | * |
f0fba2ad | 538 | * This function is the counterpart to cs4270_probe(). |
ff7bf02f | 539 | */ |
70c9a803 | 540 | static void cs4270_remove(struct snd_soc_component *component) |
0db4d070 | 541 | { |
70c9a803 | 542 | struct cs4270_private *cs4270 = snd_soc_component_get_drvdata(component); |
0db4d070 | 543 | |
f0fba2ad | 544 | regulator_bulk_disable(ARRAY_SIZE(cs4270->supplies), cs4270->supplies); |
ff637d38 | 545 | }; |
ff637d38 | 546 | |
5e7c0344 DM |
547 | #ifdef CONFIG_PM |
548 | ||
549 | /* This suspend/resume implementation can handle both - a simple standby | |
550 | * where the codec remains powered, and a full suspend, where the voltage | |
551 | * domain the codec is connected to is teared down and/or any other hardware | |
552 | * reset condition is asserted. | |
553 | * | |
554 | * The codec's own power saving features are enabled in the suspend callback, | |
555 | * and all registers are written back to the hardware when resuming. | |
556 | */ | |
557 | ||
70c9a803 | 558 | static int cs4270_soc_suspend(struct snd_soc_component *component) |
15b5bdae | 559 | { |
70c9a803 | 560 | struct cs4270_private *cs4270 = snd_soc_component_get_drvdata(component); |
ffbfd336 | 561 | int reg, ret; |
15b5bdae | 562 | |
a11f8a1c | 563 | reg = snd_soc_component_read(component, CS4270_PWRCTL) | CS4270_PWRCTL_PDN_ALL; |
ffbfd336 DM |
564 | if (reg < 0) |
565 | return reg; | |
566 | ||
70c9a803 | 567 | ret = snd_soc_component_write(component, CS4270_PWRCTL, reg); |
ffbfd336 DM |
568 | if (ret < 0) |
569 | return ret; | |
570 | ||
571 | regulator_bulk_disable(ARRAY_SIZE(cs4270->supplies), | |
572 | cs4270->supplies); | |
573 | ||
574 | return 0; | |
15b5bdae DM |
575 | } |
576 | ||
70c9a803 | 577 | static int cs4270_soc_resume(struct snd_soc_component *component) |
15b5bdae | 578 | { |
70c9a803 | 579 | struct cs4270_private *cs4270 = snd_soc_component_get_drvdata(component); |
ab92d09d | 580 | int reg, ret; |
5e7c0344 | 581 | |
ab92d09d MB |
582 | ret = regulator_bulk_enable(ARRAY_SIZE(cs4270->supplies), |
583 | cs4270->supplies); | |
584 | if (ret != 0) | |
585 | return ret; | |
ffbfd336 | 586 | |
5e7c0344 DM |
587 | /* In case the device was put to hard reset during sleep, we need to |
588 | * wait 500ns here before any I2C communication. */ | |
589 | ndelay(500); | |
590 | ||
591 | /* first restore the entire register cache ... */ | |
1ca65175 | 592 | regcache_sync(cs4270->regmap); |
5e7c0344 DM |
593 | |
594 | /* ... then disable the power-down bits */ | |
a11f8a1c | 595 | reg = snd_soc_component_read(component, CS4270_PWRCTL); |
5e7c0344 DM |
596 | reg &= ~CS4270_PWRCTL_PDN_ALL; |
597 | ||
70c9a803 | 598 | return snd_soc_component_write(component, CS4270_PWRCTL, reg); |
5e7c0344 DM |
599 | } |
600 | #else | |
15b5bdae DM |
601 | #define cs4270_soc_suspend NULL |
602 | #define cs4270_soc_resume NULL | |
5e7c0344 DM |
603 | #endif /* CONFIG_PM */ |
604 | ||
f0fba2ad | 605 | /* |
b6f7d7c8 | 606 | * ASoC codec driver structure |
f0fba2ad | 607 | */ |
70c9a803 KM |
608 | static const struct snd_soc_component_driver soc_component_device_cs4270 = { |
609 | .probe = cs4270_probe, | |
610 | .remove = cs4270_remove, | |
611 | .suspend = cs4270_soc_suspend, | |
612 | .resume = cs4270_soc_resume, | |
613 | .controls = cs4270_snd_controls, | |
614 | .num_controls = ARRAY_SIZE(cs4270_snd_controls), | |
615 | .dapm_widgets = cs4270_dapm_widgets, | |
616 | .num_dapm_widgets = ARRAY_SIZE(cs4270_dapm_widgets), | |
617 | .dapm_routes = cs4270_dapm_routes, | |
618 | .num_dapm_routes = ARRAY_SIZE(cs4270_dapm_routes), | |
619 | .idle_bias_on = 1, | |
620 | .use_pmdown_time = 1, | |
621 | .endianness = 1, | |
f0fba2ad LG |
622 | }; |
623 | ||
85d07e4d DM |
624 | /* |
625 | * cs4270_of_match - the device tree bindings | |
626 | */ | |
627 | static const struct of_device_id cs4270_of_match[] = { | |
628 | { .compatible = "cirrus,cs4270", }, | |
629 | { } | |
630 | }; | |
631 | MODULE_DEVICE_TABLE(of, cs4270_of_match); | |
632 | ||
1ca65175 MB |
633 | static const struct regmap_config cs4270_regmap = { |
634 | .reg_bits = 8, | |
635 | .val_bits = 8, | |
636 | .max_register = CS4270_LASTREG, | |
637 | .reg_defaults = cs4270_reg_defaults, | |
638 | .num_reg_defaults = ARRAY_SIZE(cs4270_reg_defaults), | |
7a2827ad | 639 | .cache_type = REGCACHE_MAPLE, |
f0f2338a | 640 | .write_flag_mask = CS4270_I2C_INCR, |
1ca65175 MB |
641 | |
642 | .readable_reg = cs4270_reg_is_readable, | |
643 | .volatile_reg = cs4270_reg_is_volatile, | |
644 | }; | |
645 | ||
ccfc5316 MW |
646 | /** |
647 | * cs4270_i2c_remove - deinitialize the I2C interface of the CS4270 | |
648 | * @i2c_client: the I2C client object | |
649 | * | |
650 | * This function puts the chip into low power mode when the i2c device | |
651 | * is removed. | |
652 | */ | |
ed5c2f5f | 653 | static void cs4270_i2c_remove(struct i2c_client *i2c_client) |
ccfc5316 MW |
654 | { |
655 | struct cs4270_private *cs4270 = i2c_get_clientdata(i2c_client); | |
656 | ||
657 | gpiod_set_value_cansleep(cs4270->reset_gpio, 0); | |
ccfc5316 MW |
658 | } |
659 | ||
f0fba2ad LG |
660 | /** |
661 | * cs4270_i2c_probe - initialize the I2C interface of the CS4270 | |
662 | * @i2c_client: the I2C client object | |
f0fba2ad LG |
663 | * |
664 | * This function is called whenever the I2C subsystem finds a device that | |
665 | * matches the device ID given via a prior call to i2c_add_driver(). | |
666 | */ | |
4a404345 | 667 | static int cs4270_i2c_probe(struct i2c_client *i2c_client) |
f0fba2ad LG |
668 | { |
669 | struct cs4270_private *cs4270; | |
1ca65175 | 670 | unsigned int val; |
b61d6d40 MB |
671 | int ret, i; |
672 | ||
673 | cs4270 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs4270_private), | |
674 | GFP_KERNEL); | |
0e0327f2 | 675 | if (!cs4270) |
b61d6d40 | 676 | return -ENOMEM; |
b61d6d40 MB |
677 | |
678 | /* get the power supply regulators */ | |
679 | for (i = 0; i < ARRAY_SIZE(supply_names); i++) | |
680 | cs4270->supplies[i].supply = supply_names[i]; | |
681 | ||
682 | ret = devm_regulator_bulk_get(&i2c_client->dev, | |
683 | ARRAY_SIZE(cs4270->supplies), | |
684 | cs4270->supplies); | |
685 | if (ret < 0) | |
686 | return ret; | |
f0fba2ad | 687 | |
ccfc5316 MW |
688 | /* reset the device */ |
689 | cs4270->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev, "reset", | |
690 | GPIOD_OUT_LOW); | |
691 | if (IS_ERR(cs4270->reset_gpio)) { | |
692 | dev_dbg(&i2c_client->dev, "Error getting CS4270 reset GPIO\n"); | |
693 | return PTR_ERR(cs4270->reset_gpio); | |
694 | } | |
695 | ||
696 | if (cs4270->reset_gpio) { | |
697 | dev_dbg(&i2c_client->dev, "Found reset GPIO\n"); | |
698 | gpiod_set_value_cansleep(cs4270->reset_gpio, 1); | |
699 | } | |
700 | ||
701 | /* Sleep 500ns before i2c communications */ | |
702 | ndelay(500); | |
02286190 | 703 | |
1ca65175 MB |
704 | cs4270->regmap = devm_regmap_init_i2c(i2c_client, &cs4270_regmap); |
705 | if (IS_ERR(cs4270->regmap)) | |
706 | return PTR_ERR(cs4270->regmap); | |
f0fba2ad | 707 | |
1ca65175 MB |
708 | /* Verify that we have a CS4270 */ |
709 | ret = regmap_read(cs4270->regmap, CS4270_CHIPID, &val); | |
f0fba2ad LG |
710 | if (ret < 0) { |
711 | dev_err(&i2c_client->dev, "failed to read i2c at addr %X\n", | |
712 | i2c_client->addr); | |
713 | return ret; | |
714 | } | |
715 | /* The top four bits of the chip ID should be 1100. */ | |
1ca65175 | 716 | if ((val & 0xF0) != 0xC0) { |
f0fba2ad LG |
717 | dev_err(&i2c_client->dev, "device at addr %X is not a CS4270\n", |
718 | i2c_client->addr); | |
719 | return -ENODEV; | |
720 | } | |
721 | ||
722 | dev_info(&i2c_client->dev, "found device at i2c address %X\n", | |
723 | i2c_client->addr); | |
1ca65175 | 724 | dev_info(&i2c_client->dev, "hardware revision %X\n", val & 0xF); |
f0fba2ad | 725 | |
f0fba2ad | 726 | i2c_set_clientdata(i2c_client, cs4270); |
f0fba2ad | 727 | |
70c9a803 KM |
728 | ret = devm_snd_soc_register_component(&i2c_client->dev, |
729 | &soc_component_device_cs4270, &cs4270_dai, 1); | |
f0fba2ad LG |
730 | return ret; |
731 | } | |
732 | ||
f0fba2ad LG |
733 | /* |
734 | * cs4270_id - I2C device IDs supported by this driver | |
735 | */ | |
79a54ea1 | 736 | static const struct i2c_device_id cs4270_id[] = { |
f0fba2ad LG |
737 | {"cs4270", 0}, |
738 | {} | |
739 | }; | |
740 | MODULE_DEVICE_TABLE(i2c, cs4270_id); | |
741 | ||
ff7bf02f TT |
742 | /* |
743 | * cs4270_i2c_driver - I2C device identification | |
744 | * | |
745 | * This structure tells the I2C subsystem how to identify and support a | |
746 | * given I2C device type. | |
747 | */ | |
ff637d38 TT |
748 | static struct i2c_driver cs4270_i2c_driver = { |
749 | .driver = { | |
64902b29 | 750 | .name = "cs4270", |
85d07e4d | 751 | .of_match_table = cs4270_of_match, |
ff637d38 TT |
752 | }, |
753 | .id_table = cs4270_id, | |
9abcd240 | 754 | .probe = cs4270_i2c_probe, |
ccfc5316 | 755 | .remove = cs4270_i2c_remove, |
ff637d38 | 756 | }; |
b0c813ce | 757 | |
5e383f53 | 758 | module_i2c_driver(cs4270_i2c_driver); |
64089b84 | 759 | |
b0c813ce TT |
760 | MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); |
761 | MODULE_DESCRIPTION("Cirrus Logic CS4270 ALSA SoC Codec Driver"); | |
762 | MODULE_LICENSE("GPL"); |