[linux-2.6-block.git] / sound / soc / codecs / cs4265.c

/*
 * cs4265.c -- CS4265 ALSA SoC audio driver
 *
 * Copyright 2014 Cirrus Logic, Inc.
 *
 * Author: Paul Handrigan <paul.handrigan@cirrus.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/gpio/consumer.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/input.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "cs4265.h"

struct cs4265_private {
	struct regmap *regmap;
	struct gpio_desc *reset_gpio;
	u8 format;
	u32 sysclk;
};

static const struct reg_default cs4265_reg_defaults[] = {
	{ CS4265_PWRCTL, 0x0F },
	{ CS4265_DAC_CTL, 0x08 },
	{ CS4265_ADC_CTL, 0x00 },
	{ CS4265_MCLK_FREQ, 0x00 },
	{ CS4265_SIG_SEL, 0x40 },
	{ CS4265_CHB_PGA_CTL, 0x00 },
	{ CS4265_CHA_PGA_CTL, 0x00 },
	{ CS4265_ADC_CTL2, 0x19 },
	{ CS4265_DAC_CHA_VOL, 0x00 },
	{ CS4265_DAC_CHB_VOL, 0x00 },
	{ CS4265_DAC_CTL2, 0xC0 },
	{ CS4265_SPDIF_CTL1, 0x00 },
	{ CS4265_SPDIF_CTL2, 0x00 },
	{ CS4265_INT_MASK, 0x00 },
	{ CS4265_STATUS_MODE_MSB, 0x00 },
	{ CS4265_STATUS_MODE_LSB, 0x00 },
};

static bool cs4265_readable_register(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case CS4265_CHIP_ID ... CS4265_SPDIF_CTL2:
		return true;
	default:
		return false;
	}
}

static bool cs4265_volatile_register(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case CS4265_INT_STATUS:
		return true;
	default:
		return false;
	}
}

static DECLARE_TLV_DB_SCALE(pga_tlv, -1200, 50, 0);

static DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 0);

static const char * const digital_input_mux_text[] = {
	"SDIN1", "SDIN2"
};

static SOC_ENUM_SINGLE_DECL(digital_input_mux_enum, CS4265_SIG_SEL, 7,
		digital_input_mux_text);

static const struct snd_kcontrol_new digital_input_mux =
	SOC_DAPM_ENUM("Digital Input Mux", digital_input_mux_enum);

static const char * const mic_linein_text[] = {
	"MIC", "LINEIN"
};

static SOC_ENUM_SINGLE_DECL(mic_linein_enum, CS4265_ADC_CTL2, 0,
		mic_linein_text);

static const char * const cam_mode_text[] = {
	"One Byte", "Two Byte"
};

static SOC_ENUM_SINGLE_DECL(cam_mode_enum, CS4265_SPDIF_CTL1, 5,
		cam_mode_text);

static const char * const cam_mono_stereo_text[] = {
	"Stereo", "Mono"
};

static SOC_ENUM_SINGLE_DECL(spdif_mono_stereo_enum, CS4265_SPDIF_CTL2, 2,
		cam_mono_stereo_text);

static const char * const mono_select_text[] = {
	"Channel A", "Channel B"
};

static SOC_ENUM_SINGLE_DECL(spdif_mono_select_enum, CS4265_SPDIF_CTL2, 0,
		mono_select_text);

static const struct snd_kcontrol_new mic_linein_mux =
	SOC_DAPM_ENUM("ADC Input Capture Mux", mic_linein_enum);

static const struct snd_kcontrol_new loopback_ctl =
	SOC_DAPM_SINGLE("Switch", CS4265_SIG_SEL, 1, 1, 0);

static const struct snd_kcontrol_new spdif_switch =
	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 0, 0);

static const struct snd_kcontrol_new dac_switch =
	SOC_DAPM_SINGLE("Switch", CS4265_PWRCTL, 1, 1, 0);

static const struct snd_kcontrol_new cs4265_snd_controls[] = {

	SOC_DOUBLE_R_SX_TLV("PGA Volume", CS4265_CHA_PGA_CTL,
			      CS4265_CHB_PGA_CTL, 0, 0x28, 0x30, pga_tlv),
	SOC_DOUBLE_R_TLV("DAC Volume", CS4265_DAC_CHA_VOL,
		      CS4265_DAC_CHB_VOL, 0, 0xFF, 1, dac_tlv),
	SOC_SINGLE("De-emp 44.1kHz Switch", CS4265_DAC_CTL, 1,
				1, 0),
	SOC_SINGLE("DAC INV Switch", CS4265_DAC_CTL2, 5,
				1, 0),
	SOC_SINGLE("DAC Zero Cross Switch", CS4265_DAC_CTL2, 6,
				1, 0),
	SOC_SINGLE("DAC Soft Ramp Switch", CS4265_DAC_CTL2, 7,
				1, 0),
	SOC_SINGLE("ADC HPF Switch", CS4265_ADC_CTL, 1,
				1, 0),
	SOC_SINGLE("ADC Zero Cross Switch", CS4265_ADC_CTL2, 3,
				1, 1),
	SOC_SINGLE("ADC Soft Ramp Switch", CS4265_ADC_CTL2, 7,
				1, 0),
	SOC_SINGLE("E to F Buffer Disable Switch", CS4265_SPDIF_CTL1,
				6, 1, 0),
	SOC_ENUM("C Data Access", cam_mode_enum),
	SOC_SINGLE("SPDIF Switch", CS4265_SPDIF_CTL2, 5, 1, 1),
	SOC_SINGLE("Validity Bit Control Switch", CS4265_SPDIF_CTL2,
				3, 1, 0),
	SOC_ENUM("SPDIF Mono/Stereo", spdif_mono_stereo_enum),
	SOC_SINGLE("MMTLR Data Switch", CS4265_SPDIF_CTL2, 0, 1, 0),
	SOC_ENUM("Mono Channel Select", spdif_mono_select_enum),
	SND_SOC_BYTES("C Data Buffer", CS4265_C_DATA_BUFF, 24),
};

static const struct snd_soc_dapm_widget cs4265_dapm_widgets[] = {

	SND_SOC_DAPM_INPUT("LINEINL"),
	SND_SOC_DAPM_INPUT("LINEINR"),
	SND_SOC_DAPM_INPUT("MICL"),
	SND_SOC_DAPM_INPUT("MICR"),

	SND_SOC_DAPM_AIF_OUT("DOUT", NULL,  0,
			SND_SOC_NOPM, 0, 0),
	SND_SOC_DAPM_AIF_OUT("SPDIFOUT", NULL,  0,
			SND_SOC_NOPM, 0, 0),

	SND_SOC_DAPM_MUX("ADC Mux", SND_SOC_NOPM, 0, 0, &mic_linein_mux),

	SND_SOC_DAPM_ADC("ADC", NULL, CS4265_PWRCTL, 2, 1),
	SND_SOC_DAPM_PGA("Pre-amp MIC", CS4265_PWRCTL, 3,
			1, NULL, 0),

	SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM,
			 0, 0, &digital_input_mux),

	SND_SOC_DAPM_MIXER("SDIN1 Input Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
	SND_SOC_DAPM_MIXER("SDIN2 Input Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
	SND_SOC_DAPM_MIXER("SPDIF Transmitter", SND_SOC_NOPM, 0, 0, NULL, 0),

	SND_SOC_DAPM_SWITCH("Loopback", SND_SOC_NOPM, 0, 0,
			&loopback_ctl),
	SND_SOC_DAPM_SWITCH("SPDIF", SND_SOC_NOPM, 0, 0,
			&spdif_switch),
	SND_SOC_DAPM_SWITCH("DAC", CS4265_PWRCTL, 1, 1,
			&dac_switch),

	SND_SOC_DAPM_AIF_IN("DIN1", NULL,  0,
			SND_SOC_NOPM, 0, 0),
	SND_SOC_DAPM_AIF_IN("DIN2", NULL,  0,
			SND_SOC_NOPM, 0, 0),
	SND_SOC_DAPM_AIF_IN("TXIN", NULL,  0,
			CS4265_SPDIF_CTL2, 5, 1),

	SND_SOC_DAPM_OUTPUT("LINEOUTL"),
	SND_SOC_DAPM_OUTPUT("LINEOUTR"),

};

static const struct snd_soc_dapm_route cs4265_audio_map[] = {

	{"DIN1", NULL, "DAI1 Playback"},
	{"DIN2", NULL, "DAI2 Playback"},
	{"SDIN1 Input Mixer", NULL, "DIN1"},
	{"SDIN2 Input Mixer", NULL, "DIN2"},
	{"Input Mux", "SDIN1", "SDIN1 Input Mixer"},
	{"Input Mux", "SDIN2", "SDIN2 Input Mixer"},
	{"DAC", "Switch", "Input Mux"},
	{"SPDIF", "Switch", "Input Mux"},
	{"LINEOUTL", NULL, "DAC"},
	{"LINEOUTR", NULL, "DAC"},
	{"SPDIFOUT", NULL, "SPDIF"},

	{"Pre-amp MIC", NULL, "MICL"},
	{"Pre-amp MIC", NULL, "MICR"},
	{"ADC Mux", "MIC", "Pre-amp MIC"},
	{"ADC Mux", "LINEIN", "LINEINL"},
	{"ADC Mux", "LINEIN", "LINEINR"},
	{"ADC", NULL, "ADC Mux"},
	{"DOUT", NULL, "ADC"},
	{"DAI1 Capture", NULL, "DOUT"},
	{"DAI2 Capture", NULL, "DOUT"},

	/* Loopback */
	{"Loopback", "Switch", "ADC"},
	{"DAC", NULL, "Loopback"},
};

struct cs4265_clk_para {
	u32 mclk;
	u32 rate;
	u8 fm_mode; /* values 1, 2, or 4 */
	u8 mclkdiv;
};

static const struct cs4265_clk_para clk_map_table[] = {
	/*32k*/
	{8192000, 32000, 0, 0},
	{12288000, 32000, 0, 1},
	{16384000, 32000, 0, 2},
	{24576000, 32000, 0, 3},
	{32768000, 32000, 0, 4},

	/*44.1k*/
	{11289600, 44100, 0, 0},
	{16934400, 44100, 0, 1},
	{22579200, 44100, 0, 2},
	{33868000, 44100, 0, 3},
	{45158400, 44100, 0, 4},

	/*48k*/
	{12288000, 48000, 0, 0},
	{18432000, 48000, 0, 1},
	{24576000, 48000, 0, 2},
	{36864000, 48000, 0, 3},
	{49152000, 48000, 0, 4},

	/*64k*/
	{8192000, 64000, 1, 0},
	{12288000, 64000, 1, 1},
	{16934400, 64000, 1, 2},
	{24576000, 64000, 1, 3},
	{32768000, 64000, 1, 4},

	/* 88.2k */
	{11289600, 88200, 1, 0},
	{16934400, 88200, 1, 1},
	{22579200, 88200, 1, 2},
	{33868000, 88200, 1, 3},
	{45158400, 88200, 1, 4},

	/* 96k */
	{12288000, 96000, 1, 0},
	{18432000, 96000, 1, 1},
	{24576000, 96000, 1, 2},
	{36864000, 96000, 1, 3},
	{49152000, 96000, 1, 4},

	/* 128k */
	{8192000, 128000, 2, 0},
	{12288000, 128000, 2, 1},
	{16934400, 128000, 2, 2},
	{24576000, 128000, 2, 3},
	{32768000, 128000, 2, 4},

	/* 176.4k */
	{11289600, 176400, 2, 0},
	{16934400, 176400, 2, 1},
	{22579200, 176400, 2, 2},
	{33868000, 176400, 2, 3},
	{49152000, 176400, 2, 4},

	/* 192k */
	{12288000, 192000, 2, 0},
	{18432000, 192000, 2, 1},
	{24576000, 192000, 2, 2},
	{36864000, 192000, 2, 3},
	{49152000, 192000, 2, 4},
};

static int cs4265_get_clk_index(int mclk, int rate)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(clk_map_table); i++) {
		if (clk_map_table[i].rate == rate &&
				clk_map_table[i].mclk == mclk)
			return i;
	}
	return -EINVAL;
}

static int cs4265_set_sysclk(struct snd_soc_dai *codec_dai, int clk_id,
			unsigned int freq, int dir)
{
	struct snd_soc_component *component = codec_dai->component;
	struct cs4265_private *cs4265 = snd_soc_component_get_drvdata(component);
	int i;

	if (clk_id != 0) {
		dev_err(component->dev, "Invalid clk_id %d\n", clk_id);
		return -EINVAL;
	}
	for (i = 0; i < ARRAY_SIZE(clk_map_table); i++) {
		if (clk_map_table[i].mclk == freq) {
			cs4265->sysclk = freq;
			return 0;
		}
	}
	cs4265->sysclk = 0;
	dev_err(component->dev, "Invalid freq parameter %d\n", freq);
	return -EINVAL;
}

static int cs4265_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
	struct snd_soc_component *component = codec_dai->component;
	struct cs4265_private *cs4265 = snd_soc_component_get_drvdata(component);
	u8 iface = 0;

	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBM_CFM:
		snd_soc_component_update_bits(component, CS4265_ADC_CTL,
				CS4265_ADC_MASTER,
				CS4265_ADC_MASTER);
		break;
	case SND_SOC_DAIFMT_CBS_CFS:
		snd_soc_component_update_bits(component, CS4265_ADC_CTL,
				CS4265_ADC_MASTER,
				0);
		break;
	default:
		return -EINVAL;
	}

	 /* interface format */
	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_I2S:
		iface |= SND_SOC_DAIFMT_I2S;
		break;
	case SND_SOC_DAIFMT_RIGHT_J:
		iface |= SND_SOC_DAIFMT_RIGHT_J;
		break;
	case SND_SOC_DAIFMT_LEFT_J:
		iface |= SND_SOC_DAIFMT_LEFT_J;
		break;
	default:
		return -EINVAL;
	}

	cs4265->format = iface;
	return 0;
}

static int cs4265_digital_mute(struct snd_soc_dai *dai, int mute)
{
	struct snd_soc_component *component = dai->component;

	if (mute) {
		snd_soc_component_update_bits(component, CS4265_DAC_CTL,
			CS4265_DAC_CTL_MUTE,
			CS4265_DAC_CTL_MUTE);
		snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2,
			CS4265_SPDIF_CTL2_MUTE,
			CS4265_SPDIF_CTL2_MUTE);
	} else {
		snd_soc_component_update_bits(component, CS4265_DAC_CTL,
			CS4265_DAC_CTL_MUTE,
			0);
		snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2,
			CS4265_SPDIF_CTL2_MUTE,
			0);
	}
	return 0;
}

static int cs4265_pcm_hw_params(struct snd_pcm_substream *substream,
				     struct snd_pcm_hw_params *params,
				     struct snd_soc_dai *dai)
{
	struct snd_soc_component *component = dai->component;
	struct cs4265_private *cs4265 = snd_soc_component_get_drvdata(component);
	int index;

	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE &&
		((cs4265->format & SND_SOC_DAIFMT_FORMAT_MASK)
		== SND_SOC_DAIFMT_RIGHT_J))
		return -EINVAL;

	index = cs4265_get_clk_index(cs4265->sysclk, params_rate(params));
	if (index >= 0) {
		snd_soc_component_update_bits(component, CS4265_ADC_CTL,
			CS4265_ADC_FM, clk_map_table[index].fm_mode << 6);
		snd_soc_component_update_bits(component, CS4265_MCLK_FREQ,
			CS4265_MCLK_FREQ_MASK,
			clk_map_table[index].mclkdiv << 4);

	} else {
		dev_err(component->dev, "can't get correct mclk\n");
		return -EINVAL;
	}

	switch (cs4265->format & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_I2S:
		snd_soc_component_update_bits(component, CS4265_DAC_CTL,
			CS4265_DAC_CTL_DIF, (1 << 4));
		snd_soc_component_update_bits(component, CS4265_ADC_CTL,
			CS4265_ADC_DIF, (1 << 4));
		snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2,
			CS4265_SPDIF_CTL2_DIF, (1 << 6));
		break;
	case SND_SOC_DAIFMT_RIGHT_J:
		if (params_width(params) == 16) {
			snd_soc_component_update_bits(component, CS4265_DAC_CTL,
				CS4265_DAC_CTL_DIF, (2 << 4));
			snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2,
				CS4265_SPDIF_CTL2_DIF, (2 << 6));
		} else {
			snd_soc_component_update_bits(component, CS4265_DAC_CTL,
				CS4265_DAC_CTL_DIF, (3 << 4));
			snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2,
				CS4265_SPDIF_CTL2_DIF, (3 << 6));
		}
		break;
	case SND_SOC_DAIFMT_LEFT_J:
		snd_soc_component_update_bits(component, CS4265_DAC_CTL,
			CS4265_DAC_CTL_DIF, 0);
		snd_soc_component_update_bits(component, CS4265_ADC_CTL,
			CS4265_ADC_DIF, 0);
		snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2,
			CS4265_SPDIF_CTL2_DIF, 0);

		break;
	default:
		return -EINVAL;
	}
	return 0;
}

static int cs4265_set_bias_level(struct snd_soc_component *component,
					enum snd_soc_bias_level level)
{
	switch (level) {
	case SND_SOC_BIAS_ON:
		break;
	case SND_SOC_BIAS_PREPARE:
		snd_soc_component_update_bits(component, CS4265_PWRCTL,
			CS4265_PWRCTL_PDN, 0);
		break;
	case SND_SOC_BIAS_STANDBY:
		snd_soc_component_update_bits(component, CS4265_PWRCTL,
			CS4265_PWRCTL_PDN,
			CS4265_PWRCTL_PDN);
		break;
	case SND_SOC_BIAS_OFF:
		snd_soc_component_update_bits(component, CS4265_PWRCTL,
			CS4265_PWRCTL_PDN,
			CS4265_PWRCTL_PDN);
		break;
	}
	return 0;
}

#define CS4265_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
			SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \
			SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | \
			SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000)

#define CS4265_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE | \
			SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_U24_LE | \
			SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_U32_LE)

static const struct snd_soc_dai_ops cs4265_ops = {
	.hw_params	= cs4265_pcm_hw_params,
	.digital_mute	= cs4265_digital_mute,
	.set_fmt	= cs4265_set_fmt,
	.set_sysclk	= cs4265_set_sysclk,
};

static struct snd_soc_dai_driver cs4265_dai[] = {
	{
		.name = "cs4265-dai1",
		.playback = {
			.stream_name = "DAI1 Playback",
			.channels_min = 1,
			.channels_max = 2,
			.rates = CS4265_RATES,
			.formats = CS4265_FORMATS,
		},
		.capture = {
			.stream_name = "DAI1 Capture",
			.channels_min = 1,
			.channels_max = 2,
			.rates = CS4265_RATES,
			.formats = CS4265_FORMATS,
		},
		.ops = &cs4265_ops,
	},
	{
		.name = "cs4265-dai2",
		.playback = {
			.stream_name = "DAI2 Playback",
			.channels_min = 1,
			.channels_max = 2,
			.rates = CS4265_RATES,
			.formats = CS4265_FORMATS,
		},
		.capture = {
			.stream_name = "DAI2 Capture",
			.channels_min = 1,
			.channels_max = 2,
			.rates = CS4265_RATES,
			.formats = CS4265_FORMATS,
		},
		.ops = &cs4265_ops,
	},
};

static const struct snd_soc_component_driver soc_component_cs4265 = {
	.set_bias_level		= cs4265_set_bias_level,
	.controls		= cs4265_snd_controls,
	.num_controls		= ARRAY_SIZE(cs4265_snd_controls),
	.dapm_widgets		= cs4265_dapm_widgets,
	.num_dapm_widgets	= ARRAY_SIZE(cs4265_dapm_widgets),
	.dapm_routes		= cs4265_audio_map,
	.num_dapm_routes	= ARRAY_SIZE(cs4265_audio_map),
	.idle_bias_on		= 1,
	.use_pmdown_time	= 1,
	.endianness		= 1,
	.non_legacy_dai_naming	= 1,
};

static const struct regmap_config cs4265_regmap = {
	.reg_bits = 8,
	.val_bits = 8,

	.max_register = CS4265_MAX_REGISTER,
	.reg_defaults = cs4265_reg_defaults,
	.num_reg_defaults = ARRAY_SIZE(cs4265_reg_defaults),
	.readable_reg = cs4265_readable_register,
	.volatile_reg = cs4265_volatile_register,
	.cache_type = REGCACHE_RBTREE,
};

static int cs4265_i2c_probe(struct i2c_client *i2c_client,
			     const struct i2c_device_id *id)
{
	struct cs4265_private *cs4265;
	int ret = 0;
	unsigned int devid = 0;
	unsigned int reg;

	cs4265 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs4265_private),
			       GFP_KERNEL);
	if (cs4265 == NULL)
		return -ENOMEM;

	cs4265->regmap = devm_regmap_init_i2c(i2c_client, &cs4265_regmap);
	if (IS_ERR(cs4265->regmap)) {
		ret = PTR_ERR(cs4265->regmap);
		dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
		return ret;
	}

	cs4265->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
		"reset", GPIOD_OUT_LOW);
	if (IS_ERR(cs4265->reset_gpio))
		return PTR_ERR(cs4265->reset_gpio);

	if (cs4265->reset_gpio) {
		mdelay(1);
		gpiod_set_value_cansleep(cs4265->reset_gpio, 1);
	}

	i2c_set_clientdata(i2c_client, cs4265);

	ret = regmap_read(cs4265->regmap, CS4265_CHIP_ID, &reg);
	devid = reg & CS4265_CHIP_ID_MASK;
	if (devid != CS4265_CHIP_ID_VAL) {
		ret = -ENODEV;
		dev_err(&i2c_client->dev,
			"CS4265 Device ID (%X). Expected %X\n",
			devid, CS4265_CHIP_ID);
		return ret;
	}
	dev_info(&i2c_client->dev,
		"CS4265 Version %x\n",
			reg & CS4265_REV_ID_MASK);

	regmap_write(cs4265->regmap, CS4265_PWRCTL, 0x0F);

	ret = devm_snd_soc_register_component(&i2c_client->dev,
			&soc_component_cs4265, cs4265_dai,
			ARRAY_SIZE(cs4265_dai));
	return ret;
}

static const struct of_device_id cs4265_of_match[] = {
	{ .compatible = "cirrus,cs4265", },
	{ }
};
MODULE_DEVICE_TABLE(of, cs4265_of_match);

static const struct i2c_device_id cs4265_id[] = {
	{ "cs4265", 0 },
	{ }
};
MODULE_DEVICE_TABLE(i2c, cs4265_id);

static struct i2c_driver cs4265_i2c_driver = {
	.driver = {
		.name = "cs4265",
		.of_match_table = cs4265_of_match,
	},
	.id_table = cs4265_id,
	.probe =    cs4265_i2c_probe,
};

module_i2c_driver(cs4265_i2c_driver);

MODULE_DESCRIPTION("ASoC CS4265 driver");
MODULE_AUTHOR("Paul Handrigan, Cirrus Logic Inc, <paul.handrigan@cirrus.com>");
MODULE_LICENSE("GPL");
Commit	Line	Data
fb6f8069 PH	1	/*
	2	* cs4265.c -- CS4265 ALSA SoC audio driver
	3	*
	4	* Copyright 2014 Cirrus Logic, Inc.
	5	*
	6	* Author: Paul Handrigan <paul.handrigan@cirrus.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	*/
	13
	14	#include <linux/module.h>
	15	#include <linux/moduleparam.h>
	16	#include <linux/kernel.h>
	17	#include <linux/gpio/consumer.h>
	18	#include <linux/init.h>
	19	#include <linux/delay.h>
	20	#include <linux/i2c.h>
	21	#include <linux/input.h>
	22	#include <linux/regmap.h>
	23	#include <linux/slab.h>
	24	#include <linux/platform_device.h>
	25	#include <sound/core.h>
	26	#include <sound/pcm.h>
	27	#include <sound/pcm_params.h>
	28	#include <sound/soc.h>
	29	#include <sound/soc-dapm.h>
	30	#include <sound/initval.h>
	31	#include <sound/tlv.h>
	32	#include "cs4265.h"
	33
	34	struct cs4265_private {
fb6f8069 PH	35	struct regmap *regmap;
	36	struct gpio_desc *reset_gpio;
	37	u8 format;
	38	u32 sysclk;
	39	};
	40
	41	static const struct reg_default cs4265_reg_defaults[] = {
	42	{ CS4265_PWRCTL, 0x0F },
	43	{ CS4265_DAC_CTL, 0x08 },
	44	{ CS4265_ADC_CTL, 0x00 },
	45	{ CS4265_MCLK_FREQ, 0x00 },
	46	{ CS4265_SIG_SEL, 0x40 },
	47	{ CS4265_CHB_PGA_CTL, 0x00 },
	48	{ CS4265_CHA_PGA_CTL, 0x00 },
	49	{ CS4265_ADC_CTL2, 0x19 },
	50	{ CS4265_DAC_CHA_VOL, 0x00 },
	51	{ CS4265_DAC_CHB_VOL, 0x00 },
	52	{ CS4265_DAC_CTL2, 0xC0 },
	53	{ CS4265_SPDIF_CTL1, 0x00 },
	54	{ CS4265_SPDIF_CTL2, 0x00 },
	55	{ CS4265_INT_MASK, 0x00 },
	56	{ CS4265_STATUS_MODE_MSB, 0x00 },
	57	{ CS4265_STATUS_MODE_LSB, 0x00 },
	58	};
	59
	60	static bool cs4265_readable_register(struct device *dev, unsigned int reg)
	61	{
	62	switch (reg) {
80deaf09	63	case CS4265_CHIP_ID ... CS4265_SPDIF_CTL2:
fb6f8069 PH	64	return true;
	65	default:
	66	return false;
	67	}
	68	}
	69
	70	static bool cs4265_volatile_register(struct device *dev, unsigned int reg)
	71	{
	72	switch (reg) {
	73	case CS4265_INT_STATUS:
59f5cbec	74	return true;
fb6f8069	75	default:
59f5cbec	76	return false;
fb6f8069 PH	77	}
	78	}
	79
	80	static DECLARE_TLV_DB_SCALE(pga_tlv, -1200, 50, 0);
	81
	82	static DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 0);
	83
	84	static const char * const digital_input_mux_text[] = {
	85	"SDIN1", "SDIN2"
	86	};
	87
	88	static SOC_ENUM_SINGLE_DECL(digital_input_mux_enum, CS4265_SIG_SEL, 7,
	89	digital_input_mux_text);
	90
	91	static const struct snd_kcontrol_new digital_input_mux =
	92	SOC_DAPM_ENUM("Digital Input Mux", digital_input_mux_enum);
	93
	94	static const char * const mic_linein_text[] = {
	95	"MIC", "LINEIN"
	96	};
	97
	98	static SOC_ENUM_SINGLE_DECL(mic_linein_enum, CS4265_ADC_CTL2, 0,
	99	mic_linein_text);
	100
	101	static const char * const cam_mode_text[] = {
	102	"One Byte", "Two Byte"
	103	};
	104
	105	static SOC_ENUM_SINGLE_DECL(cam_mode_enum, CS4265_SPDIF_CTL1, 5,
	106	cam_mode_text);
	107
	108	static const char * const cam_mono_stereo_text[] = {
	109	"Stereo", "Mono"
	110	};
	111
	112	static SOC_ENUM_SINGLE_DECL(spdif_mono_stereo_enum, CS4265_SPDIF_CTL2, 2,
	113	cam_mono_stereo_text);
	114
	115	static const char * const mono_select_text[] = {
	116	"Channel A", "Channel B"
	117	};
	118
	119	static SOC_ENUM_SINGLE_DECL(spdif_mono_select_enum, CS4265_SPDIF_CTL2, 0,
	120	mono_select_text);
	121
	122	static const struct snd_kcontrol_new mic_linein_mux =
	123	SOC_DAPM_ENUM("ADC Input Capture Mux", mic_linein_enum);
	124
	125	static const struct snd_kcontrol_new loopback_ctl =
	126	SOC_DAPM_SINGLE("Switch", CS4265_SIG_SEL, 1, 1, 0);
	127
	128	static const struct snd_kcontrol_new spdif_switch =
	129	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 0, 0);
	130
	131	static const struct snd_kcontrol_new dac_switch =
	132	SOC_DAPM_SINGLE("Switch", CS4265_PWRCTL, 1, 1, 0);
	133
	134	static const struct snd_kcontrol_new cs4265_snd_controls[] = {
	135
	136	SOC_DOUBLE_R_SX_TLV("PGA Volume", CS4265_CHA_PGA_CTL,
	137	CS4265_CHB_PGA_CTL, 0, 0x28, 0x30, pga_tlv),
	138	SOC_DOUBLE_R_TLV("DAC Volume", CS4265_DAC_CHA_VOL,
	139	CS4265_DAC_CHB_VOL, 0, 0xFF, 1, dac_tlv),
	140	SOC_SINGLE("De-emp 44.1kHz Switch", CS4265_DAC_CTL, 1,
141	1, 0),
142	SOC_SINGLE("DAC INV Switch", CS4265_DAC_CTL2, 5,
143	1, 0),
144	SOC_SINGLE("DAC Zero Cross Switch", CS4265_DAC_CTL2, 6,
145	1, 0),
146	SOC_SINGLE("DAC Soft Ramp Switch", CS4265_DAC_CTL2, 7,
147	1, 0),
148	SOC_SINGLE("ADC HPF Switch", CS4265_ADC_CTL, 1,
149	1, 0),
150	SOC_SINGLE("ADC Zero Cross Switch", CS4265_ADC_CTL2, 3,
151	1, 1),
152	SOC_SINGLE("ADC Soft Ramp Switch", CS4265_ADC_CTL2, 7,
153	1, 0),
154	SOC_SINGLE("E to F Buffer Disable Switch", CS4265_SPDIF_CTL1,
155	6, 1, 0),
156	SOC_ENUM("C Data Access", cam_mode_enum),
f853d6b3	157	SOC_SINGLE("SPDIF Switch", CS4265_SPDIF_CTL2, 5, 1, 1),
fb6f8069 PH	158	SOC_SINGLE("Validity Bit Control Switch", CS4265_SPDIF_CTL2,
	159	3, 1, 0),
	160	SOC_ENUM("SPDIF Mono/Stereo", spdif_mono_stereo_enum),
6f18bcda	161	SOC_SINGLE("MMTLR Data Switch", CS4265_SPDIF_CTL2, 0, 1, 0),
fb6f8069 PH	162	SOC_ENUM("Mono Channel Select", spdif_mono_select_enum),
	163	SND_SOC_BYTES("C Data Buffer", CS4265_C_DATA_BUFF, 24),
	164	};
	165
	166	static const struct snd_soc_dapm_widget cs4265_dapm_widgets[] = {
	167
	168	SND_SOC_DAPM_INPUT("LINEINL"),
	169	SND_SOC_DAPM_INPUT("LINEINR"),
	170	SND_SOC_DAPM_INPUT("MICL"),
	171	SND_SOC_DAPM_INPUT("MICR"),
	172
	173	SND_SOC_DAPM_AIF_OUT("DOUT", NULL, 0,
	174	SND_SOC_NOPM, 0, 0),
	175	SND_SOC_DAPM_AIF_OUT("SPDIFOUT", NULL, 0,
	176	SND_SOC_NOPM, 0, 0),
	177
	178	SND_SOC_DAPM_MUX("ADC Mux", SND_SOC_NOPM, 0, 0, &mic_linein_mux),
	179
	180	SND_SOC_DAPM_ADC("ADC", NULL, CS4265_PWRCTL, 2, 1),
	181	SND_SOC_DAPM_PGA("Pre-amp MIC", CS4265_PWRCTL, 3,
	182	1, NULL, 0),
	183
	184	SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM,
	185	0, 0, &digital_input_mux),
	186
	187	SND_SOC_DAPM_MIXER("SDIN1 Input Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
	188	SND_SOC_DAPM_MIXER("SDIN2 Input Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
	189	SND_SOC_DAPM_MIXER("SPDIF Transmitter", SND_SOC_NOPM, 0, 0, NULL, 0),
	190
	191	SND_SOC_DAPM_SWITCH("Loopback", SND_SOC_NOPM, 0, 0,
	192	&loopback_ctl),
	193	SND_SOC_DAPM_SWITCH("SPDIF", SND_SOC_NOPM, 0, 0,
	194	&spdif_switch),
	195	SND_SOC_DAPM_SWITCH("DAC", CS4265_PWRCTL, 1, 1,
	196	&dac_switch),
	197
	198	SND_SOC_DAPM_AIF_IN("DIN1", NULL, 0,
	199	SND_SOC_NOPM, 0, 0),
	200	SND_SOC_DAPM_AIF_IN("DIN2", NULL, 0,
	201	SND_SOC_NOPM, 0, 0),
	202	SND_SOC_DAPM_AIF_IN("TXIN", NULL, 0,
	203	CS4265_SPDIF_CTL2, 5, 1),
	204
	205	SND_SOC_DAPM_OUTPUT("LINEOUTL"),
	206	SND_SOC_DAPM_OUTPUT("LINEOUTR"),
	207
	208	};
	209
	210	static const struct snd_soc_dapm_route cs4265_audio_map[] = {
	211
	212	{"DIN1", NULL, "DAI1 Playback"},
	213	{"DIN2", NULL, "DAI2 Playback"},
	214	{"SDIN1 Input Mixer", NULL, "DIN1"},
	215	{"SDIN2 Input Mixer", NULL, "DIN2"},
	216	{"Input Mux", "SDIN1", "SDIN1 Input Mixer"},
	217	{"Input Mux", "SDIN2", "SDIN2 Input Mixer"},
	218	{"DAC", "Switch", "Input Mux"},
	219	{"SPDIF", "Switch", "Input Mux"},
	220	{"LINEOUTL", NULL, "DAC"},
	221	{"LINEOUTR", NULL, "DAC"},
	222	{"SPDIFOUT", NULL, "SPDIF"},
	223
b0ef5011 MF	224	{"Pre-amp MIC", NULL, "MICL"},
	225	{"Pre-amp MIC", NULL, "MICR"},
	226	{"ADC Mux", "MIC", "Pre-amp MIC"},
fb6f8069 PH	227	{"ADC Mux", "LINEIN", "LINEINL"},
fb6f8069 PH	228	{"ADC Mux", "LINEIN", "LINEINR"},
fb6f8069 PH	229	{"ADC", NULL, "ADC Mux"},
	230	{"DOUT", NULL, "ADC"},
	231	{"DAI1 Capture", NULL, "DOUT"},
	232	{"DAI2 Capture", NULL, "DOUT"},
	233
	234	/* Loopback */
	235	{"Loopback", "Switch", "ADC"},
	236	{"DAC", NULL, "Loopback"},
	237	};
	238
	239	struct cs4265_clk_para {
	240	u32 mclk;
	241	u32 rate;
	242	u8 fm_mode; /* values 1, 2, or 4 */
	243	u8 mclkdiv;
	244	};
	245
	246	static const struct cs4265_clk_para clk_map_table[] = {
	247	/32k/
	248	{8192000, 32000, 0, 0},
	249	{12288000, 32000, 0, 1},
	250	{16384000, 32000, 0, 2},
	251	{24576000, 32000, 0, 3},
	252	{32768000, 32000, 0, 4},
	253
	254	/44.1k/
	255	{11289600, 44100, 0, 0},
	256	{16934400, 44100, 0, 1},
	257	{22579200, 44100, 0, 2},
	258	{33868000, 44100, 0, 3},
	259	{45158400, 44100, 0, 4},
	260
	261	/48k/
	262	{12288000, 48000, 0, 0},
	263	{18432000, 48000, 0, 1},
	264	{24576000, 48000, 0, 2},
	265	{36864000, 48000, 0, 3},
	266	{49152000, 48000, 0, 4},
	267
	268	/64k/
	269	{8192000, 64000, 1, 0},
c98853ae PH	270	{12288000, 64000, 1, 1},
	271	{16934400, 64000, 1, 2},
	272	{24576000, 64000, 1, 3},
	273	{32768000, 64000, 1, 4},
fb6f8069 PH	274
	275	/* 88.2k */
	276	{11289600, 88200, 1, 0},
	277	{16934400, 88200, 1, 1},
	278	{22579200, 88200, 1, 2},
	279	{33868000, 88200, 1, 3},
	280	{45158400, 88200, 1, 4},
	281
	282	/* 96k */
	283	{12288000, 96000, 1, 0},
	284	{18432000, 96000, 1, 1},
	285	{24576000, 96000, 1, 2},
	286	{36864000, 96000, 1, 3},
	287	{49152000, 96000, 1, 4},
	288
	289	/* 128k */
	290	{8192000, 128000, 2, 0},
	291	{12288000, 128000, 2, 1},
	292	{16934400, 128000, 2, 2},
	293	{24576000, 128000, 2, 3},
	294	{32768000, 128000, 2, 4},
	295
	296	/* 176.4k */
	297	{11289600, 176400, 2, 0},
	298	{16934400, 176400, 2, 1},
	299	{22579200, 176400, 2, 2},
	300	{33868000, 176400, 2, 3},
	301	{49152000, 176400, 2, 4},
	302
	303	/* 192k */
	304	{12288000, 192000, 2, 0},
	305	{18432000, 192000, 2, 1},
	306	{24576000, 192000, 2, 2},
	307	{36864000, 192000, 2, 3},
	308	{49152000, 192000, 2, 4},
	309	};
	310
	311	static int cs4265_get_clk_index(int mclk, int rate)
	312	{
	313	int i;
	314
	315	for (i = 0; i < ARRAY_SIZE(clk_map_table); i++) {
	316	if (clk_map_table[i].rate == rate &&
	317	clk_map_table[i].mclk == mclk)
	318	return i;
	319	}
	320	return -EINVAL;
	321	}
	322
	323	static int cs4265_set_sysclk(struct snd_soc_dai *codec_dai, int clk_id,
	324	unsigned int freq, int dir)
	325	{
aebbf9cc KM	326	struct snd_soc_component *component = codec_dai->component;
aebbf9cc KM	327	struct cs4265_private *cs4265 = snd_soc_component_get_drvdata(component);
fb6f8069 PH	328	int i;
	329
	330	if (clk_id != 0) {
aebbf9cc	331	dev_err(component->dev, "Invalid clk_id %d\n", clk_id);
fb6f8069 PH	332	return -EINVAL;
	333	}
	334	for (i = 0; i < ARRAY_SIZE(clk_map_table); i++) {
	335	if (clk_map_table[i].mclk == freq) {
	336	cs4265->sysclk = freq;
	337	return 0;
	338	}
	339	}
	340	cs4265->sysclk = 0;
aebbf9cc	341	dev_err(component->dev, "Invalid freq parameter %d\n", freq);
fb6f8069 PH	342	return -EINVAL;
	343	}
	344
	345	static int cs4265_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
	346	{
aebbf9cc KM	347	struct snd_soc_component *component = codec_dai->component;
aebbf9cc KM	348	struct cs4265_private *cs4265 = snd_soc_component_get_drvdata(component);
fb6f8069 PH	349	u8 iface = 0;
	350
	351	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	352	case SND_SOC_DAIFMT_CBM_CFM:
aebbf9cc	353	snd_soc_component_update_bits(component, CS4265_ADC_CTL,
fb6f8069 PH	354	CS4265_ADC_MASTER,
	355	CS4265_ADC_MASTER);
	356	break;
	357	case SND_SOC_DAIFMT_CBS_CFS:
aebbf9cc	358	snd_soc_component_update_bits(component, CS4265_ADC_CTL,
fb6f8069 PH	359	CS4265_ADC_MASTER,
	360	0);
	361	break;
	362	default:
	363	return -EINVAL;
	364	}
	365
	366	/* interface format */
	367	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	368	case SND_SOC_DAIFMT_I2S:
	369	iface \|= SND_SOC_DAIFMT_I2S;
	370	break;
	371	case SND_SOC_DAIFMT_RIGHT_J:
	372	iface \|= SND_SOC_DAIFMT_RIGHT_J;
	373	break;
	374	case SND_SOC_DAIFMT_LEFT_J:
	375	iface \|= SND_SOC_DAIFMT_LEFT_J;
	376	break;
	377	default:
	378	return -EINVAL;
	379	}
	380
	381	cs4265->format = iface;
	382	return 0;
	383	}
	384
	385	static int cs4265_digital_mute(struct snd_soc_dai *dai, int mute)
	386	{
aebbf9cc	387	struct snd_soc_component *component = dai->component;
fb6f8069 PH	388
fb6f8069 PH	389	if (mute) {
aebbf9cc	390	snd_soc_component_update_bits(component, CS4265_DAC_CTL,
fb6f8069 PH	391	CS4265_DAC_CTL_MUTE,
fb6f8069 PH	392	CS4265_DAC_CTL_MUTE);
aebbf9cc	393	snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2,
fb6f8069 PH	394	CS4265_SPDIF_CTL2_MUTE,
	395	CS4265_SPDIF_CTL2_MUTE);
	396	} else {
aebbf9cc	397	snd_soc_component_update_bits(component, CS4265_DAC_CTL,
fb6f8069 PH	398	CS4265_DAC_CTL_MUTE,
fb6f8069 PH	399	0);
aebbf9cc	400	snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2,
fb6f8069 PH	401	CS4265_SPDIF_CTL2_MUTE,
	402	0);
	403	}
	404	return 0;
	405	}
	406
	407	static int cs4265_pcm_hw_params(struct snd_pcm_substream *substream,
	408	struct snd_pcm_hw_params *params,
	409	struct snd_soc_dai *dai)
	410	{
aebbf9cc KM	411	struct snd_soc_component *component = dai->component;
aebbf9cc KM	412	struct cs4265_private *cs4265 = snd_soc_component_get_drvdata(component);
fb6f8069 PH	413	int index;
	414
	415	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE &&
	416	((cs4265->format & SND_SOC_DAIFMT_FORMAT_MASK)
	417	== SND_SOC_DAIFMT_RIGHT_J))
	418	return -EINVAL;
	419
	420	index = cs4265_get_clk_index(cs4265->sysclk, params_rate(params));
	421	if (index >= 0) {
aebbf9cc	422	snd_soc_component_update_bits(component, CS4265_ADC_CTL,
fb18cd2a	423	CS4265_ADC_FM, clk_map_table[index].fm_mode << 6);
aebbf9cc	424	snd_soc_component_update_bits(component, CS4265_MCLK_FREQ,
fb6f8069	425	CS4265_MCLK_FREQ_MASK,
fb18cd2a	426	clk_map_table[index].mclkdiv << 4);
fb6f8069 PH	427
fb6f8069 PH	428	} else {
aebbf9cc	429	dev_err(component->dev, "can't get correct mclk\n");
fb6f8069 PH	430	return -EINVAL;
	431	}
	432
	433	switch (cs4265->format & SND_SOC_DAIFMT_FORMAT_MASK) {
	434	case SND_SOC_DAIFMT_I2S:
aebbf9cc	435	snd_soc_component_update_bits(component, CS4265_DAC_CTL,
fb6f8069	436	CS4265_DAC_CTL_DIF, (1 << 4));
aebbf9cc	437	snd_soc_component_update_bits(component, CS4265_ADC_CTL,
fb6f8069	438	CS4265_ADC_DIF, (1 << 4));
aebbf9cc	439	snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2,
fb6f8069 PH	440	CS4265_SPDIF_CTL2_DIF, (1 << 6));
	441	break;
	442	case SND_SOC_DAIFMT_RIGHT_J:
12efd9f4	443	if (params_width(params) == 16) {
aebbf9cc	444	snd_soc_component_update_bits(component, CS4265_DAC_CTL,
bffc4496	445	CS4265_DAC_CTL_DIF, (2 << 4));
aebbf9cc	446	snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2,
bffc4496	447	CS4265_SPDIF_CTL2_DIF, (2 << 6));
fb6f8069	448	} else {
aebbf9cc	449	snd_soc_component_update_bits(component, CS4265_DAC_CTL,
bffc4496	450	CS4265_DAC_CTL_DIF, (3 << 4));
aebbf9cc	451	snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2,
bffc4496	452	CS4265_SPDIF_CTL2_DIF, (3 << 6));
fb6f8069 PH	453	}
	454	break;
	455	case SND_SOC_DAIFMT_LEFT_J:
aebbf9cc	456	snd_soc_component_update_bits(component, CS4265_DAC_CTL,
fb6f8069	457	CS4265_DAC_CTL_DIF, 0);
aebbf9cc	458	snd_soc_component_update_bits(component, CS4265_ADC_CTL,
fb6f8069	459	CS4265_ADC_DIF, 0);
aebbf9cc	460	snd_soc_component_update_bits(component, CS4265_SPDIF_CTL2,
bffc4496	461	CS4265_SPDIF_CTL2_DIF, 0);
fb6f8069 PH	462
	463	break;
	464	default:
	465	return -EINVAL;
	466	}
	467	return 0;
	468	}
	469
aebbf9cc	470	static int cs4265_set_bias_level(struct snd_soc_component *component,
fb6f8069 PH	471	enum snd_soc_bias_level level)
	472	{
	473	switch (level) {
	474	case SND_SOC_BIAS_ON:
	475	break;
	476	case SND_SOC_BIAS_PREPARE:
aebbf9cc	477	snd_soc_component_update_bits(component, CS4265_PWRCTL,
fb6f8069 PH	478	CS4265_PWRCTL_PDN, 0);
	479	break;
	480	case SND_SOC_BIAS_STANDBY:
aebbf9cc	481	snd_soc_component_update_bits(component, CS4265_PWRCTL,
fb6f8069 PH	482	CS4265_PWRCTL_PDN,
	483	CS4265_PWRCTL_PDN);
	484	break;
	485	case SND_SOC_BIAS_OFF:
aebbf9cc	486	snd_soc_component_update_bits(component, CS4265_PWRCTL,
fb6f8069 PH	487	CS4265_PWRCTL_PDN,
	488	CS4265_PWRCTL_PDN);
	489	break;
	490	}
fb6f8069 PH	491	return 0;
	492	}
	493
	494	#define CS4265_RATES (SNDRV_PCM_RATE_32000 \| SNDRV_PCM_RATE_44100 \| \
	495	SNDRV_PCM_RATE_48000 \| SNDRV_PCM_RATE_64000 \| \
	496	SNDRV_PCM_RATE_88200 \| SNDRV_PCM_RATE_96000 \| \
	497	SNDRV_PCM_RATE_176400 \| SNDRV_PCM_RATE_192000)
	498
	499	#define CS4265_FORMATS (SNDRV_PCM_FMTBIT_S16_LE \| SNDRV_PCM_FMTBIT_U16_LE \| \
be47e75e MF	500	SNDRV_PCM_FMTBIT_S24_LE \| SNDRV_PCM_FMTBIT_U24_LE \| \
be47e75e MF	501	SNDRV_PCM_FMTBIT_S32_LE \| SNDRV_PCM_FMTBIT_U32_LE)
fb6f8069 PH	502
	503	static const struct snd_soc_dai_ops cs4265_ops = {
	504	.hw_params = cs4265_pcm_hw_params,
	505	.digital_mute = cs4265_digital_mute,
	506	.set_fmt = cs4265_set_fmt,
	507	.set_sysclk = cs4265_set_sysclk,
	508	};
	509
	510	static struct snd_soc_dai_driver cs4265_dai[] = {
	511	{
	512	.name = "cs4265-dai1",
	513	.playback = {
	514	.stream_name = "DAI1 Playback",
	515	.channels_min = 1,
	516	.channels_max = 2,
	517	.rates = CS4265_RATES,
	518	.formats = CS4265_FORMATS,
	519	},
	520	.capture = {
	521	.stream_name = "DAI1 Capture",
	522	.channels_min = 1,
	523	.channels_max = 2,
	524	.rates = CS4265_RATES,
	525	.formats = CS4265_FORMATS,
	526	},
	527	.ops = &cs4265_ops,
	528	},
	529	{
	530	.name = "cs4265-dai2",
	531	.playback = {
	532	.stream_name = "DAI2 Playback",
	533	.channels_min = 1,
	534	.channels_max = 2,
	535	.rates = CS4265_RATES,
	536	.formats = CS4265_FORMATS,
	537	},
	538	.capture = {
	539	.stream_name = "DAI2 Capture",
	540	.channels_min = 1,
	541	.channels_max = 2,
	542	.rates = CS4265_RATES,
	543	.formats = CS4265_FORMATS,
	544	},
	545	.ops = &cs4265_ops,
	546	},
	547	};
	548
aebbf9cc KM	549	static const struct snd_soc_component_driver soc_component_cs4265 = {
	550	.set_bias_level = cs4265_set_bias_level,
	551	.controls = cs4265_snd_controls,
	552	.num_controls = ARRAY_SIZE(cs4265_snd_controls),
	553	.dapm_widgets = cs4265_dapm_widgets,
	554	.num_dapm_widgets = ARRAY_SIZE(cs4265_dapm_widgets),
	555	.dapm_routes = cs4265_audio_map,
	556	.num_dapm_routes = ARRAY_SIZE(cs4265_audio_map),
	557	.idle_bias_on = 1,
	558	.use_pmdown_time = 1,
	559	.endianness = 1,
	560	.non_legacy_dai_naming = 1,
fb6f8069 PH	561	};
	562
	563	static const struct regmap_config cs4265_regmap = {
	564	.reg_bits = 8,
	565	.val_bits = 8,
	566
	567	.max_register = CS4265_MAX_REGISTER,
	568	.reg_defaults = cs4265_reg_defaults,
	569	.num_reg_defaults = ARRAY_SIZE(cs4265_reg_defaults),
	570	.readable_reg = cs4265_readable_register,
	571	.volatile_reg = cs4265_volatile_register,
	572	.cache_type = REGCACHE_RBTREE,
	573	};
	574
	575	static int cs4265_i2c_probe(struct i2c_client *i2c_client,
	576	const struct i2c_device_id *id)
	577	{
	578	struct cs4265_private *cs4265;
	579	int ret = 0;
	580	unsigned int devid = 0;
	581	unsigned int reg;
	582
	583	cs4265 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs4265_private),
	584	GFP_KERNEL);
	585	if (cs4265 == NULL)
	586	return -ENOMEM;
fb6f8069 PH	587
	588	cs4265->regmap = devm_regmap_init_i2c(i2c_client, &cs4265_regmap);
	589	if (IS_ERR(cs4265->regmap)) {
	590	ret = PTR_ERR(cs4265->regmap);
	591	dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
	592	return ret;
	593	}
	594
34d7c390 UKK	595	cs4265->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
	596	"reset", GPIOD_OUT_LOW);
	597	if (IS_ERR(cs4265->reset_gpio))
	598	return PTR_ERR(cs4265->reset_gpio);
	599
	600	if (cs4265->reset_gpio) {
fb6f8069 PH	601	mdelay(1);
fb6f8069 PH	602	gpiod_set_value_cansleep(cs4265->reset_gpio, 1);
fb6f8069 PH	603	}
	604
	605	i2c_set_clientdata(i2c_client, cs4265);
	606
	607	ret = regmap_read(cs4265->regmap, CS4265_CHIP_ID, &reg);
	608	devid = reg & CS4265_CHIP_ID_MASK;
	609	if (devid != CS4265_CHIP_ID_VAL) {
	610	ret = -ENODEV;
	611	dev_err(&i2c_client->dev,
	612	"CS4265 Device ID (%X). Expected %X\n",
	613	devid, CS4265_CHIP_ID);
	614	return ret;
	615	}
	616	dev_info(&i2c_client->dev,
	617	"CS4265 Version %x\n",
	618	reg & CS4265_REV_ID_MASK);
	619
	620	regmap_write(cs4265->regmap, CS4265_PWRCTL, 0x0F);
	621
aebbf9cc KM	622	ret = devm_snd_soc_register_component(&i2c_client->dev,
aebbf9cc KM	623	&soc_component_cs4265, cs4265_dai,
fb6f8069 PH	624	ARRAY_SIZE(cs4265_dai));
	625	return ret;
	626	}
	627
fb6f8069 PH	628	static const struct of_device_id cs4265_of_match[] = {
	629	{ .compatible = "cirrus,cs4265", },
	630	{ }
	631	};
	632	MODULE_DEVICE_TABLE(of, cs4265_of_match);
	633
	634	static const struct i2c_device_id cs4265_id[] = {
	635	{ "cs4265", 0 },
	636	{ }
	637	};
	638	MODULE_DEVICE_TABLE(i2c, cs4265_id);
	639
	640	static struct i2c_driver cs4265_i2c_driver = {
	641	.driver = {
	642	.name = "cs4265",
fb6f8069 PH	643	.of_match_table = cs4265_of_match,
	644	},
	645	.id_table = cs4265_id,
	646	.probe = cs4265_i2c_probe,
fb6f8069 PH	647	};
	648
	649	module_i2c_driver(cs4265_i2c_driver);
	650
	651	MODULE_DESCRIPTION("ASoC CS4265 driver");
	652	MODULE_AUTHOR("Paul Handrigan, Cirrus Logic Inc, <paul.handrigan@cirrus.com>");
	653	MODULE_LICENSE("GPL");