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Merge tag 'sound-6.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai...
[linux-block.git] / sound / soc / codecs / cs35l45.c
CommitLineData
0d463d01
JS		 1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2//
3// cs35l45.c - CS35L45 ALSA SoC audio driver
4//
5// Copyright 2019-2022 Cirrus Logic, Inc.
6//
7// Author: James Schulman <james.schulman@cirrus.com>
8
9#include <linux/gpio/consumer.h>
10#include <linux/module.h>
11#include <linux/pm_runtime.h>
12#include <linux/property.h>
74b14e28 13#include <linux/firmware.h>
0d463d01
JS		 14#include <linux/regulator/consumer.h>
15#include <sound/core.h>
16#include <sound/pcm.h>
17#include <sound/pcm_params.h>
18#include <sound/soc.h>
19#include <sound/tlv.h>
20
21#include "cs35l45.h"
22
74b14e28
VK		 23static bool cs35l45_check_cspl_mbox_sts(const enum cs35l45_cspl_mboxcmd cmd,
24 enum cs35l45_cspl_mboxstate sts)
25{
26 switch (cmd) {
27 case CSPL_MBOX_CMD_NONE:
28 case CSPL_MBOX_CMD_UNKNOWN_CMD:
29 return true;
30 case CSPL_MBOX_CMD_PAUSE:
31 case CSPL_MBOX_CMD_OUT_OF_HIBERNATE:
32 return (sts == CSPL_MBOX_STS_PAUSED);
33 case CSPL_MBOX_CMD_RESUME:
34 return (sts == CSPL_MBOX_STS_RUNNING);
35 case CSPL_MBOX_CMD_REINIT:
36 return (sts == CSPL_MBOX_STS_RUNNING);
37 case CSPL_MBOX_CMD_STOP_PRE_REINIT:
38 return (sts == CSPL_MBOX_STS_RDY_FOR_REINIT);
6c07be8f
VK		 39 case CSPL_MBOX_CMD_HIBERNATE:
40 return (sts == CSPL_MBOX_STS_HIBERNATE);
74b14e28
VK		 41 default:
42 return false;
43 }
44}
45
46static int cs35l45_set_cspl_mbox_cmd(struct cs35l45_private *cs35l45,
47 struct regmap *regmap,
48 const enum cs35l45_cspl_mboxcmd cmd)
49{
50 unsigned int sts = 0, i;
51 int ret;
52
53 if (!cs35l45->dsp.cs_dsp.running) {
54 dev_err(cs35l45->dev, "DSP not running\n");
55 return -EPERM;
56 }
57
58 // Set mailbox cmd
59 ret = regmap_write(regmap, CS35L45_DSP_VIRT1_MBOX_1, cmd);
60 if (ret < 0) {
61 if (cmd != CSPL_MBOX_CMD_OUT_OF_HIBERNATE)
62 dev_err(cs35l45->dev, "Failed to write MBOX: %d\n", ret);
63 return ret;
64 }
65
66 // Read mailbox status and verify it is appropriate for the given cmd
67 for (i = 0; i < 5; i++) {
68 usleep_range(1000, 1100);
69
70 ret = regmap_read(regmap, CS35L45_DSP_MBOX_2, &sts);
71 if (ret < 0) {
72 dev_err(cs35l45->dev, "Failed to read MBOX STS: %d\n", ret);
73 continue;
74 }
75
76 if (!cs35l45_check_cspl_mbox_sts(cmd, sts))
77 dev_dbg(cs35l45->dev, "[%u] cmd %u returned invalid sts %u", i, cmd, sts);
78 else
79 return 0;
80 }
81
82 if (cmd != CSPL_MBOX_CMD_OUT_OF_HIBERNATE)
83 dev_err(cs35l45->dev, "Failed to set mailbox cmd %u (status %u)\n", cmd, sts);
84
85 return -ENOMSG;
86}
87
0d463d01
JS		 88static int cs35l45_global_en_ev(struct snd_soc_dapm_widget *w,
89 struct snd_kcontrol *kcontrol, int event)
90{
91 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
92 struct cs35l45_private *cs35l45 = snd_soc_component_get_drvdata(component);
93
94 dev_dbg(cs35l45->dev, "%s event : %x\n", __func__, event);
95
96 switch (event) {
97 case SND_SOC_DAPM_POST_PMU:
98 regmap_write(cs35l45->regmap, CS35L45_GLOBAL_ENABLES,
99 CS35L45_GLOBAL_EN_MASK);
100
101 usleep_range(CS35L45_POST_GLOBAL_EN_US, CS35L45_POST_GLOBAL_EN_US + 100);
102 break;
103 case SND_SOC_DAPM_PRE_PMD:
104 usleep_range(CS35L45_PRE_GLOBAL_DIS_US, CS35L45_PRE_GLOBAL_DIS_US + 100);
105
106 regmap_write(cs35l45->regmap, CS35L45_GLOBAL_ENABLES, 0);
107 break;
108 default:
109 break;
110 }
111
112 return 0;
113}
114
74b14e28
VK		 115static int cs35l45_dsp_preload_ev(struct snd_soc_dapm_widget *w,
116 struct snd_kcontrol *kcontrol, int event)
117{
118 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
119 struct cs35l45_private *cs35l45 = snd_soc_component_get_drvdata(component);
120 int ret;
121
122 switch (event) {
123 case SND_SOC_DAPM_PRE_PMU:
124 if (cs35l45->dsp.cs_dsp.booted)
125 return 0;
126
127 return wm_adsp_early_event(w, kcontrol, event);
128 case SND_SOC_DAPM_POST_PMU:
129 if (cs35l45->dsp.cs_dsp.running)
130 return 0;
131
132 regmap_set_bits(cs35l45->regmap, CS35L45_PWRMGT_CTL,
133 CS35L45_MEM_RDY_MASK);
134
135 return wm_adsp_event(w, kcontrol, event);
136 case SND_SOC_DAPM_PRE_PMD:
137 if (cs35l45->dsp.preloaded)
138 return 0;
139
140 if (cs35l45->dsp.cs_dsp.running) {
141 ret = wm_adsp_event(w, kcontrol, event);
142 if (ret)
143 return ret;
144 }
145
146 return wm_adsp_early_event(w, kcontrol, event);
147 default:
148 return 0;
149 }
150}
151
152static int cs35l45_dsp_audio_ev(struct snd_soc_dapm_widget *w,
153 struct snd_kcontrol *kcontrol, int event)
154{
155 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
156 struct cs35l45_private *cs35l45 = snd_soc_component_get_drvdata(component);
157
158 switch (event) {
159 case SND_SOC_DAPM_POST_PMU:
160 return cs35l45_set_cspl_mbox_cmd(cs35l45, cs35l45->regmap,
161 CSPL_MBOX_CMD_RESUME);
162 case SND_SOC_DAPM_PRE_PMD:
163 return cs35l45_set_cspl_mbox_cmd(cs35l45, cs35l45->regmap,
164 CSPL_MBOX_CMD_PAUSE);
165 default:
166 return 0;
167 }
168
169 return 0;
170}
171
0d463d01
JS		 172static const char * const cs35l45_asp_tx_txt[] = {
173 "Zero", "ASP_RX1", "ASP_RX2",
174 "VMON", "IMON", "ERR_VOL",
175 "VDD_BATTMON", "VDD_BSTMON",
74b14e28 176 "DSP_TX1", "DSP_TX2",
0d463d01
JS		 177 "Interpolator", "IL_TARGET",
178};
179
180static const unsigned int cs35l45_asp_tx_val[] = {
181 CS35L45_PCM_SRC_ZERO, CS35L45_PCM_SRC_ASP_RX1, CS35L45_PCM_SRC_ASP_RX2,
182 CS35L45_PCM_SRC_VMON, CS35L45_PCM_SRC_IMON, CS35L45_PCM_SRC_ERR_VOL,
183 CS35L45_PCM_SRC_VDD_BATTMON, CS35L45_PCM_SRC_VDD_BSTMON,
74b14e28 184 CS35L45_PCM_SRC_DSP_TX1, CS35L45_PCM_SRC_DSP_TX2,
0d463d01
JS		 185 CS35L45_PCM_SRC_INTERPOLATOR, CS35L45_PCM_SRC_IL_TARGET,
186};
187
188static const struct soc_enum cs35l45_asp_tx_enums[] = {
189 SOC_VALUE_ENUM_SINGLE(CS35L45_ASPTX1_INPUT, 0, CS35L45_PCM_SRC_MASK,
190 ARRAY_SIZE(cs35l45_asp_tx_txt), cs35l45_asp_tx_txt,
191 cs35l45_asp_tx_val),
192 SOC_VALUE_ENUM_SINGLE(CS35L45_ASPTX2_INPUT, 0, CS35L45_PCM_SRC_MASK,
193 ARRAY_SIZE(cs35l45_asp_tx_txt), cs35l45_asp_tx_txt,
194 cs35l45_asp_tx_val),
195 SOC_VALUE_ENUM_SINGLE(CS35L45_ASPTX3_INPUT, 0, CS35L45_PCM_SRC_MASK,
196 ARRAY_SIZE(cs35l45_asp_tx_txt), cs35l45_asp_tx_txt,
197 cs35l45_asp_tx_val),
198 SOC_VALUE_ENUM_SINGLE(CS35L45_ASPTX4_INPUT, 0, CS35L45_PCM_SRC_MASK,
199 ARRAY_SIZE(cs35l45_asp_tx_txt), cs35l45_asp_tx_txt,
200 cs35l45_asp_tx_val),
201 SOC_VALUE_ENUM_SINGLE(CS35L45_ASPTX5_INPUT, 0, CS35L45_PCM_SRC_MASK,
202 ARRAY_SIZE(cs35l45_asp_tx_txt), cs35l45_asp_tx_txt,
203 cs35l45_asp_tx_val),
204};
205
74b14e28
VK		 206static const char * const cs35l45_dsp_rx_txt[] = {
207 "Zero", "ASP_RX1", "ASP_RX2",
208 "VMON", "IMON", "ERR_VOL",
209 "CLASSH_TGT", "VDD_BATTMON",
210 "VDD_BSTMON", "TEMPMON",
211};
212
213static const unsigned int cs35l45_dsp_rx_val[] = {
214 CS35L45_PCM_SRC_ZERO, CS35L45_PCM_SRC_ASP_RX1, CS35L45_PCM_SRC_ASP_RX2,
215 CS35L45_PCM_SRC_VMON, CS35L45_PCM_SRC_IMON, CS35L45_PCM_SRC_ERR_VOL,
216 CS35L45_PCM_SRC_CLASSH_TGT, CS35L45_PCM_SRC_VDD_BATTMON,
217 CS35L45_PCM_SRC_VDD_BSTMON, CS35L45_PCM_SRC_TEMPMON,
218};
219
220static const struct soc_enum cs35l45_dsp_rx_enums[] = {
221 SOC_VALUE_ENUM_SINGLE(CS35L45_DSP1RX1_INPUT, 0, CS35L45_PCM_SRC_MASK,
222 ARRAY_SIZE(cs35l45_dsp_rx_txt), cs35l45_dsp_rx_txt,
223 cs35l45_dsp_rx_val),
224 SOC_VALUE_ENUM_SINGLE(CS35L45_DSP1RX2_INPUT, 0, CS35L45_PCM_SRC_MASK,
225 ARRAY_SIZE(cs35l45_dsp_rx_txt), cs35l45_dsp_rx_txt,
226 cs35l45_dsp_rx_val),
227 SOC_VALUE_ENUM_SINGLE(CS35L45_DSP1RX3_INPUT, 0, CS35L45_PCM_SRC_MASK,
228 ARRAY_SIZE(cs35l45_dsp_rx_txt), cs35l45_dsp_rx_txt,
229 cs35l45_dsp_rx_val),
230 SOC_VALUE_ENUM_SINGLE(CS35L45_DSP1RX4_INPUT, 0, CS35L45_PCM_SRC_MASK,
231 ARRAY_SIZE(cs35l45_dsp_rx_txt), cs35l45_dsp_rx_txt,
232 cs35l45_dsp_rx_val),
233 SOC_VALUE_ENUM_SINGLE(CS35L45_DSP1RX5_INPUT, 0, CS35L45_PCM_SRC_MASK,
234 ARRAY_SIZE(cs35l45_dsp_rx_txt), cs35l45_dsp_rx_txt,
235 cs35l45_dsp_rx_val),
236 SOC_VALUE_ENUM_SINGLE(CS35L45_DSP1RX6_INPUT, 0, CS35L45_PCM_SRC_MASK,
237 ARRAY_SIZE(cs35l45_dsp_rx_txt), cs35l45_dsp_rx_txt,
238 cs35l45_dsp_rx_val),
239 SOC_VALUE_ENUM_SINGLE(CS35L45_DSP1RX7_INPUT, 0, CS35L45_PCM_SRC_MASK,
240 ARRAY_SIZE(cs35l45_dsp_rx_txt), cs35l45_dsp_rx_txt,
241 cs35l45_dsp_rx_val),
242 SOC_VALUE_ENUM_SINGLE(CS35L45_DSP1RX8_INPUT, 0, CS35L45_PCM_SRC_MASK,
243 ARRAY_SIZE(cs35l45_dsp_rx_txt), cs35l45_dsp_rx_txt,
244 cs35l45_dsp_rx_val),
245};
246
0d463d01 247static const char * const cs35l45_dac_txt[] = {
74b14e28 248 "Zero", "ASP_RX1", "ASP_RX2", "DSP_TX1", "DSP_TX2"
0d463d01
JS		 249};
250
251static const unsigned int cs35l45_dac_val[] = {
74b14e28
VK		 252 CS35L45_PCM_SRC_ZERO, CS35L45_PCM_SRC_ASP_RX1, CS35L45_PCM_SRC_ASP_RX2,
253 CS35L45_PCM_SRC_DSP_TX1, CS35L45_PCM_SRC_DSP_TX2
0d463d01
JS		 254};
255
256static const struct soc_enum cs35l45_dacpcm_enums[] = {
257 SOC_VALUE_ENUM_SINGLE(CS35L45_DACPCM1_INPUT, 0, CS35L45_PCM_SRC_MASK,
258 ARRAY_SIZE(cs35l45_dac_txt), cs35l45_dac_txt,
259 cs35l45_dac_val),
260};
261
262static const struct snd_kcontrol_new cs35l45_asp_muxes[] = {
263 SOC_DAPM_ENUM("ASP_TX1 Source", cs35l45_asp_tx_enums[0]),
264 SOC_DAPM_ENUM("ASP_TX2 Source", cs35l45_asp_tx_enums[1]),
265 SOC_DAPM_ENUM("ASP_TX3 Source", cs35l45_asp_tx_enums[2]),
266 SOC_DAPM_ENUM("ASP_TX4 Source", cs35l45_asp_tx_enums[3]),
267 SOC_DAPM_ENUM("ASP_TX5 Source", cs35l45_asp_tx_enums[4]),
268};
269
74b14e28
VK		 270static const struct snd_kcontrol_new cs35l45_dsp_muxes[] = {
271 SOC_DAPM_ENUM("DSP_RX1 Source", cs35l45_dsp_rx_enums[0]),
272 SOC_DAPM_ENUM("DSP_RX2 Source", cs35l45_dsp_rx_enums[1]),
273 SOC_DAPM_ENUM("DSP_RX3 Source", cs35l45_dsp_rx_enums[2]),
274 SOC_DAPM_ENUM("DSP_RX4 Source", cs35l45_dsp_rx_enums[3]),
275 SOC_DAPM_ENUM("DSP_RX5 Source", cs35l45_dsp_rx_enums[4]),
276 SOC_DAPM_ENUM("DSP_RX6 Source", cs35l45_dsp_rx_enums[5]),
277 SOC_DAPM_ENUM("DSP_RX7 Source", cs35l45_dsp_rx_enums[6]),
278 SOC_DAPM_ENUM("DSP_RX8 Source", cs35l45_dsp_rx_enums[7]),
279};
280
0d463d01
JS		 281static const struct snd_kcontrol_new cs35l45_dac_muxes[] = {
282 SOC_DAPM_ENUM("DACPCM1 Source", cs35l45_dacpcm_enums[0]),
283};
284
285static const struct snd_soc_dapm_widget cs35l45_dapm_widgets[] = {
74b14e28
VK		 286 SND_SOC_DAPM_SPK("DSP1 Preload", NULL),
287 SND_SOC_DAPM_SUPPLY_S("DSP1 Preloader", 100, SND_SOC_NOPM, 0, 0,
288 cs35l45_dsp_preload_ev,
289 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
290 SND_SOC_DAPM_OUT_DRV_E("DSP1", SND_SOC_NOPM, 0, 0, NULL, 0,
291 cs35l45_dsp_audio_ev,
292 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
0d463d01
JS		 293 SND_SOC_DAPM_SUPPLY("GLOBAL_EN", SND_SOC_NOPM, 0, 0,
294 cs35l45_global_en_ev,
295 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
296 SND_SOC_DAPM_SUPPLY("ASP_EN", CS35L45_BLOCK_ENABLES2, CS35L45_ASP_EN_SHIFT, 0, NULL, 0),
297
298 SND_SOC_DAPM_SIGGEN("VMON_SRC"),
299 SND_SOC_DAPM_SIGGEN("IMON_SRC"),
300 SND_SOC_DAPM_SIGGEN("VDD_BATTMON_SRC"),
301 SND_SOC_DAPM_SIGGEN("VDD_BSTMON_SRC"),
302 SND_SOC_DAPM_SIGGEN("ERR_VOL"),
303 SND_SOC_DAPM_SIGGEN("AMP_INTP"),
304 SND_SOC_DAPM_SIGGEN("IL_TARGET"),
305 SND_SOC_DAPM_ADC("VMON", NULL, CS35L45_BLOCK_ENABLES, CS35L45_VMON_EN_SHIFT, 0),
306 SND_SOC_DAPM_ADC("IMON", NULL, CS35L45_BLOCK_ENABLES, CS35L45_IMON_EN_SHIFT, 0),
307 SND_SOC_DAPM_ADC("VDD_BATTMON", NULL, CS35L45_BLOCK_ENABLES,
308 CS35L45_VDD_BATTMON_EN_SHIFT, 0),
309 SND_SOC_DAPM_ADC("VDD_BSTMON", NULL, CS35L45_BLOCK_ENABLES,
310 CS35L45_VDD_BSTMON_EN_SHIFT, 0),
311
312 SND_SOC_DAPM_AIF_IN("ASP_RX1", NULL, 0, CS35L45_ASP_ENABLES1, CS35L45_ASP_RX1_EN_SHIFT, 0),
313 SND_SOC_DAPM_AIF_IN("ASP_RX2", NULL, 1, CS35L45_ASP_ENABLES1, CS35L45_ASP_RX2_EN_SHIFT, 0),
314
315 SND_SOC_DAPM_AIF_OUT("ASP_TX1", NULL, 0, CS35L45_ASP_ENABLES1, CS35L45_ASP_TX1_EN_SHIFT, 0),
316 SND_SOC_DAPM_AIF_OUT("ASP_TX2", NULL, 1, CS35L45_ASP_ENABLES1, CS35L45_ASP_TX2_EN_SHIFT, 0),
317 SND_SOC_DAPM_AIF_OUT("ASP_TX3", NULL, 2, CS35L45_ASP_ENABLES1, CS35L45_ASP_TX3_EN_SHIFT, 0),
318 SND_SOC_DAPM_AIF_OUT("ASP_TX4", NULL, 3, CS35L45_ASP_ENABLES1, CS35L45_ASP_TX4_EN_SHIFT, 0),
319 SND_SOC_DAPM_AIF_OUT("ASP_TX5", NULL, 3, CS35L45_ASP_ENABLES1, CS35L45_ASP_TX5_EN_SHIFT, 0),
320
321 SND_SOC_DAPM_MUX("ASP_TX1 Source", SND_SOC_NOPM, 0, 0, &cs35l45_asp_muxes[0]),
322 SND_SOC_DAPM_MUX("ASP_TX2 Source", SND_SOC_NOPM, 0, 0, &cs35l45_asp_muxes[1]),
323 SND_SOC_DAPM_MUX("ASP_TX3 Source", SND_SOC_NOPM, 0, 0, &cs35l45_asp_muxes[2]),
324 SND_SOC_DAPM_MUX("ASP_TX4 Source", SND_SOC_NOPM, 0, 0, &cs35l45_asp_muxes[3]),
325 SND_SOC_DAPM_MUX("ASP_TX5 Source", SND_SOC_NOPM, 0, 0, &cs35l45_asp_muxes[4]),
326
74b14e28
VK		 327 SND_SOC_DAPM_MUX("DSP_RX1 Source", SND_SOC_NOPM, 0, 0, &cs35l45_dsp_muxes[0]),
328 SND_SOC_DAPM_MUX("DSP_RX2 Source", SND_SOC_NOPM, 0, 0, &cs35l45_dsp_muxes[1]),
329 SND_SOC_DAPM_MUX("DSP_RX3 Source", SND_SOC_NOPM, 0, 0, &cs35l45_dsp_muxes[2]),
330 SND_SOC_DAPM_MUX("DSP_RX4 Source", SND_SOC_NOPM, 0, 0, &cs35l45_dsp_muxes[3]),
331 SND_SOC_DAPM_MUX("DSP_RX5 Source", SND_SOC_NOPM, 0, 0, &cs35l45_dsp_muxes[4]),
332 SND_SOC_DAPM_MUX("DSP_RX6 Source", SND_SOC_NOPM, 0, 0, &cs35l45_dsp_muxes[5]),
333 SND_SOC_DAPM_MUX("DSP_RX7 Source", SND_SOC_NOPM, 0, 0, &cs35l45_dsp_muxes[6]),
334 SND_SOC_DAPM_MUX("DSP_RX8 Source", SND_SOC_NOPM, 0, 0, &cs35l45_dsp_muxes[7]),
335
0d463d01
JS		 336 SND_SOC_DAPM_MUX("DACPCM1 Source", SND_SOC_NOPM, 0, 0, &cs35l45_dac_muxes[0]),
337
338 SND_SOC_DAPM_OUT_DRV("AMP", SND_SOC_NOPM, 0, 0, NULL, 0),
339
340 SND_SOC_DAPM_OUTPUT("SPK"),
341};
342
343#define CS35L45_ASP_MUX_ROUTE(name) \
344 { name" Source", "ASP_RX1", "ASP_RX1" }, \
345 { name" Source", "ASP_RX2", "ASP_RX2" }, \
74b14e28
VK		 346 { name" Source", "DSP_TX1", "DSP1" }, \
347 { name" Source", "DSP_TX2", "DSP1" }, \
0d463d01
JS		 348 { name" Source", "VMON", "VMON" }, \
349 { name" Source", "IMON", "IMON" }, \
350 { name" Source", "ERR_VOL", "ERR_VOL" }, \
351 { name" Source", "VDD_BATTMON", "VDD_BATTMON" }, \
352 { name" Source", "VDD_BSTMON", "VDD_BSTMON" }, \
353 { name" Source", "Interpolator", "AMP_INTP" }, \
354 { name" Source", "IL_TARGET", "IL_TARGET" }
355
74b14e28 356#define CS35L45_DSP_MUX_ROUTE(name) \
0d463d01
JS		 357 { name" Source", "ASP_RX1", "ASP_RX1" }, \
358 { name" Source", "ASP_RX2", "ASP_RX2" }
359
74b14e28
VK		 360#define CS35L45_DAC_MUX_ROUTE(name) \
361 { name" Source", "ASP_RX1", "ASP_RX1" }, \
362 { name" Source", "ASP_RX2", "ASP_RX2" }, \
363 { name" Source", "DSP_TX1", "DSP1" }, \
364 { name" Source", "DSP_TX2", "DSP1" }
365
0d463d01
JS		 366static const struct snd_soc_dapm_route cs35l45_dapm_routes[] = {
367 /* Feedback */
368 { "VMON", NULL, "VMON_SRC" },
369 { "IMON", NULL, "IMON_SRC" },
370 { "VDD_BATTMON", NULL, "VDD_BATTMON_SRC" },
371 { "VDD_BSTMON", NULL, "VDD_BSTMON_SRC" },
372
373 { "Capture", NULL, "ASP_TX1"},
374 { "Capture", NULL, "ASP_TX2"},
375 { "Capture", NULL, "ASP_TX3"},
376 { "Capture", NULL, "ASP_TX4"},
377 { "Capture", NULL, "ASP_TX5"},
378 { "ASP_TX1", NULL, "ASP_TX1 Source"},
379 { "ASP_TX2", NULL, "ASP_TX2 Source"},
380 { "ASP_TX3", NULL, "ASP_TX3 Source"},
381 { "ASP_TX4", NULL, "ASP_TX4 Source"},
382 { "ASP_TX5", NULL, "ASP_TX5 Source"},
383
384 { "ASP_TX1", NULL, "ASP_EN" },
385 { "ASP_TX2", NULL, "ASP_EN" },
386 { "ASP_TX3", NULL, "ASP_EN" },
387 { "ASP_TX4", NULL, "ASP_EN" },
388 { "ASP_TX1", NULL, "GLOBAL_EN" },
389 { "ASP_TX2", NULL, "GLOBAL_EN" },
390 { "ASP_TX3", NULL, "GLOBAL_EN" },
391 { "ASP_TX4", NULL, "GLOBAL_EN" },
392 { "ASP_TX5", NULL, "GLOBAL_EN" },
393
394 CS35L45_ASP_MUX_ROUTE("ASP_TX1"),
395 CS35L45_ASP_MUX_ROUTE("ASP_TX2"),
396 CS35L45_ASP_MUX_ROUTE("ASP_TX3"),
397 CS35L45_ASP_MUX_ROUTE("ASP_TX4"),
398 CS35L45_ASP_MUX_ROUTE("ASP_TX5"),
399
400 /* Playback */
401 { "ASP_RX1", NULL, "Playback" },
402 { "ASP_RX2", NULL, "Playback" },
403 { "ASP_RX1", NULL, "ASP_EN" },
404 { "ASP_RX2", NULL, "ASP_EN" },
405
406 { "AMP", NULL, "DACPCM1 Source"},
407 { "AMP", NULL, "GLOBAL_EN"},
408
74b14e28
VK		 409 CS35L45_DSP_MUX_ROUTE("DSP_RX1"),
410 CS35L45_DSP_MUX_ROUTE("DSP_RX2"),
411 CS35L45_DSP_MUX_ROUTE("DSP_RX3"),
412 CS35L45_DSP_MUX_ROUTE("DSP_RX4"),
413 CS35L45_DSP_MUX_ROUTE("DSP_RX5"),
414 CS35L45_DSP_MUX_ROUTE("DSP_RX6"),
415 CS35L45_DSP_MUX_ROUTE("DSP_RX7"),
416 CS35L45_DSP_MUX_ROUTE("DSP_RX8"),
417
418 {"DSP1", NULL, "DSP_RX1 Source"},
419 {"DSP1", NULL, "DSP_RX2 Source"},
420 {"DSP1", NULL, "DSP_RX3 Source"},
421 {"DSP1", NULL, "DSP_RX4 Source"},
422 {"DSP1", NULL, "DSP_RX5 Source"},
423 {"DSP1", NULL, "DSP_RX6 Source"},
424 {"DSP1", NULL, "DSP_RX7 Source"},
425 {"DSP1", NULL, "DSP_RX8 Source"},
426
427 {"DSP1 Preload", NULL, "DSP1 Preloader"},
428 {"DSP1", NULL, "DSP1 Preloader"},
429
0d463d01
JS		 430 CS35L45_DAC_MUX_ROUTE("DACPCM1"),
431
432 { "SPK", NULL, "AMP"},
433};
434
435static const DECLARE_TLV_DB_SCALE(cs35l45_dig_pcm_vol_tlv, -10225, 25, true);
436
437static const struct snd_kcontrol_new cs35l45_controls[] = {
438 /* Ignore bit 0: it is beyond the resolution of TLV_DB_SCALE */
439 SOC_SINGLE_S_TLV("Digital PCM Volume",
440 CS35L45_AMP_PCM_CONTROL,
441 CS35L45_AMP_VOL_PCM_SHIFT + 1,
442 -409, 48,
443 (CS35L45_AMP_VOL_PCM_WIDTH - 1) - 1,
444 0, cs35l45_dig_pcm_vol_tlv),
74b14e28
VK		 445 WM_ADSP2_PRELOAD_SWITCH("DSP1", 1),
446 WM_ADSP_FW_CONTROL("DSP1", 0),
0d463d01
JS		 447};
448
449static int cs35l45_set_pll(struct cs35l45_private *cs35l45, unsigned int freq)
450{
451 unsigned int val;
452 int freq_id;
453
454 freq_id = cs35l45_get_clk_freq_id(freq);
455 if (freq_id < 0) {
456 dev_err(cs35l45->dev, "Invalid freq: %u\n", freq);
457 return -EINVAL;
458 }
459
460 regmap_read(cs35l45->regmap, CS35L45_REFCLK_INPUT, &val);
461 val = (val & CS35L45_PLL_REFCLK_FREQ_MASK) >> CS35L45_PLL_REFCLK_FREQ_SHIFT;
462 if (val == freq_id)
463 return 0;
464
465 regmap_set_bits(cs35l45->regmap, CS35L45_REFCLK_INPUT, CS35L45_PLL_OPEN_LOOP_MASK);
466 regmap_update_bits(cs35l45->regmap, CS35L45_REFCLK_INPUT,
467 CS35L45_PLL_REFCLK_FREQ_MASK,
468 freq_id << CS35L45_PLL_REFCLK_FREQ_SHIFT);
469 regmap_clear_bits(cs35l45->regmap, CS35L45_REFCLK_INPUT, CS35L45_PLL_REFCLK_EN_MASK);
470 regmap_clear_bits(cs35l45->regmap, CS35L45_REFCLK_INPUT, CS35L45_PLL_OPEN_LOOP_MASK);
471 regmap_set_bits(cs35l45->regmap, CS35L45_REFCLK_INPUT, CS35L45_PLL_REFCLK_EN_MASK);
472
473 return 0;
474}
475
476static int cs35l45_asp_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
477{
478 struct cs35l45_private *cs35l45 = snd_soc_component_get_drvdata(codec_dai->component);
479 unsigned int asp_fmt, fsync_inv, bclk_inv;
480
481 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
482 case SND_SOC_DAIFMT_CBC_CFC:
483 break;
484 default:
485 dev_err(cs35l45->dev, "Invalid DAI clocking\n");
486 return -EINVAL;
487 }
488
489 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
490 case SND_SOC_DAIFMT_DSP_A:
491 asp_fmt = CS35l45_ASP_FMT_DSP_A;
492 break;
493 case SND_SOC_DAIFMT_I2S:
494 asp_fmt = CS35L45_ASP_FMT_I2S;
495 break;
496 default:
497 dev_err(cs35l45->dev, "Invalid DAI format\n");
498 return -EINVAL;
499 }
500
501 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
502 case SND_SOC_DAIFMT_NB_IF:
503 fsync_inv = 1;
504 bclk_inv = 0;
505 break;
506 case SND_SOC_DAIFMT_IB_NF:
507 fsync_inv = 0;
508 bclk_inv = 1;
509 break;
510 case SND_SOC_DAIFMT_IB_IF:
511 fsync_inv = 1;
512 bclk_inv = 1;
513 break;
514 case SND_SOC_DAIFMT_NB_NF:
515 fsync_inv = 0;
516 bclk_inv = 0;
517 break;
518 default:
519 dev_warn(cs35l45->dev, "Invalid DAI clock polarity\n");
520 return -EINVAL;
521 }
522
523 regmap_update_bits(cs35l45->regmap, CS35L45_ASP_CONTROL2,
524 CS35L45_ASP_FMT_MASK |
525 CS35L45_ASP_FSYNC_INV_MASK |
526 CS35L45_ASP_BCLK_INV_MASK,
527 (asp_fmt << CS35L45_ASP_FMT_SHIFT) |
528 (fsync_inv << CS35L45_ASP_FSYNC_INV_SHIFT) |
529 (bclk_inv << CS35L45_ASP_BCLK_INV_SHIFT));
530
531 return 0;
532}
533
534static int cs35l45_asp_hw_params(struct snd_pcm_substream *substream,
535 struct snd_pcm_hw_params *params,
536 struct snd_soc_dai *dai)
537{
538 struct cs35l45_private *cs35l45 = snd_soc_component_get_drvdata(dai->component);
539 unsigned int asp_width, asp_wl, global_fs, slot_multiple, asp_fmt;
540 int bclk;
541
542 switch (params_rate(params)) {
543 case 44100:
544 global_fs = CS35L45_44P100_KHZ;
545 break;
546 case 48000:
547 global_fs = CS35L45_48P0_KHZ;
548 break;
549 case 88200:
550 global_fs = CS35L45_88P200_KHZ;
551 break;
552 case 96000:
553 global_fs = CS35L45_96P0_KHZ;
554 break;
555 default:
556 dev_warn(cs35l45->dev, "Unsupported sample rate (%d)\n",
557 params_rate(params));
558 return -EINVAL;
559 }
560
561 regmap_update_bits(cs35l45->regmap, CS35L45_GLOBAL_SAMPLE_RATE,
562 CS35L45_GLOBAL_FS_MASK,
563 global_fs << CS35L45_GLOBAL_FS_SHIFT);
564
565 asp_wl = params_width(params);
566
567 if (cs35l45->slot_width)
568 asp_width = cs35l45->slot_width;
569 else
570 asp_width = params_width(params);
571
572 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
573 regmap_update_bits(cs35l45->regmap, CS35L45_ASP_CONTROL2,
574 CS35L45_ASP_WIDTH_RX_MASK,
575 asp_width << CS35L45_ASP_WIDTH_RX_SHIFT);
576
577 regmap_update_bits(cs35l45->regmap, CS35L45_ASP_DATA_CONTROL5,
578 CS35L45_ASP_WL_MASK,
579 asp_wl << CS35L45_ASP_WL_SHIFT);
580 } else {
581 regmap_update_bits(cs35l45->regmap, CS35L45_ASP_CONTROL2,
582 CS35L45_ASP_WIDTH_TX_MASK,
583 asp_width << CS35L45_ASP_WIDTH_TX_SHIFT);
584
585 regmap_update_bits(cs35l45->regmap, CS35L45_ASP_DATA_CONTROL1,
586 CS35L45_ASP_WL_MASK,
587 asp_wl << CS35L45_ASP_WL_SHIFT);
588 }
589
590 if (cs35l45->sysclk_set)
591 return 0;
592
593 /* I2S always has an even number of channels */
594 regmap_read(cs35l45->regmap, CS35L45_ASP_CONTROL2, &asp_fmt);
595 asp_fmt = (asp_fmt & CS35L45_ASP_FMT_MASK) >> CS35L45_ASP_FMT_SHIFT;
596 if (asp_fmt == CS35L45_ASP_FMT_I2S)
597 slot_multiple = 2;
598 else
599 slot_multiple = 1;
600
601 bclk = snd_soc_tdm_params_to_bclk(params, asp_width,
602 cs35l45->slot_count, slot_multiple);
603
604 return cs35l45_set_pll(cs35l45, bclk);
605}
606
607static int cs35l45_asp_set_tdm_slot(struct snd_soc_dai *dai,
608 unsigned int tx_mask, unsigned int rx_mask,
609 int slots, int slot_width)
610{
611 struct cs35l45_private *cs35l45 = snd_soc_component_get_drvdata(dai->component);
612
613 if (slot_width && ((slot_width < 16) || (slot_width > 128)))
614 return -EINVAL;
615
616 cs35l45->slot_width = slot_width;
617 cs35l45->slot_count = slots;
618
619 return 0;
620}
621
622static int cs35l45_asp_set_sysclk(struct snd_soc_dai *dai,
623 int clk_id, unsigned int freq, int dir)
624{
625 struct cs35l45_private *cs35l45 = snd_soc_component_get_drvdata(dai->component);
626 int ret;
627
628 if (clk_id != 0) {
629 dev_err(cs35l45->dev, "Invalid clk_id %d\n", clk_id);
630 return -EINVAL;
631 }
632
633 cs35l45->sysclk_set = false;
634 if (freq == 0)
635 return 0;
636
637 ret = cs35l45_set_pll(cs35l45, freq);
638 if (ret < 0)
639 return -EINVAL;
640
641 cs35l45->sysclk_set = true;
642
643 return 0;
644}
645
646static int cs35l45_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
647{
648 struct cs35l45_private *cs35l45 = snd_soc_component_get_drvdata(dai->component);
649 unsigned int global_fs, val, hpf_tune;
650
651 if (mute)
652 return 0;
653
654 regmap_read(cs35l45->regmap, CS35L45_GLOBAL_SAMPLE_RATE, &global_fs);
655 global_fs = (global_fs & CS35L45_GLOBAL_FS_MASK) >> CS35L45_GLOBAL_FS_SHIFT;
656 switch (global_fs) {
657 case CS35L45_44P100_KHZ:
658 hpf_tune = CS35L45_HPF_44P1;
659 break;
660 case CS35L45_88P200_KHZ:
661 hpf_tune = CS35L45_HPF_88P2;
662 break;
663 default:
664 hpf_tune = CS35l45_HPF_DEFAULT;
665 break;
666 }
667
668 regmap_read(cs35l45->regmap, CS35L45_AMP_PCM_HPF_TST, &val);
669 if (val != hpf_tune) {
670 struct reg_sequence hpf_override_seq[] = {
671 { 0x00000040, 0x00000055 },
672 { 0x00000040, 0x000000AA },
673 { 0x00000044, 0x00000055 },
674 { 0x00000044, 0x000000AA },
675 { CS35L45_AMP_PCM_HPF_TST, hpf_tune },
676 { 0x00000040, 0x00000000 },
677 { 0x00000044, 0x00000000 },
678 };
679 regmap_multi_reg_write(cs35l45->regmap, hpf_override_seq,
680 ARRAY_SIZE(hpf_override_seq));
681 }
682
683 return 0;
684}
685
686static const struct snd_soc_dai_ops cs35l45_asp_dai_ops = {
687 .set_fmt = cs35l45_asp_set_fmt,
688 .hw_params = cs35l45_asp_hw_params,
689 .set_tdm_slot = cs35l45_asp_set_tdm_slot,
690 .set_sysclk = cs35l45_asp_set_sysclk,
691 .mute_stream = cs35l45_mute_stream,
692};
693
694static struct snd_soc_dai_driver cs35l45_dai[] = {
695 {
696 .name = "cs35l45",
697 .playback = {
698 .stream_name = "Playback",
699 .channels_min = 1,
700 .channels_max = 2,
701 .rates = CS35L45_RATES,
702 .formats = CS35L45_FORMATS,
703 },
704 .capture = {
705 .stream_name = "Capture",
706 .channels_min = 1,
707 .channels_max = 5,
708 .rates = CS35L45_RATES,
709 .formats = CS35L45_FORMATS,
710 },
711 .symmetric_rate = true,
712 .symmetric_sample_bits = true,
713 .ops = &cs35l45_asp_dai_ops,
714 },
715};
716
74b14e28
VK		 717static int cs35l45_component_probe(struct snd_soc_component *component)
718{
719 struct cs35l45_private *cs35l45 = snd_soc_component_get_drvdata(component);
720
721 return wm_adsp2_component_probe(&cs35l45->dsp, component);
722}
723
724static void cs35l45_component_remove(struct snd_soc_component *component)
725{
726 struct cs35l45_private *cs35l45 = snd_soc_component_get_drvdata(component);
727
728 wm_adsp2_component_remove(&cs35l45->dsp, component);
729}
730
0d463d01 731static const struct snd_soc_component_driver cs35l45_component = {
74b14e28
VK		 732 .probe = cs35l45_component_probe,
733 .remove = cs35l45_component_remove,
734
0d463d01
JS		 735 .dapm_widgets = cs35l45_dapm_widgets,
736 .num_dapm_widgets = ARRAY_SIZE(cs35l45_dapm_widgets),
737
738 .dapm_routes = cs35l45_dapm_routes,
739 .num_dapm_routes = ARRAY_SIZE(cs35l45_dapm_routes),
740
741 .controls = cs35l45_controls,
742 .num_controls = ARRAY_SIZE(cs35l45_controls),
743
744 .name = "cs35l45",
d919630f
CK		 745
746 .endianness = 1,
0d463d01
JS		 747};
748
6c07be8f
VK		 749static void cs35l45_setup_hibernate(struct cs35l45_private *cs35l45)
750{
751 unsigned int wksrc;
752
753 if (cs35l45->bus_type == CONTROL_BUS_I2C)
754 wksrc = CS35L45_WKSRC_I2C;
755 else
756 wksrc = CS35L45_WKSRC_SPI;
757
758 regmap_update_bits(cs35l45->regmap, CS35L45_WAKESRC_CTL,
759 CS35L45_WKSRC_EN_MASK,
760 wksrc << CS35L45_WKSRC_EN_SHIFT);
761
762 regmap_set_bits(cs35l45->regmap, CS35L45_WAKESRC_CTL,
763 CS35L45_UPDT_WKCTL_MASK);
764
765 regmap_update_bits(cs35l45->regmap, CS35L45_WKI2C_CTL,
766 CS35L45_WKI2C_ADDR_MASK, cs35l45->i2c_addr);
767
768 regmap_set_bits(cs35l45->regmap, CS35L45_WKI2C_CTL,
769 CS35L45_UPDT_WKI2C_MASK);
770}
771
772static int cs35l45_enter_hibernate(struct cs35l45_private *cs35l45)
773{
774 dev_dbg(cs35l45->dev, "Enter hibernate\n");
775
776 cs35l45_setup_hibernate(cs35l45);
777
778 // Don't wait for ACK since bus activity would wake the device
779 regmap_write(cs35l45->regmap, CS35L45_DSP_VIRT1_MBOX_1, CSPL_MBOX_CMD_HIBERNATE);
780
781 return 0;
782}
783
784static int cs35l45_exit_hibernate(struct cs35l45_private *cs35l45)
785{
786 const int wake_retries = 20;
787 const int sleep_retries = 5;
788 int ret, i, j;
789
790 for (i = 0; i < sleep_retries; i++) {
791 dev_dbg(cs35l45->dev, "Exit hibernate\n");
792
793 for (j = 0; j < wake_retries; j++) {
794 ret = cs35l45_set_cspl_mbox_cmd(cs35l45, cs35l45->regmap,
795 CSPL_MBOX_CMD_OUT_OF_HIBERNATE);
796 if (!ret) {
797 dev_dbg(cs35l45->dev, "Wake success at cycle: %d\n", j);
798 return 0;
799 }
800 usleep_range(100, 200);
801 }
802
803 dev_err(cs35l45->dev, "Wake failed, re-enter hibernate: %d\n", ret);
804
805 cs35l45_setup_hibernate(cs35l45);
806 }
807
808 dev_err(cs35l45->dev, "Timed out waking device\n");
809
810 return -ETIMEDOUT;
811}
812
0d463d01
JS		 813static int __maybe_unused cs35l45_runtime_suspend(struct device *dev)
814{
815 struct cs35l45_private *cs35l45 = dev_get_drvdata(dev);
816
6c07be8f
VK		 817 if (!cs35l45->dsp.preloaded || !cs35l45->dsp.cs_dsp.running)
818 return 0;
819
820 cs35l45_enter_hibernate(cs35l45);
821
0d463d01 822 regcache_cache_only(cs35l45->regmap, true);
6c07be8f 823 regcache_mark_dirty(cs35l45->regmap);
0d463d01
JS		 824
825 dev_dbg(cs35l45->dev, "Runtime suspended\n");
826
827 return 0;
828}
829
830static int __maybe_unused cs35l45_runtime_resume(struct device *dev)
831{
832 struct cs35l45_private *cs35l45 = dev_get_drvdata(dev);
833 int ret;
834
6c07be8f
VK		 835 if (!cs35l45->dsp.preloaded || !cs35l45->dsp.cs_dsp.running)
836 return 0;
837
0d463d01
JS		 838 dev_dbg(cs35l45->dev, "Runtime resume\n");
839
840 regcache_cache_only(cs35l45->regmap, false);
6c07be8f
VK		 841
842 ret = cs35l45_exit_hibernate(cs35l45);
843 if (ret)
844 return ret;
845
0d463d01
JS		 846 ret = regcache_sync(cs35l45->regmap);
847 if (ret != 0)
848 dev_warn(cs35l45->dev, "regcache_sync failed: %d\n", ret);
849
850 /* Clear global error status */
851 regmap_clear_bits(cs35l45->regmap, CS35L45_ERROR_RELEASE, CS35L45_GLOBAL_ERR_RLS_MASK);
852 regmap_set_bits(cs35l45->regmap, CS35L45_ERROR_RELEASE, CS35L45_GLOBAL_ERR_RLS_MASK);
853 regmap_clear_bits(cs35l45->regmap, CS35L45_ERROR_RELEASE, CS35L45_GLOBAL_ERR_RLS_MASK);
854 return ret;
855}
856
857static int cs35l45_apply_property_config(struct cs35l45_private *cs35l45)
858{
fa8c052b
VK		 859 struct device_node *node = cs35l45->dev->of_node;
860 unsigned int gpio_regs[] = {CS35L45_GPIO1_CTRL1, CS35L45_GPIO2_CTRL1,
861 CS35L45_GPIO3_CTRL1};
862 unsigned int pad_regs[] = {CS35L45_SYNC_GPIO1,
863 CS35L45_INTB_GPIO2_MCLK_REF, CS35L45_GPIO3};
864 struct device_node *child;
0d463d01 865 unsigned int val;
fa8c052b
VK		 866 char of_name[32];
867 int ret, i;
868
869 if (!node)
870 return 0;
871
872 for (i = 0; i < CS35L45_NUM_GPIOS; i++) {
873 sprintf(of_name, "cirrus,gpio-ctrl%d", i + 1);
874 child = of_get_child_by_name(node, of_name);
875 if (!child)
876 continue;
877
878 ret = of_property_read_u32(child, "gpio-dir", &val);
879 if (!ret)
880 regmap_update_bits(cs35l45->regmap, gpio_regs[i],
881 CS35L45_GPIO_DIR_MASK,
882 val << CS35L45_GPIO_DIR_SHIFT);
883
884 ret = of_property_read_u32(child, "gpio-lvl", &val);
885 if (!ret)
886 regmap_update_bits(cs35l45->regmap, gpio_regs[i],
887 CS35L45_GPIO_LVL_MASK,
888 val << CS35L45_GPIO_LVL_SHIFT);
889
890 ret = of_property_read_u32(child, "gpio-op-cfg", &val);
891 if (!ret)
892 regmap_update_bits(cs35l45->regmap, gpio_regs[i],
893 CS35L45_GPIO_OP_CFG_MASK,
894 val << CS35L45_GPIO_OP_CFG_SHIFT);
895
896 ret = of_property_read_u32(child, "gpio-pol", &val);
897 if (!ret)
898 regmap_update_bits(cs35l45->regmap, gpio_regs[i],
899 CS35L45_GPIO_POL_MASK,
900 val << CS35L45_GPIO_POL_SHIFT);
901
902 ret = of_property_read_u32(child, "gpio-ctrl", &val);
903 if (!ret)
904 regmap_update_bits(cs35l45->regmap, pad_regs[i],
905 CS35L45_GPIO_CTRL_MASK,
906 val << CS35L45_GPIO_CTRL_SHIFT);
907
908 ret = of_property_read_u32(child, "gpio-invert", &val);
6085f9e6 909 if (!ret) {
fa8c052b
VK		 910 regmap_update_bits(cs35l45->regmap, pad_regs[i],
911 CS35L45_GPIO_INVERT_MASK,
912 val << CS35L45_GPIO_INVERT_SHIFT);
6085f9e6
VK		 913 if (i == 1)
914 cs35l45->irq_invert = val;
915 }
fa8c052b
VK		 916
917 of_node_put(child);
918 }
0d463d01
JS		 919
920 if (device_property_read_u32(cs35l45->dev,
921 "cirrus,asp-sdout-hiz-ctrl", &val) == 0) {
922 regmap_update_bits(cs35l45->regmap, CS35L45_ASP_CONTROL3,
923 CS35L45_ASP_DOUT_HIZ_CTRL_MASK,
924 val << CS35L45_ASP_DOUT_HIZ_CTRL_SHIFT);
925 }
926
927 return 0;
928}
929
74b14e28
VK		 930static int cs35l45_dsp_virt2_mbox3_irq_handle(struct cs35l45_private *cs35l45,
931 const unsigned int cmd,
932 unsigned int data)
933{
934 static char *speak_status = "Unknown";
935
936 switch (cmd) {
937 case EVENT_SPEAKER_STATUS:
938 switch (data) {
939 case 1:
940 speak_status = "All Clear";
941 break;
942 case 2:
943 speak_status = "Open Circuit";
944 break;
945 case 4:
946 speak_status = "Short Circuit";
947 break;
948 }
949
950 dev_info(cs35l45->dev, "MBOX event (SPEAKER_STATUS): %s\n",
951 speak_status);
952 break;
953 case EVENT_BOOT_DONE:
954 dev_dbg(cs35l45->dev, "MBOX event (BOOT_DONE)\n");
955 break;
956 default:
957 dev_err(cs35l45->dev, "MBOX event not supported %u\n", cmd);
958 return -EINVAL;
959 }
960
961 return 0;
962}
963
964static irqreturn_t cs35l45_dsp_virt2_mbox_cb(int irq, void *data)
965{
966 struct cs35l45_private *cs35l45 = data;
967 unsigned int mbox_val;
968 int ret = 0;
969
970 ret = regmap_read(cs35l45->regmap, CS35L45_DSP_VIRT2_MBOX_3, &mbox_val);
971 if (!ret && mbox_val)
972 ret = cs35l45_dsp_virt2_mbox3_irq_handle(cs35l45, mbox_val & CS35L45_MBOX3_CMD_MASK,
973 (mbox_val & CS35L45_MBOX3_DATA_MASK) >> CS35L45_MBOX3_DATA_SHIFT);
974
975 /* Handle DSP trace log IRQ */
976 ret = regmap_read(cs35l45->regmap, CS35L45_DSP_VIRT2_MBOX_4, &mbox_val);
977 if (!ret && mbox_val != 0) {
978 dev_err(cs35l45->dev, "Spurious DSP MBOX4 IRQ\n");
979 }
980
981 return IRQ_RETVAL(ret);
982}
983
6085f9e6
VK		 984static irqreturn_t cs35l45_pll_unlock(int irq, void *data)
985{
986 struct cs35l45_private *cs35l45 = data;
987
988 dev_dbg(cs35l45->dev, "PLL unlock detected!");
989
990 return IRQ_HANDLED;
991}
992
993static irqreturn_t cs35l45_pll_lock(int irq, void *data)
994{
995 struct cs35l45_private *cs35l45 = data;
996
997 dev_dbg(cs35l45->dev, "PLL lock detected!");
998
999 return IRQ_HANDLED;
1000}
1001
1002static irqreturn_t cs35l45_spk_safe_err(int irq, void *data);
1003
1004static const struct cs35l45_irq cs35l45_irqs[] = {
1005 CS35L45_IRQ(AMP_SHORT_ERR, "Amplifier short error", cs35l45_spk_safe_err),
1006 CS35L45_IRQ(UVLO_VDDBATT_ERR, "VDDBATT undervoltage error", cs35l45_spk_safe_err),
1007 CS35L45_IRQ(BST_SHORT_ERR, "Boost inductor error", cs35l45_spk_safe_err),
1008 CS35L45_IRQ(BST_UVP_ERR, "Boost undervoltage error", cs35l45_spk_safe_err),
1009 CS35L45_IRQ(TEMP_ERR, "Overtemperature error", cs35l45_spk_safe_err),
1010 CS35L45_IRQ(AMP_CAL_ERR, "Amplifier calibration error", cs35l45_spk_safe_err),
1011 CS35L45_IRQ(UVLO_VDDLV_ERR, "LV threshold detector error", cs35l45_spk_safe_err),
1012 CS35L45_IRQ(GLOBAL_ERROR, "Global error", cs35l45_spk_safe_err),
1013 CS35L45_IRQ(DSP_WDT_EXPIRE, "DSP Watchdog Timer", cs35l45_spk_safe_err),
1014 CS35L45_IRQ(PLL_UNLOCK_FLAG_RISE, "PLL unlock", cs35l45_pll_unlock),
1015 CS35L45_IRQ(PLL_LOCK_FLAG, "PLL lock", cs35l45_pll_lock),
74b14e28 1016 CS35L45_IRQ(DSP_VIRT2_MBOX, "DSP virtual MBOX 2 write flag", cs35l45_dsp_virt2_mbox_cb),
6085f9e6
VK		 1017};
1018
1019static irqreturn_t cs35l45_spk_safe_err(int irq, void *data)
1020{
1021 struct cs35l45_private *cs35l45 = data;
1022 int i;
1023
1024 i = irq - regmap_irq_get_virq(cs35l45->irq_data, 0);
1025
1026 dev_err(cs35l45->dev, "%s condition detected!\n", cs35l45_irqs[i].name);
1027
1028 return IRQ_HANDLED;
1029}
1030
1031static const struct regmap_irq cs35l45_reg_irqs[] = {
1032 CS35L45_REG_IRQ(IRQ1_EINT_1, AMP_SHORT_ERR),
1033 CS35L45_REG_IRQ(IRQ1_EINT_1, UVLO_VDDBATT_ERR),
1034 CS35L45_REG_IRQ(IRQ1_EINT_1, BST_SHORT_ERR),
1035 CS35L45_REG_IRQ(IRQ1_EINT_1, BST_UVP_ERR),
1036 CS35L45_REG_IRQ(IRQ1_EINT_1, TEMP_ERR),
1037 CS35L45_REG_IRQ(IRQ1_EINT_3, AMP_CAL_ERR),
1038 CS35L45_REG_IRQ(IRQ1_EINT_18, UVLO_VDDLV_ERR),
1039 CS35L45_REG_IRQ(IRQ1_EINT_18, GLOBAL_ERROR),
1040 CS35L45_REG_IRQ(IRQ1_EINT_2, DSP_WDT_EXPIRE),
1041 CS35L45_REG_IRQ(IRQ1_EINT_3, PLL_UNLOCK_FLAG_RISE),
1042 CS35L45_REG_IRQ(IRQ1_EINT_3, PLL_LOCK_FLAG),
74b14e28 1043 CS35L45_REG_IRQ(IRQ1_EINT_2, DSP_VIRT2_MBOX),
6085f9e6
VK		 1044};
1045
1046static const struct regmap_irq_chip cs35l45_regmap_irq_chip = {
1047 .name = "cs35l45 IRQ1 Controller",
1048 .main_status = CS35L45_IRQ1_STATUS,
1049 .status_base = CS35L45_IRQ1_EINT_1,
1050 .mask_base = CS35L45_IRQ1_MASK_1,
1051 .ack_base = CS35L45_IRQ1_EINT_1,
1052 .num_regs = 18,
1053 .irqs = cs35l45_reg_irqs,
1054 .num_irqs = ARRAY_SIZE(cs35l45_reg_irqs),
1055 .runtime_pm = true,
1056};
1057
0d463d01
JS		 1058static int cs35l45_initialize(struct cs35l45_private *cs35l45)
1059{
1060 struct device *dev = cs35l45->dev;
1061 unsigned int dev_id[5];
1062 unsigned int sts;
1063 int ret;
1064
1065 ret = regmap_read_poll_timeout(cs35l45->regmap, CS35L45_IRQ1_EINT_4, sts,
1066 (sts & CS35L45_OTP_BOOT_DONE_STS_MASK),
1067 1000, 5000);
1068 if (ret < 0) {
1069 dev_err(cs35l45->dev, "Timeout waiting for OTP boot\n");
1070 return ret;
1071 }
1072
1073 ret = regmap_bulk_read(cs35l45->regmap, CS35L45_DEVID, dev_id, ARRAY_SIZE(dev_id));
1074 if (ret) {
1075 dev_err(cs35l45->dev, "Get Device ID failed: %d\n", ret);
1076 return ret;
1077 }
1078
1079 switch (dev_id[0]) {
1080 case 0x35A450:
1081 break;
1082 default:
1083 dev_err(cs35l45->dev, "Bad DEVID 0x%x\n", dev_id[0]);
1084 return -ENODEV;
1085 }
1086
1087 dev_info(cs35l45->dev, "Cirrus Logic CS35L45: REVID %02X OTPID %02X\n",
1088 dev_id[1], dev_id[4]);
1089
1090 regmap_write(cs35l45->regmap, CS35L45_IRQ1_EINT_4,
1091 CS35L45_OTP_BOOT_DONE_STS_MASK | CS35L45_OTP_BUSY_MASK);
1092
1093 ret = cs35l45_apply_patch(cs35l45);
1094 if (ret < 0) {
1095 dev_err(dev, "Failed to apply init patch %d\n", ret);
1096 return ret;
1097 }
1098
0d463d01
JS		 1099 ret = cs35l45_apply_property_config(cs35l45);
1100 if (ret < 0)
1101 return ret;
1102
0d463d01
JS		 1103 return 0;
1104}
1105
74b14e28
VK		 1106static const struct reg_sequence cs35l45_fs_errata_patch[] = {
1107 {0x02B80080, 0x00000001},
1108 {0x02B80088, 0x00000001},
1109 {0x02B80090, 0x00000001},
1110 {0x02B80098, 0x00000001},
1111 {0x02B800A0, 0x00000001},
1112 {0x02B800A8, 0x00000001},
1113 {0x02B800B0, 0x00000001},
1114 {0x02B800B8, 0x00000001},
1115 {0x02B80280, 0x00000001},
1116 {0x02B80288, 0x00000001},
1117 {0x02B80290, 0x00000001},
1118 {0x02B80298, 0x00000001},
1119 {0x02B802A0, 0x00000001},
1120 {0x02B802A8, 0x00000001},
1121 {0x02B802B0, 0x00000001},
1122 {0x02B802B8, 0x00000001},
1123};
1124
1125static const struct cs_dsp_region cs35l45_dsp1_regions[] = {
1126 { .type = WMFW_HALO_PM_PACKED, .base = CS35L45_DSP1_PMEM_0 },
1127 { .type = WMFW_HALO_XM_PACKED, .base = CS35L45_DSP1_XMEM_PACK_0 },
1128 { .type = WMFW_HALO_YM_PACKED, .base = CS35L45_DSP1_YMEM_PACK_0 },
1129 {. type = WMFW_ADSP2_XM, .base = CS35L45_DSP1_XMEM_UNPACK24_0},
1130 {. type = WMFW_ADSP2_YM, .base = CS35L45_DSP1_YMEM_UNPACK24_0},
1131};
1132
1133static int cs35l45_dsp_init(struct cs35l45_private *cs35l45)
1134{
1135 struct wm_adsp *dsp = &cs35l45->dsp;
1136 int ret;
1137
1138 dsp->part = "cs35l45";
1139 dsp->fw = 9; /* 9 is WM_ADSP_FW_SPK_PROT in wm_adsp.c */
1140 dsp->toggle_preload = true;
1141 dsp->cs_dsp.num = 1;
1142 dsp->cs_dsp.type = WMFW_HALO;
1143 dsp->cs_dsp.rev = 0;
1144 dsp->cs_dsp.dev = cs35l45->dev;
1145 dsp->cs_dsp.regmap = cs35l45->regmap;
1146 dsp->cs_dsp.base = CS35L45_DSP1_CLOCK_FREQ;
1147 dsp->cs_dsp.base_sysinfo = CS35L45_DSP1_SYS_ID;
1148 dsp->cs_dsp.mem = cs35l45_dsp1_regions;
1149 dsp->cs_dsp.num_mems = ARRAY_SIZE(cs35l45_dsp1_regions);
1150 dsp->cs_dsp.lock_regions = 0xFFFFFFFF;
1151
1152 ret = wm_halo_init(dsp);
1153
1154 regmap_multi_reg_write(cs35l45->regmap, cs35l45_fs_errata_patch,
1155 ARRAY_SIZE(cs35l45_fs_errata_patch));
1156
1157 return ret;
1158}
1159
0d463d01
JS		 1160int cs35l45_probe(struct cs35l45_private *cs35l45)
1161{
1162 struct device *dev = cs35l45->dev;
6085f9e6
VK		 1163 unsigned long irq_pol = IRQF_ONESHOT | IRQF_SHARED;
1164 int ret, i, irq;
0d463d01
JS		 1165
1166 cs35l45->vdd_batt = devm_regulator_get(dev, "vdd-batt");
1167 if (IS_ERR(cs35l45->vdd_batt))
1168 return dev_err_probe(dev, PTR_ERR(cs35l45->vdd_batt),
1169 "Failed to request vdd-batt\n");
1170
1171 cs35l45->vdd_a = devm_regulator_get(dev, "vdd-a");
1172 if (IS_ERR(cs35l45->vdd_a))
1173 return dev_err_probe(dev, PTR_ERR(cs35l45->vdd_a),
1174 "Failed to request vdd-a\n");
1175
1176 /* VDD_BATT must always be enabled before other supplies */
1177 ret = regulator_enable(cs35l45->vdd_batt);
1178 if (ret < 0)
1179 return dev_err_probe(dev, ret, "Failed to enable vdd-batt\n");
1180
1181 ret = regulator_enable(cs35l45->vdd_a);
1182 if (ret < 0)
1183 return dev_err_probe(dev, ret, "Failed to enable vdd-a\n");
1184
1185 /* If reset is shared only one instance can claim it */
1186 cs35l45->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
1187 if (IS_ERR(cs35l45->reset_gpio)) {
1188 ret = PTR_ERR(cs35l45->reset_gpio);
1189 cs35l45->reset_gpio = NULL;
1190 if (ret == -EBUSY) {
1191 dev_dbg(dev, "Reset line busy, assuming shared reset\n");
1192 } else {
1193 dev_err_probe(dev, ret, "Failed to get reset GPIO\n");
1194 goto err;
1195 }
1196 }
1197
1198 if (cs35l45->reset_gpio) {
1199 usleep_range(CS35L45_RESET_HOLD_US, CS35L45_RESET_HOLD_US + 100);
1200 gpiod_set_value_cansleep(cs35l45->reset_gpio, 1);
1201 }
1202
1203 usleep_range(CS35L45_RESET_US, CS35L45_RESET_US + 100);
1204
1205 ret = cs35l45_initialize(cs35l45);
1206 if (ret < 0)
1207 goto err_reset;
1208
74b14e28
VK		 1209 ret = cs35l45_dsp_init(cs35l45);
1210 if (ret < 0)
1211 goto err_reset;
1212
1213 pm_runtime_set_autosuspend_delay(cs35l45->dev, 3000);
1214 pm_runtime_use_autosuspend(cs35l45->dev);
1215 pm_runtime_mark_last_busy(cs35l45->dev);
1216 pm_runtime_set_active(cs35l45->dev);
1217 pm_runtime_get_noresume(cs35l45->dev);
1218 pm_runtime_enable(cs35l45->dev);
1219
6085f9e6
VK		 1220 if (cs35l45->irq) {
1221 if (cs35l45->irq_invert)
1222 irq_pol |= IRQF_TRIGGER_HIGH;
1223 else
1224 irq_pol |= IRQF_TRIGGER_LOW;
1225
1226 ret = devm_regmap_add_irq_chip(dev, cs35l45->regmap, cs35l45->irq, irq_pol, 0,
1227 &cs35l45_regmap_irq_chip, &cs35l45->irq_data);
1228 if (ret) {
1229 dev_err(dev, "Failed to register IRQ chip: %d\n", ret);
74b14e28 1230 goto err_dsp;
6085f9e6
VK		 1231 }
1232
1233 for (i = 0; i < ARRAY_SIZE(cs35l45_irqs); i++) {
1234 irq = regmap_irq_get_virq(cs35l45->irq_data, cs35l45_irqs[i].irq);
1235 if (irq < 0) {
1236 dev_err(dev, "Failed to get %s\n", cs35l45_irqs[i].name);
1237 ret = irq;
74b14e28 1238 goto err_dsp;
6085f9e6
VK		 1239 }
1240
1241 ret = devm_request_threaded_irq(dev, irq, NULL, cs35l45_irqs[i].handler,
1242 irq_pol, cs35l45_irqs[i].name, cs35l45);
1243 if (ret) {
1244 dev_err(dev, "Failed to request IRQ %s: %d\n",
1245 cs35l45_irqs[i].name, ret);
74b14e28 1246 goto err_dsp;
6085f9e6
VK		 1247 }
1248 }
1249 }
1250
0d463d01
JS		 1251 ret = devm_snd_soc_register_component(dev, &cs35l45_component,
1252 cs35l45_dai,
1253 ARRAY_SIZE(cs35l45_dai));
1254 if (ret < 0)
74b14e28
VK		 1255 goto err_dsp;
1256
1257 pm_runtime_put_autosuspend(cs35l45->dev);
0d463d01
JS		 1258
1259 return 0;
1260
74b14e28
VK		 1261err_dsp:
1262 pm_runtime_disable(cs35l45->dev);
1263 pm_runtime_put_noidle(cs35l45->dev);
1264 wm_adsp2_remove(&cs35l45->dsp);
1265
0d463d01
JS		 1266err_reset:
1267 gpiod_set_value_cansleep(cs35l45->reset_gpio, 0);
1268err:
1269 regulator_disable(cs35l45->vdd_a);
1270 regulator_disable(cs35l45->vdd_batt);
1271
1272 return ret;
1273}
31c90dd5 1274EXPORT_SYMBOL_NS_GPL(cs35l45_probe, SND_SOC_CS35L45);
0d463d01 1275
84965cc6 1276void cs35l45_remove(struct cs35l45_private *cs35l45)
0d463d01 1277{
74b14e28 1278 pm_runtime_get_sync(cs35l45->dev);
0d463d01 1279 pm_runtime_disable(cs35l45->dev);
74b14e28 1280 wm_adsp2_remove(&cs35l45->dsp);
0d463d01
JS		 1281
1282 gpiod_set_value_cansleep(cs35l45->reset_gpio, 0);
74b14e28
VK		 1283
1284 pm_runtime_put_noidle(cs35l45->dev);
0d463d01
JS		 1285 regulator_disable(cs35l45->vdd_a);
1286 /* VDD_BATT must be the last to power-off */
1287 regulator_disable(cs35l45->vdd_batt);
0d463d01 1288}
31c90dd5 1289EXPORT_SYMBOL_NS_GPL(cs35l45_remove, SND_SOC_CS35L45);
0d463d01
JS		 1290
1291const struct dev_pm_ops cs35l45_pm_ops = {
1292 SET_RUNTIME_PM_OPS(cs35l45_runtime_suspend, cs35l45_runtime_resume, NULL)
1293};
31c90dd5 1294EXPORT_SYMBOL_NS_GPL(cs35l45_pm_ops, SND_SOC_CS35L45);
0d463d01
JS		 1295
1296MODULE_DESCRIPTION("ASoC CS35L45 driver");
1297MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>");
1298MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>");
1299MODULE_LICENSE("Dual BSD/GPL");
Linux 6.x block layer and io_uring tree(s)