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ASoC: cros_ec_codec: switch to library API for SHA-256
[linux-2.6-block.git] / sound / soc / codecs / cros_ec_codec.c
CommitLineData
b291f42a
CYC		 1// SPDX-License-Identifier: GPL-2.0
2/*
727f1c71
TBS		 3 * Copyright 2019 Google, Inc.
4 *
5 * ChromeOS Embedded Controller codec driver.
b291f42a
CYC		 6 *
7 * This driver uses the cros-ec interface to communicate with the ChromeOS
8 * EC for audio function.
9 */
10
b6bc07d4 11#include <crypto/sha.h>
877167ef 12#include <linux/acpi.h>
b291f42a
CYC		 13#include <linux/delay.h>
14#include <linux/device.h>
b6bc07d4
TBS		 15#include <linux/io.h>
16#include <linux/jiffies.h>
b291f42a 17#include <linux/kernel.h>
b291f42a 18#include <linux/module.h>
b6bc07d4
TBS		 19#include <linux/of.h>
20#include <linux/of_address.h>
840d9f13
EBS		 21#include <linux/platform_data/cros_ec_commands.h>
22#include <linux/platform_data/cros_ec_proto.h>
b291f42a
CYC		 23#include <linux/platform_device.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/soc.h>
27#include <sound/tlv.h>
28
727f1c71 29struct cros_ec_codec_priv {
b291f42a
CYC		 30 struct device *dev;
31 struct cros_ec_device *ec_device;
b6bc07d4
TBS		 32
33 /* common */
34 uint32_t ec_capabilities;
35
36 uint64_t ec_shm_addr;
37 uint32_t ec_shm_len;
38
39 uint64_t ap_shm_phys_addr;
40 uint32_t ap_shm_len;
41 uint64_t ap_shm_addr;
42 uint64_t ap_shm_last_alloc;
43
44 /* DMIC */
45 atomic_t dmic_probed;
46
99b4f439
YHH		 47 /* I2S_RX */
48 uint32_t i2s_rx_bclk_ratio;
49
b6bc07d4
TBS		 50 /* WoV */
51 bool wov_enabled;
52 uint8_t *wov_audio_shm_p;
53 uint32_t wov_audio_shm_len;
54 uint8_t wov_audio_shm_type;
55 uint8_t *wov_lang_shm_p;
56 uint32_t wov_lang_shm_len;
57 uint8_t wov_lang_shm_type;
58
59 struct mutex wov_dma_lock;
60 uint8_t wov_buf[64000];
61 uint32_t wov_rp, wov_wp;
62 size_t wov_dma_offset;
63 bool wov_burst_read;
64 struct snd_pcm_substream *wov_substream;
65 struct delayed_work wov_copy_work;
66 struct notifier_block wov_notifier;
b291f42a
CYC		 67};
68
b6bc07d4
TBS		 69static int ec_codec_capable(struct cros_ec_codec_priv *priv, uint8_t cap)
70{
71 return priv->ec_capabilities & BIT(cap);
72}
73
727f1c71
TBS		 74static int send_ec_host_command(struct cros_ec_device *ec_dev, uint32_t cmd,
75 uint8_t *out, size_t outsize,
76 uint8_t *in, size_t insize)
b291f42a 77{
b291f42a 78 int ret;
727f1c71
TBS		 79 struct cros_ec_command *msg;
80
81 msg = kmalloc(sizeof(*msg) + max(outsize, insize), GFP_KERNEL);
82 if (!msg)
83 return -ENOMEM;
b291f42a
CYC		 84
85 msg->version = 0;
727f1c71
TBS		 86 msg->command = cmd;
87 msg->outsize = outsize;
88 msg->insize = insize;
89
90 if (outsize)
91 memcpy(msg->data, out, outsize);
b291f42a 92
727f1c71
TBS		 93 ret = cros_ec_cmd_xfer_status(ec_dev, msg);
94 if (ret < 0)
95 goto error;
b291f42a 96
727f1c71
TBS		 97 if (insize)
98 memcpy(in, msg->data, insize);
b291f42a 99
727f1c71
TBS		 100 ret = 0;
101error:
102 kfree(msg);
b291f42a
CYC		 103 return ret;
104}
105
b6bc07d4
TBS		 106static int calculate_sha256(struct cros_ec_codec_priv *priv,
107 uint8_t *buf, uint32_t size, uint8_t *digest)
108{
93fa0af4 109 struct sha256_state sctx;
b6bc07d4 110
93fa0af4
AB		 111 sha256_init(&sctx);
112 sha256_update(&sctx, buf, size);
113 sha256_final(&sctx, digest);
b6bc07d4
TBS		 114
115#ifdef DEBUG
116 {
117 char digest_str[65];
118
119 bin2hex(digest_str, digest, 32);
120 digest_str[64] = 0;
121 dev_dbg(priv->dev, "hash=%s\n", digest_str);
122 }
123#endif
124
125 return 0;
126}
127
727f1c71
TBS		 128static int dmic_get_gain(struct snd_kcontrol *kcontrol,
129 struct snd_ctl_elem_value *ucontrol)
b291f42a 130{
727f1c71
TBS		 131 struct snd_soc_component *component =
132 snd_soc_kcontrol_component(kcontrol);
133 struct cros_ec_codec_priv *priv =
b291f42a 134 snd_soc_component_get_drvdata(component);
8f731d4c 135 struct ec_param_ec_codec_dmic p;
f3e82ad4 136 struct ec_response_ec_codec_dmic_get_gain_idx r;
727f1c71 137 int ret;
b291f42a 138
f3e82ad4
TBS		 139 p.cmd = EC_CODEC_DMIC_GET_GAIN_IDX;
140 p.get_gain_idx_param.channel = EC_CODEC_DMIC_CHANNEL_0;
8f731d4c 141 ret = send_ec_host_command(priv->ec_device, EC_CMD_EC_CODEC_DMIC,
727f1c71
TBS		 142 (uint8_t *)&p, sizeof(p),
143 (uint8_t *)&r, sizeof(r));
144 if (ret < 0)
145 return ret;
f3e82ad4 146 ucontrol->value.integer.value[0] = r.gain;
b291f42a 147
f3e82ad4
TBS		 148 p.cmd = EC_CODEC_DMIC_GET_GAIN_IDX;
149 p.get_gain_idx_param.channel = EC_CODEC_DMIC_CHANNEL_1;
150 ret = send_ec_host_command(priv->ec_device, EC_CMD_EC_CODEC_DMIC,
151 (uint8_t *)&p, sizeof(p),
152 (uint8_t *)&r, sizeof(r));
153 if (ret < 0)
154 return ret;
155 ucontrol->value.integer.value[1] = r.gain;
b291f42a 156
727f1c71 157 return 0;
b291f42a
CYC		 158}
159
727f1c71
TBS		 160static int dmic_put_gain(struct snd_kcontrol *kcontrol,
161 struct snd_ctl_elem_value *ucontrol)
b291f42a 162{
727f1c71
TBS		 163 struct snd_soc_component *component =
164 snd_soc_kcontrol_component(kcontrol);
165 struct cros_ec_codec_priv *priv =
166 snd_soc_component_get_drvdata(component);
167 struct soc_mixer_control *control =
168 (struct soc_mixer_control *)kcontrol->private_value;
169 int max_dmic_gain = control->max;
170 int left = ucontrol->value.integer.value[0];
171 int right = ucontrol->value.integer.value[1];
8f731d4c 172 struct ec_param_ec_codec_dmic p;
f3e82ad4 173 int ret;
b291f42a 174
727f1c71 175 if (left > max_dmic_gain || right > max_dmic_gain)
b291f42a 176 return -EINVAL;
b291f42a 177
727f1c71 178 dev_dbg(component->dev, "set mic gain to %u, %u\n", left, right);
b291f42a 179
f3e82ad4
TBS		 180 p.cmd = EC_CODEC_DMIC_SET_GAIN_IDX;
181 p.set_gain_idx_param.channel = EC_CODEC_DMIC_CHANNEL_0;
182 p.set_gain_idx_param.gain = left;
183 ret = send_ec_host_command(priv->ec_device, EC_CMD_EC_CODEC_DMIC,
184 (uint8_t *)&p, sizeof(p), NULL, 0);
185 if (ret < 0)
186 return ret;
187
188 p.cmd = EC_CODEC_DMIC_SET_GAIN_IDX;
189 p.set_gain_idx_param.channel = EC_CODEC_DMIC_CHANNEL_1;
190 p.set_gain_idx_param.gain = right;
8f731d4c 191 return send_ec_host_command(priv->ec_device, EC_CMD_EC_CODEC_DMIC,
727f1c71 192 (uint8_t *)&p, sizeof(p), NULL, 0);
b291f42a
CYC		 193}
194
727f1c71 195static const DECLARE_TLV_DB_SCALE(dmic_gain_tlv, 0, 100, 0);
b291f42a 196
727f1c71
TBS		 197enum {
198 DMIC_CTL_GAIN = 0,
199};
b291f42a 200
727f1c71
TBS		 201static struct snd_kcontrol_new dmic_controls[] = {
202 [DMIC_CTL_GAIN] =
203 SOC_DOUBLE_EXT_TLV("EC Mic Gain", SND_SOC_NOPM, SND_SOC_NOPM,
204 0, 0, 0, dmic_get_gain, dmic_put_gain,
205 dmic_gain_tlv),
206};
b291f42a 207
8f731d4c
TBS		 208static int dmic_probe(struct snd_soc_component *component)
209{
210 struct cros_ec_codec_priv *priv =
211 snd_soc_component_get_drvdata(component);
212 struct device *dev = priv->dev;
8f731d4c 213 struct soc_mixer_control *control;
f3e82ad4
TBS		 214 struct ec_param_ec_codec_dmic p;
215 struct ec_response_ec_codec_dmic_get_max_gain r;
216 int ret;
8f731d4c 217
b6bc07d4
TBS		 218 if (!atomic_add_unless(&priv->dmic_probed, 1, 1))
219 return 0;
220
f3e82ad4
TBS		 221 p.cmd = EC_CODEC_DMIC_GET_MAX_GAIN;
222
223 ret = send_ec_host_command(priv->ec_device, EC_CMD_EC_CODEC_DMIC,
224 (uint8_t *)&p, sizeof(p),
225 (uint8_t *)&r, sizeof(r));
226 if (ret < 0) {
227 dev_warn(dev, "get_max_gain() unsupported\n");
228 return 0;
8f731d4c
TBS		 229 }
230
f3e82ad4
TBS		 231 dev_dbg(dev, "max gain = %d\n", r.max_gain);
232
8f731d4c
TBS		 233 control = (struct soc_mixer_control *)
234 dmic_controls[DMIC_CTL_GAIN].private_value;
f3e82ad4
TBS		 235 control->max = r.max_gain;
236 control->platform_max = r.max_gain;
8f731d4c
TBS		 237
238 return snd_soc_add_component_controls(component,
239 &dmic_controls[DMIC_CTL_GAIN], 1);
240}
241
727f1c71
TBS		 242static int i2s_rx_hw_params(struct snd_pcm_substream *substream,
243 struct snd_pcm_hw_params *params,
244 struct snd_soc_dai *dai)
b291f42a
CYC		 245{
246 struct snd_soc_component *component = dai->component;
727f1c71
TBS		 247 struct cros_ec_codec_priv *priv =
248 snd_soc_component_get_drvdata(component);
249 struct ec_param_ec_codec_i2s_rx p;
250 enum ec_codec_i2s_rx_sample_depth depth;
99b4f439 251 uint32_t bclk;
b291f42a
CYC		 252 int ret;
253
727f1c71 254 if (params_rate(params) != 48000)
b291f42a
CYC		 255 return -EINVAL;
256
257 switch (params_format(params)) {
258 case SNDRV_PCM_FORMAT_S16_LE:
727f1c71 259 depth = EC_CODEC_I2S_RX_SAMPLE_DEPTH_16;
b291f42a
CYC		 260 break;
261 case SNDRV_PCM_FORMAT_S24_LE:
727f1c71 262 depth = EC_CODEC_I2S_RX_SAMPLE_DEPTH_24;
b291f42a
CYC		 263 break;
264 default:
265 return -EINVAL;
266 }
b291f42a 267
727f1c71 268 dev_dbg(component->dev, "set depth to %u\n", depth);
b291f42a 269
727f1c71
TBS		 270 p.cmd = EC_CODEC_I2S_RX_SET_SAMPLE_DEPTH;
271 p.set_sample_depth_param.depth = depth;
272 ret = send_ec_host_command(priv->ec_device, EC_CMD_EC_CODEC_I2S_RX,
273 (uint8_t *)&p, sizeof(p), NULL, 0);
b291f42a
CYC		 274 if (ret < 0)
275 return ret;
276
99b4f439
YHH		 277 if (priv->i2s_rx_bclk_ratio)
278 bclk = params_rate(params) * priv->i2s_rx_bclk_ratio;
279 else
280 bclk = snd_soc_params_to_bclk(params);
281
282 dev_dbg(component->dev, "set bclk to %u\n", bclk);
b291f42a 283
727f1c71 284 p.cmd = EC_CODEC_I2S_RX_SET_BCLK;
99b4f439 285 p.set_bclk_param.bclk = bclk;
727f1c71
TBS		 286 return send_ec_host_command(priv->ec_device, EC_CMD_EC_CODEC_I2S_RX,
287 (uint8_t *)&p, sizeof(p), NULL, 0);
b291f42a
CYC		 288}
289
99b4f439
YHH		 290static int i2s_rx_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
291{
292 struct snd_soc_component *component = dai->component;
293 struct cros_ec_codec_priv *priv =
294 snd_soc_component_get_drvdata(component);
295
296 priv->i2s_rx_bclk_ratio = ratio;
297 return 0;
298}
299
727f1c71 300static int i2s_rx_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
b291f42a 301{
727f1c71
TBS		 302 struct snd_soc_component *component = dai->component;
303 struct cros_ec_codec_priv *priv =
b291f42a 304 snd_soc_component_get_drvdata(component);
727f1c71
TBS		 305 struct ec_param_ec_codec_i2s_rx p;
306 enum ec_codec_i2s_rx_daifmt daifmt;
b291f42a 307
727f1c71
TBS		 308 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
309 case SND_SOC_DAIFMT_CBS_CFS:
310 break;
311 default:
b291f42a 312 return -EINVAL;
727f1c71 313 }
b291f42a 314
727f1c71
TBS		 315 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
316 case SND_SOC_DAIFMT_NB_NF:
317 break;
318 default:
319 return -EINVAL;
320 }
b291f42a 321
727f1c71
TBS		 322 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
323 case SND_SOC_DAIFMT_I2S:
324 daifmt = EC_CODEC_I2S_RX_DAIFMT_I2S;
325 break;
326 case SND_SOC_DAIFMT_RIGHT_J:
327 daifmt = EC_CODEC_I2S_RX_DAIFMT_RIGHT_J;
328 break;
329 case SND_SOC_DAIFMT_LEFT_J:
330 daifmt = EC_CODEC_I2S_RX_DAIFMT_LEFT_J;
331 break;
332 default:
333 return -EINVAL;
334 }
b291f42a 335
727f1c71 336 dev_dbg(component->dev, "set format to %u\n", daifmt);
b291f42a 337
727f1c71
TBS		 338 p.cmd = EC_CODEC_I2S_RX_SET_DAIFMT;
339 p.set_daifmt_param.daifmt = daifmt;
340 return send_ec_host_command(priv->ec_device, EC_CMD_EC_CODEC_I2S_RX,
341 (uint8_t *)&p, sizeof(p), NULL, 0);
b291f42a
CYC		 342}
343
727f1c71
TBS		 344static const struct snd_soc_dai_ops i2s_rx_dai_ops = {
345 .hw_params = i2s_rx_hw_params,
346 .set_fmt = i2s_rx_set_fmt,
99b4f439 347 .set_bclk_ratio = i2s_rx_set_bclk_ratio,
727f1c71
TBS		 348};
349
350static int i2s_rx_event(struct snd_soc_dapm_widget *w,
351 struct snd_kcontrol *kcontrol, int event)
b291f42a
CYC		 352{
353 struct snd_soc_component *component =
354 snd_soc_dapm_to_component(w->dapm);
727f1c71
TBS		 355 struct cros_ec_codec_priv *priv =
356 snd_soc_component_get_drvdata(component);
357 struct ec_param_ec_codec_i2s_rx p;
b291f42a
CYC		 358
359 switch (event) {
360 case SND_SOC_DAPM_PRE_PMU:
727f1c71
TBS		 361 dev_dbg(component->dev, "enable I2S RX\n");
362 p.cmd = EC_CODEC_I2S_RX_ENABLE;
363 break;
b291f42a 364 case SND_SOC_DAPM_PRE_PMD:
727f1c71
TBS		 365 dev_dbg(component->dev, "disable I2S RX\n");
366 p.cmd = EC_CODEC_I2S_RX_DISABLE;
367 break;
368 default:
369 return 0;
b291f42a
CYC		 370 }
371
727f1c71
TBS		 372 return send_ec_host_command(priv->ec_device, EC_CMD_EC_CODEC_I2S_RX,
373 (uint8_t *)&p, sizeof(p), NULL, 0);
b291f42a
CYC		 374}
375
727f1c71 376static struct snd_soc_dapm_widget i2s_rx_dapm_widgets[] = {
b291f42a 377 SND_SOC_DAPM_INPUT("DMIC"),
727f1c71 378 SND_SOC_DAPM_SUPPLY("I2S RX Enable", SND_SOC_NOPM, 0, 0, i2s_rx_event,
b291f42a 379 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
727f1c71
TBS		 380 SND_SOC_DAPM_AIF_OUT("I2S RX", "I2S Capture", 0, SND_SOC_NOPM, 0, 0),
381};
b291f42a 382
727f1c71
TBS		 383static struct snd_soc_dapm_route i2s_rx_dapm_routes[] = {
384 {"I2S RX", NULL, "DMIC"},
385 {"I2S RX", NULL, "I2S RX Enable"},
b291f42a
CYC		 386};
387
727f1c71
TBS		 388static struct snd_soc_dai_driver i2s_rx_dai_driver = {
389 .name = "EC Codec I2S RX",
390 .capture = {
391 .stream_name = "I2S Capture",
392 .channels_min = 2,
393 .channels_max = 2,
394 .rates = SNDRV_PCM_RATE_48000,
395 .formats = SNDRV_PCM_FMTBIT_S16_LE |
396 SNDRV_PCM_FMTBIT_S24_LE,
397 },
398 .ops = &i2s_rx_dai_ops,
b291f42a
CYC		 399};
400
727f1c71 401static int i2s_rx_probe(struct snd_soc_component *component)
b291f42a 402{
8f731d4c 403 return dmic_probe(component);
b291f42a
CYC		 404}
405
727f1c71
TBS		 406static const struct snd_soc_component_driver i2s_rx_component_driver = {
407 .probe = i2s_rx_probe,
408 .dapm_widgets = i2s_rx_dapm_widgets,
409 .num_dapm_widgets = ARRAY_SIZE(i2s_rx_dapm_widgets),
410 .dapm_routes = i2s_rx_dapm_routes,
411 .num_dapm_routes = ARRAY_SIZE(i2s_rx_dapm_routes),
b291f42a
CYC		 412};
413
b6bc07d4
TBS		 414static void *wov_map_shm(struct cros_ec_codec_priv *priv,
415 uint8_t shm_id, uint32_t *len, uint8_t *type)
416{
417 struct ec_param_ec_codec p;
418 struct ec_response_ec_codec_get_shm_addr r;
419 uint32_t req, offset;
420
421 p.cmd = EC_CODEC_GET_SHM_ADDR;
422 p.get_shm_addr_param.shm_id = shm_id;
423 if (send_ec_host_command(priv->ec_device, EC_CMD_EC_CODEC,
424 (uint8_t *)&p, sizeof(p),
425 (uint8_t *)&r, sizeof(r)) < 0) {
426 dev_err(priv->dev, "failed to EC_CODEC_GET_SHM_ADDR\n");
427 return NULL;
428 }
429
430 dev_dbg(priv->dev, "phys_addr=%#llx, len=%#x\n", r.phys_addr, r.len);
431
432 *len = r.len;
433 *type = r.type;
434
435 switch (r.type) {
436 case EC_CODEC_SHM_TYPE_EC_RAM:
437 return (void __force *)devm_ioremap_wc(priv->dev,
438 r.phys_addr + priv->ec_shm_addr, r.len);
439 case EC_CODEC_SHM_TYPE_SYSTEM_RAM:
440 if (r.phys_addr) {
441 dev_err(priv->dev, "unknown status\n");
442 return NULL;
443 }
444
445 req = round_up(r.len, PAGE_SIZE);
446 dev_dbg(priv->dev, "round up from %u to %u\n", r.len, req);
447
448 if (priv->ap_shm_last_alloc + req >
449 priv->ap_shm_phys_addr + priv->ap_shm_len) {
450 dev_err(priv->dev, "insufficient space for AP SHM\n");
451 return NULL;
452 }
453
454 dev_dbg(priv->dev, "alloc AP SHM addr=%#llx, len=%#x\n",
455 priv->ap_shm_last_alloc, req);
456
457 p.cmd = EC_CODEC_SET_SHM_ADDR;
458 p.set_shm_addr_param.phys_addr = priv->ap_shm_last_alloc;
459 p.set_shm_addr_param.len = req;
460 p.set_shm_addr_param.shm_id = shm_id;
461 if (send_ec_host_command(priv->ec_device, EC_CMD_EC_CODEC,
462 (uint8_t *)&p, sizeof(p),
463 NULL, 0) < 0) {
464 dev_err(priv->dev, "failed to EC_CODEC_SET_SHM_ADDR\n");
465 return NULL;
466 }
467
468 /*
469 * Note: EC codec only requests for `r.len' but we allocate
470 * round up PAGE_SIZE `req'.
471 */
472 offset = priv->ap_shm_last_alloc - priv->ap_shm_phys_addr;
473 priv->ap_shm_last_alloc += req;
474
475 return (void *)(uintptr_t)(priv->ap_shm_addr + offset);
476 default:
477 return NULL;
478 }
479}
480
481static bool wov_queue_full(struct cros_ec_codec_priv *priv)
482{
483 return ((priv->wov_wp + 1) % sizeof(priv->wov_buf)) == priv->wov_rp;
484}
485
486static size_t wov_queue_size(struct cros_ec_codec_priv *priv)
487{
488 if (priv->wov_wp >= priv->wov_rp)
489 return priv->wov_wp - priv->wov_rp;
490 else
491 return sizeof(priv->wov_buf) - priv->wov_rp + priv->wov_wp;
492}
493
494static void wov_queue_dequeue(struct cros_ec_codec_priv *priv, size_t len)
495{
496 struct snd_pcm_runtime *runtime = priv->wov_substream->runtime;
497 size_t req;
498
499 while (len) {
500 req = min(len, runtime->dma_bytes - priv->wov_dma_offset);
501 if (priv->wov_wp >= priv->wov_rp)
502 req = min(req, (size_t)priv->wov_wp - priv->wov_rp);
503 else
504 req = min(req, sizeof(priv->wov_buf) - priv->wov_rp);
505
506 memcpy(runtime->dma_area + priv->wov_dma_offset,
507 priv->wov_buf + priv->wov_rp, req);
508
509 priv->wov_dma_offset += req;
510 if (priv->wov_dma_offset == runtime->dma_bytes)
511 priv->wov_dma_offset = 0;
512
513 priv->wov_rp += req;
514 if (priv->wov_rp == sizeof(priv->wov_buf))
515 priv->wov_rp = 0;
516
517 len -= req;
518 }
519
520 snd_pcm_period_elapsed(priv->wov_substream);
521}
522
523static void wov_queue_try_dequeue(struct cros_ec_codec_priv *priv)
524{
525 size_t period_bytes = snd_pcm_lib_period_bytes(priv->wov_substream);
526
527 while (period_bytes && wov_queue_size(priv) >= period_bytes) {
528 wov_queue_dequeue(priv, period_bytes);
529 period_bytes = snd_pcm_lib_period_bytes(priv->wov_substream);
530 }
531}
532
533static void wov_queue_enqueue(struct cros_ec_codec_priv *priv,
534 uint8_t *addr, size_t len, bool iomem)
535{
536 size_t req;
537
538 while (len) {
539 if (wov_queue_full(priv)) {
540 wov_queue_try_dequeue(priv);
541
542 if (wov_queue_full(priv)) {
543 dev_err(priv->dev, "overrun detected\n");
544 return;
545 }
546 }
547
548 if (priv->wov_wp >= priv->wov_rp)
549 req = sizeof(priv->wov_buf) - priv->wov_wp;
550 else
551 /* Note: waste 1-byte to differentiate full and empty */
552 req = priv->wov_rp - priv->wov_wp - 1;
553 req = min(req, len);
554
555 if (iomem)
556 memcpy_fromio(priv->wov_buf + priv->wov_wp,
557 (void __force __iomem *)addr, req);
558 else
559 memcpy(priv->wov_buf + priv->wov_wp, addr, req);
560
561 priv->wov_wp += req;
562 if (priv->wov_wp == sizeof(priv->wov_buf))
563 priv->wov_wp = 0;
564
565 addr += req;
566 len -= req;
567 }
568
569 wov_queue_try_dequeue(priv);
570}
571
572static int wov_read_audio_shm(struct cros_ec_codec_priv *priv)
573{
574 struct ec_param_ec_codec_wov p;
575 struct ec_response_ec_codec_wov_read_audio_shm r;
576 int ret;
577
578 p.cmd = EC_CODEC_WOV_READ_AUDIO_SHM;
579 ret = send_ec_host_command(priv->ec_device, EC_CMD_EC_CODEC_WOV,
580 (uint8_t *)&p, sizeof(p),
581 (uint8_t *)&r, sizeof(r));
582 if (ret) {
583 dev_err(priv->dev, "failed to EC_CODEC_WOV_READ_AUDIO_SHM\n");
584 return ret;
585 }
586
587 if (!r.len)
588 dev_dbg(priv->dev, "no data, sleep\n");
589 else
590 wov_queue_enqueue(priv, priv->wov_audio_shm_p + r.offset, r.len,
591 priv->wov_audio_shm_type == EC_CODEC_SHM_TYPE_EC_RAM);
592 return -EAGAIN;
593}
594
595static int wov_read_audio(struct cros_ec_codec_priv *priv)
596{
597 struct ec_param_ec_codec_wov p;
598 struct ec_response_ec_codec_wov_read_audio r;
599 int remain = priv->wov_burst_read ? 16000 : 320;
600 int ret;
601
602 while (remain >= 0) {
603 p.cmd = EC_CODEC_WOV_READ_AUDIO;
604 ret = send_ec_host_command(priv->ec_device, EC_CMD_EC_CODEC_WOV,
605 (uint8_t *)&p, sizeof(p),
606 (uint8_t *)&r, sizeof(r));
607 if (ret) {
608 dev_err(priv->dev,
609 "failed to EC_CODEC_WOV_READ_AUDIO\n");
610 return ret;
611 }
612
613 if (!r.len) {
614 dev_dbg(priv->dev, "no data, sleep\n");
615 priv->wov_burst_read = false;
616 break;
617 }
618
619 wov_queue_enqueue(priv, r.buf, r.len, false);
620 remain -= r.len;
621 }
622
623 return -EAGAIN;
624}
625
626static void wov_copy_work(struct work_struct *w)
627{
628 struct cros_ec_codec_priv *priv =
629 container_of(w, struct cros_ec_codec_priv, wov_copy_work.work);
630 int ret;
631
632 mutex_lock(&priv->wov_dma_lock);
633 if (!priv->wov_substream) {
634 dev_warn(priv->dev, "no pcm substream\n");
635 goto leave;
636 }
637
638 if (ec_codec_capable(priv, EC_CODEC_CAP_WOV_AUDIO_SHM))
639 ret = wov_read_audio_shm(priv);
640 else
641 ret = wov_read_audio(priv);
642
643 if (ret == -EAGAIN)
644 schedule_delayed_work(&priv->wov_copy_work,
645 msecs_to_jiffies(10));
646 else if (ret)
647 dev_err(priv->dev, "failed to read audio data\n");
648leave:
649 mutex_unlock(&priv->wov_dma_lock);
650}
651
652static int wov_enable_get(struct snd_kcontrol *kcontrol,
653 struct snd_ctl_elem_value *ucontrol)
654{
655 struct snd_soc_component *c = snd_soc_kcontrol_component(kcontrol);
656 struct cros_ec_codec_priv *priv = snd_soc_component_get_drvdata(c);
657
658 ucontrol->value.integer.value[0] = priv->wov_enabled;
659 return 0;
660}
661
662static int wov_enable_put(struct snd_kcontrol *kcontrol,
663 struct snd_ctl_elem_value *ucontrol)
664{
665 struct snd_soc_component *c = snd_soc_kcontrol_component(kcontrol);
666 struct cros_ec_codec_priv *priv = snd_soc_component_get_drvdata(c);
667 int enabled = ucontrol->value.integer.value[0];
668 struct ec_param_ec_codec_wov p;
669 int ret;
670
671 if (priv->wov_enabled != enabled) {
672 if (enabled)
673 p.cmd = EC_CODEC_WOV_ENABLE;
674 else
675 p.cmd = EC_CODEC_WOV_DISABLE;
676
677 ret = send_ec_host_command(priv->ec_device, EC_CMD_EC_CODEC_WOV,
678 (uint8_t *)&p, sizeof(p), NULL, 0);
679 if (ret) {
680 dev_err(priv->dev, "failed to %s wov\n",
681 enabled ? "enable" : "disable");
682 return ret;
683 }
684
685 priv->wov_enabled = enabled;
686 }
687
688 return 0;
689}
690
691static int wov_set_lang_shm(struct cros_ec_codec_priv *priv,
692 uint8_t *buf, size_t size, uint8_t *digest)
693{
694 struct ec_param_ec_codec_wov p;
695 struct ec_param_ec_codec_wov_set_lang_shm *pp = &p.set_lang_shm_param;
696 int ret;
697
698 if (size > priv->wov_lang_shm_len) {
699 dev_err(priv->dev, "no enough SHM size: %d\n",
700 priv->wov_lang_shm_len);
701 return -EIO;
702 }
703
704 switch (priv->wov_lang_shm_type) {
705 case EC_CODEC_SHM_TYPE_EC_RAM:
706 memcpy_toio((void __force __iomem *)priv->wov_lang_shm_p,
707 buf, size);
708 memset_io((void __force __iomem *)priv->wov_lang_shm_p + size,
709 0, priv->wov_lang_shm_len - size);
710 break;
711 case EC_CODEC_SHM_TYPE_SYSTEM_RAM:
712 memcpy(priv->wov_lang_shm_p, buf, size);
713 memset(priv->wov_lang_shm_p + size, 0,
714 priv->wov_lang_shm_len - size);
715
716 /* make sure write to memory before calling host command */
717 wmb();
718 break;
719 }
720
721 p.cmd = EC_CODEC_WOV_SET_LANG_SHM;
722 memcpy(pp->hash, digest, SHA256_DIGEST_SIZE);
723 pp->total_len = size;
724 ret = send_ec_host_command(priv->ec_device, EC_CMD_EC_CODEC_WOV,
725 (uint8_t *)&p, sizeof(p), NULL, 0);
726 if (ret) {
727 dev_err(priv->dev, "failed to EC_CODEC_WOV_SET_LANG_SHM\n");
728 return ret;
729 }
730
731 return 0;
732}
733
734static int wov_set_lang(struct cros_ec_codec_priv *priv,
735 uint8_t *buf, size_t size, uint8_t *digest)
736{
737 struct ec_param_ec_codec_wov p;
738 struct ec_param_ec_codec_wov_set_lang *pp = &p.set_lang_param;
739 size_t i, req;
740 int ret;
741
742 for (i = 0; i < size; i += req) {
743 req = min(size - i, ARRAY_SIZE(pp->buf));
744
745 p.cmd = EC_CODEC_WOV_SET_LANG;
746 memcpy(pp->hash, digest, SHA256_DIGEST_SIZE);
747 pp->total_len = size;
748 pp->offset = i;
749 memcpy(pp->buf, buf + i, req);
750 pp->len = req;
751 ret = send_ec_host_command(priv->ec_device, EC_CMD_EC_CODEC_WOV,
752 (uint8_t *)&p, sizeof(p), NULL, 0);
753 if (ret) {
754 dev_err(priv->dev, "failed to EC_CODEC_WOV_SET_LANG\n");
755 return ret;
756 }
757 }
758
759 return 0;
760}
761
762static int wov_hotword_model_put(struct snd_kcontrol *kcontrol,
763 const unsigned int __user *bytes,
764 unsigned int size)
765{
766 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
767 struct cros_ec_codec_priv *priv =
768 snd_soc_component_get_drvdata(component);
769 struct ec_param_ec_codec_wov p;
770 struct ec_response_ec_codec_wov_get_lang r;
771 uint8_t digest[SHA256_DIGEST_SIZE];
772 uint8_t *buf;
773 int ret;
774
775 /* Skips the TLV header. */
776 bytes += 2;
777 size -= 8;
778
779 dev_dbg(priv->dev, "%s: size=%d\n", __func__, size);
780
781 buf = memdup_user(bytes, size);
782 if (IS_ERR(buf))
783 return PTR_ERR(buf);
784
785 ret = calculate_sha256(priv, buf, size, digest);
786 if (ret)
787 goto leave;
788
789 p.cmd = EC_CODEC_WOV_GET_LANG;
790 ret = send_ec_host_command(priv->ec_device, EC_CMD_EC_CODEC_WOV,
791 (uint8_t *)&p, sizeof(p),
792 (uint8_t *)&r, sizeof(r));
793 if (ret)
794 goto leave;
795
796 if (memcmp(digest, r.hash, SHA256_DIGEST_SIZE) == 0) {
797 dev_dbg(priv->dev, "not updated");
798 goto leave;
799 }
800
801 if (ec_codec_capable(priv, EC_CODEC_CAP_WOV_LANG_SHM))
802 ret = wov_set_lang_shm(priv, buf, size, digest);
803 else
804 ret = wov_set_lang(priv, buf, size, digest);
805
806leave:
807 kfree(buf);
808 return ret;
809}
810
811static struct snd_kcontrol_new wov_controls[] = {
812 SOC_SINGLE_BOOL_EXT("Wake-on-Voice Switch", 0,
813 wov_enable_get, wov_enable_put),
814 SND_SOC_BYTES_TLV("Hotword Model", 0x11000, NULL,
815 wov_hotword_model_put),
816};
817
818static struct snd_soc_dai_driver wov_dai_driver = {
819 .name = "Wake on Voice",
820 .capture = {
821 .stream_name = "WoV Capture",
822 .channels_min = 1,
823 .channels_max = 1,
824 .rates = SNDRV_PCM_RATE_16000,
825 .formats = SNDRV_PCM_FMTBIT_S16_LE,
826 },
827};
828
829static int wov_host_event(struct notifier_block *nb,
830 unsigned long queued_during_suspend, void *notify)
831{
832 struct cros_ec_codec_priv *priv =
833 container_of(nb, struct cros_ec_codec_priv, wov_notifier);
834 u32 host_event;
835
836 dev_dbg(priv->dev, "%s\n", __func__);
837
838 host_event = cros_ec_get_host_event(priv->ec_device);
839 if (host_event & EC_HOST_EVENT_MASK(EC_HOST_EVENT_WOV)) {
840 schedule_delayed_work(&priv->wov_copy_work, 0);
841 return NOTIFY_OK;
842 } else {
843 return NOTIFY_DONE;
844 }
845}
846
847static int wov_probe(struct snd_soc_component *component)
848{
849 struct cros_ec_codec_priv *priv =
850 snd_soc_component_get_drvdata(component);
851 int ret;
852
853 mutex_init(&priv->wov_dma_lock);
854 INIT_DELAYED_WORK(&priv->wov_copy_work, wov_copy_work);
855
856 priv->wov_notifier.notifier_call = wov_host_event;
857 ret = blocking_notifier_chain_register(
858 &priv->ec_device->event_notifier, &priv->wov_notifier);
859 if (ret)
860 return ret;
861
862 if (ec_codec_capable(priv, EC_CODEC_CAP_WOV_LANG_SHM)) {
863 priv->wov_lang_shm_p = wov_map_shm(priv,
864 EC_CODEC_SHM_ID_WOV_LANG,
865 &priv->wov_lang_shm_len,
866 &priv->wov_lang_shm_type);
867 if (!priv->wov_lang_shm_p)
868 return -EFAULT;
869 }
870
871 if (ec_codec_capable(priv, EC_CODEC_CAP_WOV_AUDIO_SHM)) {
872 priv->wov_audio_shm_p = wov_map_shm(priv,
873 EC_CODEC_SHM_ID_WOV_AUDIO,
874 &priv->wov_audio_shm_len,
875 &priv->wov_audio_shm_type);
876 if (!priv->wov_audio_shm_p)
877 return -EFAULT;
878 }
879
880 return dmic_probe(component);
881}
882
883static void wov_remove(struct snd_soc_component *component)
884{
885 struct cros_ec_codec_priv *priv =
886 snd_soc_component_get_drvdata(component);
887
888 blocking_notifier_chain_unregister(
889 &priv->ec_device->event_notifier, &priv->wov_notifier);
890}
891
892static int wov_pcm_open(struct snd_soc_component *component,
893 struct snd_pcm_substream *substream)
894{
895 static const struct snd_pcm_hardware hw_param = {
896 .info = SNDRV_PCM_INFO_MMAP |
897 SNDRV_PCM_INFO_INTERLEAVED |
898 SNDRV_PCM_INFO_MMAP_VALID,
899 .formats = SNDRV_PCM_FMTBIT_S16_LE,
900 .rates = SNDRV_PCM_RATE_16000,
901 .channels_min = 1,
902 .channels_max = 1,
903 .period_bytes_min = PAGE_SIZE,
904 .period_bytes_max = 0x20000 / 8,
905 .periods_min = 8,
906 .periods_max = 8,
907 .buffer_bytes_max = 0x20000,
908 };
909
910 return snd_soc_set_runtime_hwparams(substream, &hw_param);
911}
912
913static int wov_pcm_hw_params(struct snd_soc_component *component,
914 struct snd_pcm_substream *substream,
915 struct snd_pcm_hw_params *hw_params)
916{
917 struct cros_ec_codec_priv *priv =
918 snd_soc_component_get_drvdata(component);
919
920 mutex_lock(&priv->wov_dma_lock);
921 priv->wov_substream = substream;
922 priv->wov_rp = priv->wov_wp = 0;
923 priv->wov_dma_offset = 0;
924 priv->wov_burst_read = true;
925 mutex_unlock(&priv->wov_dma_lock);
926
66b3621b 927 return 0;
b6bc07d4
TBS		 928}
929
930static int wov_pcm_hw_free(struct snd_soc_component *component,
931 struct snd_pcm_substream *substream)
932{
933 struct cros_ec_codec_priv *priv =
934 snd_soc_component_get_drvdata(component);
935
936 mutex_lock(&priv->wov_dma_lock);
937 wov_queue_dequeue(priv, wov_queue_size(priv));
938 priv->wov_substream = NULL;
939 mutex_unlock(&priv->wov_dma_lock);
940
941 cancel_delayed_work_sync(&priv->wov_copy_work);
942
66b3621b 943 return 0;
b6bc07d4
TBS		 944}
945
946static snd_pcm_uframes_t wov_pcm_pointer(struct snd_soc_component *component,
947 struct snd_pcm_substream *substream)
948{
949 struct snd_pcm_runtime *runtime = substream->runtime;
950 struct cros_ec_codec_priv *priv =
951 snd_soc_component_get_drvdata(component);
952
953 return bytes_to_frames(runtime, priv->wov_dma_offset);
954}
955
e610748a
TI		 956static int wov_pcm_new(struct snd_soc_component *component,
957 struct snd_soc_pcm_runtime *rtd)
b6bc07d4 958{
66b3621b
TI		 959 snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_VMALLOC,
960 NULL, 0, 0);
e610748a 961 return 0;
b6bc07d4
TBS		 962}
963
964static const struct snd_soc_component_driver wov_component_driver = {
965 .probe = wov_probe,
966 .remove = wov_remove,
967 .controls = wov_controls,
968 .num_controls = ARRAY_SIZE(wov_controls),
969 .open = wov_pcm_open,
970 .hw_params = wov_pcm_hw_params,
971 .hw_free = wov_pcm_hw_free,
972 .pointer = wov_pcm_pointer,
e610748a 973 .pcm_construct = wov_pcm_new,
b6bc07d4
TBS		 974};
975
727f1c71 976static int cros_ec_codec_platform_probe(struct platform_device *pdev)
b291f42a 977{
727f1c71
TBS		 978 struct device *dev = &pdev->dev;
979 struct cros_ec_device *ec_device = dev_get_drvdata(pdev->dev.parent);
980 struct cros_ec_codec_priv *priv;
b6bc07d4
TBS		 981 struct ec_param_ec_codec p;
982 struct ec_response_ec_codec_get_capabilities r;
983 int ret;
984#ifdef CONFIG_OF
985 struct device_node *node;
986 struct resource res;
987 u64 ec_shm_size;
988 const __be32 *regaddr_p;
989#endif
b291f42a 990
727f1c71
TBS		 991 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
992 if (!priv)
b291f42a
CYC		 993 return -ENOMEM;
994
b6bc07d4
TBS		 995#ifdef CONFIG_OF
996 regaddr_p = of_get_address(dev->of_node, 0, &ec_shm_size, NULL);
997 if (regaddr_p) {
998 priv->ec_shm_addr = of_read_number(regaddr_p, 2);
999 priv->ec_shm_len = ec_shm_size;
1000
1001 dev_dbg(dev, "ec_shm_addr=%#llx len=%#x\n",
1002 priv->ec_shm_addr, priv->ec_shm_len);
1003 }
1004
1005 node = of_parse_phandle(dev->of_node, "memory-region", 0);
1006 if (node) {
1007 ret = of_address_to_resource(node, 0, &res);
1008 if (!ret) {
1009 priv->ap_shm_phys_addr = res.start;
1010 priv->ap_shm_len = resource_size(&res);
1011 priv->ap_shm_addr =
1012 (uint64_t)(uintptr_t)devm_ioremap_wc(
1013 dev, priv->ap_shm_phys_addr,
1014 priv->ap_shm_len);
1015 priv->ap_shm_last_alloc = priv->ap_shm_phys_addr;
1016
1017 dev_dbg(dev, "ap_shm_phys_addr=%#llx len=%#x\n",
1018 priv->ap_shm_phys_addr, priv->ap_shm_len);
1019 }
1020 }
1021#endif
1022
727f1c71
TBS		 1023 priv->dev = dev;
1024 priv->ec_device = ec_device;
b6bc07d4
TBS		 1025 atomic_set(&priv->dmic_probed, 0);
1026
1027 p.cmd = EC_CODEC_GET_CAPABILITIES;
1028 ret = send_ec_host_command(priv->ec_device, EC_CMD_EC_CODEC,
1029 (uint8_t *)&p, sizeof(p),
1030 (uint8_t *)&r, sizeof(r));
1031 if (ret) {
1032 dev_err(dev, "failed to EC_CODEC_GET_CAPABILITIES\n");
1033 return ret;
1034 }
1035 priv->ec_capabilities = r.capabilities;
b291f42a 1036
727f1c71 1037 platform_set_drvdata(pdev, priv);
b291f42a 1038
b6bc07d4
TBS		 1039 ret = devm_snd_soc_register_component(dev, &i2s_rx_component_driver,
1040 &i2s_rx_dai_driver, 1);
1041 if (ret)
1042 return ret;
1043
1044 return devm_snd_soc_register_component(dev, &wov_component_driver,
1045 &wov_dai_driver, 1);
b291f42a
CYC		 1046}
1047
1048#ifdef CONFIG_OF
1049static const struct of_device_id cros_ec_codec_of_match[] = {
1050 { .compatible = "google,cros-ec-codec" },
1051 {},
1052};
1053MODULE_DEVICE_TABLE(of, cros_ec_codec_of_match);
1054#endif
1055
877167ef
YHH		 1056static const struct acpi_device_id cros_ec_codec_acpi_id[] = {
1057 { "GOOG0013", 0 },
1058 { }
1059};
1060MODULE_DEVICE_TABLE(acpi, cros_ec_codec_acpi_id);
1061
b291f42a
CYC		 1062static struct platform_driver cros_ec_codec_platform_driver = {
1063 .driver = {
727f1c71 1064 .name = "cros-ec-codec",
b291f42a 1065 .of_match_table = of_match_ptr(cros_ec_codec_of_match),
877167ef 1066 .acpi_match_table = ACPI_PTR(cros_ec_codec_acpi_id),
b291f42a
CYC		 1067 },
1068 .probe = cros_ec_codec_platform_probe,
1069};
1070
1071module_platform_driver(cros_ec_codec_platform_driver);
1072
1073MODULE_LICENSE("GPL v2");
1074MODULE_DESCRIPTION("ChromeOS EC codec driver");
1075MODULE_AUTHOR("Cheng-Yi Chiang <cychiang@chromium.org>");
727f1c71 1076MODULE_ALIAS("platform:cros-ec-codec");
Linux 6.x block layer and io_uring tree(s)