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6c742509 SG |
1 | /* |
2 | * atmel_ssc_dai.c -- ALSA SoC ATMEL SSC Audio Layer Platform driver | |
3 | * | |
4 | * Copyright (C) 2005 SAN People | |
5 | * Copyright (C) 2008 Atmel | |
6 | * | |
7 | * Author: Sedji Gaouaou <sedji.gaouaou@atmel.com> | |
8 | * ATMEL CORP. | |
9 | * | |
10 | * Based on at91-ssc.c by | |
11 | * Frank Mandarino <fmandarino@endrelia.com> | |
12 | * Based on pxa2xx Platform drivers by | |
64ca0404 | 13 | * Liam Girdwood <lrg@slimlogic.co.uk> |
6c742509 SG |
14 | * |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License as published by | |
17 | * the Free Software Foundation; either version 2 of the License, or | |
18 | * (at your option) any later version. | |
19 | * | |
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | * | |
25 | * You should have received a copy of the GNU General Public License | |
26 | * along with this program; if not, write to the Free Software | |
27 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
28 | */ | |
29 | ||
30 | #include <linux/init.h> | |
31 | #include <linux/module.h> | |
32 | #include <linux/interrupt.h> | |
33 | #include <linux/device.h> | |
34 | #include <linux/delay.h> | |
35 | #include <linux/clk.h> | |
36 | #include <linux/atmel_pdc.h> | |
37 | ||
38 | #include <linux/atmel-ssc.h> | |
39 | #include <sound/core.h> | |
40 | #include <sound/pcm.h> | |
41 | #include <sound/pcm_params.h> | |
42 | #include <sound/initval.h> | |
43 | #include <sound/soc.h> | |
44 | ||
6c742509 SG |
45 | #include "atmel-pcm.h" |
46 | #include "atmel_ssc_dai.h" | |
47 | ||
48 | ||
6c742509 | 49 | #define NUM_SSC_DEVICES 3 |
6c742509 SG |
50 | |
51 | /* | |
52 | * SSC PDC registers required by the PCM DMA engine. | |
53 | */ | |
54 | static struct atmel_pdc_regs pdc_tx_reg = { | |
55 | .xpr = ATMEL_PDC_TPR, | |
56 | .xcr = ATMEL_PDC_TCR, | |
57 | .xnpr = ATMEL_PDC_TNPR, | |
58 | .xncr = ATMEL_PDC_TNCR, | |
59 | }; | |
60 | ||
61 | static struct atmel_pdc_regs pdc_rx_reg = { | |
62 | .xpr = ATMEL_PDC_RPR, | |
63 | .xcr = ATMEL_PDC_RCR, | |
64 | .xnpr = ATMEL_PDC_RNPR, | |
65 | .xncr = ATMEL_PDC_RNCR, | |
66 | }; | |
67 | ||
68 | /* | |
69 | * SSC & PDC status bits for transmit and receive. | |
70 | */ | |
71 | static struct atmel_ssc_mask ssc_tx_mask = { | |
72 | .ssc_enable = SSC_BIT(CR_TXEN), | |
73 | .ssc_disable = SSC_BIT(CR_TXDIS), | |
74 | .ssc_endx = SSC_BIT(SR_ENDTX), | |
75 | .ssc_endbuf = SSC_BIT(SR_TXBUFE), | |
f1b0dd8b | 76 | .ssc_error = SSC_BIT(SR_OVRUN), |
6c742509 SG |
77 | .pdc_enable = ATMEL_PDC_TXTEN, |
78 | .pdc_disable = ATMEL_PDC_TXTDIS, | |
79 | }; | |
80 | ||
81 | static struct atmel_ssc_mask ssc_rx_mask = { | |
82 | .ssc_enable = SSC_BIT(CR_RXEN), | |
83 | .ssc_disable = SSC_BIT(CR_RXDIS), | |
84 | .ssc_endx = SSC_BIT(SR_ENDRX), | |
85 | .ssc_endbuf = SSC_BIT(SR_RXBUFF), | |
f1b0dd8b | 86 | .ssc_error = SSC_BIT(SR_OVRUN), |
6c742509 SG |
87 | .pdc_enable = ATMEL_PDC_RXTEN, |
88 | .pdc_disable = ATMEL_PDC_RXTDIS, | |
89 | }; | |
90 | ||
91 | ||
92 | /* | |
93 | * DMA parameters. | |
94 | */ | |
95 | static struct atmel_pcm_dma_params ssc_dma_params[NUM_SSC_DEVICES][2] = { | |
96 | {{ | |
97 | .name = "SSC0 PCM out", | |
98 | .pdc = &pdc_tx_reg, | |
99 | .mask = &ssc_tx_mask, | |
100 | }, | |
101 | { | |
102 | .name = "SSC0 PCM in", | |
103 | .pdc = &pdc_rx_reg, | |
104 | .mask = &ssc_rx_mask, | |
105 | } }, | |
6c742509 SG |
106 | {{ |
107 | .name = "SSC1 PCM out", | |
108 | .pdc = &pdc_tx_reg, | |
109 | .mask = &ssc_tx_mask, | |
110 | }, | |
111 | { | |
112 | .name = "SSC1 PCM in", | |
113 | .pdc = &pdc_rx_reg, | |
114 | .mask = &ssc_rx_mask, | |
115 | } }, | |
116 | {{ | |
117 | .name = "SSC2 PCM out", | |
118 | .pdc = &pdc_tx_reg, | |
119 | .mask = &ssc_tx_mask, | |
120 | }, | |
121 | { | |
122 | .name = "SSC2 PCM in", | |
123 | .pdc = &pdc_rx_reg, | |
124 | .mask = &ssc_rx_mask, | |
125 | } }, | |
6c742509 SG |
126 | }; |
127 | ||
128 | ||
129 | static struct atmel_ssc_info ssc_info[NUM_SSC_DEVICES] = { | |
130 | { | |
131 | .name = "ssc0", | |
132 | .lock = __SPIN_LOCK_UNLOCKED(ssc_info[0].lock), | |
133 | .dir_mask = SSC_DIR_MASK_UNUSED, | |
134 | .initialized = 0, | |
135 | }, | |
6c742509 SG |
136 | { |
137 | .name = "ssc1", | |
138 | .lock = __SPIN_LOCK_UNLOCKED(ssc_info[1].lock), | |
139 | .dir_mask = SSC_DIR_MASK_UNUSED, | |
140 | .initialized = 0, | |
141 | }, | |
142 | { | |
143 | .name = "ssc2", | |
144 | .lock = __SPIN_LOCK_UNLOCKED(ssc_info[2].lock), | |
145 | .dir_mask = SSC_DIR_MASK_UNUSED, | |
146 | .initialized = 0, | |
147 | }, | |
6c742509 SG |
148 | }; |
149 | ||
150 | ||
151 | /* | |
152 | * SSC interrupt handler. Passes PDC interrupts to the DMA | |
153 | * interrupt handler in the PCM driver. | |
154 | */ | |
155 | static irqreturn_t atmel_ssc_interrupt(int irq, void *dev_id) | |
156 | { | |
157 | struct atmel_ssc_info *ssc_p = dev_id; | |
158 | struct atmel_pcm_dma_params *dma_params; | |
159 | u32 ssc_sr; | |
160 | u32 ssc_substream_mask; | |
161 | int i; | |
162 | ||
163 | ssc_sr = (unsigned long)ssc_readl(ssc_p->ssc->regs, SR) | |
164 | & (unsigned long)ssc_readl(ssc_p->ssc->regs, IMR); | |
165 | ||
166 | /* | |
167 | * Loop through the substreams attached to this SSC. If | |
168 | * a DMA-related interrupt occurred on that substream, call | |
169 | * the DMA interrupt handler function, if one has been | |
170 | * registered in the dma_params structure by the PCM driver. | |
171 | */ | |
172 | for (i = 0; i < ARRAY_SIZE(ssc_p->dma_params); i++) { | |
173 | dma_params = ssc_p->dma_params[i]; | |
174 | ||
175 | if ((dma_params != NULL) && | |
176 | (dma_params->dma_intr_handler != NULL)) { | |
177 | ssc_substream_mask = (dma_params->mask->ssc_endx | | |
178 | dma_params->mask->ssc_endbuf); | |
179 | if (ssc_sr & ssc_substream_mask) { | |
180 | dma_params->dma_intr_handler(ssc_sr, | |
181 | dma_params-> | |
182 | substream); | |
183 | } | |
184 | } | |
185 | } | |
186 | ||
187 | return IRQ_HANDLED; | |
188 | } | |
189 | ||
b6d6c6e9 PR |
190 | /* |
191 | * When the bit clock is input, limit the maximum rate according to the | |
192 | * Serial Clock Ratio Considerations section from the SSC documentation: | |
193 | * | |
194 | * The Transmitter and the Receiver can be programmed to operate | |
195 | * with the clock signals provided on either the TK or RK pins. | |
196 | * This allows the SSC to support many slave-mode data transfers. | |
197 | * In this case, the maximum clock speed allowed on the RK pin is: | |
198 | * - Peripheral clock divided by 2 if Receiver Frame Synchro is input | |
199 | * - Peripheral clock divided by 3 if Receiver Frame Synchro is output | |
200 | * In addition, the maximum clock speed allowed on the TK pin is: | |
201 | * - Peripheral clock divided by 6 if Transmit Frame Synchro is input | |
202 | * - Peripheral clock divided by 2 if Transmit Frame Synchro is output | |
203 | * | |
204 | * When the bit clock is output, limit the rate according to the | |
205 | * SSC divider restrictions. | |
206 | */ | |
207 | static int atmel_ssc_hw_rule_rate(struct snd_pcm_hw_params *params, | |
208 | struct snd_pcm_hw_rule *rule) | |
209 | { | |
210 | struct atmel_ssc_info *ssc_p = rule->private; | |
211 | struct ssc_device *ssc = ssc_p->ssc; | |
212 | struct snd_interval *i = hw_param_interval(params, rule->var); | |
213 | struct snd_interval t; | |
214 | struct snd_ratnum r = { | |
215 | .den_min = 1, | |
216 | .den_max = 4095, | |
217 | .den_step = 1, | |
218 | }; | |
219 | unsigned int num = 0, den = 0; | |
220 | int frame_size; | |
221 | int mck_div = 2; | |
222 | int ret; | |
223 | ||
224 | frame_size = snd_soc_params_to_frame_size(params); | |
225 | if (frame_size < 0) | |
226 | return frame_size; | |
227 | ||
228 | switch (ssc_p->daifmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
229 | case SND_SOC_DAIFMT_CBM_CFS: | |
230 | if ((ssc_p->dir_mask & SSC_DIR_MASK_CAPTURE) | |
231 | && ssc->clk_from_rk_pin) | |
232 | /* Receiver Frame Synchro (i.e. capture) | |
233 | * is output (format is _CFS) and the RK pin | |
234 | * is used for input (format is _CBM_). | |
235 | */ | |
236 | mck_div = 3; | |
237 | break; | |
238 | ||
239 | case SND_SOC_DAIFMT_CBM_CFM: | |
240 | if ((ssc_p->dir_mask & SSC_DIR_MASK_PLAYBACK) | |
241 | && !ssc->clk_from_rk_pin) | |
242 | /* Transmit Frame Synchro (i.e. playback) | |
243 | * is input (format is _CFM) and the TK pin | |
244 | * is used for input (format _CBM_ but not | |
245 | * using the RK pin). | |
246 | */ | |
247 | mck_div = 6; | |
248 | break; | |
249 | } | |
250 | ||
251 | switch (ssc_p->daifmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
252 | case SND_SOC_DAIFMT_CBS_CFS: | |
253 | r.num = ssc_p->mck_rate / mck_div / frame_size; | |
254 | ||
255 | ret = snd_interval_ratnum(i, 1, &r, &num, &den); | |
256 | if (ret >= 0 && den && rule->var == SNDRV_PCM_HW_PARAM_RATE) { | |
257 | params->rate_num = num; | |
258 | params->rate_den = den; | |
259 | } | |
260 | break; | |
261 | ||
262 | case SND_SOC_DAIFMT_CBM_CFS: | |
263 | case SND_SOC_DAIFMT_CBM_CFM: | |
264 | t.min = 8000; | |
265 | t.max = ssc_p->mck_rate / mck_div / frame_size; | |
266 | t.openmin = t.openmax = 0; | |
267 | t.integer = 0; | |
268 | ret = snd_interval_refine(i, &t); | |
269 | break; | |
270 | ||
271 | default: | |
272 | ret = -EINVAL; | |
273 | break; | |
274 | } | |
275 | ||
276 | return ret; | |
277 | } | |
6c742509 SG |
278 | |
279 | /*-------------------------------------------------------------------------*\ | |
280 | * DAI functions | |
281 | \*-------------------------------------------------------------------------*/ | |
282 | /* | |
283 | * Startup. Only that one substream allowed in each direction. | |
284 | */ | |
dee89c4d MB |
285 | static int atmel_ssc_startup(struct snd_pcm_substream *substream, |
286 | struct snd_soc_dai *dai) | |
6c742509 | 287 | { |
c706f2e5 SW |
288 | struct platform_device *pdev = to_platform_device(dai->dev); |
289 | struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id]; | |
01f00d55 BS |
290 | struct atmel_pcm_dma_params *dma_params; |
291 | int dir, dir_mask; | |
b6d6c6e9 | 292 | int ret; |
6c742509 | 293 | |
56113f6e | 294 | pr_debug("atmel_ssc_startup: SSC_SR=0x%x\n", |
6c742509 SG |
295 | ssc_readl(ssc_p->ssc->regs, SR)); |
296 | ||
cbaadf0f BS |
297 | /* Enable PMC peripheral clock for this SSC */ |
298 | pr_debug("atmel_ssc_dai: Starting clock\n"); | |
299 | clk_enable(ssc_p->ssc->clk); | |
b6d6c6e9 | 300 | ssc_p->mck_rate = clk_get_rate(ssc_p->ssc->clk); |
cbaadf0f | 301 | |
3e103a65 CH |
302 | /* Reset the SSC unless initialized to keep it in a clean state */ |
303 | if (!ssc_p->initialized) | |
304 | ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST)); | |
cbaadf0f | 305 | |
01f00d55 BS |
306 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
307 | dir = 0; | |
6c742509 | 308 | dir_mask = SSC_DIR_MASK_PLAYBACK; |
01f00d55 BS |
309 | } else { |
310 | dir = 1; | |
6c742509 | 311 | dir_mask = SSC_DIR_MASK_CAPTURE; |
01f00d55 BS |
312 | } |
313 | ||
b6d6c6e9 PR |
314 | ret = snd_pcm_hw_rule_add(substream->runtime, 0, |
315 | SNDRV_PCM_HW_PARAM_RATE, | |
316 | atmel_ssc_hw_rule_rate, | |
317 | ssc_p, | |
318 | SNDRV_PCM_HW_PARAM_FRAME_BITS, | |
319 | SNDRV_PCM_HW_PARAM_CHANNELS, -1); | |
320 | if (ret < 0) { | |
321 | dev_err(dai->dev, "Failed to specify rate rule: %d\n", ret); | |
322 | return ret; | |
323 | } | |
324 | ||
e401029e | 325 | dma_params = &ssc_dma_params[pdev->id][dir]; |
01f00d55 BS |
326 | dma_params->ssc = ssc_p->ssc; |
327 | dma_params->substream = substream; | |
328 | ||
329 | ssc_p->dma_params[dir] = dma_params; | |
330 | ||
331 | snd_soc_dai_set_dma_data(dai, substream, dma_params); | |
6c742509 SG |
332 | |
333 | spin_lock_irq(&ssc_p->lock); | |
334 | if (ssc_p->dir_mask & dir_mask) { | |
335 | spin_unlock_irq(&ssc_p->lock); | |
336 | return -EBUSY; | |
337 | } | |
338 | ssc_p->dir_mask |= dir_mask; | |
339 | spin_unlock_irq(&ssc_p->lock); | |
340 | ||
341 | return 0; | |
342 | } | |
343 | ||
344 | /* | |
345 | * Shutdown. Clear DMA parameters and shutdown the SSC if there | |
346 | * are no other substreams open. | |
347 | */ | |
dee89c4d MB |
348 | static void atmel_ssc_shutdown(struct snd_pcm_substream *substream, |
349 | struct snd_soc_dai *dai) | |
6c742509 | 350 | { |
c706f2e5 SW |
351 | struct platform_device *pdev = to_platform_device(dai->dev); |
352 | struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id]; | |
6c742509 SG |
353 | struct atmel_pcm_dma_params *dma_params; |
354 | int dir, dir_mask; | |
355 | ||
356 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
357 | dir = 0; | |
358 | else | |
359 | dir = 1; | |
360 | ||
361 | dma_params = ssc_p->dma_params[dir]; | |
362 | ||
363 | if (dma_params != NULL) { | |
6c742509 SG |
364 | dma_params->ssc = NULL; |
365 | dma_params->substream = NULL; | |
366 | ssc_p->dma_params[dir] = NULL; | |
367 | } | |
368 | ||
369 | dir_mask = 1 << dir; | |
370 | ||
371 | spin_lock_irq(&ssc_p->lock); | |
372 | ssc_p->dir_mask &= ~dir_mask; | |
373 | if (!ssc_p->dir_mask) { | |
374 | if (ssc_p->initialized) { | |
6c742509 SG |
375 | free_irq(ssc_p->ssc->irq, ssc_p); |
376 | ssc_p->initialized = 0; | |
377 | } | |
378 | ||
379 | /* Reset the SSC */ | |
380 | ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST)); | |
381 | /* Clear the SSC dividers */ | |
382 | ssc_p->cmr_div = ssc_p->tcmr_period = ssc_p->rcmr_period = 0; | |
a85787ed | 383 | ssc_p->forced_divider = 0; |
6c742509 SG |
384 | } |
385 | spin_unlock_irq(&ssc_p->lock); | |
cbaadf0f BS |
386 | |
387 | /* Shutdown the SSC clock. */ | |
388 | pr_debug("atmel_ssc_dai: Stopping clock\n"); | |
389 | clk_disable(ssc_p->ssc->clk); | |
6c742509 SG |
390 | } |
391 | ||
392 | ||
393 | /* | |
394 | * Record the DAI format for use in hw_params(). | |
395 | */ | |
396 | static int atmel_ssc_set_dai_fmt(struct snd_soc_dai *cpu_dai, | |
397 | unsigned int fmt) | |
398 | { | |
c706f2e5 SW |
399 | struct platform_device *pdev = to_platform_device(cpu_dai->dev); |
400 | struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id]; | |
6c742509 SG |
401 | |
402 | ssc_p->daifmt = fmt; | |
403 | return 0; | |
404 | } | |
405 | ||
406 | /* | |
407 | * Record SSC clock dividers for use in hw_params(). | |
408 | */ | |
409 | static int atmel_ssc_set_dai_clkdiv(struct snd_soc_dai *cpu_dai, | |
410 | int div_id, int div) | |
411 | { | |
c706f2e5 SW |
412 | struct platform_device *pdev = to_platform_device(cpu_dai->dev); |
413 | struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id]; | |
6c742509 SG |
414 | |
415 | switch (div_id) { | |
416 | case ATMEL_SSC_CMR_DIV: | |
417 | /* | |
418 | * The same master clock divider is used for both | |
419 | * transmit and receive, so if a value has already | |
420 | * been set, it must match this value. | |
421 | */ | |
eb58960e PR |
422 | if (ssc_p->dir_mask != |
423 | (SSC_DIR_MASK_PLAYBACK | SSC_DIR_MASK_CAPTURE)) | |
424 | ssc_p->cmr_div = div; | |
425 | else if (ssc_p->cmr_div == 0) | |
6c742509 SG |
426 | ssc_p->cmr_div = div; |
427 | else | |
428 | if (div != ssc_p->cmr_div) | |
429 | return -EBUSY; | |
a85787ed | 430 | ssc_p->forced_divider |= BIT(ATMEL_SSC_CMR_DIV); |
6c742509 SG |
431 | break; |
432 | ||
433 | case ATMEL_SSC_TCMR_PERIOD: | |
434 | ssc_p->tcmr_period = div; | |
a85787ed | 435 | ssc_p->forced_divider |= BIT(ATMEL_SSC_TCMR_PERIOD); |
6c742509 SG |
436 | break; |
437 | ||
438 | case ATMEL_SSC_RCMR_PERIOD: | |
439 | ssc_p->rcmr_period = div; | |
a85787ed | 440 | ssc_p->forced_divider |= BIT(ATMEL_SSC_RCMR_PERIOD); |
6c742509 SG |
441 | break; |
442 | ||
443 | default: | |
444 | return -EINVAL; | |
445 | } | |
446 | ||
447 | return 0; | |
448 | } | |
449 | ||
a85787ed PR |
450 | /* Is the cpu-dai master of the frame clock? */ |
451 | static int atmel_ssc_cfs(struct atmel_ssc_info *ssc_p) | |
452 | { | |
453 | switch (ssc_p->daifmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
454 | case SND_SOC_DAIFMT_CBM_CFS: | |
455 | case SND_SOC_DAIFMT_CBS_CFS: | |
456 | return 1; | |
457 | } | |
458 | return 0; | |
459 | } | |
460 | ||
461 | /* Is the cpu-dai master of the bit clock? */ | |
462 | static int atmel_ssc_cbs(struct atmel_ssc_info *ssc_p) | |
463 | { | |
464 | switch (ssc_p->daifmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
465 | case SND_SOC_DAIFMT_CBS_CFM: | |
466 | case SND_SOC_DAIFMT_CBS_CFS: | |
467 | return 1; | |
468 | } | |
469 | return 0; | |
470 | } | |
471 | ||
6c742509 SG |
472 | /* |
473 | * Configure the SSC. | |
474 | */ | |
475 | static int atmel_ssc_hw_params(struct snd_pcm_substream *substream, | |
dee89c4d MB |
476 | struct snd_pcm_hw_params *params, |
477 | struct snd_soc_dai *dai) | |
6c742509 | 478 | { |
c706f2e5 SW |
479 | struct platform_device *pdev = to_platform_device(dai->dev); |
480 | int id = pdev->id; | |
6c742509 | 481 | struct atmel_ssc_info *ssc_p = &ssc_info[id]; |
048d4ff8 | 482 | struct ssc_device *ssc = ssc_p->ssc; |
6c742509 SG |
483 | struct atmel_pcm_dma_params *dma_params; |
484 | int dir, channels, bits; | |
485 | u32 tfmr, rfmr, tcmr, rcmr; | |
6c742509 | 486 | int ret; |
dfaf5356 | 487 | int fslen, fslen_ext; |
a85787ed PR |
488 | u32 cmr_div; |
489 | u32 tcmr_period; | |
490 | u32 rcmr_period; | |
6c742509 SG |
491 | |
492 | /* | |
493 | * Currently, there is only one set of dma params for | |
494 | * each direction. If more are added, this code will | |
495 | * have to be changed to select the proper set. | |
496 | */ | |
497 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
498 | dir = 0; | |
499 | else | |
500 | dir = 1; | |
501 | ||
a85787ed PR |
502 | /* |
503 | * If the cpu dai should provide BCLK, but noone has provided the | |
504 | * divider needed for that to work, fall back to something sensible. | |
505 | */ | |
506 | cmr_div = ssc_p->cmr_div; | |
507 | if (!(ssc_p->forced_divider & BIT(ATMEL_SSC_CMR_DIV)) && | |
508 | atmel_ssc_cbs(ssc_p)) { | |
509 | int bclk_rate = snd_soc_params_to_bclk(params); | |
510 | ||
511 | if (bclk_rate < 0) { | |
512 | dev_err(dai->dev, "unable to calculate cmr_div: %d\n", | |
513 | bclk_rate); | |
514 | return bclk_rate; | |
515 | } | |
516 | ||
517 | cmr_div = DIV_ROUND_CLOSEST(ssc_p->mck_rate, 2 * bclk_rate); | |
518 | } | |
519 | ||
520 | /* | |
521 | * If the cpu dai should provide LRCLK, but noone has provided the | |
522 | * dividers needed for that to work, fall back to something sensible. | |
523 | */ | |
524 | tcmr_period = ssc_p->tcmr_period; | |
525 | rcmr_period = ssc_p->rcmr_period; | |
526 | if (atmel_ssc_cfs(ssc_p)) { | |
527 | int frame_size = snd_soc_params_to_frame_size(params); | |
528 | ||
529 | if (frame_size < 0) { | |
530 | dev_err(dai->dev, | |
531 | "unable to calculate tx/rx cmr_period: %d\n", | |
532 | frame_size); | |
533 | return frame_size; | |
534 | } | |
535 | ||
536 | if (!(ssc_p->forced_divider & BIT(ATMEL_SSC_TCMR_PERIOD))) | |
537 | tcmr_period = frame_size / 2 - 1; | |
538 | if (!(ssc_p->forced_divider & BIT(ATMEL_SSC_RCMR_PERIOD))) | |
539 | rcmr_period = frame_size / 2 - 1; | |
540 | } | |
541 | ||
01f00d55 | 542 | dma_params = ssc_p->dma_params[dir]; |
6c742509 SG |
543 | |
544 | channels = params_channels(params); | |
545 | ||
546 | /* | |
547 | * Determine sample size in bits and the PDC increment. | |
548 | */ | |
549 | switch (params_format(params)) { | |
550 | case SNDRV_PCM_FORMAT_S8: | |
551 | bits = 8; | |
552 | dma_params->pdc_xfer_size = 1; | |
553 | break; | |
554 | case SNDRV_PCM_FORMAT_S16_LE: | |
555 | bits = 16; | |
556 | dma_params->pdc_xfer_size = 2; | |
557 | break; | |
558 | case SNDRV_PCM_FORMAT_S24_LE: | |
559 | bits = 24; | |
560 | dma_params->pdc_xfer_size = 4; | |
561 | break; | |
562 | case SNDRV_PCM_FORMAT_S32_LE: | |
563 | bits = 32; | |
564 | dma_params->pdc_xfer_size = 4; | |
565 | break; | |
566 | default: | |
567 | printk(KERN_WARNING "atmel_ssc_dai: unsupported PCM format"); | |
568 | return -EINVAL; | |
569 | } | |
570 | ||
6c742509 SG |
571 | /* |
572 | * Compute SSC register settings. | |
573 | */ | |
574 | switch (ssc_p->daifmt | |
575 | & (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_MASTER_MASK)) { | |
576 | ||
577 | case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS: | |
578 | /* | |
579 | * I2S format, SSC provides BCLK and LRC clocks. | |
580 | * | |
581 | * The SSC transmit and receive clocks are generated | |
582 | * from the MCK divider, and the BCLK signal | |
583 | * is output on the SSC TK line. | |
584 | */ | |
dfaf5356 BS |
585 | |
586 | if (bits > 16 && !ssc->pdata->has_fslen_ext) { | |
587 | dev_err(dai->dev, | |
588 | "sample size %d is too large for SSC device\n", | |
589 | bits); | |
590 | return -EINVAL; | |
591 | } | |
592 | ||
593 | fslen_ext = (bits - 1) / 16; | |
594 | fslen = (bits - 1) % 16; | |
595 | ||
a85787ed | 596 | rcmr = SSC_BF(RCMR_PERIOD, rcmr_period) |
6c742509 SG |
597 | | SSC_BF(RCMR_STTDLY, START_DELAY) |
598 | | SSC_BF(RCMR_START, SSC_START_FALLING_RF) | |
599 | | SSC_BF(RCMR_CKI, SSC_CKI_RISING) | |
600 | | SSC_BF(RCMR_CKO, SSC_CKO_NONE) | |
601 | | SSC_BF(RCMR_CKS, SSC_CKS_DIV); | |
602 | ||
dfaf5356 BS |
603 | rfmr = SSC_BF(RFMR_FSLEN_EXT, fslen_ext) |
604 | | SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE) | |
6c742509 | 605 | | SSC_BF(RFMR_FSOS, SSC_FSOS_NEGATIVE) |
dfaf5356 | 606 | | SSC_BF(RFMR_FSLEN, fslen) |
6c742509 SG |
607 | | SSC_BF(RFMR_DATNB, (channels - 1)) |
608 | | SSC_BIT(RFMR_MSBF) | |
609 | | SSC_BF(RFMR_LOOP, 0) | |
610 | | SSC_BF(RFMR_DATLEN, (bits - 1)); | |
611 | ||
a85787ed | 612 | tcmr = SSC_BF(TCMR_PERIOD, tcmr_period) |
6c742509 SG |
613 | | SSC_BF(TCMR_STTDLY, START_DELAY) |
614 | | SSC_BF(TCMR_START, SSC_START_FALLING_RF) | |
615 | | SSC_BF(TCMR_CKI, SSC_CKI_FALLING) | |
616 | | SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS) | |
617 | | SSC_BF(TCMR_CKS, SSC_CKS_DIV); | |
618 | ||
dfaf5356 BS |
619 | tfmr = SSC_BF(TFMR_FSLEN_EXT, fslen_ext) |
620 | | SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE) | |
6c742509 SG |
621 | | SSC_BF(TFMR_FSDEN, 0) |
622 | | SSC_BF(TFMR_FSOS, SSC_FSOS_NEGATIVE) | |
dfaf5356 | 623 | | SSC_BF(TFMR_FSLEN, fslen) |
6c742509 SG |
624 | | SSC_BF(TFMR_DATNB, (channels - 1)) |
625 | | SSC_BIT(TFMR_MSBF) | |
626 | | SSC_BF(TFMR_DATDEF, 0) | |
627 | | SSC_BF(TFMR_DATLEN, (bits - 1)); | |
628 | break; | |
629 | ||
630 | case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM: | |
67d1aed0 | 631 | /* I2S format, CODEC supplies BCLK and LRC clocks. */ |
6c742509 SG |
632 | rcmr = SSC_BF(RCMR_PERIOD, 0) |
633 | | SSC_BF(RCMR_STTDLY, START_DELAY) | |
a43bd7e1 | 634 | | SSC_BF(RCMR_START, SSC_START_FALLING_RF) |
6c742509 SG |
635 | | SSC_BF(RCMR_CKI, SSC_CKI_RISING) |
636 | | SSC_BF(RCMR_CKO, SSC_CKO_NONE) | |
048d4ff8 BS |
637 | | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ? |
638 | SSC_CKS_PIN : SSC_CKS_CLOCK); | |
6c742509 SG |
639 | |
640 | rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE) | |
641 | | SSC_BF(RFMR_FSOS, SSC_FSOS_NONE) | |
642 | | SSC_BF(RFMR_FSLEN, 0) | |
a43bd7e1 | 643 | | SSC_BF(RFMR_DATNB, (channels - 1)) |
6c742509 SG |
644 | | SSC_BIT(RFMR_MSBF) |
645 | | SSC_BF(RFMR_LOOP, 0) | |
646 | | SSC_BF(RFMR_DATLEN, (bits - 1)); | |
647 | ||
648 | tcmr = SSC_BF(TCMR_PERIOD, 0) | |
649 | | SSC_BF(TCMR_STTDLY, START_DELAY) | |
a43bd7e1 | 650 | | SSC_BF(TCMR_START, SSC_START_FALLING_RF) |
6c742509 SG |
651 | | SSC_BF(TCMR_CKI, SSC_CKI_FALLING) |
652 | | SSC_BF(TCMR_CKO, SSC_CKO_NONE) | |
048d4ff8 BS |
653 | | SSC_BF(TCMR_CKS, ssc->clk_from_rk_pin ? |
654 | SSC_CKS_CLOCK : SSC_CKS_PIN); | |
6c742509 SG |
655 | |
656 | tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE) | |
657 | | SSC_BF(TFMR_FSDEN, 0) | |
658 | | SSC_BF(TFMR_FSOS, SSC_FSOS_NONE) | |
659 | | SSC_BF(TFMR_FSLEN, 0) | |
a43bd7e1 | 660 | | SSC_BF(TFMR_DATNB, (channels - 1)) |
6c742509 SG |
661 | | SSC_BIT(TFMR_MSBF) |
662 | | SSC_BF(TFMR_DATDEF, 0) | |
663 | | SSC_BF(TFMR_DATLEN, (bits - 1)); | |
664 | break; | |
665 | ||
eb527149 PR |
666 | case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFS: |
667 | /* I2S format, CODEC supplies BCLK, SSC supplies LRCLK. */ | |
668 | if (bits > 16 && !ssc->pdata->has_fslen_ext) { | |
669 | dev_err(dai->dev, | |
670 | "sample size %d is too large for SSC device\n", | |
671 | bits); | |
672 | return -EINVAL; | |
673 | } | |
674 | ||
675 | fslen_ext = (bits - 1) / 16; | |
676 | fslen = (bits - 1) % 16; | |
677 | ||
a85787ed | 678 | rcmr = SSC_BF(RCMR_PERIOD, rcmr_period) |
eb527149 PR |
679 | | SSC_BF(RCMR_STTDLY, START_DELAY) |
680 | | SSC_BF(RCMR_START, SSC_START_FALLING_RF) | |
681 | | SSC_BF(RCMR_CKI, SSC_CKI_RISING) | |
682 | | SSC_BF(RCMR_CKO, SSC_CKO_NONE) | |
683 | | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ? | |
684 | SSC_CKS_PIN : SSC_CKS_CLOCK); | |
685 | ||
686 | rfmr = SSC_BF(RFMR_FSLEN_EXT, fslen_ext) | |
687 | | SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE) | |
688 | | SSC_BF(RFMR_FSOS, SSC_FSOS_NEGATIVE) | |
689 | | SSC_BF(RFMR_FSLEN, fslen) | |
690 | | SSC_BF(RFMR_DATNB, (channels - 1)) | |
691 | | SSC_BIT(RFMR_MSBF) | |
692 | | SSC_BF(RFMR_LOOP, 0) | |
693 | | SSC_BF(RFMR_DATLEN, (bits - 1)); | |
694 | ||
a85787ed | 695 | tcmr = SSC_BF(TCMR_PERIOD, tcmr_period) |
eb527149 PR |
696 | | SSC_BF(TCMR_STTDLY, START_DELAY) |
697 | | SSC_BF(TCMR_START, SSC_START_FALLING_RF) | |
698 | | SSC_BF(TCMR_CKI, SSC_CKI_FALLING) | |
699 | | SSC_BF(TCMR_CKO, SSC_CKO_NONE) | |
700 | | SSC_BF(TCMR_CKS, ssc->clk_from_rk_pin ? | |
701 | SSC_CKS_CLOCK : SSC_CKS_PIN); | |
702 | ||
703 | tfmr = SSC_BF(TFMR_FSLEN_EXT, fslen_ext) | |
704 | | SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_NEGATIVE) | |
705 | | SSC_BF(TFMR_FSDEN, 0) | |
706 | | SSC_BF(TFMR_FSOS, SSC_FSOS_NEGATIVE) | |
707 | | SSC_BF(TFMR_FSLEN, fslen) | |
708 | | SSC_BF(TFMR_DATNB, (channels - 1)) | |
6c742509 SG |
709 | | SSC_BIT(TFMR_MSBF) |
710 | | SSC_BF(TFMR_DATDEF, 0) | |
711 | | SSC_BF(TFMR_DATLEN, (bits - 1)); | |
712 | break; | |
713 | ||
714 | case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBS_CFS: | |
715 | /* | |
716 | * DSP/PCM Mode A format, SSC provides BCLK and LRC clocks. | |
717 | * | |
718 | * The SSC transmit and receive clocks are generated from the | |
719 | * MCK divider, and the BCLK signal is output | |
720 | * on the SSC TK line. | |
721 | */ | |
a85787ed | 722 | rcmr = SSC_BF(RCMR_PERIOD, rcmr_period) |
6c742509 SG |
723 | | SSC_BF(RCMR_STTDLY, 1) |
724 | | SSC_BF(RCMR_START, SSC_START_RISING_RF) | |
80833ff0 | 725 | | SSC_BF(RCMR_CKI, SSC_CKI_RISING) |
6c742509 SG |
726 | | SSC_BF(RCMR_CKO, SSC_CKO_NONE) |
727 | | SSC_BF(RCMR_CKS, SSC_CKS_DIV); | |
728 | ||
729 | rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE) | |
730 | | SSC_BF(RFMR_FSOS, SSC_FSOS_POSITIVE) | |
731 | | SSC_BF(RFMR_FSLEN, 0) | |
732 | | SSC_BF(RFMR_DATNB, (channels - 1)) | |
733 | | SSC_BIT(RFMR_MSBF) | |
734 | | SSC_BF(RFMR_LOOP, 0) | |
735 | | SSC_BF(RFMR_DATLEN, (bits - 1)); | |
736 | ||
a85787ed | 737 | tcmr = SSC_BF(TCMR_PERIOD, tcmr_period) |
6c742509 SG |
738 | | SSC_BF(TCMR_STTDLY, 1) |
739 | | SSC_BF(TCMR_START, SSC_START_RISING_RF) | |
20cf2603 | 740 | | SSC_BF(TCMR_CKI, SSC_CKI_FALLING) |
6c742509 SG |
741 | | SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS) |
742 | | SSC_BF(TCMR_CKS, SSC_CKS_DIV); | |
743 | ||
744 | tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE) | |
745 | | SSC_BF(TFMR_FSDEN, 0) | |
746 | | SSC_BF(TFMR_FSOS, SSC_FSOS_POSITIVE) | |
747 | | SSC_BF(TFMR_FSLEN, 0) | |
748 | | SSC_BF(TFMR_DATNB, (channels - 1)) | |
749 | | SSC_BIT(TFMR_MSBF) | |
750 | | SSC_BF(TFMR_DATDEF, 0) | |
751 | | SSC_BF(TFMR_DATLEN, (bits - 1)); | |
752 | break; | |
753 | ||
754 | case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBM_CFM: | |
f6a75d95 ZP |
755 | /* |
756 | * DSP/PCM Mode A format, CODEC supplies BCLK and LRC clocks. | |
757 | * | |
f6a75d95 ZP |
758 | * Data is transferred on first BCLK after LRC pulse rising |
759 | * edge.If stereo, the right channel data is contiguous with | |
760 | * the left channel data. | |
761 | */ | |
762 | rcmr = SSC_BF(RCMR_PERIOD, 0) | |
763 | | SSC_BF(RCMR_STTDLY, START_DELAY) | |
764 | | SSC_BF(RCMR_START, SSC_START_RISING_RF) | |
80833ff0 | 765 | | SSC_BF(RCMR_CKI, SSC_CKI_RISING) |
f6a75d95 | 766 | | SSC_BF(RCMR_CKO, SSC_CKO_NONE) |
048d4ff8 BS |
767 | | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ? |
768 | SSC_CKS_PIN : SSC_CKS_CLOCK); | |
f6a75d95 ZP |
769 | |
770 | rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE) | |
771 | | SSC_BF(RFMR_FSOS, SSC_FSOS_NONE) | |
772 | | SSC_BF(RFMR_FSLEN, 0) | |
773 | | SSC_BF(RFMR_DATNB, (channels - 1)) | |
774 | | SSC_BIT(RFMR_MSBF) | |
775 | | SSC_BF(RFMR_LOOP, 0) | |
776 | | SSC_BF(RFMR_DATLEN, (bits - 1)); | |
777 | ||
778 | tcmr = SSC_BF(TCMR_PERIOD, 0) | |
779 | | SSC_BF(TCMR_STTDLY, START_DELAY) | |
780 | | SSC_BF(TCMR_START, SSC_START_RISING_RF) | |
781 | | SSC_BF(TCMR_CKI, SSC_CKI_FALLING) | |
782 | | SSC_BF(TCMR_CKO, SSC_CKO_NONE) | |
048d4ff8 BS |
783 | | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ? |
784 | SSC_CKS_CLOCK : SSC_CKS_PIN); | |
f6a75d95 ZP |
785 | |
786 | tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE) | |
787 | | SSC_BF(TFMR_FSDEN, 0) | |
788 | | SSC_BF(TFMR_FSOS, SSC_FSOS_NONE) | |
789 | | SSC_BF(TFMR_FSLEN, 0) | |
790 | | SSC_BF(TFMR_DATNB, (channels - 1)) | |
791 | | SSC_BIT(TFMR_MSBF) | |
792 | | SSC_BF(TFMR_DATDEF, 0) | |
793 | | SSC_BF(TFMR_DATLEN, (bits - 1)); | |
794 | break; | |
795 | ||
6c742509 SG |
796 | default: |
797 | printk(KERN_WARNING "atmel_ssc_dai: unsupported DAI format 0x%x\n", | |
798 | ssc_p->daifmt); | |
799 | return -EINVAL; | |
6c742509 SG |
800 | } |
801 | pr_debug("atmel_ssc_hw_params: " | |
802 | "RCMR=%08x RFMR=%08x TCMR=%08x TFMR=%08x\n", | |
803 | rcmr, rfmr, tcmr, tfmr); | |
804 | ||
805 | if (!ssc_p->initialized) { | |
3fd5b30c BS |
806 | if (!ssc_p->ssc->pdata->use_dma) { |
807 | ssc_writel(ssc_p->ssc->regs, PDC_RPR, 0); | |
808 | ssc_writel(ssc_p->ssc->regs, PDC_RCR, 0); | |
809 | ssc_writel(ssc_p->ssc->regs, PDC_RNPR, 0); | |
810 | ssc_writel(ssc_p->ssc->regs, PDC_RNCR, 0); | |
811 | ||
812 | ssc_writel(ssc_p->ssc->regs, PDC_TPR, 0); | |
813 | ssc_writel(ssc_p->ssc->regs, PDC_TCR, 0); | |
814 | ssc_writel(ssc_p->ssc->regs, PDC_TNPR, 0); | |
815 | ssc_writel(ssc_p->ssc->regs, PDC_TNCR, 0); | |
816 | } | |
6c742509 SG |
817 | |
818 | ret = request_irq(ssc_p->ssc->irq, atmel_ssc_interrupt, 0, | |
819 | ssc_p->name, ssc_p); | |
820 | if (ret < 0) { | |
821 | printk(KERN_WARNING | |
822 | "atmel_ssc_dai: request_irq failure\n"); | |
7bdeac2e | 823 | pr_debug("Atmel_ssc_dai: Stopping clock\n"); |
6c742509 SG |
824 | clk_disable(ssc_p->ssc->clk); |
825 | return ret; | |
826 | } | |
827 | ||
828 | ssc_p->initialized = 1; | |
829 | } | |
830 | ||
831 | /* set SSC clock mode register */ | |
a85787ed | 832 | ssc_writel(ssc_p->ssc->regs, CMR, cmr_div); |
6c742509 SG |
833 | |
834 | /* set receive clock mode and format */ | |
835 | ssc_writel(ssc_p->ssc->regs, RCMR, rcmr); | |
836 | ssc_writel(ssc_p->ssc->regs, RFMR, rfmr); | |
837 | ||
838 | /* set transmit clock mode and format */ | |
839 | ssc_writel(ssc_p->ssc->regs, TCMR, tcmr); | |
840 | ssc_writel(ssc_p->ssc->regs, TFMR, tfmr); | |
841 | ||
842 | pr_debug("atmel_ssc_dai,hw_params: SSC initialized\n"); | |
843 | return 0; | |
844 | } | |
845 | ||
846 | ||
dee89c4d MB |
847 | static int atmel_ssc_prepare(struct snd_pcm_substream *substream, |
848 | struct snd_soc_dai *dai) | |
6c742509 | 849 | { |
c706f2e5 SW |
850 | struct platform_device *pdev = to_platform_device(dai->dev); |
851 | struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id]; | |
6c742509 SG |
852 | struct atmel_pcm_dma_params *dma_params; |
853 | int dir; | |
854 | ||
855 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
856 | dir = 0; | |
857 | else | |
858 | dir = 1; | |
859 | ||
860 | dma_params = ssc_p->dma_params[dir]; | |
861 | ||
a8f1f100 | 862 | ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable); |
e0111434 | 863 | ssc_writel(ssc_p->ssc->regs, IDR, dma_params->mask->ssc_error); |
6c742509 SG |
864 | |
865 | pr_debug("%s enabled SSC_SR=0x%08x\n", | |
866 | dir ? "receive" : "transmit", | |
867 | ssc_readl(ssc_p->ssc->regs, SR)); | |
868 | return 0; | |
869 | } | |
870 | ||
a8f1f100 BS |
871 | static int atmel_ssc_trigger(struct snd_pcm_substream *substream, |
872 | int cmd, struct snd_soc_dai *dai) | |
873 | { | |
c706f2e5 SW |
874 | struct platform_device *pdev = to_platform_device(dai->dev); |
875 | struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id]; | |
a8f1f100 BS |
876 | struct atmel_pcm_dma_params *dma_params; |
877 | int dir; | |
878 | ||
879 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
880 | dir = 0; | |
881 | else | |
882 | dir = 1; | |
883 | ||
884 | dma_params = ssc_p->dma_params[dir]; | |
885 | ||
886 | switch (cmd) { | |
887 | case SNDRV_PCM_TRIGGER_START: | |
888 | case SNDRV_PCM_TRIGGER_RESUME: | |
889 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
890 | ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_enable); | |
891 | break; | |
892 | default: | |
893 | ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable); | |
894 | break; | |
895 | } | |
896 | ||
897 | return 0; | |
898 | } | |
6c742509 SG |
899 | |
900 | #ifdef CONFIG_PM | |
dc7d7b83 | 901 | static int atmel_ssc_suspend(struct snd_soc_dai *cpu_dai) |
6c742509 SG |
902 | { |
903 | struct atmel_ssc_info *ssc_p; | |
c706f2e5 | 904 | struct platform_device *pdev = to_platform_device(cpu_dai->dev); |
6c742509 SG |
905 | |
906 | if (!cpu_dai->active) | |
907 | return 0; | |
908 | ||
c706f2e5 | 909 | ssc_p = &ssc_info[pdev->id]; |
6c742509 SG |
910 | |
911 | /* Save the status register before disabling transmit and receive */ | |
912 | ssc_p->ssc_state.ssc_sr = ssc_readl(ssc_p->ssc->regs, SR); | |
913 | ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_TXDIS) | SSC_BIT(CR_RXDIS)); | |
914 | ||
915 | /* Save the current interrupt mask, then disable unmasked interrupts */ | |
916 | ssc_p->ssc_state.ssc_imr = ssc_readl(ssc_p->ssc->regs, IMR); | |
917 | ssc_writel(ssc_p->ssc->regs, IDR, ssc_p->ssc_state.ssc_imr); | |
918 | ||
919 | ssc_p->ssc_state.ssc_cmr = ssc_readl(ssc_p->ssc->regs, CMR); | |
920 | ssc_p->ssc_state.ssc_rcmr = ssc_readl(ssc_p->ssc->regs, RCMR); | |
921 | ssc_p->ssc_state.ssc_rfmr = ssc_readl(ssc_p->ssc->regs, RFMR); | |
922 | ssc_p->ssc_state.ssc_tcmr = ssc_readl(ssc_p->ssc->regs, TCMR); | |
923 | ssc_p->ssc_state.ssc_tfmr = ssc_readl(ssc_p->ssc->regs, TFMR); | |
924 | ||
925 | return 0; | |
926 | } | |
927 | ||
928 | ||
929 | ||
dc7d7b83 | 930 | static int atmel_ssc_resume(struct snd_soc_dai *cpu_dai) |
6c742509 SG |
931 | { |
932 | struct atmel_ssc_info *ssc_p; | |
c706f2e5 | 933 | struct platform_device *pdev = to_platform_device(cpu_dai->dev); |
6c742509 SG |
934 | u32 cr; |
935 | ||
936 | if (!cpu_dai->active) | |
937 | return 0; | |
938 | ||
c706f2e5 | 939 | ssc_p = &ssc_info[pdev->id]; |
6c742509 SG |
940 | |
941 | /* restore SSC register settings */ | |
942 | ssc_writel(ssc_p->ssc->regs, TFMR, ssc_p->ssc_state.ssc_tfmr); | |
943 | ssc_writel(ssc_p->ssc->regs, TCMR, ssc_p->ssc_state.ssc_tcmr); | |
944 | ssc_writel(ssc_p->ssc->regs, RFMR, ssc_p->ssc_state.ssc_rfmr); | |
945 | ssc_writel(ssc_p->ssc->regs, RCMR, ssc_p->ssc_state.ssc_rcmr); | |
946 | ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->ssc_state.ssc_cmr); | |
947 | ||
948 | /* re-enable interrupts */ | |
949 | ssc_writel(ssc_p->ssc->regs, IER, ssc_p->ssc_state.ssc_imr); | |
950 | ||
25985edc | 951 | /* Re-enable receive and transmit as appropriate */ |
6c742509 SG |
952 | cr = 0; |
953 | cr |= | |
954 | (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_RXEN)) ? SSC_BIT(CR_RXEN) : 0; | |
955 | cr |= | |
956 | (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_TXEN)) ? SSC_BIT(CR_TXEN) : 0; | |
957 | ssc_writel(ssc_p->ssc->regs, CR, cr); | |
958 | ||
959 | return 0; | |
960 | } | |
961 | #else /* CONFIG_PM */ | |
962 | # define atmel_ssc_suspend NULL | |
963 | # define atmel_ssc_resume NULL | |
964 | #endif /* CONFIG_PM */ | |
965 | ||
6c742509 SG |
966 | #define ATMEL_SSC_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\ |
967 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) | |
968 | ||
85e7652d | 969 | static const struct snd_soc_dai_ops atmel_ssc_dai_ops = { |
6335d055 EM |
970 | .startup = atmel_ssc_startup, |
971 | .shutdown = atmel_ssc_shutdown, | |
972 | .prepare = atmel_ssc_prepare, | |
a8f1f100 | 973 | .trigger = atmel_ssc_trigger, |
6335d055 EM |
974 | .hw_params = atmel_ssc_hw_params, |
975 | .set_fmt = atmel_ssc_set_dai_fmt, | |
976 | .set_clkdiv = atmel_ssc_set_dai_clkdiv, | |
977 | }; | |
978 | ||
be681a82 | 979 | static struct snd_soc_dai_driver atmel_ssc_dai = { |
6c742509 SG |
980 | .suspend = atmel_ssc_suspend, |
981 | .resume = atmel_ssc_resume, | |
982 | .playback = { | |
983 | .channels_min = 1, | |
984 | .channels_max = 2, | |
b6d6c6e9 PR |
985 | .rates = SNDRV_PCM_RATE_CONTINUOUS, |
986 | .rate_min = 8000, | |
987 | .rate_max = 384000, | |
6c742509 SG |
988 | .formats = ATMEL_SSC_FORMATS,}, |
989 | .capture = { | |
990 | .channels_min = 1, | |
991 | .channels_max = 2, | |
b6d6c6e9 PR |
992 | .rates = SNDRV_PCM_RATE_CONTINUOUS, |
993 | .rate_min = 8000, | |
994 | .rate_max = 384000, | |
6c742509 | 995 | .formats = ATMEL_SSC_FORMATS,}, |
6335d055 | 996 | .ops = &atmel_ssc_dai_ops, |
6c742509 | 997 | }; |
6c742509 | 998 | |
a2c662c0 KM |
999 | static const struct snd_soc_component_driver atmel_ssc_component = { |
1000 | .name = "atmel-ssc", | |
1001 | }; | |
1002 | ||
be681a82 | 1003 | static int asoc_ssc_init(struct device *dev) |
f0fba2ad | 1004 | { |
c0380478 | 1005 | struct ssc_device *ssc = dev_get_drvdata(dev); |
be681a82 BS |
1006 | int ret; |
1007 | ||
e14614dc | 1008 | ret = devm_snd_soc_register_component(dev, &atmel_ssc_component, |
a2c662c0 | 1009 | &atmel_ssc_dai, 1); |
be681a82 BS |
1010 | if (ret) { |
1011 | dev_err(dev, "Could not register DAI: %d\n", ret); | |
e14614dc | 1012 | return ret; |
be681a82 BS |
1013 | } |
1014 | ||
3951e4aa BS |
1015 | if (ssc->pdata->use_dma) |
1016 | ret = atmel_pcm_dma_platform_register(dev); | |
1017 | else | |
1018 | ret = atmel_pcm_pdc_platform_register(dev); | |
1019 | ||
be681a82 BS |
1020 | if (ret) { |
1021 | dev_err(dev, "Could not register PCM: %d\n", ret); | |
e14614dc | 1022 | return ret; |
1d198f26 | 1023 | } |
f0fba2ad | 1024 | |
f0fba2ad | 1025 | return 0; |
be681a82 | 1026 | } |
f0fba2ad | 1027 | |
be681a82 BS |
1028 | static void asoc_ssc_exit(struct device *dev) |
1029 | { | |
c0380478 | 1030 | struct ssc_device *ssc = dev_get_drvdata(dev); |
3951e4aa BS |
1031 | |
1032 | if (ssc->pdata->use_dma) | |
1033 | atmel_pcm_dma_platform_unregister(dev); | |
1034 | else | |
1035 | atmel_pcm_pdc_platform_unregister(dev); | |
be681a82 | 1036 | } |
f0fba2ad | 1037 | |
abfa4eae MB |
1038 | /** |
1039 | * atmel_ssc_set_audio - Allocate the specified SSC for audio use. | |
1040 | */ | |
1041 | int atmel_ssc_set_audio(int ssc_id) | |
1042 | { | |
1043 | struct ssc_device *ssc; | |
abfa4eae MB |
1044 | int ret; |
1045 | ||
abfa4eae MB |
1046 | /* If we can grab the SSC briefly to parent the DAI device off it */ |
1047 | ssc = ssc_request(ssc_id); | |
be681a82 BS |
1048 | if (IS_ERR(ssc)) { |
1049 | pr_err("Unable to parent ASoC SSC DAI on SSC: %ld\n", | |
abfa4eae | 1050 | PTR_ERR(ssc)); |
be681a82 BS |
1051 | return PTR_ERR(ssc); |
1052 | } else { | |
1053 | ssc_info[ssc_id].ssc = ssc; | |
840d8e5e | 1054 | } |
abfa4eae | 1055 | |
be681a82 | 1056 | ret = asoc_ssc_init(&ssc->pdev->dev); |
abfa4eae MB |
1057 | |
1058 | return ret; | |
1059 | } | |
1060 | EXPORT_SYMBOL_GPL(atmel_ssc_set_audio); | |
1061 | ||
be681a82 BS |
1062 | void atmel_ssc_put_audio(int ssc_id) |
1063 | { | |
1064 | struct ssc_device *ssc = ssc_info[ssc_id].ssc; | |
1065 | ||
be681a82 | 1066 | asoc_ssc_exit(&ssc->pdev->dev); |
69706028 | 1067 | ssc_free(ssc); |
be681a82 BS |
1068 | } |
1069 | EXPORT_SYMBOL_GPL(atmel_ssc_put_audio); | |
3f4b783c | 1070 | |
6c742509 SG |
1071 | /* Module information */ |
1072 | MODULE_AUTHOR("Sedji Gaouaou, sedji.gaouaou@atmel.com, www.atmel.com"); | |
1073 | MODULE_DESCRIPTION("ATMEL SSC ASoC Interface"); | |
1074 | MODULE_LICENSE("GPL"); |