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2025cf9e | 1 | // SPDX-License-Identifier: GPL-2.0-only |
7c31335a MSB |
2 | /* |
3 | * AMD ALSA SoC PCM Driver for ACP 2.x | |
4 | * | |
5 | * Copyright 2014-2015 Advanced Micro Devices, Inc. | |
7c31335a MSB |
6 | */ |
7 | ||
8 | #include <linux/module.h> | |
9 | #include <linux/delay.h> | |
7cb1dc81 | 10 | #include <linux/io.h> |
2a665dba | 11 | #include <linux/iopoll.h> |
7c31335a | 12 | #include <linux/sizes.h> |
1927da93 | 13 | #include <linux/pm_runtime.h> |
7c31335a MSB |
14 | |
15 | #include <sound/soc.h> | |
607b39ef | 16 | #include <drm/amd_asic_type.h> |
7c31335a MSB |
17 | #include "acp.h" |
18 | ||
a1042a42 KM |
19 | #define DRV_NAME "acp_audio_dma" |
20 | ||
7c31335a MSB |
21 | #define PLAYBACK_MIN_NUM_PERIODS 2 |
22 | #define PLAYBACK_MAX_NUM_PERIODS 2 | |
23 | #define PLAYBACK_MAX_PERIOD_SIZE 16384 | |
24 | #define PLAYBACK_MIN_PERIOD_SIZE 1024 | |
25 | #define CAPTURE_MIN_NUM_PERIODS 2 | |
26 | #define CAPTURE_MAX_NUM_PERIODS 2 | |
27 | #define CAPTURE_MAX_PERIOD_SIZE 16384 | |
28 | #define CAPTURE_MIN_PERIOD_SIZE 1024 | |
29 | ||
30 | #define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS) | |
31 | #define MIN_BUFFER MAX_BUFFER | |
32 | ||
ccfbb4f5 | 33 | #define ST_PLAYBACK_MAX_PERIOD_SIZE 4096 |
9c7d6fab VM |
34 | #define ST_CAPTURE_MAX_PERIOD_SIZE ST_PLAYBACK_MAX_PERIOD_SIZE |
35 | #define ST_MAX_BUFFER (ST_PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS) | |
36 | #define ST_MIN_BUFFER ST_MAX_BUFFER | |
37 | ||
bdd2a858 | 38 | #define DRV_NAME "acp_audio_dma" |
ccfbb4f5 MV |
39 | bool bt_uart_enable = true; |
40 | EXPORT_SYMBOL(bt_uart_enable); | |
bdd2a858 | 41 | |
7c31335a MSB |
42 | static const struct snd_pcm_hardware acp_pcm_hardware_playback = { |
43 | .info = SNDRV_PCM_INFO_INTERLEAVED | | |
44 | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | | |
45 | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | | |
46 | SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, | |
47 | .formats = SNDRV_PCM_FMTBIT_S16_LE | | |
48 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, | |
49 | .channels_min = 1, | |
50 | .channels_max = 8, | |
51 | .rates = SNDRV_PCM_RATE_8000_96000, | |
52 | .rate_min = 8000, | |
53 | .rate_max = 96000, | |
54 | .buffer_bytes_max = PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE, | |
55 | .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE, | |
56 | .period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE, | |
57 | .periods_min = PLAYBACK_MIN_NUM_PERIODS, | |
58 | .periods_max = PLAYBACK_MAX_NUM_PERIODS, | |
59 | }; | |
60 | ||
61 | static const struct snd_pcm_hardware acp_pcm_hardware_capture = { | |
62 | .info = SNDRV_PCM_INFO_INTERLEAVED | | |
63 | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | | |
64 | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | | |
65 | SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, | |
66 | .formats = SNDRV_PCM_FMTBIT_S16_LE | | |
67 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, | |
68 | .channels_min = 1, | |
69 | .channels_max = 2, | |
70 | .rates = SNDRV_PCM_RATE_8000_48000, | |
71 | .rate_min = 8000, | |
72 | .rate_max = 48000, | |
73 | .buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE, | |
74 | .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE, | |
75 | .period_bytes_max = CAPTURE_MAX_PERIOD_SIZE, | |
76 | .periods_min = CAPTURE_MIN_NUM_PERIODS, | |
77 | .periods_max = CAPTURE_MAX_NUM_PERIODS, | |
78 | }; | |
79 | ||
9c7d6fab VM |
80 | static const struct snd_pcm_hardware acp_st_pcm_hardware_playback = { |
81 | .info = SNDRV_PCM_INFO_INTERLEAVED | | |
82 | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | | |
83 | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | | |
84 | SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, | |
85 | .formats = SNDRV_PCM_FMTBIT_S16_LE | | |
86 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, | |
87 | .channels_min = 1, | |
88 | .channels_max = 8, | |
89 | .rates = SNDRV_PCM_RATE_8000_96000, | |
90 | .rate_min = 8000, | |
91 | .rate_max = 96000, | |
92 | .buffer_bytes_max = ST_MAX_BUFFER, | |
93 | .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE, | |
94 | .period_bytes_max = ST_PLAYBACK_MAX_PERIOD_SIZE, | |
95 | .periods_min = PLAYBACK_MIN_NUM_PERIODS, | |
96 | .periods_max = PLAYBACK_MAX_NUM_PERIODS, | |
97 | }; | |
98 | ||
99 | static const struct snd_pcm_hardware acp_st_pcm_hardware_capture = { | |
100 | .info = SNDRV_PCM_INFO_INTERLEAVED | | |
101 | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | | |
102 | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | | |
103 | SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, | |
104 | .formats = SNDRV_PCM_FMTBIT_S16_LE | | |
105 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, | |
106 | .channels_min = 1, | |
107 | .channels_max = 2, | |
108 | .rates = SNDRV_PCM_RATE_8000_48000, | |
109 | .rate_min = 8000, | |
110 | .rate_max = 48000, | |
111 | .buffer_bytes_max = ST_MAX_BUFFER, | |
112 | .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE, | |
113 | .period_bytes_max = ST_CAPTURE_MAX_PERIOD_SIZE, | |
114 | .periods_min = CAPTURE_MIN_NUM_PERIODS, | |
115 | .periods_max = CAPTURE_MAX_NUM_PERIODS, | |
116 | }; | |
117 | ||
7c31335a MSB |
118 | static u32 acp_reg_read(void __iomem *acp_mmio, u32 reg) |
119 | { | |
120 | return readl(acp_mmio + (reg * 4)); | |
121 | } | |
122 | ||
123 | static void acp_reg_write(u32 val, void __iomem *acp_mmio, u32 reg) | |
124 | { | |
125 | writel(val, acp_mmio + (reg * 4)); | |
126 | } | |
127 | ||
13838c11 MV |
128 | /* |
129 | * Configure a given dma channel parameters - enable/disable, | |
7c31335a MSB |
130 | * number of descriptors, priority |
131 | */ | |
132 | static void config_acp_dma_channel(void __iomem *acp_mmio, u8 ch_num, | |
133 | u16 dscr_strt_idx, u16 num_dscrs, | |
134 | enum acp_dma_priority_level priority_level) | |
135 | { | |
136 | u32 dma_ctrl; | |
137 | ||
138 | /* disable the channel run field */ | |
139 | dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); | |
140 | dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK; | |
141 | acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); | |
142 | ||
143 | /* program a DMA channel with first descriptor to be processed. */ | |
144 | acp_reg_write((ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx_MASK | |
145 | & dscr_strt_idx), | |
146 | acp_mmio, mmACP_DMA_DSCR_STRT_IDX_0 + ch_num); | |
147 | ||
13838c11 MV |
148 | /* |
149 | * program a DMA channel with the number of descriptors to be | |
7c31335a | 150 | * processed in the transfer |
13838c11 | 151 | */ |
7c31335a | 152 | acp_reg_write(ACP_DMA_DSCR_CNT_0__DMAChDscrCnt_MASK & num_dscrs, |
13838c11 | 153 | acp_mmio, mmACP_DMA_DSCR_CNT_0 + ch_num); |
7c31335a MSB |
154 | |
155 | /* set DMA channel priority */ | |
156 | acp_reg_write(priority_level, acp_mmio, mmACP_DMA_PRIO_0 + ch_num); | |
157 | } | |
158 | ||
159 | /* Initialize a dma descriptor in SRAM based on descritor information passed */ | |
160 | static void config_dma_descriptor_in_sram(void __iomem *acp_mmio, | |
161 | u16 descr_idx, | |
162 | acp_dma_dscr_transfer_t *descr_info) | |
163 | { | |
164 | u32 sram_offset; | |
165 | ||
166 | sram_offset = (descr_idx * sizeof(acp_dma_dscr_transfer_t)); | |
167 | ||
168 | /* program the source base address. */ | |
169 | acp_reg_write(sram_offset, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); | |
170 | acp_reg_write(descr_info->src, acp_mmio, mmACP_SRBM_Targ_Idx_Data); | |
171 | /* program the destination base address. */ | |
172 | acp_reg_write(sram_offset + 4, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); | |
173 | acp_reg_write(descr_info->dest, acp_mmio, mmACP_SRBM_Targ_Idx_Data); | |
174 | ||
175 | /* program the number of bytes to be transferred for this descriptor. */ | |
176 | acp_reg_write(sram_offset + 8, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); | |
177 | acp_reg_write(descr_info->xfer_val, acp_mmio, mmACP_SRBM_Targ_Idx_Data); | |
178 | } | |
179 | ||
2a665dba AA |
180 | static void pre_config_reset(void __iomem *acp_mmio, u16 ch_num) |
181 | { | |
182 | u32 dma_ctrl; | |
183 | int ret; | |
184 | ||
185 | /* clear the reset bit */ | |
186 | dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); | |
187 | dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK; | |
188 | acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); | |
189 | /* check the reset bit before programming configuration registers */ | |
190 | ret = readl_poll_timeout(acp_mmio + ((mmACP_DMA_CNTL_0 + ch_num) * 4), | |
191 | dma_ctrl, | |
192 | !(dma_ctrl & ACP_DMA_CNTL_0__DMAChRst_MASK), | |
193 | 100, ACP_DMA_RESET_TIME); | |
194 | if (ret < 0) | |
195 | pr_err("Failed to clear reset of channel : %d\n", ch_num); | |
196 | } | |
197 | ||
13838c11 MV |
198 | /* |
199 | * Initialize the DMA descriptor information for transfer between | |
7c31335a MSB |
200 | * system memory <-> ACP SRAM |
201 | */ | |
202 | static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio, | |
13838c11 MV |
203 | u32 size, int direction, |
204 | u32 pte_offset, u16 ch, | |
205 | u32 sram_bank, u16 dma_dscr_idx, | |
206 | u32 asic_type) | |
7c31335a MSB |
207 | { |
208 | u16 i; | |
7c31335a MSB |
209 | acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL]; |
210 | ||
211 | for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) { | |
212 | dmadscr[i].xfer_val = 0; | |
213 | if (direction == SNDRV_PCM_STREAM_PLAYBACK) { | |
4376a86c | 214 | dma_dscr_idx = dma_dscr_idx + i; |
13838c11 | 215 | dmadscr[i].dest = sram_bank + (i * (size / 2)); |
7c31335a | 216 | dmadscr[i].src = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS |
13838c11 | 217 | + (pte_offset * SZ_4K) + (i * (size / 2)); |
aac89748 VM |
218 | switch (asic_type) { |
219 | case CHIP_STONEY: | |
220 | dmadscr[i].xfer_val |= | |
13838c11 | 221 | (ACP_DMA_ATTR_DAGB_GARLIC_TO_SHAREDMEM << 16) | |
aac89748 VM |
222 | (size / 2); |
223 | break; | |
224 | default: | |
225 | dmadscr[i].xfer_val |= | |
13838c11 | 226 | (ACP_DMA_ATTR_DAGB_ONION_TO_SHAREDMEM << 16) | |
aac89748 VM |
227 | (size / 2); |
228 | } | |
7c31335a | 229 | } else { |
4376a86c | 230 | dma_dscr_idx = dma_dscr_idx + i; |
13838c11 | 231 | dmadscr[i].src = sram_bank + (i * (size / 2)); |
4376a86c MV |
232 | dmadscr[i].dest = |
233 | ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS + | |
13838c11 | 234 | (pte_offset * SZ_4K) + (i * (size / 2)); |
aac89748 VM |
235 | switch (asic_type) { |
236 | case CHIP_STONEY: | |
aac89748 | 237 | dmadscr[i].xfer_val |= |
13838c11 | 238 | (ACP_DMA_ATTR_SHARED_MEM_TO_DAGB_GARLIC << 16) | |
aac89748 VM |
239 | (size / 2); |
240 | break; | |
241 | default: | |
aac89748 | 242 | dmadscr[i].xfer_val |= |
13838c11 | 243 | (ACP_DMA_ATTR_SHAREDMEM_TO_DAGB_ONION << 16) | |
aac89748 VM |
244 | (size / 2); |
245 | } | |
7c31335a MSB |
246 | } |
247 | config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx, | |
13838c11 | 248 | &dmadscr[i]); |
7c31335a | 249 | } |
2a665dba | 250 | pre_config_reset(acp_mmio, ch); |
4376a86c | 251 | config_acp_dma_channel(acp_mmio, ch, |
13838c11 MV |
252 | dma_dscr_idx - 1, |
253 | NUM_DSCRS_PER_CHANNEL, | |
254 | ACP_DMA_PRIORITY_LEVEL_NORMAL); | |
7c31335a MSB |
255 | } |
256 | ||
13838c11 MV |
257 | /* |
258 | * Initialize the DMA descriptor information for transfer between | |
7c31335a MSB |
259 | * ACP SRAM <-> I2S |
260 | */ | |
4376a86c | 261 | static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio, u32 size, |
13838c11 MV |
262 | int direction, u32 sram_bank, |
263 | u16 destination, u16 ch, | |
264 | u16 dma_dscr_idx, u32 asic_type) | |
7c31335a | 265 | { |
7c31335a | 266 | u16 i; |
7c31335a MSB |
267 | acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL]; |
268 | ||
269 | for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) { | |
270 | dmadscr[i].xfer_val = 0; | |
271 | if (direction == SNDRV_PCM_STREAM_PLAYBACK) { | |
4376a86c | 272 | dma_dscr_idx = dma_dscr_idx + i; |
13838c11 | 273 | dmadscr[i].src = sram_bank + (i * (size / 2)); |
7c31335a MSB |
274 | /* dmadscr[i].dest is unused by hardware. */ |
275 | dmadscr[i].dest = 0; | |
4376a86c | 276 | dmadscr[i].xfer_val |= BIT(22) | (destination << 16) | |
7c31335a MSB |
277 | (size / 2); |
278 | } else { | |
4376a86c | 279 | dma_dscr_idx = dma_dscr_idx + i; |
7c31335a MSB |
280 | /* dmadscr[i].src is unused by hardware. */ |
281 | dmadscr[i].src = 0; | |
4376a86c MV |
282 | dmadscr[i].dest = |
283 | sram_bank + (i * (size / 2)); | |
7c31335a | 284 | dmadscr[i].xfer_val |= BIT(22) | |
4376a86c | 285 | (destination << 16) | (size / 2); |
7c31335a MSB |
286 | } |
287 | config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx, | |
13838c11 | 288 | &dmadscr[i]); |
7c31335a | 289 | } |
2a665dba | 290 | pre_config_reset(acp_mmio, ch); |
7c31335a | 291 | /* Configure the DMA channel with the above descriptore */ |
4376a86c | 292 | config_acp_dma_channel(acp_mmio, ch, dma_dscr_idx - 1, |
13838c11 MV |
293 | NUM_DSCRS_PER_CHANNEL, |
294 | ACP_DMA_PRIORITY_LEVEL_NORMAL); | |
7c31335a MSB |
295 | } |
296 | ||
297 | /* Create page table entries in ACP SRAM for the allocated memory */ | |
d6d08273 | 298 | static void acp_pte_config(void __iomem *acp_mmio, dma_addr_t addr, |
7c31335a MSB |
299 | u16 num_of_pages, u32 pte_offset) |
300 | { | |
301 | u16 page_idx; | |
7c31335a MSB |
302 | u32 low; |
303 | u32 high; | |
304 | u32 offset; | |
305 | ||
306 | offset = ACP_DAGB_GRP_SRBM_SRAM_BASE_OFFSET + (pte_offset * 8); | |
307 | for (page_idx = 0; page_idx < (num_of_pages); page_idx++) { | |
308 | /* Load the low address of page int ACP SRAM through SRBM */ | |
309 | acp_reg_write((offset + (page_idx * 8)), | |
13838c11 | 310 | acp_mmio, mmACP_SRBM_Targ_Idx_Addr); |
7c31335a MSB |
311 | |
312 | low = lower_32_bits(addr); | |
313 | high = upper_32_bits(addr); | |
314 | ||
315 | acp_reg_write(low, acp_mmio, mmACP_SRBM_Targ_Idx_Data); | |
316 | ||
317 | /* Load the High address of page int ACP SRAM through SRBM */ | |
318 | acp_reg_write((offset + (page_idx * 8) + 4), | |
13838c11 | 319 | acp_mmio, mmACP_SRBM_Targ_Idx_Addr); |
7c31335a MSB |
320 | |
321 | /* page enable in ACP */ | |
322 | high |= BIT(31); | |
323 | acp_reg_write(high, acp_mmio, mmACP_SRBM_Targ_Idx_Data); | |
324 | ||
325 | /* Move to next physically contiguos page */ | |
d6d08273 | 326 | addr += PAGE_SIZE; |
7c31335a MSB |
327 | } |
328 | } | |
329 | ||
330 | static void config_acp_dma(void __iomem *acp_mmio, | |
8349b7f5 | 331 | struct audio_substream_data *rtd, |
13838c11 | 332 | u32 asic_type) |
7c31335a | 333 | { |
fa9d2f17 AA |
334 | u16 ch_acp_sysmem, ch_acp_i2s; |
335 | ||
d6d08273 | 336 | acp_pte_config(acp_mmio, rtd->dma_addr, rtd->num_of_pages, |
e188c525 | 337 | rtd->pte_offset); |
fa9d2f17 AA |
338 | |
339 | if (rtd->direction == SNDRV_PCM_STREAM_PLAYBACK) { | |
340 | ch_acp_sysmem = rtd->ch1; | |
341 | ch_acp_i2s = rtd->ch2; | |
342 | } else { | |
343 | ch_acp_i2s = rtd->ch1; | |
344 | ch_acp_sysmem = rtd->ch2; | |
345 | } | |
7c31335a | 346 | /* Configure System memory <-> ACP SRAM DMA descriptors */ |
8349b7f5 | 347 | set_acp_sysmem_dma_descriptors(acp_mmio, rtd->size, |
e188c525 | 348 | rtd->direction, rtd->pte_offset, |
fa9d2f17 | 349 | ch_acp_sysmem, rtd->sram_bank, |
8769bb55 | 350 | rtd->dma_dscr_idx_1, asic_type); |
7c31335a | 351 | /* Configure ACP SRAM <-> I2S DMA descriptors */ |
8349b7f5 | 352 | set_acp_to_i2s_dma_descriptors(acp_mmio, rtd->size, |
18e8a40d | 353 | rtd->direction, rtd->sram_bank, |
fa9d2f17 | 354 | rtd->destination, ch_acp_i2s, |
8769bb55 | 355 | rtd->dma_dscr_idx_2, asic_type); |
7c31335a MSB |
356 | } |
357 | ||
2718c89a AA |
358 | static void acp_dma_cap_channel_enable(void __iomem *acp_mmio, |
359 | u16 cap_channel) | |
360 | { | |
361 | u32 val, ch_reg, imr_reg, res_reg; | |
362 | ||
363 | switch (cap_channel) { | |
364 | case CAP_CHANNEL1: | |
365 | ch_reg = mmACP_I2SMICSP_RER1; | |
366 | res_reg = mmACP_I2SMICSP_RCR1; | |
367 | imr_reg = mmACP_I2SMICSP_IMR1; | |
368 | break; | |
369 | case CAP_CHANNEL0: | |
370 | default: | |
371 | ch_reg = mmACP_I2SMICSP_RER0; | |
372 | res_reg = mmACP_I2SMICSP_RCR0; | |
373 | imr_reg = mmACP_I2SMICSP_IMR0; | |
374 | break; | |
375 | } | |
376 | val = acp_reg_read(acp_mmio, | |
377 | mmACP_I2S_16BIT_RESOLUTION_EN); | |
378 | if (val & ACP_I2S_MIC_16BIT_RESOLUTION_EN) { | |
379 | acp_reg_write(0x0, acp_mmio, ch_reg); | |
380 | /* Set 16bit resolution on capture */ | |
381 | acp_reg_write(0x2, acp_mmio, res_reg); | |
382 | } | |
383 | val = acp_reg_read(acp_mmio, imr_reg); | |
384 | val &= ~ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK; | |
385 | val &= ~ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK; | |
386 | acp_reg_write(val, acp_mmio, imr_reg); | |
387 | acp_reg_write(0x1, acp_mmio, ch_reg); | |
388 | } | |
389 | ||
390 | static void acp_dma_cap_channel_disable(void __iomem *acp_mmio, | |
391 | u16 cap_channel) | |
392 | { | |
393 | u32 val, ch_reg, imr_reg; | |
394 | ||
395 | switch (cap_channel) { | |
396 | case CAP_CHANNEL1: | |
397 | imr_reg = mmACP_I2SMICSP_IMR1; | |
398 | ch_reg = mmACP_I2SMICSP_RER1; | |
399 | break; | |
400 | case CAP_CHANNEL0: | |
401 | default: | |
402 | imr_reg = mmACP_I2SMICSP_IMR0; | |
403 | ch_reg = mmACP_I2SMICSP_RER0; | |
404 | break; | |
405 | } | |
406 | val = acp_reg_read(acp_mmio, imr_reg); | |
407 | val |= ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK; | |
408 | val |= ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK; | |
409 | acp_reg_write(val, acp_mmio, imr_reg); | |
410 | acp_reg_write(0x0, acp_mmio, ch_reg); | |
411 | } | |
412 | ||
7c31335a | 413 | /* Start a given DMA channel transfer */ |
bbdb7012 | 414 | static void acp_dma_start(void __iomem *acp_mmio, u16 ch_num, bool is_circular) |
7c31335a MSB |
415 | { |
416 | u32 dma_ctrl; | |
417 | ||
418 | /* read the dma control register and disable the channel run field */ | |
419 | dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); | |
420 | ||
421 | /* Invalidating the DAGB cache */ | |
422 | acp_reg_write(1, acp_mmio, mmACP_DAGB_ATU_CTRL); | |
423 | ||
13838c11 MV |
424 | /* |
425 | * configure the DMA channel and start the DMA transfer | |
7c31335a MSB |
426 | * set dmachrun bit to start the transfer and enable the |
427 | * interrupt on completion of the dma transfer | |
428 | */ | |
429 | dma_ctrl |= ACP_DMA_CNTL_0__DMAChRun_MASK; | |
430 | ||
431 | switch (ch_num) { | |
432 | case ACP_TO_I2S_DMA_CH_NUM: | |
19e023e3 | 433 | case I2S_TO_ACP_DMA_CH_NUM: |
ccfbb4f5 | 434 | case ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM: |
19e023e3 | 435 | case I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM: |
7c31335a MSB |
436 | dma_ctrl |= ACP_DMA_CNTL_0__DMAChIOCEn_MASK; |
437 | break; | |
438 | default: | |
439 | dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK; | |
440 | break; | |
441 | } | |
442 | ||
bbdb7012 AA |
443 | /* enable for ACP to SRAM DMA channel */ |
444 | if (is_circular == true) | |
445 | dma_ctrl |= ACP_DMA_CNTL_0__Circular_DMA_En_MASK; | |
446 | else | |
447 | dma_ctrl &= ~ACP_DMA_CNTL_0__Circular_DMA_En_MASK; | |
7c31335a MSB |
448 | |
449 | acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); | |
450 | } | |
451 | ||
452 | /* Stop a given DMA channel transfer */ | |
453 | static int acp_dma_stop(void __iomem *acp_mmio, u8 ch_num) | |
454 | { | |
455 | u32 dma_ctrl; | |
456 | u32 dma_ch_sts; | |
457 | u32 count = ACP_DMA_RESET_TIME; | |
458 | ||
459 | dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); | |
460 | ||
13838c11 MV |
461 | /* |
462 | * clear the dma control register fields before writing zero | |
7c31335a | 463 | * in reset bit |
13838c11 | 464 | */ |
7c31335a MSB |
465 | dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK; |
466 | dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK; | |
467 | ||
468 | acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); | |
469 | dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS); | |
470 | ||
471 | if (dma_ch_sts & BIT(ch_num)) { | |
13838c11 MV |
472 | /* |
473 | * set the reset bit for this channel to stop the dma | |
474 | * transfer | |
475 | */ | |
7c31335a MSB |
476 | dma_ctrl |= ACP_DMA_CNTL_0__DMAChRst_MASK; |
477 | acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); | |
478 | } | |
479 | ||
480 | /* check the channel status bit for some time and return the status */ | |
481 | while (true) { | |
482 | dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS); | |
483 | if (!(dma_ch_sts & BIT(ch_num))) { | |
13838c11 MV |
484 | /* |
485 | * clear the reset flag after successfully stopping | |
486 | * the dma transfer and break from the loop | |
487 | */ | |
7c31335a MSB |
488 | dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK; |
489 | ||
490 | acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 | |
13838c11 | 491 | + ch_num); |
7c31335a MSB |
492 | break; |
493 | } | |
494 | if (--count == 0) { | |
495 | pr_err("Failed to stop ACP DMA channel : %d\n", ch_num); | |
496 | return -ETIMEDOUT; | |
497 | } | |
498 | udelay(100); | |
499 | } | |
500 | return 0; | |
501 | } | |
502 | ||
c36d9b3f | 503 | static void acp_set_sram_bank_state(void __iomem *acp_mmio, u16 bank, |
13838c11 | 504 | bool power_on) |
c36d9b3f MSB |
505 | { |
506 | u32 val, req_reg, sts_reg, sts_reg_mask; | |
507 | u32 loops = 1000; | |
508 | ||
509 | if (bank < 32) { | |
510 | req_reg = mmACP_MEM_SHUT_DOWN_REQ_LO; | |
511 | sts_reg = mmACP_MEM_SHUT_DOWN_STS_LO; | |
512 | sts_reg_mask = 0xFFFFFFFF; | |
513 | ||
514 | } else { | |
515 | bank -= 32; | |
516 | req_reg = mmACP_MEM_SHUT_DOWN_REQ_HI; | |
517 | sts_reg = mmACP_MEM_SHUT_DOWN_STS_HI; | |
518 | sts_reg_mask = 0x0000FFFF; | |
519 | } | |
520 | ||
521 | val = acp_reg_read(acp_mmio, req_reg); | |
522 | if (val & (1 << bank)) { | |
523 | /* bank is in off state */ | |
524 | if (power_on == true) | |
525 | /* request to on */ | |
526 | val &= ~(1 << bank); | |
527 | else | |
528 | /* request to off */ | |
529 | return; | |
530 | } else { | |
531 | /* bank is in on state */ | |
532 | if (power_on == false) | |
533 | /* request to off */ | |
534 | val |= 1 << bank; | |
535 | else | |
536 | /* request to on */ | |
537 | return; | |
538 | } | |
539 | acp_reg_write(val, acp_mmio, req_reg); | |
540 | ||
541 | while (acp_reg_read(acp_mmio, sts_reg) != sts_reg_mask) { | |
542 | if (!loops--) { | |
543 | pr_err("ACP SRAM bank %d state change failed\n", bank); | |
544 | break; | |
545 | } | |
546 | cpu_relax(); | |
547 | } | |
548 | } | |
549 | ||
7c31335a | 550 | /* Initialize and bring ACP hardware to default state. */ |
607b39ef | 551 | static int acp_init(void __iomem *acp_mmio, u32 asic_type) |
7c31335a | 552 | { |
c36d9b3f | 553 | u16 bank; |
7c31335a MSB |
554 | u32 val, count, sram_pte_offset; |
555 | ||
556 | /* Assert Soft reset of ACP */ | |
557 | val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); | |
558 | ||
559 | val |= ACP_SOFT_RESET__SoftResetAud_MASK; | |
560 | acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); | |
561 | ||
562 | count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; | |
563 | while (true) { | |
564 | val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); | |
565 | if (ACP_SOFT_RESET__SoftResetAudDone_MASK == | |
566 | (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) | |
567 | break; | |
568 | if (--count == 0) { | |
569 | pr_err("Failed to reset ACP\n"); | |
570 | return -ETIMEDOUT; | |
571 | } | |
572 | udelay(100); | |
573 | } | |
574 | ||
575 | /* Enable clock to ACP and wait until the clock is enabled */ | |
576 | val = acp_reg_read(acp_mmio, mmACP_CONTROL); | |
577 | val = val | ACP_CONTROL__ClkEn_MASK; | |
578 | acp_reg_write(val, acp_mmio, mmACP_CONTROL); | |
579 | ||
580 | count = ACP_CLOCK_EN_TIME_OUT_VALUE; | |
581 | ||
582 | while (true) { | |
583 | val = acp_reg_read(acp_mmio, mmACP_STATUS); | |
13838c11 | 584 | if (val & (u32)0x1) |
7c31335a MSB |
585 | break; |
586 | if (--count == 0) { | |
587 | pr_err("Failed to reset ACP\n"); | |
588 | return -ETIMEDOUT; | |
589 | } | |
590 | udelay(100); | |
591 | } | |
592 | ||
593 | /* Deassert the SOFT RESET flags */ | |
594 | val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); | |
595 | val &= ~ACP_SOFT_RESET__SoftResetAud_MASK; | |
596 | acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); | |
597 | ||
ccfbb4f5 MV |
598 | /* For BT instance change pins from UART to BT */ |
599 | if (!bt_uart_enable) { | |
600 | val = acp_reg_read(acp_mmio, mmACP_BT_UART_PAD_SEL); | |
601 | val |= ACP_BT_UART_PAD_SELECT_MASK; | |
602 | acp_reg_write(val, acp_mmio, mmACP_BT_UART_PAD_SEL); | |
603 | } | |
604 | ||
7c31335a MSB |
605 | /* initiailize Onion control DAGB register */ |
606 | acp_reg_write(ACP_ONION_CNTL_DEFAULT, acp_mmio, | |
13838c11 | 607 | mmACP_AXI2DAGB_ONION_CNTL); |
7c31335a MSB |
608 | |
609 | /* initiailize Garlic control DAGB registers */ | |
610 | acp_reg_write(ACP_GARLIC_CNTL_DEFAULT, acp_mmio, | |
13838c11 | 611 | mmACP_AXI2DAGB_GARLIC_CNTL); |
7c31335a MSB |
612 | |
613 | sram_pte_offset = ACP_DAGB_GRP_SRAM_BASE_ADDRESS | | |
614 | ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel_MASK | | |
615 | ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel_MASK | | |
616 | ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable_MASK; | |
617 | acp_reg_write(sram_pte_offset, acp_mmio, mmACP_DAGB_BASE_ADDR_GRP_1); | |
618 | acp_reg_write(ACP_PAGE_SIZE_4K_ENABLE, acp_mmio, | |
13838c11 | 619 | mmACP_DAGB_PAGE_SIZE_GRP_1); |
7c31335a MSB |
620 | |
621 | acp_reg_write(ACP_SRAM_BASE_ADDRESS, acp_mmio, | |
13838c11 | 622 | mmACP_DMA_DESC_BASE_ADDR); |
7c31335a MSB |
623 | |
624 | /* Num of descriptiors in SRAM 0x4, means 256 descriptors;(64 * 4) */ | |
625 | acp_reg_write(0x4, acp_mmio, mmACP_DMA_DESC_MAX_NUM_DSCR); | |
626 | acp_reg_write(ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK, | |
13838c11 | 627 | acp_mmio, mmACP_EXTERNAL_INTR_CNTL); |
7c31335a | 628 | |
13838c11 MV |
629 | /* |
630 | * When ACP_TILE_P1 is turned on, all SRAM banks get turned on. | |
c36d9b3f MSB |
631 | * Now, turn off all of them. This can't be done in 'poweron' of |
632 | * ACP pm domain, as this requires ACP to be initialized. | |
607b39ef VM |
633 | * For Stoney, Memory gating is disabled,i.e SRAM Banks |
634 | * won't be turned off. The default state for SRAM banks is ON. | |
635 | * Setting SRAM bank state code skipped for STONEY platform. | |
c36d9b3f | 636 | */ |
607b39ef VM |
637 | if (asic_type != CHIP_STONEY) { |
638 | for (bank = 1; bank < 48; bank++) | |
639 | acp_set_sram_bank_state(acp_mmio, bank, false); | |
640 | } | |
7c31335a MSB |
641 | return 0; |
642 | } | |
643 | ||
1cce2000 | 644 | /* Deinitialize ACP */ |
7c31335a MSB |
645 | static int acp_deinit(void __iomem *acp_mmio) |
646 | { | |
647 | u32 val; | |
648 | u32 count; | |
649 | ||
650 | /* Assert Soft reset of ACP */ | |
651 | val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); | |
652 | ||
653 | val |= ACP_SOFT_RESET__SoftResetAud_MASK; | |
654 | acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); | |
655 | ||
656 | count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; | |
657 | while (true) { | |
658 | val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); | |
659 | if (ACP_SOFT_RESET__SoftResetAudDone_MASK == | |
660 | (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) | |
661 | break; | |
662 | if (--count == 0) { | |
663 | pr_err("Failed to reset ACP\n"); | |
664 | return -ETIMEDOUT; | |
665 | } | |
666 | udelay(100); | |
667 | } | |
13838c11 | 668 | /* Disable ACP clock */ |
7c31335a MSB |
669 | val = acp_reg_read(acp_mmio, mmACP_CONTROL); |
670 | val &= ~ACP_CONTROL__ClkEn_MASK; | |
671 | acp_reg_write(val, acp_mmio, mmACP_CONTROL); | |
672 | ||
673 | count = ACP_CLOCK_EN_TIME_OUT_VALUE; | |
674 | ||
675 | while (true) { | |
676 | val = acp_reg_read(acp_mmio, mmACP_STATUS); | |
13838c11 | 677 | if (!(val & (u32)0x1)) |
7c31335a MSB |
678 | break; |
679 | if (--count == 0) { | |
680 | pr_err("Failed to reset ACP\n"); | |
681 | return -ETIMEDOUT; | |
682 | } | |
683 | udelay(100); | |
684 | } | |
685 | return 0; | |
686 | } | |
687 | ||
688 | /* ACP DMA irq handler routine for playback, capture usecases */ | |
689 | static irqreturn_t dma_irq_handler(int irq, void *arg) | |
690 | { | |
bbdb7012 | 691 | u16 dscr_idx; |
7c31335a MSB |
692 | u32 intr_flag, ext_intr_status; |
693 | struct audio_drv_data *irq_data; | |
694 | void __iomem *acp_mmio; | |
695 | struct device *dev = arg; | |
696 | bool valid_irq = false; | |
697 | ||
698 | irq_data = dev_get_drvdata(dev); | |
699 | acp_mmio = irq_data->acp_mmio; | |
700 | ||
701 | ext_intr_status = acp_reg_read(acp_mmio, mmACP_EXTERNAL_INTR_STAT); | |
702 | intr_flag = (((ext_intr_status & | |
703 | ACP_EXTERNAL_INTR_STAT__DMAIOCStat_MASK) >> | |
704 | ACP_EXTERNAL_INTR_STAT__DMAIOCStat__SHIFT)); | |
705 | ||
706 | if ((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) != 0) { | |
707 | valid_irq = true; | |
e21358c4 | 708 | snd_pcm_period_elapsed(irq_data->play_i2ssp_stream); |
7c31335a | 709 | acp_reg_write((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) << 16, |
13838c11 | 710 | acp_mmio, mmACP_EXTERNAL_INTR_STAT); |
7c31335a MSB |
711 | } |
712 | ||
ccfbb4f5 MV |
713 | if ((intr_flag & BIT(ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM)) != 0) { |
714 | valid_irq = true; | |
ccfbb4f5 MV |
715 | snd_pcm_period_elapsed(irq_data->play_i2sbt_stream); |
716 | acp_reg_write((intr_flag & | |
717 | BIT(ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM)) << 16, | |
718 | acp_mmio, mmACP_EXTERNAL_INTR_STAT); | |
719 | } | |
720 | ||
19e023e3 | 721 | if ((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) != 0) { |
7c31335a | 722 | valid_irq = true; |
bbdb7012 AA |
723 | if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_14) == |
724 | CAPTURE_START_DMA_DESCR_CH15) | |
725 | dscr_idx = CAPTURE_END_DMA_DESCR_CH14; | |
726 | else | |
727 | dscr_idx = CAPTURE_START_DMA_DESCR_CH14; | |
728 | config_acp_dma_channel(acp_mmio, ACP_TO_SYSRAM_CH_NUM, dscr_idx, | |
729 | 1, 0); | |
730 | acp_dma_start(acp_mmio, ACP_TO_SYSRAM_CH_NUM, false); | |
731 | ||
6b116dfb | 732 | snd_pcm_period_elapsed(irq_data->capture_i2ssp_stream); |
19e023e3 | 733 | acp_reg_write((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) << 16, |
13838c11 | 734 | acp_mmio, mmACP_EXTERNAL_INTR_STAT); |
7c31335a MSB |
735 | } |
736 | ||
19e023e3 | 737 | if ((intr_flag & BIT(I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM)) != 0) { |
ccfbb4f5 | 738 | valid_irq = true; |
bbdb7012 AA |
739 | if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_10) == |
740 | CAPTURE_START_DMA_DESCR_CH11) | |
741 | dscr_idx = CAPTURE_END_DMA_DESCR_CH10; | |
742 | else | |
743 | dscr_idx = CAPTURE_START_DMA_DESCR_CH10; | |
744 | config_acp_dma_channel(acp_mmio, | |
745 | ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM, | |
746 | dscr_idx, 1, 0); | |
747 | acp_dma_start(acp_mmio, ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM, | |
748 | false); | |
749 | ||
6b116dfb | 750 | snd_pcm_period_elapsed(irq_data->capture_i2sbt_stream); |
ccfbb4f5 | 751 | acp_reg_write((intr_flag & |
19e023e3 | 752 | BIT(I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM)) << 16, |
ccfbb4f5 MV |
753 | acp_mmio, mmACP_EXTERNAL_INTR_STAT); |
754 | } | |
755 | ||
7c31335a MSB |
756 | if (valid_irq) |
757 | return IRQ_HANDLED; | |
758 | else | |
759 | return IRQ_NONE; | |
760 | } | |
761 | ||
762 | static int acp_dma_open(struct snd_pcm_substream *substream) | |
763 | { | |
c36d9b3f | 764 | u16 bank; |
7c31335a MSB |
765 | int ret = 0; |
766 | struct snd_pcm_runtime *runtime = substream->runtime; | |
767 | struct snd_soc_pcm_runtime *prtd = substream->private_data; | |
13838c11 MV |
768 | struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd, |
769 | DRV_NAME); | |
a1042a42 | 770 | struct audio_drv_data *intr_data = dev_get_drvdata(component->dev); |
7c31335a MSB |
771 | struct audio_substream_data *adata = |
772 | kzalloc(sizeof(struct audio_substream_data), GFP_KERNEL); | |
13838c11 | 773 | if (!adata) |
7c31335a MSB |
774 | return -ENOMEM; |
775 | ||
9c7d6fab VM |
776 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
777 | switch (intr_data->asic_type) { | |
778 | case CHIP_STONEY: | |
779 | runtime->hw = acp_st_pcm_hardware_playback; | |
780 | break; | |
781 | default: | |
782 | runtime->hw = acp_pcm_hardware_playback; | |
783 | } | |
784 | } else { | |
785 | switch (intr_data->asic_type) { | |
786 | case CHIP_STONEY: | |
787 | runtime->hw = acp_st_pcm_hardware_capture; | |
788 | break; | |
789 | default: | |
790 | runtime->hw = acp_pcm_hardware_capture; | |
791 | } | |
792 | } | |
7c31335a MSB |
793 | |
794 | ret = snd_pcm_hw_constraint_integer(runtime, | |
795 | SNDRV_PCM_HW_PARAM_PERIODS); | |
796 | if (ret < 0) { | |
a1042a42 | 797 | dev_err(component->dev, "set integer constraint failed\n"); |
cde6bcd5 | 798 | kfree(adata); |
7c31335a MSB |
799 | return ret; |
800 | } | |
801 | ||
802 | adata->acp_mmio = intr_data->acp_mmio; | |
803 | runtime->private_data = adata; | |
804 | ||
13838c11 MV |
805 | /* |
806 | * Enable ACP irq, when neither playback or capture streams are | |
7c31335a MSB |
807 | * active by the time when a new stream is being opened. |
808 | * This enablement is not required for another stream, if current | |
809 | * stream is not closed | |
13838c11 | 810 | */ |
ccfbb4f5 MV |
811 | if (!intr_data->play_i2ssp_stream && !intr_data->capture_i2ssp_stream && |
812 | !intr_data->play_i2sbt_stream && !intr_data->capture_i2sbt_stream) | |
7c31335a MSB |
813 | acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); |
814 | ||
c36d9b3f | 815 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
13838c11 MV |
816 | /* |
817 | * For Stoney, Memory gating is disabled,i.e SRAM Banks | |
607b39ef VM |
818 | * won't be turned off. The default state for SRAM banks is ON. |
819 | * Setting SRAM bank state code skipped for STONEY platform. | |
820 | */ | |
821 | if (intr_data->asic_type != CHIP_STONEY) { | |
822 | for (bank = 1; bank <= 4; bank++) | |
823 | acp_set_sram_bank_state(intr_data->acp_mmio, | |
824 | bank, true); | |
825 | } | |
c36d9b3f | 826 | } else { |
607b39ef VM |
827 | if (intr_data->asic_type != CHIP_STONEY) { |
828 | for (bank = 5; bank <= 8; bank++) | |
829 | acp_set_sram_bank_state(intr_data->acp_mmio, | |
830 | bank, true); | |
831 | } | |
c36d9b3f | 832 | } |
7c31335a MSB |
833 | |
834 | return 0; | |
835 | } | |
836 | ||
837 | static int acp_dma_hw_params(struct snd_pcm_substream *substream, | |
838 | struct snd_pcm_hw_params *params) | |
839 | { | |
840 | int status; | |
841 | uint64_t size; | |
a37d48e3 | 842 | u32 val = 0; |
7c31335a MSB |
843 | struct snd_pcm_runtime *runtime; |
844 | struct audio_substream_data *rtd; | |
aac89748 | 845 | struct snd_soc_pcm_runtime *prtd = substream->private_data; |
13838c11 MV |
846 | struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd, |
847 | DRV_NAME); | |
a1042a42 | 848 | struct audio_drv_data *adata = dev_get_drvdata(component->dev); |
ccfbb4f5 MV |
849 | struct snd_soc_card *card = prtd->card; |
850 | struct acp_platform_info *pinfo = snd_soc_card_get_drvdata(card); | |
7c31335a | 851 | |
7c31335a MSB |
852 | runtime = substream->runtime; |
853 | rtd = runtime->private_data; | |
854 | ||
855 | if (WARN_ON(!rtd)) | |
856 | return -EINVAL; | |
857 | ||
2718c89a | 858 | if (pinfo) { |
8dcb0c90 AA |
859 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
860 | rtd->i2s_instance = pinfo->play_i2s_instance; | |
861 | } else { | |
862 | rtd->i2s_instance = pinfo->cap_i2s_instance; | |
863 | rtd->capture_channel = pinfo->capture_channel; | |
864 | } | |
2718c89a | 865 | } |
a37d48e3 | 866 | if (adata->asic_type == CHIP_STONEY) { |
13838c11 MV |
867 | val = acp_reg_read(adata->acp_mmio, |
868 | mmACP_I2S_16BIT_RESOLUTION_EN); | |
ccfbb4f5 MV |
869 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
870 | switch (rtd->i2s_instance) { | |
871 | case I2S_BT_INSTANCE: | |
872 | val |= ACP_I2S_BT_16BIT_RESOLUTION_EN; | |
873 | break; | |
874 | case I2S_SP_INSTANCE: | |
875 | default: | |
876 | val |= ACP_I2S_SP_16BIT_RESOLUTION_EN; | |
877 | } | |
878 | } else { | |
879 | switch (rtd->i2s_instance) { | |
880 | case I2S_BT_INSTANCE: | |
881 | val |= ACP_I2S_BT_16BIT_RESOLUTION_EN; | |
882 | break; | |
883 | case I2S_SP_INSTANCE: | |
884 | default: | |
885 | val |= ACP_I2S_MIC_16BIT_RESOLUTION_EN; | |
886 | } | |
887 | } | |
13838c11 MV |
888 | acp_reg_write(val, adata->acp_mmio, |
889 | mmACP_I2S_16BIT_RESOLUTION_EN); | |
a37d48e3 | 890 | } |
8769bb55 VM |
891 | |
892 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
ccfbb4f5 MV |
893 | switch (rtd->i2s_instance) { |
894 | case I2S_BT_INSTANCE: | |
895 | rtd->pte_offset = ACP_ST_BT_PLAYBACK_PTE_OFFSET; | |
896 | rtd->ch1 = SYSRAM_TO_ACP_BT_INSTANCE_CH_NUM; | |
897 | rtd->ch2 = ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM; | |
898 | rtd->sram_bank = ACP_SRAM_BANK_3_ADDRESS; | |
899 | rtd->destination = TO_BLUETOOTH; | |
900 | rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH8; | |
901 | rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH9; | |
902 | rtd->byte_cnt_high_reg_offset = | |
903 | mmACP_I2S_BT_TRANSMIT_BYTE_CNT_HIGH; | |
904 | rtd->byte_cnt_low_reg_offset = | |
905 | mmACP_I2S_BT_TRANSMIT_BYTE_CNT_LOW; | |
906 | adata->play_i2sbt_stream = substream; | |
e188c525 | 907 | break; |
ccfbb4f5 | 908 | case I2S_SP_INSTANCE: |
e188c525 | 909 | default: |
ccfbb4f5 MV |
910 | switch (adata->asic_type) { |
911 | case CHIP_STONEY: | |
912 | rtd->pte_offset = ACP_ST_PLAYBACK_PTE_OFFSET; | |
913 | break; | |
914 | default: | |
915 | rtd->pte_offset = ACP_PLAYBACK_PTE_OFFSET; | |
916 | } | |
917 | rtd->ch1 = SYSRAM_TO_ACP_CH_NUM; | |
918 | rtd->ch2 = ACP_TO_I2S_DMA_CH_NUM; | |
919 | rtd->sram_bank = ACP_SRAM_BANK_1_ADDRESS; | |
920 | rtd->destination = TO_ACP_I2S_1; | |
921 | rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH12; | |
922 | rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH13; | |
923 | rtd->byte_cnt_high_reg_offset = | |
924 | mmACP_I2S_TRANSMIT_BYTE_CNT_HIGH; | |
925 | rtd->byte_cnt_low_reg_offset = | |
926 | mmACP_I2S_TRANSMIT_BYTE_CNT_LOW; | |
927 | adata->play_i2ssp_stream = substream; | |
e188c525 | 928 | } |
8769bb55 | 929 | } else { |
ccfbb4f5 MV |
930 | switch (rtd->i2s_instance) { |
931 | case I2S_BT_INSTANCE: | |
932 | rtd->pte_offset = ACP_ST_BT_CAPTURE_PTE_OFFSET; | |
55af49ac DK |
933 | rtd->ch1 = I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM; |
934 | rtd->ch2 = ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM; | |
ccfbb4f5 MV |
935 | rtd->sram_bank = ACP_SRAM_BANK_4_ADDRESS; |
936 | rtd->destination = FROM_BLUETOOTH; | |
937 | rtd->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH10; | |
938 | rtd->dma_dscr_idx_2 = CAPTURE_START_DMA_DESCR_CH11; | |
c21c834a AA |
939 | rtd->byte_cnt_high_reg_offset = |
940 | mmACP_I2S_BT_RECEIVE_BYTE_CNT_HIGH; | |
941 | rtd->byte_cnt_low_reg_offset = | |
942 | mmACP_I2S_BT_RECEIVE_BYTE_CNT_LOW; | |
662fb3ef | 943 | rtd->dma_curr_dscr = mmACP_DMA_CUR_DSCR_11; |
ccfbb4f5 | 944 | adata->capture_i2sbt_stream = substream; |
e188c525 | 945 | break; |
ccfbb4f5 | 946 | case I2S_SP_INSTANCE: |
e188c525 MV |
947 | default: |
948 | rtd->pte_offset = ACP_CAPTURE_PTE_OFFSET; | |
55af49ac DK |
949 | rtd->ch1 = I2S_TO_ACP_DMA_CH_NUM; |
950 | rtd->ch2 = ACP_TO_SYSRAM_CH_NUM; | |
ccfbb4f5 MV |
951 | switch (adata->asic_type) { |
952 | case CHIP_STONEY: | |
953 | rtd->pte_offset = ACP_ST_CAPTURE_PTE_OFFSET; | |
954 | rtd->sram_bank = ACP_SRAM_BANK_2_ADDRESS; | |
955 | break; | |
956 | default: | |
957 | rtd->pte_offset = ACP_CAPTURE_PTE_OFFSET; | |
958 | rtd->sram_bank = ACP_SRAM_BANK_5_ADDRESS; | |
959 | } | |
960 | rtd->destination = FROM_ACP_I2S_1; | |
961 | rtd->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH14; | |
962 | rtd->dma_dscr_idx_2 = CAPTURE_START_DMA_DESCR_CH15; | |
c21c834a AA |
963 | rtd->byte_cnt_high_reg_offset = |
964 | mmACP_I2S_RECEIVED_BYTE_CNT_HIGH; | |
965 | rtd->byte_cnt_low_reg_offset = | |
966 | mmACP_I2S_RECEIVED_BYTE_CNT_LOW; | |
662fb3ef | 967 | rtd->dma_curr_dscr = mmACP_DMA_CUR_DSCR_15; |
ccfbb4f5 | 968 | adata->capture_i2ssp_stream = substream; |
e188c525 | 969 | } |
8769bb55 VM |
970 | } |
971 | ||
7c31335a MSB |
972 | size = params_buffer_bytes(params); |
973 | status = snd_pcm_lib_malloc_pages(substream, size); | |
974 | if (status < 0) | |
975 | return status; | |
976 | ||
977 | memset(substream->runtime->dma_area, 0, params_buffer_bytes(params)); | |
7c31335a | 978 | |
d6d08273 | 979 | if (substream->dma_buffer.area) { |
c36d9b3f | 980 | acp_set_sram_bank_state(rtd->acp_mmio, 0, true); |
7c31335a | 981 | /* Save for runtime private data */ |
d6d08273 | 982 | rtd->dma_addr = substream->dma_buffer.addr; |
7c31335a MSB |
983 | rtd->order = get_order(size); |
984 | ||
985 | /* Fill the page table entries in ACP SRAM */ | |
7c31335a MSB |
986 | rtd->size = size; |
987 | rtd->num_of_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
988 | rtd->direction = substream->stream; | |
989 | ||
aac89748 | 990 | config_acp_dma(rtd->acp_mmio, rtd, adata->asic_type); |
7c31335a MSB |
991 | status = 0; |
992 | } else { | |
993 | status = -ENOMEM; | |
994 | } | |
995 | return status; | |
996 | } | |
997 | ||
998 | static int acp_dma_hw_free(struct snd_pcm_substream *substream) | |
999 | { | |
1000 | return snd_pcm_lib_free_pages(substream); | |
1001 | } | |
1002 | ||
7f004847 | 1003 | static u64 acp_get_byte_count(struct audio_substream_data *rtd) |
61add814 | 1004 | { |
7f004847 | 1005 | union acp_dma_count byte_count; |
61add814 | 1006 | |
7f004847 VM |
1007 | byte_count.bcount.high = acp_reg_read(rtd->acp_mmio, |
1008 | rtd->byte_cnt_high_reg_offset); | |
1009 | byte_count.bcount.low = acp_reg_read(rtd->acp_mmio, | |
1010 | rtd->byte_cnt_low_reg_offset); | |
1011 | return byte_count.bytescount; | |
61add814 VM |
1012 | } |
1013 | ||
7c31335a MSB |
1014 | static snd_pcm_uframes_t acp_dma_pointer(struct snd_pcm_substream *substream) |
1015 | { | |
61add814 | 1016 | u32 buffersize; |
7c31335a | 1017 | u32 pos = 0; |
61add814 | 1018 | u64 bytescount = 0; |
662fb3ef | 1019 | u16 dscr; |
c21c834a | 1020 | u32 period_bytes, delay; |
7c31335a MSB |
1021 | |
1022 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1023 | struct audio_substream_data *rtd = runtime->private_data; | |
1024 | ||
7afa535e MV |
1025 | if (!rtd) |
1026 | return -EINVAL; | |
1027 | ||
662fb3ef MV |
1028 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { |
1029 | period_bytes = frames_to_bytes(runtime, runtime->period_size); | |
c21c834a | 1030 | bytescount = acp_get_byte_count(rtd); |
c50535ed | 1031 | if (bytescount >= rtd->bytescount) |
c21c834a | 1032 | bytescount -= rtd->bytescount; |
c50535ed AA |
1033 | if (bytescount < period_bytes) { |
1034 | pos = 0; | |
1035 | } else { | |
1036 | dscr = acp_reg_read(rtd->acp_mmio, rtd->dma_curr_dscr); | |
1037 | if (dscr == rtd->dma_dscr_idx_1) | |
1038 | pos = period_bytes; | |
1039 | else | |
1040 | pos = 0; | |
1041 | } | |
1042 | if (bytescount > 0) { | |
1043 | delay = do_div(bytescount, period_bytes); | |
1044 | runtime->delay = bytes_to_frames(runtime, delay); | |
1045 | } | |
662fb3ef MV |
1046 | } else { |
1047 | buffersize = frames_to_bytes(runtime, runtime->buffer_size); | |
1048 | bytescount = acp_get_byte_count(rtd); | |
1049 | if (bytescount > rtd->bytescount) | |
1050 | bytescount -= rtd->bytescount; | |
1051 | pos = do_div(bytescount, buffersize); | |
1052 | } | |
7c31335a MSB |
1053 | return bytes_to_frames(runtime, pos); |
1054 | } | |
1055 | ||
1056 | static int acp_dma_mmap(struct snd_pcm_substream *substream, | |
1057 | struct vm_area_struct *vma) | |
1058 | { | |
1059 | return snd_pcm_lib_default_mmap(substream, vma); | |
1060 | } | |
1061 | ||
1062 | static int acp_dma_prepare(struct snd_pcm_substream *substream) | |
1063 | { | |
1064 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1065 | struct audio_substream_data *rtd = runtime->private_data; | |
fa9d2f17 | 1066 | u16 ch_acp_sysmem, ch_acp_i2s; |
7c31335a | 1067 | |
7afa535e MV |
1068 | if (!rtd) |
1069 | return -EINVAL; | |
8769bb55 | 1070 | |
fa9d2f17 AA |
1071 | if (rtd->direction == SNDRV_PCM_STREAM_PLAYBACK) { |
1072 | ch_acp_sysmem = rtd->ch1; | |
1073 | ch_acp_i2s = rtd->ch2; | |
1074 | } else { | |
1075 | ch_acp_i2s = rtd->ch1; | |
1076 | ch_acp_sysmem = rtd->ch2; | |
1077 | } | |
8769bb55 | 1078 | config_acp_dma_channel(rtd->acp_mmio, |
fa9d2f17 | 1079 | ch_acp_sysmem, |
8769bb55 VM |
1080 | rtd->dma_dscr_idx_1, |
1081 | NUM_DSCRS_PER_CHANNEL, 0); | |
1082 | config_acp_dma_channel(rtd->acp_mmio, | |
fa9d2f17 | 1083 | ch_acp_i2s, |
8769bb55 VM |
1084 | rtd->dma_dscr_idx_2, |
1085 | NUM_DSCRS_PER_CHANNEL, 0); | |
7c31335a MSB |
1086 | return 0; |
1087 | } | |
1088 | ||
1089 | static int acp_dma_trigger(struct snd_pcm_substream *substream, int cmd) | |
1090 | { | |
1091 | int ret; | |
7c31335a MSB |
1092 | |
1093 | struct snd_pcm_runtime *runtime = substream->runtime; | |
7c31335a MSB |
1094 | struct audio_substream_data *rtd = runtime->private_data; |
1095 | ||
1096 | if (!rtd) | |
1097 | return -EINVAL; | |
1098 | switch (cmd) { | |
1099 | case SNDRV_PCM_TRIGGER_START: | |
1100 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
1101 | case SNDRV_PCM_TRIGGER_RESUME: | |
1a337a1e | 1102 | rtd->bytescount = acp_get_byte_count(rtd); |
df61f9f7 | 1103 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { |
2718c89a AA |
1104 | if (rtd->capture_channel == CAP_CHANNEL0) { |
1105 | acp_dma_cap_channel_disable(rtd->acp_mmio, | |
1106 | CAP_CHANNEL1); | |
1107 | acp_dma_cap_channel_enable(rtd->acp_mmio, | |
1108 | CAP_CHANNEL0); | |
1109 | } | |
1110 | if (rtd->capture_channel == CAP_CHANNEL1) { | |
1111 | acp_dma_cap_channel_disable(rtd->acp_mmio, | |
1112 | CAP_CHANNEL0); | |
1113 | acp_dma_cap_channel_enable(rtd->acp_mmio, | |
1114 | CAP_CHANNEL1); | |
1115 | } | |
bbdb7012 AA |
1116 | acp_dma_start(rtd->acp_mmio, rtd->ch1, true); |
1117 | } else { | |
1118 | acp_dma_start(rtd->acp_mmio, rtd->ch1, true); | |
1119 | acp_dma_start(rtd->acp_mmio, rtd->ch2, true); | |
7c31335a MSB |
1120 | } |
1121 | ret = 0; | |
1122 | break; | |
1123 | case SNDRV_PCM_TRIGGER_STOP: | |
1124 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
1125 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
30896d36 DK |
1126 | acp_dma_stop(rtd->acp_mmio, rtd->ch2); |
1127 | ret = acp_dma_stop(rtd->acp_mmio, rtd->ch1); | |
7c31335a MSB |
1128 | break; |
1129 | default: | |
1130 | ret = -EINVAL; | |
7c31335a MSB |
1131 | } |
1132 | return ret; | |
1133 | } | |
1134 | ||
1135 | static int acp_dma_new(struct snd_soc_pcm_runtime *rtd) | |
1136 | { | |
13838c11 MV |
1137 | struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, |
1138 | DRV_NAME); | |
a1042a42 | 1139 | struct audio_drv_data *adata = dev_get_drvdata(component->dev); |
23aa128b | 1140 | struct device *parent = component->dev->parent; |
9c7d6fab VM |
1141 | |
1142 | switch (adata->asic_type) { | |
1143 | case CHIP_STONEY: | |
f6aa470f TI |
1144 | snd_pcm_lib_preallocate_pages_for_all(rtd->pcm, |
1145 | SNDRV_DMA_TYPE_DEV, | |
1146 | parent, | |
1147 | ST_MIN_BUFFER, | |
1148 | ST_MAX_BUFFER); | |
9c7d6fab VM |
1149 | break; |
1150 | default: | |
f6aa470f TI |
1151 | snd_pcm_lib_preallocate_pages_for_all(rtd->pcm, |
1152 | SNDRV_DMA_TYPE_DEV, | |
1153 | parent, | |
1154 | MIN_BUFFER, | |
1155 | MAX_BUFFER); | |
9c7d6fab VM |
1156 | break; |
1157 | } | |
f6aa470f | 1158 | return 0; |
7c31335a MSB |
1159 | } |
1160 | ||
1161 | static int acp_dma_close(struct snd_pcm_substream *substream) | |
1162 | { | |
c36d9b3f | 1163 | u16 bank; |
7c31335a MSB |
1164 | struct snd_pcm_runtime *runtime = substream->runtime; |
1165 | struct audio_substream_data *rtd = runtime->private_data; | |
1166 | struct snd_soc_pcm_runtime *prtd = substream->private_data; | |
13838c11 MV |
1167 | struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd, |
1168 | DRV_NAME); | |
a1042a42 | 1169 | struct audio_drv_data *adata = dev_get_drvdata(component->dev); |
7c31335a | 1170 | |
c36d9b3f | 1171 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
ccfbb4f5 MV |
1172 | switch (rtd->i2s_instance) { |
1173 | case I2S_BT_INSTANCE: | |
1174 | adata->play_i2sbt_stream = NULL; | |
1175 | break; | |
1176 | case I2S_SP_INSTANCE: | |
1177 | default: | |
1178 | adata->play_i2ssp_stream = NULL; | |
1179 | /* | |
1180 | * For Stoney, Memory gating is disabled,i.e SRAM Banks | |
1181 | * won't be turned off. The default state for SRAM banks | |
1182 | * is ON.Setting SRAM bank state code skipped for STONEY | |
1183 | * platform. Added condition checks for Carrizo platform | |
1184 | * only. | |
1185 | */ | |
1186 | if (adata->asic_type != CHIP_STONEY) { | |
1187 | for (bank = 1; bank <= 4; bank++) | |
1188 | acp_set_sram_bank_state(adata->acp_mmio, | |
1189 | bank, false); | |
1190 | } | |
607b39ef VM |
1191 | } |
1192 | } else { | |
ccfbb4f5 MV |
1193 | switch (rtd->i2s_instance) { |
1194 | case I2S_BT_INSTANCE: | |
1195 | adata->capture_i2sbt_stream = NULL; | |
1196 | break; | |
1197 | case I2S_SP_INSTANCE: | |
1198 | default: | |
1199 | adata->capture_i2ssp_stream = NULL; | |
1200 | if (adata->asic_type != CHIP_STONEY) { | |
1201 | for (bank = 5; bank <= 8; bank++) | |
1202 | acp_set_sram_bank_state(adata->acp_mmio, | |
1203 | bank, false); | |
1204 | } | |
607b39ef | 1205 | } |
c36d9b3f | 1206 | } |
7c31335a | 1207 | |
13838c11 MV |
1208 | /* |
1209 | * Disable ACP irq, when the current stream is being closed and | |
7c31335a | 1210 | * another stream is also not active. |
13838c11 | 1211 | */ |
ccfbb4f5 MV |
1212 | if (!adata->play_i2ssp_stream && !adata->capture_i2ssp_stream && |
1213 | !adata->play_i2sbt_stream && !adata->capture_i2sbt_stream) | |
7c31335a | 1214 | acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); |
cac6f597 | 1215 | kfree(rtd); |
7c31335a MSB |
1216 | return 0; |
1217 | } | |
1218 | ||
115c7254 | 1219 | static const struct snd_pcm_ops acp_dma_ops = { |
7c31335a MSB |
1220 | .open = acp_dma_open, |
1221 | .close = acp_dma_close, | |
1222 | .ioctl = snd_pcm_lib_ioctl, | |
1223 | .hw_params = acp_dma_hw_params, | |
1224 | .hw_free = acp_dma_hw_free, | |
1225 | .trigger = acp_dma_trigger, | |
1226 | .pointer = acp_dma_pointer, | |
1227 | .mmap = acp_dma_mmap, | |
1228 | .prepare = acp_dma_prepare, | |
1229 | }; | |
1230 | ||
13838c11 | 1231 | static const struct snd_soc_component_driver acp_asoc_platform = { |
a1042a42 | 1232 | .name = DRV_NAME, |
7c31335a MSB |
1233 | .ops = &acp_dma_ops, |
1234 | .pcm_new = acp_dma_new, | |
1235 | }; | |
1236 | ||
1237 | static int acp_audio_probe(struct platform_device *pdev) | |
1238 | { | |
1239 | int status; | |
1240 | struct audio_drv_data *audio_drv_data; | |
1241 | struct resource *res; | |
a1b16aaa | 1242 | const u32 *pdata = pdev->dev.platform_data; |
7c31335a | 1243 | |
fdaa4511 GR |
1244 | if (!pdata) { |
1245 | dev_err(&pdev->dev, "Missing platform data\n"); | |
1246 | return -ENODEV; | |
1247 | } | |
1248 | ||
7c31335a | 1249 | audio_drv_data = devm_kzalloc(&pdev->dev, sizeof(struct audio_drv_data), |
13838c11 MV |
1250 | GFP_KERNEL); |
1251 | if (!audio_drv_data) | |
7c31335a MSB |
1252 | return -ENOMEM; |
1253 | ||
1254 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1255 | audio_drv_data->acp_mmio = devm_ioremap_resource(&pdev->dev, res); | |
fdaa4511 GR |
1256 | if (IS_ERR(audio_drv_data->acp_mmio)) |
1257 | return PTR_ERR(audio_drv_data->acp_mmio); | |
7c31335a | 1258 | |
13838c11 MV |
1259 | /* |
1260 | * The following members gets populated in device 'open' | |
7c31335a MSB |
1261 | * function. Till then interrupts are disabled in 'acp_init' |
1262 | * and device doesn't generate any interrupts. | |
1263 | */ | |
1264 | ||
e21358c4 MV |
1265 | audio_drv_data->play_i2ssp_stream = NULL; |
1266 | audio_drv_data->capture_i2ssp_stream = NULL; | |
ccfbb4f5 MV |
1267 | audio_drv_data->play_i2sbt_stream = NULL; |
1268 | audio_drv_data->capture_i2sbt_stream = NULL; | |
e21358c4 | 1269 | |
a1b16aaa | 1270 | audio_drv_data->asic_type = *pdata; |
7c31335a MSB |
1271 | |
1272 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
1273 | if (!res) { | |
1274 | dev_err(&pdev->dev, "IORESOURCE_IRQ FAILED\n"); | |
1275 | return -ENODEV; | |
1276 | } | |
1277 | ||
1278 | status = devm_request_irq(&pdev->dev, res->start, dma_irq_handler, | |
13838c11 | 1279 | 0, "ACP_IRQ", &pdev->dev); |
7c31335a MSB |
1280 | if (status) { |
1281 | dev_err(&pdev->dev, "ACP IRQ request failed\n"); | |
1282 | return status; | |
1283 | } | |
1284 | ||
1285 | dev_set_drvdata(&pdev->dev, audio_drv_data); | |
1286 | ||
1287 | /* Initialize the ACP */ | |
7afa535e MV |
1288 | status = acp_init(audio_drv_data->acp_mmio, audio_drv_data->asic_type); |
1289 | if (status) { | |
1290 | dev_err(&pdev->dev, "ACP Init failed status:%d\n", status); | |
1291 | return status; | |
1292 | } | |
7c31335a | 1293 | |
a1042a42 | 1294 | status = devm_snd_soc_register_component(&pdev->dev, |
13838c11 | 1295 | &acp_asoc_platform, NULL, 0); |
7c31335a MSB |
1296 | if (status != 0) { |
1297 | dev_err(&pdev->dev, "Fail to register ALSA platform device\n"); | |
1298 | return status; | |
1299 | } | |
1300 | ||
1927da93 MSB |
1301 | pm_runtime_set_autosuspend_delay(&pdev->dev, 10000); |
1302 | pm_runtime_use_autosuspend(&pdev->dev); | |
1303 | pm_runtime_enable(&pdev->dev); | |
1304 | ||
7c31335a MSB |
1305 | return status; |
1306 | } | |
1307 | ||
1308 | static int acp_audio_remove(struct platform_device *pdev) | |
1309 | { | |
7afa535e | 1310 | int status; |
7c31335a MSB |
1311 | struct audio_drv_data *adata = dev_get_drvdata(&pdev->dev); |
1312 | ||
7afa535e MV |
1313 | status = acp_deinit(adata->acp_mmio); |
1314 | if (status) | |
1315 | dev_err(&pdev->dev, "ACP Deinit failed status:%d\n", status); | |
1927da93 | 1316 | pm_runtime_disable(&pdev->dev); |
7c31335a MSB |
1317 | |
1318 | return 0; | |
1319 | } | |
1320 | ||
1927da93 MSB |
1321 | static int acp_pcm_resume(struct device *dev) |
1322 | { | |
c36d9b3f | 1323 | u16 bank; |
7afa535e | 1324 | int status; |
ccfbb4f5 | 1325 | struct audio_substream_data *rtd; |
1927da93 MSB |
1326 | struct audio_drv_data *adata = dev_get_drvdata(dev); |
1327 | ||
7afa535e MV |
1328 | status = acp_init(adata->acp_mmio, adata->asic_type); |
1329 | if (status) { | |
1330 | dev_err(dev, "ACP Init failed status:%d\n", status); | |
1331 | return status; | |
1332 | } | |
1927da93 | 1333 | |
e21358c4 | 1334 | if (adata->play_i2ssp_stream && adata->play_i2ssp_stream->runtime) { |
13838c11 MV |
1335 | /* |
1336 | * For Stoney, Memory gating is disabled,i.e SRAM Banks | |
607b39ef VM |
1337 | * won't be turned off. The default state for SRAM banks is ON. |
1338 | * Setting SRAM bank state code skipped for STONEY platform. | |
1339 | */ | |
1340 | if (adata->asic_type != CHIP_STONEY) { | |
1341 | for (bank = 1; bank <= 4; bank++) | |
1342 | acp_set_sram_bank_state(adata->acp_mmio, bank, | |
13838c11 | 1343 | true); |
607b39ef | 1344 | } |
ccfbb4f5 MV |
1345 | rtd = adata->play_i2ssp_stream->runtime->private_data; |
1346 | config_acp_dma(adata->acp_mmio, rtd, adata->asic_type); | |
c36d9b3f | 1347 | } |
13838c11 MV |
1348 | if (adata->capture_i2ssp_stream && |
1349 | adata->capture_i2ssp_stream->runtime) { | |
607b39ef VM |
1350 | if (adata->asic_type != CHIP_STONEY) { |
1351 | for (bank = 5; bank <= 8; bank++) | |
1352 | acp_set_sram_bank_state(adata->acp_mmio, bank, | |
13838c11 | 1353 | true); |
607b39ef | 1354 | } |
ccfbb4f5 MV |
1355 | rtd = adata->capture_i2ssp_stream->runtime->private_data; |
1356 | config_acp_dma(adata->acp_mmio, rtd, adata->asic_type); | |
1357 | } | |
1358 | if (adata->asic_type != CHIP_CARRIZO) { | |
1359 | if (adata->play_i2sbt_stream && | |
1360 | adata->play_i2sbt_stream->runtime) { | |
1361 | rtd = adata->play_i2sbt_stream->runtime->private_data; | |
1362 | config_acp_dma(adata->acp_mmio, rtd, adata->asic_type); | |
1363 | } | |
1364 | if (adata->capture_i2sbt_stream && | |
1365 | adata->capture_i2sbt_stream->runtime) { | |
1366 | rtd = adata->capture_i2sbt_stream->runtime->private_data; | |
1367 | config_acp_dma(adata->acp_mmio, rtd, adata->asic_type); | |
1368 | } | |
c36d9b3f | 1369 | } |
1927da93 MSB |
1370 | acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); |
1371 | return 0; | |
1372 | } | |
1373 | ||
1374 | static int acp_pcm_runtime_suspend(struct device *dev) | |
1375 | { | |
7afa535e | 1376 | int status; |
1927da93 MSB |
1377 | struct audio_drv_data *adata = dev_get_drvdata(dev); |
1378 | ||
7afa535e MV |
1379 | status = acp_deinit(adata->acp_mmio); |
1380 | if (status) | |
1381 | dev_err(dev, "ACP Deinit failed status:%d\n", status); | |
1927da93 MSB |
1382 | acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); |
1383 | return 0; | |
1384 | } | |
1385 | ||
1386 | static int acp_pcm_runtime_resume(struct device *dev) | |
1387 | { | |
7afa535e | 1388 | int status; |
1927da93 MSB |
1389 | struct audio_drv_data *adata = dev_get_drvdata(dev); |
1390 | ||
7afa535e MV |
1391 | status = acp_init(adata->acp_mmio, adata->asic_type); |
1392 | if (status) { | |
1393 | dev_err(dev, "ACP Init failed status:%d\n", status); | |
1394 | return status; | |
1395 | } | |
1927da93 MSB |
1396 | acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); |
1397 | return 0; | |
1398 | } | |
1399 | ||
1400 | static const struct dev_pm_ops acp_pm_ops = { | |
1401 | .resume = acp_pcm_resume, | |
1402 | .runtime_suspend = acp_pcm_runtime_suspend, | |
1403 | .runtime_resume = acp_pcm_runtime_resume, | |
1404 | }; | |
1405 | ||
7c31335a MSB |
1406 | static struct platform_driver acp_dma_driver = { |
1407 | .probe = acp_audio_probe, | |
1408 | .remove = acp_audio_remove, | |
1409 | .driver = { | |
bdd2a858 | 1410 | .name = DRV_NAME, |
1927da93 | 1411 | .pm = &acp_pm_ops, |
7c31335a MSB |
1412 | }, |
1413 | }; | |
1414 | ||
1415 | module_platform_driver(acp_dma_driver); | |
1416 | ||
607b39ef | 1417 | MODULE_AUTHOR("Vijendar.Mukunda@amd.com"); |
7c31335a MSB |
1418 | MODULE_AUTHOR("Maruthi.Bayyavarapu@amd.com"); |
1419 | MODULE_DESCRIPTION("AMD ACP PCM Driver"); | |
1420 | MODULE_LICENSE("GPL v2"); | |
bdd2a858 | 1421 | MODULE_ALIAS("platform:"DRV_NAME); |