Commit | Line | Data |
---|---|---|
ef5fa1a4 | 1 | /* |
763f356c TI |
2 | * ALSA driver for RME Hammerfall DSP MADI audio interface(s) |
3 | * | |
4 | * Copyright (c) 2003 Winfried Ritsch (IEM) | |
5 | * code based on hdsp.c Paul Davis | |
6 | * Marcus Andersson | |
7 | * Thomas Charbonnel | |
3cee5a60 RB |
8 | * Modified 2006-06-01 for AES32 support by Remy Bruno |
9 | * <remy.bruno@trinnov.com> | |
763f356c | 10 | * |
0dca1793 AK |
11 | * Modified 2009-04-13 for proper metering by Florian Faber |
12 | * <faber@faberman.de> | |
13 | * | |
14 | * Modified 2009-04-14 for native float support by Florian Faber | |
15 | * <faber@faberman.de> | |
16 | * | |
17 | * Modified 2009-04-26 fixed bug in rms metering by Florian Faber | |
18 | * <faber@faberman.de> | |
19 | * | |
20 | * Modified 2009-04-30 added hw serial number support by Florian Faber | |
21 | * | |
22 | * Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth | |
23 | * | |
24 | * Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth | |
25 | * | |
763f356c TI |
26 | * This program is free software; you can redistribute it and/or modify |
27 | * it under the terms of the GNU General Public License as published by | |
28 | * the Free Software Foundation; either version 2 of the License, or | |
29 | * (at your option) any later version. | |
30 | * | |
31 | * This program is distributed in the hope that it will be useful, | |
32 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
33 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
34 | * GNU General Public License for more details. | |
35 | * | |
36 | * You should have received a copy of the GNU General Public License | |
37 | * along with this program; if not, write to the Free Software | |
38 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
39 | * | |
40 | */ | |
763f356c TI |
41 | #include <linux/init.h> |
42 | #include <linux/delay.h> | |
43 | #include <linux/interrupt.h> | |
44 | #include <linux/moduleparam.h> | |
45 | #include <linux/slab.h> | |
46 | #include <linux/pci.h> | |
3f7440a6 | 47 | #include <linux/math64.h> |
763f356c TI |
48 | #include <asm/io.h> |
49 | ||
50 | #include <sound/core.h> | |
51 | #include <sound/control.h> | |
52 | #include <sound/pcm.h> | |
0dca1793 | 53 | #include <sound/pcm_params.h> |
763f356c TI |
54 | #include <sound/info.h> |
55 | #include <sound/asoundef.h> | |
56 | #include <sound/rawmidi.h> | |
57 | #include <sound/hwdep.h> | |
58 | #include <sound/initval.h> | |
59 | ||
60 | #include <sound/hdspm.h> | |
61 | ||
62 | static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ | |
63 | static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ | |
64 | static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */ | |
65 | ||
763f356c TI |
66 | module_param_array(index, int, NULL, 0444); |
67 | MODULE_PARM_DESC(index, "Index value for RME HDSPM interface."); | |
68 | ||
69 | module_param_array(id, charp, NULL, 0444); | |
70 | MODULE_PARM_DESC(id, "ID string for RME HDSPM interface."); | |
71 | ||
72 | module_param_array(enable, bool, NULL, 0444); | |
73 | MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards."); | |
74 | ||
763f356c TI |
75 | |
76 | MODULE_AUTHOR | |
0dca1793 AK |
77 | ( |
78 | "Winfried Ritsch <ritsch_AT_iem.at>, " | |
79 | "Paul Davis <paul@linuxaudiosystems.com>, " | |
80 | "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, " | |
81 | "Remy Bruno <remy.bruno@trinnov.com>, " | |
82 | "Florian Faber <faberman@linuxproaudio.org>, " | |
83 | "Adrian Knoth <adi@drcomp.erfurt.thur.de>" | |
84 | ); | |
763f356c TI |
85 | MODULE_DESCRIPTION("RME HDSPM"); |
86 | MODULE_LICENSE("GPL"); | |
87 | MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}"); | |
88 | ||
0dca1793 | 89 | /* --- Write registers. --- |
763f356c TI |
90 | These are defined as byte-offsets from the iobase value. */ |
91 | ||
0dca1793 AK |
92 | #define HDSPM_WR_SETTINGS 0 |
93 | #define HDSPM_outputBufferAddress 32 | |
94 | #define HDSPM_inputBufferAddress 36 | |
763f356c TI |
95 | #define HDSPM_controlRegister 64 |
96 | #define HDSPM_interruptConfirmation 96 | |
97 | #define HDSPM_control2Reg 256 /* not in specs ???????? */ | |
ffb2c3c0 | 98 | #define HDSPM_freqReg 256 /* for AES32 */ |
0dca1793 AK |
99 | #define HDSPM_midiDataOut0 352 /* just believe in old code */ |
100 | #define HDSPM_midiDataOut1 356 | |
ffb2c3c0 | 101 | #define HDSPM_eeprom_wr 384 /* for AES32 */ |
763f356c TI |
102 | |
103 | /* DMA enable for 64 channels, only Bit 0 is relevant */ | |
0dca1793 | 104 | #define HDSPM_outputEnableBase 512 /* 512-767 input DMA */ |
763f356c TI |
105 | #define HDSPM_inputEnableBase 768 /* 768-1023 output DMA */ |
106 | ||
0dca1793 | 107 | /* 16 page addresses for each of the 64 channels DMA buffer in and out |
763f356c TI |
108 | (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */ |
109 | #define HDSPM_pageAddressBufferOut 8192 | |
110 | #define HDSPM_pageAddressBufferIn (HDSPM_pageAddressBufferOut+64*16*4) | |
111 | ||
112 | #define HDSPM_MADI_mixerBase 32768 /* 32768-65535 for 2x64x64 Fader */ | |
113 | ||
114 | #define HDSPM_MATRIX_MIXER_SIZE 8192 /* = 2*64*64 * 4 Byte => 32kB */ | |
115 | ||
116 | /* --- Read registers. --- | |
117 | These are defined as byte-offsets from the iobase value */ | |
118 | #define HDSPM_statusRegister 0 | |
3cee5a60 RB |
119 | /*#define HDSPM_statusRegister2 96 */ |
120 | /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at | |
121 | * offset 192, for AES32 *and* MADI | |
122 | * => need to check that offset 192 is working on MADI */ | |
123 | #define HDSPM_statusRegister2 192 | |
124 | #define HDSPM_timecodeRegister 128 | |
763f356c | 125 | |
0dca1793 AK |
126 | /* AIO, RayDAT */ |
127 | #define HDSPM_RD_STATUS_0 0 | |
128 | #define HDSPM_RD_STATUS_1 64 | |
129 | #define HDSPM_RD_STATUS_2 128 | |
130 | #define HDSPM_RD_STATUS_3 192 | |
131 | ||
132 | #define HDSPM_RD_TCO 256 | |
133 | #define HDSPM_RD_PLL_FREQ 512 | |
134 | #define HDSPM_WR_TCO 128 | |
135 | ||
136 | #define HDSPM_TCO1_TCO_lock 0x00000001 | |
137 | #define HDSPM_TCO1_WCK_Input_Range_LSB 0x00000002 | |
138 | #define HDSPM_TCO1_WCK_Input_Range_MSB 0x00000004 | |
139 | #define HDSPM_TCO1_LTC_Input_valid 0x00000008 | |
140 | #define HDSPM_TCO1_WCK_Input_valid 0x00000010 | |
141 | #define HDSPM_TCO1_Video_Input_Format_NTSC 0x00000020 | |
142 | #define HDSPM_TCO1_Video_Input_Format_PAL 0x00000040 | |
143 | ||
144 | #define HDSPM_TCO1_set_TC 0x00000100 | |
145 | #define HDSPM_TCO1_set_drop_frame_flag 0x00000200 | |
146 | #define HDSPM_TCO1_LTC_Format_LSB 0x00000400 | |
147 | #define HDSPM_TCO1_LTC_Format_MSB 0x00000800 | |
148 | ||
149 | #define HDSPM_TCO2_TC_run 0x00010000 | |
150 | #define HDSPM_TCO2_WCK_IO_ratio_LSB 0x00020000 | |
151 | #define HDSPM_TCO2_WCK_IO_ratio_MSB 0x00040000 | |
152 | #define HDSPM_TCO2_set_num_drop_frames_LSB 0x00080000 | |
153 | #define HDSPM_TCO2_set_num_drop_frames_MSB 0x00100000 | |
154 | #define HDSPM_TCO2_set_jam_sync 0x00200000 | |
155 | #define HDSPM_TCO2_set_flywheel 0x00400000 | |
156 | ||
157 | #define HDSPM_TCO2_set_01_4 0x01000000 | |
158 | #define HDSPM_TCO2_set_pull_down 0x02000000 | |
159 | #define HDSPM_TCO2_set_pull_up 0x04000000 | |
160 | #define HDSPM_TCO2_set_freq 0x08000000 | |
161 | #define HDSPM_TCO2_set_term_75R 0x10000000 | |
162 | #define HDSPM_TCO2_set_input_LSB 0x20000000 | |
163 | #define HDSPM_TCO2_set_input_MSB 0x40000000 | |
164 | #define HDSPM_TCO2_set_freq_from_app 0x80000000 | |
165 | ||
166 | ||
167 | #define HDSPM_midiDataOut0 352 | |
168 | #define HDSPM_midiDataOut1 356 | |
169 | #define HDSPM_midiDataOut2 368 | |
170 | ||
763f356c TI |
171 | #define HDSPM_midiDataIn0 360 |
172 | #define HDSPM_midiDataIn1 364 | |
0dca1793 AK |
173 | #define HDSPM_midiDataIn2 372 |
174 | #define HDSPM_midiDataIn3 376 | |
763f356c TI |
175 | |
176 | /* status is data bytes in MIDI-FIFO (0-128) */ | |
0dca1793 AK |
177 | #define HDSPM_midiStatusOut0 384 |
178 | #define HDSPM_midiStatusOut1 388 | |
179 | #define HDSPM_midiStatusOut2 400 | |
180 | ||
181 | #define HDSPM_midiStatusIn0 392 | |
182 | #define HDSPM_midiStatusIn1 396 | |
183 | #define HDSPM_midiStatusIn2 404 | |
184 | #define HDSPM_midiStatusIn3 408 | |
763f356c TI |
185 | |
186 | ||
187 | /* the meters are regular i/o-mapped registers, but offset | |
188 | considerably from the rest. the peak registers are reset | |
0dca1793 | 189 | when read; the least-significant 4 bits are full-scale counters; |
763f356c TI |
190 | the actual peak value is in the most-significant 24 bits. |
191 | */ | |
0dca1793 AK |
192 | |
193 | #define HDSPM_MADI_INPUT_PEAK 4096 | |
194 | #define HDSPM_MADI_PLAYBACK_PEAK 4352 | |
195 | #define HDSPM_MADI_OUTPUT_PEAK 4608 | |
196 | ||
197 | #define HDSPM_MADI_INPUT_RMS_L 6144 | |
198 | #define HDSPM_MADI_PLAYBACK_RMS_L 6400 | |
199 | #define HDSPM_MADI_OUTPUT_RMS_L 6656 | |
200 | ||
201 | #define HDSPM_MADI_INPUT_RMS_H 7168 | |
202 | #define HDSPM_MADI_PLAYBACK_RMS_H 7424 | |
203 | #define HDSPM_MADI_OUTPUT_RMS_H 7680 | |
763f356c TI |
204 | |
205 | /* --- Control Register bits --------- */ | |
206 | #define HDSPM_Start (1<<0) /* start engine */ | |
207 | ||
208 | #define HDSPM_Latency0 (1<<1) /* buffer size = 2^n */ | |
209 | #define HDSPM_Latency1 (1<<2) /* where n is defined */ | |
210 | #define HDSPM_Latency2 (1<<3) /* by Latency{2,1,0} */ | |
211 | ||
0dca1793 AK |
212 | #define HDSPM_ClockModeMaster (1<<4) /* 1=Master, 0=Autosync */ |
213 | #define HDSPM_c0Master 0x1 /* Master clock bit in settings | |
214 | register [RayDAT, AIO] */ | |
763f356c TI |
215 | |
216 | #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */ | |
217 | ||
218 | #define HDSPM_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */ | |
219 | #define HDSPM_Frequency1 (1<<7) /* 0=32kHz/64kHz */ | |
220 | #define HDSPM_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */ | |
3cee5a60 | 221 | #define HDSPM_QuadSpeed (1<<31) /* quad speed bit */ |
763f356c | 222 | |
3cee5a60 | 223 | #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */ |
763f356c | 224 | #define HDSPM_TX_64ch (1<<10) /* Output 64channel MODE=1, |
3cee5a60 RB |
225 | 56channelMODE=0 */ /* MADI ONLY*/ |
226 | #define HDSPM_Emphasis (1<<10) /* Emphasis */ /* AES32 ONLY */ | |
763f356c | 227 | |
0dca1793 | 228 | #define HDSPM_AutoInp (1<<11) /* Auto Input (takeover) == Safe Mode, |
3cee5a60 RB |
229 | 0=off, 1=on */ /* MADI ONLY */ |
230 | #define HDSPM_Dolby (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */ | |
763f356c | 231 | |
ef5fa1a4 TI |
232 | #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax |
233 | * -- MADI ONLY | |
234 | */ | |
763f356c TI |
235 | #define HDSPM_InputSelect1 (1<<15) /* should be 0 */ |
236 | ||
3cee5a60 RB |
237 | #define HDSPM_SyncRef2 (1<<13) |
238 | #define HDSPM_SyncRef3 (1<<25) | |
763f356c | 239 | |
3cee5a60 | 240 | #define HDSPM_SMUX (1<<18) /* Frame ??? */ /* MADI ONY */ |
0dca1793 | 241 | #define HDSPM_clr_tms (1<<19) /* clear track marker, do not use |
763f356c TI |
242 | AES additional bits in |
243 | lower 5 Audiodatabits ??? */ | |
3cee5a60 RB |
244 | #define HDSPM_taxi_reset (1<<20) /* ??? */ /* MADI ONLY ? */ |
245 | #define HDSPM_WCK48 (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */ | |
763f356c | 246 | |
0dca1793 AK |
247 | #define HDSPM_Midi0InterruptEnable 0x0400000 |
248 | #define HDSPM_Midi1InterruptEnable 0x0800000 | |
249 | #define HDSPM_Midi2InterruptEnable 0x0200000 | |
250 | #define HDSPM_Midi3InterruptEnable 0x4000000 | |
763f356c TI |
251 | |
252 | #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */ | |
0dca1793 | 253 | #define HDSPe_FLOAT_FORMAT 0x2000000 |
763f356c | 254 | |
3cee5a60 RB |
255 | #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */ |
256 | #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */ | |
257 | #define HDSPM_QS_QuadWire (1<<28) /* AES32 ONLY */ | |
258 | ||
259 | #define HDSPM_wclk_sel (1<<30) | |
763f356c TI |
260 | |
261 | /* --- bit helper defines */ | |
262 | #define HDSPM_LatencyMask (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2) | |
ef5fa1a4 TI |
263 | #define HDSPM_FrequencyMask (HDSPM_Frequency0|HDSPM_Frequency1|\ |
264 | HDSPM_DoubleSpeed|HDSPM_QuadSpeed) | |
763f356c TI |
265 | #define HDSPM_InputMask (HDSPM_InputSelect0|HDSPM_InputSelect1) |
266 | #define HDSPM_InputOptical 0 | |
267 | #define HDSPM_InputCoaxial (HDSPM_InputSelect0) | |
ef5fa1a4 TI |
268 | #define HDSPM_SyncRefMask (HDSPM_SyncRef0|HDSPM_SyncRef1|\ |
269 | HDSPM_SyncRef2|HDSPM_SyncRef3) | |
763f356c | 270 | |
0dca1793 AK |
271 | #define HDSPM_c0_SyncRef0 0x2 |
272 | #define HDSPM_c0_SyncRef1 0x4 | |
273 | #define HDSPM_c0_SyncRef2 0x8 | |
274 | #define HDSPM_c0_SyncRef3 0x10 | |
275 | #define HDSPM_c0_SyncRefMask (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\ | |
276 | HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3) | |
277 | ||
278 | #define HDSPM_SYNC_FROM_WORD 0 /* Preferred sync reference */ | |
279 | #define HDSPM_SYNC_FROM_MADI 1 /* choices - used by "pref_sync_ref" */ | |
280 | #define HDSPM_SYNC_FROM_TCO 2 | |
281 | #define HDSPM_SYNC_FROM_SYNC_IN 3 | |
763f356c TI |
282 | |
283 | #define HDSPM_Frequency32KHz HDSPM_Frequency0 | |
284 | #define HDSPM_Frequency44_1KHz HDSPM_Frequency1 | |
285 | #define HDSPM_Frequency48KHz (HDSPM_Frequency1|HDSPM_Frequency0) | |
286 | #define HDSPM_Frequency64KHz (HDSPM_DoubleSpeed|HDSPM_Frequency0) | |
287 | #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1) | |
ef5fa1a4 TI |
288 | #define HDSPM_Frequency96KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1|\ |
289 | HDSPM_Frequency0) | |
3cee5a60 RB |
290 | #define HDSPM_Frequency128KHz (HDSPM_QuadSpeed|HDSPM_Frequency0) |
291 | #define HDSPM_Frequency176_4KHz (HDSPM_QuadSpeed|HDSPM_Frequency1) | |
ef5fa1a4 TI |
292 | #define HDSPM_Frequency192KHz (HDSPM_QuadSpeed|HDSPM_Frequency1|\ |
293 | HDSPM_Frequency0) | |
763f356c | 294 | |
763f356c TI |
295 | |
296 | /* Synccheck Status */ | |
297 | #define HDSPM_SYNC_CHECK_NO_LOCK 0 | |
298 | #define HDSPM_SYNC_CHECK_LOCK 1 | |
299 | #define HDSPM_SYNC_CHECK_SYNC 2 | |
300 | ||
301 | /* AutoSync References - used by "autosync_ref" control switch */ | |
302 | #define HDSPM_AUTOSYNC_FROM_WORD 0 | |
303 | #define HDSPM_AUTOSYNC_FROM_MADI 1 | |
0dca1793 AK |
304 | #define HDSPM_AUTOSYNC_FROM_TCO 2 |
305 | #define HDSPM_AUTOSYNC_FROM_SYNC_IN 3 | |
306 | #define HDSPM_AUTOSYNC_FROM_NONE 4 | |
763f356c TI |
307 | |
308 | /* Possible sources of MADI input */ | |
309 | #define HDSPM_OPTICAL 0 /* optical */ | |
310 | #define HDSPM_COAXIAL 1 /* BNC */ | |
311 | ||
312 | #define hdspm_encode_latency(x) (((x)<<1) & HDSPM_LatencyMask) | |
0dca1793 | 313 | #define hdspm_decode_latency(x) ((((x) & HDSPM_LatencyMask)>>1)) |
763f356c TI |
314 | |
315 | #define hdspm_encode_in(x) (((x)&0x3)<<14) | |
316 | #define hdspm_decode_in(x) (((x)>>14)&0x3) | |
317 | ||
318 | /* --- control2 register bits --- */ | |
319 | #define HDSPM_TMS (1<<0) | |
320 | #define HDSPM_TCK (1<<1) | |
321 | #define HDSPM_TDI (1<<2) | |
322 | #define HDSPM_JTAG (1<<3) | |
323 | #define HDSPM_PWDN (1<<4) | |
324 | #define HDSPM_PROGRAM (1<<5) | |
325 | #define HDSPM_CONFIG_MODE_0 (1<<6) | |
326 | #define HDSPM_CONFIG_MODE_1 (1<<7) | |
327 | /*#define HDSPM_VERSION_BIT (1<<8) not defined any more*/ | |
328 | #define HDSPM_BIGENDIAN_MODE (1<<9) | |
329 | #define HDSPM_RD_MULTIPLE (1<<10) | |
330 | ||
3cee5a60 | 331 | /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and |
ef5fa1a4 TI |
332 | that do not conflict with specific bits for AES32 seem to be valid also |
333 | for the AES32 | |
334 | */ | |
763f356c | 335 | #define HDSPM_audioIRQPending (1<<0) /* IRQ is high and pending */ |
ef5fa1a4 TI |
336 | #define HDSPM_RX_64ch (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */ |
337 | #define HDSPM_AB_int (1<<2) /* InputChannel Opt=0, Coax=1 | |
338 | * (like inp0) | |
339 | */ | |
0dca1793 | 340 | |
763f356c | 341 | #define HDSPM_madiLock (1<<3) /* MADI Locked =1, no=0 */ |
0dca1793 AK |
342 | #define HDSPM_madiSync (1<<18) /* MADI is in sync */ |
343 | ||
344 | #define HDSPM_tcoLock 0x00000020 /* Optional TCO locked status FOR HDSPe MADI! */ | |
345 | #define HDSPM_tcoSync 0x10000000 /* Optional TCO sync status */ | |
346 | ||
347 | #define HDSPM_syncInLock 0x00010000 /* Sync In lock status FOR HDSPe MADI! */ | |
348 | #define HDSPM_syncInSync 0x00020000 /* Sync In sync status FOR HDSPe MADI! */ | |
763f356c TI |
349 | |
350 | #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */ | |
0dca1793 AK |
351 | /* since 64byte accurate, last 6 bits are not used */ |
352 | ||
353 | ||
763f356c | 354 | |
763f356c TI |
355 | #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */ |
356 | ||
357 | #define HDSPM_madiFreq0 (1<<22) /* system freq 0=error */ | |
358 | #define HDSPM_madiFreq1 (1<<23) /* 1=32, 2=44.1 3=48 */ | |
359 | #define HDSPM_madiFreq2 (1<<24) /* 4=64, 5=88.2 6=96 */ | |
360 | #define HDSPM_madiFreq3 (1<<25) /* 7=128, 8=176.4 9=192 */ | |
361 | ||
ef5fa1a4 TI |
362 | #define HDSPM_BufferID (1<<26) /* (Double)Buffer ID toggles with |
363 | * Interrupt | |
364 | */ | |
0dca1793 AK |
365 | #define HDSPM_tco_detect 0x08000000 |
366 | #define HDSPM_tco_lock 0x20000000 | |
367 | ||
368 | #define HDSPM_s2_tco_detect 0x00000040 | |
369 | #define HDSPM_s2_AEBO_D 0x00000080 | |
370 | #define HDSPM_s2_AEBI_D 0x00000100 | |
371 | ||
372 | ||
373 | #define HDSPM_midi0IRQPending 0x40000000 | |
374 | #define HDSPM_midi1IRQPending 0x80000000 | |
375 | #define HDSPM_midi2IRQPending 0x20000000 | |
376 | #define HDSPM_midi2IRQPendingAES 0x00000020 | |
377 | #define HDSPM_midi3IRQPending 0x00200000 | |
763f356c TI |
378 | |
379 | /* --- status bit helpers */ | |
ef5fa1a4 TI |
380 | #define HDSPM_madiFreqMask (HDSPM_madiFreq0|HDSPM_madiFreq1|\ |
381 | HDSPM_madiFreq2|HDSPM_madiFreq3) | |
763f356c TI |
382 | #define HDSPM_madiFreq32 (HDSPM_madiFreq0) |
383 | #define HDSPM_madiFreq44_1 (HDSPM_madiFreq1) | |
384 | #define HDSPM_madiFreq48 (HDSPM_madiFreq0|HDSPM_madiFreq1) | |
385 | #define HDSPM_madiFreq64 (HDSPM_madiFreq2) | |
386 | #define HDSPM_madiFreq88_2 (HDSPM_madiFreq0|HDSPM_madiFreq2) | |
387 | #define HDSPM_madiFreq96 (HDSPM_madiFreq1|HDSPM_madiFreq2) | |
388 | #define HDSPM_madiFreq128 (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2) | |
389 | #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3) | |
390 | #define HDSPM_madiFreq192 (HDSPM_madiFreq3|HDSPM_madiFreq0) | |
391 | ||
3cee5a60 | 392 | /* Status2 Register bits */ /* MADI ONLY */ |
763f356c TI |
393 | |
394 | #define HDSPM_version0 (1<<0) /* not realy defined but I guess */ | |
395 | #define HDSPM_version1 (1<<1) /* in former cards it was ??? */ | |
396 | #define HDSPM_version2 (1<<2) | |
397 | ||
398 | #define HDSPM_wcLock (1<<3) /* Wordclock is detected and locked */ | |
399 | #define HDSPM_wcSync (1<<4) /* Wordclock is in sync with systemclock */ | |
400 | ||
401 | #define HDSPM_wc_freq0 (1<<5) /* input freq detected via autosync */ | |
402 | #define HDSPM_wc_freq1 (1<<6) /* 001=32, 010==44.1, 011=48, */ | |
403 | #define HDSPM_wc_freq2 (1<<7) /* 100=64, 101=88.2, 110=96, */ | |
404 | /* missing Bit for 111=128, 1000=176.4, 1001=192 */ | |
405 | ||
0dca1793 AK |
406 | #define HDSPM_SyncRef0 0x10000 /* Sync Reference */ |
407 | #define HDSPM_SyncRef1 0x20000 | |
408 | ||
409 | #define HDSPM_SelSyncRef0 (1<<8) /* AutoSync Source */ | |
763f356c TI |
410 | #define HDSPM_SelSyncRef1 (1<<9) /* 000=word, 001=MADI, */ |
411 | #define HDSPM_SelSyncRef2 (1<<10) /* 111=no valid signal */ | |
412 | ||
413 | #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync) | |
414 | ||
415 | #define HDSPM_wcFreqMask (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2) | |
416 | #define HDSPM_wcFreq32 (HDSPM_wc_freq0) | |
417 | #define HDSPM_wcFreq44_1 (HDSPM_wc_freq1) | |
418 | #define HDSPM_wcFreq48 (HDSPM_wc_freq0|HDSPM_wc_freq1) | |
419 | #define HDSPM_wcFreq64 (HDSPM_wc_freq2) | |
420 | #define HDSPM_wcFreq88_2 (HDSPM_wc_freq0|HDSPM_wc_freq2) | |
421 | #define HDSPM_wcFreq96 (HDSPM_wc_freq1|HDSPM_wc_freq2) | |
422 | ||
0dca1793 AK |
423 | #define HDSPM_status1_F_0 0x0400000 |
424 | #define HDSPM_status1_F_1 0x0800000 | |
425 | #define HDSPM_status1_F_2 0x1000000 | |
426 | #define HDSPM_status1_F_3 0x2000000 | |
427 | #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3) | |
428 | ||
763f356c | 429 | |
ef5fa1a4 TI |
430 | #define HDSPM_SelSyncRefMask (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\ |
431 | HDSPM_SelSyncRef2) | |
763f356c TI |
432 | #define HDSPM_SelSyncRef_WORD 0 |
433 | #define HDSPM_SelSyncRef_MADI (HDSPM_SelSyncRef0) | |
0dca1793 AK |
434 | #define HDSPM_SelSyncRef_TCO (HDSPM_SelSyncRef1) |
435 | #define HDSPM_SelSyncRef_SyncIn (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1) | |
ef5fa1a4 TI |
436 | #define HDSPM_SelSyncRef_NVALID (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\ |
437 | HDSPM_SelSyncRef2) | |
763f356c | 438 | |
3cee5a60 RB |
439 | /* |
440 | For AES32, bits for status, status2 and timecode are different | |
441 | */ | |
442 | /* status */ | |
443 | #define HDSPM_AES32_wcLock 0x0200000 | |
444 | #define HDSPM_AES32_wcFreq_bit 22 | |
0dca1793 | 445 | /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function |
3cee5a60 RB |
446 | HDSPM_bit2freq */ |
447 | #define HDSPM_AES32_syncref_bit 16 | |
448 | /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */ | |
449 | ||
450 | #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0 | |
451 | #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1 | |
452 | #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2 | |
453 | #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3 | |
454 | #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4 | |
455 | #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5 | |
456 | #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6 | |
457 | #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7 | |
458 | #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8 | |
6534599d | 459 | #define HDSPM_AES32_AUTOSYNC_FROM_NONE 9 |
3cee5a60 RB |
460 | |
461 | /* status2 */ | |
462 | /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */ | |
463 | #define HDSPM_LockAES 0x80 | |
464 | #define HDSPM_LockAES1 0x80 | |
465 | #define HDSPM_LockAES2 0x40 | |
466 | #define HDSPM_LockAES3 0x20 | |
467 | #define HDSPM_LockAES4 0x10 | |
468 | #define HDSPM_LockAES5 0x8 | |
469 | #define HDSPM_LockAES6 0x4 | |
470 | #define HDSPM_LockAES7 0x2 | |
471 | #define HDSPM_LockAES8 0x1 | |
472 | /* | |
473 | Timecode | |
474 | After windows driver sources, bits 4*i to 4*i+3 give the input frequency on | |
475 | AES i+1 | |
476 | bits 3210 | |
477 | 0001 32kHz | |
478 | 0010 44.1kHz | |
479 | 0011 48kHz | |
480 | 0100 64kHz | |
481 | 0101 88.2kHz | |
482 | 0110 96kHz | |
483 | 0111 128kHz | |
484 | 1000 176.4kHz | |
485 | 1001 192kHz | |
486 | NB: Timecode register doesn't seem to work on AES32 card revision 230 | |
487 | */ | |
488 | ||
763f356c TI |
489 | /* Mixer Values */ |
490 | #define UNITY_GAIN 32768 /* = 65536/2 */ | |
491 | #define MINUS_INFINITY_GAIN 0 | |
492 | ||
763f356c TI |
493 | /* Number of channels for different Speed Modes */ |
494 | #define MADI_SS_CHANNELS 64 | |
495 | #define MADI_DS_CHANNELS 32 | |
496 | #define MADI_QS_CHANNELS 16 | |
497 | ||
0dca1793 AK |
498 | #define RAYDAT_SS_CHANNELS 36 |
499 | #define RAYDAT_DS_CHANNELS 20 | |
500 | #define RAYDAT_QS_CHANNELS 12 | |
501 | ||
502 | #define AIO_IN_SS_CHANNELS 14 | |
503 | #define AIO_IN_DS_CHANNELS 10 | |
504 | #define AIO_IN_QS_CHANNELS 8 | |
505 | #define AIO_OUT_SS_CHANNELS 16 | |
506 | #define AIO_OUT_DS_CHANNELS 12 | |
507 | #define AIO_OUT_QS_CHANNELS 10 | |
508 | ||
d2d10a21 AK |
509 | #define AES32_CHANNELS 16 |
510 | ||
763f356c TI |
511 | /* the size of a substream (1 mono data stream) */ |
512 | #define HDSPM_CHANNEL_BUFFER_SAMPLES (16*1024) | |
513 | #define HDSPM_CHANNEL_BUFFER_BYTES (4*HDSPM_CHANNEL_BUFFER_SAMPLES) | |
514 | ||
515 | /* the size of the area we need to allocate for DMA transfers. the | |
516 | size is the same regardless of the number of channels, and | |
0dca1793 | 517 | also the latency to use. |
763f356c TI |
518 | for one direction !!! |
519 | */ | |
ffb2c3c0 | 520 | #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES) |
763f356c TI |
521 | #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024) |
522 | ||
3cee5a60 | 523 | /* revisions >= 230 indicate AES32 card */ |
0dca1793 AK |
524 | #define HDSPM_MADI_REV 210 |
525 | #define HDSPM_RAYDAT_REV 211 | |
526 | #define HDSPM_AIO_REV 212 | |
527 | #define HDSPM_MADIFACE_REV 213 | |
528 | #define HDSPM_AES_REV 240 | |
3cee5a60 | 529 | |
6534599d RB |
530 | /* speed factor modes */ |
531 | #define HDSPM_SPEED_SINGLE 0 | |
532 | #define HDSPM_SPEED_DOUBLE 1 | |
533 | #define HDSPM_SPEED_QUAD 2 | |
0dca1793 | 534 | |
6534599d RB |
535 | /* names for speed modes */ |
536 | static char *hdspm_speed_names[] = { "single", "double", "quad" }; | |
537 | ||
0dca1793 AK |
538 | static char *texts_autosync_aes_tco[] = { "Word Clock", |
539 | "AES1", "AES2", "AES3", "AES4", | |
540 | "AES5", "AES6", "AES7", "AES8", | |
541 | "TCO" }; | |
542 | static char *texts_autosync_aes[] = { "Word Clock", | |
543 | "AES1", "AES2", "AES3", "AES4", | |
544 | "AES5", "AES6", "AES7", "AES8" }; | |
545 | static char *texts_autosync_madi_tco[] = { "Word Clock", | |
546 | "MADI", "TCO", "Sync In" }; | |
547 | static char *texts_autosync_madi[] = { "Word Clock", | |
548 | "MADI", "Sync In" }; | |
549 | ||
550 | static char *texts_autosync_raydat_tco[] = { | |
551 | "Word Clock", | |
552 | "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4", | |
553 | "AES", "SPDIF", "TCO", "Sync In" | |
554 | }; | |
555 | static char *texts_autosync_raydat[] = { | |
556 | "Word Clock", | |
557 | "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4", | |
558 | "AES", "SPDIF", "Sync In" | |
559 | }; | |
560 | static char *texts_autosync_aio_tco[] = { | |
561 | "Word Clock", | |
562 | "ADAT", "AES", "SPDIF", "TCO", "Sync In" | |
563 | }; | |
564 | static char *texts_autosync_aio[] = { "Word Clock", | |
565 | "ADAT", "AES", "SPDIF", "Sync In" }; | |
566 | ||
567 | static char *texts_freq[] = { | |
568 | "No Lock", | |
569 | "32 kHz", | |
570 | "44.1 kHz", | |
571 | "48 kHz", | |
572 | "64 kHz", | |
573 | "88.2 kHz", | |
574 | "96 kHz", | |
575 | "128 kHz", | |
576 | "176.4 kHz", | |
577 | "192 kHz" | |
578 | }; | |
579 | ||
0dca1793 AK |
580 | static char *texts_ports_madi[] = { |
581 | "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6", | |
582 | "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12", | |
583 | "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18", | |
584 | "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24", | |
585 | "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30", | |
586 | "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36", | |
587 | "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42", | |
588 | "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48", | |
589 | "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54", | |
590 | "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60", | |
591 | "MADI.61", "MADI.62", "MADI.63", "MADI.64", | |
592 | }; | |
593 | ||
594 | ||
595 | static char *texts_ports_raydat_ss[] = { | |
596 | "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6", | |
597 | "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4", | |
598 | "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2", | |
599 | "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8", | |
600 | "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6", | |
601 | "ADAT4.7", "ADAT4.8", | |
602 | "AES.L", "AES.R", | |
603 | "SPDIF.L", "SPDIF.R" | |
604 | }; | |
605 | ||
606 | static char *texts_ports_raydat_ds[] = { | |
607 | "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", | |
608 | "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4", | |
609 | "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4", | |
610 | "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", | |
611 | "AES.L", "AES.R", | |
612 | "SPDIF.L", "SPDIF.R" | |
613 | }; | |
614 | ||
615 | static char *texts_ports_raydat_qs[] = { | |
616 | "ADAT1.1", "ADAT1.2", | |
617 | "ADAT2.1", "ADAT2.2", | |
618 | "ADAT3.1", "ADAT3.2", | |
619 | "ADAT4.1", "ADAT4.2", | |
620 | "AES.L", "AES.R", | |
621 | "SPDIF.L", "SPDIF.R" | |
622 | }; | |
623 | ||
624 | ||
625 | static char *texts_ports_aio_in_ss[] = { | |
626 | "Analogue.L", "Analogue.R", | |
627 | "AES.L", "AES.R", | |
628 | "SPDIF.L", "SPDIF.R", | |
629 | "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6", | |
630 | "ADAT.7", "ADAT.8" | |
631 | }; | |
632 | ||
633 | static char *texts_ports_aio_out_ss[] = { | |
634 | "Analogue.L", "Analogue.R", | |
635 | "AES.L", "AES.R", | |
636 | "SPDIF.L", "SPDIF.R", | |
637 | "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6", | |
638 | "ADAT.7", "ADAT.8", | |
639 | "Phone.L", "Phone.R" | |
640 | }; | |
641 | ||
642 | static char *texts_ports_aio_in_ds[] = { | |
643 | "Analogue.L", "Analogue.R", | |
644 | "AES.L", "AES.R", | |
645 | "SPDIF.L", "SPDIF.R", | |
646 | "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4" | |
647 | }; | |
648 | ||
649 | static char *texts_ports_aio_out_ds[] = { | |
650 | "Analogue.L", "Analogue.R", | |
651 | "AES.L", "AES.R", | |
652 | "SPDIF.L", "SPDIF.R", | |
653 | "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", | |
654 | "Phone.L", "Phone.R" | |
655 | }; | |
656 | ||
657 | static char *texts_ports_aio_in_qs[] = { | |
658 | "Analogue.L", "Analogue.R", | |
659 | "AES.L", "AES.R", | |
660 | "SPDIF.L", "SPDIF.R", | |
661 | "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4" | |
662 | }; | |
663 | ||
664 | static char *texts_ports_aio_out_qs[] = { | |
665 | "Analogue.L", "Analogue.R", | |
666 | "AES.L", "AES.R", | |
667 | "SPDIF.L", "SPDIF.R", | |
668 | "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", | |
669 | "Phone.L", "Phone.R" | |
670 | }; | |
671 | ||
432d2500 AK |
672 | static char *texts_ports_aes32[] = { |
673 | "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7", | |
674 | "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14", | |
675 | "AES.15", "AES.16" | |
676 | }; | |
677 | ||
55a57606 AK |
678 | /* These tables map the ALSA channels 1..N to the channels that we |
679 | need to use in order to find the relevant channel buffer. RME | |
680 | refers to this kind of mapping as between "the ADAT channel and | |
681 | the DMA channel." We index it using the logical audio channel, | |
682 | and the value is the DMA channel (i.e. channel buffer number) | |
683 | where the data for that channel can be read/written from/to. | |
684 | */ | |
685 | ||
686 | static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = { | |
687 | 0, 1, 2, 3, 4, 5, 6, 7, | |
688 | 8, 9, 10, 11, 12, 13, 14, 15, | |
689 | 16, 17, 18, 19, 20, 21, 22, 23, | |
690 | 24, 25, 26, 27, 28, 29, 30, 31, | |
691 | 32, 33, 34, 35, 36, 37, 38, 39, | |
692 | 40, 41, 42, 43, 44, 45, 46, 47, | |
693 | 48, 49, 50, 51, 52, 53, 54, 55, | |
694 | 56, 57, 58, 59, 60, 61, 62, 63 | |
695 | }; | |
696 | ||
55a57606 AK |
697 | static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = { |
698 | 4, 5, 6, 7, 8, 9, 10, 11, /* ADAT 1 */ | |
699 | 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */ | |
700 | 20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */ | |
701 | 28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */ | |
702 | 0, 1, /* AES */ | |
703 | 2, 3, /* SPDIF */ | |
704 | -1, -1, -1, -1, | |
705 | -1, -1, -1, -1, -1, -1, -1, -1, | |
706 | -1, -1, -1, -1, -1, -1, -1, -1, | |
707 | -1, -1, -1, -1, -1, -1, -1, -1, | |
708 | }; | |
709 | ||
710 | static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = { | |
711 | 4, 5, 6, 7, /* ADAT 1 */ | |
712 | 8, 9, 10, 11, /* ADAT 2 */ | |
713 | 12, 13, 14, 15, /* ADAT 3 */ | |
714 | 16, 17, 18, 19, /* ADAT 4 */ | |
715 | 0, 1, /* AES */ | |
716 | 2, 3, /* SPDIF */ | |
717 | -1, -1, -1, -1, | |
718 | -1, -1, -1, -1, -1, -1, -1, -1, | |
719 | -1, -1, -1, -1, -1, -1, -1, -1, | |
720 | -1, -1, -1, -1, -1, -1, -1, -1, | |
721 | -1, -1, -1, -1, -1, -1, -1, -1, | |
722 | -1, -1, -1, -1, -1, -1, -1, -1, | |
723 | }; | |
724 | ||
725 | static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = { | |
726 | 4, 5, /* ADAT 1 */ | |
727 | 6, 7, /* ADAT 2 */ | |
728 | 8, 9, /* ADAT 3 */ | |
729 | 10, 11, /* ADAT 4 */ | |
730 | 0, 1, /* AES */ | |
731 | 2, 3, /* SPDIF */ | |
732 | -1, -1, -1, -1, | |
733 | -1, -1, -1, -1, -1, -1, -1, -1, | |
734 | -1, -1, -1, -1, -1, -1, -1, -1, | |
735 | -1, -1, -1, -1, -1, -1, -1, -1, | |
736 | -1, -1, -1, -1, -1, -1, -1, -1, | |
737 | -1, -1, -1, -1, -1, -1, -1, -1, | |
738 | -1, -1, -1, -1, -1, -1, -1, -1, | |
739 | }; | |
740 | ||
741 | static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = { | |
742 | 0, 1, /* line in */ | |
743 | 8, 9, /* aes in, */ | |
744 | 10, 11, /* spdif in */ | |
745 | 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */ | |
746 | -1, -1, | |
747 | -1, -1, -1, -1, -1, -1, -1, -1, | |
748 | -1, -1, -1, -1, -1, -1, -1, -1, | |
749 | -1, -1, -1, -1, -1, -1, -1, -1, | |
750 | -1, -1, -1, -1, -1, -1, -1, -1, | |
751 | -1, -1, -1, -1, -1, -1, -1, -1, | |
752 | -1, -1, -1, -1, -1, -1, -1, -1, | |
753 | }; | |
754 | ||
755 | static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = { | |
756 | 0, 1, /* line out */ | |
757 | 8, 9, /* aes out */ | |
758 | 10, 11, /* spdif out */ | |
759 | 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */ | |
760 | 6, 7, /* phone out */ | |
761 | -1, -1, -1, -1, -1, -1, -1, -1, | |
762 | -1, -1, -1, -1, -1, -1, -1, -1, | |
763 | -1, -1, -1, -1, -1, -1, -1, -1, | |
764 | -1, -1, -1, -1, -1, -1, -1, -1, | |
765 | -1, -1, -1, -1, -1, -1, -1, -1, | |
766 | -1, -1, -1, -1, -1, -1, -1, -1, | |
767 | }; | |
768 | ||
769 | static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = { | |
770 | 0, 1, /* line in */ | |
771 | 8, 9, /* aes in */ | |
772 | 10, 11, /* spdif in */ | |
773 | 12, 14, 16, 18, /* adat in */ | |
774 | -1, -1, -1, -1, -1, -1, | |
775 | -1, -1, -1, -1, -1, -1, -1, -1, | |
776 | -1, -1, -1, -1, -1, -1, -1, -1, | |
777 | -1, -1, -1, -1, -1, -1, -1, -1, | |
778 | -1, -1, -1, -1, -1, -1, -1, -1, | |
779 | -1, -1, -1, -1, -1, -1, -1, -1, | |
780 | -1, -1, -1, -1, -1, -1, -1, -1 | |
781 | }; | |
782 | ||
783 | static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = { | |
784 | 0, 1, /* line out */ | |
785 | 8, 9, /* aes out */ | |
786 | 10, 11, /* spdif out */ | |
787 | 12, 14, 16, 18, /* adat out */ | |
788 | 6, 7, /* phone out */ | |
789 | -1, -1, -1, -1, | |
790 | -1, -1, -1, -1, -1, -1, -1, -1, | |
791 | -1, -1, -1, -1, -1, -1, -1, -1, | |
792 | -1, -1, -1, -1, -1, -1, -1, -1, | |
793 | -1, -1, -1, -1, -1, -1, -1, -1, | |
794 | -1, -1, -1, -1, -1, -1, -1, -1, | |
795 | -1, -1, -1, -1, -1, -1, -1, -1 | |
796 | }; | |
797 | ||
798 | static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = { | |
799 | 0, 1, /* line in */ | |
800 | 8, 9, /* aes in */ | |
801 | 10, 11, /* spdif in */ | |
802 | 12, 16, /* adat in */ | |
803 | -1, -1, -1, -1, -1, -1, -1, -1, | |
804 | -1, -1, -1, -1, -1, -1, -1, -1, | |
805 | -1, -1, -1, -1, -1, -1, -1, -1, | |
806 | -1, -1, -1, -1, -1, -1, -1, -1, | |
807 | -1, -1, -1, -1, -1, -1, -1, -1, | |
808 | -1, -1, -1, -1, -1, -1, -1, -1, | |
809 | -1, -1, -1, -1, -1, -1, -1, -1 | |
810 | }; | |
811 | ||
812 | static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = { | |
813 | 0, 1, /* line out */ | |
814 | 8, 9, /* aes out */ | |
815 | 10, 11, /* spdif out */ | |
816 | 12, 16, /* adat out */ | |
817 | 6, 7, /* phone out */ | |
818 | -1, -1, -1, -1, -1, -1, | |
819 | -1, -1, -1, -1, -1, -1, -1, -1, | |
820 | -1, -1, -1, -1, -1, -1, -1, -1, | |
821 | -1, -1, -1, -1, -1, -1, -1, -1, | |
822 | -1, -1, -1, -1, -1, -1, -1, -1, | |
823 | -1, -1, -1, -1, -1, -1, -1, -1, | |
824 | -1, -1, -1, -1, -1, -1, -1, -1 | |
825 | }; | |
826 | ||
432d2500 AK |
827 | static char channel_map_aes32[HDSPM_MAX_CHANNELS] = { |
828 | 0, 1, 2, 3, 4, 5, 6, 7, | |
829 | 8, 9, 10, 11, 12, 13, 14, 15, | |
830 | -1, -1, -1, -1, -1, -1, -1, -1, | |
831 | -1, -1, -1, -1, -1, -1, -1, -1, | |
832 | -1, -1, -1, -1, -1, -1, -1, -1, | |
833 | -1, -1, -1, -1, -1, -1, -1, -1, | |
834 | -1, -1, -1, -1, -1, -1, -1, -1, | |
835 | -1, -1, -1, -1, -1, -1, -1, -1 | |
836 | }; | |
837 | ||
98274f07 TI |
838 | struct hdspm_midi { |
839 | struct hdspm *hdspm; | |
763f356c | 840 | int id; |
98274f07 TI |
841 | struct snd_rawmidi *rmidi; |
842 | struct snd_rawmidi_substream *input; | |
843 | struct snd_rawmidi_substream *output; | |
763f356c TI |
844 | char istimer; /* timer in use */ |
845 | struct timer_list timer; | |
846 | spinlock_t lock; | |
847 | int pending; | |
0dca1793 AK |
848 | int dataIn; |
849 | int statusIn; | |
850 | int dataOut; | |
851 | int statusOut; | |
852 | int ie; | |
853 | int irq; | |
854 | }; | |
855 | ||
856 | struct hdspm_tco { | |
857 | int input; | |
858 | int framerate; | |
859 | int wordclock; | |
860 | int samplerate; | |
861 | int pull; | |
862 | int term; /* 0 = off, 1 = on */ | |
763f356c TI |
863 | }; |
864 | ||
98274f07 | 865 | struct hdspm { |
763f356c | 866 | spinlock_t lock; |
ef5fa1a4 TI |
867 | /* only one playback and/or capture stream */ |
868 | struct snd_pcm_substream *capture_substream; | |
869 | struct snd_pcm_substream *playback_substream; | |
763f356c TI |
870 | |
871 | char *card_name; /* for procinfo */ | |
3cee5a60 RB |
872 | unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/ |
873 | ||
0dca1793 | 874 | uint8_t io_type; |
763f356c | 875 | |
763f356c TI |
876 | int monitor_outs; /* set up monitoring outs init flag */ |
877 | ||
878 | u32 control_register; /* cached value */ | |
879 | u32 control2_register; /* cached value */ | |
0dca1793 | 880 | u32 settings_register; |
763f356c | 881 | |
0dca1793 | 882 | struct hdspm_midi midi[4]; |
763f356c TI |
883 | struct tasklet_struct midi_tasklet; |
884 | ||
885 | size_t period_bytes; | |
0dca1793 AK |
886 | unsigned char ss_in_channels; |
887 | unsigned char ds_in_channels; | |
888 | unsigned char qs_in_channels; | |
889 | unsigned char ss_out_channels; | |
890 | unsigned char ds_out_channels; | |
891 | unsigned char qs_out_channels; | |
892 | ||
893 | unsigned char max_channels_in; | |
894 | unsigned char max_channels_out; | |
895 | ||
896 | char *channel_map_in; | |
897 | char *channel_map_out; | |
898 | ||
899 | char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs; | |
900 | char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs; | |
901 | ||
902 | char **port_names_in; | |
903 | char **port_names_out; | |
904 | ||
905 | char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs; | |
906 | char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs; | |
763f356c TI |
907 | |
908 | unsigned char *playback_buffer; /* suitably aligned address */ | |
909 | unsigned char *capture_buffer; /* suitably aligned address */ | |
910 | ||
911 | pid_t capture_pid; /* process id which uses capture */ | |
912 | pid_t playback_pid; /* process id which uses capture */ | |
913 | int running; /* running status */ | |
914 | ||
915 | int last_external_sample_rate; /* samplerate mystic ... */ | |
916 | int last_internal_sample_rate; | |
917 | int system_sample_rate; | |
918 | ||
763f356c TI |
919 | int dev; /* Hardware vars... */ |
920 | int irq; | |
921 | unsigned long port; | |
922 | void __iomem *iobase; | |
923 | ||
924 | int irq_count; /* for debug */ | |
0dca1793 | 925 | int midiPorts; |
763f356c | 926 | |
98274f07 TI |
927 | struct snd_card *card; /* one card */ |
928 | struct snd_pcm *pcm; /* has one pcm */ | |
929 | struct snd_hwdep *hwdep; /* and a hwdep for additional ioctl */ | |
763f356c TI |
930 | struct pci_dev *pci; /* and an pci info */ |
931 | ||
932 | /* Mixer vars */ | |
ef5fa1a4 TI |
933 | /* fast alsa mixer */ |
934 | struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS]; | |
935 | /* but input to much, so not used */ | |
936 | struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS]; | |
0dca1793 | 937 | /* full mixer accessable over mixer ioctl or hwdep-device */ |
ef5fa1a4 | 938 | struct hdspm_mixer *mixer; |
763f356c | 939 | |
0dca1793 | 940 | struct hdspm_tco *tco; /* NULL if no TCO detected */ |
763f356c | 941 | |
0dca1793 AK |
942 | char **texts_autosync; |
943 | int texts_autosync_items; | |
763f356c | 944 | |
0dca1793 | 945 | cycles_t last_interrupt; |
730a5865 JK |
946 | |
947 | struct hdspm_peak_rms peak_rms; | |
763f356c TI |
948 | }; |
949 | ||
763f356c | 950 | |
cebe41d4 | 951 | static DEFINE_PCI_DEVICE_TABLE(snd_hdspm_ids) = { |
763f356c TI |
952 | { |
953 | .vendor = PCI_VENDOR_ID_XILINX, | |
954 | .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI, | |
955 | .subvendor = PCI_ANY_ID, | |
956 | .subdevice = PCI_ANY_ID, | |
957 | .class = 0, | |
958 | .class_mask = 0, | |
959 | .driver_data = 0}, | |
960 | {0,} | |
961 | }; | |
962 | ||
963 | MODULE_DEVICE_TABLE(pci, snd_hdspm_ids); | |
964 | ||
965 | /* prototypes */ | |
98274f07 TI |
966 | static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card, |
967 | struct hdspm * hdspm); | |
968 | static int __devinit snd_hdspm_create_pcm(struct snd_card *card, | |
969 | struct hdspm * hdspm); | |
970 | ||
0dca1793 AK |
971 | static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm); |
972 | static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm); | |
973 | static int hdspm_autosync_ref(struct hdspm *hdspm); | |
974 | static int snd_hdspm_set_defaults(struct hdspm *hdspm); | |
975 | static void hdspm_set_sgbuf(struct hdspm *hdspm, | |
77a23f26 | 976 | struct snd_pcm_substream *substream, |
763f356c TI |
977 | unsigned int reg, int channels); |
978 | ||
3cee5a60 RB |
979 | static inline int HDSPM_bit2freq(int n) |
980 | { | |
62cef821 DV |
981 | static const int bit2freq_tab[] = { |
982 | 0, 32000, 44100, 48000, 64000, 88200, | |
3cee5a60 RB |
983 | 96000, 128000, 176400, 192000 }; |
984 | if (n < 1 || n > 9) | |
985 | return 0; | |
986 | return bit2freq_tab[n]; | |
987 | } | |
988 | ||
0dca1793 | 989 | /* Write/read to/from HDSPM with Adresses in Bytes |
763f356c TI |
990 | not words but only 32Bit writes are allowed */ |
991 | ||
98274f07 | 992 | static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg, |
763f356c TI |
993 | unsigned int val) |
994 | { | |
995 | writel(val, hdspm->iobase + reg); | |
996 | } | |
997 | ||
98274f07 | 998 | static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg) |
763f356c TI |
999 | { |
1000 | return readl(hdspm->iobase + reg); | |
1001 | } | |
1002 | ||
0dca1793 AK |
1003 | /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader |
1004 | mixer is write only on hardware so we have to cache him for read | |
763f356c TI |
1005 | each fader is a u32, but uses only the first 16 bit */ |
1006 | ||
98274f07 | 1007 | static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan, |
763f356c TI |
1008 | unsigned int in) |
1009 | { | |
5bab2482 | 1010 | if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS) |
763f356c TI |
1011 | return 0; |
1012 | ||
1013 | return hdspm->mixer->ch[chan].in[in]; | |
1014 | } | |
1015 | ||
98274f07 | 1016 | static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan, |
763f356c TI |
1017 | unsigned int pb) |
1018 | { | |
5bab2482 | 1019 | if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS) |
763f356c TI |
1020 | return 0; |
1021 | return hdspm->mixer->ch[chan].pb[pb]; | |
1022 | } | |
1023 | ||
62cef821 | 1024 | static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan, |
763f356c TI |
1025 | unsigned int in, unsigned short data) |
1026 | { | |
1027 | if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS) | |
1028 | return -1; | |
1029 | ||
1030 | hdspm_write(hdspm, | |
1031 | HDSPM_MADI_mixerBase + | |
1032 | ((in + 128 * chan) * sizeof(u32)), | |
1033 | (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF)); | |
1034 | return 0; | |
1035 | } | |
1036 | ||
62cef821 | 1037 | static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan, |
763f356c TI |
1038 | unsigned int pb, unsigned short data) |
1039 | { | |
1040 | if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS) | |
1041 | return -1; | |
1042 | ||
1043 | hdspm_write(hdspm, | |
1044 | HDSPM_MADI_mixerBase + | |
1045 | ((64 + pb + 128 * chan) * sizeof(u32)), | |
1046 | (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF)); | |
1047 | return 0; | |
1048 | } | |
1049 | ||
1050 | ||
1051 | /* enable DMA for specific channels, now available for DSP-MADI */ | |
98274f07 | 1052 | static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v) |
763f356c TI |
1053 | { |
1054 | hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v); | |
1055 | } | |
1056 | ||
98274f07 | 1057 | static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v) |
763f356c TI |
1058 | { |
1059 | hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v); | |
1060 | } | |
1061 | ||
1062 | /* check if same process is writing and reading */ | |
62cef821 | 1063 | static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm) |
763f356c TI |
1064 | { |
1065 | unsigned long flags; | |
1066 | int ret = 1; | |
1067 | ||
1068 | spin_lock_irqsave(&hdspm->lock, flags); | |
1069 | if ((hdspm->playback_pid != hdspm->capture_pid) && | |
1070 | (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) { | |
1071 | ret = 0; | |
1072 | } | |
1073 | spin_unlock_irqrestore(&hdspm->lock, flags); | |
1074 | return ret; | |
1075 | } | |
1076 | ||
1077 | /* check for external sample rate */ | |
62cef821 | 1078 | static int hdspm_external_sample_rate(struct hdspm *hdspm) |
763f356c | 1079 | { |
0dca1793 AK |
1080 | unsigned int status, status2, timecode; |
1081 | int syncref, rate = 0, rate_bits; | |
3cee5a60 | 1082 | |
0dca1793 AK |
1083 | switch (hdspm->io_type) { |
1084 | case AES32: | |
1085 | status2 = hdspm_read(hdspm, HDSPM_statusRegister2); | |
1086 | status = hdspm_read(hdspm, HDSPM_statusRegister); | |
7c4a95b5 | 1087 | timecode = hdspm_read(hdspm, HDSPM_timecodeRegister); |
0dca1793 AK |
1088 | |
1089 | syncref = hdspm_autosync_ref(hdspm); | |
3cee5a60 RB |
1090 | |
1091 | if (syncref == HDSPM_AES32_AUTOSYNC_FROM_WORD && | |
1092 | status & HDSPM_AES32_wcLock) | |
0dca1793 AK |
1093 | return HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF); |
1094 | ||
3cee5a60 | 1095 | if (syncref >= HDSPM_AES32_AUTOSYNC_FROM_AES1 && |
0dca1793 AK |
1096 | syncref <= HDSPM_AES32_AUTOSYNC_FROM_AES8 && |
1097 | status2 & (HDSPM_LockAES >> | |
1098 | (syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1))) | |
1099 | return HDSPM_bit2freq((timecode >> (4*(syncref-HDSPM_AES32_AUTOSYNC_FROM_AES1))) & 0xF); | |
3cee5a60 | 1100 | return 0; |
0dca1793 AK |
1101 | break; |
1102 | ||
1103 | case MADIface: | |
1104 | status = hdspm_read(hdspm, HDSPM_statusRegister); | |
1105 | ||
1106 | if (!(status & HDSPM_madiLock)) { | |
1107 | rate = 0; /* no lock */ | |
1108 | } else { | |
1109 | switch (status & (HDSPM_status1_freqMask)) { | |
1110 | case HDSPM_status1_F_0*1: | |
1111 | rate = 32000; break; | |
1112 | case HDSPM_status1_F_0*2: | |
1113 | rate = 44100; break; | |
1114 | case HDSPM_status1_F_0*3: | |
1115 | rate = 48000; break; | |
1116 | case HDSPM_status1_F_0*4: | |
1117 | rate = 64000; break; | |
1118 | case HDSPM_status1_F_0*5: | |
1119 | rate = 88200; break; | |
1120 | case HDSPM_status1_F_0*6: | |
1121 | rate = 96000; break; | |
1122 | case HDSPM_status1_F_0*7: | |
1123 | rate = 128000; break; | |
1124 | case HDSPM_status1_F_0*8: | |
1125 | rate = 176400; break; | |
1126 | case HDSPM_status1_F_0*9: | |
1127 | rate = 192000; break; | |
1128 | default: | |
1129 | rate = 0; break; | |
1130 | } | |
1131 | } | |
1132 | ||
1133 | break; | |
1134 | ||
1135 | case MADI: | |
1136 | case AIO: | |
1137 | case RayDAT: | |
1138 | status2 = hdspm_read(hdspm, HDSPM_statusRegister2); | |
1139 | status = hdspm_read(hdspm, HDSPM_statusRegister); | |
1140 | rate = 0; | |
763f356c | 1141 | |
3cee5a60 RB |
1142 | /* if wordclock has synced freq and wordclock is valid */ |
1143 | if ((status2 & HDSPM_wcLock) != 0 && | |
1144 | (status & HDSPM_SelSyncRef0) == 0) { | |
763f356c | 1145 | |
3cee5a60 | 1146 | rate_bits = status2 & HDSPM_wcFreqMask; |
763f356c | 1147 | |
0dca1793 | 1148 | |
3cee5a60 RB |
1149 | switch (rate_bits) { |
1150 | case HDSPM_wcFreq32: | |
1151 | rate = 32000; | |
1152 | break; | |
1153 | case HDSPM_wcFreq44_1: | |
1154 | rate = 44100; | |
1155 | break; | |
1156 | case HDSPM_wcFreq48: | |
1157 | rate = 48000; | |
1158 | break; | |
1159 | case HDSPM_wcFreq64: | |
1160 | rate = 64000; | |
1161 | break; | |
1162 | case HDSPM_wcFreq88_2: | |
1163 | rate = 88200; | |
1164 | break; | |
1165 | case HDSPM_wcFreq96: | |
1166 | rate = 96000; | |
1167 | break; | |
3cee5a60 RB |
1168 | default: |
1169 | rate = 0; | |
1170 | break; | |
1171 | } | |
763f356c | 1172 | } |
763f356c | 1173 | |
ef5fa1a4 TI |
1174 | /* if rate detected and Syncref is Word than have it, |
1175 | * word has priority to MADI | |
1176 | */ | |
3cee5a60 | 1177 | if (rate != 0 && |
0dca1793 | 1178 | (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD) |
3cee5a60 | 1179 | return rate; |
763f356c | 1180 | |
0dca1793 | 1181 | /* maybe a madi input (which is taken if sel sync is madi) */ |
3cee5a60 RB |
1182 | if (status & HDSPM_madiLock) { |
1183 | rate_bits = status & HDSPM_madiFreqMask; | |
763f356c | 1184 | |
3cee5a60 RB |
1185 | switch (rate_bits) { |
1186 | case HDSPM_madiFreq32: | |
1187 | rate = 32000; | |
1188 | break; | |
1189 | case HDSPM_madiFreq44_1: | |
1190 | rate = 44100; | |
1191 | break; | |
1192 | case HDSPM_madiFreq48: | |
1193 | rate = 48000; | |
1194 | break; | |
1195 | case HDSPM_madiFreq64: | |
1196 | rate = 64000; | |
1197 | break; | |
1198 | case HDSPM_madiFreq88_2: | |
1199 | rate = 88200; | |
1200 | break; | |
1201 | case HDSPM_madiFreq96: | |
1202 | rate = 96000; | |
1203 | break; | |
1204 | case HDSPM_madiFreq128: | |
1205 | rate = 128000; | |
1206 | break; | |
1207 | case HDSPM_madiFreq176_4: | |
1208 | rate = 176400; | |
1209 | break; | |
1210 | case HDSPM_madiFreq192: | |
1211 | rate = 192000; | |
1212 | break; | |
1213 | default: | |
1214 | rate = 0; | |
1215 | break; | |
1216 | } | |
763f356c | 1217 | } |
0dca1793 | 1218 | break; |
763f356c | 1219 | } |
0dca1793 AK |
1220 | |
1221 | return rate; | |
763f356c TI |
1222 | } |
1223 | ||
1224 | /* Latency function */ | |
0dca1793 | 1225 | static inline void hdspm_compute_period_size(struct hdspm *hdspm) |
763f356c | 1226 | { |
0dca1793 | 1227 | hdspm->period_bytes = 1 << ((hdspm_decode_latency(hdspm->control_register) + 8)); |
763f356c TI |
1228 | } |
1229 | ||
0dca1793 AK |
1230 | |
1231 | static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm) | |
763f356c TI |
1232 | { |
1233 | int position; | |
1234 | ||
1235 | position = hdspm_read(hdspm, HDSPM_statusRegister); | |
483cee77 AK |
1236 | |
1237 | switch (hdspm->io_type) { | |
1238 | case RayDAT: | |
1239 | case AIO: | |
1240 | position &= HDSPM_BufferPositionMask; | |
1241 | position /= 4; /* Bytes per sample */ | |
1242 | break; | |
1243 | default: | |
1244 | position = (position & HDSPM_BufferID) ? | |
1245 | (hdspm->period_bytes / 4) : 0; | |
1246 | } | |
763f356c TI |
1247 | |
1248 | return position; | |
1249 | } | |
1250 | ||
1251 | ||
98274f07 | 1252 | static inline void hdspm_start_audio(struct hdspm * s) |
763f356c TI |
1253 | { |
1254 | s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start); | |
1255 | hdspm_write(s, HDSPM_controlRegister, s->control_register); | |
1256 | } | |
1257 | ||
98274f07 | 1258 | static inline void hdspm_stop_audio(struct hdspm * s) |
763f356c TI |
1259 | { |
1260 | s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable); | |
1261 | hdspm_write(s, HDSPM_controlRegister, s->control_register); | |
1262 | } | |
1263 | ||
1264 | /* should I silence all or only opened ones ? doit all for first even is 4MB*/ | |
62cef821 | 1265 | static void hdspm_silence_playback(struct hdspm *hdspm) |
763f356c TI |
1266 | { |
1267 | int i; | |
1268 | int n = hdspm->period_bytes; | |
1269 | void *buf = hdspm->playback_buffer; | |
1270 | ||
3cee5a60 RB |
1271 | if (buf == NULL) |
1272 | return; | |
763f356c TI |
1273 | |
1274 | for (i = 0; i < HDSPM_MAX_CHANNELS; i++) { | |
1275 | memset(buf, 0, n); | |
1276 | buf += HDSPM_CHANNEL_BUFFER_BYTES; | |
1277 | } | |
1278 | } | |
1279 | ||
0dca1793 | 1280 | static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames) |
763f356c TI |
1281 | { |
1282 | int n; | |
1283 | ||
1284 | spin_lock_irq(&s->lock); | |
1285 | ||
1286 | frames >>= 7; | |
1287 | n = 0; | |
1288 | while (frames) { | |
1289 | n++; | |
1290 | frames >>= 1; | |
1291 | } | |
1292 | s->control_register &= ~HDSPM_LatencyMask; | |
1293 | s->control_register |= hdspm_encode_latency(n); | |
1294 | ||
1295 | hdspm_write(s, HDSPM_controlRegister, s->control_register); | |
1296 | ||
1297 | hdspm_compute_period_size(s); | |
1298 | ||
1299 | spin_unlock_irq(&s->lock); | |
1300 | ||
1301 | return 0; | |
1302 | } | |
1303 | ||
0dca1793 AK |
1304 | static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period) |
1305 | { | |
1306 | u64 freq_const; | |
1307 | ||
1308 | if (period == 0) | |
1309 | return 0; | |
1310 | ||
1311 | switch (hdspm->io_type) { | |
1312 | case MADI: | |
1313 | case AES32: | |
1314 | freq_const = 110069313433624ULL; | |
1315 | break; | |
1316 | case RayDAT: | |
1317 | case AIO: | |
1318 | freq_const = 104857600000000ULL; | |
1319 | break; | |
1320 | case MADIface: | |
1321 | freq_const = 131072000000000ULL; | |
1322 | } | |
1323 | ||
1324 | return div_u64(freq_const, period); | |
1325 | } | |
1326 | ||
1327 | ||
ffb2c3c0 RB |
1328 | static void hdspm_set_dds_value(struct hdspm *hdspm, int rate) |
1329 | { | |
1330 | u64 n; | |
0dca1793 | 1331 | |
ffb2c3c0 RB |
1332 | if (rate >= 112000) |
1333 | rate /= 4; | |
1334 | else if (rate >= 56000) | |
1335 | rate /= 2; | |
1336 | ||
0dca1793 AK |
1337 | switch (hdspm->io_type) { |
1338 | case MADIface: | |
1339 | n = 131072000000000ULL; /* 125 MHz */ | |
1340 | break; | |
1341 | case MADI: | |
1342 | case AES32: | |
1343 | n = 110069313433624ULL; /* 105 MHz */ | |
1344 | break; | |
1345 | case RayDAT: | |
1346 | case AIO: | |
1347 | n = 104857600000000ULL; /* 100 MHz */ | |
1348 | break; | |
1349 | } | |
1350 | ||
3f7440a6 | 1351 | n = div_u64(n, rate); |
ffb2c3c0 | 1352 | /* n should be less than 2^32 for being written to FREQ register */ |
da3cec35 | 1353 | snd_BUG_ON(n >> 32); |
ffb2c3c0 RB |
1354 | hdspm_write(hdspm, HDSPM_freqReg, (u32)n); |
1355 | } | |
763f356c TI |
1356 | |
1357 | /* dummy set rate lets see what happens */ | |
98274f07 | 1358 | static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally) |
763f356c | 1359 | { |
763f356c TI |
1360 | int current_rate; |
1361 | int rate_bits; | |
1362 | int not_set = 0; | |
6534599d | 1363 | int current_speed, target_speed; |
763f356c TI |
1364 | |
1365 | /* ASSUMPTION: hdspm->lock is either set, or there is no need for | |
1366 | it (e.g. during module initialization). | |
1367 | */ | |
1368 | ||
1369 | if (!(hdspm->control_register & HDSPM_ClockModeMaster)) { | |
1370 | ||
0dca1793 | 1371 | /* SLAVE --- */ |
763f356c TI |
1372 | if (called_internally) { |
1373 | ||
0dca1793 AK |
1374 | /* request from ctl or card initialization |
1375 | just make a warning an remember setting | |
1376 | for future master mode switching */ | |
1377 | ||
ef5fa1a4 TI |
1378 | snd_printk(KERN_WARNING "HDSPM: " |
1379 | "Warning: device is not running " | |
1380 | "as a clock master.\n"); | |
763f356c TI |
1381 | not_set = 1; |
1382 | } else { | |
1383 | ||
1384 | /* hw_param request while in AutoSync mode */ | |
1385 | int external_freq = | |
1386 | hdspm_external_sample_rate(hdspm); | |
1387 | ||
ef5fa1a4 TI |
1388 | if (hdspm_autosync_ref(hdspm) == |
1389 | HDSPM_AUTOSYNC_FROM_NONE) { | |
763f356c | 1390 | |
ef5fa1a4 TI |
1391 | snd_printk(KERN_WARNING "HDSPM: " |
1392 | "Detected no Externel Sync \n"); | |
763f356c TI |
1393 | not_set = 1; |
1394 | ||
1395 | } else if (rate != external_freq) { | |
1396 | ||
ef5fa1a4 TI |
1397 | snd_printk(KERN_WARNING "HDSPM: " |
1398 | "Warning: No AutoSync source for " | |
1399 | "requested rate\n"); | |
763f356c TI |
1400 | not_set = 1; |
1401 | } | |
1402 | } | |
1403 | } | |
1404 | ||
1405 | current_rate = hdspm->system_sample_rate; | |
1406 | ||
1407 | /* Changing between Singe, Double and Quad speed is not | |
1408 | allowed if any substreams are open. This is because such a change | |
1409 | causes a shift in the location of the DMA buffers and a reduction | |
1410 | in the number of available buffers. | |
1411 | ||
1412 | Note that a similar but essentially insoluble problem exists for | |
1413 | externally-driven rate changes. All we can do is to flag rate | |
0dca1793 | 1414 | changes in the read/write routines. |
763f356c TI |
1415 | */ |
1416 | ||
6534599d RB |
1417 | if (current_rate <= 48000) |
1418 | current_speed = HDSPM_SPEED_SINGLE; | |
1419 | else if (current_rate <= 96000) | |
1420 | current_speed = HDSPM_SPEED_DOUBLE; | |
1421 | else | |
1422 | current_speed = HDSPM_SPEED_QUAD; | |
1423 | ||
1424 | if (rate <= 48000) | |
1425 | target_speed = HDSPM_SPEED_SINGLE; | |
1426 | else if (rate <= 96000) | |
1427 | target_speed = HDSPM_SPEED_DOUBLE; | |
1428 | else | |
1429 | target_speed = HDSPM_SPEED_QUAD; | |
3cee5a60 | 1430 | |
763f356c TI |
1431 | switch (rate) { |
1432 | case 32000: | |
763f356c TI |
1433 | rate_bits = HDSPM_Frequency32KHz; |
1434 | break; | |
1435 | case 44100: | |
763f356c TI |
1436 | rate_bits = HDSPM_Frequency44_1KHz; |
1437 | break; | |
1438 | case 48000: | |
763f356c TI |
1439 | rate_bits = HDSPM_Frequency48KHz; |
1440 | break; | |
1441 | case 64000: | |
763f356c TI |
1442 | rate_bits = HDSPM_Frequency64KHz; |
1443 | break; | |
1444 | case 88200: | |
763f356c TI |
1445 | rate_bits = HDSPM_Frequency88_2KHz; |
1446 | break; | |
1447 | case 96000: | |
763f356c TI |
1448 | rate_bits = HDSPM_Frequency96KHz; |
1449 | break; | |
3cee5a60 | 1450 | case 128000: |
3cee5a60 RB |
1451 | rate_bits = HDSPM_Frequency128KHz; |
1452 | break; | |
1453 | case 176400: | |
3cee5a60 RB |
1454 | rate_bits = HDSPM_Frequency176_4KHz; |
1455 | break; | |
1456 | case 192000: | |
3cee5a60 RB |
1457 | rate_bits = HDSPM_Frequency192KHz; |
1458 | break; | |
763f356c TI |
1459 | default: |
1460 | return -EINVAL; | |
1461 | } | |
1462 | ||
6534599d | 1463 | if (current_speed != target_speed |
763f356c TI |
1464 | && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) { |
1465 | snd_printk | |
ef5fa1a4 | 1466 | (KERN_ERR "HDSPM: " |
6534599d | 1467 | "cannot change from %s speed to %s speed mode " |
ef5fa1a4 | 1468 | "(capture PID = %d, playback PID = %d)\n", |
6534599d RB |
1469 | hdspm_speed_names[current_speed], |
1470 | hdspm_speed_names[target_speed], | |
763f356c TI |
1471 | hdspm->capture_pid, hdspm->playback_pid); |
1472 | return -EBUSY; | |
1473 | } | |
1474 | ||
1475 | hdspm->control_register &= ~HDSPM_FrequencyMask; | |
1476 | hdspm->control_register |= rate_bits; | |
1477 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); | |
1478 | ||
ffb2c3c0 RB |
1479 | /* For AES32, need to set DDS value in FREQ register |
1480 | For MADI, also apparently */ | |
1481 | hdspm_set_dds_value(hdspm, rate); | |
0dca1793 AK |
1482 | |
1483 | if (AES32 == hdspm->io_type && rate != current_rate) | |
ffb2c3c0 | 1484 | hdspm_write(hdspm, HDSPM_eeprom_wr, 0); |
763f356c TI |
1485 | |
1486 | hdspm->system_sample_rate = rate; | |
1487 | ||
0dca1793 AK |
1488 | if (rate <= 48000) { |
1489 | hdspm->channel_map_in = hdspm->channel_map_in_ss; | |
1490 | hdspm->channel_map_out = hdspm->channel_map_out_ss; | |
1491 | hdspm->max_channels_in = hdspm->ss_in_channels; | |
1492 | hdspm->max_channels_out = hdspm->ss_out_channels; | |
1493 | hdspm->port_names_in = hdspm->port_names_in_ss; | |
1494 | hdspm->port_names_out = hdspm->port_names_out_ss; | |
1495 | } else if (rate <= 96000) { | |
1496 | hdspm->channel_map_in = hdspm->channel_map_in_ds; | |
1497 | hdspm->channel_map_out = hdspm->channel_map_out_ds; | |
1498 | hdspm->max_channels_in = hdspm->ds_in_channels; | |
1499 | hdspm->max_channels_out = hdspm->ds_out_channels; | |
1500 | hdspm->port_names_in = hdspm->port_names_in_ds; | |
1501 | hdspm->port_names_out = hdspm->port_names_out_ds; | |
1502 | } else { | |
1503 | hdspm->channel_map_in = hdspm->channel_map_in_qs; | |
1504 | hdspm->channel_map_out = hdspm->channel_map_out_qs; | |
1505 | hdspm->max_channels_in = hdspm->qs_in_channels; | |
1506 | hdspm->max_channels_out = hdspm->qs_out_channels; | |
1507 | hdspm->port_names_in = hdspm->port_names_in_qs; | |
1508 | hdspm->port_names_out = hdspm->port_names_out_qs; | |
1509 | } | |
1510 | ||
763f356c TI |
1511 | if (not_set != 0) |
1512 | return -1; | |
1513 | ||
1514 | return 0; | |
1515 | } | |
1516 | ||
1517 | /* mainly for init to 0 on load */ | |
98274f07 | 1518 | static void all_in_all_mixer(struct hdspm * hdspm, int sgain) |
763f356c TI |
1519 | { |
1520 | int i, j; | |
ef5fa1a4 TI |
1521 | unsigned int gain; |
1522 | ||
1523 | if (sgain > UNITY_GAIN) | |
1524 | gain = UNITY_GAIN; | |
1525 | else if (sgain < 0) | |
1526 | gain = 0; | |
1527 | else | |
1528 | gain = sgain; | |
763f356c TI |
1529 | |
1530 | for (i = 0; i < HDSPM_MIXER_CHANNELS; i++) | |
1531 | for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) { | |
1532 | hdspm_write_in_gain(hdspm, i, j, gain); | |
1533 | hdspm_write_pb_gain(hdspm, i, j, gain); | |
1534 | } | |
1535 | } | |
1536 | ||
1537 | /*---------------------------------------------------------------------------- | |
1538 | MIDI | |
1539 | ----------------------------------------------------------------------------*/ | |
1540 | ||
ef5fa1a4 TI |
1541 | static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm, |
1542 | int id) | |
763f356c TI |
1543 | { |
1544 | /* the hardware already does the relevant bit-mask with 0xff */ | |
0dca1793 | 1545 | return hdspm_read(hdspm, hdspm->midi[id].dataIn); |
763f356c TI |
1546 | } |
1547 | ||
ef5fa1a4 TI |
1548 | static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id, |
1549 | int val) | |
763f356c TI |
1550 | { |
1551 | /* the hardware already does the relevant bit-mask with 0xff */ | |
0dca1793 | 1552 | return hdspm_write(hdspm, hdspm->midi[id].dataOut, val); |
763f356c TI |
1553 | } |
1554 | ||
98274f07 | 1555 | static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id) |
763f356c | 1556 | { |
0dca1793 | 1557 | return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF; |
763f356c TI |
1558 | } |
1559 | ||
98274f07 | 1560 | static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id) |
763f356c TI |
1561 | { |
1562 | int fifo_bytes_used; | |
1563 | ||
0dca1793 | 1564 | fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF; |
763f356c TI |
1565 | |
1566 | if (fifo_bytes_used < 128) | |
1567 | return 128 - fifo_bytes_used; | |
1568 | else | |
1569 | return 0; | |
1570 | } | |
1571 | ||
62cef821 | 1572 | static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id) |
763f356c TI |
1573 | { |
1574 | while (snd_hdspm_midi_input_available (hdspm, id)) | |
1575 | snd_hdspm_midi_read_byte (hdspm, id); | |
1576 | } | |
1577 | ||
98274f07 | 1578 | static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi) |
763f356c TI |
1579 | { |
1580 | unsigned long flags; | |
1581 | int n_pending; | |
1582 | int to_write; | |
1583 | int i; | |
1584 | unsigned char buf[128]; | |
1585 | ||
1586 | /* Output is not interrupt driven */ | |
0dca1793 | 1587 | |
763f356c | 1588 | spin_lock_irqsave (&hmidi->lock, flags); |
ef5fa1a4 TI |
1589 | if (hmidi->output && |
1590 | !snd_rawmidi_transmit_empty (hmidi->output)) { | |
1591 | n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm, | |
1592 | hmidi->id); | |
1593 | if (n_pending > 0) { | |
1594 | if (n_pending > (int)sizeof (buf)) | |
1595 | n_pending = sizeof (buf); | |
0dca1793 | 1596 | |
ef5fa1a4 TI |
1597 | to_write = snd_rawmidi_transmit (hmidi->output, buf, |
1598 | n_pending); | |
1599 | if (to_write > 0) { | |
0dca1793 | 1600 | for (i = 0; i < to_write; ++i) |
ef5fa1a4 TI |
1601 | snd_hdspm_midi_write_byte (hmidi->hdspm, |
1602 | hmidi->id, | |
1603 | buf[i]); | |
763f356c TI |
1604 | } |
1605 | } | |
1606 | } | |
1607 | spin_unlock_irqrestore (&hmidi->lock, flags); | |
1608 | return 0; | |
1609 | } | |
1610 | ||
98274f07 | 1611 | static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi) |
763f356c | 1612 | { |
ef5fa1a4 TI |
1613 | unsigned char buf[128]; /* this buffer is designed to match the MIDI |
1614 | * input FIFO size | |
1615 | */ | |
763f356c TI |
1616 | unsigned long flags; |
1617 | int n_pending; | |
1618 | int i; | |
1619 | ||
1620 | spin_lock_irqsave (&hmidi->lock, flags); | |
ef5fa1a4 TI |
1621 | n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id); |
1622 | if (n_pending > 0) { | |
763f356c | 1623 | if (hmidi->input) { |
ef5fa1a4 | 1624 | if (n_pending > (int)sizeof (buf)) |
763f356c | 1625 | n_pending = sizeof (buf); |
ef5fa1a4 TI |
1626 | for (i = 0; i < n_pending; ++i) |
1627 | buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm, | |
1628 | hmidi->id); | |
1629 | if (n_pending) | |
1630 | snd_rawmidi_receive (hmidi->input, buf, | |
1631 | n_pending); | |
763f356c TI |
1632 | } else { |
1633 | /* flush the MIDI input FIFO */ | |
ef5fa1a4 TI |
1634 | while (n_pending--) |
1635 | snd_hdspm_midi_read_byte (hmidi->hdspm, | |
1636 | hmidi->id); | |
763f356c TI |
1637 | } |
1638 | } | |
1639 | hmidi->pending = 0; | |
0dca1793 AK |
1640 | |
1641 | hmidi->hdspm->control_register |= hmidi->ie; | |
ef5fa1a4 TI |
1642 | hdspm_write(hmidi->hdspm, HDSPM_controlRegister, |
1643 | hmidi->hdspm->control_register); | |
0dca1793 | 1644 | |
763f356c TI |
1645 | spin_unlock_irqrestore (&hmidi->lock, flags); |
1646 | return snd_hdspm_midi_output_write (hmidi); | |
1647 | } | |
1648 | ||
ef5fa1a4 TI |
1649 | static void |
1650 | snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) | |
763f356c | 1651 | { |
98274f07 TI |
1652 | struct hdspm *hdspm; |
1653 | struct hdspm_midi *hmidi; | |
763f356c | 1654 | unsigned long flags; |
763f356c | 1655 | |
ef5fa1a4 | 1656 | hmidi = substream->rmidi->private_data; |
763f356c | 1657 | hdspm = hmidi->hdspm; |
0dca1793 | 1658 | |
763f356c TI |
1659 | spin_lock_irqsave (&hdspm->lock, flags); |
1660 | if (up) { | |
0dca1793 | 1661 | if (!(hdspm->control_register & hmidi->ie)) { |
763f356c | 1662 | snd_hdspm_flush_midi_input (hdspm, hmidi->id); |
0dca1793 | 1663 | hdspm->control_register |= hmidi->ie; |
763f356c TI |
1664 | } |
1665 | } else { | |
0dca1793 | 1666 | hdspm->control_register &= ~hmidi->ie; |
763f356c TI |
1667 | } |
1668 | ||
1669 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); | |
1670 | spin_unlock_irqrestore (&hdspm->lock, flags); | |
1671 | } | |
1672 | ||
1673 | static void snd_hdspm_midi_output_timer(unsigned long data) | |
1674 | { | |
98274f07 | 1675 | struct hdspm_midi *hmidi = (struct hdspm_midi *) data; |
763f356c | 1676 | unsigned long flags; |
0dca1793 | 1677 | |
763f356c TI |
1678 | snd_hdspm_midi_output_write(hmidi); |
1679 | spin_lock_irqsave (&hmidi->lock, flags); | |
1680 | ||
1681 | /* this does not bump hmidi->istimer, because the | |
1682 | kernel automatically removed the timer when it | |
1683 | expired, and we are now adding it back, thus | |
0dca1793 | 1684 | leaving istimer wherever it was set before. |
763f356c TI |
1685 | */ |
1686 | ||
1687 | if (hmidi->istimer) { | |
1688 | hmidi->timer.expires = 1 + jiffies; | |
1689 | add_timer(&hmidi->timer); | |
1690 | } | |
1691 | ||
1692 | spin_unlock_irqrestore (&hmidi->lock, flags); | |
1693 | } | |
1694 | ||
ef5fa1a4 TI |
1695 | static void |
1696 | snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) | |
763f356c | 1697 | { |
98274f07 | 1698 | struct hdspm_midi *hmidi; |
763f356c TI |
1699 | unsigned long flags; |
1700 | ||
ef5fa1a4 | 1701 | hmidi = substream->rmidi->private_data; |
763f356c TI |
1702 | spin_lock_irqsave (&hmidi->lock, flags); |
1703 | if (up) { | |
1704 | if (!hmidi->istimer) { | |
1705 | init_timer(&hmidi->timer); | |
1706 | hmidi->timer.function = snd_hdspm_midi_output_timer; | |
1707 | hmidi->timer.data = (unsigned long) hmidi; | |
1708 | hmidi->timer.expires = 1 + jiffies; | |
1709 | add_timer(&hmidi->timer); | |
1710 | hmidi->istimer++; | |
1711 | } | |
1712 | } else { | |
ef5fa1a4 | 1713 | if (hmidi->istimer && --hmidi->istimer <= 0) |
763f356c | 1714 | del_timer (&hmidi->timer); |
763f356c TI |
1715 | } |
1716 | spin_unlock_irqrestore (&hmidi->lock, flags); | |
1717 | if (up) | |
1718 | snd_hdspm_midi_output_write(hmidi); | |
1719 | } | |
1720 | ||
98274f07 | 1721 | static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream) |
763f356c | 1722 | { |
98274f07 | 1723 | struct hdspm_midi *hmidi; |
763f356c | 1724 | |
ef5fa1a4 | 1725 | hmidi = substream->rmidi->private_data; |
763f356c TI |
1726 | spin_lock_irq (&hmidi->lock); |
1727 | snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id); | |
1728 | hmidi->input = substream; | |
1729 | spin_unlock_irq (&hmidi->lock); | |
1730 | ||
1731 | return 0; | |
1732 | } | |
1733 | ||
98274f07 | 1734 | static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream) |
763f356c | 1735 | { |
98274f07 | 1736 | struct hdspm_midi *hmidi; |
763f356c | 1737 | |
ef5fa1a4 | 1738 | hmidi = substream->rmidi->private_data; |
763f356c TI |
1739 | spin_lock_irq (&hmidi->lock); |
1740 | hmidi->output = substream; | |
1741 | spin_unlock_irq (&hmidi->lock); | |
1742 | ||
1743 | return 0; | |
1744 | } | |
1745 | ||
98274f07 | 1746 | static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream) |
763f356c | 1747 | { |
98274f07 | 1748 | struct hdspm_midi *hmidi; |
763f356c TI |
1749 | |
1750 | snd_hdspm_midi_input_trigger (substream, 0); | |
1751 | ||
ef5fa1a4 | 1752 | hmidi = substream->rmidi->private_data; |
763f356c TI |
1753 | spin_lock_irq (&hmidi->lock); |
1754 | hmidi->input = NULL; | |
1755 | spin_unlock_irq (&hmidi->lock); | |
1756 | ||
1757 | return 0; | |
1758 | } | |
1759 | ||
98274f07 | 1760 | static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream) |
763f356c | 1761 | { |
98274f07 | 1762 | struct hdspm_midi *hmidi; |
763f356c TI |
1763 | |
1764 | snd_hdspm_midi_output_trigger (substream, 0); | |
1765 | ||
ef5fa1a4 | 1766 | hmidi = substream->rmidi->private_data; |
763f356c TI |
1767 | spin_lock_irq (&hmidi->lock); |
1768 | hmidi->output = NULL; | |
1769 | spin_unlock_irq (&hmidi->lock); | |
1770 | ||
1771 | return 0; | |
1772 | } | |
1773 | ||
98274f07 | 1774 | static struct snd_rawmidi_ops snd_hdspm_midi_output = |
763f356c TI |
1775 | { |
1776 | .open = snd_hdspm_midi_output_open, | |
1777 | .close = snd_hdspm_midi_output_close, | |
1778 | .trigger = snd_hdspm_midi_output_trigger, | |
1779 | }; | |
1780 | ||
98274f07 | 1781 | static struct snd_rawmidi_ops snd_hdspm_midi_input = |
763f356c TI |
1782 | { |
1783 | .open = snd_hdspm_midi_input_open, | |
1784 | .close = snd_hdspm_midi_input_close, | |
1785 | .trigger = snd_hdspm_midi_input_trigger, | |
1786 | }; | |
1787 | ||
ef5fa1a4 TI |
1788 | static int __devinit snd_hdspm_create_midi (struct snd_card *card, |
1789 | struct hdspm *hdspm, int id) | |
763f356c TI |
1790 | { |
1791 | int err; | |
1792 | char buf[32]; | |
1793 | ||
1794 | hdspm->midi[id].id = id; | |
763f356c | 1795 | hdspm->midi[id].hdspm = hdspm; |
763f356c TI |
1796 | spin_lock_init (&hdspm->midi[id].lock); |
1797 | ||
0dca1793 AK |
1798 | if (0 == id) { |
1799 | if (MADIface == hdspm->io_type) { | |
1800 | /* MIDI-over-MADI on HDSPe MADIface */ | |
1801 | hdspm->midi[0].dataIn = HDSPM_midiDataIn2; | |
1802 | hdspm->midi[0].statusIn = HDSPM_midiStatusIn2; | |
1803 | hdspm->midi[0].dataOut = HDSPM_midiDataOut2; | |
1804 | hdspm->midi[0].statusOut = HDSPM_midiStatusOut2; | |
1805 | hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable; | |
1806 | hdspm->midi[0].irq = HDSPM_midi2IRQPending; | |
1807 | } else { | |
1808 | hdspm->midi[0].dataIn = HDSPM_midiDataIn0; | |
1809 | hdspm->midi[0].statusIn = HDSPM_midiStatusIn0; | |
1810 | hdspm->midi[0].dataOut = HDSPM_midiDataOut0; | |
1811 | hdspm->midi[0].statusOut = HDSPM_midiStatusOut0; | |
1812 | hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable; | |
1813 | hdspm->midi[0].irq = HDSPM_midi0IRQPending; | |
1814 | } | |
1815 | } else if (1 == id) { | |
1816 | hdspm->midi[1].dataIn = HDSPM_midiDataIn1; | |
1817 | hdspm->midi[1].statusIn = HDSPM_midiStatusIn1; | |
1818 | hdspm->midi[1].dataOut = HDSPM_midiDataOut1; | |
1819 | hdspm->midi[1].statusOut = HDSPM_midiStatusOut1; | |
1820 | hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable; | |
1821 | hdspm->midi[1].irq = HDSPM_midi1IRQPending; | |
1822 | } else if ((2 == id) && (MADI == hdspm->io_type)) { | |
1823 | /* MIDI-over-MADI on HDSPe MADI */ | |
1824 | hdspm->midi[2].dataIn = HDSPM_midiDataIn2; | |
1825 | hdspm->midi[2].statusIn = HDSPM_midiStatusIn2; | |
1826 | hdspm->midi[2].dataOut = HDSPM_midiDataOut2; | |
1827 | hdspm->midi[2].statusOut = HDSPM_midiStatusOut2; | |
1828 | hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable; | |
1829 | hdspm->midi[2].irq = HDSPM_midi2IRQPending; | |
1830 | } else if (2 == id) { | |
1831 | /* TCO MTC, read only */ | |
1832 | hdspm->midi[2].dataIn = HDSPM_midiDataIn2; | |
1833 | hdspm->midi[2].statusIn = HDSPM_midiStatusIn2; | |
1834 | hdspm->midi[2].dataOut = -1; | |
1835 | hdspm->midi[2].statusOut = -1; | |
1836 | hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable; | |
1837 | hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES; | |
1838 | } else if (3 == id) { | |
1839 | /* TCO MTC on HDSPe MADI */ | |
1840 | hdspm->midi[3].dataIn = HDSPM_midiDataIn3; | |
1841 | hdspm->midi[3].statusIn = HDSPM_midiStatusIn3; | |
1842 | hdspm->midi[3].dataOut = -1; | |
1843 | hdspm->midi[3].statusOut = -1; | |
1844 | hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable; | |
1845 | hdspm->midi[3].irq = HDSPM_midi3IRQPending; | |
1846 | } | |
1847 | ||
1848 | if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) || | |
1849 | (MADIface == hdspm->io_type)))) { | |
1850 | if ((id == 0) && (MADIface == hdspm->io_type)) { | |
1851 | sprintf(buf, "%s MIDIoverMADI", card->shortname); | |
1852 | } else if ((id == 2) && (MADI == hdspm->io_type)) { | |
1853 | sprintf(buf, "%s MIDIoverMADI", card->shortname); | |
1854 | } else { | |
1855 | sprintf(buf, "%s MIDI %d", card->shortname, id+1); | |
1856 | } | |
1857 | err = snd_rawmidi_new(card, buf, id, 1, 1, | |
1858 | &hdspm->midi[id].rmidi); | |
1859 | if (err < 0) | |
1860 | return err; | |
763f356c | 1861 | |
0dca1793 AK |
1862 | sprintf(hdspm->midi[id].rmidi->name, "%s MIDI %d", |
1863 | card->id, id+1); | |
1864 | hdspm->midi[id].rmidi->private_data = &hdspm->midi[id]; | |
1865 | ||
1866 | snd_rawmidi_set_ops(hdspm->midi[id].rmidi, | |
1867 | SNDRV_RAWMIDI_STREAM_OUTPUT, | |
1868 | &snd_hdspm_midi_output); | |
1869 | snd_rawmidi_set_ops(hdspm->midi[id].rmidi, | |
1870 | SNDRV_RAWMIDI_STREAM_INPUT, | |
1871 | &snd_hdspm_midi_input); | |
1872 | ||
1873 | hdspm->midi[id].rmidi->info_flags |= | |
1874 | SNDRV_RAWMIDI_INFO_OUTPUT | | |
1875 | SNDRV_RAWMIDI_INFO_INPUT | | |
1876 | SNDRV_RAWMIDI_INFO_DUPLEX; | |
1877 | } else { | |
1878 | /* TCO MTC, read only */ | |
1879 | sprintf(buf, "%s MTC %d", card->shortname, id+1); | |
1880 | err = snd_rawmidi_new(card, buf, id, 1, 1, | |
1881 | &hdspm->midi[id].rmidi); | |
1882 | if (err < 0) | |
1883 | return err; | |
1884 | ||
1885 | sprintf(hdspm->midi[id].rmidi->name, | |
1886 | "%s MTC %d", card->id, id+1); | |
1887 | hdspm->midi[id].rmidi->private_data = &hdspm->midi[id]; | |
763f356c | 1888 | |
0dca1793 AK |
1889 | snd_rawmidi_set_ops(hdspm->midi[id].rmidi, |
1890 | SNDRV_RAWMIDI_STREAM_INPUT, | |
1891 | &snd_hdspm_midi_input); | |
763f356c | 1892 | |
0dca1793 AK |
1893 | hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT; |
1894 | } | |
763f356c TI |
1895 | |
1896 | return 0; | |
1897 | } | |
1898 | ||
1899 | ||
1900 | static void hdspm_midi_tasklet(unsigned long arg) | |
1901 | { | |
98274f07 | 1902 | struct hdspm *hdspm = (struct hdspm *)arg; |
0dca1793 AK |
1903 | int i = 0; |
1904 | ||
1905 | while (i < hdspm->midiPorts) { | |
1906 | if (hdspm->midi[i].pending) | |
1907 | snd_hdspm_midi_input_read(&hdspm->midi[i]); | |
1908 | ||
1909 | i++; | |
1910 | } | |
1911 | } | |
763f356c TI |
1912 | |
1913 | ||
1914 | /*----------------------------------------------------------------------------- | |
1915 | Status Interface | |
1916 | ----------------------------------------------------------------------------*/ | |
1917 | ||
1918 | /* get the system sample rate which is set */ | |
1919 | ||
0dca1793 AK |
1920 | |
1921 | /** | |
1922 | * Calculate the real sample rate from the | |
1923 | * current DDS value. | |
1924 | **/ | |
1925 | static int hdspm_get_system_sample_rate(struct hdspm *hdspm) | |
1926 | { | |
1927 | unsigned int period, rate; | |
1928 | ||
1929 | period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); | |
1930 | rate = hdspm_calc_dds_value(hdspm, period); | |
1931 | ||
1932 | return rate; | |
1933 | } | |
1934 | ||
1935 | ||
763f356c | 1936 | #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \ |
67ed4161 | 1937 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
763f356c TI |
1938 | .name = xname, \ |
1939 | .index = xindex, \ | |
1940 | .access = SNDRV_CTL_ELEM_ACCESS_READ, \ | |
1941 | .info = snd_hdspm_info_system_sample_rate, \ | |
1942 | .get = snd_hdspm_get_system_sample_rate \ | |
1943 | } | |
1944 | ||
98274f07 TI |
1945 | static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol, |
1946 | struct snd_ctl_elem_info *uinfo) | |
763f356c TI |
1947 | { |
1948 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; | |
1949 | uinfo->count = 1; | |
0dca1793 AK |
1950 | uinfo->value.integer.min = 27000; |
1951 | uinfo->value.integer.max = 207000; | |
1952 | uinfo->value.integer.step = 1; | |
763f356c TI |
1953 | return 0; |
1954 | } | |
1955 | ||
0dca1793 | 1956 | |
98274f07 TI |
1957 | static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol, |
1958 | struct snd_ctl_elem_value * | |
763f356c TI |
1959 | ucontrol) |
1960 | { | |
98274f07 | 1961 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c | 1962 | |
0dca1793 AK |
1963 | ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm); |
1964 | return 0; | |
1965 | } | |
1966 | ||
1967 | ||
1968 | /** | |
1969 | * Returns the WordClock sample rate class for the given card. | |
1970 | **/ | |
1971 | static int hdspm_get_wc_sample_rate(struct hdspm *hdspm) | |
1972 | { | |
1973 | int status; | |
1974 | ||
1975 | switch (hdspm->io_type) { | |
1976 | case RayDAT: | |
1977 | case AIO: | |
1978 | status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); | |
1979 | return (status >> 16) & 0xF; | |
1980 | break; | |
1981 | default: | |
1982 | break; | |
1983 | } | |
1984 | ||
1985 | ||
1986 | return 0; | |
1987 | } | |
1988 | ||
1989 | ||
1990 | /** | |
1991 | * Returns the TCO sample rate class for the given card. | |
1992 | **/ | |
1993 | static int hdspm_get_tco_sample_rate(struct hdspm *hdspm) | |
1994 | { | |
1995 | int status; | |
1996 | ||
1997 | if (hdspm->tco) { | |
1998 | switch (hdspm->io_type) { | |
1999 | case RayDAT: | |
2000 | case AIO: | |
2001 | status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); | |
2002 | return (status >> 20) & 0xF; | |
2003 | break; | |
2004 | default: | |
2005 | break; | |
2006 | } | |
2007 | } | |
2008 | ||
2009 | return 0; | |
2010 | } | |
2011 | ||
2012 | ||
2013 | /** | |
2014 | * Returns the SYNC_IN sample rate class for the given card. | |
2015 | **/ | |
2016 | static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm) | |
2017 | { | |
2018 | int status; | |
2019 | ||
2020 | if (hdspm->tco) { | |
2021 | switch (hdspm->io_type) { | |
2022 | case RayDAT: | |
2023 | case AIO: | |
2024 | status = hdspm_read(hdspm, HDSPM_RD_STATUS_2); | |
2025 | return (status >> 12) & 0xF; | |
2026 | break; | |
2027 | default: | |
2028 | break; | |
2029 | } | |
2030 | } | |
2031 | ||
763f356c TI |
2032 | return 0; |
2033 | } | |
2034 | ||
0dca1793 AK |
2035 | |
2036 | /** | |
2037 | * Returns the sample rate class for input source <idx> for | |
2038 | * 'new style' cards like the AIO and RayDAT. | |
2039 | **/ | |
2040 | static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx) | |
2041 | { | |
2042 | int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2); | |
2043 | ||
2044 | return (status >> (idx*4)) & 0xF; | |
2045 | } | |
2046 | ||
2047 | ||
2048 | ||
763f356c | 2049 | #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \ |
0dca1793 AK |
2050 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
2051 | .name = xname, \ | |
2052 | .private_value = xindex, \ | |
2053 | .access = SNDRV_CTL_ELEM_ACCESS_READ, \ | |
2054 | .info = snd_hdspm_info_autosync_sample_rate, \ | |
2055 | .get = snd_hdspm_get_autosync_sample_rate \ | |
763f356c TI |
2056 | } |
2057 | ||
0dca1793 | 2058 | |
98274f07 TI |
2059 | static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, |
2060 | struct snd_ctl_elem_info *uinfo) | |
763f356c | 2061 | { |
763f356c TI |
2062 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; |
2063 | uinfo->count = 1; | |
2064 | uinfo->value.enumerated.items = 10; | |
0dca1793 | 2065 | |
763f356c | 2066 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) |
0dca1793 | 2067 | uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; |
763f356c | 2068 | strcpy(uinfo->value.enumerated.name, |
0dca1793 | 2069 | texts_freq[uinfo->value.enumerated.item]); |
763f356c TI |
2070 | return 0; |
2071 | } | |
2072 | ||
0dca1793 | 2073 | |
98274f07 TI |
2074 | static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, |
2075 | struct snd_ctl_elem_value * | |
763f356c TI |
2076 | ucontrol) |
2077 | { | |
98274f07 | 2078 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c | 2079 | |
0dca1793 AK |
2080 | switch (hdspm->io_type) { |
2081 | case RayDAT: | |
2082 | switch (kcontrol->private_value) { | |
2083 | case 0: | |
2084 | ucontrol->value.enumerated.item[0] = | |
2085 | hdspm_get_wc_sample_rate(hdspm); | |
2086 | break; | |
2087 | case 7: | |
2088 | ucontrol->value.enumerated.item[0] = | |
2089 | hdspm_get_tco_sample_rate(hdspm); | |
2090 | break; | |
2091 | case 8: | |
2092 | ucontrol->value.enumerated.item[0] = | |
2093 | hdspm_get_sync_in_sample_rate(hdspm); | |
2094 | break; | |
2095 | default: | |
2096 | ucontrol->value.enumerated.item[0] = | |
2097 | hdspm_get_s1_sample_rate(hdspm, | |
2098 | kcontrol->private_value-1); | |
2099 | } | |
763f356c | 2100 | |
0dca1793 AK |
2101 | case AIO: |
2102 | switch (kcontrol->private_value) { | |
2103 | case 0: /* WC */ | |
2104 | ucontrol->value.enumerated.item[0] = | |
2105 | hdspm_get_wc_sample_rate(hdspm); | |
2106 | break; | |
2107 | case 4: /* TCO */ | |
2108 | ucontrol->value.enumerated.item[0] = | |
2109 | hdspm_get_tco_sample_rate(hdspm); | |
2110 | break; | |
2111 | case 5: /* SYNC_IN */ | |
2112 | ucontrol->value.enumerated.item[0] = | |
2113 | hdspm_get_sync_in_sample_rate(hdspm); | |
2114 | break; | |
2115 | default: | |
2116 | ucontrol->value.enumerated.item[0] = | |
2117 | hdspm_get_s1_sample_rate(hdspm, | |
2118 | ucontrol->id.index-1); | |
2119 | } | |
7c4a95b5 AK |
2120 | |
2121 | case AES32: | |
2122 | ||
2123 | switch (kcontrol->private_value) { | |
2124 | case 0: /* WC */ | |
2125 | ucontrol->value.enumerated.item[0] = | |
2126 | hdspm_get_wc_sample_rate(hdspm); | |
2127 | break; | |
2128 | case 9: /* TCO */ | |
2129 | ucontrol->value.enumerated.item[0] = | |
2130 | hdspm_get_tco_sample_rate(hdspm); | |
2131 | break; | |
2132 | case 10: /* SYNC_IN */ | |
2133 | ucontrol->value.enumerated.item[0] = | |
2134 | hdspm_get_sync_in_sample_rate(hdspm); | |
2135 | break; | |
2136 | default: /* AES1 to AES8 */ | |
2137 | ucontrol->value.enumerated.item[0] = | |
2138 | hdspm_get_s1_sample_rate(hdspm, | |
2139 | kcontrol->private_value-1); | |
2140 | break; | |
2141 | ||
2142 | } | |
763f356c | 2143 | default: |
0dca1793 | 2144 | break; |
763f356c | 2145 | } |
763f356c | 2146 | |
0dca1793 | 2147 | return 0; |
763f356c TI |
2148 | } |
2149 | ||
2150 | ||
0dca1793 AK |
2151 | #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \ |
2152 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ | |
2153 | .name = xname, \ | |
2154 | .index = xindex, \ | |
2155 | .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ | |
2156 | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
2157 | .info = snd_hdspm_info_system_clock_mode, \ | |
2158 | .get = snd_hdspm_get_system_clock_mode, \ | |
2159 | .put = snd_hdspm_put_system_clock_mode, \ | |
2160 | } | |
2161 | ||
2162 | ||
2163 | /** | |
2164 | * Returns the system clock mode for the given card. | |
2165 | * @returns 0 - master, 1 - slave | |
2166 | **/ | |
2167 | static int hdspm_system_clock_mode(struct hdspm *hdspm) | |
2168 | { | |
2169 | switch (hdspm->io_type) { | |
2170 | case AIO: | |
2171 | case RayDAT: | |
2172 | if (hdspm->settings_register & HDSPM_c0Master) | |
2173 | return 0; | |
2174 | break; | |
763f356c | 2175 | |
0dca1793 AK |
2176 | default: |
2177 | if (hdspm->control_register & HDSPM_ClockModeMaster) | |
2178 | return 0; | |
2179 | } | |
763f356c | 2180 | |
763f356c TI |
2181 | return 1; |
2182 | } | |
2183 | ||
0dca1793 AK |
2184 | |
2185 | /** | |
2186 | * Sets the system clock mode. | |
2187 | * @param mode 0 - master, 1 - slave | |
2188 | **/ | |
2189 | static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode) | |
2190 | { | |
2191 | switch (hdspm->io_type) { | |
2192 | case AIO: | |
2193 | case RayDAT: | |
2194 | if (0 == mode) | |
2195 | hdspm->settings_register |= HDSPM_c0Master; | |
2196 | else | |
2197 | hdspm->settings_register &= ~HDSPM_c0Master; | |
2198 | ||
2199 | hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); | |
2200 | break; | |
2201 | ||
2202 | default: | |
2203 | if (0 == mode) | |
2204 | hdspm->control_register |= HDSPM_ClockModeMaster; | |
2205 | else | |
2206 | hdspm->control_register &= ~HDSPM_ClockModeMaster; | |
2207 | ||
2208 | hdspm_write(hdspm, HDSPM_controlRegister, | |
2209 | hdspm->control_register); | |
2210 | } | |
2211 | } | |
2212 | ||
2213 | ||
2214 | static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol, | |
98274f07 | 2215 | struct snd_ctl_elem_info *uinfo) |
763f356c | 2216 | { |
0dca1793 | 2217 | static char *texts[] = { "Master", "AutoSync" }; |
763f356c TI |
2218 | |
2219 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
2220 | uinfo->count = 1; | |
2221 | uinfo->value.enumerated.items = 2; | |
2222 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
2223 | uinfo->value.enumerated.item = | |
2224 | uinfo->value.enumerated.items - 1; | |
2225 | strcpy(uinfo->value.enumerated.name, | |
2226 | texts[uinfo->value.enumerated.item]); | |
2227 | return 0; | |
2228 | } | |
2229 | ||
98274f07 TI |
2230 | static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol, |
2231 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 2232 | { |
98274f07 | 2233 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c | 2234 | |
0dca1793 | 2235 | ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm); |
763f356c TI |
2236 | return 0; |
2237 | } | |
2238 | ||
0dca1793 AK |
2239 | static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol, |
2240 | struct snd_ctl_elem_value *ucontrol) | |
2241 | { | |
2242 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
2243 | int val; | |
2244 | ||
2245 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
2246 | return -EBUSY; | |
2247 | ||
2248 | val = ucontrol->value.enumerated.item[0]; | |
2249 | if (val < 0) | |
2250 | val = 0; | |
2251 | else if (val > 1) | |
2252 | val = 1; | |
2253 | ||
2254 | hdspm_set_system_clock_mode(hdspm, val); | |
2255 | ||
2256 | return 0; | |
2257 | } | |
2258 | ||
2259 | ||
2260 | #define HDSPM_INTERNAL_CLOCK(xname, xindex) \ | |
2261 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ | |
2262 | .name = xname, \ | |
2263 | .index = xindex, \ | |
2264 | .info = snd_hdspm_info_clock_source, \ | |
2265 | .get = snd_hdspm_get_clock_source, \ | |
2266 | .put = snd_hdspm_put_clock_source \ | |
763f356c TI |
2267 | } |
2268 | ||
0dca1793 | 2269 | |
98274f07 | 2270 | static int hdspm_clock_source(struct hdspm * hdspm) |
763f356c | 2271 | { |
0dca1793 AK |
2272 | switch (hdspm->system_sample_rate) { |
2273 | case 32000: return 0; | |
2274 | case 44100: return 1; | |
2275 | case 48000: return 2; | |
2276 | case 64000: return 3; | |
2277 | case 88200: return 4; | |
2278 | case 96000: return 5; | |
2279 | case 128000: return 6; | |
2280 | case 176400: return 7; | |
2281 | case 192000: return 8; | |
763f356c | 2282 | } |
0dca1793 AK |
2283 | |
2284 | return -1; | |
763f356c TI |
2285 | } |
2286 | ||
98274f07 | 2287 | static int hdspm_set_clock_source(struct hdspm * hdspm, int mode) |
763f356c TI |
2288 | { |
2289 | int rate; | |
2290 | switch (mode) { | |
0dca1793 AK |
2291 | case 0: |
2292 | rate = 32000; break; | |
2293 | case 1: | |
2294 | rate = 44100; break; | |
2295 | case 2: | |
2296 | rate = 48000; break; | |
2297 | case 3: | |
2298 | rate = 64000; break; | |
2299 | case 4: | |
2300 | rate = 88200; break; | |
2301 | case 5: | |
2302 | rate = 96000; break; | |
2303 | case 6: | |
2304 | rate = 128000; break; | |
2305 | case 7: | |
2306 | rate = 176400; break; | |
2307 | case 8: | |
2308 | rate = 192000; break; | |
763f356c | 2309 | default: |
0dca1793 | 2310 | rate = 48000; |
763f356c | 2311 | } |
763f356c TI |
2312 | hdspm_set_rate(hdspm, rate, 1); |
2313 | return 0; | |
2314 | } | |
2315 | ||
98274f07 TI |
2316 | static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol, |
2317 | struct snd_ctl_elem_info *uinfo) | |
763f356c | 2318 | { |
763f356c TI |
2319 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; |
2320 | uinfo->count = 1; | |
0dca1793 | 2321 | uinfo->value.enumerated.items = 9; |
763f356c TI |
2322 | |
2323 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
2324 | uinfo->value.enumerated.item = | |
2325 | uinfo->value.enumerated.items - 1; | |
2326 | ||
2327 | strcpy(uinfo->value.enumerated.name, | |
0dca1793 | 2328 | texts_freq[uinfo->value.enumerated.item+1]); |
763f356c TI |
2329 | |
2330 | return 0; | |
2331 | } | |
2332 | ||
98274f07 TI |
2333 | static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol, |
2334 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 2335 | { |
98274f07 | 2336 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
2337 | |
2338 | ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm); | |
2339 | return 0; | |
2340 | } | |
2341 | ||
98274f07 TI |
2342 | static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol, |
2343 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 2344 | { |
98274f07 | 2345 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
2346 | int change; |
2347 | int val; | |
2348 | ||
2349 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
2350 | return -EBUSY; | |
2351 | val = ucontrol->value.enumerated.item[0]; | |
2352 | if (val < 0) | |
2353 | val = 0; | |
6534599d RB |
2354 | if (val > 9) |
2355 | val = 9; | |
763f356c TI |
2356 | spin_lock_irq(&hdspm->lock); |
2357 | if (val != hdspm_clock_source(hdspm)) | |
2358 | change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0; | |
2359 | else | |
2360 | change = 0; | |
2361 | spin_unlock_irq(&hdspm->lock); | |
2362 | return change; | |
2363 | } | |
2364 | ||
763f356c | 2365 | |
0dca1793 AK |
2366 | #define HDSPM_PREF_SYNC_REF(xname, xindex) \ |
2367 | {.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ | |
2368 | .name = xname, \ | |
2369 | .index = xindex, \ | |
2370 | .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ | |
2371 | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
2372 | .info = snd_hdspm_info_pref_sync_ref, \ | |
2373 | .get = snd_hdspm_get_pref_sync_ref, \ | |
2374 | .put = snd_hdspm_put_pref_sync_ref \ | |
2375 | } | |
2376 | ||
2377 | ||
2378 | /** | |
2379 | * Returns the current preferred sync reference setting. | |
2380 | * The semantics of the return value are depending on the | |
2381 | * card, please see the comments for clarification. | |
2382 | **/ | |
98274f07 | 2383 | static int hdspm_pref_sync_ref(struct hdspm * hdspm) |
763f356c | 2384 | { |
0dca1793 AK |
2385 | switch (hdspm->io_type) { |
2386 | case AES32: | |
3cee5a60 | 2387 | switch (hdspm->control_register & HDSPM_SyncRefMask) { |
0dca1793 AK |
2388 | case 0: return 0; /* WC */ |
2389 | case HDSPM_SyncRef0: return 1; /* AES 1 */ | |
2390 | case HDSPM_SyncRef1: return 2; /* AES 2 */ | |
2391 | case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */ | |
2392 | case HDSPM_SyncRef2: return 4; /* AES 4 */ | |
2393 | case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */ | |
2394 | case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */ | |
2395 | case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0: | |
2396 | return 7; /* AES 7 */ | |
2397 | case HDSPM_SyncRef3: return 8; /* AES 8 */ | |
2398 | case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */ | |
3cee5a60 | 2399 | } |
0dca1793 AK |
2400 | break; |
2401 | ||
2402 | case MADI: | |
2403 | case MADIface: | |
2404 | if (hdspm->tco) { | |
2405 | switch (hdspm->control_register & HDSPM_SyncRefMask) { | |
2406 | case 0: return 0; /* WC */ | |
2407 | case HDSPM_SyncRef0: return 1; /* MADI */ | |
2408 | case HDSPM_SyncRef1: return 2; /* TCO */ | |
2409 | case HDSPM_SyncRef1+HDSPM_SyncRef0: | |
2410 | return 3; /* SYNC_IN */ | |
2411 | } | |
2412 | } else { | |
2413 | switch (hdspm->control_register & HDSPM_SyncRefMask) { | |
2414 | case 0: return 0; /* WC */ | |
2415 | case HDSPM_SyncRef0: return 1; /* MADI */ | |
2416 | case HDSPM_SyncRef1+HDSPM_SyncRef0: | |
2417 | return 2; /* SYNC_IN */ | |
2418 | } | |
2419 | } | |
2420 | break; | |
2421 | ||
2422 | case RayDAT: | |
2423 | if (hdspm->tco) { | |
2424 | switch ((hdspm->settings_register & | |
2425 | HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { | |
2426 | case 0: return 0; /* WC */ | |
2427 | case 3: return 1; /* ADAT 1 */ | |
2428 | case 4: return 2; /* ADAT 2 */ | |
2429 | case 5: return 3; /* ADAT 3 */ | |
2430 | case 6: return 4; /* ADAT 4 */ | |
2431 | case 1: return 5; /* AES */ | |
2432 | case 2: return 6; /* SPDIF */ | |
2433 | case 9: return 7; /* TCO */ | |
2434 | case 10: return 8; /* SYNC_IN */ | |
2435 | } | |
2436 | } else { | |
2437 | switch ((hdspm->settings_register & | |
2438 | HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { | |
2439 | case 0: return 0; /* WC */ | |
2440 | case 3: return 1; /* ADAT 1 */ | |
2441 | case 4: return 2; /* ADAT 2 */ | |
2442 | case 5: return 3; /* ADAT 3 */ | |
2443 | case 6: return 4; /* ADAT 4 */ | |
2444 | case 1: return 5; /* AES */ | |
2445 | case 2: return 6; /* SPDIF */ | |
2446 | case 10: return 7; /* SYNC_IN */ | |
2447 | } | |
3cee5a60 | 2448 | } |
0dca1793 AK |
2449 | |
2450 | break; | |
2451 | ||
2452 | case AIO: | |
2453 | if (hdspm->tco) { | |
2454 | switch ((hdspm->settings_register & | |
2455 | HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { | |
2456 | case 0: return 0; /* WC */ | |
2457 | case 3: return 1; /* ADAT */ | |
2458 | case 1: return 2; /* AES */ | |
2459 | case 2: return 3; /* SPDIF */ | |
2460 | case 9: return 4; /* TCO */ | |
2461 | case 10: return 5; /* SYNC_IN */ | |
2462 | } | |
2463 | } else { | |
2464 | switch ((hdspm->settings_register & | |
2465 | HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { | |
2466 | case 0: return 0; /* WC */ | |
2467 | case 3: return 1; /* ADAT */ | |
2468 | case 1: return 2; /* AES */ | |
2469 | case 2: return 3; /* SPDIF */ | |
2470 | case 10: return 4; /* SYNC_IN */ | |
2471 | } | |
2472 | } | |
2473 | ||
2474 | break; | |
763f356c TI |
2475 | } |
2476 | ||
0dca1793 | 2477 | return -1; |
763f356c TI |
2478 | } |
2479 | ||
0dca1793 AK |
2480 | |
2481 | /** | |
2482 | * Set the preferred sync reference to <pref>. The semantics | |
2483 | * of <pref> are depending on the card type, see the comments | |
2484 | * for clarification. | |
2485 | **/ | |
98274f07 | 2486 | static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref) |
763f356c | 2487 | { |
0dca1793 | 2488 | int p = 0; |
763f356c | 2489 | |
0dca1793 AK |
2490 | switch (hdspm->io_type) { |
2491 | case AES32: | |
2492 | hdspm->control_register &= ~HDSPM_SyncRefMask; | |
3cee5a60 | 2493 | switch (pref) { |
0dca1793 AK |
2494 | case 0: /* WC */ |
2495 | break; | |
2496 | case 1: /* AES 1 */ | |
2497 | hdspm->control_register |= HDSPM_SyncRef0; | |
2498 | break; | |
2499 | case 2: /* AES 2 */ | |
2500 | hdspm->control_register |= HDSPM_SyncRef1; | |
2501 | break; | |
2502 | case 3: /* AES 3 */ | |
2503 | hdspm->control_register |= | |
2504 | HDSPM_SyncRef1+HDSPM_SyncRef0; | |
2505 | break; | |
2506 | case 4: /* AES 4 */ | |
2507 | hdspm->control_register |= HDSPM_SyncRef2; | |
2508 | break; | |
2509 | case 5: /* AES 5 */ | |
2510 | hdspm->control_register |= | |
2511 | HDSPM_SyncRef2+HDSPM_SyncRef0; | |
2512 | break; | |
2513 | case 6: /* AES 6 */ | |
2514 | hdspm->control_register |= | |
2515 | HDSPM_SyncRef2+HDSPM_SyncRef1; | |
2516 | break; | |
2517 | case 7: /* AES 7 */ | |
2518 | hdspm->control_register |= | |
2519 | HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0; | |
3cee5a60 | 2520 | break; |
0dca1793 AK |
2521 | case 8: /* AES 8 */ |
2522 | hdspm->control_register |= HDSPM_SyncRef3; | |
2523 | break; | |
2524 | case 9: /* TCO */ | |
2525 | hdspm->control_register |= | |
2526 | HDSPM_SyncRef3+HDSPM_SyncRef0; | |
3cee5a60 RB |
2527 | break; |
2528 | default: | |
2529 | return -1; | |
2530 | } | |
0dca1793 AK |
2531 | |
2532 | break; | |
2533 | ||
2534 | case MADI: | |
2535 | case MADIface: | |
2536 | hdspm->control_register &= ~HDSPM_SyncRefMask; | |
2537 | if (hdspm->tco) { | |
2538 | switch (pref) { | |
2539 | case 0: /* WC */ | |
2540 | break; | |
2541 | case 1: /* MADI */ | |
2542 | hdspm->control_register |= HDSPM_SyncRef0; | |
2543 | break; | |
2544 | case 2: /* TCO */ | |
2545 | hdspm->control_register |= HDSPM_SyncRef1; | |
2546 | break; | |
2547 | case 3: /* SYNC_IN */ | |
2548 | hdspm->control_register |= | |
2549 | HDSPM_SyncRef0+HDSPM_SyncRef1; | |
2550 | break; | |
2551 | default: | |
2552 | return -1; | |
2553 | } | |
2554 | } else { | |
2555 | switch (pref) { | |
2556 | case 0: /* WC */ | |
2557 | break; | |
2558 | case 1: /* MADI */ | |
2559 | hdspm->control_register |= HDSPM_SyncRef0; | |
2560 | break; | |
2561 | case 2: /* SYNC_IN */ | |
2562 | hdspm->control_register |= | |
2563 | HDSPM_SyncRef0+HDSPM_SyncRef1; | |
2564 | break; | |
2565 | default: | |
2566 | return -1; | |
2567 | } | |
2568 | } | |
2569 | ||
2570 | break; | |
2571 | ||
2572 | case RayDAT: | |
2573 | if (hdspm->tco) { | |
2574 | switch (pref) { | |
2575 | case 0: p = 0; break; /* WC */ | |
2576 | case 1: p = 3; break; /* ADAT 1 */ | |
2577 | case 2: p = 4; break; /* ADAT 2 */ | |
2578 | case 3: p = 5; break; /* ADAT 3 */ | |
2579 | case 4: p = 6; break; /* ADAT 4 */ | |
2580 | case 5: p = 1; break; /* AES */ | |
2581 | case 6: p = 2; break; /* SPDIF */ | |
2582 | case 7: p = 9; break; /* TCO */ | |
2583 | case 8: p = 10; break; /* SYNC_IN */ | |
2584 | default: return -1; | |
2585 | } | |
2586 | } else { | |
2587 | switch (pref) { | |
2588 | case 0: p = 0; break; /* WC */ | |
2589 | case 1: p = 3; break; /* ADAT 1 */ | |
2590 | case 2: p = 4; break; /* ADAT 2 */ | |
2591 | case 3: p = 5; break; /* ADAT 3 */ | |
2592 | case 4: p = 6; break; /* ADAT 4 */ | |
2593 | case 5: p = 1; break; /* AES */ | |
2594 | case 6: p = 2; break; /* SPDIF */ | |
2595 | case 7: p = 10; break; /* SYNC_IN */ | |
2596 | default: return -1; | |
2597 | } | |
2598 | } | |
2599 | break; | |
2600 | ||
2601 | case AIO: | |
2602 | if (hdspm->tco) { | |
2603 | switch (pref) { | |
2604 | case 0: p = 0; break; /* WC */ | |
2605 | case 1: p = 3; break; /* ADAT */ | |
2606 | case 2: p = 1; break; /* AES */ | |
2607 | case 3: p = 2; break; /* SPDIF */ | |
2608 | case 4: p = 9; break; /* TCO */ | |
2609 | case 5: p = 10; break; /* SYNC_IN */ | |
2610 | default: return -1; | |
2611 | } | |
2612 | } else { | |
2613 | switch (pref) { | |
2614 | case 0: p = 0; break; /* WC */ | |
2615 | case 1: p = 3; break; /* ADAT */ | |
2616 | case 2: p = 1; break; /* AES */ | |
2617 | case 3: p = 2; break; /* SPDIF */ | |
2618 | case 4: p = 10; break; /* SYNC_IN */ | |
2619 | default: return -1; | |
2620 | } | |
2621 | } | |
2622 | break; | |
763f356c | 2623 | } |
0dca1793 AK |
2624 | |
2625 | switch (hdspm->io_type) { | |
2626 | case RayDAT: | |
2627 | case AIO: | |
2628 | hdspm->settings_register &= ~HDSPM_c0_SyncRefMask; | |
2629 | hdspm->settings_register |= HDSPM_c0_SyncRef0 * p; | |
2630 | hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); | |
2631 | break; | |
2632 | ||
2633 | case MADI: | |
2634 | case MADIface: | |
2635 | case AES32: | |
2636 | hdspm_write(hdspm, HDSPM_controlRegister, | |
2637 | hdspm->control_register); | |
2638 | } | |
2639 | ||
763f356c TI |
2640 | return 0; |
2641 | } | |
2642 | ||
0dca1793 | 2643 | |
98274f07 TI |
2644 | static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol, |
2645 | struct snd_ctl_elem_info *uinfo) | |
763f356c | 2646 | { |
3cee5a60 | 2647 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c | 2648 | |
0dca1793 AK |
2649 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; |
2650 | uinfo->count = 1; | |
2651 | uinfo->value.enumerated.items = hdspm->texts_autosync_items; | |
3cee5a60 | 2652 | |
0dca1793 AK |
2653 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) |
2654 | uinfo->value.enumerated.item = | |
2655 | uinfo->value.enumerated.items - 1; | |
3cee5a60 | 2656 | |
0dca1793 AK |
2657 | strcpy(uinfo->value.enumerated.name, |
2658 | hdspm->texts_autosync[uinfo->value.enumerated.item]); | |
3cee5a60 | 2659 | |
763f356c TI |
2660 | return 0; |
2661 | } | |
2662 | ||
98274f07 TI |
2663 | static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol, |
2664 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 2665 | { |
98274f07 | 2666 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
0dca1793 | 2667 | int psf = hdspm_pref_sync_ref(hdspm); |
763f356c | 2668 | |
0dca1793 AK |
2669 | if (psf >= 0) { |
2670 | ucontrol->value.enumerated.item[0] = psf; | |
2671 | return 0; | |
2672 | } | |
2673 | ||
2674 | return -1; | |
763f356c TI |
2675 | } |
2676 | ||
98274f07 TI |
2677 | static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol, |
2678 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 2679 | { |
98274f07 | 2680 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
0dca1793 | 2681 | int val, change = 0; |
763f356c TI |
2682 | |
2683 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
2684 | return -EBUSY; | |
2685 | ||
0dca1793 AK |
2686 | val = ucontrol->value.enumerated.item[0]; |
2687 | ||
2688 | if (val < 0) | |
2689 | val = 0; | |
2690 | else if (val >= hdspm->texts_autosync_items) | |
2691 | val = hdspm->texts_autosync_items-1; | |
763f356c TI |
2692 | |
2693 | spin_lock_irq(&hdspm->lock); | |
0dca1793 AK |
2694 | if (val != hdspm_pref_sync_ref(hdspm)) |
2695 | change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0; | |
2696 | ||
763f356c TI |
2697 | spin_unlock_irq(&hdspm->lock); |
2698 | return change; | |
2699 | } | |
2700 | ||
0dca1793 | 2701 | |
763f356c | 2702 | #define HDSPM_AUTOSYNC_REF(xname, xindex) \ |
67ed4161 | 2703 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
763f356c TI |
2704 | .name = xname, \ |
2705 | .index = xindex, \ | |
2706 | .access = SNDRV_CTL_ELEM_ACCESS_READ, \ | |
2707 | .info = snd_hdspm_info_autosync_ref, \ | |
2708 | .get = snd_hdspm_get_autosync_ref, \ | |
2709 | } | |
2710 | ||
0dca1793 | 2711 | static int hdspm_autosync_ref(struct hdspm *hdspm) |
763f356c | 2712 | { |
0dca1793 | 2713 | if (AES32 == hdspm->io_type) { |
3cee5a60 | 2714 | unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister); |
0dca1793 AK |
2715 | unsigned int syncref = |
2716 | (status >> HDSPM_AES32_syncref_bit) & 0xF; | |
3cee5a60 RB |
2717 | if (syncref == 0) |
2718 | return HDSPM_AES32_AUTOSYNC_FROM_WORD; | |
2719 | if (syncref <= 8) | |
2720 | return syncref; | |
2721 | return HDSPM_AES32_AUTOSYNC_FROM_NONE; | |
0dca1793 | 2722 | } else if (MADI == hdspm->io_type) { |
3cee5a60 RB |
2723 | /* This looks at the autosync selected sync reference */ |
2724 | unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2); | |
2725 | ||
2726 | switch (status2 & HDSPM_SelSyncRefMask) { | |
2727 | case HDSPM_SelSyncRef_WORD: | |
2728 | return HDSPM_AUTOSYNC_FROM_WORD; | |
2729 | case HDSPM_SelSyncRef_MADI: | |
2730 | return HDSPM_AUTOSYNC_FROM_MADI; | |
0dca1793 AK |
2731 | case HDSPM_SelSyncRef_TCO: |
2732 | return HDSPM_AUTOSYNC_FROM_TCO; | |
2733 | case HDSPM_SelSyncRef_SyncIn: | |
2734 | return HDSPM_AUTOSYNC_FROM_SYNC_IN; | |
3cee5a60 RB |
2735 | case HDSPM_SelSyncRef_NVALID: |
2736 | return HDSPM_AUTOSYNC_FROM_NONE; | |
2737 | default: | |
2738 | return 0; | |
2739 | } | |
763f356c | 2740 | |
763f356c | 2741 | } |
0dca1793 | 2742 | return 0; |
763f356c TI |
2743 | } |
2744 | ||
0dca1793 | 2745 | |
98274f07 TI |
2746 | static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol, |
2747 | struct snd_ctl_elem_info *uinfo) | |
763f356c | 2748 | { |
3cee5a60 | 2749 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c | 2750 | |
0dca1793 | 2751 | if (AES32 == hdspm->io_type) { |
3cee5a60 RB |
2752 | static char *texts[] = { "WordClock", "AES1", "AES2", "AES3", |
2753 | "AES4", "AES5", "AES6", "AES7", "AES8", "None"}; | |
2754 | ||
2755 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
2756 | uinfo->count = 1; | |
2757 | uinfo->value.enumerated.items = 10; | |
ef5fa1a4 TI |
2758 | if (uinfo->value.enumerated.item >= |
2759 | uinfo->value.enumerated.items) | |
3cee5a60 RB |
2760 | uinfo->value.enumerated.item = |
2761 | uinfo->value.enumerated.items - 1; | |
2762 | strcpy(uinfo->value.enumerated.name, | |
2763 | texts[uinfo->value.enumerated.item]); | |
0dca1793 AK |
2764 | } else if (MADI == hdspm->io_type) { |
2765 | static char *texts[] = {"Word Clock", "MADI", "TCO", | |
2766 | "Sync In", "None" }; | |
3cee5a60 RB |
2767 | |
2768 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
2769 | uinfo->count = 1; | |
0dca1793 | 2770 | uinfo->value.enumerated.items = 5; |
ef5fa1a4 | 2771 | if (uinfo->value.enumerated.item >= |
0dca1793 | 2772 | uinfo->value.enumerated.items) |
3cee5a60 RB |
2773 | uinfo->value.enumerated.item = |
2774 | uinfo->value.enumerated.items - 1; | |
2775 | strcpy(uinfo->value.enumerated.name, | |
2776 | texts[uinfo->value.enumerated.item]); | |
2777 | } | |
763f356c TI |
2778 | return 0; |
2779 | } | |
2780 | ||
98274f07 TI |
2781 | static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol, |
2782 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 2783 | { |
98274f07 | 2784 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c | 2785 | |
6534599d | 2786 | ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm); |
763f356c TI |
2787 | return 0; |
2788 | } | |
2789 | ||
0dca1793 | 2790 | |
763f356c | 2791 | #define HDSPM_LINE_OUT(xname, xindex) \ |
67ed4161 | 2792 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
763f356c TI |
2793 | .name = xname, \ |
2794 | .index = xindex, \ | |
2795 | .info = snd_hdspm_info_line_out, \ | |
2796 | .get = snd_hdspm_get_line_out, \ | |
2797 | .put = snd_hdspm_put_line_out \ | |
2798 | } | |
2799 | ||
98274f07 | 2800 | static int hdspm_line_out(struct hdspm * hdspm) |
763f356c TI |
2801 | { |
2802 | return (hdspm->control_register & HDSPM_LineOut) ? 1 : 0; | |
2803 | } | |
2804 | ||
2805 | ||
98274f07 | 2806 | static int hdspm_set_line_output(struct hdspm * hdspm, int out) |
763f356c TI |
2807 | { |
2808 | if (out) | |
2809 | hdspm->control_register |= HDSPM_LineOut; | |
2810 | else | |
2811 | hdspm->control_register &= ~HDSPM_LineOut; | |
2812 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); | |
2813 | ||
2814 | return 0; | |
2815 | } | |
2816 | ||
a5ce8890 | 2817 | #define snd_hdspm_info_line_out snd_ctl_boolean_mono_info |
763f356c | 2818 | |
98274f07 TI |
2819 | static int snd_hdspm_get_line_out(struct snd_kcontrol *kcontrol, |
2820 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 2821 | { |
98274f07 | 2822 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
2823 | |
2824 | spin_lock_irq(&hdspm->lock); | |
2825 | ucontrol->value.integer.value[0] = hdspm_line_out(hdspm); | |
2826 | spin_unlock_irq(&hdspm->lock); | |
2827 | return 0; | |
2828 | } | |
2829 | ||
98274f07 TI |
2830 | static int snd_hdspm_put_line_out(struct snd_kcontrol *kcontrol, |
2831 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 2832 | { |
98274f07 | 2833 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
2834 | int change; |
2835 | unsigned int val; | |
2836 | ||
2837 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
2838 | return -EBUSY; | |
2839 | val = ucontrol->value.integer.value[0] & 1; | |
2840 | spin_lock_irq(&hdspm->lock); | |
2841 | change = (int) val != hdspm_line_out(hdspm); | |
2842 | hdspm_set_line_output(hdspm, val); | |
2843 | spin_unlock_irq(&hdspm->lock); | |
2844 | return change; | |
2845 | } | |
2846 | ||
0dca1793 | 2847 | |
763f356c | 2848 | #define HDSPM_TX_64(xname, xindex) \ |
67ed4161 | 2849 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
763f356c TI |
2850 | .name = xname, \ |
2851 | .index = xindex, \ | |
2852 | .info = snd_hdspm_info_tx_64, \ | |
2853 | .get = snd_hdspm_get_tx_64, \ | |
2854 | .put = snd_hdspm_put_tx_64 \ | |
2855 | } | |
2856 | ||
98274f07 | 2857 | static int hdspm_tx_64(struct hdspm * hdspm) |
763f356c TI |
2858 | { |
2859 | return (hdspm->control_register & HDSPM_TX_64ch) ? 1 : 0; | |
2860 | } | |
2861 | ||
98274f07 | 2862 | static int hdspm_set_tx_64(struct hdspm * hdspm, int out) |
763f356c TI |
2863 | { |
2864 | if (out) | |
2865 | hdspm->control_register |= HDSPM_TX_64ch; | |
2866 | else | |
2867 | hdspm->control_register &= ~HDSPM_TX_64ch; | |
2868 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); | |
2869 | ||
2870 | return 0; | |
2871 | } | |
2872 | ||
a5ce8890 | 2873 | #define snd_hdspm_info_tx_64 snd_ctl_boolean_mono_info |
763f356c | 2874 | |
98274f07 TI |
2875 | static int snd_hdspm_get_tx_64(struct snd_kcontrol *kcontrol, |
2876 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 2877 | { |
98274f07 | 2878 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
2879 | |
2880 | spin_lock_irq(&hdspm->lock); | |
2881 | ucontrol->value.integer.value[0] = hdspm_tx_64(hdspm); | |
2882 | spin_unlock_irq(&hdspm->lock); | |
2883 | return 0; | |
2884 | } | |
2885 | ||
98274f07 TI |
2886 | static int snd_hdspm_put_tx_64(struct snd_kcontrol *kcontrol, |
2887 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 2888 | { |
98274f07 | 2889 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
2890 | int change; |
2891 | unsigned int val; | |
2892 | ||
2893 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
2894 | return -EBUSY; | |
2895 | val = ucontrol->value.integer.value[0] & 1; | |
2896 | spin_lock_irq(&hdspm->lock); | |
2897 | change = (int) val != hdspm_tx_64(hdspm); | |
2898 | hdspm_set_tx_64(hdspm, val); | |
2899 | spin_unlock_irq(&hdspm->lock); | |
2900 | return change; | |
2901 | } | |
2902 | ||
0dca1793 | 2903 | |
763f356c | 2904 | #define HDSPM_C_TMS(xname, xindex) \ |
67ed4161 | 2905 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
763f356c TI |
2906 | .name = xname, \ |
2907 | .index = xindex, \ | |
2908 | .info = snd_hdspm_info_c_tms, \ | |
2909 | .get = snd_hdspm_get_c_tms, \ | |
2910 | .put = snd_hdspm_put_c_tms \ | |
2911 | } | |
2912 | ||
98274f07 | 2913 | static int hdspm_c_tms(struct hdspm * hdspm) |
763f356c TI |
2914 | { |
2915 | return (hdspm->control_register & HDSPM_clr_tms) ? 1 : 0; | |
2916 | } | |
2917 | ||
98274f07 | 2918 | static int hdspm_set_c_tms(struct hdspm * hdspm, int out) |
763f356c TI |
2919 | { |
2920 | if (out) | |
2921 | hdspm->control_register |= HDSPM_clr_tms; | |
2922 | else | |
2923 | hdspm->control_register &= ~HDSPM_clr_tms; | |
2924 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); | |
2925 | ||
2926 | return 0; | |
2927 | } | |
2928 | ||
a5ce8890 | 2929 | #define snd_hdspm_info_c_tms snd_ctl_boolean_mono_info |
763f356c | 2930 | |
98274f07 TI |
2931 | static int snd_hdspm_get_c_tms(struct snd_kcontrol *kcontrol, |
2932 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 2933 | { |
98274f07 | 2934 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
2935 | |
2936 | spin_lock_irq(&hdspm->lock); | |
2937 | ucontrol->value.integer.value[0] = hdspm_c_tms(hdspm); | |
2938 | spin_unlock_irq(&hdspm->lock); | |
2939 | return 0; | |
2940 | } | |
2941 | ||
98274f07 TI |
2942 | static int snd_hdspm_put_c_tms(struct snd_kcontrol *kcontrol, |
2943 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 2944 | { |
98274f07 | 2945 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
2946 | int change; |
2947 | unsigned int val; | |
2948 | ||
2949 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
2950 | return -EBUSY; | |
2951 | val = ucontrol->value.integer.value[0] & 1; | |
2952 | spin_lock_irq(&hdspm->lock); | |
2953 | change = (int) val != hdspm_c_tms(hdspm); | |
2954 | hdspm_set_c_tms(hdspm, val); | |
2955 | spin_unlock_irq(&hdspm->lock); | |
2956 | return change; | |
2957 | } | |
2958 | ||
0dca1793 | 2959 | |
763f356c | 2960 | #define HDSPM_SAFE_MODE(xname, xindex) \ |
67ed4161 | 2961 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
763f356c TI |
2962 | .name = xname, \ |
2963 | .index = xindex, \ | |
2964 | .info = snd_hdspm_info_safe_mode, \ | |
2965 | .get = snd_hdspm_get_safe_mode, \ | |
2966 | .put = snd_hdspm_put_safe_mode \ | |
2967 | } | |
2968 | ||
3cee5a60 RB |
2969 | static int hdspm_safe_mode(struct hdspm * hdspm) |
2970 | { | |
2971 | return (hdspm->control_register & HDSPM_AutoInp) ? 1 : 0; | |
2972 | } | |
2973 | ||
2974 | static int hdspm_set_safe_mode(struct hdspm * hdspm, int out) | |
2975 | { | |
2976 | if (out) | |
2977 | hdspm->control_register |= HDSPM_AutoInp; | |
2978 | else | |
2979 | hdspm->control_register &= ~HDSPM_AutoInp; | |
2980 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); | |
2981 | ||
2982 | return 0; | |
2983 | } | |
2984 | ||
a5ce8890 | 2985 | #define snd_hdspm_info_safe_mode snd_ctl_boolean_mono_info |
3cee5a60 RB |
2986 | |
2987 | static int snd_hdspm_get_safe_mode(struct snd_kcontrol *kcontrol, | |
2988 | struct snd_ctl_elem_value *ucontrol) | |
2989 | { | |
2990 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
2991 | ||
2992 | spin_lock_irq(&hdspm->lock); | |
2993 | ucontrol->value.integer.value[0] = hdspm_safe_mode(hdspm); | |
2994 | spin_unlock_irq(&hdspm->lock); | |
2995 | return 0; | |
2996 | } | |
2997 | ||
2998 | static int snd_hdspm_put_safe_mode(struct snd_kcontrol *kcontrol, | |
2999 | struct snd_ctl_elem_value *ucontrol) | |
3000 | { | |
3001 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
3002 | int change; | |
3003 | unsigned int val; | |
3004 | ||
3005 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
3006 | return -EBUSY; | |
3007 | val = ucontrol->value.integer.value[0] & 1; | |
3008 | spin_lock_irq(&hdspm->lock); | |
3009 | change = (int) val != hdspm_safe_mode(hdspm); | |
3010 | hdspm_set_safe_mode(hdspm, val); | |
3011 | spin_unlock_irq(&hdspm->lock); | |
3012 | return change; | |
3013 | } | |
3014 | ||
0dca1793 | 3015 | |
3cee5a60 RB |
3016 | #define HDSPM_EMPHASIS(xname, xindex) \ |
3017 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ | |
3018 | .name = xname, \ | |
3019 | .index = xindex, \ | |
3020 | .info = snd_hdspm_info_emphasis, \ | |
3021 | .get = snd_hdspm_get_emphasis, \ | |
3022 | .put = snd_hdspm_put_emphasis \ | |
3023 | } | |
3024 | ||
3025 | static int hdspm_emphasis(struct hdspm * hdspm) | |
3026 | { | |
3027 | return (hdspm->control_register & HDSPM_Emphasis) ? 1 : 0; | |
3028 | } | |
3029 | ||
3030 | static int hdspm_set_emphasis(struct hdspm * hdspm, int emp) | |
3031 | { | |
3032 | if (emp) | |
3033 | hdspm->control_register |= HDSPM_Emphasis; | |
3034 | else | |
3035 | hdspm->control_register &= ~HDSPM_Emphasis; | |
3036 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); | |
3037 | ||
3038 | return 0; | |
3039 | } | |
3040 | ||
a5ce8890 | 3041 | #define snd_hdspm_info_emphasis snd_ctl_boolean_mono_info |
3cee5a60 RB |
3042 | |
3043 | static int snd_hdspm_get_emphasis(struct snd_kcontrol *kcontrol, | |
3044 | struct snd_ctl_elem_value *ucontrol) | |
3045 | { | |
3046 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
3047 | ||
3048 | spin_lock_irq(&hdspm->lock); | |
3049 | ucontrol->value.enumerated.item[0] = hdspm_emphasis(hdspm); | |
3050 | spin_unlock_irq(&hdspm->lock); | |
3051 | return 0; | |
3052 | } | |
3053 | ||
3054 | static int snd_hdspm_put_emphasis(struct snd_kcontrol *kcontrol, | |
3055 | struct snd_ctl_elem_value *ucontrol) | |
3056 | { | |
3057 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
3058 | int change; | |
3059 | unsigned int val; | |
3060 | ||
3061 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
3062 | return -EBUSY; | |
3063 | val = ucontrol->value.integer.value[0] & 1; | |
3064 | spin_lock_irq(&hdspm->lock); | |
3065 | change = (int) val != hdspm_emphasis(hdspm); | |
3066 | hdspm_set_emphasis(hdspm, val); | |
3067 | spin_unlock_irq(&hdspm->lock); | |
3068 | return change; | |
3069 | } | |
3070 | ||
0dca1793 | 3071 | |
3cee5a60 RB |
3072 | #define HDSPM_DOLBY(xname, xindex) \ |
3073 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ | |
3074 | .name = xname, \ | |
3075 | .index = xindex, \ | |
3076 | .info = snd_hdspm_info_dolby, \ | |
3077 | .get = snd_hdspm_get_dolby, \ | |
3078 | .put = snd_hdspm_put_dolby \ | |
3079 | } | |
3080 | ||
3081 | static int hdspm_dolby(struct hdspm * hdspm) | |
3082 | { | |
3083 | return (hdspm->control_register & HDSPM_Dolby) ? 1 : 0; | |
3084 | } | |
3085 | ||
3086 | static int hdspm_set_dolby(struct hdspm * hdspm, int dol) | |
3087 | { | |
3088 | if (dol) | |
3089 | hdspm->control_register |= HDSPM_Dolby; | |
3090 | else | |
3091 | hdspm->control_register &= ~HDSPM_Dolby; | |
3092 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); | |
3093 | ||
3094 | return 0; | |
3095 | } | |
3096 | ||
a5ce8890 | 3097 | #define snd_hdspm_info_dolby snd_ctl_boolean_mono_info |
3cee5a60 RB |
3098 | |
3099 | static int snd_hdspm_get_dolby(struct snd_kcontrol *kcontrol, | |
3100 | struct snd_ctl_elem_value *ucontrol) | |
3101 | { | |
3102 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
3103 | ||
3104 | spin_lock_irq(&hdspm->lock); | |
3105 | ucontrol->value.enumerated.item[0] = hdspm_dolby(hdspm); | |
3106 | spin_unlock_irq(&hdspm->lock); | |
3107 | return 0; | |
3108 | } | |
3109 | ||
3110 | static int snd_hdspm_put_dolby(struct snd_kcontrol *kcontrol, | |
3111 | struct snd_ctl_elem_value *ucontrol) | |
3112 | { | |
3113 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
3114 | int change; | |
3115 | unsigned int val; | |
3116 | ||
3117 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
3118 | return -EBUSY; | |
3119 | val = ucontrol->value.integer.value[0] & 1; | |
3120 | spin_lock_irq(&hdspm->lock); | |
3121 | change = (int) val != hdspm_dolby(hdspm); | |
3122 | hdspm_set_dolby(hdspm, val); | |
3123 | spin_unlock_irq(&hdspm->lock); | |
3124 | return change; | |
3125 | } | |
3126 | ||
0dca1793 | 3127 | |
3cee5a60 RB |
3128 | #define HDSPM_PROFESSIONAL(xname, xindex) \ |
3129 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ | |
3130 | .name = xname, \ | |
3131 | .index = xindex, \ | |
3132 | .info = snd_hdspm_info_professional, \ | |
3133 | .get = snd_hdspm_get_professional, \ | |
3134 | .put = snd_hdspm_put_professional \ | |
3135 | } | |
3136 | ||
3137 | static int hdspm_professional(struct hdspm * hdspm) | |
3138 | { | |
3139 | return (hdspm->control_register & HDSPM_Professional) ? 1 : 0; | |
3140 | } | |
3141 | ||
3142 | static int hdspm_set_professional(struct hdspm * hdspm, int dol) | |
3143 | { | |
3144 | if (dol) | |
3145 | hdspm->control_register |= HDSPM_Professional; | |
3146 | else | |
3147 | hdspm->control_register &= ~HDSPM_Professional; | |
3148 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); | |
3149 | ||
3150 | return 0; | |
3151 | } | |
3152 | ||
a5ce8890 | 3153 | #define snd_hdspm_info_professional snd_ctl_boolean_mono_info |
3cee5a60 RB |
3154 | |
3155 | static int snd_hdspm_get_professional(struct snd_kcontrol *kcontrol, | |
3156 | struct snd_ctl_elem_value *ucontrol) | |
3157 | { | |
3158 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
3159 | ||
3160 | spin_lock_irq(&hdspm->lock); | |
3161 | ucontrol->value.enumerated.item[0] = hdspm_professional(hdspm); | |
3162 | spin_unlock_irq(&hdspm->lock); | |
3163 | return 0; | |
3164 | } | |
3165 | ||
3166 | static int snd_hdspm_put_professional(struct snd_kcontrol *kcontrol, | |
3167 | struct snd_ctl_elem_value *ucontrol) | |
3168 | { | |
3169 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
3170 | int change; | |
3171 | unsigned int val; | |
3172 | ||
3173 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
3174 | return -EBUSY; | |
3175 | val = ucontrol->value.integer.value[0] & 1; | |
3176 | spin_lock_irq(&hdspm->lock); | |
3177 | change = (int) val != hdspm_professional(hdspm); | |
3178 | hdspm_set_professional(hdspm, val); | |
3179 | spin_unlock_irq(&hdspm->lock); | |
3180 | return change; | |
3181 | } | |
3182 | ||
3183 | #define HDSPM_INPUT_SELECT(xname, xindex) \ | |
3184 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ | |
3185 | .name = xname, \ | |
3186 | .index = xindex, \ | |
3187 | .info = snd_hdspm_info_input_select, \ | |
3188 | .get = snd_hdspm_get_input_select, \ | |
3189 | .put = snd_hdspm_put_input_select \ | |
3190 | } | |
3191 | ||
3192 | static int hdspm_input_select(struct hdspm * hdspm) | |
3193 | { | |
3194 | return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0; | |
3195 | } | |
3196 | ||
3197 | static int hdspm_set_input_select(struct hdspm * hdspm, int out) | |
3198 | { | |
3199 | if (out) | |
3200 | hdspm->control_register |= HDSPM_InputSelect0; | |
3201 | else | |
3202 | hdspm->control_register &= ~HDSPM_InputSelect0; | |
3203 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); | |
3204 | ||
3205 | return 0; | |
3206 | } | |
3207 | ||
3208 | static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol, | |
3209 | struct snd_ctl_elem_info *uinfo) | |
3210 | { | |
3211 | static char *texts[] = { "optical", "coaxial" }; | |
3212 | ||
3213 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
3214 | uinfo->count = 1; | |
3215 | uinfo->value.enumerated.items = 2; | |
3216 | ||
3217 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
3218 | uinfo->value.enumerated.item = | |
3219 | uinfo->value.enumerated.items - 1; | |
3220 | strcpy(uinfo->value.enumerated.name, | |
3221 | texts[uinfo->value.enumerated.item]); | |
3222 | ||
3223 | return 0; | |
3224 | } | |
3225 | ||
3226 | static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol, | |
3227 | struct snd_ctl_elem_value *ucontrol) | |
3228 | { | |
3229 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
3230 | ||
3231 | spin_lock_irq(&hdspm->lock); | |
3232 | ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm); | |
3233 | spin_unlock_irq(&hdspm->lock); | |
3234 | return 0; | |
3235 | } | |
3236 | ||
3237 | static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol, | |
3238 | struct snd_ctl_elem_value *ucontrol) | |
3239 | { | |
3240 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
3241 | int change; | |
3242 | unsigned int val; | |
3243 | ||
3244 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
3245 | return -EBUSY; | |
3246 | val = ucontrol->value.integer.value[0] & 1; | |
3247 | spin_lock_irq(&hdspm->lock); | |
3248 | change = (int) val != hdspm_input_select(hdspm); | |
3249 | hdspm_set_input_select(hdspm, val); | |
3250 | spin_unlock_irq(&hdspm->lock); | |
3251 | return change; | |
3252 | } | |
3253 | ||
0dca1793 | 3254 | |
3cee5a60 RB |
3255 | #define HDSPM_DS_WIRE(xname, xindex) \ |
3256 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ | |
3257 | .name = xname, \ | |
3258 | .index = xindex, \ | |
3259 | .info = snd_hdspm_info_ds_wire, \ | |
3260 | .get = snd_hdspm_get_ds_wire, \ | |
3261 | .put = snd_hdspm_put_ds_wire \ | |
3262 | } | |
3263 | ||
3264 | static int hdspm_ds_wire(struct hdspm * hdspm) | |
763f356c | 3265 | { |
3cee5a60 | 3266 | return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0; |
763f356c TI |
3267 | } |
3268 | ||
3cee5a60 | 3269 | static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds) |
763f356c | 3270 | { |
3cee5a60 RB |
3271 | if (ds) |
3272 | hdspm->control_register |= HDSPM_DS_DoubleWire; | |
763f356c | 3273 | else |
3cee5a60 | 3274 | hdspm->control_register &= ~HDSPM_DS_DoubleWire; |
763f356c TI |
3275 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); |
3276 | ||
3277 | return 0; | |
3278 | } | |
3279 | ||
3cee5a60 RB |
3280 | static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol, |
3281 | struct snd_ctl_elem_info *uinfo) | |
763f356c | 3282 | { |
3cee5a60 RB |
3283 | static char *texts[] = { "Single", "Double" }; |
3284 | ||
3285 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
763f356c | 3286 | uinfo->count = 1; |
3cee5a60 RB |
3287 | uinfo->value.enumerated.items = 2; |
3288 | ||
3289 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
3290 | uinfo->value.enumerated.item = | |
3291 | uinfo->value.enumerated.items - 1; | |
3292 | strcpy(uinfo->value.enumerated.name, | |
3293 | texts[uinfo->value.enumerated.item]); | |
3294 | ||
763f356c TI |
3295 | return 0; |
3296 | } | |
3297 | ||
3cee5a60 RB |
3298 | static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol, |
3299 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 3300 | { |
98274f07 | 3301 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
3302 | |
3303 | spin_lock_irq(&hdspm->lock); | |
3cee5a60 | 3304 | ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm); |
763f356c TI |
3305 | spin_unlock_irq(&hdspm->lock); |
3306 | return 0; | |
3307 | } | |
3308 | ||
3cee5a60 RB |
3309 | static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol, |
3310 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 3311 | { |
98274f07 | 3312 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
3313 | int change; |
3314 | unsigned int val; | |
3315 | ||
3316 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
3317 | return -EBUSY; | |
3318 | val = ucontrol->value.integer.value[0] & 1; | |
3319 | spin_lock_irq(&hdspm->lock); | |
3cee5a60 RB |
3320 | change = (int) val != hdspm_ds_wire(hdspm); |
3321 | hdspm_set_ds_wire(hdspm, val); | |
763f356c TI |
3322 | spin_unlock_irq(&hdspm->lock); |
3323 | return change; | |
3324 | } | |
3325 | ||
0dca1793 | 3326 | |
3cee5a60 | 3327 | #define HDSPM_QS_WIRE(xname, xindex) \ |
67ed4161 | 3328 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
763f356c TI |
3329 | .name = xname, \ |
3330 | .index = xindex, \ | |
3cee5a60 RB |
3331 | .info = snd_hdspm_info_qs_wire, \ |
3332 | .get = snd_hdspm_get_qs_wire, \ | |
3333 | .put = snd_hdspm_put_qs_wire \ | |
763f356c TI |
3334 | } |
3335 | ||
3cee5a60 | 3336 | static int hdspm_qs_wire(struct hdspm * hdspm) |
763f356c | 3337 | { |
3cee5a60 RB |
3338 | if (hdspm->control_register & HDSPM_QS_DoubleWire) |
3339 | return 1; | |
3340 | if (hdspm->control_register & HDSPM_QS_QuadWire) | |
3341 | return 2; | |
3342 | return 0; | |
763f356c TI |
3343 | } |
3344 | ||
3cee5a60 | 3345 | static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode) |
763f356c | 3346 | { |
3cee5a60 RB |
3347 | hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire); |
3348 | switch (mode) { | |
3349 | case 0: | |
3350 | break; | |
3351 | case 1: | |
3352 | hdspm->control_register |= HDSPM_QS_DoubleWire; | |
3353 | break; | |
3354 | case 2: | |
3355 | hdspm->control_register |= HDSPM_QS_QuadWire; | |
3356 | break; | |
3357 | } | |
763f356c TI |
3358 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); |
3359 | ||
3360 | return 0; | |
3361 | } | |
3362 | ||
3cee5a60 | 3363 | static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol, |
98274f07 | 3364 | struct snd_ctl_elem_info *uinfo) |
763f356c | 3365 | { |
3cee5a60 | 3366 | static char *texts[] = { "Single", "Double", "Quad" }; |
763f356c TI |
3367 | |
3368 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
3369 | uinfo->count = 1; | |
3cee5a60 | 3370 | uinfo->value.enumerated.items = 3; |
763f356c TI |
3371 | |
3372 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
3373 | uinfo->value.enumerated.item = | |
3374 | uinfo->value.enumerated.items - 1; | |
3375 | strcpy(uinfo->value.enumerated.name, | |
3376 | texts[uinfo->value.enumerated.item]); | |
3377 | ||
3378 | return 0; | |
3379 | } | |
3380 | ||
3cee5a60 | 3381 | static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol, |
98274f07 | 3382 | struct snd_ctl_elem_value *ucontrol) |
763f356c | 3383 | { |
98274f07 | 3384 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
3385 | |
3386 | spin_lock_irq(&hdspm->lock); | |
3cee5a60 | 3387 | ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm); |
763f356c TI |
3388 | spin_unlock_irq(&hdspm->lock); |
3389 | return 0; | |
3390 | } | |
3391 | ||
3cee5a60 | 3392 | static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol, |
98274f07 | 3393 | struct snd_ctl_elem_value *ucontrol) |
763f356c | 3394 | { |
98274f07 | 3395 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c | 3396 | int change; |
3cee5a60 | 3397 | int val; |
763f356c TI |
3398 | |
3399 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
3400 | return -EBUSY; | |
3cee5a60 RB |
3401 | val = ucontrol->value.integer.value[0]; |
3402 | if (val < 0) | |
3403 | val = 0; | |
3404 | if (val > 2) | |
3405 | val = 2; | |
763f356c | 3406 | spin_lock_irq(&hdspm->lock); |
ef5fa1a4 | 3407 | change = val != hdspm_qs_wire(hdspm); |
3cee5a60 | 3408 | hdspm_set_qs_wire(hdspm, val); |
763f356c TI |
3409 | spin_unlock_irq(&hdspm->lock); |
3410 | return change; | |
3411 | } | |
3412 | ||
763f356c TI |
3413 | |
3414 | #define HDSPM_MIXER(xname, xindex) \ | |
3415 | { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ | |
3416 | .name = xname, \ | |
3417 | .index = xindex, \ | |
67ed4161 | 3418 | .device = 0, \ |
763f356c TI |
3419 | .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ |
3420 | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
3421 | .info = snd_hdspm_info_mixer, \ | |
3422 | .get = snd_hdspm_get_mixer, \ | |
3423 | .put = snd_hdspm_put_mixer \ | |
3424 | } | |
3425 | ||
98274f07 TI |
3426 | static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol, |
3427 | struct snd_ctl_elem_info *uinfo) | |
763f356c TI |
3428 | { |
3429 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; | |
3430 | uinfo->count = 3; | |
3431 | uinfo->value.integer.min = 0; | |
3432 | uinfo->value.integer.max = 65535; | |
3433 | uinfo->value.integer.step = 1; | |
3434 | return 0; | |
3435 | } | |
3436 | ||
98274f07 TI |
3437 | static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol, |
3438 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 3439 | { |
98274f07 | 3440 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
3441 | int source; |
3442 | int destination; | |
3443 | ||
3444 | source = ucontrol->value.integer.value[0]; | |
3445 | if (source < 0) | |
3446 | source = 0; | |
3447 | else if (source >= 2 * HDSPM_MAX_CHANNELS) | |
3448 | source = 2 * HDSPM_MAX_CHANNELS - 1; | |
3449 | ||
3450 | destination = ucontrol->value.integer.value[1]; | |
3451 | if (destination < 0) | |
3452 | destination = 0; | |
3453 | else if (destination >= HDSPM_MAX_CHANNELS) | |
3454 | destination = HDSPM_MAX_CHANNELS - 1; | |
3455 | ||
3456 | spin_lock_irq(&hdspm->lock); | |
3457 | if (source >= HDSPM_MAX_CHANNELS) | |
3458 | ucontrol->value.integer.value[2] = | |
3459 | hdspm_read_pb_gain(hdspm, destination, | |
3460 | source - HDSPM_MAX_CHANNELS); | |
3461 | else | |
3462 | ucontrol->value.integer.value[2] = | |
3463 | hdspm_read_in_gain(hdspm, destination, source); | |
3464 | ||
3465 | spin_unlock_irq(&hdspm->lock); | |
3466 | ||
3467 | return 0; | |
3468 | } | |
3469 | ||
98274f07 TI |
3470 | static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol, |
3471 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 3472 | { |
98274f07 | 3473 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
3474 | int change; |
3475 | int source; | |
3476 | int destination; | |
3477 | int gain; | |
3478 | ||
3479 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
3480 | return -EBUSY; | |
3481 | ||
3482 | source = ucontrol->value.integer.value[0]; | |
3483 | destination = ucontrol->value.integer.value[1]; | |
3484 | ||
3485 | if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS) | |
3486 | return -1; | |
3487 | if (destination < 0 || destination >= HDSPM_MAX_CHANNELS) | |
3488 | return -1; | |
3489 | ||
3490 | gain = ucontrol->value.integer.value[2]; | |
3491 | ||
3492 | spin_lock_irq(&hdspm->lock); | |
3493 | ||
3494 | if (source >= HDSPM_MAX_CHANNELS) | |
3495 | change = gain != hdspm_read_pb_gain(hdspm, destination, | |
3496 | source - | |
3497 | HDSPM_MAX_CHANNELS); | |
3498 | else | |
ef5fa1a4 TI |
3499 | change = gain != hdspm_read_in_gain(hdspm, destination, |
3500 | source); | |
763f356c TI |
3501 | |
3502 | if (change) { | |
3503 | if (source >= HDSPM_MAX_CHANNELS) | |
3504 | hdspm_write_pb_gain(hdspm, destination, | |
3505 | source - HDSPM_MAX_CHANNELS, | |
3506 | gain); | |
3507 | else | |
3508 | hdspm_write_in_gain(hdspm, destination, source, | |
3509 | gain); | |
3510 | } | |
3511 | spin_unlock_irq(&hdspm->lock); | |
3512 | ||
3513 | return change; | |
3514 | } | |
3515 | ||
3516 | /* The simple mixer control(s) provide gain control for the | |
3517 | basic 1:1 mappings of playback streams to output | |
0dca1793 | 3518 | streams. |
763f356c TI |
3519 | */ |
3520 | ||
3521 | #define HDSPM_PLAYBACK_MIXER \ | |
3522 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ | |
3523 | .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \ | |
3524 | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
3525 | .info = snd_hdspm_info_playback_mixer, \ | |
3526 | .get = snd_hdspm_get_playback_mixer, \ | |
3527 | .put = snd_hdspm_put_playback_mixer \ | |
3528 | } | |
3529 | ||
98274f07 TI |
3530 | static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol, |
3531 | struct snd_ctl_elem_info *uinfo) | |
763f356c TI |
3532 | { |
3533 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; | |
3534 | uinfo->count = 1; | |
3535 | uinfo->value.integer.min = 0; | |
0dca1793 | 3536 | uinfo->value.integer.max = 64; |
763f356c TI |
3537 | uinfo->value.integer.step = 1; |
3538 | return 0; | |
3539 | } | |
3540 | ||
98274f07 TI |
3541 | static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol, |
3542 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 3543 | { |
98274f07 | 3544 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c | 3545 | int channel; |
763f356c TI |
3546 | |
3547 | channel = ucontrol->id.index - 1; | |
3548 | ||
da3cec35 TI |
3549 | if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS)) |
3550 | return -EINVAL; | |
763f356c | 3551 | |
763f356c TI |
3552 | spin_lock_irq(&hdspm->lock); |
3553 | ucontrol->value.integer.value[0] = | |
0dca1793 | 3554 | (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN; |
763f356c TI |
3555 | spin_unlock_irq(&hdspm->lock); |
3556 | ||
763f356c TI |
3557 | return 0; |
3558 | } | |
3559 | ||
98274f07 TI |
3560 | static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol, |
3561 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 3562 | { |
98274f07 | 3563 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
3564 | int change; |
3565 | int channel; | |
763f356c TI |
3566 | int gain; |
3567 | ||
3568 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
3569 | return -EBUSY; | |
3570 | ||
3571 | channel = ucontrol->id.index - 1; | |
3572 | ||
da3cec35 TI |
3573 | if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS)) |
3574 | return -EINVAL; | |
763f356c | 3575 | |
0dca1793 | 3576 | gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64; |
763f356c TI |
3577 | |
3578 | spin_lock_irq(&hdspm->lock); | |
3579 | change = | |
0dca1793 AK |
3580 | gain != hdspm_read_pb_gain(hdspm, channel, |
3581 | channel); | |
763f356c | 3582 | if (change) |
0dca1793 | 3583 | hdspm_write_pb_gain(hdspm, channel, channel, |
763f356c TI |
3584 | gain); |
3585 | spin_unlock_irq(&hdspm->lock); | |
3586 | return change; | |
3587 | } | |
3588 | ||
0dca1793 AK |
3589 | #define HDSPM_SYNC_CHECK(xname, xindex) \ |
3590 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ | |
3591 | .name = xname, \ | |
3592 | .private_value = xindex, \ | |
3593 | .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
3594 | .info = snd_hdspm_info_sync_check, \ | |
3595 | .get = snd_hdspm_get_sync_check \ | |
763f356c TI |
3596 | } |
3597 | ||
0dca1793 | 3598 | |
98274f07 TI |
3599 | static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol, |
3600 | struct snd_ctl_elem_info *uinfo) | |
763f356c | 3601 | { |
0dca1793 | 3602 | static char *texts[] = { "No Lock", "Lock", "Sync", "N/A" }; |
763f356c TI |
3603 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; |
3604 | uinfo->count = 1; | |
0dca1793 | 3605 | uinfo->value.enumerated.items = 4; |
763f356c TI |
3606 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) |
3607 | uinfo->value.enumerated.item = | |
0dca1793 | 3608 | uinfo->value.enumerated.items - 1; |
763f356c | 3609 | strcpy(uinfo->value.enumerated.name, |
0dca1793 | 3610 | texts[uinfo->value.enumerated.item]); |
763f356c TI |
3611 | return 0; |
3612 | } | |
3613 | ||
0dca1793 | 3614 | static int hdspm_wc_sync_check(struct hdspm *hdspm) |
763f356c | 3615 | { |
0dca1793 AK |
3616 | int status, status2; |
3617 | ||
3618 | switch (hdspm->io_type) { | |
3619 | case AES32: | |
3620 | status = hdspm_read(hdspm, HDSPM_statusRegister); | |
3621 | if (status & HDSPM_wcSync) | |
763f356c | 3622 | return 2; |
0dca1793 AK |
3623 | else if (status & HDSPM_wcLock) |
3624 | return 1; | |
3cee5a60 | 3625 | return 0; |
0dca1793 AK |
3626 | break; |
3627 | ||
3628 | case MADI: | |
3629 | status2 = hdspm_read(hdspm, HDSPM_statusRegister2); | |
3cee5a60 RB |
3630 | if (status2 & HDSPM_wcLock) { |
3631 | if (status2 & HDSPM_wcSync) | |
3632 | return 2; | |
3633 | else | |
3634 | return 1; | |
3635 | } | |
3636 | return 0; | |
0dca1793 | 3637 | break; |
763f356c | 3638 | |
0dca1793 AK |
3639 | case RayDAT: |
3640 | case AIO: | |
3641 | status = hdspm_read(hdspm, HDSPM_statusRegister); | |
763f356c | 3642 | |
0dca1793 AK |
3643 | if (status & 0x2000000) |
3644 | return 2; | |
3645 | else if (status & 0x1000000) | |
3646 | return 1; | |
3647 | return 0; | |
763f356c | 3648 | |
0dca1793 | 3649 | break; |
763f356c | 3650 | |
0dca1793 AK |
3651 | case MADIface: |
3652 | break; | |
3653 | } | |
3654 | ||
3655 | ||
3656 | return 3; | |
763f356c TI |
3657 | } |
3658 | ||
0dca1793 AK |
3659 | |
3660 | static int hdspm_madi_sync_check(struct hdspm *hdspm) | |
763f356c TI |
3661 | { |
3662 | int status = hdspm_read(hdspm, HDSPM_statusRegister); | |
3663 | if (status & HDSPM_madiLock) { | |
3664 | if (status & HDSPM_madiSync) | |
3665 | return 2; | |
3666 | else | |
3667 | return 1; | |
3668 | } | |
3669 | return 0; | |
3670 | } | |
3671 | ||
763f356c | 3672 | |
0dca1793 AK |
3673 | static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx) |
3674 | { | |
3675 | int status, lock, sync; | |
763f356c | 3676 | |
0dca1793 | 3677 | status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); |
763f356c | 3678 | |
0dca1793 AK |
3679 | lock = (status & (0x1<<idx)) ? 1 : 0; |
3680 | sync = (status & (0x100<<idx)) ? 1 : 0; | |
3cee5a60 | 3681 | |
0dca1793 | 3682 | if (lock && sync) |
3cee5a60 | 3683 | return 2; |
0dca1793 AK |
3684 | else if (lock) |
3685 | return 1; | |
3cee5a60 RB |
3686 | return 0; |
3687 | } | |
3688 | ||
0dca1793 AK |
3689 | |
3690 | static int hdspm_sync_in_sync_check(struct hdspm *hdspm) | |
3691 | { | |
3692 | int status, lock = 0, sync = 0; | |
3693 | ||
3694 | switch (hdspm->io_type) { | |
3695 | case RayDAT: | |
3696 | case AIO: | |
3697 | status = hdspm_read(hdspm, HDSPM_RD_STATUS_3); | |
3698 | lock = (status & 0x400) ? 1 : 0; | |
3699 | sync = (status & 0x800) ? 1 : 0; | |
3700 | break; | |
3701 | ||
3702 | case MADI: | |
3703 | case AES32: | |
3704 | status = hdspm_read(hdspm, HDSPM_statusRegister2); | |
a7edbd5b AK |
3705 | lock = (status & HDSPM_syncInLock) ? 1 : 0; |
3706 | sync = (status & HDSPM_syncInSync) ? 1 : 0; | |
0dca1793 AK |
3707 | break; |
3708 | ||
3709 | case MADIface: | |
3710 | break; | |
3711 | } | |
3712 | ||
3713 | if (lock && sync) | |
3714 | return 2; | |
3715 | else if (lock) | |
3716 | return 1; | |
3717 | ||
3718 | return 0; | |
3719 | } | |
3720 | ||
3721 | static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx) | |
3722 | { | |
3723 | int status2, lock, sync; | |
3724 | status2 = hdspm_read(hdspm, HDSPM_statusRegister2); | |
3725 | ||
3726 | lock = (status2 & (0x0080 >> idx)) ? 1 : 0; | |
3727 | sync = (status2 & (0x8000 >> idx)) ? 1 : 0; | |
3728 | ||
3729 | if (sync) | |
3730 | return 2; | |
3731 | else if (lock) | |
3732 | return 1; | |
3733 | return 0; | |
3734 | } | |
3735 | ||
3736 | ||
3737 | static int hdspm_tco_sync_check(struct hdspm *hdspm) | |
3738 | { | |
3739 | int status; | |
3740 | ||
3741 | if (hdspm->tco) { | |
3742 | switch (hdspm->io_type) { | |
3743 | case MADI: | |
3744 | case AES32: | |
3745 | status = hdspm_read(hdspm, HDSPM_statusRegister); | |
3746 | if (status & HDSPM_tcoLock) { | |
3747 | if (status & HDSPM_tcoSync) | |
3748 | return 2; | |
3749 | else | |
3750 | return 1; | |
3751 | } | |
3752 | return 0; | |
3753 | ||
3754 | break; | |
3755 | ||
3756 | case RayDAT: | |
3757 | case AIO: | |
3758 | status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); | |
3759 | ||
3760 | if (status & 0x8000000) | |
3761 | return 2; /* Sync */ | |
3762 | if (status & 0x4000000) | |
3763 | return 1; /* Lock */ | |
3764 | return 0; /* No signal */ | |
3765 | break; | |
3766 | ||
3767 | default: | |
3768 | break; | |
3769 | } | |
3770 | } | |
3771 | ||
3772 | return 3; /* N/A */ | |
3773 | } | |
3774 | ||
3775 | ||
3776 | static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol, | |
3777 | struct snd_ctl_elem_value *ucontrol) | |
3778 | { | |
3779 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
3780 | int val = -1; | |
3781 | ||
3782 | switch (hdspm->io_type) { | |
3783 | case RayDAT: | |
3784 | switch (kcontrol->private_value) { | |
3785 | case 0: /* WC */ | |
3786 | val = hdspm_wc_sync_check(hdspm); break; | |
3787 | case 7: /* TCO */ | |
3788 | val = hdspm_tco_sync_check(hdspm); break; | |
3789 | case 8: /* SYNC IN */ | |
3790 | val = hdspm_sync_in_sync_check(hdspm); break; | |
3791 | default: | |
3792 | val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1); | |
3793 | } | |
3794 | ||
3795 | case AIO: | |
3796 | switch (kcontrol->private_value) { | |
3797 | case 0: /* WC */ | |
3798 | val = hdspm_wc_sync_check(hdspm); break; | |
3799 | case 4: /* TCO */ | |
3800 | val = hdspm_tco_sync_check(hdspm); break; | |
3801 | case 5: /* SYNC IN */ | |
3802 | val = hdspm_sync_in_sync_check(hdspm); break; | |
3803 | default: | |
3804 | val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1); | |
3805 | } | |
3806 | ||
3807 | case MADI: | |
3808 | switch (kcontrol->private_value) { | |
3809 | case 0: /* WC */ | |
3810 | val = hdspm_wc_sync_check(hdspm); break; | |
3811 | case 1: /* MADI */ | |
3812 | val = hdspm_madi_sync_check(hdspm); break; | |
3813 | case 2: /* TCO */ | |
3814 | val = hdspm_tco_sync_check(hdspm); break; | |
3815 | case 3: /* SYNC_IN */ | |
3816 | val = hdspm_sync_in_sync_check(hdspm); break; | |
3817 | } | |
3818 | ||
3819 | case MADIface: | |
3820 | val = hdspm_madi_sync_check(hdspm); /* MADI */ | |
3821 | break; | |
3822 | ||
3823 | case AES32: | |
3824 | switch (kcontrol->private_value) { | |
3825 | case 0: /* WC */ | |
3826 | val = hdspm_wc_sync_check(hdspm); break; | |
3827 | case 9: /* TCO */ | |
3828 | val = hdspm_tco_sync_check(hdspm); break; | |
3829 | case 10 /* SYNC IN */: | |
3830 | val = hdspm_sync_in_sync_check(hdspm); break; | |
7c4a95b5 | 3831 | default: /* AES1 to AES8 */ |
0dca1793 | 3832 | val = hdspm_aes_sync_check(hdspm, |
7c4a95b5 | 3833 | kcontrol->private_value-1); |
0dca1793 AK |
3834 | } |
3835 | ||
3836 | } | |
3837 | ||
3838 | if (-1 == val) | |
3839 | val = 3; | |
3840 | ||
3841 | ucontrol->value.enumerated.item[0] = val; | |
3842 | return 0; | |
3843 | } | |
3844 | ||
3845 | ||
3846 | ||
3847 | /** | |
3848 | * TCO controls | |
3849 | **/ | |
3850 | static void hdspm_tco_write(struct hdspm *hdspm) | |
3851 | { | |
3852 | unsigned int tc[4] = { 0, 0, 0, 0}; | |
3853 | ||
3854 | switch (hdspm->tco->input) { | |
3855 | case 0: | |
3856 | tc[2] |= HDSPM_TCO2_set_input_MSB; | |
3857 | break; | |
3858 | case 1: | |
3859 | tc[2] |= HDSPM_TCO2_set_input_LSB; | |
3860 | break; | |
3861 | default: | |
3862 | break; | |
3863 | } | |
3864 | ||
3865 | switch (hdspm->tco->framerate) { | |
3866 | case 1: | |
3867 | tc[1] |= HDSPM_TCO1_LTC_Format_LSB; | |
3868 | break; | |
3869 | case 2: | |
3870 | tc[1] |= HDSPM_TCO1_LTC_Format_MSB; | |
3871 | break; | |
3872 | case 3: | |
3873 | tc[1] |= HDSPM_TCO1_LTC_Format_MSB + | |
3874 | HDSPM_TCO1_set_drop_frame_flag; | |
3875 | break; | |
3876 | case 4: | |
3877 | tc[1] |= HDSPM_TCO1_LTC_Format_LSB + | |
3878 | HDSPM_TCO1_LTC_Format_MSB; | |
3879 | break; | |
3880 | case 5: | |
3881 | tc[1] |= HDSPM_TCO1_LTC_Format_LSB + | |
3882 | HDSPM_TCO1_LTC_Format_MSB + | |
3883 | HDSPM_TCO1_set_drop_frame_flag; | |
3884 | break; | |
3885 | default: | |
3886 | break; | |
3887 | } | |
3888 | ||
3889 | switch (hdspm->tco->wordclock) { | |
3890 | case 1: | |
3891 | tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB; | |
3892 | break; | |
3893 | case 2: | |
3894 | tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB; | |
3895 | break; | |
3896 | default: | |
3897 | break; | |
3898 | } | |
3899 | ||
3900 | switch (hdspm->tco->samplerate) { | |
3901 | case 1: | |
3902 | tc[2] |= HDSPM_TCO2_set_freq; | |
3903 | break; | |
3904 | case 2: | |
3905 | tc[2] |= HDSPM_TCO2_set_freq_from_app; | |
3906 | break; | |
3907 | default: | |
3908 | break; | |
3909 | } | |
3910 | ||
3911 | switch (hdspm->tco->pull) { | |
3912 | case 1: | |
3913 | tc[2] |= HDSPM_TCO2_set_pull_up; | |
3914 | break; | |
3915 | case 2: | |
3916 | tc[2] |= HDSPM_TCO2_set_pull_down; | |
3917 | break; | |
3918 | case 3: | |
3919 | tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4; | |
3920 | break; | |
3921 | case 4: | |
3922 | tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4; | |
3923 | break; | |
3924 | default: | |
3925 | break; | |
3926 | } | |
3927 | ||
3928 | if (1 == hdspm->tco->term) { | |
3929 | tc[2] |= HDSPM_TCO2_set_term_75R; | |
3930 | } | |
3931 | ||
3932 | hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]); | |
3933 | hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]); | |
3934 | hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]); | |
3935 | hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]); | |
3936 | } | |
3937 | ||
3938 | ||
3939 | #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \ | |
3940 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ | |
3941 | .name = xname, \ | |
3942 | .index = xindex, \ | |
3943 | .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ | |
3944 | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
3945 | .info = snd_hdspm_info_tco_sample_rate, \ | |
3946 | .get = snd_hdspm_get_tco_sample_rate, \ | |
3947 | .put = snd_hdspm_put_tco_sample_rate \ | |
3948 | } | |
3949 | ||
3950 | static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol, | |
3951 | struct snd_ctl_elem_info *uinfo) | |
3952 | { | |
3953 | static char *texts[] = { "44.1 kHz", "48 kHz" }; | |
3954 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
3955 | uinfo->count = 1; | |
3956 | uinfo->value.enumerated.items = 2; | |
3957 | ||
3958 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
3959 | uinfo->value.enumerated.item = | |
3960 | uinfo->value.enumerated.items - 1; | |
3961 | ||
3962 | strcpy(uinfo->value.enumerated.name, | |
3963 | texts[uinfo->value.enumerated.item]); | |
3964 | ||
3965 | return 0; | |
3966 | } | |
3967 | ||
3968 | static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol, | |
3969 | struct snd_ctl_elem_value *ucontrol) | |
3970 | { | |
3971 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
3972 | ||
3973 | ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate; | |
3974 | ||
3975 | return 0; | |
3976 | } | |
3977 | ||
3978 | static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol, | |
3979 | struct snd_ctl_elem_value *ucontrol) | |
3980 | { | |
3981 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
3982 | ||
3983 | if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) { | |
3984 | hdspm->tco->samplerate = ucontrol->value.enumerated.item[0]; | |
3985 | ||
3986 | hdspm_tco_write(hdspm); | |
3987 | ||
3988 | return 1; | |
3989 | } | |
3990 | ||
3991 | return 0; | |
3992 | } | |
3993 | ||
3994 | ||
3995 | #define HDSPM_TCO_PULL(xname, xindex) \ | |
3996 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ | |
3997 | .name = xname, \ | |
3998 | .index = xindex, \ | |
3999 | .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ | |
4000 | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
4001 | .info = snd_hdspm_info_tco_pull, \ | |
4002 | .get = snd_hdspm_get_tco_pull, \ | |
4003 | .put = snd_hdspm_put_tco_pull \ | |
4004 | } | |
4005 | ||
4006 | static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol, | |
4007 | struct snd_ctl_elem_info *uinfo) | |
4008 | { | |
4009 | static char *texts[] = { "0", "+ 0.1 %", "- 0.1 %", "+ 4 %", "- 4 %" }; | |
4010 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
4011 | uinfo->count = 1; | |
4012 | uinfo->value.enumerated.items = 5; | |
4013 | ||
4014 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
4015 | uinfo->value.enumerated.item = | |
4016 | uinfo->value.enumerated.items - 1; | |
4017 | ||
4018 | strcpy(uinfo->value.enumerated.name, | |
4019 | texts[uinfo->value.enumerated.item]); | |
4020 | ||
4021 | return 0; | |
4022 | } | |
4023 | ||
4024 | static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol, | |
4025 | struct snd_ctl_elem_value *ucontrol) | |
4026 | { | |
4027 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
4028 | ||
4029 | ucontrol->value.enumerated.item[0] = hdspm->tco->pull; | |
4030 | ||
4031 | return 0; | |
4032 | } | |
4033 | ||
4034 | static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol, | |
4035 | struct snd_ctl_elem_value *ucontrol) | |
4036 | { | |
4037 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
4038 | ||
4039 | if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) { | |
4040 | hdspm->tco->pull = ucontrol->value.enumerated.item[0]; | |
4041 | ||
4042 | hdspm_tco_write(hdspm); | |
4043 | ||
4044 | return 1; | |
4045 | } | |
4046 | ||
4047 | return 0; | |
4048 | } | |
4049 | ||
4050 | #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \ | |
4051 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ | |
4052 | .name = xname, \ | |
4053 | .index = xindex, \ | |
4054 | .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ | |
4055 | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
4056 | .info = snd_hdspm_info_tco_wck_conversion, \ | |
4057 | .get = snd_hdspm_get_tco_wck_conversion, \ | |
4058 | .put = snd_hdspm_put_tco_wck_conversion \ | |
4059 | } | |
4060 | ||
4061 | static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol, | |
4062 | struct snd_ctl_elem_info *uinfo) | |
4063 | { | |
4064 | static char *texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" }; | |
4065 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
4066 | uinfo->count = 1; | |
4067 | uinfo->value.enumerated.items = 3; | |
4068 | ||
4069 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
4070 | uinfo->value.enumerated.item = | |
4071 | uinfo->value.enumerated.items - 1; | |
4072 | ||
4073 | strcpy(uinfo->value.enumerated.name, | |
4074 | texts[uinfo->value.enumerated.item]); | |
4075 | ||
4076 | return 0; | |
4077 | } | |
4078 | ||
4079 | static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol, | |
4080 | struct snd_ctl_elem_value *ucontrol) | |
4081 | { | |
4082 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
4083 | ||
4084 | ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock; | |
4085 | ||
4086 | return 0; | |
4087 | } | |
4088 | ||
4089 | static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol, | |
4090 | struct snd_ctl_elem_value *ucontrol) | |
4091 | { | |
4092 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
4093 | ||
4094 | if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) { | |
4095 | hdspm->tco->wordclock = ucontrol->value.enumerated.item[0]; | |
4096 | ||
4097 | hdspm_tco_write(hdspm); | |
4098 | ||
4099 | return 1; | |
4100 | } | |
4101 | ||
4102 | return 0; | |
4103 | } | |
4104 | ||
4105 | ||
4106 | #define HDSPM_TCO_FRAME_RATE(xname, xindex) \ | |
4107 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ | |
4108 | .name = xname, \ | |
4109 | .index = xindex, \ | |
4110 | .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ | |
4111 | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
4112 | .info = snd_hdspm_info_tco_frame_rate, \ | |
4113 | .get = snd_hdspm_get_tco_frame_rate, \ | |
4114 | .put = snd_hdspm_put_tco_frame_rate \ | |
4115 | } | |
4116 | ||
4117 | static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol, | |
4118 | struct snd_ctl_elem_info *uinfo) | |
4119 | { | |
4120 | static char *texts[] = { "24 fps", "25 fps", "29.97fps", | |
4121 | "29.97 dfps", "30 fps", "30 dfps" }; | |
4122 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
4123 | uinfo->count = 1; | |
4124 | uinfo->value.enumerated.items = 6; | |
4125 | ||
4126 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
4127 | uinfo->value.enumerated.item = | |
4128 | uinfo->value.enumerated.items - 1; | |
4129 | ||
4130 | strcpy(uinfo->value.enumerated.name, | |
4131 | texts[uinfo->value.enumerated.item]); | |
4132 | ||
4133 | return 0; | |
4134 | } | |
4135 | ||
4136 | static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol, | |
3cee5a60 RB |
4137 | struct snd_ctl_elem_value *ucontrol) |
4138 | { | |
3cee5a60 RB |
4139 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
4140 | ||
0dca1793 | 4141 | ucontrol->value.enumerated.item[0] = hdspm->tco->framerate; |
3cee5a60 | 4142 | |
3cee5a60 RB |
4143 | return 0; |
4144 | } | |
763f356c | 4145 | |
0dca1793 AK |
4146 | static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol, |
4147 | struct snd_ctl_elem_value *ucontrol) | |
4148 | { | |
4149 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
763f356c | 4150 | |
0dca1793 AK |
4151 | if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) { |
4152 | hdspm->tco->framerate = ucontrol->value.enumerated.item[0]; | |
763f356c | 4153 | |
0dca1793 AK |
4154 | hdspm_tco_write(hdspm); |
4155 | ||
4156 | return 1; | |
4157 | } | |
4158 | ||
4159 | return 0; | |
4160 | } | |
763f356c | 4161 | |
0dca1793 AK |
4162 | |
4163 | #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \ | |
4164 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ | |
4165 | .name = xname, \ | |
4166 | .index = xindex, \ | |
4167 | .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ | |
4168 | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
4169 | .info = snd_hdspm_info_tco_sync_source, \ | |
4170 | .get = snd_hdspm_get_tco_sync_source, \ | |
4171 | .put = snd_hdspm_put_tco_sync_source \ | |
4172 | } | |
4173 | ||
4174 | static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol, | |
4175 | struct snd_ctl_elem_info *uinfo) | |
4176 | { | |
4177 | static char *texts[] = { "LTC", "Video", "WCK" }; | |
4178 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
4179 | uinfo->count = 1; | |
4180 | uinfo->value.enumerated.items = 3; | |
4181 | ||
4182 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
4183 | uinfo->value.enumerated.item = | |
4184 | uinfo->value.enumerated.items - 1; | |
4185 | ||
4186 | strcpy(uinfo->value.enumerated.name, | |
4187 | texts[uinfo->value.enumerated.item]); | |
4188 | ||
4189 | return 0; | |
4190 | } | |
4191 | ||
4192 | static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol, | |
4193 | struct snd_ctl_elem_value *ucontrol) | |
4194 | { | |
4195 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
4196 | ||
4197 | ucontrol->value.enumerated.item[0] = hdspm->tco->input; | |
4198 | ||
4199 | return 0; | |
4200 | } | |
4201 | ||
4202 | static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol, | |
4203 | struct snd_ctl_elem_value *ucontrol) | |
4204 | { | |
4205 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
4206 | ||
4207 | if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) { | |
4208 | hdspm->tco->input = ucontrol->value.enumerated.item[0]; | |
4209 | ||
4210 | hdspm_tco_write(hdspm); | |
4211 | ||
4212 | return 1; | |
4213 | } | |
4214 | ||
4215 | return 0; | |
4216 | } | |
4217 | ||
4218 | ||
4219 | #define HDSPM_TCO_WORD_TERM(xname, xindex) \ | |
4220 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ | |
4221 | .name = xname, \ | |
4222 | .index = xindex, \ | |
4223 | .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ | |
4224 | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
4225 | .info = snd_hdspm_info_tco_word_term, \ | |
4226 | .get = snd_hdspm_get_tco_word_term, \ | |
4227 | .put = snd_hdspm_put_tco_word_term \ | |
4228 | } | |
4229 | ||
4230 | static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol, | |
4231 | struct snd_ctl_elem_info *uinfo) | |
4232 | { | |
4233 | uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; | |
4234 | uinfo->count = 1; | |
4235 | uinfo->value.integer.min = 0; | |
4236 | uinfo->value.integer.max = 1; | |
4237 | ||
4238 | return 0; | |
4239 | } | |
4240 | ||
4241 | ||
4242 | static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol, | |
4243 | struct snd_ctl_elem_value *ucontrol) | |
4244 | { | |
4245 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
4246 | ||
4247 | ucontrol->value.enumerated.item[0] = hdspm->tco->term; | |
4248 | ||
4249 | return 0; | |
4250 | } | |
4251 | ||
4252 | ||
4253 | static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol, | |
4254 | struct snd_ctl_elem_value *ucontrol) | |
4255 | { | |
4256 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
4257 | ||
4258 | if (hdspm->tco->term != ucontrol->value.enumerated.item[0]) { | |
4259 | hdspm->tco->term = ucontrol->value.enumerated.item[0]; | |
4260 | ||
4261 | hdspm_tco_write(hdspm); | |
4262 | ||
4263 | return 1; | |
4264 | } | |
4265 | ||
4266 | return 0; | |
4267 | } | |
4268 | ||
4269 | ||
4270 | ||
4271 | ||
4272 | static struct snd_kcontrol_new snd_hdspm_controls_madi[] = { | |
4273 | HDSPM_MIXER("Mixer", 0), | |
4274 | HDSPM_INTERNAL_CLOCK("Internal Clock", 0), | |
763f356c TI |
4275 | HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), |
4276 | HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), | |
4277 | HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), | |
4278 | HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), | |
0dca1793 AK |
4279 | HDSPM_SYNC_CHECK("WC SyncCheck", 0), |
4280 | HDSPM_SYNC_CHECK("MADI SyncCheck", 1), | |
4281 | HDSPM_SYNC_CHECK("TCO SyncCHeck", 2), | |
4282 | HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3), | |
763f356c TI |
4283 | HDSPM_LINE_OUT("Line Out", 0), |
4284 | HDSPM_TX_64("TX 64 channels mode", 0), | |
4285 | HDSPM_C_TMS("Clear Track Marker", 0), | |
4286 | HDSPM_SAFE_MODE("Safe Mode", 0), | |
0dca1793 AK |
4287 | HDSPM_INPUT_SELECT("Input Select", 0) |
4288 | }; | |
4289 | ||
4290 | ||
4291 | static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = { | |
4292 | HDSPM_MIXER("Mixer", 0), | |
4293 | HDSPM_INTERNAL_CLOCK("Internal Clock", 0), | |
4294 | HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), | |
4295 | HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), | |
4296 | HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), | |
4297 | HDSPM_SYNC_CHECK("MADI SyncCheck", 0), | |
4298 | HDSPM_TX_64("TX 64 channels mode", 0), | |
4299 | HDSPM_C_TMS("Clear Track Marker", 0), | |
f6ea805f | 4300 | HDSPM_SAFE_MODE("Safe Mode", 0) |
763f356c TI |
4301 | }; |
4302 | ||
0dca1793 AK |
4303 | static struct snd_kcontrol_new snd_hdspm_controls_aio[] = { |
4304 | HDSPM_MIXER("Mixer", 0), | |
4305 | HDSPM_INTERNAL_CLOCK("Internal Clock", 0), | |
4306 | HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), | |
4307 | HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), | |
4308 | HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), | |
4309 | HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), | |
4310 | HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), | |
4311 | HDSPM_SYNC_CHECK("WC SyncCheck", 0), | |
4312 | HDSPM_SYNC_CHECK("AES SyncCheck", 1), | |
4313 | HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2), | |
4314 | HDSPM_SYNC_CHECK("ADAT SyncCheck", 3), | |
4315 | HDSPM_SYNC_CHECK("TCO SyncCheck", 4), | |
4316 | HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5), | |
4317 | HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), | |
4318 | HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1), | |
4319 | HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2), | |
4320 | HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3), | |
4321 | HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4), | |
4322 | HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5) | |
4323 | ||
4324 | /* | |
4325 | HDSPM_INPUT_SELECT("Input Select", 0), | |
4326 | HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0), | |
4327 | HDSPM_PROFESSIONAL("SPDIF Out Professional", 0); | |
4328 | HDSPM_SPDIF_IN("SPDIF In", 0); | |
4329 | HDSPM_BREAKOUT_CABLE("Breakout Cable", 0); | |
4330 | HDSPM_INPUT_LEVEL("Input Level", 0); | |
4331 | HDSPM_OUTPUT_LEVEL("Output Level", 0); | |
4332 | HDSPM_PHONES("Phones", 0); | |
4333 | */ | |
4334 | }; | |
3cee5a60 | 4335 | |
0dca1793 AK |
4336 | static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = { |
4337 | HDSPM_MIXER("Mixer", 0), | |
4338 | HDSPM_INTERNAL_CLOCK("Internal Clock", 0), | |
4339 | HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0), | |
4340 | HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0), | |
4341 | HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), | |
4342 | HDSPM_SYNC_CHECK("WC SyncCheck", 0), | |
4343 | HDSPM_SYNC_CHECK("AES SyncCheck", 1), | |
4344 | HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2), | |
4345 | HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3), | |
4346 | HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4), | |
4347 | HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5), | |
4348 | HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6), | |
4349 | HDSPM_SYNC_CHECK("TCO SyncCheck", 7), | |
4350 | HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8), | |
4351 | HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), | |
4352 | HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1), | |
4353 | HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2), | |
4354 | HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3), | |
4355 | HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4), | |
4356 | HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5), | |
4357 | HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6), | |
4358 | HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7), | |
4359 | HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8) | |
4360 | }; | |
4361 | ||
4362 | static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = { | |
3cee5a60 | 4363 | HDSPM_MIXER("Mixer", 0), |
0dca1793 | 4364 | HDSPM_INTERNAL_CLOCK("Internal Clock", 0), |
3cee5a60 RB |
4365 | HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), |
4366 | HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), | |
4367 | HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), | |
4368 | HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), | |
3cee5a60 | 4369 | HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), |
0dca1793 AK |
4370 | HDSPM_SYNC_CHECK("WC Sync Check", 0), |
4371 | HDSPM_SYNC_CHECK("AES1 Sync Check", 1), | |
4372 | HDSPM_SYNC_CHECK("AES2 Sync Check", 2), | |
4373 | HDSPM_SYNC_CHECK("AES3 Sync Check", 3), | |
4374 | HDSPM_SYNC_CHECK("AES4 Sync Check", 4), | |
4375 | HDSPM_SYNC_CHECK("AES5 Sync Check", 5), | |
4376 | HDSPM_SYNC_CHECK("AES6 Sync Check", 6), | |
4377 | HDSPM_SYNC_CHECK("AES7 Sync Check", 7), | |
4378 | HDSPM_SYNC_CHECK("AES8 Sync Check", 8), | |
4379 | HDSPM_SYNC_CHECK("TCO Sync Check", 9), | |
4380 | HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10), | |
4381 | HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), | |
4382 | HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1), | |
4383 | HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2), | |
4384 | HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3), | |
4385 | HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4), | |
4386 | HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5), | |
4387 | HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6), | |
4388 | HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7), | |
4389 | HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8), | |
4390 | HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9), | |
4391 | HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10), | |
3cee5a60 RB |
4392 | HDSPM_LINE_OUT("Line Out", 0), |
4393 | HDSPM_EMPHASIS("Emphasis", 0), | |
4394 | HDSPM_DOLBY("Non Audio", 0), | |
4395 | HDSPM_PROFESSIONAL("Professional", 0), | |
4396 | HDSPM_C_TMS("Clear Track Marker", 0), | |
4397 | HDSPM_DS_WIRE("Double Speed Wire Mode", 0), | |
4398 | HDSPM_QS_WIRE("Quad Speed Wire Mode", 0), | |
4399 | }; | |
4400 | ||
0dca1793 AK |
4401 | |
4402 | ||
4403 | /* Control elements for the optional TCO module */ | |
4404 | static struct snd_kcontrol_new snd_hdspm_controls_tco[] = { | |
4405 | HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0), | |
4406 | HDSPM_TCO_PULL("TCO Pull", 0), | |
4407 | HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0), | |
4408 | HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0), | |
4409 | HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0), | |
4410 | HDSPM_TCO_WORD_TERM("TCO Word Term", 0) | |
4411 | }; | |
4412 | ||
4413 | ||
98274f07 | 4414 | static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER; |
763f356c TI |
4415 | |
4416 | ||
98274f07 | 4417 | static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm) |
763f356c TI |
4418 | { |
4419 | int i; | |
4420 | ||
0dca1793 | 4421 | for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) { |
763f356c TI |
4422 | if (hdspm->system_sample_rate > 48000) { |
4423 | hdspm->playback_mixer_ctls[i]->vd[0].access = | |
0dca1793 AK |
4424 | SNDRV_CTL_ELEM_ACCESS_INACTIVE | |
4425 | SNDRV_CTL_ELEM_ACCESS_READ | | |
4426 | SNDRV_CTL_ELEM_ACCESS_VOLATILE; | |
763f356c TI |
4427 | } else { |
4428 | hdspm->playback_mixer_ctls[i]->vd[0].access = | |
0dca1793 AK |
4429 | SNDRV_CTL_ELEM_ACCESS_READWRITE | |
4430 | SNDRV_CTL_ELEM_ACCESS_VOLATILE; | |
763f356c TI |
4431 | } |
4432 | snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE | | |
0dca1793 AK |
4433 | SNDRV_CTL_EVENT_MASK_INFO, |
4434 | &hdspm->playback_mixer_ctls[i]->id); | |
763f356c TI |
4435 | } |
4436 | ||
4437 | return 0; | |
4438 | } | |
4439 | ||
4440 | ||
0dca1793 AK |
4441 | static int snd_hdspm_create_controls(struct snd_card *card, |
4442 | struct hdspm *hdspm) | |
763f356c TI |
4443 | { |
4444 | unsigned int idx, limit; | |
4445 | int err; | |
98274f07 | 4446 | struct snd_kcontrol *kctl; |
0dca1793 | 4447 | struct snd_kcontrol_new *list = NULL; |
763f356c | 4448 | |
0dca1793 AK |
4449 | switch (hdspm->io_type) { |
4450 | case MADI: | |
4451 | list = snd_hdspm_controls_madi; | |
4452 | limit = ARRAY_SIZE(snd_hdspm_controls_madi); | |
4453 | break; | |
4454 | case MADIface: | |
4455 | list = snd_hdspm_controls_madiface; | |
4456 | limit = ARRAY_SIZE(snd_hdspm_controls_madiface); | |
4457 | break; | |
4458 | case AIO: | |
4459 | list = snd_hdspm_controls_aio; | |
4460 | limit = ARRAY_SIZE(snd_hdspm_controls_aio); | |
4461 | break; | |
4462 | case RayDAT: | |
4463 | list = snd_hdspm_controls_raydat; | |
4464 | limit = ARRAY_SIZE(snd_hdspm_controls_raydat); | |
4465 | break; | |
4466 | case AES32: | |
4467 | list = snd_hdspm_controls_aes32; | |
4468 | limit = ARRAY_SIZE(snd_hdspm_controls_aes32); | |
4469 | break; | |
4470 | } | |
3cee5a60 | 4471 | |
0dca1793 AK |
4472 | if (NULL != list) { |
4473 | for (idx = 0; idx < limit; idx++) { | |
3cee5a60 | 4474 | err = snd_ctl_add(card, |
0dca1793 | 4475 | snd_ctl_new1(&list[idx], hdspm)); |
3cee5a60 RB |
4476 | if (err < 0) |
4477 | return err; | |
763f356c TI |
4478 | } |
4479 | } | |
4480 | ||
763f356c | 4481 | |
0dca1793 | 4482 | /* create simple 1:1 playback mixer controls */ |
763f356c | 4483 | snd_hdspm_playback_mixer.name = "Chn"; |
0dca1793 AK |
4484 | if (hdspm->system_sample_rate >= 128000) { |
4485 | limit = hdspm->qs_out_channels; | |
4486 | } else if (hdspm->system_sample_rate >= 64000) { | |
4487 | limit = hdspm->ds_out_channels; | |
4488 | } else { | |
4489 | limit = hdspm->ss_out_channels; | |
4490 | } | |
763f356c TI |
4491 | for (idx = 0; idx < limit; ++idx) { |
4492 | snd_hdspm_playback_mixer.index = idx + 1; | |
ef5fa1a4 TI |
4493 | kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm); |
4494 | err = snd_ctl_add(card, kctl); | |
4495 | if (err < 0) | |
763f356c | 4496 | return err; |
763f356c TI |
4497 | hdspm->playback_mixer_ctls[idx] = kctl; |
4498 | } | |
4499 | ||
0dca1793 AK |
4500 | |
4501 | if (hdspm->tco) { | |
4502 | /* add tco control elements */ | |
4503 | list = snd_hdspm_controls_tco; | |
4504 | limit = ARRAY_SIZE(snd_hdspm_controls_tco); | |
4505 | for (idx = 0; idx < limit; idx++) { | |
4506 | err = snd_ctl_add(card, | |
4507 | snd_ctl_new1(&list[idx], hdspm)); | |
4508 | if (err < 0) | |
4509 | return err; | |
4510 | } | |
4511 | } | |
4512 | ||
763f356c TI |
4513 | return 0; |
4514 | } | |
4515 | ||
4516 | /*------------------------------------------------------------ | |
0dca1793 | 4517 | /proc interface |
763f356c TI |
4518 | ------------------------------------------------------------*/ |
4519 | ||
4520 | static void | |
3cee5a60 RB |
4521 | snd_hdspm_proc_read_madi(struct snd_info_entry * entry, |
4522 | struct snd_info_buffer *buffer) | |
763f356c | 4523 | { |
ef5fa1a4 | 4524 | struct hdspm *hdspm = entry->private_data; |
0dca1793 AK |
4525 | unsigned int status, status2, control, freq; |
4526 | ||
763f356c TI |
4527 | char *pref_sync_ref; |
4528 | char *autosync_ref; | |
4529 | char *system_clock_mode; | |
763f356c | 4530 | char *insel; |
763f356c TI |
4531 | int x, x2; |
4532 | ||
0dca1793 AK |
4533 | /* TCO stuff */ |
4534 | int a, ltc, frames, seconds, minutes, hours; | |
4535 | unsigned int period; | |
4536 | u64 freq_const = 0; | |
4537 | u32 rate; | |
4538 | ||
763f356c TI |
4539 | status = hdspm_read(hdspm, HDSPM_statusRegister); |
4540 | status2 = hdspm_read(hdspm, HDSPM_statusRegister2); | |
0dca1793 AK |
4541 | control = hdspm->control_register; |
4542 | freq = hdspm_read(hdspm, HDSPM_timecodeRegister); | |
763f356c TI |
4543 | |
4544 | snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n", | |
0dca1793 AK |
4545 | hdspm->card_name, hdspm->card->number + 1, |
4546 | hdspm->firmware_rev, | |
4547 | (status2 & HDSPM_version0) | | |
4548 | (status2 & HDSPM_version1) | (status2 & | |
4549 | HDSPM_version2)); | |
4550 | ||
4551 | snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n", | |
4552 | (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF, | |
4553 | (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF); | |
763f356c TI |
4554 | |
4555 | snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", | |
0dca1793 | 4556 | hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase); |
763f356c TI |
4557 | |
4558 | snd_iprintf(buffer, "--- System ---\n"); | |
4559 | ||
4560 | snd_iprintf(buffer, | |
0dca1793 AK |
4561 | "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n", |
4562 | status & HDSPM_audioIRQPending, | |
4563 | (status & HDSPM_midi0IRQPending) ? 1 : 0, | |
4564 | (status & HDSPM_midi1IRQPending) ? 1 : 0, | |
4565 | hdspm->irq_count); | |
763f356c | 4566 | snd_iprintf(buffer, |
0dca1793 AK |
4567 | "HW pointer: id = %d, rawptr = %d (%d->%d) " |
4568 | "estimated= %ld (bytes)\n", | |
4569 | ((status & HDSPM_BufferID) ? 1 : 0), | |
4570 | (status & HDSPM_BufferPositionMask), | |
4571 | (status & HDSPM_BufferPositionMask) % | |
4572 | (2 * (int)hdspm->period_bytes), | |
4573 | ((status & HDSPM_BufferPositionMask) - 64) % | |
4574 | (2 * (int)hdspm->period_bytes), | |
4575 | (long) hdspm_hw_pointer(hdspm) * 4); | |
763f356c TI |
4576 | |
4577 | snd_iprintf(buffer, | |
0dca1793 AK |
4578 | "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n", |
4579 | hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF, | |
4580 | hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF, | |
4581 | hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF, | |
4582 | hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF); | |
763f356c | 4583 | snd_iprintf(buffer, |
0dca1793 AK |
4584 | "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n", |
4585 | hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF, | |
4586 | hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF); | |
4587 | snd_iprintf(buffer, | |
4588 | "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, " | |
4589 | "status2=0x%x\n", | |
4590 | hdspm->control_register, hdspm->control2_register, | |
4591 | status, status2); | |
4592 | if (status & HDSPM_tco_detect) { | |
4593 | snd_iprintf(buffer, "TCO module detected.\n"); | |
4594 | a = hdspm_read(hdspm, HDSPM_RD_TCO+4); | |
4595 | if (a & HDSPM_TCO1_LTC_Input_valid) { | |
4596 | snd_iprintf(buffer, " LTC valid, "); | |
4597 | switch (a & (HDSPM_TCO1_LTC_Format_LSB | | |
4598 | HDSPM_TCO1_LTC_Format_MSB)) { | |
4599 | case 0: | |
4600 | snd_iprintf(buffer, "24 fps, "); | |
4601 | break; | |
4602 | case HDSPM_TCO1_LTC_Format_LSB: | |
4603 | snd_iprintf(buffer, "25 fps, "); | |
4604 | break; | |
4605 | case HDSPM_TCO1_LTC_Format_MSB: | |
4606 | snd_iprintf(buffer, "29.97 fps, "); | |
4607 | break; | |
4608 | default: | |
4609 | snd_iprintf(buffer, "30 fps, "); | |
4610 | break; | |
4611 | } | |
4612 | if (a & HDSPM_TCO1_set_drop_frame_flag) { | |
4613 | snd_iprintf(buffer, "drop frame\n"); | |
4614 | } else { | |
4615 | snd_iprintf(buffer, "full frame\n"); | |
4616 | } | |
4617 | } else { | |
4618 | snd_iprintf(buffer, " no LTC\n"); | |
4619 | } | |
4620 | if (a & HDSPM_TCO1_Video_Input_Format_NTSC) { | |
4621 | snd_iprintf(buffer, " Video: NTSC\n"); | |
4622 | } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) { | |
4623 | snd_iprintf(buffer, " Video: PAL\n"); | |
4624 | } else { | |
4625 | snd_iprintf(buffer, " No video\n"); | |
4626 | } | |
4627 | if (a & HDSPM_TCO1_TCO_lock) { | |
4628 | snd_iprintf(buffer, " Sync: lock\n"); | |
4629 | } else { | |
4630 | snd_iprintf(buffer, " Sync: no lock\n"); | |
4631 | } | |
4632 | ||
4633 | switch (hdspm->io_type) { | |
4634 | case MADI: | |
4635 | case AES32: | |
4636 | freq_const = 110069313433624ULL; | |
4637 | break; | |
4638 | case RayDAT: | |
4639 | case AIO: | |
4640 | freq_const = 104857600000000ULL; | |
4641 | break; | |
4642 | case MADIface: | |
4643 | break; /* no TCO possible */ | |
4644 | } | |
4645 | ||
4646 | period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); | |
4647 | snd_iprintf(buffer, " period: %u\n", period); | |
4648 | ||
4649 | ||
4650 | /* rate = freq_const/period; */ | |
4651 | rate = div_u64(freq_const, period); | |
4652 | ||
4653 | if (control & HDSPM_QuadSpeed) { | |
4654 | rate *= 4; | |
4655 | } else if (control & HDSPM_DoubleSpeed) { | |
4656 | rate *= 2; | |
4657 | } | |
4658 | ||
4659 | snd_iprintf(buffer, " Frequency: %u Hz\n", | |
4660 | (unsigned int) rate); | |
4661 | ||
4662 | ltc = hdspm_read(hdspm, HDSPM_RD_TCO); | |
4663 | frames = ltc & 0xF; | |
4664 | ltc >>= 4; | |
4665 | frames += (ltc & 0x3) * 10; | |
4666 | ltc >>= 4; | |
4667 | seconds = ltc & 0xF; | |
4668 | ltc >>= 4; | |
4669 | seconds += (ltc & 0x7) * 10; | |
4670 | ltc >>= 4; | |
4671 | minutes = ltc & 0xF; | |
4672 | ltc >>= 4; | |
4673 | minutes += (ltc & 0x7) * 10; | |
4674 | ltc >>= 4; | |
4675 | hours = ltc & 0xF; | |
4676 | ltc >>= 4; | |
4677 | hours += (ltc & 0x3) * 10; | |
4678 | snd_iprintf(buffer, | |
4679 | " LTC In: %02d:%02d:%02d:%02d\n", | |
4680 | hours, minutes, seconds, frames); | |
4681 | ||
4682 | } else { | |
4683 | snd_iprintf(buffer, "No TCO module detected.\n"); | |
4684 | } | |
763f356c TI |
4685 | |
4686 | snd_iprintf(buffer, "--- Settings ---\n"); | |
4687 | ||
ef5fa1a4 | 4688 | x = 1 << (6 + hdspm_decode_latency(hdspm->control_register & |
0dca1793 | 4689 | HDSPM_LatencyMask)); |
763f356c TI |
4690 | |
4691 | snd_iprintf(buffer, | |
0dca1793 AK |
4692 | "Size (Latency): %d samples (2 periods of %lu bytes)\n", |
4693 | x, (unsigned long) hdspm->period_bytes); | |
763f356c | 4694 | |
0dca1793 AK |
4695 | snd_iprintf(buffer, "Line out: %s\n", |
4696 | (hdspm->control_register & HDSPM_LineOut) ? "on " : "off"); | |
763f356c TI |
4697 | |
4698 | switch (hdspm->control_register & HDSPM_InputMask) { | |
4699 | case HDSPM_InputOptical: | |
4700 | insel = "Optical"; | |
4701 | break; | |
4702 | case HDSPM_InputCoaxial: | |
4703 | insel = "Coaxial"; | |
4704 | break; | |
4705 | default: | |
0dca1793 | 4706 | insel = "Unkown"; |
763f356c | 4707 | } |
763f356c TI |
4708 | |
4709 | snd_iprintf(buffer, | |
0dca1793 AK |
4710 | "ClearTrackMarker = %s, Transmit in %s Channel Mode, " |
4711 | "Auto Input %s\n", | |
4712 | (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off", | |
4713 | (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56", | |
4714 | (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off"); | |
4715 | ||
763f356c | 4716 | |
3cee5a60 | 4717 | if (!(hdspm->control_register & HDSPM_ClockModeMaster)) |
0dca1793 | 4718 | system_clock_mode = "AutoSync"; |
3cee5a60 | 4719 | else |
763f356c | 4720 | system_clock_mode = "Master"; |
0dca1793 | 4721 | snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode); |
763f356c TI |
4722 | |
4723 | switch (hdspm_pref_sync_ref(hdspm)) { | |
4724 | case HDSPM_SYNC_FROM_WORD: | |
4725 | pref_sync_ref = "Word Clock"; | |
4726 | break; | |
4727 | case HDSPM_SYNC_FROM_MADI: | |
4728 | pref_sync_ref = "MADI Sync"; | |
4729 | break; | |
0dca1793 AK |
4730 | case HDSPM_SYNC_FROM_TCO: |
4731 | pref_sync_ref = "TCO"; | |
4732 | break; | |
4733 | case HDSPM_SYNC_FROM_SYNC_IN: | |
4734 | pref_sync_ref = "Sync In"; | |
4735 | break; | |
763f356c TI |
4736 | default: |
4737 | pref_sync_ref = "XXXX Clock"; | |
4738 | break; | |
4739 | } | |
4740 | snd_iprintf(buffer, "Preferred Sync Reference: %s\n", | |
0dca1793 | 4741 | pref_sync_ref); |
763f356c TI |
4742 | |
4743 | snd_iprintf(buffer, "System Clock Frequency: %d\n", | |
0dca1793 | 4744 | hdspm->system_sample_rate); |
763f356c TI |
4745 | |
4746 | ||
4747 | snd_iprintf(buffer, "--- Status:\n"); | |
4748 | ||
4749 | x = status & HDSPM_madiSync; | |
4750 | x2 = status2 & HDSPM_wcSync; | |
4751 | ||
4752 | snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n", | |
0dca1793 AK |
4753 | (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") : |
4754 | "NoLock", | |
4755 | (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") : | |
4756 | "NoLock"); | |
763f356c TI |
4757 | |
4758 | switch (hdspm_autosync_ref(hdspm)) { | |
0dca1793 AK |
4759 | case HDSPM_AUTOSYNC_FROM_SYNC_IN: |
4760 | autosync_ref = "Sync In"; | |
4761 | break; | |
4762 | case HDSPM_AUTOSYNC_FROM_TCO: | |
4763 | autosync_ref = "TCO"; | |
4764 | break; | |
763f356c TI |
4765 | case HDSPM_AUTOSYNC_FROM_WORD: |
4766 | autosync_ref = "Word Clock"; | |
4767 | break; | |
4768 | case HDSPM_AUTOSYNC_FROM_MADI: | |
4769 | autosync_ref = "MADI Sync"; | |
4770 | break; | |
4771 | case HDSPM_AUTOSYNC_FROM_NONE: | |
4772 | autosync_ref = "Input not valid"; | |
4773 | break; | |
4774 | default: | |
4775 | autosync_ref = "---"; | |
4776 | break; | |
4777 | } | |
4778 | snd_iprintf(buffer, | |
0dca1793 AK |
4779 | "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n", |
4780 | autosync_ref, hdspm_external_sample_rate(hdspm), | |
4781 | (status & HDSPM_madiFreqMask) >> 22, | |
4782 | (status2 & HDSPM_wcFreqMask) >> 5); | |
763f356c TI |
4783 | |
4784 | snd_iprintf(buffer, "Input: %s, Mode=%s\n", | |
0dca1793 AK |
4785 | (status & HDSPM_AB_int) ? "Coax" : "Optical", |
4786 | (status & HDSPM_RX_64ch) ? "64 channels" : | |
4787 | "56 channels"); | |
763f356c TI |
4788 | |
4789 | snd_iprintf(buffer, "\n"); | |
4790 | } | |
4791 | ||
3cee5a60 RB |
4792 | static void |
4793 | snd_hdspm_proc_read_aes32(struct snd_info_entry * entry, | |
4794 | struct snd_info_buffer *buffer) | |
4795 | { | |
ef5fa1a4 | 4796 | struct hdspm *hdspm = entry->private_data; |
3cee5a60 RB |
4797 | unsigned int status; |
4798 | unsigned int status2; | |
4799 | unsigned int timecode; | |
4800 | int pref_syncref; | |
4801 | char *autosync_ref; | |
3cee5a60 RB |
4802 | int x; |
4803 | ||
4804 | status = hdspm_read(hdspm, HDSPM_statusRegister); | |
4805 | status2 = hdspm_read(hdspm, HDSPM_statusRegister2); | |
4806 | timecode = hdspm_read(hdspm, HDSPM_timecodeRegister); | |
4807 | ||
4808 | snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n", | |
4809 | hdspm->card_name, hdspm->card->number + 1, | |
4810 | hdspm->firmware_rev); | |
4811 | ||
4812 | snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", | |
4813 | hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase); | |
4814 | ||
4815 | snd_iprintf(buffer, "--- System ---\n"); | |
4816 | ||
4817 | snd_iprintf(buffer, | |
4818 | "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n", | |
4819 | status & HDSPM_audioIRQPending, | |
4820 | (status & HDSPM_midi0IRQPending) ? 1 : 0, | |
4821 | (status & HDSPM_midi1IRQPending) ? 1 : 0, | |
4822 | hdspm->irq_count); | |
4823 | snd_iprintf(buffer, | |
ef5fa1a4 TI |
4824 | "HW pointer: id = %d, rawptr = %d (%d->%d) " |
4825 | "estimated= %ld (bytes)\n", | |
3cee5a60 RB |
4826 | ((status & HDSPM_BufferID) ? 1 : 0), |
4827 | (status & HDSPM_BufferPositionMask), | |
ef5fa1a4 TI |
4828 | (status & HDSPM_BufferPositionMask) % |
4829 | (2 * (int)hdspm->period_bytes), | |
4830 | ((status & HDSPM_BufferPositionMask) - 64) % | |
4831 | (2 * (int)hdspm->period_bytes), | |
3cee5a60 RB |
4832 | (long) hdspm_hw_pointer(hdspm) * 4); |
4833 | ||
4834 | snd_iprintf(buffer, | |
4835 | "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n", | |
4836 | hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF, | |
4837 | hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF, | |
4838 | hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF, | |
4839 | hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF); | |
4840 | snd_iprintf(buffer, | |
0dca1793 AK |
4841 | "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n", |
4842 | hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF, | |
4843 | hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF); | |
4844 | snd_iprintf(buffer, | |
4845 | "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, " | |
4846 | "status2=0x%x\n", | |
4847 | hdspm->control_register, hdspm->control2_register, | |
4848 | status, status2); | |
3cee5a60 RB |
4849 | |
4850 | snd_iprintf(buffer, "--- Settings ---\n"); | |
4851 | ||
ef5fa1a4 | 4852 | x = 1 << (6 + hdspm_decode_latency(hdspm->control_register & |
0dca1793 | 4853 | HDSPM_LatencyMask)); |
3cee5a60 RB |
4854 | |
4855 | snd_iprintf(buffer, | |
4856 | "Size (Latency): %d samples (2 periods of %lu bytes)\n", | |
4857 | x, (unsigned long) hdspm->period_bytes); | |
4858 | ||
0dca1793 | 4859 | snd_iprintf(buffer, "Line out: %s\n", |
3cee5a60 | 4860 | (hdspm-> |
0dca1793 | 4861 | control_register & HDSPM_LineOut) ? "on " : "off"); |
3cee5a60 RB |
4862 | |
4863 | snd_iprintf(buffer, | |
4864 | "ClearTrackMarker %s, Emphasis %s, Dolby %s\n", | |
4865 | (hdspm-> | |
4866 | control_register & HDSPM_clr_tms) ? "on" : "off", | |
4867 | (hdspm-> | |
4868 | control_register & HDSPM_Emphasis) ? "on" : "off", | |
4869 | (hdspm-> | |
4870 | control_register & HDSPM_Dolby) ? "on" : "off"); | |
4871 | ||
3cee5a60 RB |
4872 | |
4873 | pref_syncref = hdspm_pref_sync_ref(hdspm); | |
4874 | if (pref_syncref == 0) | |
4875 | snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n"); | |
4876 | else | |
4877 | snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n", | |
4878 | pref_syncref); | |
4879 | ||
4880 | snd_iprintf(buffer, "System Clock Frequency: %d\n", | |
4881 | hdspm->system_sample_rate); | |
4882 | ||
4883 | snd_iprintf(buffer, "Double speed: %s\n", | |
4884 | hdspm->control_register & HDSPM_DS_DoubleWire? | |
4885 | "Double wire" : "Single wire"); | |
4886 | snd_iprintf(buffer, "Quad speed: %s\n", | |
4887 | hdspm->control_register & HDSPM_QS_DoubleWire? | |
4888 | "Double wire" : | |
4889 | hdspm->control_register & HDSPM_QS_QuadWire? | |
4890 | "Quad wire" : "Single wire"); | |
4891 | ||
4892 | snd_iprintf(buffer, "--- Status:\n"); | |
4893 | ||
4894 | snd_iprintf(buffer, "Word: %s Frequency: %d\n", | |
0dca1793 | 4895 | (status & HDSPM_AES32_wcLock) ? "Sync " : "No Lock", |
ef5fa1a4 | 4896 | HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF)); |
3cee5a60 RB |
4897 | |
4898 | for (x = 0; x < 8; x++) { | |
4899 | snd_iprintf(buffer, "AES%d: %s Frequency: %d\n", | |
ef5fa1a4 TI |
4900 | x+1, |
4901 | (status2 & (HDSPM_LockAES >> x)) ? | |
0dca1793 | 4902 | "Sync " : "No Lock", |
ef5fa1a4 | 4903 | HDSPM_bit2freq((timecode >> (4*x)) & 0xF)); |
3cee5a60 RB |
4904 | } |
4905 | ||
4906 | switch (hdspm_autosync_ref(hdspm)) { | |
0dca1793 AK |
4907 | case HDSPM_AES32_AUTOSYNC_FROM_NONE: |
4908 | autosync_ref = "None"; break; | |
4909 | case HDSPM_AES32_AUTOSYNC_FROM_WORD: | |
4910 | autosync_ref = "Word Clock"; break; | |
4911 | case HDSPM_AES32_AUTOSYNC_FROM_AES1: | |
4912 | autosync_ref = "AES1"; break; | |
4913 | case HDSPM_AES32_AUTOSYNC_FROM_AES2: | |
4914 | autosync_ref = "AES2"; break; | |
4915 | case HDSPM_AES32_AUTOSYNC_FROM_AES3: | |
4916 | autosync_ref = "AES3"; break; | |
4917 | case HDSPM_AES32_AUTOSYNC_FROM_AES4: | |
4918 | autosync_ref = "AES4"; break; | |
4919 | case HDSPM_AES32_AUTOSYNC_FROM_AES5: | |
4920 | autosync_ref = "AES5"; break; | |
4921 | case HDSPM_AES32_AUTOSYNC_FROM_AES6: | |
4922 | autosync_ref = "AES6"; break; | |
4923 | case HDSPM_AES32_AUTOSYNC_FROM_AES7: | |
4924 | autosync_ref = "AES7"; break; | |
4925 | case HDSPM_AES32_AUTOSYNC_FROM_AES8: | |
4926 | autosync_ref = "AES8"; break; | |
4927 | default: | |
4928 | autosync_ref = "---"; break; | |
3cee5a60 RB |
4929 | } |
4930 | snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref); | |
4931 | ||
4932 | snd_iprintf(buffer, "\n"); | |
4933 | } | |
4934 | ||
0dca1793 AK |
4935 | static void |
4936 | snd_hdspm_proc_read_raydat(struct snd_info_entry *entry, | |
4937 | struct snd_info_buffer *buffer) | |
4938 | { | |
4939 | struct hdspm *hdspm = entry->private_data; | |
4940 | unsigned int status1, status2, status3, control, i; | |
4941 | unsigned int lock, sync; | |
4942 | ||
4943 | status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */ | |
4944 | status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */ | |
4945 | status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */ | |
4946 | ||
4947 | control = hdspm->control_register; | |
4948 | ||
4949 | snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1); | |
4950 | snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2); | |
4951 | snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3); | |
4952 | ||
4953 | ||
4954 | snd_iprintf(buffer, "\n*** CLOCK MODE\n\n"); | |
4955 | ||
4956 | snd_iprintf(buffer, "Clock mode : %s\n", | |
4957 | (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave"); | |
4958 | snd_iprintf(buffer, "System frequency: %d Hz\n", | |
4959 | hdspm_get_system_sample_rate(hdspm)); | |
4960 | ||
4961 | snd_iprintf(buffer, "\n*** INPUT STATUS\n\n"); | |
4962 | ||
4963 | lock = 0x1; | |
4964 | sync = 0x100; | |
4965 | ||
4966 | for (i = 0; i < 8; i++) { | |
4967 | snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n", | |
4968 | i, | |
4969 | (status1 & lock) ? 1 : 0, | |
4970 | (status1 & sync) ? 1 : 0, | |
4971 | texts_freq[(status2 >> (i * 4)) & 0xF]); | |
4972 | ||
4973 | lock = lock<<1; | |
4974 | sync = sync<<1; | |
4975 | } | |
4976 | ||
4977 | snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n", | |
4978 | (status1 & 0x1000000) ? 1 : 0, | |
4979 | (status1 & 0x2000000) ? 1 : 0, | |
4980 | texts_freq[(status1 >> 16) & 0xF]); | |
4981 | ||
4982 | snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n", | |
4983 | (status1 & 0x4000000) ? 1 : 0, | |
4984 | (status1 & 0x8000000) ? 1 : 0, | |
4985 | texts_freq[(status1 >> 20) & 0xF]); | |
4986 | ||
4987 | snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n", | |
4988 | (status3 & 0x400) ? 1 : 0, | |
4989 | (status3 & 0x800) ? 1 : 0, | |
4990 | texts_freq[(status2 >> 12) & 0xF]); | |
4991 | ||
4992 | } | |
4993 | ||
3cee5a60 RB |
4994 | #ifdef CONFIG_SND_DEBUG |
4995 | static void | |
0dca1793 | 4996 | snd_hdspm_proc_read_debug(struct snd_info_entry *entry, |
3cee5a60 RB |
4997 | struct snd_info_buffer *buffer) |
4998 | { | |
ef5fa1a4 | 4999 | struct hdspm *hdspm = entry->private_data; |
3cee5a60 RB |
5000 | |
5001 | int j,i; | |
5002 | ||
ef5fa1a4 | 5003 | for (i = 0; i < 256 /* 1024*64 */; i += j) { |
3cee5a60 RB |
5004 | snd_iprintf(buffer, "0x%08X: ", i); |
5005 | for (j = 0; j < 16; j += 4) | |
5006 | snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j)); | |
5007 | snd_iprintf(buffer, "\n"); | |
5008 | } | |
5009 | } | |
5010 | #endif | |
5011 | ||
5012 | ||
0dca1793 AK |
5013 | static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry, |
5014 | struct snd_info_buffer *buffer) | |
5015 | { | |
5016 | struct hdspm *hdspm = entry->private_data; | |
5017 | int i; | |
5018 | ||
5019 | snd_iprintf(buffer, "# generated by hdspm\n"); | |
5020 | ||
5021 | for (i = 0; i < hdspm->max_channels_in; i++) { | |
5022 | snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]); | |
5023 | } | |
5024 | } | |
5025 | ||
5026 | static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry, | |
5027 | struct snd_info_buffer *buffer) | |
5028 | { | |
5029 | struct hdspm *hdspm = entry->private_data; | |
5030 | int i; | |
5031 | ||
5032 | snd_iprintf(buffer, "# generated by hdspm\n"); | |
5033 | ||
5034 | for (i = 0; i < hdspm->max_channels_out; i++) { | |
5035 | snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]); | |
5036 | } | |
5037 | } | |
5038 | ||
3cee5a60 | 5039 | |
0dca1793 | 5040 | static void __devinit snd_hdspm_proc_init(struct hdspm *hdspm) |
763f356c | 5041 | { |
98274f07 | 5042 | struct snd_info_entry *entry; |
763f356c | 5043 | |
0dca1793 AK |
5044 | if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) { |
5045 | switch (hdspm->io_type) { | |
5046 | case AES32: | |
5047 | snd_info_set_text_ops(entry, hdspm, | |
5048 | snd_hdspm_proc_read_aes32); | |
5049 | break; | |
5050 | case MADI: | |
5051 | snd_info_set_text_ops(entry, hdspm, | |
5052 | snd_hdspm_proc_read_madi); | |
5053 | break; | |
5054 | case MADIface: | |
5055 | /* snd_info_set_text_ops(entry, hdspm, | |
5056 | snd_hdspm_proc_read_madiface); */ | |
5057 | break; | |
5058 | case RayDAT: | |
5059 | snd_info_set_text_ops(entry, hdspm, | |
5060 | snd_hdspm_proc_read_raydat); | |
5061 | break; | |
5062 | case AIO: | |
5063 | break; | |
5064 | } | |
5065 | } | |
5066 | ||
5067 | if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) { | |
5068 | snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in); | |
5069 | } | |
5070 | ||
5071 | if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) { | |
5072 | snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out); | |
5073 | } | |
5074 | ||
3cee5a60 RB |
5075 | #ifdef CONFIG_SND_DEBUG |
5076 | /* debug file to read all hdspm registers */ | |
5077 | if (!snd_card_proc_new(hdspm->card, "debug", &entry)) | |
5078 | snd_info_set_text_ops(entry, hdspm, | |
5079 | snd_hdspm_proc_read_debug); | |
5080 | #endif | |
763f356c TI |
5081 | } |
5082 | ||
5083 | /*------------------------------------------------------------ | |
0dca1793 | 5084 | hdspm intitialize |
763f356c TI |
5085 | ------------------------------------------------------------*/ |
5086 | ||
98274f07 | 5087 | static int snd_hdspm_set_defaults(struct hdspm * hdspm) |
763f356c | 5088 | { |
763f356c | 5089 | /* ASSUMPTION: hdspm->lock is either held, or there is no need to |
561de31a | 5090 | hold it (e.g. during module initialization). |
0dca1793 | 5091 | */ |
763f356c TI |
5092 | |
5093 | /* set defaults: */ | |
5094 | ||
0dca1793 AK |
5095 | hdspm->settings_register = 0; |
5096 | ||
5097 | switch (hdspm->io_type) { | |
5098 | case MADI: | |
5099 | case MADIface: | |
5100 | hdspm->control_register = | |
5101 | 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000; | |
5102 | break; | |
5103 | ||
5104 | case RayDAT: | |
5105 | case AIO: | |
5106 | hdspm->settings_register = 0x1 + 0x1000; | |
5107 | /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0, | |
5108 | * line_out */ | |
5109 | hdspm->control_register = | |
5110 | 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000; | |
5111 | break; | |
5112 | ||
5113 | case AES32: | |
ef5fa1a4 TI |
5114 | hdspm->control_register = |
5115 | HDSPM_ClockModeMaster | /* Master Cloack Mode on */ | |
0dca1793 | 5116 | hdspm_encode_latency(7) | /* latency max=8192samples */ |
3cee5a60 RB |
5117 | HDSPM_SyncRef0 | /* AES1 is syncclock */ |
5118 | HDSPM_LineOut | /* Analog output in */ | |
5119 | HDSPM_Professional; /* Professional mode */ | |
0dca1793 AK |
5120 | break; |
5121 | } | |
763f356c TI |
5122 | |
5123 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); | |
5124 | ||
0dca1793 | 5125 | if (AES32 == hdspm->io_type) { |
ffb2c3c0 | 5126 | /* No control2 register for AES32 */ |
763f356c | 5127 | #ifdef SNDRV_BIG_ENDIAN |
ffb2c3c0 | 5128 | hdspm->control2_register = HDSPM_BIGENDIAN_MODE; |
763f356c | 5129 | #else |
ffb2c3c0 | 5130 | hdspm->control2_register = 0; |
763f356c TI |
5131 | #endif |
5132 | ||
ffb2c3c0 RB |
5133 | hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register); |
5134 | } | |
763f356c TI |
5135 | hdspm_compute_period_size(hdspm); |
5136 | ||
5137 | /* silence everything */ | |
5138 | ||
5139 | all_in_all_mixer(hdspm, 0 * UNITY_GAIN); | |
5140 | ||
0dca1793 AK |
5141 | if (hdspm->io_type == AIO || hdspm->io_type == RayDAT) { |
5142 | hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); | |
763f356c TI |
5143 | } |
5144 | ||
5145 | /* set a default rate so that the channel map is set up. */ | |
0dca1793 | 5146 | hdspm_set_rate(hdspm, 48000, 1); |
763f356c TI |
5147 | |
5148 | return 0; | |
5149 | } | |
5150 | ||
5151 | ||
5152 | /*------------------------------------------------------------ | |
0dca1793 | 5153 | interrupt |
763f356c TI |
5154 | ------------------------------------------------------------*/ |
5155 | ||
7d12e780 | 5156 | static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id) |
763f356c | 5157 | { |
98274f07 | 5158 | struct hdspm *hdspm = (struct hdspm *) dev_id; |
763f356c | 5159 | unsigned int status; |
0dca1793 AK |
5160 | int i, audio, midi, schedule = 0; |
5161 | /* cycles_t now; */ | |
763f356c TI |
5162 | |
5163 | status = hdspm_read(hdspm, HDSPM_statusRegister); | |
5164 | ||
5165 | audio = status & HDSPM_audioIRQPending; | |
0dca1793 AK |
5166 | midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending | |
5167 | HDSPM_midi2IRQPending | HDSPM_midi3IRQPending); | |
5168 | ||
5169 | /* now = get_cycles(); */ | |
5170 | /** | |
5171 | * LAT_2..LAT_0 period counter (win) counter (mac) | |
5172 | * 6 4096 ~256053425 ~514672358 | |
5173 | * 5 2048 ~128024983 ~257373821 | |
5174 | * 4 1024 ~64023706 ~128718089 | |
5175 | * 3 512 ~32005945 ~64385999 | |
5176 | * 2 256 ~16003039 ~32260176 | |
5177 | * 1 128 ~7998738 ~16194507 | |
5178 | * 0 64 ~3998231 ~8191558 | |
5179 | **/ | |
5180 | /* | |
5181 | snd_printk(KERN_INFO "snd_hdspm_interrupt %llu @ %llx\n", | |
5182 | now-hdspm->last_interrupt, status & 0xFFC0); | |
5183 | hdspm->last_interrupt = now; | |
5184 | */ | |
763f356c | 5185 | |
0dca1793 | 5186 | if (!audio && !midi) |
763f356c TI |
5187 | return IRQ_NONE; |
5188 | ||
5189 | hdspm_write(hdspm, HDSPM_interruptConfirmation, 0); | |
5190 | hdspm->irq_count++; | |
5191 | ||
763f356c TI |
5192 | |
5193 | if (audio) { | |
763f356c | 5194 | if (hdspm->capture_substream) |
ef5fa1a4 | 5195 | snd_pcm_period_elapsed(hdspm->capture_substream); |
763f356c TI |
5196 | |
5197 | if (hdspm->playback_substream) | |
ef5fa1a4 | 5198 | snd_pcm_period_elapsed(hdspm->playback_substream); |
763f356c TI |
5199 | } |
5200 | ||
0dca1793 AK |
5201 | if (midi) { |
5202 | i = 0; | |
5203 | while (i < hdspm->midiPorts) { | |
5204 | if ((hdspm_read(hdspm, | |
5205 | hdspm->midi[i].statusIn) & 0xff) && | |
5206 | (status & hdspm->midi[i].irq)) { | |
5207 | /* we disable interrupts for this input until | |
5208 | * processing is done | |
5209 | */ | |
5210 | hdspm->control_register &= ~hdspm->midi[i].ie; | |
5211 | hdspm_write(hdspm, HDSPM_controlRegister, | |
5212 | hdspm->control_register); | |
5213 | hdspm->midi[i].pending = 1; | |
5214 | schedule = 1; | |
5215 | } | |
5216 | ||
5217 | i++; | |
5218 | } | |
5219 | ||
5220 | if (schedule) | |
5221 | tasklet_hi_schedule(&hdspm->midi_tasklet); | |
763f356c | 5222 | } |
0dca1793 | 5223 | |
763f356c TI |
5224 | return IRQ_HANDLED; |
5225 | } | |
5226 | ||
5227 | /*------------------------------------------------------------ | |
0dca1793 | 5228 | pcm interface |
763f356c TI |
5229 | ------------------------------------------------------------*/ |
5230 | ||
5231 | ||
0dca1793 AK |
5232 | static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream |
5233 | *substream) | |
763f356c | 5234 | { |
98274f07 | 5235 | struct hdspm *hdspm = snd_pcm_substream_chip(substream); |
763f356c TI |
5236 | return hdspm_hw_pointer(hdspm); |
5237 | } | |
5238 | ||
763f356c | 5239 | |
98274f07 | 5240 | static int snd_hdspm_reset(struct snd_pcm_substream *substream) |
763f356c | 5241 | { |
98274f07 TI |
5242 | struct snd_pcm_runtime *runtime = substream->runtime; |
5243 | struct hdspm *hdspm = snd_pcm_substream_chip(substream); | |
5244 | struct snd_pcm_substream *other; | |
763f356c TI |
5245 | |
5246 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
5247 | other = hdspm->capture_substream; | |
5248 | else | |
5249 | other = hdspm->playback_substream; | |
5250 | ||
5251 | if (hdspm->running) | |
5252 | runtime->status->hw_ptr = hdspm_hw_pointer(hdspm); | |
5253 | else | |
5254 | runtime->status->hw_ptr = 0; | |
5255 | if (other) { | |
98274f07 TI |
5256 | struct snd_pcm_substream *s; |
5257 | struct snd_pcm_runtime *oruntime = other->runtime; | |
ef991b95 | 5258 | snd_pcm_group_for_each_entry(s, substream) { |
763f356c TI |
5259 | if (s == other) { |
5260 | oruntime->status->hw_ptr = | |
0dca1793 | 5261 | runtime->status->hw_ptr; |
763f356c TI |
5262 | break; |
5263 | } | |
5264 | } | |
5265 | } | |
5266 | return 0; | |
5267 | } | |
5268 | ||
98274f07 TI |
5269 | static int snd_hdspm_hw_params(struct snd_pcm_substream *substream, |
5270 | struct snd_pcm_hw_params *params) | |
763f356c | 5271 | { |
98274f07 | 5272 | struct hdspm *hdspm = snd_pcm_substream_chip(substream); |
763f356c TI |
5273 | int err; |
5274 | int i; | |
5275 | pid_t this_pid; | |
5276 | pid_t other_pid; | |
763f356c TI |
5277 | |
5278 | spin_lock_irq(&hdspm->lock); | |
5279 | ||
5280 | if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
5281 | this_pid = hdspm->playback_pid; | |
5282 | other_pid = hdspm->capture_pid; | |
5283 | } else { | |
5284 | this_pid = hdspm->capture_pid; | |
5285 | other_pid = hdspm->playback_pid; | |
5286 | } | |
5287 | ||
ef5fa1a4 | 5288 | if (other_pid > 0 && this_pid != other_pid) { |
763f356c TI |
5289 | |
5290 | /* The other stream is open, and not by the same | |
5291 | task as this one. Make sure that the parameters | |
5292 | that matter are the same. | |
0dca1793 | 5293 | */ |
763f356c TI |
5294 | |
5295 | if (params_rate(params) != hdspm->system_sample_rate) { | |
5296 | spin_unlock_irq(&hdspm->lock); | |
5297 | _snd_pcm_hw_param_setempty(params, | |
0dca1793 | 5298 | SNDRV_PCM_HW_PARAM_RATE); |
763f356c TI |
5299 | return -EBUSY; |
5300 | } | |
5301 | ||
5302 | if (params_period_size(params) != hdspm->period_bytes / 4) { | |
5303 | spin_unlock_irq(&hdspm->lock); | |
5304 | _snd_pcm_hw_param_setempty(params, | |
0dca1793 | 5305 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE); |
763f356c TI |
5306 | return -EBUSY; |
5307 | } | |
5308 | ||
5309 | } | |
5310 | /* We're fine. */ | |
5311 | spin_unlock_irq(&hdspm->lock); | |
5312 | ||
5313 | /* how to make sure that the rate matches an externally-set one ? */ | |
5314 | ||
5315 | spin_lock_irq(&hdspm->lock); | |
ef5fa1a4 TI |
5316 | err = hdspm_set_rate(hdspm, params_rate(params), 0); |
5317 | if (err < 0) { | |
0dca1793 | 5318 | snd_printk(KERN_INFO "err on hdspm_set_rate: %d\n", err); |
763f356c TI |
5319 | spin_unlock_irq(&hdspm->lock); |
5320 | _snd_pcm_hw_param_setempty(params, | |
0dca1793 | 5321 | SNDRV_PCM_HW_PARAM_RATE); |
763f356c TI |
5322 | return err; |
5323 | } | |
5324 | spin_unlock_irq(&hdspm->lock); | |
5325 | ||
ef5fa1a4 | 5326 | err = hdspm_set_interrupt_interval(hdspm, |
0dca1793 | 5327 | params_period_size(params)); |
ef5fa1a4 | 5328 | if (err < 0) { |
0dca1793 | 5329 | snd_printk(KERN_INFO "err on hdspm_set_interrupt_interval: %d\n", err); |
763f356c | 5330 | _snd_pcm_hw_param_setempty(params, |
0dca1793 | 5331 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE); |
763f356c TI |
5332 | return err; |
5333 | } | |
5334 | ||
ef5fa1a4 TI |
5335 | /* Memory allocation, takashi's method, dont know if we should |
5336 | * spinlock | |
5337 | */ | |
763f356c | 5338 | /* malloc all buffer even if not enabled to get sure */ |
ffb2c3c0 RB |
5339 | /* Update for MADI rev 204: we need to allocate for all channels, |
5340 | * otherwise it doesn't work at 96kHz */ | |
0dca1793 | 5341 | |
763f356c | 5342 | err = |
0dca1793 AK |
5343 | snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES); |
5344 | if (err < 0) { | |
5345 | snd_printk(KERN_INFO "err on snd_pcm_lib_malloc_pages: %d\n", err); | |
763f356c | 5346 | return err; |
0dca1793 | 5347 | } |
763f356c | 5348 | |
763f356c TI |
5349 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
5350 | ||
77a23f26 | 5351 | hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut, |
763f356c TI |
5352 | params_channels(params)); |
5353 | ||
5354 | for (i = 0; i < params_channels(params); ++i) | |
5355 | snd_hdspm_enable_out(hdspm, i, 1); | |
5356 | ||
5357 | hdspm->playback_buffer = | |
0dca1793 | 5358 | (unsigned char *) substream->runtime->dma_area; |
54bf5dd9 | 5359 | snd_printdd("Allocated sample buffer for playback at %p\n", |
3cee5a60 | 5360 | hdspm->playback_buffer); |
763f356c | 5361 | } else { |
77a23f26 | 5362 | hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn, |
763f356c TI |
5363 | params_channels(params)); |
5364 | ||
5365 | for (i = 0; i < params_channels(params); ++i) | |
5366 | snd_hdspm_enable_in(hdspm, i, 1); | |
5367 | ||
5368 | hdspm->capture_buffer = | |
0dca1793 | 5369 | (unsigned char *) substream->runtime->dma_area; |
54bf5dd9 | 5370 | snd_printdd("Allocated sample buffer for capture at %p\n", |
3cee5a60 | 5371 | hdspm->capture_buffer); |
763f356c | 5372 | } |
0dca1793 | 5373 | |
3cee5a60 RB |
5374 | /* |
5375 | snd_printdd("Allocated sample buffer for %s at 0x%08X\n", | |
5376 | substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? | |
5377 | "playback" : "capture", | |
77a23f26 | 5378 | snd_pcm_sgbuf_get_addr(substream, 0)); |
0dca1793 | 5379 | */ |
ffb2c3c0 | 5380 | /* |
0dca1793 AK |
5381 | snd_printdd("set_hwparams: %s %d Hz, %d channels, bs = %d\n", |
5382 | substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? | |
5383 | "playback" : "capture", | |
5384 | params_rate(params), params_channels(params), | |
5385 | params_buffer_size(params)); | |
5386 | */ | |
5387 | ||
5388 | ||
5389 | /* Switch to native float format if requested */ | |
5390 | if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) { | |
5391 | if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT)) | |
5392 | snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE float format.\n"); | |
5393 | ||
5394 | hdspm->control_register |= HDSPe_FLOAT_FORMAT; | |
5395 | } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) { | |
5396 | if (hdspm->control_register & HDSPe_FLOAT_FORMAT) | |
5397 | snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE integer format.\n"); | |
5398 | ||
5399 | hdspm->control_register &= ~HDSPe_FLOAT_FORMAT; | |
5400 | } | |
5401 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); | |
5402 | ||
763f356c TI |
5403 | return 0; |
5404 | } | |
5405 | ||
98274f07 | 5406 | static int snd_hdspm_hw_free(struct snd_pcm_substream *substream) |
763f356c TI |
5407 | { |
5408 | int i; | |
98274f07 | 5409 | struct hdspm *hdspm = snd_pcm_substream_chip(substream); |
763f356c TI |
5410 | |
5411 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
5412 | ||
0dca1793 | 5413 | /* params_channels(params) should be enough, |
763f356c | 5414 | but to get sure in case of error */ |
0dca1793 | 5415 | for (i = 0; i < hdspm->max_channels_out; ++i) |
763f356c TI |
5416 | snd_hdspm_enable_out(hdspm, i, 0); |
5417 | ||
5418 | hdspm->playback_buffer = NULL; | |
5419 | } else { | |
0dca1793 | 5420 | for (i = 0; i < hdspm->max_channels_in; ++i) |
763f356c TI |
5421 | snd_hdspm_enable_in(hdspm, i, 0); |
5422 | ||
5423 | hdspm->capture_buffer = NULL; | |
5424 | ||
5425 | } | |
5426 | ||
5427 | snd_pcm_lib_free_pages(substream); | |
5428 | ||
5429 | return 0; | |
5430 | } | |
5431 | ||
0dca1793 | 5432 | |
98274f07 | 5433 | static int snd_hdspm_channel_info(struct snd_pcm_substream *substream, |
0dca1793 | 5434 | struct snd_pcm_channel_info *info) |
763f356c | 5435 | { |
98274f07 | 5436 | struct hdspm *hdspm = snd_pcm_substream_chip(substream); |
763f356c | 5437 | |
0dca1793 AK |
5438 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
5439 | if (snd_BUG_ON(info->channel >= hdspm->max_channels_out)) { | |
5440 | snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel out of range (%d)\n", info->channel); | |
5441 | return -EINVAL; | |
5442 | } | |
763f356c | 5443 | |
0dca1793 AK |
5444 | if (hdspm->channel_map_out[info->channel] < 0) { |
5445 | snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel %d mapped out\n", info->channel); | |
5446 | return -EINVAL; | |
5447 | } | |
5448 | ||
5449 | info->offset = hdspm->channel_map_out[info->channel] * | |
5450 | HDSPM_CHANNEL_BUFFER_BYTES; | |
5451 | } else { | |
5452 | if (snd_BUG_ON(info->channel >= hdspm->max_channels_in)) { | |
5453 | snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel out of range (%d)\n", info->channel); | |
5454 | return -EINVAL; | |
5455 | } | |
5456 | ||
5457 | if (hdspm->channel_map_in[info->channel] < 0) { | |
5458 | snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel %d mapped out\n", info->channel); | |
5459 | return -EINVAL; | |
5460 | } | |
5461 | ||
5462 | info->offset = hdspm->channel_map_in[info->channel] * | |
5463 | HDSPM_CHANNEL_BUFFER_BYTES; | |
5464 | } | |
763f356c | 5465 | |
763f356c TI |
5466 | info->first = 0; |
5467 | info->step = 32; | |
5468 | return 0; | |
5469 | } | |
5470 | ||
0dca1793 | 5471 | |
98274f07 | 5472 | static int snd_hdspm_ioctl(struct snd_pcm_substream *substream, |
0dca1793 | 5473 | unsigned int cmd, void *arg) |
763f356c TI |
5474 | { |
5475 | switch (cmd) { | |
5476 | case SNDRV_PCM_IOCTL1_RESET: | |
ef5fa1a4 | 5477 | return snd_hdspm_reset(substream); |
763f356c TI |
5478 | |
5479 | case SNDRV_PCM_IOCTL1_CHANNEL_INFO: | |
0dca1793 AK |
5480 | { |
5481 | struct snd_pcm_channel_info *info = arg; | |
5482 | return snd_hdspm_channel_info(substream, info); | |
5483 | } | |
763f356c TI |
5484 | default: |
5485 | break; | |
5486 | } | |
5487 | ||
5488 | return snd_pcm_lib_ioctl(substream, cmd, arg); | |
5489 | } | |
5490 | ||
98274f07 | 5491 | static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd) |
763f356c | 5492 | { |
98274f07 TI |
5493 | struct hdspm *hdspm = snd_pcm_substream_chip(substream); |
5494 | struct snd_pcm_substream *other; | |
763f356c TI |
5495 | int running; |
5496 | ||
5497 | spin_lock(&hdspm->lock); | |
5498 | running = hdspm->running; | |
5499 | switch (cmd) { | |
5500 | case SNDRV_PCM_TRIGGER_START: | |
5501 | running |= 1 << substream->stream; | |
5502 | break; | |
5503 | case SNDRV_PCM_TRIGGER_STOP: | |
5504 | running &= ~(1 << substream->stream); | |
5505 | break; | |
5506 | default: | |
5507 | snd_BUG(); | |
5508 | spin_unlock(&hdspm->lock); | |
5509 | return -EINVAL; | |
5510 | } | |
5511 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
5512 | other = hdspm->capture_substream; | |
5513 | else | |
5514 | other = hdspm->playback_substream; | |
5515 | ||
5516 | if (other) { | |
98274f07 | 5517 | struct snd_pcm_substream *s; |
ef991b95 | 5518 | snd_pcm_group_for_each_entry(s, substream) { |
763f356c TI |
5519 | if (s == other) { |
5520 | snd_pcm_trigger_done(s, substream); | |
5521 | if (cmd == SNDRV_PCM_TRIGGER_START) | |
5522 | running |= 1 << s->stream; | |
5523 | else | |
5524 | running &= ~(1 << s->stream); | |
5525 | goto _ok; | |
5526 | } | |
5527 | } | |
5528 | if (cmd == SNDRV_PCM_TRIGGER_START) { | |
5529 | if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) | |
0dca1793 AK |
5530 | && substream->stream == |
5531 | SNDRV_PCM_STREAM_CAPTURE) | |
763f356c TI |
5532 | hdspm_silence_playback(hdspm); |
5533 | } else { | |
5534 | if (running && | |
0dca1793 | 5535 | substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
763f356c TI |
5536 | hdspm_silence_playback(hdspm); |
5537 | } | |
5538 | } else { | |
5539 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) | |
5540 | hdspm_silence_playback(hdspm); | |
5541 | } | |
0dca1793 | 5542 | _ok: |
763f356c TI |
5543 | snd_pcm_trigger_done(substream, substream); |
5544 | if (!hdspm->running && running) | |
5545 | hdspm_start_audio(hdspm); | |
5546 | else if (hdspm->running && !running) | |
5547 | hdspm_stop_audio(hdspm); | |
5548 | hdspm->running = running; | |
5549 | spin_unlock(&hdspm->lock); | |
5550 | ||
5551 | return 0; | |
5552 | } | |
5553 | ||
98274f07 | 5554 | static int snd_hdspm_prepare(struct snd_pcm_substream *substream) |
763f356c TI |
5555 | { |
5556 | return 0; | |
5557 | } | |
5558 | ||
0dca1793 AK |
5559 | static unsigned int period_sizes_old[] = { |
5560 | 64, 128, 256, 512, 1024, 2048, 4096 | |
5561 | }; | |
5562 | ||
5563 | static unsigned int period_sizes_new[] = { | |
5564 | 32, 64, 128, 256, 512, 1024, 2048, 4096 | |
5565 | }; | |
5566 | ||
5567 | /* RayDAT and AIO always have a buffer of 16384 samples per channel */ | |
5568 | static unsigned int raydat_aio_buffer_sizes[] = { | |
5569 | 16384 | |
5570 | }; | |
763f356c | 5571 | |
98274f07 | 5572 | static struct snd_pcm_hardware snd_hdspm_playback_subinfo = { |
763f356c TI |
5573 | .info = (SNDRV_PCM_INFO_MMAP | |
5574 | SNDRV_PCM_INFO_MMAP_VALID | | |
5575 | SNDRV_PCM_INFO_NONINTERLEAVED | | |
5576 | SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE), | |
5577 | .formats = SNDRV_PCM_FMTBIT_S32_LE, | |
5578 | .rates = (SNDRV_PCM_RATE_32000 | | |
5579 | SNDRV_PCM_RATE_44100 | | |
5580 | SNDRV_PCM_RATE_48000 | | |
5581 | SNDRV_PCM_RATE_64000 | | |
3cee5a60 RB |
5582 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | |
5583 | SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ), | |
763f356c | 5584 | .rate_min = 32000, |
3cee5a60 | 5585 | .rate_max = 192000, |
763f356c TI |
5586 | .channels_min = 1, |
5587 | .channels_max = HDSPM_MAX_CHANNELS, | |
5588 | .buffer_bytes_max = | |
5589 | HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS, | |
5590 | .period_bytes_min = (64 * 4), | |
0dca1793 | 5591 | .period_bytes_max = (4096 * 4) * HDSPM_MAX_CHANNELS, |
763f356c | 5592 | .periods_min = 2, |
0dca1793 | 5593 | .periods_max = 512, |
763f356c TI |
5594 | .fifo_size = 0 |
5595 | }; | |
5596 | ||
98274f07 | 5597 | static struct snd_pcm_hardware snd_hdspm_capture_subinfo = { |
763f356c TI |
5598 | .info = (SNDRV_PCM_INFO_MMAP | |
5599 | SNDRV_PCM_INFO_MMAP_VALID | | |
5600 | SNDRV_PCM_INFO_NONINTERLEAVED | | |
5601 | SNDRV_PCM_INFO_SYNC_START), | |
5602 | .formats = SNDRV_PCM_FMTBIT_S32_LE, | |
5603 | .rates = (SNDRV_PCM_RATE_32000 | | |
5604 | SNDRV_PCM_RATE_44100 | | |
5605 | SNDRV_PCM_RATE_48000 | | |
5606 | SNDRV_PCM_RATE_64000 | | |
3cee5a60 RB |
5607 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | |
5608 | SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000), | |
763f356c | 5609 | .rate_min = 32000, |
3cee5a60 | 5610 | .rate_max = 192000, |
763f356c TI |
5611 | .channels_min = 1, |
5612 | .channels_max = HDSPM_MAX_CHANNELS, | |
5613 | .buffer_bytes_max = | |
5614 | HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS, | |
5615 | .period_bytes_min = (64 * 4), | |
0dca1793 | 5616 | .period_bytes_max = (4096 * 4) * HDSPM_MAX_CHANNELS, |
763f356c | 5617 | .periods_min = 2, |
0dca1793 | 5618 | .periods_max = 512, |
763f356c TI |
5619 | .fifo_size = 0 |
5620 | }; | |
5621 | ||
0dca1793 AK |
5622 | static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes_old = { |
5623 | .count = ARRAY_SIZE(period_sizes_old), | |
5624 | .list = period_sizes_old, | |
5625 | .mask = 0 | |
5626 | }; | |
5627 | ||
5628 | static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes_new = { | |
5629 | .count = ARRAY_SIZE(period_sizes_new), | |
5630 | .list = period_sizes_new, | |
5631 | .mask = 0 | |
5632 | }; | |
5633 | ||
5634 | static struct snd_pcm_hw_constraint_list hw_constraints_raydat_io_buffer = { | |
5635 | .count = ARRAY_SIZE(raydat_aio_buffer_sizes), | |
5636 | .list = raydat_aio_buffer_sizes, | |
763f356c TI |
5637 | .mask = 0 |
5638 | }; | |
5639 | ||
0dca1793 AK |
5640 | static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params, |
5641 | struct snd_pcm_hw_rule *rule) | |
5642 | { | |
5643 | struct hdspm *hdspm = rule->private; | |
5644 | struct snd_interval *c = | |
5645 | hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); | |
5646 | struct snd_interval *r = | |
5647 | hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); | |
5648 | ||
5649 | if (r->min > 96000 && r->max <= 192000) { | |
5650 | struct snd_interval t = { | |
5651 | .min = hdspm->qs_in_channels, | |
5652 | .max = hdspm->qs_in_channels, | |
5653 | .integer = 1, | |
5654 | }; | |
5655 | return snd_interval_refine(c, &t); | |
5656 | } else if (r->min > 48000 && r->max <= 96000) { | |
5657 | struct snd_interval t = { | |
5658 | .min = hdspm->ds_in_channels, | |
5659 | .max = hdspm->ds_in_channels, | |
5660 | .integer = 1, | |
5661 | }; | |
5662 | return snd_interval_refine(c, &t); | |
5663 | } else if (r->max < 64000) { | |
5664 | struct snd_interval t = { | |
5665 | .min = hdspm->ss_in_channels, | |
5666 | .max = hdspm->ss_in_channels, | |
5667 | .integer = 1, | |
5668 | }; | |
5669 | return snd_interval_refine(c, &t); | |
5670 | } | |
5671 | ||
5672 | return 0; | |
5673 | } | |
763f356c | 5674 | |
0dca1793 | 5675 | static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params, |
98274f07 | 5676 | struct snd_pcm_hw_rule * rule) |
763f356c | 5677 | { |
98274f07 TI |
5678 | struct hdspm *hdspm = rule->private; |
5679 | struct snd_interval *c = | |
763f356c | 5680 | hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); |
98274f07 | 5681 | struct snd_interval *r = |
763f356c TI |
5682 | hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); |
5683 | ||
0dca1793 AK |
5684 | if (r->min > 96000 && r->max <= 192000) { |
5685 | struct snd_interval t = { | |
5686 | .min = hdspm->qs_out_channels, | |
5687 | .max = hdspm->qs_out_channels, | |
5688 | .integer = 1, | |
5689 | }; | |
5690 | return snd_interval_refine(c, &t); | |
5691 | } else if (r->min > 48000 && r->max <= 96000) { | |
98274f07 | 5692 | struct snd_interval t = { |
0dca1793 AK |
5693 | .min = hdspm->ds_out_channels, |
5694 | .max = hdspm->ds_out_channels, | |
763f356c TI |
5695 | .integer = 1, |
5696 | }; | |
5697 | return snd_interval_refine(c, &t); | |
5698 | } else if (r->max < 64000) { | |
98274f07 | 5699 | struct snd_interval t = { |
0dca1793 AK |
5700 | .min = hdspm->ss_out_channels, |
5701 | .max = hdspm->ss_out_channels, | |
763f356c TI |
5702 | .integer = 1, |
5703 | }; | |
5704 | return snd_interval_refine(c, &t); | |
0dca1793 | 5705 | } else { |
763f356c TI |
5706 | } |
5707 | return 0; | |
5708 | } | |
5709 | ||
0dca1793 | 5710 | static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params, |
98274f07 | 5711 | struct snd_pcm_hw_rule * rule) |
763f356c | 5712 | { |
98274f07 TI |
5713 | struct hdspm *hdspm = rule->private; |
5714 | struct snd_interval *c = | |
763f356c | 5715 | hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); |
98274f07 | 5716 | struct snd_interval *r = |
763f356c TI |
5717 | hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); |
5718 | ||
0dca1793 | 5719 | if (c->min >= hdspm->ss_in_channels) { |
98274f07 | 5720 | struct snd_interval t = { |
763f356c TI |
5721 | .min = 32000, |
5722 | .max = 48000, | |
5723 | .integer = 1, | |
5724 | }; | |
5725 | return snd_interval_refine(r, &t); | |
0dca1793 AK |
5726 | } else if (c->max <= hdspm->qs_in_channels) { |
5727 | struct snd_interval t = { | |
5728 | .min = 128000, | |
5729 | .max = 192000, | |
5730 | .integer = 1, | |
5731 | }; | |
5732 | return snd_interval_refine(r, &t); | |
5733 | } else if (c->max <= hdspm->ds_in_channels) { | |
98274f07 | 5734 | struct snd_interval t = { |
763f356c TI |
5735 | .min = 64000, |
5736 | .max = 96000, | |
5737 | .integer = 1, | |
5738 | }; | |
0dca1793 AK |
5739 | return snd_interval_refine(r, &t); |
5740 | } | |
5741 | ||
5742 | return 0; | |
5743 | } | |
5744 | static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params, | |
5745 | struct snd_pcm_hw_rule *rule) | |
5746 | { | |
5747 | struct hdspm *hdspm = rule->private; | |
5748 | struct snd_interval *c = | |
5749 | hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); | |
5750 | struct snd_interval *r = | |
5751 | hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); | |
763f356c | 5752 | |
0dca1793 AK |
5753 | if (c->min >= hdspm->ss_out_channels) { |
5754 | struct snd_interval t = { | |
5755 | .min = 32000, | |
5756 | .max = 48000, | |
5757 | .integer = 1, | |
5758 | }; | |
5759 | return snd_interval_refine(r, &t); | |
5760 | } else if (c->max <= hdspm->qs_out_channels) { | |
5761 | struct snd_interval t = { | |
5762 | .min = 128000, | |
5763 | .max = 192000, | |
5764 | .integer = 1, | |
5765 | }; | |
5766 | return snd_interval_refine(r, &t); | |
5767 | } else if (c->max <= hdspm->ds_out_channels) { | |
5768 | struct snd_interval t = { | |
5769 | .min = 64000, | |
5770 | .max = 96000, | |
5771 | .integer = 1, | |
5772 | }; | |
763f356c TI |
5773 | return snd_interval_refine(r, &t); |
5774 | } | |
0dca1793 | 5775 | |
763f356c TI |
5776 | return 0; |
5777 | } | |
5778 | ||
0dca1793 | 5779 | static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params, |
ffb2c3c0 RB |
5780 | struct snd_pcm_hw_rule *rule) |
5781 | { | |
5782 | unsigned int list[3]; | |
5783 | struct hdspm *hdspm = rule->private; | |
5784 | struct snd_interval *c = hw_param_interval(params, | |
5785 | SNDRV_PCM_HW_PARAM_CHANNELS); | |
0dca1793 AK |
5786 | |
5787 | list[0] = hdspm->qs_in_channels; | |
5788 | list[1] = hdspm->ds_in_channels; | |
5789 | list[2] = hdspm->ss_in_channels; | |
5790 | return snd_interval_list(c, 3, list, 0); | |
5791 | } | |
5792 | ||
5793 | static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params, | |
5794 | struct snd_pcm_hw_rule *rule) | |
5795 | { | |
5796 | unsigned int list[3]; | |
5797 | struct hdspm *hdspm = rule->private; | |
5798 | struct snd_interval *c = hw_param_interval(params, | |
5799 | SNDRV_PCM_HW_PARAM_CHANNELS); | |
5800 | ||
5801 | list[0] = hdspm->qs_out_channels; | |
5802 | list[1] = hdspm->ds_out_channels; | |
5803 | list[2] = hdspm->ss_out_channels; | |
5804 | return snd_interval_list(c, 3, list, 0); | |
ffb2c3c0 RB |
5805 | } |
5806 | ||
5807 | ||
ef5fa1a4 TI |
5808 | static unsigned int hdspm_aes32_sample_rates[] = { |
5809 | 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 | |
5810 | }; | |
ffb2c3c0 | 5811 | |
ef5fa1a4 TI |
5812 | static struct snd_pcm_hw_constraint_list |
5813 | hdspm_hw_constraints_aes32_sample_rates = { | |
ffb2c3c0 RB |
5814 | .count = ARRAY_SIZE(hdspm_aes32_sample_rates), |
5815 | .list = hdspm_aes32_sample_rates, | |
5816 | .mask = 0 | |
5817 | }; | |
5818 | ||
98274f07 | 5819 | static int snd_hdspm_playback_open(struct snd_pcm_substream *substream) |
763f356c | 5820 | { |
98274f07 TI |
5821 | struct hdspm *hdspm = snd_pcm_substream_chip(substream); |
5822 | struct snd_pcm_runtime *runtime = substream->runtime; | |
763f356c | 5823 | |
763f356c TI |
5824 | spin_lock_irq(&hdspm->lock); |
5825 | ||
5826 | snd_pcm_set_sync(substream); | |
5827 | ||
0dca1793 | 5828 | |
763f356c TI |
5829 | runtime->hw = snd_hdspm_playback_subinfo; |
5830 | ||
5831 | if (hdspm->capture_substream == NULL) | |
5832 | hdspm_stop_audio(hdspm); | |
5833 | ||
5834 | hdspm->playback_pid = current->pid; | |
5835 | hdspm->playback_substream = substream; | |
5836 | ||
5837 | spin_unlock_irq(&hdspm->lock); | |
5838 | ||
5839 | snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); | |
5840 | ||
0dca1793 AK |
5841 | switch (hdspm->io_type) { |
5842 | case AIO: | |
5843 | case RayDAT: | |
5844 | snd_pcm_hw_constraint_list(runtime, 0, | |
5845 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE, | |
5846 | &hw_constraints_period_sizes_new); | |
5847 | snd_pcm_hw_constraint_list(runtime, 0, | |
5848 | SNDRV_PCM_HW_PARAM_BUFFER_SIZE, | |
5849 | &hw_constraints_raydat_io_buffer); | |
5850 | ||
5851 | break; | |
5852 | ||
5853 | default: | |
5854 | snd_pcm_hw_constraint_list(runtime, 0, | |
5855 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE, | |
5856 | &hw_constraints_period_sizes_old); | |
5857 | } | |
763f356c | 5858 | |
0dca1793 | 5859 | if (AES32 == hdspm->io_type) { |
ffb2c3c0 RB |
5860 | snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, |
5861 | &hdspm_hw_constraints_aes32_sample_rates); | |
5862 | } else { | |
ffb2c3c0 | 5863 | snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, |
0dca1793 AK |
5864 | snd_hdspm_hw_rule_rate_out_channels, hdspm, |
5865 | SNDRV_PCM_HW_PARAM_CHANNELS, -1); | |
ffb2c3c0 | 5866 | } |
88fabbfc AK |
5867 | |
5868 | snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, | |
5869 | snd_hdspm_hw_rule_out_channels, hdspm, | |
5870 | SNDRV_PCM_HW_PARAM_CHANNELS, -1); | |
5871 | ||
5872 | snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, | |
5873 | snd_hdspm_hw_rule_out_channels_rate, hdspm, | |
5874 | SNDRV_PCM_HW_PARAM_RATE, -1); | |
5875 | ||
763f356c TI |
5876 | return 0; |
5877 | } | |
5878 | ||
98274f07 | 5879 | static int snd_hdspm_playback_release(struct snd_pcm_substream *substream) |
763f356c | 5880 | { |
98274f07 | 5881 | struct hdspm *hdspm = snd_pcm_substream_chip(substream); |
763f356c TI |
5882 | |
5883 | spin_lock_irq(&hdspm->lock); | |
5884 | ||
5885 | hdspm->playback_pid = -1; | |
5886 | hdspm->playback_substream = NULL; | |
5887 | ||
5888 | spin_unlock_irq(&hdspm->lock); | |
5889 | ||
5890 | return 0; | |
5891 | } | |
5892 | ||
5893 | ||
98274f07 | 5894 | static int snd_hdspm_capture_open(struct snd_pcm_substream *substream) |
763f356c | 5895 | { |
98274f07 TI |
5896 | struct hdspm *hdspm = snd_pcm_substream_chip(substream); |
5897 | struct snd_pcm_runtime *runtime = substream->runtime; | |
763f356c TI |
5898 | |
5899 | spin_lock_irq(&hdspm->lock); | |
5900 | snd_pcm_set_sync(substream); | |
5901 | runtime->hw = snd_hdspm_capture_subinfo; | |
5902 | ||
5903 | if (hdspm->playback_substream == NULL) | |
5904 | hdspm_stop_audio(hdspm); | |
5905 | ||
5906 | hdspm->capture_pid = current->pid; | |
5907 | hdspm->capture_substream = substream; | |
5908 | ||
5909 | spin_unlock_irq(&hdspm->lock); | |
5910 | ||
5911 | snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); | |
0dca1793 AK |
5912 | switch (hdspm->io_type) { |
5913 | case AIO: | |
5914 | case RayDAT: | |
5915 | snd_pcm_hw_constraint_list(runtime, 0, | |
5916 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE, | |
5917 | &hw_constraints_period_sizes_new); | |
5918 | snd_pcm_hw_constraint_list(runtime, 0, | |
5919 | SNDRV_PCM_HW_PARAM_BUFFER_SIZE, | |
5920 | &hw_constraints_raydat_io_buffer); | |
5921 | break; | |
5922 | ||
5923 | default: | |
5924 | snd_pcm_hw_constraint_list(runtime, 0, | |
5925 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE, | |
5926 | &hw_constraints_period_sizes_old); | |
5927 | } | |
5928 | ||
5929 | if (AES32 == hdspm->io_type) { | |
ffb2c3c0 RB |
5930 | snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, |
5931 | &hdspm_hw_constraints_aes32_sample_rates); | |
5932 | } else { | |
ffb2c3c0 | 5933 | snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, |
88fabbfc AK |
5934 | snd_hdspm_hw_rule_rate_in_channels, hdspm, |
5935 | SNDRV_PCM_HW_PARAM_CHANNELS, -1); | |
ffb2c3c0 | 5936 | } |
88fabbfc AK |
5937 | |
5938 | snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, | |
5939 | snd_hdspm_hw_rule_in_channels, hdspm, | |
5940 | SNDRV_PCM_HW_PARAM_CHANNELS, -1); | |
5941 | ||
5942 | snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, | |
5943 | snd_hdspm_hw_rule_in_channels_rate, hdspm, | |
5944 | SNDRV_PCM_HW_PARAM_RATE, -1); | |
5945 | ||
763f356c TI |
5946 | return 0; |
5947 | } | |
5948 | ||
98274f07 | 5949 | static int snd_hdspm_capture_release(struct snd_pcm_substream *substream) |
763f356c | 5950 | { |
98274f07 | 5951 | struct hdspm *hdspm = snd_pcm_substream_chip(substream); |
763f356c TI |
5952 | |
5953 | spin_lock_irq(&hdspm->lock); | |
5954 | ||
5955 | hdspm->capture_pid = -1; | |
5956 | hdspm->capture_substream = NULL; | |
5957 | ||
5958 | spin_unlock_irq(&hdspm->lock); | |
5959 | return 0; | |
5960 | } | |
5961 | ||
0dca1793 AK |
5962 | static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file) |
5963 | { | |
5964 | /* we have nothing to initialize but the call is required */ | |
5965 | return 0; | |
5966 | } | |
5967 | ||
5968 | static inline int copy_u32_le(void __user *dest, void __iomem *src) | |
5969 | { | |
5970 | u32 val = readl(src); | |
5971 | return copy_to_user(dest, &val, 4); | |
5972 | } | |
5973 | ||
5974 | static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, | |
5975 | unsigned int cmd, unsigned long __user arg) | |
763f356c | 5976 | { |
0dca1793 | 5977 | void __user *argp = (void __user *)arg; |
ef5fa1a4 | 5978 | struct hdspm *hdspm = hw->private_data; |
98274f07 | 5979 | struct hdspm_mixer_ioctl mixer; |
0dca1793 AK |
5980 | struct hdspm_config info; |
5981 | struct hdspm_status status; | |
98274f07 | 5982 | struct hdspm_version hdspm_version; |
730a5865 | 5983 | struct hdspm_peak_rms *levels; |
0dca1793 AK |
5984 | struct hdspm_ltc ltc; |
5985 | unsigned int statusregister; | |
5986 | long unsigned int s; | |
5987 | int i = 0; | |
763f356c TI |
5988 | |
5989 | switch (cmd) { | |
5990 | ||
763f356c | 5991 | case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS: |
730a5865 | 5992 | levels = &hdspm->peak_rms; |
0dca1793 | 5993 | for (i = 0; i < HDSPM_MAX_CHANNELS; i++) { |
730a5865 | 5994 | levels->input_peaks[i] = |
0dca1793 AK |
5995 | readl(hdspm->iobase + |
5996 | HDSPM_MADI_INPUT_PEAK + i*4); | |
730a5865 | 5997 | levels->playback_peaks[i] = |
0dca1793 AK |
5998 | readl(hdspm->iobase + |
5999 | HDSPM_MADI_PLAYBACK_PEAK + i*4); | |
730a5865 | 6000 | levels->output_peaks[i] = |
0dca1793 AK |
6001 | readl(hdspm->iobase + |
6002 | HDSPM_MADI_OUTPUT_PEAK + i*4); | |
6003 | ||
730a5865 | 6004 | levels->input_rms[i] = |
0dca1793 AK |
6005 | ((uint64_t) readl(hdspm->iobase + |
6006 | HDSPM_MADI_INPUT_RMS_H + i*4) << 32) | | |
6007 | (uint64_t) readl(hdspm->iobase + | |
6008 | HDSPM_MADI_INPUT_RMS_L + i*4); | |
730a5865 | 6009 | levels->playback_rms[i] = |
0dca1793 AK |
6010 | ((uint64_t)readl(hdspm->iobase + |
6011 | HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) | | |
6012 | (uint64_t)readl(hdspm->iobase + | |
6013 | HDSPM_MADI_PLAYBACK_RMS_L + i*4); | |
730a5865 | 6014 | levels->output_rms[i] = |
0dca1793 AK |
6015 | ((uint64_t)readl(hdspm->iobase + |
6016 | HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) | | |
6017 | (uint64_t)readl(hdspm->iobase + | |
6018 | HDSPM_MADI_OUTPUT_RMS_L + i*4); | |
6019 | } | |
6020 | ||
6021 | if (hdspm->system_sample_rate > 96000) { | |
730a5865 | 6022 | levels->speed = qs; |
0dca1793 | 6023 | } else if (hdspm->system_sample_rate > 48000) { |
730a5865 | 6024 | levels->speed = ds; |
0dca1793 | 6025 | } else { |
730a5865 | 6026 | levels->speed = ss; |
0dca1793 | 6027 | } |
730a5865 | 6028 | levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2); |
0dca1793 | 6029 | |
730a5865 | 6030 | s = copy_to_user(argp, levels, sizeof(struct hdspm_peak_rms)); |
0dca1793 AK |
6031 | if (0 != s) { |
6032 | /* snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu | |
6033 | [Levels]\n", sizeof(struct hdspm_peak_rms), s); | |
6034 | */ | |
763f356c | 6035 | return -EFAULT; |
0dca1793 AK |
6036 | } |
6037 | break; | |
6038 | ||
6039 | case SNDRV_HDSPM_IOCTL_GET_LTC: | |
6040 | ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO); | |
6041 | i = hdspm_read(hdspm, HDSPM_RD_TCO + 4); | |
6042 | if (i & HDSPM_TCO1_LTC_Input_valid) { | |
6043 | switch (i & (HDSPM_TCO1_LTC_Format_LSB | | |
6044 | HDSPM_TCO1_LTC_Format_MSB)) { | |
6045 | case 0: | |
6046 | ltc.format = fps_24; | |
6047 | break; | |
6048 | case HDSPM_TCO1_LTC_Format_LSB: | |
6049 | ltc.format = fps_25; | |
6050 | break; | |
6051 | case HDSPM_TCO1_LTC_Format_MSB: | |
6052 | ltc.format = fps_2997; | |
6053 | break; | |
6054 | default: | |
6055 | ltc.format = 30; | |
6056 | break; | |
6057 | } | |
6058 | if (i & HDSPM_TCO1_set_drop_frame_flag) { | |
6059 | ltc.frame = drop_frame; | |
6060 | } else { | |
6061 | ltc.frame = full_frame; | |
6062 | } | |
6063 | } else { | |
6064 | ltc.format = format_invalid; | |
6065 | ltc.frame = frame_invalid; | |
6066 | } | |
6067 | if (i & HDSPM_TCO1_Video_Input_Format_NTSC) { | |
6068 | ltc.input_format = ntsc; | |
6069 | } else if (i & HDSPM_TCO1_Video_Input_Format_PAL) { | |
6070 | ltc.input_format = pal; | |
6071 | } else { | |
6072 | ltc.input_format = no_video; | |
6073 | } | |
6074 | ||
6075 | s = copy_to_user(argp, <c, sizeof(struct hdspm_ltc)); | |
6076 | if (0 != s) { | |
6077 | /* | |
6078 | snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */ | |
763f356c | 6079 | return -EFAULT; |
0dca1793 | 6080 | } |
763f356c TI |
6081 | |
6082 | break; | |
763f356c | 6083 | |
0dca1793 | 6084 | case SNDRV_HDSPM_IOCTL_GET_CONFIG: |
763f356c | 6085 | |
4ab69a2b | 6086 | memset(&info, 0, sizeof(info)); |
763f356c | 6087 | spin_lock_irq(&hdspm->lock); |
ef5fa1a4 TI |
6088 | info.pref_sync_ref = hdspm_pref_sync_ref(hdspm); |
6089 | info.wordclock_sync_check = hdspm_wc_sync_check(hdspm); | |
763f356c TI |
6090 | |
6091 | info.system_sample_rate = hdspm->system_sample_rate; | |
6092 | info.autosync_sample_rate = | |
0dca1793 | 6093 | hdspm_external_sample_rate(hdspm); |
ef5fa1a4 TI |
6094 | info.system_clock_mode = hdspm_system_clock_mode(hdspm); |
6095 | info.clock_source = hdspm_clock_source(hdspm); | |
6096 | info.autosync_ref = hdspm_autosync_ref(hdspm); | |
6097 | info.line_out = hdspm_line_out(hdspm); | |
763f356c TI |
6098 | info.passthru = 0; |
6099 | spin_unlock_irq(&hdspm->lock); | |
6100 | if (copy_to_user((void __user *) arg, &info, sizeof(info))) | |
6101 | return -EFAULT; | |
6102 | break; | |
6103 | ||
0dca1793 AK |
6104 | case SNDRV_HDSPM_IOCTL_GET_STATUS: |
6105 | status.card_type = hdspm->io_type; | |
6106 | ||
6107 | status.autosync_source = hdspm_autosync_ref(hdspm); | |
6108 | ||
6109 | status.card_clock = 110069313433624ULL; | |
6110 | status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); | |
6111 | ||
6112 | switch (hdspm->io_type) { | |
6113 | case MADI: | |
6114 | case MADIface: | |
6115 | status.card_specific.madi.sync_wc = | |
6116 | hdspm_wc_sync_check(hdspm); | |
6117 | status.card_specific.madi.sync_madi = | |
6118 | hdspm_madi_sync_check(hdspm); | |
6119 | status.card_specific.madi.sync_tco = | |
6120 | hdspm_tco_sync_check(hdspm); | |
6121 | status.card_specific.madi.sync_in = | |
6122 | hdspm_sync_in_sync_check(hdspm); | |
6123 | ||
6124 | statusregister = | |
6125 | hdspm_read(hdspm, HDSPM_statusRegister); | |
6126 | status.card_specific.madi.madi_input = | |
6127 | (statusregister & HDSPM_AB_int) ? 1 : 0; | |
6128 | status.card_specific.madi.channel_format = | |
6129 | (statusregister & HDSPM_TX_64ch) ? 1 : 0; | |
6130 | /* TODO: Mac driver sets it when f_s>48kHz */ | |
6131 | status.card_specific.madi.frame_format = 0; | |
6132 | ||
6133 | default: | |
6134 | break; | |
6135 | } | |
6136 | ||
6137 | if (copy_to_user((void __user *) arg, &status, sizeof(status))) | |
6138 | return -EFAULT; | |
6139 | ||
6140 | ||
6141 | break; | |
6142 | ||
763f356c | 6143 | case SNDRV_HDSPM_IOCTL_GET_VERSION: |
0dca1793 AK |
6144 | hdspm_version.card_type = hdspm->io_type; |
6145 | strncpy(hdspm_version.cardname, hdspm->card_name, | |
6146 | sizeof(hdspm_version.cardname)); | |
6147 | hdspm_version.serial = (hdspm_read(hdspm, | |
6148 | HDSPM_midiStatusIn0)>>8) & 0xFFFFFF; | |
763f356c | 6149 | hdspm_version.firmware_rev = hdspm->firmware_rev; |
0dca1793 AK |
6150 | hdspm_version.addons = 0; |
6151 | if (hdspm->tco) | |
6152 | hdspm_version.addons |= HDSPM_ADDON_TCO; | |
6153 | ||
763f356c | 6154 | if (copy_to_user((void __user *) arg, &hdspm_version, |
0dca1793 | 6155 | sizeof(hdspm_version))) |
763f356c TI |
6156 | return -EFAULT; |
6157 | break; | |
6158 | ||
6159 | case SNDRV_HDSPM_IOCTL_GET_MIXER: | |
6160 | if (copy_from_user(&mixer, (void __user *)arg, sizeof(mixer))) | |
6161 | return -EFAULT; | |
ef5fa1a4 | 6162 | if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer, |
0dca1793 | 6163 | sizeof(struct hdspm_mixer))) |
763f356c TI |
6164 | return -EFAULT; |
6165 | break; | |
6166 | ||
6167 | default: | |
6168 | return -EINVAL; | |
6169 | } | |
6170 | return 0; | |
6171 | } | |
6172 | ||
98274f07 | 6173 | static struct snd_pcm_ops snd_hdspm_playback_ops = { |
763f356c TI |
6174 | .open = snd_hdspm_playback_open, |
6175 | .close = snd_hdspm_playback_release, | |
6176 | .ioctl = snd_hdspm_ioctl, | |
6177 | .hw_params = snd_hdspm_hw_params, | |
6178 | .hw_free = snd_hdspm_hw_free, | |
6179 | .prepare = snd_hdspm_prepare, | |
6180 | .trigger = snd_hdspm_trigger, | |
6181 | .pointer = snd_hdspm_hw_pointer, | |
763f356c TI |
6182 | .page = snd_pcm_sgbuf_ops_page, |
6183 | }; | |
6184 | ||
98274f07 | 6185 | static struct snd_pcm_ops snd_hdspm_capture_ops = { |
763f356c TI |
6186 | .open = snd_hdspm_capture_open, |
6187 | .close = snd_hdspm_capture_release, | |
6188 | .ioctl = snd_hdspm_ioctl, | |
6189 | .hw_params = snd_hdspm_hw_params, | |
6190 | .hw_free = snd_hdspm_hw_free, | |
6191 | .prepare = snd_hdspm_prepare, | |
6192 | .trigger = snd_hdspm_trigger, | |
6193 | .pointer = snd_hdspm_hw_pointer, | |
763f356c TI |
6194 | .page = snd_pcm_sgbuf_ops_page, |
6195 | }; | |
6196 | ||
98274f07 TI |
6197 | static int __devinit snd_hdspm_create_hwdep(struct snd_card *card, |
6198 | struct hdspm * hdspm) | |
763f356c | 6199 | { |
98274f07 | 6200 | struct snd_hwdep *hw; |
763f356c TI |
6201 | int err; |
6202 | ||
ef5fa1a4 TI |
6203 | err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw); |
6204 | if (err < 0) | |
763f356c TI |
6205 | return err; |
6206 | ||
6207 | hdspm->hwdep = hw; | |
6208 | hw->private_data = hdspm; | |
6209 | strcpy(hw->name, "HDSPM hwdep interface"); | |
6210 | ||
0dca1793 | 6211 | hw->ops.open = snd_hdspm_hwdep_dummy_op; |
763f356c | 6212 | hw->ops.ioctl = snd_hdspm_hwdep_ioctl; |
0dca1793 | 6213 | hw->ops.release = snd_hdspm_hwdep_dummy_op; |
763f356c TI |
6214 | |
6215 | return 0; | |
6216 | } | |
6217 | ||
6218 | ||
6219 | /*------------------------------------------------------------ | |
0dca1793 | 6220 | memory interface |
763f356c | 6221 | ------------------------------------------------------------*/ |
0dca1793 | 6222 | static int __devinit snd_hdspm_preallocate_memory(struct hdspm *hdspm) |
763f356c TI |
6223 | { |
6224 | int err; | |
98274f07 | 6225 | struct snd_pcm *pcm; |
763f356c TI |
6226 | size_t wanted; |
6227 | ||
6228 | pcm = hdspm->pcm; | |
6229 | ||
3cee5a60 | 6230 | wanted = HDSPM_DMA_AREA_BYTES; |
763f356c | 6231 | |
ef5fa1a4 | 6232 | err = |
763f356c | 6233 | snd_pcm_lib_preallocate_pages_for_all(pcm, |
0dca1793 | 6234 | SNDRV_DMA_TYPE_DEV_SG, |
763f356c TI |
6235 | snd_dma_pci_data(hdspm->pci), |
6236 | wanted, | |
ef5fa1a4 TI |
6237 | wanted); |
6238 | if (err < 0) { | |
e2eba3e7 | 6239 | snd_printdd("Could not preallocate %zd Bytes\n", wanted); |
763f356c TI |
6240 | |
6241 | return err; | |
6242 | } else | |
e2eba3e7 | 6243 | snd_printdd(" Preallocated %zd Bytes\n", wanted); |
763f356c TI |
6244 | |
6245 | return 0; | |
6246 | } | |
6247 | ||
0dca1793 AK |
6248 | |
6249 | static void hdspm_set_sgbuf(struct hdspm *hdspm, | |
77a23f26 | 6250 | struct snd_pcm_substream *substream, |
763f356c TI |
6251 | unsigned int reg, int channels) |
6252 | { | |
6253 | int i; | |
0dca1793 AK |
6254 | |
6255 | /* continuous memory segment */ | |
763f356c TI |
6256 | for (i = 0; i < (channels * 16); i++) |
6257 | hdspm_write(hdspm, reg + 4 * i, | |
0dca1793 | 6258 | snd_pcm_sgbuf_get_addr(substream, 4096 * i)); |
763f356c TI |
6259 | } |
6260 | ||
0dca1793 | 6261 | |
763f356c | 6262 | /* ------------- ALSA Devices ---------------------------- */ |
98274f07 | 6263 | static int __devinit snd_hdspm_create_pcm(struct snd_card *card, |
0dca1793 | 6264 | struct hdspm *hdspm) |
763f356c | 6265 | { |
98274f07 | 6266 | struct snd_pcm *pcm; |
763f356c TI |
6267 | int err; |
6268 | ||
ef5fa1a4 TI |
6269 | err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm); |
6270 | if (err < 0) | |
763f356c TI |
6271 | return err; |
6272 | ||
6273 | hdspm->pcm = pcm; | |
6274 | pcm->private_data = hdspm; | |
6275 | strcpy(pcm->name, hdspm->card_name); | |
6276 | ||
6277 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, | |
6278 | &snd_hdspm_playback_ops); | |
6279 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, | |
6280 | &snd_hdspm_capture_ops); | |
6281 | ||
6282 | pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; | |
6283 | ||
ef5fa1a4 TI |
6284 | err = snd_hdspm_preallocate_memory(hdspm); |
6285 | if (err < 0) | |
763f356c TI |
6286 | return err; |
6287 | ||
6288 | return 0; | |
6289 | } | |
6290 | ||
98274f07 | 6291 | static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm) |
763f356c TI |
6292 | { |
6293 | snd_hdspm_flush_midi_input(hdspm, 0); | |
6294 | snd_hdspm_flush_midi_input(hdspm, 1); | |
6295 | } | |
6296 | ||
98274f07 TI |
6297 | static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card, |
6298 | struct hdspm * hdspm) | |
763f356c | 6299 | { |
0dca1793 | 6300 | int err, i; |
763f356c TI |
6301 | |
6302 | snd_printdd("Create card...\n"); | |
ef5fa1a4 TI |
6303 | err = snd_hdspm_create_pcm(card, hdspm); |
6304 | if (err < 0) | |
763f356c TI |
6305 | return err; |
6306 | ||
0dca1793 AK |
6307 | i = 0; |
6308 | while (i < hdspm->midiPorts) { | |
6309 | err = snd_hdspm_create_midi(card, hdspm, i); | |
6310 | if (err < 0) { | |
6311 | return err; | |
6312 | } | |
6313 | i++; | |
6314 | } | |
763f356c | 6315 | |
ef5fa1a4 TI |
6316 | err = snd_hdspm_create_controls(card, hdspm); |
6317 | if (err < 0) | |
763f356c TI |
6318 | return err; |
6319 | ||
ef5fa1a4 TI |
6320 | err = snd_hdspm_create_hwdep(card, hdspm); |
6321 | if (err < 0) | |
763f356c TI |
6322 | return err; |
6323 | ||
6324 | snd_printdd("proc init...\n"); | |
6325 | snd_hdspm_proc_init(hdspm); | |
6326 | ||
6327 | hdspm->system_sample_rate = -1; | |
6328 | hdspm->last_external_sample_rate = -1; | |
6329 | hdspm->last_internal_sample_rate = -1; | |
6330 | hdspm->playback_pid = -1; | |
6331 | hdspm->capture_pid = -1; | |
6332 | hdspm->capture_substream = NULL; | |
6333 | hdspm->playback_substream = NULL; | |
6334 | ||
6335 | snd_printdd("Set defaults...\n"); | |
ef5fa1a4 TI |
6336 | err = snd_hdspm_set_defaults(hdspm); |
6337 | if (err < 0) | |
763f356c TI |
6338 | return err; |
6339 | ||
6340 | snd_printdd("Update mixer controls...\n"); | |
6341 | hdspm_update_simple_mixer_controls(hdspm); | |
6342 | ||
6343 | snd_printdd("Initializeing complete ???\n"); | |
6344 | ||
ef5fa1a4 TI |
6345 | err = snd_card_register(card); |
6346 | if (err < 0) { | |
763f356c TI |
6347 | snd_printk(KERN_ERR "HDSPM: error registering card\n"); |
6348 | return err; | |
6349 | } | |
6350 | ||
6351 | snd_printdd("... yes now\n"); | |
6352 | ||
6353 | return 0; | |
6354 | } | |
6355 | ||
ef5fa1a4 | 6356 | static int __devinit snd_hdspm_create(struct snd_card *card, |
0dca1793 AK |
6357 | struct hdspm *hdspm) { |
6358 | ||
763f356c TI |
6359 | struct pci_dev *pci = hdspm->pci; |
6360 | int err; | |
763f356c TI |
6361 | unsigned long io_extent; |
6362 | ||
6363 | hdspm->irq = -1; | |
763f356c TI |
6364 | hdspm->card = card; |
6365 | ||
6366 | spin_lock_init(&hdspm->lock); | |
6367 | ||
763f356c | 6368 | pci_read_config_word(hdspm->pci, |
0dca1793 | 6369 | PCI_CLASS_REVISION, &hdspm->firmware_rev); |
3cee5a60 | 6370 | |
763f356c | 6371 | strcpy(card->mixername, "Xilinx FPGA"); |
0dca1793 AK |
6372 | strcpy(card->driver, "HDSPM"); |
6373 | ||
6374 | switch (hdspm->firmware_rev) { | |
6375 | case HDSPM_MADI_REV: | |
6376 | hdspm->io_type = MADI; | |
6377 | hdspm->card_name = "RME MADI"; | |
6378 | hdspm->midiPorts = 3; | |
6379 | break; | |
6380 | case HDSPM_RAYDAT_REV: | |
6381 | hdspm->io_type = RayDAT; | |
6382 | hdspm->card_name = "RME RayDAT"; | |
6383 | hdspm->midiPorts = 2; | |
6384 | break; | |
6385 | case HDSPM_AIO_REV: | |
6386 | hdspm->io_type = AIO; | |
6387 | hdspm->card_name = "RME AIO"; | |
6388 | hdspm->midiPorts = 1; | |
6389 | break; | |
6390 | case HDSPM_MADIFACE_REV: | |
6391 | hdspm->io_type = MADIface; | |
6392 | hdspm->card_name = "RME MADIface"; | |
6393 | hdspm->midiPorts = 1; | |
6394 | break; | |
6395 | case HDSPM_AES_REV: | |
6396 | hdspm->io_type = AES32; | |
6397 | hdspm->card_name = "RME AES32"; | |
6398 | hdspm->midiPorts = 2; | |
6399 | break; | |
3cee5a60 | 6400 | } |
763f356c | 6401 | |
ef5fa1a4 TI |
6402 | err = pci_enable_device(pci); |
6403 | if (err < 0) | |
763f356c TI |
6404 | return err; |
6405 | ||
6406 | pci_set_master(hdspm->pci); | |
6407 | ||
ef5fa1a4 TI |
6408 | err = pci_request_regions(pci, "hdspm"); |
6409 | if (err < 0) | |
763f356c TI |
6410 | return err; |
6411 | ||
6412 | hdspm->port = pci_resource_start(pci, 0); | |
6413 | io_extent = pci_resource_len(pci, 0); | |
6414 | ||
6415 | snd_printdd("grabbed memory region 0x%lx-0x%lx\n", | |
0dca1793 | 6416 | hdspm->port, hdspm->port + io_extent - 1); |
763f356c | 6417 | |
ef5fa1a4 TI |
6418 | hdspm->iobase = ioremap_nocache(hdspm->port, io_extent); |
6419 | if (!hdspm->iobase) { | |
6420 | snd_printk(KERN_ERR "HDSPM: " | |
0dca1793 AK |
6421 | "unable to remap region 0x%lx-0x%lx\n", |
6422 | hdspm->port, hdspm->port + io_extent - 1); | |
763f356c TI |
6423 | return -EBUSY; |
6424 | } | |
6425 | snd_printdd("remapped region (0x%lx) 0x%lx-0x%lx\n", | |
0dca1793 AK |
6426 | (unsigned long)hdspm->iobase, hdspm->port, |
6427 | hdspm->port + io_extent - 1); | |
763f356c TI |
6428 | |
6429 | if (request_irq(pci->irq, snd_hdspm_interrupt, | |
0dca1793 | 6430 | IRQF_SHARED, "hdspm", hdspm)) { |
763f356c TI |
6431 | snd_printk(KERN_ERR "HDSPM: unable to use IRQ %d\n", pci->irq); |
6432 | return -EBUSY; | |
6433 | } | |
6434 | ||
6435 | snd_printdd("use IRQ %d\n", pci->irq); | |
6436 | ||
6437 | hdspm->irq = pci->irq; | |
763f356c | 6438 | |
e2eba3e7 | 6439 | snd_printdd("kmalloc Mixer memory of %zd Bytes\n", |
0dca1793 | 6440 | sizeof(struct hdspm_mixer)); |
ef5fa1a4 TI |
6441 | hdspm->mixer = kzalloc(sizeof(struct hdspm_mixer), GFP_KERNEL); |
6442 | if (!hdspm->mixer) { | |
6443 | snd_printk(KERN_ERR "HDSPM: " | |
0dca1793 AK |
6444 | "unable to kmalloc Mixer memory of %d Bytes\n", |
6445 | (int)sizeof(struct hdspm_mixer)); | |
763f356c TI |
6446 | return err; |
6447 | } | |
6448 | ||
0dca1793 AK |
6449 | hdspm->port_names_in = NULL; |
6450 | hdspm->port_names_out = NULL; | |
6451 | ||
6452 | switch (hdspm->io_type) { | |
6453 | case AES32: | |
d2d10a21 AK |
6454 | hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS; |
6455 | hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS; | |
6456 | hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS; | |
432d2500 AK |
6457 | |
6458 | hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = | |
6459 | channel_map_aes32; | |
6460 | hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = | |
6461 | channel_map_aes32; | |
6462 | hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = | |
6463 | channel_map_aes32; | |
6464 | hdspm->port_names_in_ss = hdspm->port_names_out_ss = | |
6465 | texts_ports_aes32; | |
6466 | hdspm->port_names_in_ds = hdspm->port_names_out_ds = | |
6467 | texts_ports_aes32; | |
6468 | hdspm->port_names_in_qs = hdspm->port_names_out_qs = | |
6469 | texts_ports_aes32; | |
6470 | ||
d2d10a21 AK |
6471 | hdspm->max_channels_out = hdspm->max_channels_in = |
6472 | AES32_CHANNELS; | |
432d2500 AK |
6473 | hdspm->port_names_in = hdspm->port_names_out = |
6474 | texts_ports_aes32; | |
6475 | hdspm->channel_map_in = hdspm->channel_map_out = | |
6476 | channel_map_aes32; | |
6477 | ||
0dca1793 AK |
6478 | break; |
6479 | ||
6480 | case MADI: | |
6481 | case MADIface: | |
6482 | hdspm->ss_in_channels = hdspm->ss_out_channels = | |
6483 | MADI_SS_CHANNELS; | |
6484 | hdspm->ds_in_channels = hdspm->ds_out_channels = | |
6485 | MADI_DS_CHANNELS; | |
6486 | hdspm->qs_in_channels = hdspm->qs_out_channels = | |
6487 | MADI_QS_CHANNELS; | |
6488 | ||
6489 | hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = | |
6490 | channel_map_unity_ss; | |
01e96078 | 6491 | hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = |
0dca1793 | 6492 | channel_map_unity_ss; |
01e96078 | 6493 | hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = |
0dca1793 AK |
6494 | channel_map_unity_ss; |
6495 | ||
6496 | hdspm->port_names_in_ss = hdspm->port_names_out_ss = | |
6497 | texts_ports_madi; | |
6498 | hdspm->port_names_in_ds = hdspm->port_names_out_ds = | |
6499 | texts_ports_madi; | |
6500 | hdspm->port_names_in_qs = hdspm->port_names_out_qs = | |
6501 | texts_ports_madi; | |
6502 | break; | |
6503 | ||
6504 | case AIO: | |
6505 | if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) { | |
6506 | snd_printk(KERN_INFO "HDSPM: AEB input board found, but not supported\n"); | |
6507 | } | |
6508 | ||
6509 | hdspm->ss_in_channels = AIO_IN_SS_CHANNELS; | |
6510 | hdspm->ds_in_channels = AIO_IN_DS_CHANNELS; | |
6511 | hdspm->qs_in_channels = AIO_IN_QS_CHANNELS; | |
6512 | hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS; | |
6513 | hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS; | |
6514 | hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS; | |
6515 | ||
6516 | hdspm->channel_map_out_ss = channel_map_aio_out_ss; | |
6517 | hdspm->channel_map_out_ds = channel_map_aio_out_ds; | |
6518 | hdspm->channel_map_out_qs = channel_map_aio_out_qs; | |
6519 | ||
6520 | hdspm->channel_map_in_ss = channel_map_aio_in_ss; | |
6521 | hdspm->channel_map_in_ds = channel_map_aio_in_ds; | |
6522 | hdspm->channel_map_in_qs = channel_map_aio_in_qs; | |
6523 | ||
6524 | hdspm->port_names_in_ss = texts_ports_aio_in_ss; | |
6525 | hdspm->port_names_out_ss = texts_ports_aio_out_ss; | |
6526 | hdspm->port_names_in_ds = texts_ports_aio_in_ds; | |
6527 | hdspm->port_names_out_ds = texts_ports_aio_out_ds; | |
6528 | hdspm->port_names_in_qs = texts_ports_aio_in_qs; | |
6529 | hdspm->port_names_out_qs = texts_ports_aio_out_qs; | |
6530 | ||
6531 | break; | |
6532 | ||
6533 | case RayDAT: | |
6534 | hdspm->ss_in_channels = hdspm->ss_out_channels = | |
6535 | RAYDAT_SS_CHANNELS; | |
6536 | hdspm->ds_in_channels = hdspm->ds_out_channels = | |
6537 | RAYDAT_DS_CHANNELS; | |
6538 | hdspm->qs_in_channels = hdspm->qs_out_channels = | |
6539 | RAYDAT_QS_CHANNELS; | |
6540 | ||
6541 | hdspm->max_channels_in = RAYDAT_SS_CHANNELS; | |
6542 | hdspm->max_channels_out = RAYDAT_SS_CHANNELS; | |
6543 | ||
6544 | hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = | |
6545 | channel_map_raydat_ss; | |
6546 | hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = | |
6547 | channel_map_raydat_ds; | |
6548 | hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = | |
6549 | channel_map_raydat_qs; | |
6550 | hdspm->channel_map_in = hdspm->channel_map_out = | |
6551 | channel_map_raydat_ss; | |
6552 | ||
6553 | hdspm->port_names_in_ss = hdspm->port_names_out_ss = | |
6554 | texts_ports_raydat_ss; | |
6555 | hdspm->port_names_in_ds = hdspm->port_names_out_ds = | |
6556 | texts_ports_raydat_ds; | |
6557 | hdspm->port_names_in_qs = hdspm->port_names_out_qs = | |
6558 | texts_ports_raydat_qs; | |
6559 | ||
6560 | ||
6561 | break; | |
6562 | ||
6563 | } | |
6564 | ||
6565 | /* TCO detection */ | |
6566 | switch (hdspm->io_type) { | |
6567 | case AIO: | |
6568 | case RayDAT: | |
6569 | if (hdspm_read(hdspm, HDSPM_statusRegister2) & | |
6570 | HDSPM_s2_tco_detect) { | |
6571 | hdspm->midiPorts++; | |
6572 | hdspm->tco = kzalloc(sizeof(struct hdspm_tco), | |
6573 | GFP_KERNEL); | |
6574 | if (NULL != hdspm->tco) { | |
6575 | hdspm_tco_write(hdspm); | |
6576 | } | |
6577 | snd_printk(KERN_INFO "HDSPM: AIO/RayDAT TCO module found\n"); | |
6578 | } else { | |
6579 | hdspm->tco = NULL; | |
6580 | } | |
6581 | break; | |
6582 | ||
6583 | case MADI: | |
6584 | if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) { | |
6585 | hdspm->midiPorts++; | |
6586 | hdspm->tco = kzalloc(sizeof(struct hdspm_tco), | |
6587 | GFP_KERNEL); | |
6588 | if (NULL != hdspm->tco) { | |
6589 | hdspm_tco_write(hdspm); | |
6590 | } | |
6591 | snd_printk(KERN_INFO "HDSPM: MADI TCO module found\n"); | |
6592 | } else { | |
6593 | hdspm->tco = NULL; | |
6594 | } | |
6595 | break; | |
6596 | ||
6597 | default: | |
6598 | hdspm->tco = NULL; | |
6599 | } | |
6600 | ||
6601 | /* texts */ | |
6602 | switch (hdspm->io_type) { | |
6603 | case AES32: | |
6604 | if (hdspm->tco) { | |
6605 | hdspm->texts_autosync = texts_autosync_aes_tco; | |
6606 | hdspm->texts_autosync_items = 10; | |
6607 | } else { | |
6608 | hdspm->texts_autosync = texts_autosync_aes; | |
6609 | hdspm->texts_autosync_items = 9; | |
6610 | } | |
6611 | break; | |
6612 | ||
6613 | case MADI: | |
6614 | if (hdspm->tco) { | |
6615 | hdspm->texts_autosync = texts_autosync_madi_tco; | |
6616 | hdspm->texts_autosync_items = 4; | |
6617 | } else { | |
6618 | hdspm->texts_autosync = texts_autosync_madi; | |
6619 | hdspm->texts_autosync_items = 3; | |
6620 | } | |
6621 | break; | |
6622 | ||
6623 | case MADIface: | |
6624 | ||
6625 | break; | |
6626 | ||
6627 | case RayDAT: | |
6628 | if (hdspm->tco) { | |
6629 | hdspm->texts_autosync = texts_autosync_raydat_tco; | |
6630 | hdspm->texts_autosync_items = 9; | |
6631 | } else { | |
6632 | hdspm->texts_autosync = texts_autosync_raydat; | |
6633 | hdspm->texts_autosync_items = 8; | |
6634 | } | |
6635 | break; | |
6636 | ||
6637 | case AIO: | |
6638 | if (hdspm->tco) { | |
6639 | hdspm->texts_autosync = texts_autosync_aio_tco; | |
6640 | hdspm->texts_autosync_items = 6; | |
6641 | } else { | |
6642 | hdspm->texts_autosync = texts_autosync_aio; | |
6643 | hdspm->texts_autosync_items = 5; | |
6644 | } | |
6645 | break; | |
6646 | ||
6647 | } | |
6648 | ||
6649 | tasklet_init(&hdspm->midi_tasklet, | |
6650 | hdspm_midi_tasklet, (unsigned long) hdspm); | |
763f356c TI |
6651 | |
6652 | snd_printdd("create alsa devices.\n"); | |
ef5fa1a4 TI |
6653 | err = snd_hdspm_create_alsa_devices(card, hdspm); |
6654 | if (err < 0) | |
763f356c TI |
6655 | return err; |
6656 | ||
6657 | snd_hdspm_initialize_midi_flush(hdspm); | |
6658 | ||
6659 | return 0; | |
6660 | } | |
6661 | ||
0dca1793 | 6662 | |
98274f07 | 6663 | static int snd_hdspm_free(struct hdspm * hdspm) |
763f356c TI |
6664 | { |
6665 | ||
6666 | if (hdspm->port) { | |
6667 | ||
6668 | /* stop th audio, and cancel all interrupts */ | |
6669 | hdspm->control_register &= | |
ef5fa1a4 | 6670 | ~(HDSPM_Start | HDSPM_AudioInterruptEnable | |
0dca1793 AK |
6671 | HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable | |
6672 | HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable); | |
763f356c TI |
6673 | hdspm_write(hdspm, HDSPM_controlRegister, |
6674 | hdspm->control_register); | |
6675 | } | |
6676 | ||
6677 | if (hdspm->irq >= 0) | |
6678 | free_irq(hdspm->irq, (void *) hdspm); | |
6679 | ||
fc58422a | 6680 | kfree(hdspm->mixer); |
763f356c TI |
6681 | |
6682 | if (hdspm->iobase) | |
6683 | iounmap(hdspm->iobase); | |
6684 | ||
763f356c TI |
6685 | if (hdspm->port) |
6686 | pci_release_regions(hdspm->pci); | |
6687 | ||
6688 | pci_disable_device(hdspm->pci); | |
6689 | return 0; | |
6690 | } | |
6691 | ||
0dca1793 | 6692 | |
98274f07 | 6693 | static void snd_hdspm_card_free(struct snd_card *card) |
763f356c | 6694 | { |
ef5fa1a4 | 6695 | struct hdspm *hdspm = card->private_data; |
763f356c TI |
6696 | |
6697 | if (hdspm) | |
6698 | snd_hdspm_free(hdspm); | |
6699 | } | |
6700 | ||
0dca1793 | 6701 | |
763f356c TI |
6702 | static int __devinit snd_hdspm_probe(struct pci_dev *pci, |
6703 | const struct pci_device_id *pci_id) | |
6704 | { | |
6705 | static int dev; | |
98274f07 TI |
6706 | struct hdspm *hdspm; |
6707 | struct snd_card *card; | |
763f356c TI |
6708 | int err; |
6709 | ||
6710 | if (dev >= SNDRV_CARDS) | |
6711 | return -ENODEV; | |
6712 | if (!enable[dev]) { | |
6713 | dev++; | |
6714 | return -ENOENT; | |
6715 | } | |
6716 | ||
e58de7ba | 6717 | err = snd_card_create(index[dev], id[dev], |
0dca1793 | 6718 | THIS_MODULE, sizeof(struct hdspm), &card); |
e58de7ba TI |
6719 | if (err < 0) |
6720 | return err; | |
763f356c | 6721 | |
ef5fa1a4 | 6722 | hdspm = card->private_data; |
763f356c TI |
6723 | card->private_free = snd_hdspm_card_free; |
6724 | hdspm->dev = dev; | |
6725 | hdspm->pci = pci; | |
6726 | ||
c187c041 TI |
6727 | snd_card_set_dev(card, &pci->dev); |
6728 | ||
0dca1793 | 6729 | err = snd_hdspm_create(card, hdspm); |
ef5fa1a4 | 6730 | if (err < 0) { |
763f356c TI |
6731 | snd_card_free(card); |
6732 | return err; | |
6733 | } | |
6734 | ||
0dca1793 AK |
6735 | if (hdspm->io_type != MADIface) { |
6736 | sprintf(card->shortname, "%s_%x", | |
6737 | hdspm->card_name, | |
6738 | (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF); | |
6739 | sprintf(card->longname, "%s S/N 0x%x at 0x%lx, irq %d", | |
6740 | hdspm->card_name, | |
6741 | (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF, | |
6742 | hdspm->port, hdspm->irq); | |
6743 | } else { | |
6744 | sprintf(card->shortname, "%s", hdspm->card_name); | |
6745 | sprintf(card->longname, "%s at 0x%lx, irq %d", | |
6746 | hdspm->card_name, hdspm->port, hdspm->irq); | |
6747 | } | |
763f356c | 6748 | |
ef5fa1a4 TI |
6749 | err = snd_card_register(card); |
6750 | if (err < 0) { | |
763f356c TI |
6751 | snd_card_free(card); |
6752 | return err; | |
6753 | } | |
6754 | ||
6755 | pci_set_drvdata(pci, card); | |
6756 | ||
6757 | dev++; | |
6758 | return 0; | |
6759 | } | |
6760 | ||
6761 | static void __devexit snd_hdspm_remove(struct pci_dev *pci) | |
6762 | { | |
6763 | snd_card_free(pci_get_drvdata(pci)); | |
6764 | pci_set_drvdata(pci, NULL); | |
6765 | } | |
6766 | ||
6767 | static struct pci_driver driver = { | |
6768 | .name = "RME Hammerfall DSP MADI", | |
6769 | .id_table = snd_hdspm_ids, | |
6770 | .probe = snd_hdspm_probe, | |
6771 | .remove = __devexit_p(snd_hdspm_remove), | |
6772 | }; | |
6773 | ||
6774 | ||
6775 | static int __init alsa_card_hdspm_init(void) | |
6776 | { | |
6777 | return pci_register_driver(&driver); | |
6778 | } | |
6779 | ||
6780 | static void __exit alsa_card_hdspm_exit(void) | |
6781 | { | |
6782 | pci_unregister_driver(&driver); | |
6783 | } | |
6784 | ||
6785 | module_init(alsa_card_hdspm_init) | |
6786 | module_exit(alsa_card_hdspm_exit) |