Commit | Line | Data |
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ef5fa1a4 | 1 | /* |
763f356c TI |
2 | * ALSA driver for RME Hammerfall DSP MADI audio interface(s) |
3 | * | |
4 | * Copyright (c) 2003 Winfried Ritsch (IEM) | |
5 | * code based on hdsp.c Paul Davis | |
6 | * Marcus Andersson | |
7 | * Thomas Charbonnel | |
3cee5a60 RB |
8 | * Modified 2006-06-01 for AES32 support by Remy Bruno |
9 | * <remy.bruno@trinnov.com> | |
763f356c TI |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
24 | * | |
25 | */ | |
763f356c TI |
26 | #include <linux/init.h> |
27 | #include <linux/delay.h> | |
28 | #include <linux/interrupt.h> | |
29 | #include <linux/moduleparam.h> | |
30 | #include <linux/slab.h> | |
31 | #include <linux/pci.h> | |
32 | #include <asm/io.h> | |
33 | ||
34 | #include <sound/core.h> | |
35 | #include <sound/control.h> | |
36 | #include <sound/pcm.h> | |
37 | #include <sound/info.h> | |
38 | #include <sound/asoundef.h> | |
39 | #include <sound/rawmidi.h> | |
40 | #include <sound/hwdep.h> | |
41 | #include <sound/initval.h> | |
42 | ||
43 | #include <sound/hdspm.h> | |
44 | ||
45 | static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ | |
46 | static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ | |
47 | static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */ | |
48 | ||
49 | /* Disable precise pointer at start */ | |
50 | static int precise_ptr[SNDRV_CARDS]; | |
51 | ||
52 | /* Send all playback to line outs */ | |
53 | static int line_outs_monitor[SNDRV_CARDS]; | |
54 | ||
55 | /* Enable Analog Outs on Channel 63/64 by default */ | |
56 | static int enable_monitor[SNDRV_CARDS]; | |
57 | ||
58 | module_param_array(index, int, NULL, 0444); | |
59 | MODULE_PARM_DESC(index, "Index value for RME HDSPM interface."); | |
60 | ||
61 | module_param_array(id, charp, NULL, 0444); | |
62 | MODULE_PARM_DESC(id, "ID string for RME HDSPM interface."); | |
63 | ||
64 | module_param_array(enable, bool, NULL, 0444); | |
65 | MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards."); | |
66 | ||
67 | module_param_array(precise_ptr, bool, NULL, 0444); | |
e8da2fbc | 68 | MODULE_PARM_DESC(precise_ptr, "Enable or disable precise pointer."); |
763f356c TI |
69 | |
70 | module_param_array(line_outs_monitor, bool, NULL, 0444); | |
71 | MODULE_PARM_DESC(line_outs_monitor, | |
72 | "Send playback streams to analog outs by default."); | |
73 | ||
74 | module_param_array(enable_monitor, bool, NULL, 0444); | |
75 | MODULE_PARM_DESC(enable_monitor, | |
76 | "Enable Analog Out on Channel 63/64 by default."); | |
77 | ||
78 | MODULE_AUTHOR | |
ef5fa1a4 TI |
79 | ("Winfried Ritsch <ritsch_AT_iem.at>, " |
80 | "Paul Davis <paul@linuxaudiosystems.com>, " | |
3cee5a60 RB |
81 | "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, " |
82 | "Remy Bruno <remy.bruno@trinnov.com>"); | |
763f356c TI |
83 | MODULE_DESCRIPTION("RME HDSPM"); |
84 | MODULE_LICENSE("GPL"); | |
85 | MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}"); | |
86 | ||
87 | /* --- Write registers. --- | |
88 | These are defined as byte-offsets from the iobase value. */ | |
89 | ||
90 | #define HDSPM_controlRegister 64 | |
91 | #define HDSPM_interruptConfirmation 96 | |
92 | #define HDSPM_control2Reg 256 /* not in specs ???????? */ | |
ffb2c3c0 | 93 | #define HDSPM_freqReg 256 /* for AES32 */ |
763f356c TI |
94 | #define HDSPM_midiDataOut0 352 /* just believe in old code */ |
95 | #define HDSPM_midiDataOut1 356 | |
ffb2c3c0 | 96 | #define HDSPM_eeprom_wr 384 /* for AES32 */ |
763f356c TI |
97 | |
98 | /* DMA enable for 64 channels, only Bit 0 is relevant */ | |
99 | #define HDSPM_outputEnableBase 512 /* 512-767 input DMA */ | |
100 | #define HDSPM_inputEnableBase 768 /* 768-1023 output DMA */ | |
101 | ||
102 | /* 16 page addresses for each of the 64 channels DMA buffer in and out | |
103 | (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */ | |
104 | #define HDSPM_pageAddressBufferOut 8192 | |
105 | #define HDSPM_pageAddressBufferIn (HDSPM_pageAddressBufferOut+64*16*4) | |
106 | ||
107 | #define HDSPM_MADI_mixerBase 32768 /* 32768-65535 for 2x64x64 Fader */ | |
108 | ||
109 | #define HDSPM_MATRIX_MIXER_SIZE 8192 /* = 2*64*64 * 4 Byte => 32kB */ | |
110 | ||
111 | /* --- Read registers. --- | |
112 | These are defined as byte-offsets from the iobase value */ | |
113 | #define HDSPM_statusRegister 0 | |
3cee5a60 RB |
114 | /*#define HDSPM_statusRegister2 96 */ |
115 | /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at | |
116 | * offset 192, for AES32 *and* MADI | |
117 | * => need to check that offset 192 is working on MADI */ | |
118 | #define HDSPM_statusRegister2 192 | |
119 | #define HDSPM_timecodeRegister 128 | |
763f356c TI |
120 | |
121 | #define HDSPM_midiDataIn0 360 | |
122 | #define HDSPM_midiDataIn1 364 | |
123 | ||
124 | /* status is data bytes in MIDI-FIFO (0-128) */ | |
125 | #define HDSPM_midiStatusOut0 384 | |
126 | #define HDSPM_midiStatusOut1 388 | |
127 | #define HDSPM_midiStatusIn0 392 | |
128 | #define HDSPM_midiStatusIn1 396 | |
129 | ||
130 | ||
131 | /* the meters are regular i/o-mapped registers, but offset | |
132 | considerably from the rest. the peak registers are reset | |
133 | when read; the least-significant 4 bits are full-scale counters; | |
134 | the actual peak value is in the most-significant 24 bits. | |
135 | */ | |
136 | #define HDSPM_MADI_peakrmsbase 4096 /* 4096-8191 2x64x32Bit Meters */ | |
137 | ||
138 | /* --- Control Register bits --------- */ | |
139 | #define HDSPM_Start (1<<0) /* start engine */ | |
140 | ||
141 | #define HDSPM_Latency0 (1<<1) /* buffer size = 2^n */ | |
142 | #define HDSPM_Latency1 (1<<2) /* where n is defined */ | |
143 | #define HDSPM_Latency2 (1<<3) /* by Latency{2,1,0} */ | |
144 | ||
145 | #define HDSPM_ClockModeMaster (1<<4) /* 1=Master, 0=Slave/Autosync */ | |
146 | ||
147 | #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */ | |
148 | ||
149 | #define HDSPM_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */ | |
150 | #define HDSPM_Frequency1 (1<<7) /* 0=32kHz/64kHz */ | |
151 | #define HDSPM_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */ | |
3cee5a60 | 152 | #define HDSPM_QuadSpeed (1<<31) /* quad speed bit */ |
763f356c | 153 | |
3cee5a60 | 154 | #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */ |
763f356c | 155 | #define HDSPM_TX_64ch (1<<10) /* Output 64channel MODE=1, |
3cee5a60 RB |
156 | 56channelMODE=0 */ /* MADI ONLY*/ |
157 | #define HDSPM_Emphasis (1<<10) /* Emphasis */ /* AES32 ONLY */ | |
763f356c TI |
158 | |
159 | #define HDSPM_AutoInp (1<<11) /* Auto Input (takeover) == Safe Mode, | |
3cee5a60 RB |
160 | 0=off, 1=on */ /* MADI ONLY */ |
161 | #define HDSPM_Dolby (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */ | |
763f356c | 162 | |
ef5fa1a4 TI |
163 | #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax |
164 | * -- MADI ONLY | |
165 | */ | |
763f356c TI |
166 | #define HDSPM_InputSelect1 (1<<15) /* should be 0 */ |
167 | ||
168 | #define HDSPM_SyncRef0 (1<<16) /* 0=WOrd, 1=MADI */ | |
3cee5a60 RB |
169 | #define HDSPM_SyncRef1 (1<<17) /* for AES32: SyncRefN codes the AES # */ |
170 | #define HDSPM_SyncRef2 (1<<13) | |
171 | #define HDSPM_SyncRef3 (1<<25) | |
763f356c | 172 | |
3cee5a60 | 173 | #define HDSPM_SMUX (1<<18) /* Frame ??? */ /* MADI ONY */ |
763f356c TI |
174 | #define HDSPM_clr_tms (1<<19) /* clear track marker, do not use |
175 | AES additional bits in | |
176 | lower 5 Audiodatabits ??? */ | |
3cee5a60 RB |
177 | #define HDSPM_taxi_reset (1<<20) /* ??? */ /* MADI ONLY ? */ |
178 | #define HDSPM_WCK48 (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */ | |
763f356c TI |
179 | |
180 | #define HDSPM_Midi0InterruptEnable (1<<22) | |
181 | #define HDSPM_Midi1InterruptEnable (1<<23) | |
182 | ||
183 | #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */ | |
184 | ||
3cee5a60 RB |
185 | #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */ |
186 | #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */ | |
187 | #define HDSPM_QS_QuadWire (1<<28) /* AES32 ONLY */ | |
188 | ||
189 | #define HDSPM_wclk_sel (1<<30) | |
763f356c TI |
190 | |
191 | /* --- bit helper defines */ | |
192 | #define HDSPM_LatencyMask (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2) | |
ef5fa1a4 TI |
193 | #define HDSPM_FrequencyMask (HDSPM_Frequency0|HDSPM_Frequency1|\ |
194 | HDSPM_DoubleSpeed|HDSPM_QuadSpeed) | |
763f356c TI |
195 | #define HDSPM_InputMask (HDSPM_InputSelect0|HDSPM_InputSelect1) |
196 | #define HDSPM_InputOptical 0 | |
197 | #define HDSPM_InputCoaxial (HDSPM_InputSelect0) | |
ef5fa1a4 TI |
198 | #define HDSPM_SyncRefMask (HDSPM_SyncRef0|HDSPM_SyncRef1|\ |
199 | HDSPM_SyncRef2|HDSPM_SyncRef3) | |
763f356c TI |
200 | #define HDSPM_SyncRef_Word 0 |
201 | #define HDSPM_SyncRef_MADI (HDSPM_SyncRef0) | |
202 | ||
203 | #define HDSPM_SYNC_FROM_WORD 0 /* Preferred sync reference */ | |
204 | #define HDSPM_SYNC_FROM_MADI 1 /* choices - used by "pref_sync_ref" */ | |
205 | ||
206 | #define HDSPM_Frequency32KHz HDSPM_Frequency0 | |
207 | #define HDSPM_Frequency44_1KHz HDSPM_Frequency1 | |
208 | #define HDSPM_Frequency48KHz (HDSPM_Frequency1|HDSPM_Frequency0) | |
209 | #define HDSPM_Frequency64KHz (HDSPM_DoubleSpeed|HDSPM_Frequency0) | |
210 | #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1) | |
ef5fa1a4 TI |
211 | #define HDSPM_Frequency96KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1|\ |
212 | HDSPM_Frequency0) | |
3cee5a60 RB |
213 | #define HDSPM_Frequency128KHz (HDSPM_QuadSpeed|HDSPM_Frequency0) |
214 | #define HDSPM_Frequency176_4KHz (HDSPM_QuadSpeed|HDSPM_Frequency1) | |
ef5fa1a4 TI |
215 | #define HDSPM_Frequency192KHz (HDSPM_QuadSpeed|HDSPM_Frequency1|\ |
216 | HDSPM_Frequency0) | |
763f356c TI |
217 | |
218 | /* --- for internal discrimination */ | |
219 | #define HDSPM_CLOCK_SOURCE_AUTOSYNC 0 /* Sample Clock Sources */ | |
220 | #define HDSPM_CLOCK_SOURCE_INTERNAL_32KHZ 1 | |
221 | #define HDSPM_CLOCK_SOURCE_INTERNAL_44_1KHZ 2 | |
222 | #define HDSPM_CLOCK_SOURCE_INTERNAL_48KHZ 3 | |
223 | #define HDSPM_CLOCK_SOURCE_INTERNAL_64KHZ 4 | |
224 | #define HDSPM_CLOCK_SOURCE_INTERNAL_88_2KHZ 5 | |
225 | #define HDSPM_CLOCK_SOURCE_INTERNAL_96KHZ 6 | |
226 | #define HDSPM_CLOCK_SOURCE_INTERNAL_128KHZ 7 | |
227 | #define HDSPM_CLOCK_SOURCE_INTERNAL_176_4KHZ 8 | |
228 | #define HDSPM_CLOCK_SOURCE_INTERNAL_192KHZ 9 | |
229 | ||
230 | /* Synccheck Status */ | |
231 | #define HDSPM_SYNC_CHECK_NO_LOCK 0 | |
232 | #define HDSPM_SYNC_CHECK_LOCK 1 | |
233 | #define HDSPM_SYNC_CHECK_SYNC 2 | |
234 | ||
235 | /* AutoSync References - used by "autosync_ref" control switch */ | |
236 | #define HDSPM_AUTOSYNC_FROM_WORD 0 | |
237 | #define HDSPM_AUTOSYNC_FROM_MADI 1 | |
238 | #define HDSPM_AUTOSYNC_FROM_NONE 2 | |
239 | ||
240 | /* Possible sources of MADI input */ | |
241 | #define HDSPM_OPTICAL 0 /* optical */ | |
242 | #define HDSPM_COAXIAL 1 /* BNC */ | |
243 | ||
244 | #define hdspm_encode_latency(x) (((x)<<1) & HDSPM_LatencyMask) | |
245 | #define hdspm_decode_latency(x) (((x) & HDSPM_LatencyMask)>>1) | |
246 | ||
247 | #define hdspm_encode_in(x) (((x)&0x3)<<14) | |
248 | #define hdspm_decode_in(x) (((x)>>14)&0x3) | |
249 | ||
250 | /* --- control2 register bits --- */ | |
251 | #define HDSPM_TMS (1<<0) | |
252 | #define HDSPM_TCK (1<<1) | |
253 | #define HDSPM_TDI (1<<2) | |
254 | #define HDSPM_JTAG (1<<3) | |
255 | #define HDSPM_PWDN (1<<4) | |
256 | #define HDSPM_PROGRAM (1<<5) | |
257 | #define HDSPM_CONFIG_MODE_0 (1<<6) | |
258 | #define HDSPM_CONFIG_MODE_1 (1<<7) | |
259 | /*#define HDSPM_VERSION_BIT (1<<8) not defined any more*/ | |
260 | #define HDSPM_BIGENDIAN_MODE (1<<9) | |
261 | #define HDSPM_RD_MULTIPLE (1<<10) | |
262 | ||
3cee5a60 | 263 | /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and |
ef5fa1a4 TI |
264 | that do not conflict with specific bits for AES32 seem to be valid also |
265 | for the AES32 | |
266 | */ | |
763f356c | 267 | #define HDSPM_audioIRQPending (1<<0) /* IRQ is high and pending */ |
ef5fa1a4 TI |
268 | #define HDSPM_RX_64ch (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */ |
269 | #define HDSPM_AB_int (1<<2) /* InputChannel Opt=0, Coax=1 | |
270 | * (like inp0) | |
271 | */ | |
763f356c TI |
272 | #define HDSPM_madiLock (1<<3) /* MADI Locked =1, no=0 */ |
273 | ||
274 | #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */ | |
275 | /* since 64byte accurate last 6 bits | |
276 | are not used */ | |
277 | ||
278 | #define HDSPM_madiSync (1<<18) /* MADI is in sync */ | |
279 | #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */ | |
280 | ||
281 | #define HDSPM_madiFreq0 (1<<22) /* system freq 0=error */ | |
282 | #define HDSPM_madiFreq1 (1<<23) /* 1=32, 2=44.1 3=48 */ | |
283 | #define HDSPM_madiFreq2 (1<<24) /* 4=64, 5=88.2 6=96 */ | |
284 | #define HDSPM_madiFreq3 (1<<25) /* 7=128, 8=176.4 9=192 */ | |
285 | ||
ef5fa1a4 TI |
286 | #define HDSPM_BufferID (1<<26) /* (Double)Buffer ID toggles with |
287 | * Interrupt | |
288 | */ | |
763f356c TI |
289 | #define HDSPM_midi0IRQPending (1<<30) /* MIDI IRQ is pending */ |
290 | #define HDSPM_midi1IRQPending (1<<31) /* and aktiv */ | |
291 | ||
292 | /* --- status bit helpers */ | |
ef5fa1a4 TI |
293 | #define HDSPM_madiFreqMask (HDSPM_madiFreq0|HDSPM_madiFreq1|\ |
294 | HDSPM_madiFreq2|HDSPM_madiFreq3) | |
763f356c TI |
295 | #define HDSPM_madiFreq32 (HDSPM_madiFreq0) |
296 | #define HDSPM_madiFreq44_1 (HDSPM_madiFreq1) | |
297 | #define HDSPM_madiFreq48 (HDSPM_madiFreq0|HDSPM_madiFreq1) | |
298 | #define HDSPM_madiFreq64 (HDSPM_madiFreq2) | |
299 | #define HDSPM_madiFreq88_2 (HDSPM_madiFreq0|HDSPM_madiFreq2) | |
300 | #define HDSPM_madiFreq96 (HDSPM_madiFreq1|HDSPM_madiFreq2) | |
301 | #define HDSPM_madiFreq128 (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2) | |
302 | #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3) | |
303 | #define HDSPM_madiFreq192 (HDSPM_madiFreq3|HDSPM_madiFreq0) | |
304 | ||
3cee5a60 | 305 | /* Status2 Register bits */ /* MADI ONLY */ |
763f356c TI |
306 | |
307 | #define HDSPM_version0 (1<<0) /* not realy defined but I guess */ | |
308 | #define HDSPM_version1 (1<<1) /* in former cards it was ??? */ | |
309 | #define HDSPM_version2 (1<<2) | |
310 | ||
311 | #define HDSPM_wcLock (1<<3) /* Wordclock is detected and locked */ | |
312 | #define HDSPM_wcSync (1<<4) /* Wordclock is in sync with systemclock */ | |
313 | ||
314 | #define HDSPM_wc_freq0 (1<<5) /* input freq detected via autosync */ | |
315 | #define HDSPM_wc_freq1 (1<<6) /* 001=32, 010==44.1, 011=48, */ | |
316 | #define HDSPM_wc_freq2 (1<<7) /* 100=64, 101=88.2, 110=96, */ | |
317 | /* missing Bit for 111=128, 1000=176.4, 1001=192 */ | |
318 | ||
319 | #define HDSPM_SelSyncRef0 (1<<8) /* Sync Source in slave mode */ | |
320 | #define HDSPM_SelSyncRef1 (1<<9) /* 000=word, 001=MADI, */ | |
321 | #define HDSPM_SelSyncRef2 (1<<10) /* 111=no valid signal */ | |
322 | ||
323 | #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync) | |
324 | ||
325 | #define HDSPM_wcFreqMask (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2) | |
326 | #define HDSPM_wcFreq32 (HDSPM_wc_freq0) | |
327 | #define HDSPM_wcFreq44_1 (HDSPM_wc_freq1) | |
328 | #define HDSPM_wcFreq48 (HDSPM_wc_freq0|HDSPM_wc_freq1) | |
329 | #define HDSPM_wcFreq64 (HDSPM_wc_freq2) | |
330 | #define HDSPM_wcFreq88_2 (HDSPM_wc_freq0|HDSPM_wc_freq2) | |
331 | #define HDSPM_wcFreq96 (HDSPM_wc_freq1|HDSPM_wc_freq2) | |
332 | ||
333 | ||
ef5fa1a4 TI |
334 | #define HDSPM_SelSyncRefMask (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\ |
335 | HDSPM_SelSyncRef2) | |
763f356c TI |
336 | #define HDSPM_SelSyncRef_WORD 0 |
337 | #define HDSPM_SelSyncRef_MADI (HDSPM_SelSyncRef0) | |
ef5fa1a4 TI |
338 | #define HDSPM_SelSyncRef_NVALID (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\ |
339 | HDSPM_SelSyncRef2) | |
763f356c | 340 | |
3cee5a60 RB |
341 | /* |
342 | For AES32, bits for status, status2 and timecode are different | |
343 | */ | |
344 | /* status */ | |
345 | #define HDSPM_AES32_wcLock 0x0200000 | |
346 | #define HDSPM_AES32_wcFreq_bit 22 | |
347 | /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function | |
348 | HDSPM_bit2freq */ | |
349 | #define HDSPM_AES32_syncref_bit 16 | |
350 | /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */ | |
351 | ||
352 | #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0 | |
353 | #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1 | |
354 | #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2 | |
355 | #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3 | |
356 | #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4 | |
357 | #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5 | |
358 | #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6 | |
359 | #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7 | |
360 | #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8 | |
6534599d | 361 | #define HDSPM_AES32_AUTOSYNC_FROM_NONE 9 |
3cee5a60 RB |
362 | |
363 | /* status2 */ | |
364 | /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */ | |
365 | #define HDSPM_LockAES 0x80 | |
366 | #define HDSPM_LockAES1 0x80 | |
367 | #define HDSPM_LockAES2 0x40 | |
368 | #define HDSPM_LockAES3 0x20 | |
369 | #define HDSPM_LockAES4 0x10 | |
370 | #define HDSPM_LockAES5 0x8 | |
371 | #define HDSPM_LockAES6 0x4 | |
372 | #define HDSPM_LockAES7 0x2 | |
373 | #define HDSPM_LockAES8 0x1 | |
374 | /* | |
375 | Timecode | |
376 | After windows driver sources, bits 4*i to 4*i+3 give the input frequency on | |
377 | AES i+1 | |
378 | bits 3210 | |
379 | 0001 32kHz | |
380 | 0010 44.1kHz | |
381 | 0011 48kHz | |
382 | 0100 64kHz | |
383 | 0101 88.2kHz | |
384 | 0110 96kHz | |
385 | 0111 128kHz | |
386 | 1000 176.4kHz | |
387 | 1001 192kHz | |
388 | NB: Timecode register doesn't seem to work on AES32 card revision 230 | |
389 | */ | |
390 | ||
763f356c TI |
391 | /* Mixer Values */ |
392 | #define UNITY_GAIN 32768 /* = 65536/2 */ | |
393 | #define MINUS_INFINITY_GAIN 0 | |
394 | ||
763f356c TI |
395 | /* Number of channels for different Speed Modes */ |
396 | #define MADI_SS_CHANNELS 64 | |
397 | #define MADI_DS_CHANNELS 32 | |
398 | #define MADI_QS_CHANNELS 16 | |
399 | ||
400 | /* the size of a substream (1 mono data stream) */ | |
401 | #define HDSPM_CHANNEL_BUFFER_SAMPLES (16*1024) | |
402 | #define HDSPM_CHANNEL_BUFFER_BYTES (4*HDSPM_CHANNEL_BUFFER_SAMPLES) | |
403 | ||
404 | /* the size of the area we need to allocate for DMA transfers. the | |
405 | size is the same regardless of the number of channels, and | |
406 | also the latency to use. | |
407 | for one direction !!! | |
408 | */ | |
ffb2c3c0 | 409 | #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES) |
763f356c TI |
410 | #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024) |
411 | ||
3cee5a60 RB |
412 | /* revisions >= 230 indicate AES32 card */ |
413 | #define HDSPM_AESREVISION 230 | |
414 | ||
6534599d RB |
415 | /* speed factor modes */ |
416 | #define HDSPM_SPEED_SINGLE 0 | |
417 | #define HDSPM_SPEED_DOUBLE 1 | |
418 | #define HDSPM_SPEED_QUAD 2 | |
419 | /* names for speed modes */ | |
420 | static char *hdspm_speed_names[] = { "single", "double", "quad" }; | |
421 | ||
98274f07 TI |
422 | struct hdspm_midi { |
423 | struct hdspm *hdspm; | |
763f356c | 424 | int id; |
98274f07 TI |
425 | struct snd_rawmidi *rmidi; |
426 | struct snd_rawmidi_substream *input; | |
427 | struct snd_rawmidi_substream *output; | |
763f356c TI |
428 | char istimer; /* timer in use */ |
429 | struct timer_list timer; | |
430 | spinlock_t lock; | |
431 | int pending; | |
432 | }; | |
433 | ||
98274f07 | 434 | struct hdspm { |
763f356c | 435 | spinlock_t lock; |
ef5fa1a4 TI |
436 | /* only one playback and/or capture stream */ |
437 | struct snd_pcm_substream *capture_substream; | |
438 | struct snd_pcm_substream *playback_substream; | |
763f356c TI |
439 | |
440 | char *card_name; /* for procinfo */ | |
3cee5a60 RB |
441 | unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/ |
442 | ||
443 | unsigned char is_aes32; /* indicates if card is AES32 */ | |
763f356c TI |
444 | |
445 | int precise_ptr; /* use precise pointers, to be tested */ | |
446 | int monitor_outs; /* set up monitoring outs init flag */ | |
447 | ||
448 | u32 control_register; /* cached value */ | |
449 | u32 control2_register; /* cached value */ | |
450 | ||
98274f07 | 451 | struct hdspm_midi midi[2]; |
763f356c TI |
452 | struct tasklet_struct midi_tasklet; |
453 | ||
454 | size_t period_bytes; | |
455 | unsigned char ss_channels; /* channels of card in single speed */ | |
456 | unsigned char ds_channels; /* Double Speed */ | |
457 | unsigned char qs_channels; /* Quad Speed */ | |
458 | ||
459 | unsigned char *playback_buffer; /* suitably aligned address */ | |
460 | unsigned char *capture_buffer; /* suitably aligned address */ | |
461 | ||
462 | pid_t capture_pid; /* process id which uses capture */ | |
463 | pid_t playback_pid; /* process id which uses capture */ | |
464 | int running; /* running status */ | |
465 | ||
466 | int last_external_sample_rate; /* samplerate mystic ... */ | |
467 | int last_internal_sample_rate; | |
468 | int system_sample_rate; | |
469 | ||
470 | char *channel_map; /* channel map for DS and Quadspeed */ | |
471 | ||
472 | int dev; /* Hardware vars... */ | |
473 | int irq; | |
474 | unsigned long port; | |
475 | void __iomem *iobase; | |
476 | ||
477 | int irq_count; /* for debug */ | |
478 | ||
98274f07 TI |
479 | struct snd_card *card; /* one card */ |
480 | struct snd_pcm *pcm; /* has one pcm */ | |
481 | struct snd_hwdep *hwdep; /* and a hwdep for additional ioctl */ | |
763f356c TI |
482 | struct pci_dev *pci; /* and an pci info */ |
483 | ||
484 | /* Mixer vars */ | |
ef5fa1a4 TI |
485 | /* fast alsa mixer */ |
486 | struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS]; | |
487 | /* but input to much, so not used */ | |
488 | struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS]; | |
489 | /* full mixer accessable over mixer ioctl or hwdep-device */ | |
490 | struct hdspm_mixer *mixer; | |
763f356c TI |
491 | |
492 | }; | |
493 | ||
494 | /* These tables map the ALSA channels 1..N to the channels that we | |
495 | need to use in order to find the relevant channel buffer. RME | |
496 | refer to this kind of mapping as between "the ADAT channel and | |
497 | the DMA channel." We index it using the logical audio channel, | |
498 | and the value is the DMA channel (i.e. channel buffer number) | |
499 | where the data for that channel can be read/written from/to. | |
500 | */ | |
501 | ||
502 | static char channel_map_madi_ss[HDSPM_MAX_CHANNELS] = { | |
503 | 0, 1, 2, 3, 4, 5, 6, 7, | |
504 | 8, 9, 10, 11, 12, 13, 14, 15, | |
505 | 16, 17, 18, 19, 20, 21, 22, 23, | |
506 | 24, 25, 26, 27, 28, 29, 30, 31, | |
507 | 32, 33, 34, 35, 36, 37, 38, 39, | |
508 | 40, 41, 42, 43, 44, 45, 46, 47, | |
509 | 48, 49, 50, 51, 52, 53, 54, 55, | |
510 | 56, 57, 58, 59, 60, 61, 62, 63 | |
511 | }; | |
512 | ||
763f356c | 513 | |
396c9b92 | 514 | static struct pci_device_id snd_hdspm_ids[] __devinitdata = { |
763f356c TI |
515 | { |
516 | .vendor = PCI_VENDOR_ID_XILINX, | |
517 | .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI, | |
518 | .subvendor = PCI_ANY_ID, | |
519 | .subdevice = PCI_ANY_ID, | |
520 | .class = 0, | |
521 | .class_mask = 0, | |
522 | .driver_data = 0}, | |
523 | {0,} | |
524 | }; | |
525 | ||
526 | MODULE_DEVICE_TABLE(pci, snd_hdspm_ids); | |
527 | ||
528 | /* prototypes */ | |
98274f07 TI |
529 | static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card, |
530 | struct hdspm * hdspm); | |
531 | static int __devinit snd_hdspm_create_pcm(struct snd_card *card, | |
532 | struct hdspm * hdspm); | |
533 | ||
534 | static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm); | |
535 | static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm); | |
536 | static int hdspm_autosync_ref(struct hdspm * hdspm); | |
537 | static int snd_hdspm_set_defaults(struct hdspm * hdspm); | |
538 | static void hdspm_set_sgbuf(struct hdspm * hdspm, struct snd_sg_buf *sgbuf, | |
763f356c TI |
539 | unsigned int reg, int channels); |
540 | ||
3cee5a60 RB |
541 | static inline int HDSPM_bit2freq(int n) |
542 | { | |
543 | static int bit2freq_tab[] = { 0, 32000, 44100, 48000, 64000, 88200, | |
544 | 96000, 128000, 176400, 192000 }; | |
545 | if (n < 1 || n > 9) | |
546 | return 0; | |
547 | return bit2freq_tab[n]; | |
548 | } | |
549 | ||
763f356c TI |
550 | /* Write/read to/from HDSPM with Adresses in Bytes |
551 | not words but only 32Bit writes are allowed */ | |
552 | ||
98274f07 | 553 | static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg, |
763f356c TI |
554 | unsigned int val) |
555 | { | |
556 | writel(val, hdspm->iobase + reg); | |
557 | } | |
558 | ||
98274f07 | 559 | static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg) |
763f356c TI |
560 | { |
561 | return readl(hdspm->iobase + reg); | |
562 | } | |
563 | ||
564 | /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader | |
565 | mixer is write only on hardware so we have to cache him for read | |
566 | each fader is a u32, but uses only the first 16 bit */ | |
567 | ||
98274f07 | 568 | static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan, |
763f356c TI |
569 | unsigned int in) |
570 | { | |
5bab2482 | 571 | if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS) |
763f356c TI |
572 | return 0; |
573 | ||
574 | return hdspm->mixer->ch[chan].in[in]; | |
575 | } | |
576 | ||
98274f07 | 577 | static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan, |
763f356c TI |
578 | unsigned int pb) |
579 | { | |
5bab2482 | 580 | if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS) |
763f356c TI |
581 | return 0; |
582 | return hdspm->mixer->ch[chan].pb[pb]; | |
583 | } | |
584 | ||
98274f07 | 585 | static inline int hdspm_write_in_gain(struct hdspm * hdspm, unsigned int chan, |
763f356c TI |
586 | unsigned int in, unsigned short data) |
587 | { | |
588 | if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS) | |
589 | return -1; | |
590 | ||
591 | hdspm_write(hdspm, | |
592 | HDSPM_MADI_mixerBase + | |
593 | ((in + 128 * chan) * sizeof(u32)), | |
594 | (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF)); | |
595 | return 0; | |
596 | } | |
597 | ||
98274f07 | 598 | static inline int hdspm_write_pb_gain(struct hdspm * hdspm, unsigned int chan, |
763f356c TI |
599 | unsigned int pb, unsigned short data) |
600 | { | |
601 | if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS) | |
602 | return -1; | |
603 | ||
604 | hdspm_write(hdspm, | |
605 | HDSPM_MADI_mixerBase + | |
606 | ((64 + pb + 128 * chan) * sizeof(u32)), | |
607 | (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF)); | |
608 | return 0; | |
609 | } | |
610 | ||
611 | ||
612 | /* enable DMA for specific channels, now available for DSP-MADI */ | |
98274f07 | 613 | static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v) |
763f356c TI |
614 | { |
615 | hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v); | |
616 | } | |
617 | ||
98274f07 | 618 | static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v) |
763f356c TI |
619 | { |
620 | hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v); | |
621 | } | |
622 | ||
623 | /* check if same process is writing and reading */ | |
98274f07 | 624 | static inline int snd_hdspm_use_is_exclusive(struct hdspm * hdspm) |
763f356c TI |
625 | { |
626 | unsigned long flags; | |
627 | int ret = 1; | |
628 | ||
629 | spin_lock_irqsave(&hdspm->lock, flags); | |
630 | if ((hdspm->playback_pid != hdspm->capture_pid) && | |
631 | (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) { | |
632 | ret = 0; | |
633 | } | |
634 | spin_unlock_irqrestore(&hdspm->lock, flags); | |
635 | return ret; | |
636 | } | |
637 | ||
638 | /* check for external sample rate */ | |
98274f07 | 639 | static inline int hdspm_external_sample_rate(struct hdspm * hdspm) |
763f356c | 640 | { |
3cee5a60 RB |
641 | if (hdspm->is_aes32) { |
642 | unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2); | |
643 | unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister); | |
ef5fa1a4 TI |
644 | unsigned int timecode = |
645 | hdspm_read(hdspm, HDSPM_timecodeRegister); | |
3cee5a60 RB |
646 | |
647 | int syncref = hdspm_autosync_ref(hdspm); | |
648 | ||
649 | if (syncref == HDSPM_AES32_AUTOSYNC_FROM_WORD && | |
650 | status & HDSPM_AES32_wcLock) | |
ef5fa1a4 TI |
651 | return HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) |
652 | & 0xF); | |
3cee5a60 RB |
653 | if (syncref >= HDSPM_AES32_AUTOSYNC_FROM_AES1 && |
654 | syncref <= HDSPM_AES32_AUTOSYNC_FROM_AES8 && | |
655 | status2 & (HDSPM_LockAES >> | |
656 | (syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1))) | |
657 | return HDSPM_bit2freq((timecode >> | |
658 | (4*(syncref-HDSPM_AES32_AUTOSYNC_FROM_AES1))) & 0xF); | |
659 | return 0; | |
660 | } else { | |
661 | unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2); | |
662 | unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister); | |
663 | unsigned int rate_bits; | |
664 | int rate = 0; | |
763f356c | 665 | |
3cee5a60 RB |
666 | /* if wordclock has synced freq and wordclock is valid */ |
667 | if ((status2 & HDSPM_wcLock) != 0 && | |
668 | (status & HDSPM_SelSyncRef0) == 0) { | |
763f356c | 669 | |
3cee5a60 | 670 | rate_bits = status2 & HDSPM_wcFreqMask; |
763f356c | 671 | |
3cee5a60 RB |
672 | switch (rate_bits) { |
673 | case HDSPM_wcFreq32: | |
674 | rate = 32000; | |
675 | break; | |
676 | case HDSPM_wcFreq44_1: | |
677 | rate = 44100; | |
678 | break; | |
679 | case HDSPM_wcFreq48: | |
680 | rate = 48000; | |
681 | break; | |
682 | case HDSPM_wcFreq64: | |
683 | rate = 64000; | |
684 | break; | |
685 | case HDSPM_wcFreq88_2: | |
686 | rate = 88200; | |
687 | break; | |
688 | case HDSPM_wcFreq96: | |
689 | rate = 96000; | |
690 | break; | |
691 | /* Quadspeed Bit missing ???? */ | |
692 | default: | |
693 | rate = 0; | |
694 | break; | |
695 | } | |
763f356c | 696 | } |
763f356c | 697 | |
ef5fa1a4 TI |
698 | /* if rate detected and Syncref is Word than have it, |
699 | * word has priority to MADI | |
700 | */ | |
3cee5a60 RB |
701 | if (rate != 0 && |
702 | (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD) | |
703 | return rate; | |
763f356c | 704 | |
3cee5a60 RB |
705 | /* maby a madi input (which is taken if sel sync is madi) */ |
706 | if (status & HDSPM_madiLock) { | |
707 | rate_bits = status & HDSPM_madiFreqMask; | |
763f356c | 708 | |
3cee5a60 RB |
709 | switch (rate_bits) { |
710 | case HDSPM_madiFreq32: | |
711 | rate = 32000; | |
712 | break; | |
713 | case HDSPM_madiFreq44_1: | |
714 | rate = 44100; | |
715 | break; | |
716 | case HDSPM_madiFreq48: | |
717 | rate = 48000; | |
718 | break; | |
719 | case HDSPM_madiFreq64: | |
720 | rate = 64000; | |
721 | break; | |
722 | case HDSPM_madiFreq88_2: | |
723 | rate = 88200; | |
724 | break; | |
725 | case HDSPM_madiFreq96: | |
726 | rate = 96000; | |
727 | break; | |
728 | case HDSPM_madiFreq128: | |
729 | rate = 128000; | |
730 | break; | |
731 | case HDSPM_madiFreq176_4: | |
732 | rate = 176400; | |
733 | break; | |
734 | case HDSPM_madiFreq192: | |
735 | rate = 192000; | |
736 | break; | |
737 | default: | |
738 | rate = 0; | |
739 | break; | |
740 | } | |
763f356c | 741 | } |
3cee5a60 | 742 | return rate; |
763f356c | 743 | } |
763f356c TI |
744 | } |
745 | ||
746 | /* Latency function */ | |
98274f07 | 747 | static inline void hdspm_compute_period_size(struct hdspm * hdspm) |
763f356c TI |
748 | { |
749 | hdspm->period_bytes = | |
750 | 1 << ((hdspm_decode_latency(hdspm->control_register) + 8)); | |
751 | } | |
752 | ||
98274f07 | 753 | static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm * hdspm) |
763f356c TI |
754 | { |
755 | int position; | |
756 | ||
757 | position = hdspm_read(hdspm, HDSPM_statusRegister); | |
758 | ||
ef5fa1a4 TI |
759 | if (!hdspm->precise_ptr) |
760 | return (position & HDSPM_BufferID) ? | |
761 | (hdspm->period_bytes / 4) : 0; | |
763f356c | 762 | |
ef5fa1a4 TI |
763 | /* hwpointer comes in bytes and is 64Bytes accurate (by docu since |
764 | PCI Burst) | |
763f356c TI |
765 | i have experimented that it is at most 64 Byte to much for playing |
766 | so substraction of 64 byte should be ok for ALSA, but use it only | |
767 | for application where you know what you do since if you come to | |
768 | near with record pointer it can be a disaster */ | |
769 | ||
770 | position &= HDSPM_BufferPositionMask; | |
771 | position = ((position - 64) % (2 * hdspm->period_bytes)) / 4; | |
772 | ||
773 | return position; | |
774 | } | |
775 | ||
776 | ||
98274f07 | 777 | static inline void hdspm_start_audio(struct hdspm * s) |
763f356c TI |
778 | { |
779 | s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start); | |
780 | hdspm_write(s, HDSPM_controlRegister, s->control_register); | |
781 | } | |
782 | ||
98274f07 | 783 | static inline void hdspm_stop_audio(struct hdspm * s) |
763f356c TI |
784 | { |
785 | s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable); | |
786 | hdspm_write(s, HDSPM_controlRegister, s->control_register); | |
787 | } | |
788 | ||
789 | /* should I silence all or only opened ones ? doit all for first even is 4MB*/ | |
98274f07 | 790 | static inline void hdspm_silence_playback(struct hdspm * hdspm) |
763f356c TI |
791 | { |
792 | int i; | |
793 | int n = hdspm->period_bytes; | |
794 | void *buf = hdspm->playback_buffer; | |
795 | ||
3cee5a60 RB |
796 | if (buf == NULL) |
797 | return; | |
763f356c TI |
798 | |
799 | for (i = 0; i < HDSPM_MAX_CHANNELS; i++) { | |
800 | memset(buf, 0, n); | |
801 | buf += HDSPM_CHANNEL_BUFFER_BYTES; | |
802 | } | |
803 | } | |
804 | ||
98274f07 | 805 | static int hdspm_set_interrupt_interval(struct hdspm * s, unsigned int frames) |
763f356c TI |
806 | { |
807 | int n; | |
808 | ||
809 | spin_lock_irq(&s->lock); | |
810 | ||
811 | frames >>= 7; | |
812 | n = 0; | |
813 | while (frames) { | |
814 | n++; | |
815 | frames >>= 1; | |
816 | } | |
817 | s->control_register &= ~HDSPM_LatencyMask; | |
818 | s->control_register |= hdspm_encode_latency(n); | |
819 | ||
820 | hdspm_write(s, HDSPM_controlRegister, s->control_register); | |
821 | ||
822 | hdspm_compute_period_size(s); | |
823 | ||
824 | spin_unlock_irq(&s->lock); | |
825 | ||
826 | return 0; | |
827 | } | |
828 | ||
ffb2c3c0 RB |
829 | static void hdspm_set_dds_value(struct hdspm *hdspm, int rate) |
830 | { | |
831 | u64 n; | |
832 | u32 r; | |
833 | ||
834 | if (rate >= 112000) | |
835 | rate /= 4; | |
836 | else if (rate >= 56000) | |
837 | rate /= 2; | |
838 | ||
839 | /* RME says n = 104857600000000, but in the windows MADI driver, I see: | |
6534599d | 840 | // return 104857600000000 / rate; // 100 MHz |
ffb2c3c0 RB |
841 | return 110100480000000 / rate; // 105 MHz |
842 | */ | |
ef5fa1a4 | 843 | /* n = 104857600000000ULL; */ /* = 2^20 * 10^8 */ |
ffb2c3c0 RB |
844 | n = 110100480000000ULL; /* Value checked for AES32 and MADI */ |
845 | div64_32(&n, rate, &r); | |
846 | /* n should be less than 2^32 for being written to FREQ register */ | |
847 | snd_assert((n >> 32) == 0); | |
848 | hdspm_write(hdspm, HDSPM_freqReg, (u32)n); | |
849 | } | |
763f356c TI |
850 | |
851 | /* dummy set rate lets see what happens */ | |
98274f07 | 852 | static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally) |
763f356c | 853 | { |
763f356c TI |
854 | int current_rate; |
855 | int rate_bits; | |
856 | int not_set = 0; | |
6534599d | 857 | int current_speed, target_speed; |
763f356c TI |
858 | |
859 | /* ASSUMPTION: hdspm->lock is either set, or there is no need for | |
860 | it (e.g. during module initialization). | |
861 | */ | |
862 | ||
863 | if (!(hdspm->control_register & HDSPM_ClockModeMaster)) { | |
864 | ||
865 | /* SLAVE --- */ | |
866 | if (called_internally) { | |
867 | ||
868 | /* request from ctl or card initialization | |
869 | just make a warning an remember setting | |
870 | for future master mode switching */ | |
871 | ||
ef5fa1a4 TI |
872 | snd_printk(KERN_WARNING "HDSPM: " |
873 | "Warning: device is not running " | |
874 | "as a clock master.\n"); | |
763f356c TI |
875 | not_set = 1; |
876 | } else { | |
877 | ||
878 | /* hw_param request while in AutoSync mode */ | |
879 | int external_freq = | |
880 | hdspm_external_sample_rate(hdspm); | |
881 | ||
ef5fa1a4 TI |
882 | if (hdspm_autosync_ref(hdspm) == |
883 | HDSPM_AUTOSYNC_FROM_NONE) { | |
763f356c | 884 | |
ef5fa1a4 TI |
885 | snd_printk(KERN_WARNING "HDSPM: " |
886 | "Detected no Externel Sync \n"); | |
763f356c TI |
887 | not_set = 1; |
888 | ||
889 | } else if (rate != external_freq) { | |
890 | ||
ef5fa1a4 TI |
891 | snd_printk(KERN_WARNING "HDSPM: " |
892 | "Warning: No AutoSync source for " | |
893 | "requested rate\n"); | |
763f356c TI |
894 | not_set = 1; |
895 | } | |
896 | } | |
897 | } | |
898 | ||
899 | current_rate = hdspm->system_sample_rate; | |
900 | ||
901 | /* Changing between Singe, Double and Quad speed is not | |
902 | allowed if any substreams are open. This is because such a change | |
903 | causes a shift in the location of the DMA buffers and a reduction | |
904 | in the number of available buffers. | |
905 | ||
906 | Note that a similar but essentially insoluble problem exists for | |
907 | externally-driven rate changes. All we can do is to flag rate | |
908 | changes in the read/write routines. | |
909 | */ | |
910 | ||
6534599d RB |
911 | if (current_rate <= 48000) |
912 | current_speed = HDSPM_SPEED_SINGLE; | |
913 | else if (current_rate <= 96000) | |
914 | current_speed = HDSPM_SPEED_DOUBLE; | |
915 | else | |
916 | current_speed = HDSPM_SPEED_QUAD; | |
917 | ||
918 | if (rate <= 48000) | |
919 | target_speed = HDSPM_SPEED_SINGLE; | |
920 | else if (rate <= 96000) | |
921 | target_speed = HDSPM_SPEED_DOUBLE; | |
922 | else | |
923 | target_speed = HDSPM_SPEED_QUAD; | |
3cee5a60 | 924 | |
763f356c TI |
925 | switch (rate) { |
926 | case 32000: | |
763f356c TI |
927 | rate_bits = HDSPM_Frequency32KHz; |
928 | break; | |
929 | case 44100: | |
763f356c TI |
930 | rate_bits = HDSPM_Frequency44_1KHz; |
931 | break; | |
932 | case 48000: | |
763f356c TI |
933 | rate_bits = HDSPM_Frequency48KHz; |
934 | break; | |
935 | case 64000: | |
763f356c TI |
936 | rate_bits = HDSPM_Frequency64KHz; |
937 | break; | |
938 | case 88200: | |
763f356c TI |
939 | rate_bits = HDSPM_Frequency88_2KHz; |
940 | break; | |
941 | case 96000: | |
763f356c TI |
942 | rate_bits = HDSPM_Frequency96KHz; |
943 | break; | |
3cee5a60 | 944 | case 128000: |
3cee5a60 RB |
945 | rate_bits = HDSPM_Frequency128KHz; |
946 | break; | |
947 | case 176400: | |
3cee5a60 RB |
948 | rate_bits = HDSPM_Frequency176_4KHz; |
949 | break; | |
950 | case 192000: | |
3cee5a60 RB |
951 | rate_bits = HDSPM_Frequency192KHz; |
952 | break; | |
763f356c TI |
953 | default: |
954 | return -EINVAL; | |
955 | } | |
956 | ||
6534599d | 957 | if (current_speed != target_speed |
763f356c TI |
958 | && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) { |
959 | snd_printk | |
ef5fa1a4 | 960 | (KERN_ERR "HDSPM: " |
6534599d | 961 | "cannot change from %s speed to %s speed mode " |
ef5fa1a4 | 962 | "(capture PID = %d, playback PID = %d)\n", |
6534599d RB |
963 | hdspm_speed_names[current_speed], |
964 | hdspm_speed_names[target_speed], | |
763f356c TI |
965 | hdspm->capture_pid, hdspm->playback_pid); |
966 | return -EBUSY; | |
967 | } | |
968 | ||
969 | hdspm->control_register &= ~HDSPM_FrequencyMask; | |
970 | hdspm->control_register |= rate_bits; | |
971 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); | |
972 | ||
ffb2c3c0 RB |
973 | /* For AES32, need to set DDS value in FREQ register |
974 | For MADI, also apparently */ | |
975 | hdspm_set_dds_value(hdspm, rate); | |
976 | ||
977 | if (hdspm->is_aes32 && rate != current_rate) | |
978 | hdspm_write(hdspm, HDSPM_eeprom_wr, 0); | |
979 | ||
980 | /* For AES32 and for MADI (at least rev 204), channel_map needs to | |
981 | * always be channel_map_madi_ss, whatever the sample rate */ | |
982 | hdspm->channel_map = channel_map_madi_ss; | |
763f356c TI |
983 | |
984 | hdspm->system_sample_rate = rate; | |
985 | ||
986 | if (not_set != 0) | |
987 | return -1; | |
988 | ||
989 | return 0; | |
990 | } | |
991 | ||
992 | /* mainly for init to 0 on load */ | |
98274f07 | 993 | static void all_in_all_mixer(struct hdspm * hdspm, int sgain) |
763f356c TI |
994 | { |
995 | int i, j; | |
ef5fa1a4 TI |
996 | unsigned int gain; |
997 | ||
998 | if (sgain > UNITY_GAIN) | |
999 | gain = UNITY_GAIN; | |
1000 | else if (sgain < 0) | |
1001 | gain = 0; | |
1002 | else | |
1003 | gain = sgain; | |
763f356c TI |
1004 | |
1005 | for (i = 0; i < HDSPM_MIXER_CHANNELS; i++) | |
1006 | for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) { | |
1007 | hdspm_write_in_gain(hdspm, i, j, gain); | |
1008 | hdspm_write_pb_gain(hdspm, i, j, gain); | |
1009 | } | |
1010 | } | |
1011 | ||
1012 | /*---------------------------------------------------------------------------- | |
1013 | MIDI | |
1014 | ----------------------------------------------------------------------------*/ | |
1015 | ||
ef5fa1a4 TI |
1016 | static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm, |
1017 | int id) | |
763f356c TI |
1018 | { |
1019 | /* the hardware already does the relevant bit-mask with 0xff */ | |
1020 | if (id) | |
1021 | return hdspm_read(hdspm, HDSPM_midiDataIn1); | |
1022 | else | |
1023 | return hdspm_read(hdspm, HDSPM_midiDataIn0); | |
1024 | } | |
1025 | ||
ef5fa1a4 TI |
1026 | static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id, |
1027 | int val) | |
763f356c TI |
1028 | { |
1029 | /* the hardware already does the relevant bit-mask with 0xff */ | |
1030 | if (id) | |
0b76b51e | 1031 | hdspm_write(hdspm, HDSPM_midiDataOut1, val); |
763f356c | 1032 | else |
0b76b51e | 1033 | hdspm_write(hdspm, HDSPM_midiDataOut0, val); |
763f356c TI |
1034 | } |
1035 | ||
98274f07 | 1036 | static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id) |
763f356c TI |
1037 | { |
1038 | if (id) | |
1039 | return (hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xff); | |
1040 | else | |
1041 | return (hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xff); | |
1042 | } | |
1043 | ||
98274f07 | 1044 | static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id) |
763f356c TI |
1045 | { |
1046 | int fifo_bytes_used; | |
1047 | ||
1048 | if (id) | |
ef5fa1a4 | 1049 | fifo_bytes_used = hdspm_read(hdspm, HDSPM_midiStatusOut1); |
763f356c | 1050 | else |
ef5fa1a4 TI |
1051 | fifo_bytes_used = hdspm_read(hdspm, HDSPM_midiStatusOut0); |
1052 | fifo_bytes_used &= 0xff; | |
763f356c TI |
1053 | |
1054 | if (fifo_bytes_used < 128) | |
1055 | return 128 - fifo_bytes_used; | |
1056 | else | |
1057 | return 0; | |
1058 | } | |
1059 | ||
98274f07 | 1060 | static inline void snd_hdspm_flush_midi_input (struct hdspm *hdspm, int id) |
763f356c TI |
1061 | { |
1062 | while (snd_hdspm_midi_input_available (hdspm, id)) | |
1063 | snd_hdspm_midi_read_byte (hdspm, id); | |
1064 | } | |
1065 | ||
98274f07 | 1066 | static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi) |
763f356c TI |
1067 | { |
1068 | unsigned long flags; | |
1069 | int n_pending; | |
1070 | int to_write; | |
1071 | int i; | |
1072 | unsigned char buf[128]; | |
1073 | ||
1074 | /* Output is not interrupt driven */ | |
1075 | ||
1076 | spin_lock_irqsave (&hmidi->lock, flags); | |
ef5fa1a4 TI |
1077 | if (hmidi->output && |
1078 | !snd_rawmidi_transmit_empty (hmidi->output)) { | |
1079 | n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm, | |
1080 | hmidi->id); | |
1081 | if (n_pending > 0) { | |
1082 | if (n_pending > (int)sizeof (buf)) | |
1083 | n_pending = sizeof (buf); | |
1084 | ||
1085 | to_write = snd_rawmidi_transmit (hmidi->output, buf, | |
1086 | n_pending); | |
1087 | if (to_write > 0) { | |
1088 | for (i = 0; i < to_write; ++i) | |
1089 | snd_hdspm_midi_write_byte (hmidi->hdspm, | |
1090 | hmidi->id, | |
1091 | buf[i]); | |
763f356c TI |
1092 | } |
1093 | } | |
1094 | } | |
1095 | spin_unlock_irqrestore (&hmidi->lock, flags); | |
1096 | return 0; | |
1097 | } | |
1098 | ||
98274f07 | 1099 | static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi) |
763f356c | 1100 | { |
ef5fa1a4 TI |
1101 | unsigned char buf[128]; /* this buffer is designed to match the MIDI |
1102 | * input FIFO size | |
1103 | */ | |
763f356c TI |
1104 | unsigned long flags; |
1105 | int n_pending; | |
1106 | int i; | |
1107 | ||
1108 | spin_lock_irqsave (&hmidi->lock, flags); | |
ef5fa1a4 TI |
1109 | n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id); |
1110 | if (n_pending > 0) { | |
763f356c | 1111 | if (hmidi->input) { |
ef5fa1a4 | 1112 | if (n_pending > (int)sizeof (buf)) |
763f356c | 1113 | n_pending = sizeof (buf); |
ef5fa1a4 TI |
1114 | for (i = 0; i < n_pending; ++i) |
1115 | buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm, | |
1116 | hmidi->id); | |
1117 | if (n_pending) | |
1118 | snd_rawmidi_receive (hmidi->input, buf, | |
1119 | n_pending); | |
763f356c TI |
1120 | } else { |
1121 | /* flush the MIDI input FIFO */ | |
ef5fa1a4 TI |
1122 | while (n_pending--) |
1123 | snd_hdspm_midi_read_byte (hmidi->hdspm, | |
1124 | hmidi->id); | |
763f356c TI |
1125 | } |
1126 | } | |
1127 | hmidi->pending = 0; | |
ef5fa1a4 | 1128 | if (hmidi->id) |
763f356c | 1129 | hmidi->hdspm->control_register |= HDSPM_Midi1InterruptEnable; |
ef5fa1a4 | 1130 | else |
763f356c | 1131 | hmidi->hdspm->control_register |= HDSPM_Midi0InterruptEnable; |
ef5fa1a4 TI |
1132 | hdspm_write(hmidi->hdspm, HDSPM_controlRegister, |
1133 | hmidi->hdspm->control_register); | |
763f356c TI |
1134 | spin_unlock_irqrestore (&hmidi->lock, flags); |
1135 | return snd_hdspm_midi_output_write (hmidi); | |
1136 | } | |
1137 | ||
ef5fa1a4 TI |
1138 | static void |
1139 | snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) | |
763f356c | 1140 | { |
98274f07 TI |
1141 | struct hdspm *hdspm; |
1142 | struct hdspm_midi *hmidi; | |
763f356c TI |
1143 | unsigned long flags; |
1144 | u32 ie; | |
1145 | ||
ef5fa1a4 | 1146 | hmidi = substream->rmidi->private_data; |
763f356c | 1147 | hdspm = hmidi->hdspm; |
ef5fa1a4 TI |
1148 | ie = hmidi->id ? |
1149 | HDSPM_Midi1InterruptEnable : HDSPM_Midi0InterruptEnable; | |
763f356c TI |
1150 | spin_lock_irqsave (&hdspm->lock, flags); |
1151 | if (up) { | |
1152 | if (!(hdspm->control_register & ie)) { | |
1153 | snd_hdspm_flush_midi_input (hdspm, hmidi->id); | |
1154 | hdspm->control_register |= ie; | |
1155 | } | |
1156 | } else { | |
1157 | hdspm->control_register &= ~ie; | |
1158 | } | |
1159 | ||
1160 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); | |
1161 | spin_unlock_irqrestore (&hdspm->lock, flags); | |
1162 | } | |
1163 | ||
1164 | static void snd_hdspm_midi_output_timer(unsigned long data) | |
1165 | { | |
98274f07 | 1166 | struct hdspm_midi *hmidi = (struct hdspm_midi *) data; |
763f356c TI |
1167 | unsigned long flags; |
1168 | ||
1169 | snd_hdspm_midi_output_write(hmidi); | |
1170 | spin_lock_irqsave (&hmidi->lock, flags); | |
1171 | ||
1172 | /* this does not bump hmidi->istimer, because the | |
1173 | kernel automatically removed the timer when it | |
1174 | expired, and we are now adding it back, thus | |
1175 | leaving istimer wherever it was set before. | |
1176 | */ | |
1177 | ||
1178 | if (hmidi->istimer) { | |
1179 | hmidi->timer.expires = 1 + jiffies; | |
1180 | add_timer(&hmidi->timer); | |
1181 | } | |
1182 | ||
1183 | spin_unlock_irqrestore (&hmidi->lock, flags); | |
1184 | } | |
1185 | ||
ef5fa1a4 TI |
1186 | static void |
1187 | snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) | |
763f356c | 1188 | { |
98274f07 | 1189 | struct hdspm_midi *hmidi; |
763f356c TI |
1190 | unsigned long flags; |
1191 | ||
ef5fa1a4 | 1192 | hmidi = substream->rmidi->private_data; |
763f356c TI |
1193 | spin_lock_irqsave (&hmidi->lock, flags); |
1194 | if (up) { | |
1195 | if (!hmidi->istimer) { | |
1196 | init_timer(&hmidi->timer); | |
1197 | hmidi->timer.function = snd_hdspm_midi_output_timer; | |
1198 | hmidi->timer.data = (unsigned long) hmidi; | |
1199 | hmidi->timer.expires = 1 + jiffies; | |
1200 | add_timer(&hmidi->timer); | |
1201 | hmidi->istimer++; | |
1202 | } | |
1203 | } else { | |
ef5fa1a4 | 1204 | if (hmidi->istimer && --hmidi->istimer <= 0) |
763f356c | 1205 | del_timer (&hmidi->timer); |
763f356c TI |
1206 | } |
1207 | spin_unlock_irqrestore (&hmidi->lock, flags); | |
1208 | if (up) | |
1209 | snd_hdspm_midi_output_write(hmidi); | |
1210 | } | |
1211 | ||
98274f07 | 1212 | static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream) |
763f356c | 1213 | { |
98274f07 | 1214 | struct hdspm_midi *hmidi; |
763f356c | 1215 | |
ef5fa1a4 | 1216 | hmidi = substream->rmidi->private_data; |
763f356c TI |
1217 | spin_lock_irq (&hmidi->lock); |
1218 | snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id); | |
1219 | hmidi->input = substream; | |
1220 | spin_unlock_irq (&hmidi->lock); | |
1221 | ||
1222 | return 0; | |
1223 | } | |
1224 | ||
98274f07 | 1225 | static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream) |
763f356c | 1226 | { |
98274f07 | 1227 | struct hdspm_midi *hmidi; |
763f356c | 1228 | |
ef5fa1a4 | 1229 | hmidi = substream->rmidi->private_data; |
763f356c TI |
1230 | spin_lock_irq (&hmidi->lock); |
1231 | hmidi->output = substream; | |
1232 | spin_unlock_irq (&hmidi->lock); | |
1233 | ||
1234 | return 0; | |
1235 | } | |
1236 | ||
98274f07 | 1237 | static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream) |
763f356c | 1238 | { |
98274f07 | 1239 | struct hdspm_midi *hmidi; |
763f356c TI |
1240 | |
1241 | snd_hdspm_midi_input_trigger (substream, 0); | |
1242 | ||
ef5fa1a4 | 1243 | hmidi = substream->rmidi->private_data; |
763f356c TI |
1244 | spin_lock_irq (&hmidi->lock); |
1245 | hmidi->input = NULL; | |
1246 | spin_unlock_irq (&hmidi->lock); | |
1247 | ||
1248 | return 0; | |
1249 | } | |
1250 | ||
98274f07 | 1251 | static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream) |
763f356c | 1252 | { |
98274f07 | 1253 | struct hdspm_midi *hmidi; |
763f356c TI |
1254 | |
1255 | snd_hdspm_midi_output_trigger (substream, 0); | |
1256 | ||
ef5fa1a4 | 1257 | hmidi = substream->rmidi->private_data; |
763f356c TI |
1258 | spin_lock_irq (&hmidi->lock); |
1259 | hmidi->output = NULL; | |
1260 | spin_unlock_irq (&hmidi->lock); | |
1261 | ||
1262 | return 0; | |
1263 | } | |
1264 | ||
98274f07 | 1265 | static struct snd_rawmidi_ops snd_hdspm_midi_output = |
763f356c TI |
1266 | { |
1267 | .open = snd_hdspm_midi_output_open, | |
1268 | .close = snd_hdspm_midi_output_close, | |
1269 | .trigger = snd_hdspm_midi_output_trigger, | |
1270 | }; | |
1271 | ||
98274f07 | 1272 | static struct snd_rawmidi_ops snd_hdspm_midi_input = |
763f356c TI |
1273 | { |
1274 | .open = snd_hdspm_midi_input_open, | |
1275 | .close = snd_hdspm_midi_input_close, | |
1276 | .trigger = snd_hdspm_midi_input_trigger, | |
1277 | }; | |
1278 | ||
ef5fa1a4 TI |
1279 | static int __devinit snd_hdspm_create_midi (struct snd_card *card, |
1280 | struct hdspm *hdspm, int id) | |
763f356c TI |
1281 | { |
1282 | int err; | |
1283 | char buf[32]; | |
1284 | ||
1285 | hdspm->midi[id].id = id; | |
763f356c | 1286 | hdspm->midi[id].hdspm = hdspm; |
763f356c TI |
1287 | spin_lock_init (&hdspm->midi[id].lock); |
1288 | ||
1289 | sprintf (buf, "%s MIDI %d", card->shortname, id+1); | |
ef5fa1a4 TI |
1290 | err = snd_rawmidi_new (card, buf, id, 1, 1, &hdspm->midi[id].rmidi); |
1291 | if (err < 0) | |
763f356c TI |
1292 | return err; |
1293 | ||
1294 | sprintf (hdspm->midi[id].rmidi->name, "%s MIDI %d", card->id, id+1); | |
1295 | hdspm->midi[id].rmidi->private_data = &hdspm->midi[id]; | |
1296 | ||
ef5fa1a4 TI |
1297 | snd_rawmidi_set_ops(hdspm->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, |
1298 | &snd_hdspm_midi_output); | |
1299 | snd_rawmidi_set_ops(hdspm->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, | |
1300 | &snd_hdspm_midi_input); | |
763f356c TI |
1301 | |
1302 | hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | | |
1303 | SNDRV_RAWMIDI_INFO_INPUT | | |
1304 | SNDRV_RAWMIDI_INFO_DUPLEX; | |
1305 | ||
1306 | return 0; | |
1307 | } | |
1308 | ||
1309 | ||
1310 | static void hdspm_midi_tasklet(unsigned long arg) | |
1311 | { | |
98274f07 | 1312 | struct hdspm *hdspm = (struct hdspm *)arg; |
763f356c TI |
1313 | |
1314 | if (hdspm->midi[0].pending) | |
1315 | snd_hdspm_midi_input_read (&hdspm->midi[0]); | |
1316 | if (hdspm->midi[1].pending) | |
1317 | snd_hdspm_midi_input_read (&hdspm->midi[1]); | |
1318 | } | |
1319 | ||
1320 | ||
1321 | /*----------------------------------------------------------------------------- | |
1322 | Status Interface | |
1323 | ----------------------------------------------------------------------------*/ | |
1324 | ||
1325 | /* get the system sample rate which is set */ | |
1326 | ||
1327 | #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \ | |
67ed4161 | 1328 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
763f356c TI |
1329 | .name = xname, \ |
1330 | .index = xindex, \ | |
1331 | .access = SNDRV_CTL_ELEM_ACCESS_READ, \ | |
1332 | .info = snd_hdspm_info_system_sample_rate, \ | |
1333 | .get = snd_hdspm_get_system_sample_rate \ | |
1334 | } | |
1335 | ||
98274f07 TI |
1336 | static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol, |
1337 | struct snd_ctl_elem_info *uinfo) | |
763f356c TI |
1338 | { |
1339 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; | |
1340 | uinfo->count = 1; | |
1341 | return 0; | |
1342 | } | |
1343 | ||
98274f07 TI |
1344 | static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol, |
1345 | struct snd_ctl_elem_value * | |
763f356c TI |
1346 | ucontrol) |
1347 | { | |
98274f07 | 1348 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
1349 | |
1350 | ucontrol->value.enumerated.item[0] = hdspm->system_sample_rate; | |
1351 | return 0; | |
1352 | } | |
1353 | ||
1354 | #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \ | |
67ed4161 | 1355 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
763f356c TI |
1356 | .name = xname, \ |
1357 | .index = xindex, \ | |
1358 | .access = SNDRV_CTL_ELEM_ACCESS_READ, \ | |
1359 | .info = snd_hdspm_info_autosync_sample_rate, \ | |
1360 | .get = snd_hdspm_get_autosync_sample_rate \ | |
1361 | } | |
1362 | ||
98274f07 TI |
1363 | static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, |
1364 | struct snd_ctl_elem_info *uinfo) | |
763f356c TI |
1365 | { |
1366 | static char *texts[] = { "32000", "44100", "48000", | |
1367 | "64000", "88200", "96000", | |
1368 | "128000", "176400", "192000", | |
1369 | "None" | |
1370 | }; | |
1371 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
1372 | uinfo->count = 1; | |
1373 | uinfo->value.enumerated.items = 10; | |
1374 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
1375 | uinfo->value.enumerated.item = | |
1376 | uinfo->value.enumerated.items - 1; | |
1377 | strcpy(uinfo->value.enumerated.name, | |
1378 | texts[uinfo->value.enumerated.item]); | |
1379 | return 0; | |
1380 | } | |
1381 | ||
98274f07 TI |
1382 | static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, |
1383 | struct snd_ctl_elem_value * | |
763f356c TI |
1384 | ucontrol) |
1385 | { | |
98274f07 | 1386 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
1387 | |
1388 | switch (hdspm_external_sample_rate(hdspm)) { | |
1389 | case 32000: | |
1390 | ucontrol->value.enumerated.item[0] = 0; | |
1391 | break; | |
1392 | case 44100: | |
1393 | ucontrol->value.enumerated.item[0] = 1; | |
1394 | break; | |
1395 | case 48000: | |
1396 | ucontrol->value.enumerated.item[0] = 2; | |
1397 | break; | |
1398 | case 64000: | |
1399 | ucontrol->value.enumerated.item[0] = 3; | |
1400 | break; | |
1401 | case 88200: | |
1402 | ucontrol->value.enumerated.item[0] = 4; | |
1403 | break; | |
1404 | case 96000: | |
1405 | ucontrol->value.enumerated.item[0] = 5; | |
1406 | break; | |
1407 | case 128000: | |
1408 | ucontrol->value.enumerated.item[0] = 6; | |
1409 | break; | |
1410 | case 176400: | |
1411 | ucontrol->value.enumerated.item[0] = 7; | |
1412 | break; | |
1413 | case 192000: | |
1414 | ucontrol->value.enumerated.item[0] = 8; | |
1415 | break; | |
1416 | ||
1417 | default: | |
1418 | ucontrol->value.enumerated.item[0] = 9; | |
1419 | } | |
1420 | return 0; | |
1421 | } | |
1422 | ||
1423 | #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \ | |
67ed4161 | 1424 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
763f356c TI |
1425 | .name = xname, \ |
1426 | .index = xindex, \ | |
1427 | .access = SNDRV_CTL_ELEM_ACCESS_READ, \ | |
1428 | .info = snd_hdspm_info_system_clock_mode, \ | |
1429 | .get = snd_hdspm_get_system_clock_mode, \ | |
1430 | } | |
1431 | ||
1432 | ||
1433 | ||
98274f07 | 1434 | static int hdspm_system_clock_mode(struct hdspm * hdspm) |
763f356c TI |
1435 | { |
1436 | /* Always reflect the hardware info, rme is never wrong !!!! */ | |
1437 | ||
1438 | if (hdspm->control_register & HDSPM_ClockModeMaster) | |
1439 | return 0; | |
1440 | return 1; | |
1441 | } | |
1442 | ||
98274f07 TI |
1443 | static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol, |
1444 | struct snd_ctl_elem_info *uinfo) | |
763f356c TI |
1445 | { |
1446 | static char *texts[] = { "Master", "Slave" }; | |
1447 | ||
1448 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
1449 | uinfo->count = 1; | |
1450 | uinfo->value.enumerated.items = 2; | |
1451 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
1452 | uinfo->value.enumerated.item = | |
1453 | uinfo->value.enumerated.items - 1; | |
1454 | strcpy(uinfo->value.enumerated.name, | |
1455 | texts[uinfo->value.enumerated.item]); | |
1456 | return 0; | |
1457 | } | |
1458 | ||
98274f07 TI |
1459 | static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol, |
1460 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 1461 | { |
98274f07 | 1462 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
1463 | |
1464 | ucontrol->value.enumerated.item[0] = | |
1465 | hdspm_system_clock_mode(hdspm); | |
1466 | return 0; | |
1467 | } | |
1468 | ||
1469 | #define HDSPM_CLOCK_SOURCE(xname, xindex) \ | |
67ed4161 | 1470 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
763f356c TI |
1471 | .name = xname, \ |
1472 | .index = xindex, \ | |
1473 | .info = snd_hdspm_info_clock_source, \ | |
1474 | .get = snd_hdspm_get_clock_source, \ | |
1475 | .put = snd_hdspm_put_clock_source \ | |
1476 | } | |
1477 | ||
98274f07 | 1478 | static int hdspm_clock_source(struct hdspm * hdspm) |
763f356c TI |
1479 | { |
1480 | if (hdspm->control_register & HDSPM_ClockModeMaster) { | |
1481 | switch (hdspm->system_sample_rate) { | |
1482 | case 32000: | |
1483 | return 1; | |
1484 | case 44100: | |
1485 | return 2; | |
1486 | case 48000: | |
1487 | return 3; | |
1488 | case 64000: | |
1489 | return 4; | |
1490 | case 88200: | |
1491 | return 5; | |
1492 | case 96000: | |
1493 | return 6; | |
1494 | case 128000: | |
1495 | return 7; | |
1496 | case 176400: | |
1497 | return 8; | |
1498 | case 192000: | |
1499 | return 9; | |
1500 | default: | |
1501 | return 3; | |
1502 | } | |
1503 | } else { | |
1504 | return 0; | |
1505 | } | |
1506 | } | |
1507 | ||
98274f07 | 1508 | static int hdspm_set_clock_source(struct hdspm * hdspm, int mode) |
763f356c TI |
1509 | { |
1510 | int rate; | |
1511 | switch (mode) { | |
1512 | ||
1513 | case HDSPM_CLOCK_SOURCE_AUTOSYNC: | |
1514 | if (hdspm_external_sample_rate(hdspm) != 0) { | |
1515 | hdspm->control_register &= ~HDSPM_ClockModeMaster; | |
1516 | hdspm_write(hdspm, HDSPM_controlRegister, | |
1517 | hdspm->control_register); | |
1518 | return 0; | |
1519 | } | |
1520 | return -1; | |
1521 | case HDSPM_CLOCK_SOURCE_INTERNAL_32KHZ: | |
1522 | rate = 32000; | |
1523 | break; | |
1524 | case HDSPM_CLOCK_SOURCE_INTERNAL_44_1KHZ: | |
1525 | rate = 44100; | |
1526 | break; | |
1527 | case HDSPM_CLOCK_SOURCE_INTERNAL_48KHZ: | |
1528 | rate = 48000; | |
1529 | break; | |
1530 | case HDSPM_CLOCK_SOURCE_INTERNAL_64KHZ: | |
1531 | rate = 64000; | |
1532 | break; | |
1533 | case HDSPM_CLOCK_SOURCE_INTERNAL_88_2KHZ: | |
1534 | rate = 88200; | |
1535 | break; | |
1536 | case HDSPM_CLOCK_SOURCE_INTERNAL_96KHZ: | |
1537 | rate = 96000; | |
1538 | break; | |
1539 | case HDSPM_CLOCK_SOURCE_INTERNAL_128KHZ: | |
1540 | rate = 128000; | |
1541 | break; | |
1542 | case HDSPM_CLOCK_SOURCE_INTERNAL_176_4KHZ: | |
1543 | rate = 176400; | |
1544 | break; | |
1545 | case HDSPM_CLOCK_SOURCE_INTERNAL_192KHZ: | |
1546 | rate = 192000; | |
1547 | break; | |
1548 | ||
1549 | default: | |
1550 | rate = 44100; | |
1551 | } | |
1552 | hdspm->control_register |= HDSPM_ClockModeMaster; | |
1553 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); | |
1554 | hdspm_set_rate(hdspm, rate, 1); | |
1555 | return 0; | |
1556 | } | |
1557 | ||
98274f07 TI |
1558 | static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol, |
1559 | struct snd_ctl_elem_info *uinfo) | |
763f356c TI |
1560 | { |
1561 | static char *texts[] = { "AutoSync", | |
1562 | "Internal 32.0 kHz", "Internal 44.1 kHz", | |
1563 | "Internal 48.0 kHz", | |
1564 | "Internal 64.0 kHz", "Internal 88.2 kHz", | |
1565 | "Internal 96.0 kHz", | |
1566 | "Internal 128.0 kHz", "Internal 176.4 kHz", | |
1567 | "Internal 192.0 kHz" | |
1568 | }; | |
1569 | ||
1570 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
1571 | uinfo->count = 1; | |
1572 | uinfo->value.enumerated.items = 10; | |
1573 | ||
1574 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
1575 | uinfo->value.enumerated.item = | |
1576 | uinfo->value.enumerated.items - 1; | |
1577 | ||
1578 | strcpy(uinfo->value.enumerated.name, | |
1579 | texts[uinfo->value.enumerated.item]); | |
1580 | ||
1581 | return 0; | |
1582 | } | |
1583 | ||
98274f07 TI |
1584 | static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol, |
1585 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 1586 | { |
98274f07 | 1587 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
1588 | |
1589 | ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm); | |
1590 | return 0; | |
1591 | } | |
1592 | ||
98274f07 TI |
1593 | static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol, |
1594 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 1595 | { |
98274f07 | 1596 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
1597 | int change; |
1598 | int val; | |
1599 | ||
1600 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
1601 | return -EBUSY; | |
1602 | val = ucontrol->value.enumerated.item[0]; | |
1603 | if (val < 0) | |
1604 | val = 0; | |
6534599d RB |
1605 | if (val > 9) |
1606 | val = 9; | |
763f356c TI |
1607 | spin_lock_irq(&hdspm->lock); |
1608 | if (val != hdspm_clock_source(hdspm)) | |
1609 | change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0; | |
1610 | else | |
1611 | change = 0; | |
1612 | spin_unlock_irq(&hdspm->lock); | |
1613 | return change; | |
1614 | } | |
1615 | ||
1616 | #define HDSPM_PREF_SYNC_REF(xname, xindex) \ | |
67ed4161 | 1617 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
763f356c TI |
1618 | .name = xname, \ |
1619 | .index = xindex, \ | |
1620 | .info = snd_hdspm_info_pref_sync_ref, \ | |
1621 | .get = snd_hdspm_get_pref_sync_ref, \ | |
1622 | .put = snd_hdspm_put_pref_sync_ref \ | |
1623 | } | |
1624 | ||
98274f07 | 1625 | static int hdspm_pref_sync_ref(struct hdspm * hdspm) |
763f356c TI |
1626 | { |
1627 | /* Notice that this looks at the requested sync source, | |
1628 | not the one actually in use. | |
1629 | */ | |
3cee5a60 RB |
1630 | if (hdspm->is_aes32) { |
1631 | switch (hdspm->control_register & HDSPM_SyncRefMask) { | |
1632 | /* number gives AES index, except for 0 which | |
1633 | corresponds to WordClock */ | |
1634 | case 0: return 0; | |
1635 | case HDSPM_SyncRef0: return 1; | |
1636 | case HDSPM_SyncRef1: return 2; | |
1637 | case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; | |
1638 | case HDSPM_SyncRef2: return 4; | |
1639 | case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; | |
1640 | case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; | |
1641 | case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0: return 7; | |
1642 | case HDSPM_SyncRef3: return 8; | |
1643 | } | |
1644 | } else { | |
1645 | switch (hdspm->control_register & HDSPM_SyncRefMask) { | |
1646 | case HDSPM_SyncRef_Word: | |
1647 | return HDSPM_SYNC_FROM_WORD; | |
1648 | case HDSPM_SyncRef_MADI: | |
1649 | return HDSPM_SYNC_FROM_MADI; | |
1650 | } | |
763f356c TI |
1651 | } |
1652 | ||
1653 | return HDSPM_SYNC_FROM_WORD; | |
1654 | } | |
1655 | ||
98274f07 | 1656 | static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref) |
763f356c TI |
1657 | { |
1658 | hdspm->control_register &= ~HDSPM_SyncRefMask; | |
1659 | ||
3cee5a60 RB |
1660 | if (hdspm->is_aes32) { |
1661 | switch (pref) { | |
1662 | case 0: | |
1663 | hdspm->control_register |= 0; | |
1664 | break; | |
1665 | case 1: | |
1666 | hdspm->control_register |= HDSPM_SyncRef0; | |
1667 | break; | |
1668 | case 2: | |
1669 | hdspm->control_register |= HDSPM_SyncRef1; | |
1670 | break; | |
1671 | case 3: | |
1672 | hdspm->control_register |= HDSPM_SyncRef1+HDSPM_SyncRef0; | |
1673 | break; | |
1674 | case 4: | |
1675 | hdspm->control_register |= HDSPM_SyncRef2; | |
1676 | break; | |
1677 | case 5: | |
1678 | hdspm->control_register |= HDSPM_SyncRef2+HDSPM_SyncRef0; | |
1679 | break; | |
1680 | case 6: | |
1681 | hdspm->control_register |= HDSPM_SyncRef2+HDSPM_SyncRef1; | |
1682 | break; | |
1683 | case 7: | |
ef5fa1a4 TI |
1684 | hdspm->control_register |= |
1685 | HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0; | |
3cee5a60 RB |
1686 | break; |
1687 | case 8: | |
1688 | hdspm->control_register |= HDSPM_SyncRef3; | |
1689 | break; | |
1690 | default: | |
1691 | return -1; | |
1692 | } | |
1693 | } else { | |
1694 | switch (pref) { | |
1695 | case HDSPM_SYNC_FROM_MADI: | |
1696 | hdspm->control_register |= HDSPM_SyncRef_MADI; | |
1697 | break; | |
1698 | case HDSPM_SYNC_FROM_WORD: | |
1699 | hdspm->control_register |= HDSPM_SyncRef_Word; | |
1700 | break; | |
1701 | default: | |
1702 | return -1; | |
1703 | } | |
763f356c TI |
1704 | } |
1705 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); | |
1706 | return 0; | |
1707 | } | |
1708 | ||
98274f07 TI |
1709 | static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol, |
1710 | struct snd_ctl_elem_info *uinfo) | |
763f356c | 1711 | { |
3cee5a60 | 1712 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c | 1713 | |
3cee5a60 RB |
1714 | if (hdspm->is_aes32) { |
1715 | static char *texts[] = { "Word", "AES1", "AES2", "AES3", | |
1716 | "AES4", "AES5", "AES6", "AES7", "AES8" }; | |
763f356c | 1717 | |
3cee5a60 RB |
1718 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; |
1719 | uinfo->count = 1; | |
763f356c | 1720 | |
3cee5a60 RB |
1721 | uinfo->value.enumerated.items = 9; |
1722 | ||
ef5fa1a4 TI |
1723 | if (uinfo->value.enumerated.item >= |
1724 | uinfo->value.enumerated.items) | |
3cee5a60 RB |
1725 | uinfo->value.enumerated.item = |
1726 | uinfo->value.enumerated.items - 1; | |
1727 | strcpy(uinfo->value.enumerated.name, | |
1728 | texts[uinfo->value.enumerated.item]); | |
1729 | } else { | |
1730 | static char *texts[] = { "Word", "MADI" }; | |
1731 | ||
1732 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
1733 | uinfo->count = 1; | |
1734 | ||
1735 | uinfo->value.enumerated.items = 2; | |
1736 | ||
ef5fa1a4 TI |
1737 | if (uinfo->value.enumerated.item >= |
1738 | uinfo->value.enumerated.items) | |
3cee5a60 RB |
1739 | uinfo->value.enumerated.item = |
1740 | uinfo->value.enumerated.items - 1; | |
1741 | strcpy(uinfo->value.enumerated.name, | |
1742 | texts[uinfo->value.enumerated.item]); | |
1743 | } | |
763f356c TI |
1744 | return 0; |
1745 | } | |
1746 | ||
98274f07 TI |
1747 | static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol, |
1748 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 1749 | { |
98274f07 | 1750 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
1751 | |
1752 | ucontrol->value.enumerated.item[0] = hdspm_pref_sync_ref(hdspm); | |
1753 | return 0; | |
1754 | } | |
1755 | ||
98274f07 TI |
1756 | static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol, |
1757 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 1758 | { |
98274f07 | 1759 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
1760 | int change, max; |
1761 | unsigned int val; | |
1762 | ||
3cee5a60 | 1763 | max = hdspm->is_aes32 ? 9 : 2; |
763f356c TI |
1764 | |
1765 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
1766 | return -EBUSY; | |
1767 | ||
1768 | val = ucontrol->value.enumerated.item[0] % max; | |
1769 | ||
1770 | spin_lock_irq(&hdspm->lock); | |
1771 | change = (int) val != hdspm_pref_sync_ref(hdspm); | |
1772 | hdspm_set_pref_sync_ref(hdspm, val); | |
1773 | spin_unlock_irq(&hdspm->lock); | |
1774 | return change; | |
1775 | } | |
1776 | ||
1777 | #define HDSPM_AUTOSYNC_REF(xname, xindex) \ | |
67ed4161 | 1778 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
763f356c TI |
1779 | .name = xname, \ |
1780 | .index = xindex, \ | |
1781 | .access = SNDRV_CTL_ELEM_ACCESS_READ, \ | |
1782 | .info = snd_hdspm_info_autosync_ref, \ | |
1783 | .get = snd_hdspm_get_autosync_ref, \ | |
1784 | } | |
1785 | ||
98274f07 | 1786 | static int hdspm_autosync_ref(struct hdspm * hdspm) |
763f356c | 1787 | { |
3cee5a60 RB |
1788 | if (hdspm->is_aes32) { |
1789 | unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister); | |
ef5fa1a4 TI |
1790 | unsigned int syncref = (status >> HDSPM_AES32_syncref_bit) & |
1791 | 0xF; | |
3cee5a60 RB |
1792 | if (syncref == 0) |
1793 | return HDSPM_AES32_AUTOSYNC_FROM_WORD; | |
1794 | if (syncref <= 8) | |
1795 | return syncref; | |
1796 | return HDSPM_AES32_AUTOSYNC_FROM_NONE; | |
1797 | } else { | |
1798 | /* This looks at the autosync selected sync reference */ | |
1799 | unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2); | |
1800 | ||
1801 | switch (status2 & HDSPM_SelSyncRefMask) { | |
1802 | case HDSPM_SelSyncRef_WORD: | |
1803 | return HDSPM_AUTOSYNC_FROM_WORD; | |
1804 | case HDSPM_SelSyncRef_MADI: | |
1805 | return HDSPM_AUTOSYNC_FROM_MADI; | |
1806 | case HDSPM_SelSyncRef_NVALID: | |
1807 | return HDSPM_AUTOSYNC_FROM_NONE; | |
1808 | default: | |
1809 | return 0; | |
1810 | } | |
763f356c | 1811 | |
763f356c TI |
1812 | return 0; |
1813 | } | |
763f356c TI |
1814 | } |
1815 | ||
98274f07 TI |
1816 | static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol, |
1817 | struct snd_ctl_elem_info *uinfo) | |
763f356c | 1818 | { |
3cee5a60 | 1819 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c | 1820 | |
3cee5a60 RB |
1821 | if (hdspm->is_aes32) { |
1822 | static char *texts[] = { "WordClock", "AES1", "AES2", "AES3", | |
1823 | "AES4", "AES5", "AES6", "AES7", "AES8", "None"}; | |
1824 | ||
1825 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
1826 | uinfo->count = 1; | |
1827 | uinfo->value.enumerated.items = 10; | |
ef5fa1a4 TI |
1828 | if (uinfo->value.enumerated.item >= |
1829 | uinfo->value.enumerated.items) | |
3cee5a60 RB |
1830 | uinfo->value.enumerated.item = |
1831 | uinfo->value.enumerated.items - 1; | |
1832 | strcpy(uinfo->value.enumerated.name, | |
1833 | texts[uinfo->value.enumerated.item]); | |
ef5fa1a4 | 1834 | } else { |
3cee5a60 RB |
1835 | static char *texts[] = { "WordClock", "MADI", "None" }; |
1836 | ||
1837 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
1838 | uinfo->count = 1; | |
1839 | uinfo->value.enumerated.items = 3; | |
ef5fa1a4 TI |
1840 | if (uinfo->value.enumerated.item >= |
1841 | uinfo->value.enumerated.items) | |
3cee5a60 RB |
1842 | uinfo->value.enumerated.item = |
1843 | uinfo->value.enumerated.items - 1; | |
1844 | strcpy(uinfo->value.enumerated.name, | |
1845 | texts[uinfo->value.enumerated.item]); | |
1846 | } | |
763f356c TI |
1847 | return 0; |
1848 | } | |
1849 | ||
98274f07 TI |
1850 | static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol, |
1851 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 1852 | { |
98274f07 | 1853 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c | 1854 | |
6534599d | 1855 | ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm); |
763f356c TI |
1856 | return 0; |
1857 | } | |
1858 | ||
1859 | #define HDSPM_LINE_OUT(xname, xindex) \ | |
67ed4161 | 1860 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
763f356c TI |
1861 | .name = xname, \ |
1862 | .index = xindex, \ | |
1863 | .info = snd_hdspm_info_line_out, \ | |
1864 | .get = snd_hdspm_get_line_out, \ | |
1865 | .put = snd_hdspm_put_line_out \ | |
1866 | } | |
1867 | ||
98274f07 | 1868 | static int hdspm_line_out(struct hdspm * hdspm) |
763f356c TI |
1869 | { |
1870 | return (hdspm->control_register & HDSPM_LineOut) ? 1 : 0; | |
1871 | } | |
1872 | ||
1873 | ||
98274f07 | 1874 | static int hdspm_set_line_output(struct hdspm * hdspm, int out) |
763f356c TI |
1875 | { |
1876 | if (out) | |
1877 | hdspm->control_register |= HDSPM_LineOut; | |
1878 | else | |
1879 | hdspm->control_register &= ~HDSPM_LineOut; | |
1880 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); | |
1881 | ||
1882 | return 0; | |
1883 | } | |
1884 | ||
a5ce8890 | 1885 | #define snd_hdspm_info_line_out snd_ctl_boolean_mono_info |
763f356c | 1886 | |
98274f07 TI |
1887 | static int snd_hdspm_get_line_out(struct snd_kcontrol *kcontrol, |
1888 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 1889 | { |
98274f07 | 1890 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
1891 | |
1892 | spin_lock_irq(&hdspm->lock); | |
1893 | ucontrol->value.integer.value[0] = hdspm_line_out(hdspm); | |
1894 | spin_unlock_irq(&hdspm->lock); | |
1895 | return 0; | |
1896 | } | |
1897 | ||
98274f07 TI |
1898 | static int snd_hdspm_put_line_out(struct snd_kcontrol *kcontrol, |
1899 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 1900 | { |
98274f07 | 1901 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
1902 | int change; |
1903 | unsigned int val; | |
1904 | ||
1905 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
1906 | return -EBUSY; | |
1907 | val = ucontrol->value.integer.value[0] & 1; | |
1908 | spin_lock_irq(&hdspm->lock); | |
1909 | change = (int) val != hdspm_line_out(hdspm); | |
1910 | hdspm_set_line_output(hdspm, val); | |
1911 | spin_unlock_irq(&hdspm->lock); | |
1912 | return change; | |
1913 | } | |
1914 | ||
1915 | #define HDSPM_TX_64(xname, xindex) \ | |
67ed4161 | 1916 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
763f356c TI |
1917 | .name = xname, \ |
1918 | .index = xindex, \ | |
1919 | .info = snd_hdspm_info_tx_64, \ | |
1920 | .get = snd_hdspm_get_tx_64, \ | |
1921 | .put = snd_hdspm_put_tx_64 \ | |
1922 | } | |
1923 | ||
98274f07 | 1924 | static int hdspm_tx_64(struct hdspm * hdspm) |
763f356c TI |
1925 | { |
1926 | return (hdspm->control_register & HDSPM_TX_64ch) ? 1 : 0; | |
1927 | } | |
1928 | ||
98274f07 | 1929 | static int hdspm_set_tx_64(struct hdspm * hdspm, int out) |
763f356c TI |
1930 | { |
1931 | if (out) | |
1932 | hdspm->control_register |= HDSPM_TX_64ch; | |
1933 | else | |
1934 | hdspm->control_register &= ~HDSPM_TX_64ch; | |
1935 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); | |
1936 | ||
1937 | return 0; | |
1938 | } | |
1939 | ||
a5ce8890 | 1940 | #define snd_hdspm_info_tx_64 snd_ctl_boolean_mono_info |
763f356c | 1941 | |
98274f07 TI |
1942 | static int snd_hdspm_get_tx_64(struct snd_kcontrol *kcontrol, |
1943 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 1944 | { |
98274f07 | 1945 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
1946 | |
1947 | spin_lock_irq(&hdspm->lock); | |
1948 | ucontrol->value.integer.value[0] = hdspm_tx_64(hdspm); | |
1949 | spin_unlock_irq(&hdspm->lock); | |
1950 | return 0; | |
1951 | } | |
1952 | ||
98274f07 TI |
1953 | static int snd_hdspm_put_tx_64(struct snd_kcontrol *kcontrol, |
1954 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 1955 | { |
98274f07 | 1956 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
1957 | int change; |
1958 | unsigned int val; | |
1959 | ||
1960 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
1961 | return -EBUSY; | |
1962 | val = ucontrol->value.integer.value[0] & 1; | |
1963 | spin_lock_irq(&hdspm->lock); | |
1964 | change = (int) val != hdspm_tx_64(hdspm); | |
1965 | hdspm_set_tx_64(hdspm, val); | |
1966 | spin_unlock_irq(&hdspm->lock); | |
1967 | return change; | |
1968 | } | |
1969 | ||
1970 | #define HDSPM_C_TMS(xname, xindex) \ | |
67ed4161 | 1971 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
763f356c TI |
1972 | .name = xname, \ |
1973 | .index = xindex, \ | |
1974 | .info = snd_hdspm_info_c_tms, \ | |
1975 | .get = snd_hdspm_get_c_tms, \ | |
1976 | .put = snd_hdspm_put_c_tms \ | |
1977 | } | |
1978 | ||
98274f07 | 1979 | static int hdspm_c_tms(struct hdspm * hdspm) |
763f356c TI |
1980 | { |
1981 | return (hdspm->control_register & HDSPM_clr_tms) ? 1 : 0; | |
1982 | } | |
1983 | ||
98274f07 | 1984 | static int hdspm_set_c_tms(struct hdspm * hdspm, int out) |
763f356c TI |
1985 | { |
1986 | if (out) | |
1987 | hdspm->control_register |= HDSPM_clr_tms; | |
1988 | else | |
1989 | hdspm->control_register &= ~HDSPM_clr_tms; | |
1990 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); | |
1991 | ||
1992 | return 0; | |
1993 | } | |
1994 | ||
a5ce8890 | 1995 | #define snd_hdspm_info_c_tms snd_ctl_boolean_mono_info |
763f356c | 1996 | |
98274f07 TI |
1997 | static int snd_hdspm_get_c_tms(struct snd_kcontrol *kcontrol, |
1998 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 1999 | { |
98274f07 | 2000 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
2001 | |
2002 | spin_lock_irq(&hdspm->lock); | |
2003 | ucontrol->value.integer.value[0] = hdspm_c_tms(hdspm); | |
2004 | spin_unlock_irq(&hdspm->lock); | |
2005 | return 0; | |
2006 | } | |
2007 | ||
98274f07 TI |
2008 | static int snd_hdspm_put_c_tms(struct snd_kcontrol *kcontrol, |
2009 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 2010 | { |
98274f07 | 2011 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
2012 | int change; |
2013 | unsigned int val; | |
2014 | ||
2015 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
2016 | return -EBUSY; | |
2017 | val = ucontrol->value.integer.value[0] & 1; | |
2018 | spin_lock_irq(&hdspm->lock); | |
2019 | change = (int) val != hdspm_c_tms(hdspm); | |
2020 | hdspm_set_c_tms(hdspm, val); | |
2021 | spin_unlock_irq(&hdspm->lock); | |
2022 | return change; | |
2023 | } | |
2024 | ||
2025 | #define HDSPM_SAFE_MODE(xname, xindex) \ | |
67ed4161 | 2026 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
763f356c TI |
2027 | .name = xname, \ |
2028 | .index = xindex, \ | |
2029 | .info = snd_hdspm_info_safe_mode, \ | |
2030 | .get = snd_hdspm_get_safe_mode, \ | |
2031 | .put = snd_hdspm_put_safe_mode \ | |
2032 | } | |
2033 | ||
3cee5a60 RB |
2034 | static int hdspm_safe_mode(struct hdspm * hdspm) |
2035 | { | |
2036 | return (hdspm->control_register & HDSPM_AutoInp) ? 1 : 0; | |
2037 | } | |
2038 | ||
2039 | static int hdspm_set_safe_mode(struct hdspm * hdspm, int out) | |
2040 | { | |
2041 | if (out) | |
2042 | hdspm->control_register |= HDSPM_AutoInp; | |
2043 | else | |
2044 | hdspm->control_register &= ~HDSPM_AutoInp; | |
2045 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); | |
2046 | ||
2047 | return 0; | |
2048 | } | |
2049 | ||
a5ce8890 | 2050 | #define snd_hdspm_info_safe_mode snd_ctl_boolean_mono_info |
3cee5a60 RB |
2051 | |
2052 | static int snd_hdspm_get_safe_mode(struct snd_kcontrol *kcontrol, | |
2053 | struct snd_ctl_elem_value *ucontrol) | |
2054 | { | |
2055 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
2056 | ||
2057 | spin_lock_irq(&hdspm->lock); | |
2058 | ucontrol->value.integer.value[0] = hdspm_safe_mode(hdspm); | |
2059 | spin_unlock_irq(&hdspm->lock); | |
2060 | return 0; | |
2061 | } | |
2062 | ||
2063 | static int snd_hdspm_put_safe_mode(struct snd_kcontrol *kcontrol, | |
2064 | struct snd_ctl_elem_value *ucontrol) | |
2065 | { | |
2066 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
2067 | int change; | |
2068 | unsigned int val; | |
2069 | ||
2070 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
2071 | return -EBUSY; | |
2072 | val = ucontrol->value.integer.value[0] & 1; | |
2073 | spin_lock_irq(&hdspm->lock); | |
2074 | change = (int) val != hdspm_safe_mode(hdspm); | |
2075 | hdspm_set_safe_mode(hdspm, val); | |
2076 | spin_unlock_irq(&hdspm->lock); | |
2077 | return change; | |
2078 | } | |
2079 | ||
2080 | #define HDSPM_EMPHASIS(xname, xindex) \ | |
2081 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ | |
2082 | .name = xname, \ | |
2083 | .index = xindex, \ | |
2084 | .info = snd_hdspm_info_emphasis, \ | |
2085 | .get = snd_hdspm_get_emphasis, \ | |
2086 | .put = snd_hdspm_put_emphasis \ | |
2087 | } | |
2088 | ||
2089 | static int hdspm_emphasis(struct hdspm * hdspm) | |
2090 | { | |
2091 | return (hdspm->control_register & HDSPM_Emphasis) ? 1 : 0; | |
2092 | } | |
2093 | ||
2094 | static int hdspm_set_emphasis(struct hdspm * hdspm, int emp) | |
2095 | { | |
2096 | if (emp) | |
2097 | hdspm->control_register |= HDSPM_Emphasis; | |
2098 | else | |
2099 | hdspm->control_register &= ~HDSPM_Emphasis; | |
2100 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); | |
2101 | ||
2102 | return 0; | |
2103 | } | |
2104 | ||
a5ce8890 | 2105 | #define snd_hdspm_info_emphasis snd_ctl_boolean_mono_info |
3cee5a60 RB |
2106 | |
2107 | static int snd_hdspm_get_emphasis(struct snd_kcontrol *kcontrol, | |
2108 | struct snd_ctl_elem_value *ucontrol) | |
2109 | { | |
2110 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
2111 | ||
2112 | spin_lock_irq(&hdspm->lock); | |
2113 | ucontrol->value.enumerated.item[0] = hdspm_emphasis(hdspm); | |
2114 | spin_unlock_irq(&hdspm->lock); | |
2115 | return 0; | |
2116 | } | |
2117 | ||
2118 | static int snd_hdspm_put_emphasis(struct snd_kcontrol *kcontrol, | |
2119 | struct snd_ctl_elem_value *ucontrol) | |
2120 | { | |
2121 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
2122 | int change; | |
2123 | unsigned int val; | |
2124 | ||
2125 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
2126 | return -EBUSY; | |
2127 | val = ucontrol->value.integer.value[0] & 1; | |
2128 | spin_lock_irq(&hdspm->lock); | |
2129 | change = (int) val != hdspm_emphasis(hdspm); | |
2130 | hdspm_set_emphasis(hdspm, val); | |
2131 | spin_unlock_irq(&hdspm->lock); | |
2132 | return change; | |
2133 | } | |
2134 | ||
2135 | #define HDSPM_DOLBY(xname, xindex) \ | |
2136 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ | |
2137 | .name = xname, \ | |
2138 | .index = xindex, \ | |
2139 | .info = snd_hdspm_info_dolby, \ | |
2140 | .get = snd_hdspm_get_dolby, \ | |
2141 | .put = snd_hdspm_put_dolby \ | |
2142 | } | |
2143 | ||
2144 | static int hdspm_dolby(struct hdspm * hdspm) | |
2145 | { | |
2146 | return (hdspm->control_register & HDSPM_Dolby) ? 1 : 0; | |
2147 | } | |
2148 | ||
2149 | static int hdspm_set_dolby(struct hdspm * hdspm, int dol) | |
2150 | { | |
2151 | if (dol) | |
2152 | hdspm->control_register |= HDSPM_Dolby; | |
2153 | else | |
2154 | hdspm->control_register &= ~HDSPM_Dolby; | |
2155 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); | |
2156 | ||
2157 | return 0; | |
2158 | } | |
2159 | ||
a5ce8890 | 2160 | #define snd_hdspm_info_dolby snd_ctl_boolean_mono_info |
3cee5a60 RB |
2161 | |
2162 | static int snd_hdspm_get_dolby(struct snd_kcontrol *kcontrol, | |
2163 | struct snd_ctl_elem_value *ucontrol) | |
2164 | { | |
2165 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
2166 | ||
2167 | spin_lock_irq(&hdspm->lock); | |
2168 | ucontrol->value.enumerated.item[0] = hdspm_dolby(hdspm); | |
2169 | spin_unlock_irq(&hdspm->lock); | |
2170 | return 0; | |
2171 | } | |
2172 | ||
2173 | static int snd_hdspm_put_dolby(struct snd_kcontrol *kcontrol, | |
2174 | struct snd_ctl_elem_value *ucontrol) | |
2175 | { | |
2176 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
2177 | int change; | |
2178 | unsigned int val; | |
2179 | ||
2180 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
2181 | return -EBUSY; | |
2182 | val = ucontrol->value.integer.value[0] & 1; | |
2183 | spin_lock_irq(&hdspm->lock); | |
2184 | change = (int) val != hdspm_dolby(hdspm); | |
2185 | hdspm_set_dolby(hdspm, val); | |
2186 | spin_unlock_irq(&hdspm->lock); | |
2187 | return change; | |
2188 | } | |
2189 | ||
2190 | #define HDSPM_PROFESSIONAL(xname, xindex) \ | |
2191 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ | |
2192 | .name = xname, \ | |
2193 | .index = xindex, \ | |
2194 | .info = snd_hdspm_info_professional, \ | |
2195 | .get = snd_hdspm_get_professional, \ | |
2196 | .put = snd_hdspm_put_professional \ | |
2197 | } | |
2198 | ||
2199 | static int hdspm_professional(struct hdspm * hdspm) | |
2200 | { | |
2201 | return (hdspm->control_register & HDSPM_Professional) ? 1 : 0; | |
2202 | } | |
2203 | ||
2204 | static int hdspm_set_professional(struct hdspm * hdspm, int dol) | |
2205 | { | |
2206 | if (dol) | |
2207 | hdspm->control_register |= HDSPM_Professional; | |
2208 | else | |
2209 | hdspm->control_register &= ~HDSPM_Professional; | |
2210 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); | |
2211 | ||
2212 | return 0; | |
2213 | } | |
2214 | ||
a5ce8890 | 2215 | #define snd_hdspm_info_professional snd_ctl_boolean_mono_info |
3cee5a60 RB |
2216 | |
2217 | static int snd_hdspm_get_professional(struct snd_kcontrol *kcontrol, | |
2218 | struct snd_ctl_elem_value *ucontrol) | |
2219 | { | |
2220 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
2221 | ||
2222 | spin_lock_irq(&hdspm->lock); | |
2223 | ucontrol->value.enumerated.item[0] = hdspm_professional(hdspm); | |
2224 | spin_unlock_irq(&hdspm->lock); | |
2225 | return 0; | |
2226 | } | |
2227 | ||
2228 | static int snd_hdspm_put_professional(struct snd_kcontrol *kcontrol, | |
2229 | struct snd_ctl_elem_value *ucontrol) | |
2230 | { | |
2231 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
2232 | int change; | |
2233 | unsigned int val; | |
2234 | ||
2235 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
2236 | return -EBUSY; | |
2237 | val = ucontrol->value.integer.value[0] & 1; | |
2238 | spin_lock_irq(&hdspm->lock); | |
2239 | change = (int) val != hdspm_professional(hdspm); | |
2240 | hdspm_set_professional(hdspm, val); | |
2241 | spin_unlock_irq(&hdspm->lock); | |
2242 | return change; | |
2243 | } | |
2244 | ||
2245 | #define HDSPM_INPUT_SELECT(xname, xindex) \ | |
2246 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ | |
2247 | .name = xname, \ | |
2248 | .index = xindex, \ | |
2249 | .info = snd_hdspm_info_input_select, \ | |
2250 | .get = snd_hdspm_get_input_select, \ | |
2251 | .put = snd_hdspm_put_input_select \ | |
2252 | } | |
2253 | ||
2254 | static int hdspm_input_select(struct hdspm * hdspm) | |
2255 | { | |
2256 | return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0; | |
2257 | } | |
2258 | ||
2259 | static int hdspm_set_input_select(struct hdspm * hdspm, int out) | |
2260 | { | |
2261 | if (out) | |
2262 | hdspm->control_register |= HDSPM_InputSelect0; | |
2263 | else | |
2264 | hdspm->control_register &= ~HDSPM_InputSelect0; | |
2265 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); | |
2266 | ||
2267 | return 0; | |
2268 | } | |
2269 | ||
2270 | static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol, | |
2271 | struct snd_ctl_elem_info *uinfo) | |
2272 | { | |
2273 | static char *texts[] = { "optical", "coaxial" }; | |
2274 | ||
2275 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
2276 | uinfo->count = 1; | |
2277 | uinfo->value.enumerated.items = 2; | |
2278 | ||
2279 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
2280 | uinfo->value.enumerated.item = | |
2281 | uinfo->value.enumerated.items - 1; | |
2282 | strcpy(uinfo->value.enumerated.name, | |
2283 | texts[uinfo->value.enumerated.item]); | |
2284 | ||
2285 | return 0; | |
2286 | } | |
2287 | ||
2288 | static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol, | |
2289 | struct snd_ctl_elem_value *ucontrol) | |
2290 | { | |
2291 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
2292 | ||
2293 | spin_lock_irq(&hdspm->lock); | |
2294 | ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm); | |
2295 | spin_unlock_irq(&hdspm->lock); | |
2296 | return 0; | |
2297 | } | |
2298 | ||
2299 | static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol, | |
2300 | struct snd_ctl_elem_value *ucontrol) | |
2301 | { | |
2302 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
2303 | int change; | |
2304 | unsigned int val; | |
2305 | ||
2306 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
2307 | return -EBUSY; | |
2308 | val = ucontrol->value.integer.value[0] & 1; | |
2309 | spin_lock_irq(&hdspm->lock); | |
2310 | change = (int) val != hdspm_input_select(hdspm); | |
2311 | hdspm_set_input_select(hdspm, val); | |
2312 | spin_unlock_irq(&hdspm->lock); | |
2313 | return change; | |
2314 | } | |
2315 | ||
2316 | #define HDSPM_DS_WIRE(xname, xindex) \ | |
2317 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ | |
2318 | .name = xname, \ | |
2319 | .index = xindex, \ | |
2320 | .info = snd_hdspm_info_ds_wire, \ | |
2321 | .get = snd_hdspm_get_ds_wire, \ | |
2322 | .put = snd_hdspm_put_ds_wire \ | |
2323 | } | |
2324 | ||
2325 | static int hdspm_ds_wire(struct hdspm * hdspm) | |
763f356c | 2326 | { |
3cee5a60 | 2327 | return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0; |
763f356c TI |
2328 | } |
2329 | ||
3cee5a60 | 2330 | static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds) |
763f356c | 2331 | { |
3cee5a60 RB |
2332 | if (ds) |
2333 | hdspm->control_register |= HDSPM_DS_DoubleWire; | |
763f356c | 2334 | else |
3cee5a60 | 2335 | hdspm->control_register &= ~HDSPM_DS_DoubleWire; |
763f356c TI |
2336 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); |
2337 | ||
2338 | return 0; | |
2339 | } | |
2340 | ||
3cee5a60 RB |
2341 | static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol, |
2342 | struct snd_ctl_elem_info *uinfo) | |
763f356c | 2343 | { |
3cee5a60 RB |
2344 | static char *texts[] = { "Single", "Double" }; |
2345 | ||
2346 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
763f356c | 2347 | uinfo->count = 1; |
3cee5a60 RB |
2348 | uinfo->value.enumerated.items = 2; |
2349 | ||
2350 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
2351 | uinfo->value.enumerated.item = | |
2352 | uinfo->value.enumerated.items - 1; | |
2353 | strcpy(uinfo->value.enumerated.name, | |
2354 | texts[uinfo->value.enumerated.item]); | |
2355 | ||
763f356c TI |
2356 | return 0; |
2357 | } | |
2358 | ||
3cee5a60 RB |
2359 | static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol, |
2360 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 2361 | { |
98274f07 | 2362 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
2363 | |
2364 | spin_lock_irq(&hdspm->lock); | |
3cee5a60 | 2365 | ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm); |
763f356c TI |
2366 | spin_unlock_irq(&hdspm->lock); |
2367 | return 0; | |
2368 | } | |
2369 | ||
3cee5a60 RB |
2370 | static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol, |
2371 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 2372 | { |
98274f07 | 2373 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
2374 | int change; |
2375 | unsigned int val; | |
2376 | ||
2377 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
2378 | return -EBUSY; | |
2379 | val = ucontrol->value.integer.value[0] & 1; | |
2380 | spin_lock_irq(&hdspm->lock); | |
3cee5a60 RB |
2381 | change = (int) val != hdspm_ds_wire(hdspm); |
2382 | hdspm_set_ds_wire(hdspm, val); | |
763f356c TI |
2383 | spin_unlock_irq(&hdspm->lock); |
2384 | return change; | |
2385 | } | |
2386 | ||
3cee5a60 | 2387 | #define HDSPM_QS_WIRE(xname, xindex) \ |
67ed4161 | 2388 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
763f356c TI |
2389 | .name = xname, \ |
2390 | .index = xindex, \ | |
3cee5a60 RB |
2391 | .info = snd_hdspm_info_qs_wire, \ |
2392 | .get = snd_hdspm_get_qs_wire, \ | |
2393 | .put = snd_hdspm_put_qs_wire \ | |
763f356c TI |
2394 | } |
2395 | ||
3cee5a60 | 2396 | static int hdspm_qs_wire(struct hdspm * hdspm) |
763f356c | 2397 | { |
3cee5a60 RB |
2398 | if (hdspm->control_register & HDSPM_QS_DoubleWire) |
2399 | return 1; | |
2400 | if (hdspm->control_register & HDSPM_QS_QuadWire) | |
2401 | return 2; | |
2402 | return 0; | |
763f356c TI |
2403 | } |
2404 | ||
3cee5a60 | 2405 | static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode) |
763f356c | 2406 | { |
3cee5a60 RB |
2407 | hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire); |
2408 | switch (mode) { | |
2409 | case 0: | |
2410 | break; | |
2411 | case 1: | |
2412 | hdspm->control_register |= HDSPM_QS_DoubleWire; | |
2413 | break; | |
2414 | case 2: | |
2415 | hdspm->control_register |= HDSPM_QS_QuadWire; | |
2416 | break; | |
2417 | } | |
763f356c TI |
2418 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); |
2419 | ||
2420 | return 0; | |
2421 | } | |
2422 | ||
3cee5a60 | 2423 | static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol, |
98274f07 | 2424 | struct snd_ctl_elem_info *uinfo) |
763f356c | 2425 | { |
3cee5a60 | 2426 | static char *texts[] = { "Single", "Double", "Quad" }; |
763f356c TI |
2427 | |
2428 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
2429 | uinfo->count = 1; | |
3cee5a60 | 2430 | uinfo->value.enumerated.items = 3; |
763f356c TI |
2431 | |
2432 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
2433 | uinfo->value.enumerated.item = | |
2434 | uinfo->value.enumerated.items - 1; | |
2435 | strcpy(uinfo->value.enumerated.name, | |
2436 | texts[uinfo->value.enumerated.item]); | |
2437 | ||
2438 | return 0; | |
2439 | } | |
2440 | ||
3cee5a60 | 2441 | static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol, |
98274f07 | 2442 | struct snd_ctl_elem_value *ucontrol) |
763f356c | 2443 | { |
98274f07 | 2444 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
2445 | |
2446 | spin_lock_irq(&hdspm->lock); | |
3cee5a60 | 2447 | ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm); |
763f356c TI |
2448 | spin_unlock_irq(&hdspm->lock); |
2449 | return 0; | |
2450 | } | |
2451 | ||
3cee5a60 | 2452 | static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol, |
98274f07 | 2453 | struct snd_ctl_elem_value *ucontrol) |
763f356c | 2454 | { |
98274f07 | 2455 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c | 2456 | int change; |
3cee5a60 | 2457 | int val; |
763f356c TI |
2458 | |
2459 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
2460 | return -EBUSY; | |
3cee5a60 RB |
2461 | val = ucontrol->value.integer.value[0]; |
2462 | if (val < 0) | |
2463 | val = 0; | |
2464 | if (val > 2) | |
2465 | val = 2; | |
763f356c | 2466 | spin_lock_irq(&hdspm->lock); |
ef5fa1a4 | 2467 | change = val != hdspm_qs_wire(hdspm); |
3cee5a60 | 2468 | hdspm_set_qs_wire(hdspm, val); |
763f356c TI |
2469 | spin_unlock_irq(&hdspm->lock); |
2470 | return change; | |
2471 | } | |
2472 | ||
2473 | /* Simple Mixer | |
2474 | deprecated since to much faders ??? | |
2475 | MIXER interface says output (source, destination, value) | |
2476 | where source > MAX_channels are playback channels | |
2477 | on MADICARD | |
2478 | - playback mixer matrix: [channelout+64] [output] [value] | |
2479 | - input(thru) mixer matrix: [channelin] [output] [value] | |
2480 | (better do 2 kontrols for seperation ?) | |
2481 | */ | |
2482 | ||
2483 | #define HDSPM_MIXER(xname, xindex) \ | |
2484 | { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ | |
2485 | .name = xname, \ | |
2486 | .index = xindex, \ | |
67ed4161 | 2487 | .device = 0, \ |
763f356c TI |
2488 | .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ |
2489 | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
2490 | .info = snd_hdspm_info_mixer, \ | |
2491 | .get = snd_hdspm_get_mixer, \ | |
2492 | .put = snd_hdspm_put_mixer \ | |
2493 | } | |
2494 | ||
98274f07 TI |
2495 | static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol, |
2496 | struct snd_ctl_elem_info *uinfo) | |
763f356c TI |
2497 | { |
2498 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; | |
2499 | uinfo->count = 3; | |
2500 | uinfo->value.integer.min = 0; | |
2501 | uinfo->value.integer.max = 65535; | |
2502 | uinfo->value.integer.step = 1; | |
2503 | return 0; | |
2504 | } | |
2505 | ||
98274f07 TI |
2506 | static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol, |
2507 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 2508 | { |
98274f07 | 2509 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
2510 | int source; |
2511 | int destination; | |
2512 | ||
2513 | source = ucontrol->value.integer.value[0]; | |
2514 | if (source < 0) | |
2515 | source = 0; | |
2516 | else if (source >= 2 * HDSPM_MAX_CHANNELS) | |
2517 | source = 2 * HDSPM_MAX_CHANNELS - 1; | |
2518 | ||
2519 | destination = ucontrol->value.integer.value[1]; | |
2520 | if (destination < 0) | |
2521 | destination = 0; | |
2522 | else if (destination >= HDSPM_MAX_CHANNELS) | |
2523 | destination = HDSPM_MAX_CHANNELS - 1; | |
2524 | ||
2525 | spin_lock_irq(&hdspm->lock); | |
2526 | if (source >= HDSPM_MAX_CHANNELS) | |
2527 | ucontrol->value.integer.value[2] = | |
2528 | hdspm_read_pb_gain(hdspm, destination, | |
2529 | source - HDSPM_MAX_CHANNELS); | |
2530 | else | |
2531 | ucontrol->value.integer.value[2] = | |
2532 | hdspm_read_in_gain(hdspm, destination, source); | |
2533 | ||
2534 | spin_unlock_irq(&hdspm->lock); | |
2535 | ||
2536 | return 0; | |
2537 | } | |
2538 | ||
98274f07 TI |
2539 | static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol, |
2540 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 2541 | { |
98274f07 | 2542 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
2543 | int change; |
2544 | int source; | |
2545 | int destination; | |
2546 | int gain; | |
2547 | ||
2548 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
2549 | return -EBUSY; | |
2550 | ||
2551 | source = ucontrol->value.integer.value[0]; | |
2552 | destination = ucontrol->value.integer.value[1]; | |
2553 | ||
2554 | if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS) | |
2555 | return -1; | |
2556 | if (destination < 0 || destination >= HDSPM_MAX_CHANNELS) | |
2557 | return -1; | |
2558 | ||
2559 | gain = ucontrol->value.integer.value[2]; | |
2560 | ||
2561 | spin_lock_irq(&hdspm->lock); | |
2562 | ||
2563 | if (source >= HDSPM_MAX_CHANNELS) | |
2564 | change = gain != hdspm_read_pb_gain(hdspm, destination, | |
2565 | source - | |
2566 | HDSPM_MAX_CHANNELS); | |
2567 | else | |
ef5fa1a4 TI |
2568 | change = gain != hdspm_read_in_gain(hdspm, destination, |
2569 | source); | |
763f356c TI |
2570 | |
2571 | if (change) { | |
2572 | if (source >= HDSPM_MAX_CHANNELS) | |
2573 | hdspm_write_pb_gain(hdspm, destination, | |
2574 | source - HDSPM_MAX_CHANNELS, | |
2575 | gain); | |
2576 | else | |
2577 | hdspm_write_in_gain(hdspm, destination, source, | |
2578 | gain); | |
2579 | } | |
2580 | spin_unlock_irq(&hdspm->lock); | |
2581 | ||
2582 | return change; | |
2583 | } | |
2584 | ||
2585 | /* The simple mixer control(s) provide gain control for the | |
2586 | basic 1:1 mappings of playback streams to output | |
2587 | streams. | |
2588 | */ | |
2589 | ||
2590 | #define HDSPM_PLAYBACK_MIXER \ | |
2591 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ | |
2592 | .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \ | |
2593 | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
2594 | .info = snd_hdspm_info_playback_mixer, \ | |
2595 | .get = snd_hdspm_get_playback_mixer, \ | |
2596 | .put = snd_hdspm_put_playback_mixer \ | |
2597 | } | |
2598 | ||
98274f07 TI |
2599 | static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol, |
2600 | struct snd_ctl_elem_info *uinfo) | |
763f356c TI |
2601 | { |
2602 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; | |
2603 | uinfo->count = 1; | |
2604 | uinfo->value.integer.min = 0; | |
2605 | uinfo->value.integer.max = 65536; | |
2606 | uinfo->value.integer.step = 1; | |
2607 | return 0; | |
2608 | } | |
2609 | ||
98274f07 TI |
2610 | static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol, |
2611 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 2612 | { |
98274f07 | 2613 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
2614 | int channel; |
2615 | int mapped_channel; | |
2616 | ||
2617 | channel = ucontrol->id.index - 1; | |
2618 | ||
2619 | snd_assert(channel >= 0 | |
2620 | || channel < HDSPM_MAX_CHANNELS, return -EINVAL); | |
2621 | ||
ef5fa1a4 TI |
2622 | mapped_channel = hdspm->channel_map[channel]; |
2623 | if (mapped_channel < 0) | |
763f356c TI |
2624 | return -EINVAL; |
2625 | ||
2626 | spin_lock_irq(&hdspm->lock); | |
2627 | ucontrol->value.integer.value[0] = | |
2628 | hdspm_read_pb_gain(hdspm, mapped_channel, mapped_channel); | |
2629 | spin_unlock_irq(&hdspm->lock); | |
2630 | ||
ef5fa1a4 TI |
2631 | /* |
2632 | snd_printdd("get pb mixer index %d, channel %d, mapped_channel %d, " | |
2633 | "value %d\n", | |
2634 | ucontrol->id.index, channel, mapped_channel, | |
2635 | ucontrol->value.integer.value[0]); | |
2636 | */ | |
763f356c TI |
2637 | return 0; |
2638 | } | |
2639 | ||
98274f07 TI |
2640 | static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol, |
2641 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 2642 | { |
98274f07 | 2643 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
2644 | int change; |
2645 | int channel; | |
2646 | int mapped_channel; | |
2647 | int gain; | |
2648 | ||
2649 | if (!snd_hdspm_use_is_exclusive(hdspm)) | |
2650 | return -EBUSY; | |
2651 | ||
2652 | channel = ucontrol->id.index - 1; | |
2653 | ||
2654 | snd_assert(channel >= 0 | |
2655 | || channel < HDSPM_MAX_CHANNELS, return -EINVAL); | |
2656 | ||
ef5fa1a4 TI |
2657 | mapped_channel = hdspm->channel_map[channel]; |
2658 | if (mapped_channel < 0) | |
763f356c TI |
2659 | return -EINVAL; |
2660 | ||
2661 | gain = ucontrol->value.integer.value[0]; | |
2662 | ||
2663 | spin_lock_irq(&hdspm->lock); | |
2664 | change = | |
2665 | gain != hdspm_read_pb_gain(hdspm, mapped_channel, | |
2666 | mapped_channel); | |
2667 | if (change) | |
2668 | hdspm_write_pb_gain(hdspm, mapped_channel, mapped_channel, | |
2669 | gain); | |
2670 | spin_unlock_irq(&hdspm->lock); | |
2671 | return change; | |
2672 | } | |
2673 | ||
2674 | #define HDSPM_WC_SYNC_CHECK(xname, xindex) \ | |
67ed4161 | 2675 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
763f356c TI |
2676 | .name = xname, \ |
2677 | .index = xindex, \ | |
2678 | .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
2679 | .info = snd_hdspm_info_sync_check, \ | |
2680 | .get = snd_hdspm_get_wc_sync_check \ | |
2681 | } | |
2682 | ||
98274f07 TI |
2683 | static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol, |
2684 | struct snd_ctl_elem_info *uinfo) | |
763f356c TI |
2685 | { |
2686 | static char *texts[] = { "No Lock", "Lock", "Sync" }; | |
2687 | uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
2688 | uinfo->count = 1; | |
2689 | uinfo->value.enumerated.items = 3; | |
2690 | if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) | |
2691 | uinfo->value.enumerated.item = | |
2692 | uinfo->value.enumerated.items - 1; | |
2693 | strcpy(uinfo->value.enumerated.name, | |
2694 | texts[uinfo->value.enumerated.item]); | |
2695 | return 0; | |
2696 | } | |
2697 | ||
98274f07 | 2698 | static int hdspm_wc_sync_check(struct hdspm * hdspm) |
763f356c | 2699 | { |
3cee5a60 RB |
2700 | if (hdspm->is_aes32) { |
2701 | int status = hdspm_read(hdspm, HDSPM_statusRegister); | |
2702 | if (status & HDSPM_AES32_wcLock) { | |
2703 | /* I don't know how to differenciate sync from lock. | |
2704 | Doing as if sync for now */ | |
763f356c | 2705 | return 2; |
3cee5a60 RB |
2706 | } |
2707 | return 0; | |
2708 | } else { | |
2709 | int status2 = hdspm_read(hdspm, HDSPM_statusRegister2); | |
2710 | if (status2 & HDSPM_wcLock) { | |
2711 | if (status2 & HDSPM_wcSync) | |
2712 | return 2; | |
2713 | else | |
2714 | return 1; | |
2715 | } | |
2716 | return 0; | |
763f356c | 2717 | } |
763f356c TI |
2718 | } |
2719 | ||
98274f07 TI |
2720 | static int snd_hdspm_get_wc_sync_check(struct snd_kcontrol *kcontrol, |
2721 | struct snd_ctl_elem_value *ucontrol) | |
763f356c | 2722 | { |
98274f07 | 2723 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
2724 | |
2725 | ucontrol->value.enumerated.item[0] = hdspm_wc_sync_check(hdspm); | |
2726 | return 0; | |
2727 | } | |
2728 | ||
2729 | ||
2730 | #define HDSPM_MADI_SYNC_CHECK(xname, xindex) \ | |
67ed4161 | 2731 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
763f356c TI |
2732 | .name = xname, \ |
2733 | .index = xindex, \ | |
2734 | .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
2735 | .info = snd_hdspm_info_sync_check, \ | |
2736 | .get = snd_hdspm_get_madisync_sync_check \ | |
2737 | } | |
2738 | ||
98274f07 | 2739 | static int hdspm_madisync_sync_check(struct hdspm * hdspm) |
763f356c TI |
2740 | { |
2741 | int status = hdspm_read(hdspm, HDSPM_statusRegister); | |
2742 | if (status & HDSPM_madiLock) { | |
2743 | if (status & HDSPM_madiSync) | |
2744 | return 2; | |
2745 | else | |
2746 | return 1; | |
2747 | } | |
2748 | return 0; | |
2749 | } | |
2750 | ||
98274f07 TI |
2751 | static int snd_hdspm_get_madisync_sync_check(struct snd_kcontrol *kcontrol, |
2752 | struct snd_ctl_elem_value * | |
763f356c TI |
2753 | ucontrol) |
2754 | { | |
98274f07 | 2755 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); |
763f356c TI |
2756 | |
2757 | ucontrol->value.enumerated.item[0] = | |
2758 | hdspm_madisync_sync_check(hdspm); | |
2759 | return 0; | |
2760 | } | |
2761 | ||
2762 | ||
3cee5a60 RB |
2763 | #define HDSPM_AES_SYNC_CHECK(xname, xindex) \ |
2764 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ | |
2765 | .name = xname, \ | |
2766 | .index = xindex, \ | |
2767 | .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
2768 | .info = snd_hdspm_info_sync_check, \ | |
2769 | .get = snd_hdspm_get_aes_sync_check \ | |
2770 | } | |
2771 | ||
2772 | static int hdspm_aes_sync_check(struct hdspm * hdspm, int idx) | |
2773 | { | |
2774 | int status2 = hdspm_read(hdspm, HDSPM_statusRegister2); | |
2775 | if (status2 & (HDSPM_LockAES >> idx)) { | |
2776 | /* I don't know how to differenciate sync from lock. | |
2777 | Doing as if sync for now */ | |
2778 | return 2; | |
2779 | } | |
2780 | return 0; | |
2781 | } | |
2782 | ||
2783 | static int snd_hdspm_get_aes_sync_check(struct snd_kcontrol *kcontrol, | |
2784 | struct snd_ctl_elem_value *ucontrol) | |
2785 | { | |
2786 | int offset; | |
2787 | struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); | |
2788 | ||
2789 | offset = ucontrol->id.index - 1; | |
2790 | if (offset < 0 || offset >= 8) | |
2791 | return -EINVAL; | |
2792 | ||
2793 | ucontrol->value.enumerated.item[0] = | |
2794 | hdspm_aes_sync_check(hdspm, offset); | |
2795 | return 0; | |
2796 | } | |
763f356c TI |
2797 | |
2798 | ||
3cee5a60 | 2799 | static struct snd_kcontrol_new snd_hdspm_controls_madi[] = { |
763f356c TI |
2800 | |
2801 | HDSPM_MIXER("Mixer", 0), | |
2802 | /* 'Sample Clock Source' complies with the alsa control naming scheme */ | |
2803 | HDSPM_CLOCK_SOURCE("Sample Clock Source", 0), | |
2804 | ||
2805 | HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), | |
2806 | HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), | |
2807 | HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), | |
2808 | HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), | |
2809 | /* 'External Rate' complies with the alsa control naming scheme */ | |
2810 | HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), | |
2811 | HDSPM_WC_SYNC_CHECK("Word Clock Lock Status", 0), | |
2812 | HDSPM_MADI_SYNC_CHECK("MADI Sync Lock Status", 0), | |
2813 | HDSPM_LINE_OUT("Line Out", 0), | |
2814 | HDSPM_TX_64("TX 64 channels mode", 0), | |
2815 | HDSPM_C_TMS("Clear Track Marker", 0), | |
2816 | HDSPM_SAFE_MODE("Safe Mode", 0), | |
2817 | HDSPM_INPUT_SELECT("Input Select", 0), | |
2818 | }; | |
2819 | ||
3cee5a60 RB |
2820 | static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = { |
2821 | ||
2822 | HDSPM_MIXER("Mixer", 0), | |
2823 | /* 'Sample Clock Source' complies with the alsa control naming scheme */ | |
2824 | HDSPM_CLOCK_SOURCE("Sample Clock Source", 0), | |
2825 | ||
2826 | HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), | |
2827 | HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), | |
2828 | HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), | |
2829 | HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), | |
2830 | /* 'External Rate' complies with the alsa control naming scheme */ | |
2831 | HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), | |
2832 | HDSPM_WC_SYNC_CHECK("Word Clock Lock Status", 0), | |
2833 | /* HDSPM_AES_SYNC_CHECK("AES Lock Status", 0),*/ /* created in snd_hdspm_create_controls() */ | |
2834 | HDSPM_LINE_OUT("Line Out", 0), | |
2835 | HDSPM_EMPHASIS("Emphasis", 0), | |
2836 | HDSPM_DOLBY("Non Audio", 0), | |
2837 | HDSPM_PROFESSIONAL("Professional", 0), | |
2838 | HDSPM_C_TMS("Clear Track Marker", 0), | |
2839 | HDSPM_DS_WIRE("Double Speed Wire Mode", 0), | |
2840 | HDSPM_QS_WIRE("Quad Speed Wire Mode", 0), | |
2841 | }; | |
2842 | ||
98274f07 | 2843 | static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER; |
763f356c TI |
2844 | |
2845 | ||
98274f07 | 2846 | static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm) |
763f356c TI |
2847 | { |
2848 | int i; | |
2849 | ||
2850 | for (i = hdspm->ds_channels; i < hdspm->ss_channels; ++i) { | |
2851 | if (hdspm->system_sample_rate > 48000) { | |
2852 | hdspm->playback_mixer_ctls[i]->vd[0].access = | |
2853 | SNDRV_CTL_ELEM_ACCESS_INACTIVE | | |
2854 | SNDRV_CTL_ELEM_ACCESS_READ | | |
2855 | SNDRV_CTL_ELEM_ACCESS_VOLATILE; | |
2856 | } else { | |
2857 | hdspm->playback_mixer_ctls[i]->vd[0].access = | |
2858 | SNDRV_CTL_ELEM_ACCESS_READWRITE | | |
2859 | SNDRV_CTL_ELEM_ACCESS_VOLATILE; | |
2860 | } | |
2861 | snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE | | |
2862 | SNDRV_CTL_EVENT_MASK_INFO, | |
2863 | &hdspm->playback_mixer_ctls[i]->id); | |
2864 | } | |
2865 | ||
2866 | return 0; | |
2867 | } | |
2868 | ||
2869 | ||
98274f07 | 2870 | static int snd_hdspm_create_controls(struct snd_card *card, struct hdspm * hdspm) |
763f356c TI |
2871 | { |
2872 | unsigned int idx, limit; | |
2873 | int err; | |
98274f07 | 2874 | struct snd_kcontrol *kctl; |
763f356c TI |
2875 | |
2876 | /* add control list first */ | |
3cee5a60 RB |
2877 | if (hdspm->is_aes32) { |
2878 | struct snd_kcontrol_new aes_sync_ctl = | |
2879 | HDSPM_AES_SYNC_CHECK("AES Lock Status", 0); | |
2880 | ||
2881 | for (idx = 0; idx < ARRAY_SIZE(snd_hdspm_controls_aes32); | |
2882 | idx++) { | |
2883 | err = snd_ctl_add(card, | |
2884 | snd_ctl_new1(&snd_hdspm_controls_aes32[idx], | |
2885 | hdspm)); | |
2886 | if (err < 0) | |
2887 | return err; | |
2888 | } | |
2889 | for (idx = 1; idx <= 8; idx++) { | |
2890 | aes_sync_ctl.index = idx; | |
2891 | err = snd_ctl_add(card, | |
2892 | snd_ctl_new1(&aes_sync_ctl, hdspm)); | |
2893 | if (err < 0) | |
2894 | return err; | |
2895 | } | |
2896 | } else { | |
2897 | for (idx = 0; idx < ARRAY_SIZE(snd_hdspm_controls_madi); | |
2898 | idx++) { | |
2899 | err = snd_ctl_add(card, | |
2900 | snd_ctl_new1(&snd_hdspm_controls_madi[idx], | |
2901 | hdspm)); | |
2902 | if (err < 0) | |
2903 | return err; | |
763f356c TI |
2904 | } |
2905 | } | |
2906 | ||
2907 | /* Channel playback mixer as default control | |
ef5fa1a4 TI |
2908 | Note: the whole matrix would be 128*HDSPM_MIXER_CHANNELS Faders, |
2909 | thats too * big for any alsamixer they are accesible via special | |
2910 | IOCTL on hwdep and the mixer 2dimensional mixer control | |
2911 | */ | |
763f356c TI |
2912 | |
2913 | snd_hdspm_playback_mixer.name = "Chn"; | |
2914 | limit = HDSPM_MAX_CHANNELS; | |
2915 | ||
ef5fa1a4 TI |
2916 | /* The index values are one greater than the channel ID so that |
2917 | * alsamixer will display them correctly. We want to use the index | |
2918 | * for fast lookup of the relevant channel, but if we use it at all, | |
2919 | * most ALSA software does the wrong thing with it ... | |
763f356c TI |
2920 | */ |
2921 | ||
2922 | for (idx = 0; idx < limit; ++idx) { | |
2923 | snd_hdspm_playback_mixer.index = idx + 1; | |
ef5fa1a4 TI |
2924 | kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm); |
2925 | err = snd_ctl_add(card, kctl); | |
2926 | if (err < 0) | |
763f356c | 2927 | return err; |
763f356c TI |
2928 | hdspm->playback_mixer_ctls[idx] = kctl; |
2929 | } | |
2930 | ||
2931 | return 0; | |
2932 | } | |
2933 | ||
2934 | /*------------------------------------------------------------ | |
2935 | /proc interface | |
2936 | ------------------------------------------------------------*/ | |
2937 | ||
2938 | static void | |
3cee5a60 RB |
2939 | snd_hdspm_proc_read_madi(struct snd_info_entry * entry, |
2940 | struct snd_info_buffer *buffer) | |
763f356c | 2941 | { |
ef5fa1a4 | 2942 | struct hdspm *hdspm = entry->private_data; |
763f356c TI |
2943 | unsigned int status; |
2944 | unsigned int status2; | |
2945 | char *pref_sync_ref; | |
2946 | char *autosync_ref; | |
2947 | char *system_clock_mode; | |
2948 | char *clock_source; | |
2949 | char *insel; | |
2950 | char *syncref; | |
2951 | int x, x2; | |
2952 | ||
2953 | status = hdspm_read(hdspm, HDSPM_statusRegister); | |
2954 | status2 = hdspm_read(hdspm, HDSPM_statusRegister2); | |
2955 | ||
2956 | snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n", | |
2957 | hdspm->card_name, hdspm->card->number + 1, | |
2958 | hdspm->firmware_rev, | |
2959 | (status2 & HDSPM_version0) | | |
2960 | (status2 & HDSPM_version1) | (status2 & | |
2961 | HDSPM_version2)); | |
2962 | ||
2963 | snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", | |
2964 | hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase); | |
2965 | ||
2966 | snd_iprintf(buffer, "--- System ---\n"); | |
2967 | ||
2968 | snd_iprintf(buffer, | |
2969 | "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n", | |
2970 | status & HDSPM_audioIRQPending, | |
2971 | (status & HDSPM_midi0IRQPending) ? 1 : 0, | |
2972 | (status & HDSPM_midi1IRQPending) ? 1 : 0, | |
2973 | hdspm->irq_count); | |
2974 | snd_iprintf(buffer, | |
ef5fa1a4 TI |
2975 | "HW pointer: id = %d, rawptr = %d (%d->%d) " |
2976 | "estimated= %ld (bytes)\n", | |
763f356c TI |
2977 | ((status & HDSPM_BufferID) ? 1 : 0), |
2978 | (status & HDSPM_BufferPositionMask), | |
ef5fa1a4 TI |
2979 | (status & HDSPM_BufferPositionMask) % |
2980 | (2 * (int)hdspm->period_bytes), | |
2981 | ((status & HDSPM_BufferPositionMask) - 64) % | |
2982 | (2 * (int)hdspm->period_bytes), | |
763f356c TI |
2983 | (long) hdspm_hw_pointer(hdspm) * 4); |
2984 | ||
2985 | snd_iprintf(buffer, | |
2986 | "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n", | |
2987 | hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF, | |
2988 | hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF, | |
2989 | hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF, | |
2990 | hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF); | |
2991 | snd_iprintf(buffer, | |
ef5fa1a4 TI |
2992 | "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, " |
2993 | "status2=0x%x\n", | |
763f356c TI |
2994 | hdspm->control_register, hdspm->control2_register, |
2995 | status, status2); | |
2996 | ||
2997 | snd_iprintf(buffer, "--- Settings ---\n"); | |
2998 | ||
ef5fa1a4 TI |
2999 | x = 1 << (6 + hdspm_decode_latency(hdspm->control_register & |
3000 | HDSPM_LatencyMask)); | |
763f356c TI |
3001 | |
3002 | snd_iprintf(buffer, | |
3003 | "Size (Latency): %d samples (2 periods of %lu bytes)\n", | |
3004 | x, (unsigned long) hdspm->period_bytes); | |
3005 | ||
3006 | snd_iprintf(buffer, "Line out: %s, Precise Pointer: %s\n", | |
ef5fa1a4 | 3007 | (hdspm->control_register & HDSPM_LineOut) ? "on " : "off", |
763f356c TI |
3008 | (hdspm->precise_ptr) ? "on" : "off"); |
3009 | ||
3010 | switch (hdspm->control_register & HDSPM_InputMask) { | |
3011 | case HDSPM_InputOptical: | |
3012 | insel = "Optical"; | |
3013 | break; | |
3014 | case HDSPM_InputCoaxial: | |
3015 | insel = "Coaxial"; | |
3016 | break; | |
3017 | default: | |
3018 | insel = "Unkown"; | |
3019 | } | |
3020 | ||
3021 | switch (hdspm->control_register & HDSPM_SyncRefMask) { | |
3022 | case HDSPM_SyncRef_Word: | |
3023 | syncref = "WordClock"; | |
3024 | break; | |
3025 | case HDSPM_SyncRef_MADI: | |
3026 | syncref = "MADI"; | |
3027 | break; | |
3028 | default: | |
3029 | syncref = "Unkown"; | |
3030 | } | |
3031 | snd_iprintf(buffer, "Inputsel = %s, SyncRef = %s\n", insel, | |
3032 | syncref); | |
3033 | ||
3034 | snd_iprintf(buffer, | |
ef5fa1a4 TI |
3035 | "ClearTrackMarker = %s, Transmit in %s Channel Mode, " |
3036 | "Auto Input %s\n", | |
763f356c TI |
3037 | (hdspm-> |
3038 | control_register & HDSPM_clr_tms) ? "on" : "off", | |
3039 | (hdspm-> | |
3040 | control_register & HDSPM_TX_64ch) ? "64" : "56", | |
3041 | (hdspm-> | |
3042 | control_register & HDSPM_AutoInp) ? "on" : "off"); | |
3043 | ||
3044 | switch (hdspm_clock_source(hdspm)) { | |
3045 | case HDSPM_CLOCK_SOURCE_AUTOSYNC: | |
3046 | clock_source = "AutoSync"; | |
3047 | break; | |
3048 | case HDSPM_CLOCK_SOURCE_INTERNAL_32KHZ: | |
3049 | clock_source = "Internal 32 kHz"; | |
3050 | break; | |
3051 | case HDSPM_CLOCK_SOURCE_INTERNAL_44_1KHZ: | |
3052 | clock_source = "Internal 44.1 kHz"; | |
3053 | break; | |
3054 | case HDSPM_CLOCK_SOURCE_INTERNAL_48KHZ: | |
3055 | clock_source = "Internal 48 kHz"; | |
3056 | break; | |
3057 | case HDSPM_CLOCK_SOURCE_INTERNAL_64KHZ: | |
3058 | clock_source = "Internal 64 kHz"; | |
3059 | break; | |
3060 | case HDSPM_CLOCK_SOURCE_INTERNAL_88_2KHZ: | |
3061 | clock_source = "Internal 88.2 kHz"; | |
3062 | break; | |
3063 | case HDSPM_CLOCK_SOURCE_INTERNAL_96KHZ: | |
3064 | clock_source = "Internal 96 kHz"; | |
3065 | break; | |
3066 | default: | |
3067 | clock_source = "Error"; | |
3068 | } | |
3069 | snd_iprintf(buffer, "Sample Clock Source: %s\n", clock_source); | |
3cee5a60 | 3070 | if (!(hdspm->control_register & HDSPM_ClockModeMaster)) |
763f356c | 3071 | system_clock_mode = "Slave"; |
3cee5a60 | 3072 | else |
763f356c | 3073 | system_clock_mode = "Master"; |
763f356c TI |
3074 | snd_iprintf(buffer, "System Clock Mode: %s\n", system_clock_mode); |
3075 | ||
3076 | switch (hdspm_pref_sync_ref(hdspm)) { | |
3077 | case HDSPM_SYNC_FROM_WORD: | |
3078 | pref_sync_ref = "Word Clock"; | |
3079 | break; | |
3080 | case HDSPM_SYNC_FROM_MADI: | |
3081 | pref_sync_ref = "MADI Sync"; | |
3082 | break; | |
3083 | default: | |
3084 | pref_sync_ref = "XXXX Clock"; | |
3085 | break; | |
3086 | } | |
3087 | snd_iprintf(buffer, "Preferred Sync Reference: %s\n", | |
3088 | pref_sync_ref); | |
3089 | ||
3090 | snd_iprintf(buffer, "System Clock Frequency: %d\n", | |
3091 | hdspm->system_sample_rate); | |
3092 | ||
3093 | ||
3094 | snd_iprintf(buffer, "--- Status:\n"); | |
3095 | ||
3096 | x = status & HDSPM_madiSync; | |
3097 | x2 = status2 & HDSPM_wcSync; | |
3098 | ||
3099 | snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n", | |
3100 | (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") : | |
3101 | "NoLock", | |
3102 | (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") : | |
3103 | "NoLock"); | |
3104 | ||
3105 | switch (hdspm_autosync_ref(hdspm)) { | |
3106 | case HDSPM_AUTOSYNC_FROM_WORD: | |
3107 | autosync_ref = "Word Clock"; | |
3108 | break; | |
3109 | case HDSPM_AUTOSYNC_FROM_MADI: | |
3110 | autosync_ref = "MADI Sync"; | |
3111 | break; | |
3112 | case HDSPM_AUTOSYNC_FROM_NONE: | |
3113 | autosync_ref = "Input not valid"; | |
3114 | break; | |
3115 | default: | |
3116 | autosync_ref = "---"; | |
3117 | break; | |
3118 | } | |
3119 | snd_iprintf(buffer, | |
3120 | "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n", | |
3121 | autosync_ref, hdspm_external_sample_rate(hdspm), | |
3122 | (status & HDSPM_madiFreqMask) >> 22, | |
3123 | (status2 & HDSPM_wcFreqMask) >> 5); | |
3124 | ||
3125 | snd_iprintf(buffer, "Input: %s, Mode=%s\n", | |
3126 | (status & HDSPM_AB_int) ? "Coax" : "Optical", | |
3127 | (status & HDSPM_RX_64ch) ? "64 channels" : | |
3128 | "56 channels"); | |
3129 | ||
3130 | snd_iprintf(buffer, "\n"); | |
3131 | } | |
3132 | ||
3cee5a60 RB |
3133 | static void |
3134 | snd_hdspm_proc_read_aes32(struct snd_info_entry * entry, | |
3135 | struct snd_info_buffer *buffer) | |
3136 | { | |
ef5fa1a4 | 3137 | struct hdspm *hdspm = entry->private_data; |
3cee5a60 RB |
3138 | unsigned int status; |
3139 | unsigned int status2; | |
3140 | unsigned int timecode; | |
3141 | int pref_syncref; | |
3142 | char *autosync_ref; | |
3143 | char *system_clock_mode; | |
3144 | char *clock_source; | |
3145 | int x; | |
3146 | ||
3147 | status = hdspm_read(hdspm, HDSPM_statusRegister); | |
3148 | status2 = hdspm_read(hdspm, HDSPM_statusRegister2); | |
3149 | timecode = hdspm_read(hdspm, HDSPM_timecodeRegister); | |
3150 | ||
3151 | snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n", | |
3152 | hdspm->card_name, hdspm->card->number + 1, | |
3153 | hdspm->firmware_rev); | |
3154 | ||
3155 | snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", | |
3156 | hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase); | |
3157 | ||
3158 | snd_iprintf(buffer, "--- System ---\n"); | |
3159 | ||
3160 | snd_iprintf(buffer, | |
3161 | "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n", | |
3162 | status & HDSPM_audioIRQPending, | |
3163 | (status & HDSPM_midi0IRQPending) ? 1 : 0, | |
3164 | (status & HDSPM_midi1IRQPending) ? 1 : 0, | |
3165 | hdspm->irq_count); | |
3166 | snd_iprintf(buffer, | |
ef5fa1a4 TI |
3167 | "HW pointer: id = %d, rawptr = %d (%d->%d) " |
3168 | "estimated= %ld (bytes)\n", | |
3cee5a60 RB |
3169 | ((status & HDSPM_BufferID) ? 1 : 0), |
3170 | (status & HDSPM_BufferPositionMask), | |
ef5fa1a4 TI |
3171 | (status & HDSPM_BufferPositionMask) % |
3172 | (2 * (int)hdspm->period_bytes), | |
3173 | ((status & HDSPM_BufferPositionMask) - 64) % | |
3174 | (2 * (int)hdspm->period_bytes), | |
3cee5a60 RB |
3175 | (long) hdspm_hw_pointer(hdspm) * 4); |
3176 | ||
3177 | snd_iprintf(buffer, | |
3178 | "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n", | |
3179 | hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF, | |
3180 | hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF, | |
3181 | hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF, | |
3182 | hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF); | |
3183 | snd_iprintf(buffer, | |
ef5fa1a4 TI |
3184 | "Register: ctrl1=0x%x, status1=0x%x, status2=0x%x, " |
3185 | "timecode=0x%x\n", | |
ffb2c3c0 | 3186 | hdspm->control_register, |
3cee5a60 RB |
3187 | status, status2, timecode); |
3188 | ||
3189 | snd_iprintf(buffer, "--- Settings ---\n"); | |
3190 | ||
ef5fa1a4 TI |
3191 | x = 1 << (6 + hdspm_decode_latency(hdspm->control_register & |
3192 | HDSPM_LatencyMask)); | |
3cee5a60 RB |
3193 | |
3194 | snd_iprintf(buffer, | |
3195 | "Size (Latency): %d samples (2 periods of %lu bytes)\n", | |
3196 | x, (unsigned long) hdspm->period_bytes); | |
3197 | ||
3198 | snd_iprintf(buffer, "Line out: %s, Precise Pointer: %s\n", | |
3199 | (hdspm-> | |
3200 | control_register & HDSPM_LineOut) ? "on " : "off", | |
3201 | (hdspm->precise_ptr) ? "on" : "off"); | |
3202 | ||
3203 | snd_iprintf(buffer, | |
3204 | "ClearTrackMarker %s, Emphasis %s, Dolby %s\n", | |
3205 | (hdspm-> | |
3206 | control_register & HDSPM_clr_tms) ? "on" : "off", | |
3207 | (hdspm-> | |
3208 | control_register & HDSPM_Emphasis) ? "on" : "off", | |
3209 | (hdspm-> | |
3210 | control_register & HDSPM_Dolby) ? "on" : "off"); | |
3211 | ||
3212 | switch (hdspm_clock_source(hdspm)) { | |
3213 | case HDSPM_CLOCK_SOURCE_AUTOSYNC: | |
3214 | clock_source = "AutoSync"; | |
3215 | break; | |
3216 | case HDSPM_CLOCK_SOURCE_INTERNAL_32KHZ: | |
3217 | clock_source = "Internal 32 kHz"; | |
3218 | break; | |
3219 | case HDSPM_CLOCK_SOURCE_INTERNAL_44_1KHZ: | |
3220 | clock_source = "Internal 44.1 kHz"; | |
3221 | break; | |
3222 | case HDSPM_CLOCK_SOURCE_INTERNAL_48KHZ: | |
3223 | clock_source = "Internal 48 kHz"; | |
3224 | break; | |
3225 | case HDSPM_CLOCK_SOURCE_INTERNAL_64KHZ: | |
3226 | clock_source = "Internal 64 kHz"; | |
3227 | break; | |
3228 | case HDSPM_CLOCK_SOURCE_INTERNAL_88_2KHZ: | |
3229 | clock_source = "Internal 88.2 kHz"; | |
3230 | break; | |
3231 | case HDSPM_CLOCK_SOURCE_INTERNAL_96KHZ: | |
3232 | clock_source = "Internal 96 kHz"; | |
3233 | break; | |
3234 | case HDSPM_CLOCK_SOURCE_INTERNAL_128KHZ: | |
3235 | clock_source = "Internal 128 kHz"; | |
3236 | break; | |
3237 | case HDSPM_CLOCK_SOURCE_INTERNAL_176_4KHZ: | |
3238 | clock_source = "Internal 176.4 kHz"; | |
3239 | break; | |
3240 | case HDSPM_CLOCK_SOURCE_INTERNAL_192KHZ: | |
3241 | clock_source = "Internal 192 kHz"; | |
3242 | break; | |
3243 | default: | |
3244 | clock_source = "Error"; | |
3245 | } | |
3246 | snd_iprintf(buffer, "Sample Clock Source: %s\n", clock_source); | |
3247 | if (!(hdspm->control_register & HDSPM_ClockModeMaster)) | |
3248 | system_clock_mode = "Slave"; | |
3249 | else | |
3250 | system_clock_mode = "Master"; | |
3251 | snd_iprintf(buffer, "System Clock Mode: %s\n", system_clock_mode); | |
3252 | ||
3253 | pref_syncref = hdspm_pref_sync_ref(hdspm); | |
3254 | if (pref_syncref == 0) | |
3255 | snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n"); | |
3256 | else | |
3257 | snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n", | |
3258 | pref_syncref); | |
3259 | ||
3260 | snd_iprintf(buffer, "System Clock Frequency: %d\n", | |
3261 | hdspm->system_sample_rate); | |
3262 | ||
3263 | snd_iprintf(buffer, "Double speed: %s\n", | |
3264 | hdspm->control_register & HDSPM_DS_DoubleWire? | |
3265 | "Double wire" : "Single wire"); | |
3266 | snd_iprintf(buffer, "Quad speed: %s\n", | |
3267 | hdspm->control_register & HDSPM_QS_DoubleWire? | |
3268 | "Double wire" : | |
3269 | hdspm->control_register & HDSPM_QS_QuadWire? | |
3270 | "Quad wire" : "Single wire"); | |
3271 | ||
3272 | snd_iprintf(buffer, "--- Status:\n"); | |
3273 | ||
3274 | snd_iprintf(buffer, "Word: %s Frequency: %d\n", | |
ef5fa1a4 TI |
3275 | (status & HDSPM_AES32_wcLock)? "Sync " : "No Lock", |
3276 | HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF)); | |
3cee5a60 RB |
3277 | |
3278 | for (x = 0; x < 8; x++) { | |
3279 | snd_iprintf(buffer, "AES%d: %s Frequency: %d\n", | |
ef5fa1a4 TI |
3280 | x+1, |
3281 | (status2 & (HDSPM_LockAES >> x)) ? | |
3282 | "Sync ": "No Lock", | |
3283 | HDSPM_bit2freq((timecode >> (4*x)) & 0xF)); | |
3cee5a60 RB |
3284 | } |
3285 | ||
3286 | switch (hdspm_autosync_ref(hdspm)) { | |
3287 | case HDSPM_AES32_AUTOSYNC_FROM_NONE: autosync_ref="None"; break; | |
3288 | case HDSPM_AES32_AUTOSYNC_FROM_WORD: autosync_ref="Word Clock"; break; | |
3289 | case HDSPM_AES32_AUTOSYNC_FROM_AES1: autosync_ref="AES1"; break; | |
3290 | case HDSPM_AES32_AUTOSYNC_FROM_AES2: autosync_ref="AES2"; break; | |
3291 | case HDSPM_AES32_AUTOSYNC_FROM_AES3: autosync_ref="AES3"; break; | |
3292 | case HDSPM_AES32_AUTOSYNC_FROM_AES4: autosync_ref="AES4"; break; | |
3293 | case HDSPM_AES32_AUTOSYNC_FROM_AES5: autosync_ref="AES5"; break; | |
3294 | case HDSPM_AES32_AUTOSYNC_FROM_AES6: autosync_ref="AES6"; break; | |
3295 | case HDSPM_AES32_AUTOSYNC_FROM_AES7: autosync_ref="AES7"; break; | |
3296 | case HDSPM_AES32_AUTOSYNC_FROM_AES8: autosync_ref="AES8"; break; | |
3297 | default: autosync_ref = "---"; break; | |
3298 | } | |
3299 | snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref); | |
3300 | ||
3301 | snd_iprintf(buffer, "\n"); | |
3302 | } | |
3303 | ||
3304 | #ifdef CONFIG_SND_DEBUG | |
3305 | static void | |
3306 | snd_hdspm_proc_read_debug(struct snd_info_entry * entry, | |
3307 | struct snd_info_buffer *buffer) | |
3308 | { | |
ef5fa1a4 | 3309 | struct hdspm *hdspm = entry->private_data; |
3cee5a60 RB |
3310 | |
3311 | int j,i; | |
3312 | ||
ef5fa1a4 | 3313 | for (i = 0; i < 256 /* 1024*64 */; i += j) { |
3cee5a60 RB |
3314 | snd_iprintf(buffer, "0x%08X: ", i); |
3315 | for (j = 0; j < 16; j += 4) | |
3316 | snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j)); | |
3317 | snd_iprintf(buffer, "\n"); | |
3318 | } | |
3319 | } | |
3320 | #endif | |
3321 | ||
3322 | ||
3323 | ||
98274f07 | 3324 | static void __devinit snd_hdspm_proc_init(struct hdspm * hdspm) |
763f356c | 3325 | { |
98274f07 | 3326 | struct snd_info_entry *entry; |
763f356c TI |
3327 | |
3328 | if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) | |
bf850204 | 3329 | snd_info_set_text_ops(entry, hdspm, |
3cee5a60 RB |
3330 | hdspm->is_aes32 ? |
3331 | snd_hdspm_proc_read_aes32 : | |
3332 | snd_hdspm_proc_read_madi); | |
3333 | #ifdef CONFIG_SND_DEBUG | |
3334 | /* debug file to read all hdspm registers */ | |
3335 | if (!snd_card_proc_new(hdspm->card, "debug", &entry)) | |
3336 | snd_info_set_text_ops(entry, hdspm, | |
3337 | snd_hdspm_proc_read_debug); | |
3338 | #endif | |
763f356c TI |
3339 | } |
3340 | ||
3341 | /*------------------------------------------------------------ | |
3342 | hdspm intitialize | |
3343 | ------------------------------------------------------------*/ | |
3344 | ||
98274f07 | 3345 | static int snd_hdspm_set_defaults(struct hdspm * hdspm) |
763f356c TI |
3346 | { |
3347 | unsigned int i; | |
3348 | ||
3349 | /* ASSUMPTION: hdspm->lock is either held, or there is no need to | |
561de31a | 3350 | hold it (e.g. during module initialization). |
763f356c TI |
3351 | */ |
3352 | ||
3353 | /* set defaults: */ | |
3354 | ||
3cee5a60 | 3355 | if (hdspm->is_aes32) |
ef5fa1a4 TI |
3356 | hdspm->control_register = |
3357 | HDSPM_ClockModeMaster | /* Master Cloack Mode on */ | |
3358 | hdspm_encode_latency(7) | /* latency maximum = | |
3359 | * 8192 samples | |
3360 | */ | |
3cee5a60 RB |
3361 | HDSPM_SyncRef0 | /* AES1 is syncclock */ |
3362 | HDSPM_LineOut | /* Analog output in */ | |
3363 | HDSPM_Professional; /* Professional mode */ | |
3364 | else | |
ef5fa1a4 TI |
3365 | hdspm->control_register = |
3366 | HDSPM_ClockModeMaster | /* Master Cloack Mode on */ | |
3367 | hdspm_encode_latency(7) | /* latency maximum = | |
3368 | * 8192 samples | |
3369 | */ | |
3cee5a60 RB |
3370 | HDSPM_InputCoaxial | /* Input Coax not Optical */ |
3371 | HDSPM_SyncRef_MADI | /* Madi is syncclock */ | |
3372 | HDSPM_LineOut | /* Analog output in */ | |
3373 | HDSPM_TX_64ch | /* transmit in 64ch mode */ | |
3374 | HDSPM_AutoInp; /* AutoInput chossing (takeover) */ | |
763f356c TI |
3375 | |
3376 | /* ! HDSPM_Frequency0|HDSPM_Frequency1 = 44.1khz */ | |
3377 | /* ! HDSPM_DoubleSpeed HDSPM_QuadSpeed = normal speed */ | |
3378 | /* ! HDSPM_clr_tms = do not clear bits in track marks */ | |
3379 | ||
3380 | hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); | |
3381 | ||
ffb2c3c0 RB |
3382 | if (!hdspm->is_aes32) { |
3383 | /* No control2 register for AES32 */ | |
763f356c | 3384 | #ifdef SNDRV_BIG_ENDIAN |
ffb2c3c0 | 3385 | hdspm->control2_register = HDSPM_BIGENDIAN_MODE; |
763f356c | 3386 | #else |
ffb2c3c0 | 3387 | hdspm->control2_register = 0; |
763f356c TI |
3388 | #endif |
3389 | ||
ffb2c3c0 RB |
3390 | hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register); |
3391 | } | |
763f356c TI |
3392 | hdspm_compute_period_size(hdspm); |
3393 | ||
3394 | /* silence everything */ | |
3395 | ||
3396 | all_in_all_mixer(hdspm, 0 * UNITY_GAIN); | |
3397 | ||
3398 | if (line_outs_monitor[hdspm->dev]) { | |
3399 | ||
ef5fa1a4 TI |
3400 | snd_printk(KERN_INFO "HDSPM: " |
3401 | "sending all playback streams to line outs.\n"); | |
763f356c TI |
3402 | |
3403 | for (i = 0; i < HDSPM_MIXER_CHANNELS; i++) { | |
3404 | if (hdspm_write_pb_gain(hdspm, i, i, UNITY_GAIN)) | |
3405 | return -EIO; | |
3406 | } | |
3407 | } | |
3408 | ||
3409 | /* set a default rate so that the channel map is set up. */ | |
3410 | hdspm->channel_map = channel_map_madi_ss; | |
3411 | hdspm_set_rate(hdspm, 44100, 1); | |
3412 | ||
3413 | return 0; | |
3414 | } | |
3415 | ||
3416 | ||
3417 | /*------------------------------------------------------------ | |
561de31a | 3418 | interrupt |
763f356c TI |
3419 | ------------------------------------------------------------*/ |
3420 | ||
7d12e780 | 3421 | static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id) |
763f356c | 3422 | { |
98274f07 | 3423 | struct hdspm *hdspm = (struct hdspm *) dev_id; |
763f356c TI |
3424 | unsigned int status; |
3425 | int audio; | |
3426 | int midi0; | |
3427 | int midi1; | |
3428 | unsigned int midi0status; | |
3429 | unsigned int midi1status; | |
3430 | int schedule = 0; | |
3431 | ||
3432 | status = hdspm_read(hdspm, HDSPM_statusRegister); | |
3433 | ||
3434 | audio = status & HDSPM_audioIRQPending; | |
3435 | midi0 = status & HDSPM_midi0IRQPending; | |
3436 | midi1 = status & HDSPM_midi1IRQPending; | |
3437 | ||
3438 | if (!audio && !midi0 && !midi1) | |
3439 | return IRQ_NONE; | |
3440 | ||
3441 | hdspm_write(hdspm, HDSPM_interruptConfirmation, 0); | |
3442 | hdspm->irq_count++; | |
3443 | ||
3444 | midi0status = hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xff; | |
3445 | midi1status = hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xff; | |
3446 | ||
3447 | if (audio) { | |
3448 | ||
3449 | if (hdspm->capture_substream) | |
ef5fa1a4 | 3450 | snd_pcm_period_elapsed(hdspm->capture_substream); |
763f356c TI |
3451 | |
3452 | if (hdspm->playback_substream) | |
ef5fa1a4 | 3453 | snd_pcm_period_elapsed(hdspm->playback_substream); |
763f356c TI |
3454 | } |
3455 | ||
3456 | if (midi0 && midi0status) { | |
ef5fa1a4 TI |
3457 | /* we disable interrupts for this input until processing |
3458 | * is done | |
3459 | */ | |
763f356c TI |
3460 | hdspm->control_register &= ~HDSPM_Midi0InterruptEnable; |
3461 | hdspm_write(hdspm, HDSPM_controlRegister, | |
3462 | hdspm->control_register); | |
3463 | hdspm->midi[0].pending = 1; | |
3464 | schedule = 1; | |
3465 | } | |
3466 | if (midi1 && midi1status) { | |
ef5fa1a4 TI |
3467 | /* we disable interrupts for this input until processing |
3468 | * is done | |
3469 | */ | |
763f356c TI |
3470 | hdspm->control_register &= ~HDSPM_Midi1InterruptEnable; |
3471 | hdspm_write(hdspm, HDSPM_controlRegister, | |
3472 | hdspm->control_register); | |
3473 | hdspm->midi[1].pending = 1; | |
3474 | schedule = 1; | |
3475 | } | |
3476 | if (schedule) | |
3477 | tasklet_hi_schedule(&hdspm->midi_tasklet); | |
3478 | return IRQ_HANDLED; | |
3479 | } | |
3480 | ||
3481 | /*------------------------------------------------------------ | |
3482 | pcm interface | |
3483 | ------------------------------------------------------------*/ | |
3484 | ||
3485 | ||
98274f07 | 3486 | static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream * |
763f356c TI |
3487 | substream) |
3488 | { | |
98274f07 | 3489 | struct hdspm *hdspm = snd_pcm_substream_chip(substream); |
763f356c TI |
3490 | return hdspm_hw_pointer(hdspm); |
3491 | } | |
3492 | ||
98274f07 | 3493 | static char *hdspm_channel_buffer_location(struct hdspm * hdspm, |
763f356c TI |
3494 | int stream, int channel) |
3495 | { | |
3496 | int mapped_channel; | |
3497 | ||
3498 | snd_assert(channel >= 0 | |
3499 | || channel < HDSPM_MAX_CHANNELS, return NULL); | |
3500 | ||
ef5fa1a4 TI |
3501 | mapped_channel = hdspm->channel_map[channel]; |
3502 | if (mapped_channel < 0) | |
763f356c TI |
3503 | return NULL; |
3504 | ||
ef5fa1a4 | 3505 | if (stream == SNDRV_PCM_STREAM_CAPTURE) |
763f356c TI |
3506 | return hdspm->capture_buffer + |
3507 | mapped_channel * HDSPM_CHANNEL_BUFFER_BYTES; | |
ef5fa1a4 | 3508 | else |
763f356c TI |
3509 | return hdspm->playback_buffer + |
3510 | mapped_channel * HDSPM_CHANNEL_BUFFER_BYTES; | |
763f356c TI |
3511 | } |
3512 | ||
3513 | ||
3514 | /* dont know why need it ??? */ | |
98274f07 | 3515 | static int snd_hdspm_playback_copy(struct snd_pcm_substream *substream, |
763f356c TI |
3516 | int channel, snd_pcm_uframes_t pos, |
3517 | void __user *src, snd_pcm_uframes_t count) | |
3518 | { | |
98274f07 | 3519 | struct hdspm *hdspm = snd_pcm_substream_chip(substream); |
763f356c TI |
3520 | char *channel_buf; |
3521 | ||
3522 | snd_assert(pos + count <= HDSPM_CHANNEL_BUFFER_BYTES / 4, | |
3523 | return -EINVAL); | |
3524 | ||
ef5fa1a4 TI |
3525 | channel_buf = |
3526 | hdspm_channel_buffer_location(hdspm, substream->pstr->stream, | |
3527 | channel); | |
763f356c TI |
3528 | |
3529 | snd_assert(channel_buf != NULL, return -EIO); | |
3530 | ||
3531 | return copy_from_user(channel_buf + pos * 4, src, count * 4); | |
3532 | } | |
3533 | ||
98274f07 | 3534 | static int snd_hdspm_capture_copy(struct snd_pcm_substream *substream, |
763f356c TI |
3535 | int channel, snd_pcm_uframes_t pos, |
3536 | void __user *dst, snd_pcm_uframes_t count) | |
3537 | { | |
98274f07 | 3538 | struct hdspm *hdspm = snd_pcm_substream_chip(substream); |
763f356c TI |
3539 | char *channel_buf; |
3540 | ||
3541 | snd_assert(pos + count <= HDSPM_CHANNEL_BUFFER_BYTES / 4, | |
3542 | return -EINVAL); | |
3543 | ||
ef5fa1a4 TI |
3544 | channel_buf = |
3545 | hdspm_channel_buffer_location(hdspm, substream->pstr->stream, | |
3546 | channel); | |
763f356c TI |
3547 | snd_assert(channel_buf != NULL, return -EIO); |
3548 | return copy_to_user(dst, channel_buf + pos * 4, count * 4); | |
3549 | } | |
3550 | ||
98274f07 | 3551 | static int snd_hdspm_hw_silence(struct snd_pcm_substream *substream, |
763f356c TI |
3552 | int channel, snd_pcm_uframes_t pos, |
3553 | snd_pcm_uframes_t count) | |
3554 | { | |
98274f07 | 3555 | struct hdspm *hdspm = snd_pcm_substream_chip(substream); |
763f356c TI |
3556 | char *channel_buf; |
3557 | ||
3558 | channel_buf = | |
ef5fa1a4 TI |
3559 | hdspm_channel_buffer_location(hdspm, substream->pstr->stream, |
3560 | channel); | |
763f356c TI |
3561 | snd_assert(channel_buf != NULL, return -EIO); |
3562 | memset(channel_buf + pos * 4, 0, count * 4); | |
3563 | return 0; | |
3564 | } | |
3565 | ||
98274f07 | 3566 | static int snd_hdspm_reset(struct snd_pcm_substream *substream) |
763f356c | 3567 | { |
98274f07 TI |
3568 | struct snd_pcm_runtime *runtime = substream->runtime; |
3569 | struct hdspm *hdspm = snd_pcm_substream_chip(substream); | |
3570 | struct snd_pcm_substream *other; | |
763f356c TI |
3571 | |
3572 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
3573 | other = hdspm->capture_substream; | |
3574 | else | |
3575 | other = hdspm->playback_substream; | |
3576 | ||
3577 | if (hdspm->running) | |
3578 | runtime->status->hw_ptr = hdspm_hw_pointer(hdspm); | |
3579 | else | |
3580 | runtime->status->hw_ptr = 0; | |
3581 | if (other) { | |
98274f07 TI |
3582 | struct snd_pcm_substream *s; |
3583 | struct snd_pcm_runtime *oruntime = other->runtime; | |
ef991b95 | 3584 | snd_pcm_group_for_each_entry(s, substream) { |
763f356c TI |
3585 | if (s == other) { |
3586 | oruntime->status->hw_ptr = | |
3587 | runtime->status->hw_ptr; | |
3588 | break; | |
3589 | } | |
3590 | } | |
3591 | } | |
3592 | return 0; | |
3593 | } | |
3594 | ||
98274f07 TI |
3595 | static int snd_hdspm_hw_params(struct snd_pcm_substream *substream, |
3596 | struct snd_pcm_hw_params *params) | |
763f356c | 3597 | { |
98274f07 | 3598 | struct hdspm *hdspm = snd_pcm_substream_chip(substream); |
763f356c TI |
3599 | int err; |
3600 | int i; | |
3601 | pid_t this_pid; | |
3602 | pid_t other_pid; | |
3603 | struct snd_sg_buf *sgbuf; | |
3604 | ||
3605 | ||
3606 | spin_lock_irq(&hdspm->lock); | |
3607 | ||
3608 | if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
3609 | this_pid = hdspm->playback_pid; | |
3610 | other_pid = hdspm->capture_pid; | |
3611 | } else { | |
3612 | this_pid = hdspm->capture_pid; | |
3613 | other_pid = hdspm->playback_pid; | |
3614 | } | |
3615 | ||
ef5fa1a4 | 3616 | if (other_pid > 0 && this_pid != other_pid) { |
763f356c TI |
3617 | |
3618 | /* The other stream is open, and not by the same | |
3619 | task as this one. Make sure that the parameters | |
3620 | that matter are the same. | |
3621 | */ | |
3622 | ||
3623 | if (params_rate(params) != hdspm->system_sample_rate) { | |
3624 | spin_unlock_irq(&hdspm->lock); | |
3625 | _snd_pcm_hw_param_setempty(params, | |
3626 | SNDRV_PCM_HW_PARAM_RATE); | |
3627 | return -EBUSY; | |
3628 | } | |
3629 | ||
3630 | if (params_period_size(params) != hdspm->period_bytes / 4) { | |
3631 | spin_unlock_irq(&hdspm->lock); | |
3632 | _snd_pcm_hw_param_setempty(params, | |
ef5fa1a4 | 3633 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE); |
763f356c TI |
3634 | return -EBUSY; |
3635 | } | |
3636 | ||
3637 | } | |
3638 | /* We're fine. */ | |
3639 | spin_unlock_irq(&hdspm->lock); | |
3640 | ||
3641 | /* how to make sure that the rate matches an externally-set one ? */ | |
3642 | ||
3643 | spin_lock_irq(&hdspm->lock); | |
ef5fa1a4 TI |
3644 | err = hdspm_set_rate(hdspm, params_rate(params), 0); |
3645 | if (err < 0) { | |
763f356c TI |
3646 | spin_unlock_irq(&hdspm->lock); |
3647 | _snd_pcm_hw_param_setempty(params, | |
3648 | SNDRV_PCM_HW_PARAM_RATE); | |
3649 | return err; | |
3650 | } | |
3651 | spin_unlock_irq(&hdspm->lock); | |
3652 | ||
ef5fa1a4 TI |
3653 | err = hdspm_set_interrupt_interval(hdspm, |
3654 | params_period_size(params)); | |
3655 | if (err < 0) { | |
763f356c TI |
3656 | _snd_pcm_hw_param_setempty(params, |
3657 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE); | |
3658 | return err; | |
3659 | } | |
3660 | ||
ef5fa1a4 TI |
3661 | /* Memory allocation, takashi's method, dont know if we should |
3662 | * spinlock | |
3663 | */ | |
763f356c | 3664 | /* malloc all buffer even if not enabled to get sure */ |
ffb2c3c0 RB |
3665 | /* Update for MADI rev 204: we need to allocate for all channels, |
3666 | * otherwise it doesn't work at 96kHz */ | |
763f356c | 3667 | err = |
ffb2c3c0 | 3668 | snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES); |
763f356c TI |
3669 | if (err < 0) |
3670 | return err; | |
3671 | ||
3672 | sgbuf = snd_pcm_substream_sgbuf(substream); | |
3673 | ||
3674 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
3675 | ||
3676 | hdspm_set_sgbuf(hdspm, sgbuf, HDSPM_pageAddressBufferOut, | |
3677 | params_channels(params)); | |
3678 | ||
3679 | for (i = 0; i < params_channels(params); ++i) | |
3680 | snd_hdspm_enable_out(hdspm, i, 1); | |
3681 | ||
3682 | hdspm->playback_buffer = | |
3683 | (unsigned char *) substream->runtime->dma_area; | |
54bf5dd9 | 3684 | snd_printdd("Allocated sample buffer for playback at %p\n", |
3cee5a60 | 3685 | hdspm->playback_buffer); |
763f356c TI |
3686 | } else { |
3687 | hdspm_set_sgbuf(hdspm, sgbuf, HDSPM_pageAddressBufferIn, | |
3688 | params_channels(params)); | |
3689 | ||
3690 | for (i = 0; i < params_channels(params); ++i) | |
3691 | snd_hdspm_enable_in(hdspm, i, 1); | |
3692 | ||
3693 | hdspm->capture_buffer = | |
3694 | (unsigned char *) substream->runtime->dma_area; | |
54bf5dd9 | 3695 | snd_printdd("Allocated sample buffer for capture at %p\n", |
3cee5a60 | 3696 | hdspm->capture_buffer); |
763f356c | 3697 | } |
3cee5a60 RB |
3698 | /* |
3699 | snd_printdd("Allocated sample buffer for %s at 0x%08X\n", | |
3700 | substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? | |
3701 | "playback" : "capture", | |
3702 | snd_pcm_sgbuf_get_addr(sgbuf, 0)); | |
3703 | */ | |
ffb2c3c0 RB |
3704 | /* |
3705 | snd_printdd("set_hwparams: %s %d Hz, %d channels, bs = %d\n", | |
3706 | substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? | |
3707 | "playback" : "capture", | |
3708 | params_rate(params), params_channels(params), | |
3709 | params_buffer_size(params)); | |
3710 | */ | |
763f356c TI |
3711 | return 0; |
3712 | } | |
3713 | ||
98274f07 | 3714 | static int snd_hdspm_hw_free(struct snd_pcm_substream *substream) |
763f356c TI |
3715 | { |
3716 | int i; | |
98274f07 | 3717 | struct hdspm *hdspm = snd_pcm_substream_chip(substream); |
763f356c TI |
3718 | |
3719 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
3720 | ||
3721 | /* params_channels(params) should be enough, | |
3722 | but to get sure in case of error */ | |
3723 | for (i = 0; i < HDSPM_MAX_CHANNELS; ++i) | |
3724 | snd_hdspm_enable_out(hdspm, i, 0); | |
3725 | ||
3726 | hdspm->playback_buffer = NULL; | |
3727 | } else { | |
3728 | for (i = 0; i < HDSPM_MAX_CHANNELS; ++i) | |
3729 | snd_hdspm_enable_in(hdspm, i, 0); | |
3730 | ||
3731 | hdspm->capture_buffer = NULL; | |
3732 | ||
3733 | } | |
3734 | ||
3735 | snd_pcm_lib_free_pages(substream); | |
3736 | ||
3737 | return 0; | |
3738 | } | |
3739 | ||
98274f07 TI |
3740 | static int snd_hdspm_channel_info(struct snd_pcm_substream *substream, |
3741 | struct snd_pcm_channel_info * info) | |
763f356c | 3742 | { |
98274f07 | 3743 | struct hdspm *hdspm = snd_pcm_substream_chip(substream); |
763f356c TI |
3744 | int mapped_channel; |
3745 | ||
3746 | snd_assert(info->channel < HDSPM_MAX_CHANNELS, return -EINVAL); | |
3747 | ||
ef5fa1a4 TI |
3748 | mapped_channel = hdspm->channel_map[info->channel]; |
3749 | if (mapped_channel < 0) | |
763f356c TI |
3750 | return -EINVAL; |
3751 | ||
3752 | info->offset = mapped_channel * HDSPM_CHANNEL_BUFFER_BYTES; | |
3753 | info->first = 0; | |
3754 | info->step = 32; | |
3755 | return 0; | |
3756 | } | |
3757 | ||
98274f07 | 3758 | static int snd_hdspm_ioctl(struct snd_pcm_substream *substream, |
763f356c TI |
3759 | unsigned int cmd, void *arg) |
3760 | { | |
3761 | switch (cmd) { | |
3762 | case SNDRV_PCM_IOCTL1_RESET: | |
ef5fa1a4 | 3763 | return snd_hdspm_reset(substream); |
763f356c TI |
3764 | |
3765 | case SNDRV_PCM_IOCTL1_CHANNEL_INFO: | |
ef5fa1a4 TI |
3766 | { |
3767 | struct snd_pcm_channel_info *info = arg; | |
3768 | return snd_hdspm_channel_info(substream, info); | |
3769 | } | |
763f356c TI |
3770 | default: |
3771 | break; | |
3772 | } | |
3773 | ||
3774 | return snd_pcm_lib_ioctl(substream, cmd, arg); | |
3775 | } | |
3776 | ||
98274f07 | 3777 | static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd) |
763f356c | 3778 | { |
98274f07 TI |
3779 | struct hdspm *hdspm = snd_pcm_substream_chip(substream); |
3780 | struct snd_pcm_substream *other; | |
763f356c TI |
3781 | int running; |
3782 | ||
3783 | spin_lock(&hdspm->lock); | |
3784 | running = hdspm->running; | |
3785 | switch (cmd) { | |
3786 | case SNDRV_PCM_TRIGGER_START: | |
3787 | running |= 1 << substream->stream; | |
3788 | break; | |
3789 | case SNDRV_PCM_TRIGGER_STOP: | |
3790 | running &= ~(1 << substream->stream); | |
3791 | break; | |
3792 | default: | |
3793 | snd_BUG(); | |
3794 | spin_unlock(&hdspm->lock); | |
3795 | return -EINVAL; | |
3796 | } | |
3797 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
3798 | other = hdspm->capture_substream; | |
3799 | else | |
3800 | other = hdspm->playback_substream; | |
3801 | ||
3802 | if (other) { | |
98274f07 | 3803 | struct snd_pcm_substream *s; |
ef991b95 | 3804 | snd_pcm_group_for_each_entry(s, substream) { |
763f356c TI |
3805 | if (s == other) { |
3806 | snd_pcm_trigger_done(s, substream); | |
3807 | if (cmd == SNDRV_PCM_TRIGGER_START) | |
3808 | running |= 1 << s->stream; | |
3809 | else | |
3810 | running &= ~(1 << s->stream); | |
3811 | goto _ok; | |
3812 | } | |
3813 | } | |
3814 | if (cmd == SNDRV_PCM_TRIGGER_START) { | |
3815 | if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) | |
3816 | && substream->stream == | |
3817 | SNDRV_PCM_STREAM_CAPTURE) | |
3818 | hdspm_silence_playback(hdspm); | |
3819 | } else { | |
3820 | if (running && | |
3821 | substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
3822 | hdspm_silence_playback(hdspm); | |
3823 | } | |
3824 | } else { | |
3825 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) | |
3826 | hdspm_silence_playback(hdspm); | |
3827 | } | |
3828 | _ok: | |
3829 | snd_pcm_trigger_done(substream, substream); | |
3830 | if (!hdspm->running && running) | |
3831 | hdspm_start_audio(hdspm); | |
3832 | else if (hdspm->running && !running) | |
3833 | hdspm_stop_audio(hdspm); | |
3834 | hdspm->running = running; | |
3835 | spin_unlock(&hdspm->lock); | |
3836 | ||
3837 | return 0; | |
3838 | } | |
3839 | ||
98274f07 | 3840 | static int snd_hdspm_prepare(struct snd_pcm_substream *substream) |
763f356c TI |
3841 | { |
3842 | return 0; | |
3843 | } | |
3844 | ||
3845 | static unsigned int period_sizes[] = | |
3846 | { 64, 128, 256, 512, 1024, 2048, 4096, 8192 }; | |
3847 | ||
98274f07 | 3848 | static struct snd_pcm_hardware snd_hdspm_playback_subinfo = { |
763f356c TI |
3849 | .info = (SNDRV_PCM_INFO_MMAP | |
3850 | SNDRV_PCM_INFO_MMAP_VALID | | |
3851 | SNDRV_PCM_INFO_NONINTERLEAVED | | |
3852 | SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE), | |
3853 | .formats = SNDRV_PCM_FMTBIT_S32_LE, | |
3854 | .rates = (SNDRV_PCM_RATE_32000 | | |
3855 | SNDRV_PCM_RATE_44100 | | |
3856 | SNDRV_PCM_RATE_48000 | | |
3857 | SNDRV_PCM_RATE_64000 | | |
3cee5a60 RB |
3858 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | |
3859 | SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ), | |
763f356c | 3860 | .rate_min = 32000, |
3cee5a60 | 3861 | .rate_max = 192000, |
763f356c TI |
3862 | .channels_min = 1, |
3863 | .channels_max = HDSPM_MAX_CHANNELS, | |
3864 | .buffer_bytes_max = | |
3865 | HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS, | |
3866 | .period_bytes_min = (64 * 4), | |
3867 | .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS, | |
3868 | .periods_min = 2, | |
3869 | .periods_max = 2, | |
3870 | .fifo_size = 0 | |
3871 | }; | |
3872 | ||
98274f07 | 3873 | static struct snd_pcm_hardware snd_hdspm_capture_subinfo = { |
763f356c TI |
3874 | .info = (SNDRV_PCM_INFO_MMAP | |
3875 | SNDRV_PCM_INFO_MMAP_VALID | | |
3876 | SNDRV_PCM_INFO_NONINTERLEAVED | | |
3877 | SNDRV_PCM_INFO_SYNC_START), | |
3878 | .formats = SNDRV_PCM_FMTBIT_S32_LE, | |
3879 | .rates = (SNDRV_PCM_RATE_32000 | | |
3880 | SNDRV_PCM_RATE_44100 | | |
3881 | SNDRV_PCM_RATE_48000 | | |
3882 | SNDRV_PCM_RATE_64000 | | |
3cee5a60 RB |
3883 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | |
3884 | SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000), | |
763f356c | 3885 | .rate_min = 32000, |
3cee5a60 | 3886 | .rate_max = 192000, |
763f356c TI |
3887 | .channels_min = 1, |
3888 | .channels_max = HDSPM_MAX_CHANNELS, | |
3889 | .buffer_bytes_max = | |
3890 | HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS, | |
3891 | .period_bytes_min = (64 * 4), | |
3892 | .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS, | |
3893 | .periods_min = 2, | |
3894 | .periods_max = 2, | |
3895 | .fifo_size = 0 | |
3896 | }; | |
3897 | ||
98274f07 | 3898 | static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes = { |
763f356c TI |
3899 | .count = ARRAY_SIZE(period_sizes), |
3900 | .list = period_sizes, | |
3901 | .mask = 0 | |
3902 | }; | |
3903 | ||
3904 | ||
98274f07 TI |
3905 | static int snd_hdspm_hw_rule_channels_rate(struct snd_pcm_hw_params *params, |
3906 | struct snd_pcm_hw_rule * rule) | |
763f356c | 3907 | { |
98274f07 TI |
3908 | struct hdspm *hdspm = rule->private; |
3909 | struct snd_interval *c = | |
763f356c | 3910 | hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); |
98274f07 | 3911 | struct snd_interval *r = |
763f356c TI |
3912 | hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); |
3913 | ||
ffb2c3c0 | 3914 | if (r->min > 48000 && r->max <= 96000) { |
98274f07 | 3915 | struct snd_interval t = { |
ffb2c3c0 | 3916 | .min = hdspm->ds_channels, |
763f356c TI |
3917 | .max = hdspm->ds_channels, |
3918 | .integer = 1, | |
3919 | }; | |
3920 | return snd_interval_refine(c, &t); | |
3921 | } else if (r->max < 64000) { | |
98274f07 | 3922 | struct snd_interval t = { |
ffb2c3c0 | 3923 | .min = hdspm->ss_channels, |
763f356c TI |
3924 | .max = hdspm->ss_channels, |
3925 | .integer = 1, | |
3926 | }; | |
3927 | return snd_interval_refine(c, &t); | |
3928 | } | |
3929 | return 0; | |
3930 | } | |
3931 | ||
98274f07 TI |
3932 | static int snd_hdspm_hw_rule_rate_channels(struct snd_pcm_hw_params *params, |
3933 | struct snd_pcm_hw_rule * rule) | |
763f356c | 3934 | { |
98274f07 TI |
3935 | struct hdspm *hdspm = rule->private; |
3936 | struct snd_interval *c = | |
763f356c | 3937 | hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); |
98274f07 | 3938 | struct snd_interval *r = |
763f356c TI |
3939 | hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); |
3940 | ||
ffb2c3c0 | 3941 | if (c->min >= hdspm->ss_channels) { |
98274f07 | 3942 | struct snd_interval t = { |
763f356c TI |
3943 | .min = 32000, |
3944 | .max = 48000, | |
3945 | .integer = 1, | |
3946 | }; | |
3947 | return snd_interval_refine(r, &t); | |
ffb2c3c0 | 3948 | } else if (c->max <= hdspm->ds_channels) { |
98274f07 | 3949 | struct snd_interval t = { |
763f356c TI |
3950 | .min = 64000, |
3951 | .max = 96000, | |
3952 | .integer = 1, | |
3953 | }; | |
3954 | ||
3955 | return snd_interval_refine(r, &t); | |
3956 | } | |
3957 | return 0; | |
3958 | } | |
3959 | ||
ffb2c3c0 RB |
3960 | static int snd_hdspm_hw_rule_channels(struct snd_pcm_hw_params *params, |
3961 | struct snd_pcm_hw_rule *rule) | |
3962 | { | |
3963 | unsigned int list[3]; | |
3964 | struct hdspm *hdspm = rule->private; | |
3965 | struct snd_interval *c = hw_param_interval(params, | |
3966 | SNDRV_PCM_HW_PARAM_CHANNELS); | |
3967 | if (hdspm->is_aes32) { | |
3968 | list[0] = hdspm->qs_channels; | |
3969 | list[1] = hdspm->ds_channels; | |
3970 | list[2] = hdspm->ss_channels; | |
3971 | return snd_interval_list(c, 3, list, 0); | |
3972 | } else { | |
3973 | list[0] = hdspm->ds_channels; | |
3974 | list[1] = hdspm->ss_channels; | |
3975 | return snd_interval_list(c, 2, list, 0); | |
3976 | } | |
3977 | } | |
3978 | ||
3979 | ||
ef5fa1a4 TI |
3980 | static unsigned int hdspm_aes32_sample_rates[] = { |
3981 | 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 | |
3982 | }; | |
ffb2c3c0 | 3983 | |
ef5fa1a4 TI |
3984 | static struct snd_pcm_hw_constraint_list |
3985 | hdspm_hw_constraints_aes32_sample_rates = { | |
ffb2c3c0 RB |
3986 | .count = ARRAY_SIZE(hdspm_aes32_sample_rates), |
3987 | .list = hdspm_aes32_sample_rates, | |
3988 | .mask = 0 | |
3989 | }; | |
3990 | ||
98274f07 | 3991 | static int snd_hdspm_playback_open(struct snd_pcm_substream *substream) |
763f356c | 3992 | { |
98274f07 TI |
3993 | struct hdspm *hdspm = snd_pcm_substream_chip(substream); |
3994 | struct snd_pcm_runtime *runtime = substream->runtime; | |
763f356c | 3995 | |
763f356c TI |
3996 | spin_lock_irq(&hdspm->lock); |
3997 | ||
3998 | snd_pcm_set_sync(substream); | |
3999 | ||
4000 | runtime->hw = snd_hdspm_playback_subinfo; | |
4001 | ||
4002 | if (hdspm->capture_substream == NULL) | |
4003 | hdspm_stop_audio(hdspm); | |
4004 | ||
4005 | hdspm->playback_pid = current->pid; | |
4006 | hdspm->playback_substream = substream; | |
4007 | ||
4008 | spin_unlock_irq(&hdspm->lock); | |
4009 | ||
4010 | snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); | |
4011 | ||
4012 | snd_pcm_hw_constraint_list(runtime, 0, | |
4013 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE, | |
4014 | &hw_constraints_period_sizes); | |
4015 | ||
ffb2c3c0 RB |
4016 | if (hdspm->is_aes32) { |
4017 | snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, | |
4018 | &hdspm_hw_constraints_aes32_sample_rates); | |
4019 | } else { | |
4020 | snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, | |
4021 | snd_hdspm_hw_rule_channels, hdspm, | |
4022 | SNDRV_PCM_HW_PARAM_CHANNELS, -1); | |
4023 | snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, | |
4024 | snd_hdspm_hw_rule_channels_rate, hdspm, | |
4025 | SNDRV_PCM_HW_PARAM_RATE, -1); | |
4026 | ||
4027 | snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, | |
4028 | snd_hdspm_hw_rule_rate_channels, hdspm, | |
4029 | SNDRV_PCM_HW_PARAM_CHANNELS, -1); | |
4030 | } | |
763f356c TI |
4031 | return 0; |
4032 | } | |
4033 | ||
98274f07 | 4034 | static int snd_hdspm_playback_release(struct snd_pcm_substream *substream) |
763f356c | 4035 | { |
98274f07 | 4036 | struct hdspm *hdspm = snd_pcm_substream_chip(substream); |
763f356c TI |
4037 | |
4038 | spin_lock_irq(&hdspm->lock); | |
4039 | ||
4040 | hdspm->playback_pid = -1; | |
4041 | hdspm->playback_substream = NULL; | |
4042 | ||
4043 | spin_unlock_irq(&hdspm->lock); | |
4044 | ||
4045 | return 0; | |
4046 | } | |
4047 | ||
4048 | ||
98274f07 | 4049 | static int snd_hdspm_capture_open(struct snd_pcm_substream *substream) |
763f356c | 4050 | { |
98274f07 TI |
4051 | struct hdspm *hdspm = snd_pcm_substream_chip(substream); |
4052 | struct snd_pcm_runtime *runtime = substream->runtime; | |
763f356c TI |
4053 | |
4054 | spin_lock_irq(&hdspm->lock); | |
4055 | snd_pcm_set_sync(substream); | |
4056 | runtime->hw = snd_hdspm_capture_subinfo; | |
4057 | ||
4058 | if (hdspm->playback_substream == NULL) | |
4059 | hdspm_stop_audio(hdspm); | |
4060 | ||
4061 | hdspm->capture_pid = current->pid; | |
4062 | hdspm->capture_substream = substream; | |
4063 | ||
4064 | spin_unlock_irq(&hdspm->lock); | |
4065 | ||
4066 | snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); | |
4067 | snd_pcm_hw_constraint_list(runtime, 0, | |
4068 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE, | |
4069 | &hw_constraints_period_sizes); | |
ffb2c3c0 RB |
4070 | if (hdspm->is_aes32) { |
4071 | snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, | |
4072 | &hdspm_hw_constraints_aes32_sample_rates); | |
4073 | } else { | |
4074 | snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, | |
4075 | snd_hdspm_hw_rule_channels, hdspm, | |
4076 | SNDRV_PCM_HW_PARAM_CHANNELS, -1); | |
4077 | snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, | |
4078 | snd_hdspm_hw_rule_channels_rate, hdspm, | |
4079 | SNDRV_PCM_HW_PARAM_RATE, -1); | |
4080 | ||
4081 | snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, | |
4082 | snd_hdspm_hw_rule_rate_channels, hdspm, | |
4083 | SNDRV_PCM_HW_PARAM_CHANNELS, -1); | |
4084 | } | |
763f356c TI |
4085 | return 0; |
4086 | } | |
4087 | ||
98274f07 | 4088 | static int snd_hdspm_capture_release(struct snd_pcm_substream *substream) |
763f356c | 4089 | { |
98274f07 | 4090 | struct hdspm *hdspm = snd_pcm_substream_chip(substream); |
763f356c TI |
4091 | |
4092 | spin_lock_irq(&hdspm->lock); | |
4093 | ||
4094 | hdspm->capture_pid = -1; | |
4095 | hdspm->capture_substream = NULL; | |
4096 | ||
4097 | spin_unlock_irq(&hdspm->lock); | |
4098 | return 0; | |
4099 | } | |
4100 | ||
98274f07 | 4101 | static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep * hw, struct file *file) |
763f356c TI |
4102 | { |
4103 | /* we have nothing to initialize but the call is required */ | |
4104 | return 0; | |
4105 | } | |
4106 | ||
4107 | ||
98274f07 | 4108 | static int snd_hdspm_hwdep_ioctl(struct snd_hwdep * hw, struct file *file, |
763f356c TI |
4109 | unsigned int cmd, unsigned long arg) |
4110 | { | |
ef5fa1a4 | 4111 | struct hdspm *hdspm = hw->private_data; |
98274f07 TI |
4112 | struct hdspm_mixer_ioctl mixer; |
4113 | struct hdspm_config_info info; | |
4114 | struct hdspm_version hdspm_version; | |
4115 | struct hdspm_peak_rms_ioctl rms; | |
763f356c TI |
4116 | |
4117 | switch (cmd) { | |
4118 | ||
763f356c TI |
4119 | case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS: |
4120 | if (copy_from_user(&rms, (void __user *)arg, sizeof(rms))) | |
4121 | return -EFAULT; | |
ef5fa1a4 TI |
4122 | /* maybe there is a chance to memorymap in future |
4123 | * so dont touch just copy | |
4124 | */ | |
763f356c TI |
4125 | if(copy_to_user_fromio((void __user *)rms.peak, |
4126 | hdspm->iobase+HDSPM_MADI_peakrmsbase, | |
98274f07 | 4127 | sizeof(struct hdspm_peak_rms)) != 0 ) |
763f356c TI |
4128 | return -EFAULT; |
4129 | ||
4130 | break; | |
4131 | ||
4132 | ||
4133 | case SNDRV_HDSPM_IOCTL_GET_CONFIG_INFO: | |
4134 | ||
4135 | spin_lock_irq(&hdspm->lock); | |
ef5fa1a4 TI |
4136 | info.pref_sync_ref = hdspm_pref_sync_ref(hdspm); |
4137 | info.wordclock_sync_check = hdspm_wc_sync_check(hdspm); | |
763f356c TI |
4138 | |
4139 | info.system_sample_rate = hdspm->system_sample_rate; | |
4140 | info.autosync_sample_rate = | |
4141 | hdspm_external_sample_rate(hdspm); | |
ef5fa1a4 TI |
4142 | info.system_clock_mode = hdspm_system_clock_mode(hdspm); |
4143 | info.clock_source = hdspm_clock_source(hdspm); | |
4144 | info.autosync_ref = hdspm_autosync_ref(hdspm); | |
4145 | info.line_out = hdspm_line_out(hdspm); | |
763f356c TI |
4146 | info.passthru = 0; |
4147 | spin_unlock_irq(&hdspm->lock); | |
4148 | if (copy_to_user((void __user *) arg, &info, sizeof(info))) | |
4149 | return -EFAULT; | |
4150 | break; | |
4151 | ||
4152 | case SNDRV_HDSPM_IOCTL_GET_VERSION: | |
4153 | hdspm_version.firmware_rev = hdspm->firmware_rev; | |
4154 | if (copy_to_user((void __user *) arg, &hdspm_version, | |
4155 | sizeof(hdspm_version))) | |
4156 | return -EFAULT; | |
4157 | break; | |
4158 | ||
4159 | case SNDRV_HDSPM_IOCTL_GET_MIXER: | |
4160 | if (copy_from_user(&mixer, (void __user *)arg, sizeof(mixer))) | |
4161 | return -EFAULT; | |
ef5fa1a4 TI |
4162 | if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer, |
4163 | sizeof(struct hdspm_mixer))) | |
763f356c TI |
4164 | return -EFAULT; |
4165 | break; | |
4166 | ||
4167 | default: | |
4168 | return -EINVAL; | |
4169 | } | |
4170 | return 0; | |
4171 | } | |
4172 | ||
98274f07 | 4173 | static struct snd_pcm_ops snd_hdspm_playback_ops = { |
763f356c TI |
4174 | .open = snd_hdspm_playback_open, |
4175 | .close = snd_hdspm_playback_release, | |
4176 | .ioctl = snd_hdspm_ioctl, | |
4177 | .hw_params = snd_hdspm_hw_params, | |
4178 | .hw_free = snd_hdspm_hw_free, | |
4179 | .prepare = snd_hdspm_prepare, | |
4180 | .trigger = snd_hdspm_trigger, | |
4181 | .pointer = snd_hdspm_hw_pointer, | |
4182 | .copy = snd_hdspm_playback_copy, | |
4183 | .silence = snd_hdspm_hw_silence, | |
4184 | .page = snd_pcm_sgbuf_ops_page, | |
4185 | }; | |
4186 | ||
98274f07 | 4187 | static struct snd_pcm_ops snd_hdspm_capture_ops = { |
763f356c TI |
4188 | .open = snd_hdspm_capture_open, |
4189 | .close = snd_hdspm_capture_release, | |
4190 | .ioctl = snd_hdspm_ioctl, | |
4191 | .hw_params = snd_hdspm_hw_params, | |
4192 | .hw_free = snd_hdspm_hw_free, | |
4193 | .prepare = snd_hdspm_prepare, | |
4194 | .trigger = snd_hdspm_trigger, | |
4195 | .pointer = snd_hdspm_hw_pointer, | |
4196 | .copy = snd_hdspm_capture_copy, | |
4197 | .page = snd_pcm_sgbuf_ops_page, | |
4198 | }; | |
4199 | ||
98274f07 TI |
4200 | static int __devinit snd_hdspm_create_hwdep(struct snd_card *card, |
4201 | struct hdspm * hdspm) | |
763f356c | 4202 | { |
98274f07 | 4203 | struct snd_hwdep *hw; |
763f356c TI |
4204 | int err; |
4205 | ||
ef5fa1a4 TI |
4206 | err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw); |
4207 | if (err < 0) | |
763f356c TI |
4208 | return err; |
4209 | ||
4210 | hdspm->hwdep = hw; | |
4211 | hw->private_data = hdspm; | |
4212 | strcpy(hw->name, "HDSPM hwdep interface"); | |
4213 | ||
4214 | hw->ops.open = snd_hdspm_hwdep_dummy_op; | |
4215 | hw->ops.ioctl = snd_hdspm_hwdep_ioctl; | |
4216 | hw->ops.release = snd_hdspm_hwdep_dummy_op; | |
4217 | ||
4218 | return 0; | |
4219 | } | |
4220 | ||
4221 | ||
4222 | /*------------------------------------------------------------ | |
4223 | memory interface | |
4224 | ------------------------------------------------------------*/ | |
98274f07 | 4225 | static int __devinit snd_hdspm_preallocate_memory(struct hdspm * hdspm) |
763f356c TI |
4226 | { |
4227 | int err; | |
98274f07 | 4228 | struct snd_pcm *pcm; |
763f356c TI |
4229 | size_t wanted; |
4230 | ||
4231 | pcm = hdspm->pcm; | |
4232 | ||
3cee5a60 | 4233 | wanted = HDSPM_DMA_AREA_BYTES; |
763f356c | 4234 | |
ef5fa1a4 | 4235 | err = |
763f356c TI |
4236 | snd_pcm_lib_preallocate_pages_for_all(pcm, |
4237 | SNDRV_DMA_TYPE_DEV_SG, | |
4238 | snd_dma_pci_data(hdspm->pci), | |
4239 | wanted, | |
ef5fa1a4 TI |
4240 | wanted); |
4241 | if (err < 0) { | |
e2eba3e7 | 4242 | snd_printdd("Could not preallocate %zd Bytes\n", wanted); |
763f356c TI |
4243 | |
4244 | return err; | |
4245 | } else | |
e2eba3e7 | 4246 | snd_printdd(" Preallocated %zd Bytes\n", wanted); |
763f356c TI |
4247 | |
4248 | return 0; | |
4249 | } | |
4250 | ||
98274f07 | 4251 | static void hdspm_set_sgbuf(struct hdspm * hdspm, struct snd_sg_buf *sgbuf, |
763f356c TI |
4252 | unsigned int reg, int channels) |
4253 | { | |
4254 | int i; | |
4255 | for (i = 0; i < (channels * 16); i++) | |
4256 | hdspm_write(hdspm, reg + 4 * i, | |
ef5fa1a4 | 4257 | snd_pcm_sgbuf_get_addr(sgbuf, (size_t) 4096 * i)); |
763f356c TI |
4258 | } |
4259 | ||
4260 | /* ------------- ALSA Devices ---------------------------- */ | |
98274f07 TI |
4261 | static int __devinit snd_hdspm_create_pcm(struct snd_card *card, |
4262 | struct hdspm * hdspm) | |
763f356c | 4263 | { |
98274f07 | 4264 | struct snd_pcm *pcm; |
763f356c TI |
4265 | int err; |
4266 | ||
ef5fa1a4 TI |
4267 | err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm); |
4268 | if (err < 0) | |
763f356c TI |
4269 | return err; |
4270 | ||
4271 | hdspm->pcm = pcm; | |
4272 | pcm->private_data = hdspm; | |
4273 | strcpy(pcm->name, hdspm->card_name); | |
4274 | ||
4275 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, | |
4276 | &snd_hdspm_playback_ops); | |
4277 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, | |
4278 | &snd_hdspm_capture_ops); | |
4279 | ||
4280 | pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; | |
4281 | ||
ef5fa1a4 TI |
4282 | err = snd_hdspm_preallocate_memory(hdspm); |
4283 | if (err < 0) | |
763f356c TI |
4284 | return err; |
4285 | ||
4286 | return 0; | |
4287 | } | |
4288 | ||
98274f07 | 4289 | static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm) |
763f356c TI |
4290 | { |
4291 | snd_hdspm_flush_midi_input(hdspm, 0); | |
4292 | snd_hdspm_flush_midi_input(hdspm, 1); | |
4293 | } | |
4294 | ||
98274f07 TI |
4295 | static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card, |
4296 | struct hdspm * hdspm) | |
763f356c TI |
4297 | { |
4298 | int err; | |
4299 | ||
4300 | snd_printdd("Create card...\n"); | |
ef5fa1a4 TI |
4301 | err = snd_hdspm_create_pcm(card, hdspm); |
4302 | if (err < 0) | |
763f356c TI |
4303 | return err; |
4304 | ||
ef5fa1a4 TI |
4305 | err = snd_hdspm_create_midi(card, hdspm, 0); |
4306 | if (err < 0) | |
763f356c TI |
4307 | return err; |
4308 | ||
ef5fa1a4 TI |
4309 | err = snd_hdspm_create_midi(card, hdspm, 1); |
4310 | if (err < 0) | |
763f356c TI |
4311 | return err; |
4312 | ||
ef5fa1a4 TI |
4313 | err = snd_hdspm_create_controls(card, hdspm); |
4314 | if (err < 0) | |
763f356c TI |
4315 | return err; |
4316 | ||
ef5fa1a4 TI |
4317 | err = snd_hdspm_create_hwdep(card, hdspm); |
4318 | if (err < 0) | |
763f356c TI |
4319 | return err; |
4320 | ||
4321 | snd_printdd("proc init...\n"); | |
4322 | snd_hdspm_proc_init(hdspm); | |
4323 | ||
4324 | hdspm->system_sample_rate = -1; | |
4325 | hdspm->last_external_sample_rate = -1; | |
4326 | hdspm->last_internal_sample_rate = -1; | |
4327 | hdspm->playback_pid = -1; | |
4328 | hdspm->capture_pid = -1; | |
4329 | hdspm->capture_substream = NULL; | |
4330 | hdspm->playback_substream = NULL; | |
4331 | ||
4332 | snd_printdd("Set defaults...\n"); | |
ef5fa1a4 TI |
4333 | err = snd_hdspm_set_defaults(hdspm); |
4334 | if (err < 0) | |
763f356c TI |
4335 | return err; |
4336 | ||
4337 | snd_printdd("Update mixer controls...\n"); | |
4338 | hdspm_update_simple_mixer_controls(hdspm); | |
4339 | ||
4340 | snd_printdd("Initializeing complete ???\n"); | |
4341 | ||
ef5fa1a4 TI |
4342 | err = snd_card_register(card); |
4343 | if (err < 0) { | |
763f356c TI |
4344 | snd_printk(KERN_ERR "HDSPM: error registering card\n"); |
4345 | return err; | |
4346 | } | |
4347 | ||
4348 | snd_printdd("... yes now\n"); | |
4349 | ||
4350 | return 0; | |
4351 | } | |
4352 | ||
ef5fa1a4 TI |
4353 | static int __devinit snd_hdspm_create(struct snd_card *card, |
4354 | struct hdspm *hdspm, | |
763f356c TI |
4355 | int precise_ptr, int enable_monitor) |
4356 | { | |
4357 | struct pci_dev *pci = hdspm->pci; | |
4358 | int err; | |
763f356c TI |
4359 | unsigned long io_extent; |
4360 | ||
4361 | hdspm->irq = -1; | |
ef5fa1a4 | 4362 | |
763f356c TI |
4363 | spin_lock_init(&hdspm->midi[0].lock); |
4364 | spin_lock_init(&hdspm->midi[1].lock); | |
763f356c TI |
4365 | |
4366 | hdspm->card = card; | |
4367 | ||
4368 | spin_lock_init(&hdspm->lock); | |
4369 | ||
4370 | tasklet_init(&hdspm->midi_tasklet, | |
4371 | hdspm_midi_tasklet, (unsigned long) hdspm); | |
4372 | ||
4373 | pci_read_config_word(hdspm->pci, | |
4374 | PCI_CLASS_REVISION, &hdspm->firmware_rev); | |
4375 | ||
3cee5a60 RB |
4376 | hdspm->is_aes32 = (hdspm->firmware_rev >= HDSPM_AESREVISION); |
4377 | ||
763f356c | 4378 | strcpy(card->mixername, "Xilinx FPGA"); |
3cee5a60 RB |
4379 | if (hdspm->is_aes32) { |
4380 | strcpy(card->driver, "HDSPAES32"); | |
4381 | hdspm->card_name = "RME HDSPM AES32"; | |
4382 | } else { | |
4383 | strcpy(card->driver, "HDSPM"); | |
4384 | hdspm->card_name = "RME HDSPM MADI"; | |
4385 | } | |
763f356c | 4386 | |
ef5fa1a4 TI |
4387 | err = pci_enable_device(pci); |
4388 | if (err < 0) | |
763f356c TI |
4389 | return err; |
4390 | ||
4391 | pci_set_master(hdspm->pci); | |
4392 | ||
ef5fa1a4 TI |
4393 | err = pci_request_regions(pci, "hdspm"); |
4394 | if (err < 0) | |
763f356c TI |
4395 | return err; |
4396 | ||
4397 | hdspm->port = pci_resource_start(pci, 0); | |
4398 | io_extent = pci_resource_len(pci, 0); | |
4399 | ||
4400 | snd_printdd("grabbed memory region 0x%lx-0x%lx\n", | |
4401 | hdspm->port, hdspm->port + io_extent - 1); | |
4402 | ||
4403 | ||
ef5fa1a4 TI |
4404 | hdspm->iobase = ioremap_nocache(hdspm->port, io_extent); |
4405 | if (!hdspm->iobase) { | |
4406 | snd_printk(KERN_ERR "HDSPM: " | |
4407 | "unable to remap region 0x%lx-0x%lx\n", | |
763f356c TI |
4408 | hdspm->port, hdspm->port + io_extent - 1); |
4409 | return -EBUSY; | |
4410 | } | |
4411 | snd_printdd("remapped region (0x%lx) 0x%lx-0x%lx\n", | |
4412 | (unsigned long)hdspm->iobase, hdspm->port, | |
4413 | hdspm->port + io_extent - 1); | |
4414 | ||
4415 | if (request_irq(pci->irq, snd_hdspm_interrupt, | |
437a5a46 | 4416 | IRQF_SHARED, "hdspm", hdspm)) { |
763f356c TI |
4417 | snd_printk(KERN_ERR "HDSPM: unable to use IRQ %d\n", pci->irq); |
4418 | return -EBUSY; | |
4419 | } | |
4420 | ||
4421 | snd_printdd("use IRQ %d\n", pci->irq); | |
4422 | ||
4423 | hdspm->irq = pci->irq; | |
4424 | hdspm->precise_ptr = precise_ptr; | |
4425 | ||
4426 | hdspm->monitor_outs = enable_monitor; | |
4427 | ||
e2eba3e7 | 4428 | snd_printdd("kmalloc Mixer memory of %zd Bytes\n", |
98274f07 | 4429 | sizeof(struct hdspm_mixer)); |
ef5fa1a4 TI |
4430 | hdspm->mixer = kzalloc(sizeof(struct hdspm_mixer), GFP_KERNEL); |
4431 | if (!hdspm->mixer) { | |
4432 | snd_printk(KERN_ERR "HDSPM: " | |
4433 | "unable to kmalloc Mixer memory of %d Bytes\n", | |
98274f07 | 4434 | (int)sizeof(struct hdspm_mixer)); |
763f356c TI |
4435 | return err; |
4436 | } | |
4437 | ||
4438 | hdspm->ss_channels = MADI_SS_CHANNELS; | |
4439 | hdspm->ds_channels = MADI_DS_CHANNELS; | |
4440 | hdspm->qs_channels = MADI_QS_CHANNELS; | |
4441 | ||
4442 | snd_printdd("create alsa devices.\n"); | |
ef5fa1a4 TI |
4443 | err = snd_hdspm_create_alsa_devices(card, hdspm); |
4444 | if (err < 0) | |
763f356c TI |
4445 | return err; |
4446 | ||
4447 | snd_hdspm_initialize_midi_flush(hdspm); | |
4448 | ||
4449 | return 0; | |
4450 | } | |
4451 | ||
98274f07 | 4452 | static int snd_hdspm_free(struct hdspm * hdspm) |
763f356c TI |
4453 | { |
4454 | ||
4455 | if (hdspm->port) { | |
4456 | ||
4457 | /* stop th audio, and cancel all interrupts */ | |
4458 | hdspm->control_register &= | |
ef5fa1a4 TI |
4459 | ~(HDSPM_Start | HDSPM_AudioInterruptEnable | |
4460 | HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable); | |
763f356c TI |
4461 | hdspm_write(hdspm, HDSPM_controlRegister, |
4462 | hdspm->control_register); | |
4463 | } | |
4464 | ||
4465 | if (hdspm->irq >= 0) | |
4466 | free_irq(hdspm->irq, (void *) hdspm); | |
4467 | ||
fc58422a | 4468 | kfree(hdspm->mixer); |
763f356c TI |
4469 | |
4470 | if (hdspm->iobase) | |
4471 | iounmap(hdspm->iobase); | |
4472 | ||
763f356c TI |
4473 | if (hdspm->port) |
4474 | pci_release_regions(hdspm->pci); | |
4475 | ||
4476 | pci_disable_device(hdspm->pci); | |
4477 | return 0; | |
4478 | } | |
4479 | ||
98274f07 | 4480 | static void snd_hdspm_card_free(struct snd_card *card) |
763f356c | 4481 | { |
ef5fa1a4 | 4482 | struct hdspm *hdspm = card->private_data; |
763f356c TI |
4483 | |
4484 | if (hdspm) | |
4485 | snd_hdspm_free(hdspm); | |
4486 | } | |
4487 | ||
4488 | static int __devinit snd_hdspm_probe(struct pci_dev *pci, | |
4489 | const struct pci_device_id *pci_id) | |
4490 | { | |
4491 | static int dev; | |
98274f07 TI |
4492 | struct hdspm *hdspm; |
4493 | struct snd_card *card; | |
763f356c TI |
4494 | int err; |
4495 | ||
4496 | if (dev >= SNDRV_CARDS) | |
4497 | return -ENODEV; | |
4498 | if (!enable[dev]) { | |
4499 | dev++; | |
4500 | return -ENOENT; | |
4501 | } | |
4502 | ||
ef5fa1a4 TI |
4503 | card = snd_card_new(index[dev], id[dev], |
4504 | THIS_MODULE, sizeof(struct hdspm)); | |
4505 | if (!card) | |
763f356c TI |
4506 | return -ENOMEM; |
4507 | ||
ef5fa1a4 | 4508 | hdspm = card->private_data; |
763f356c TI |
4509 | card->private_free = snd_hdspm_card_free; |
4510 | hdspm->dev = dev; | |
4511 | hdspm->pci = pci; | |
4512 | ||
c187c041 TI |
4513 | snd_card_set_dev(card, &pci->dev); |
4514 | ||
ef5fa1a4 TI |
4515 | err = snd_hdspm_create(card, hdspm, precise_ptr[dev], |
4516 | enable_monitor[dev]); | |
4517 | if (err < 0) { | |
763f356c TI |
4518 | snd_card_free(card); |
4519 | return err; | |
4520 | } | |
4521 | ||
4522 | strcpy(card->shortname, "HDSPM MADI"); | |
4523 | sprintf(card->longname, "%s at 0x%lx, irq %d", hdspm->card_name, | |
4524 | hdspm->port, hdspm->irq); | |
4525 | ||
ef5fa1a4 TI |
4526 | err = snd_card_register(card); |
4527 | if (err < 0) { | |
763f356c TI |
4528 | snd_card_free(card); |
4529 | return err; | |
4530 | } | |
4531 | ||
4532 | pci_set_drvdata(pci, card); | |
4533 | ||
4534 | dev++; | |
4535 | return 0; | |
4536 | } | |
4537 | ||
4538 | static void __devexit snd_hdspm_remove(struct pci_dev *pci) | |
4539 | { | |
4540 | snd_card_free(pci_get_drvdata(pci)); | |
4541 | pci_set_drvdata(pci, NULL); | |
4542 | } | |
4543 | ||
4544 | static struct pci_driver driver = { | |
4545 | .name = "RME Hammerfall DSP MADI", | |
4546 | .id_table = snd_hdspm_ids, | |
4547 | .probe = snd_hdspm_probe, | |
4548 | .remove = __devexit_p(snd_hdspm_remove), | |
4549 | }; | |
4550 | ||
4551 | ||
4552 | static int __init alsa_card_hdspm_init(void) | |
4553 | { | |
4554 | return pci_register_driver(&driver); | |
4555 | } | |
4556 | ||
4557 | static void __exit alsa_card_hdspm_exit(void) | |
4558 | { | |
4559 | pci_unregister_driver(&driver); | |
4560 | } | |
4561 | ||
4562 | module_init(alsa_card_hdspm_init) | |
4563 | module_exit(alsa_card_hdspm_exit) |