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ALSA: rme96: Adjust five checks for null pointers
[linux-block.git] / sound / pci / rme9652 / hdspm.c
CommitLineData
ef5fa1a4 1/*
763f356c
TI		 2 * ALSA driver for RME Hammerfall DSP MADI audio interface(s)
3 *
4 * Copyright (c) 2003 Winfried Ritsch (IEM)
5 * code based on hdsp.c Paul Davis
6 * Marcus Andersson
7 * Thomas Charbonnel
3cee5a60
RB		 8 * Modified 2006-06-01 for AES32 support by Remy Bruno
9 * <remy.bruno@trinnov.com>
763f356c 10 *
0dca1793
AK		 11 * Modified 2009-04-13 for proper metering by Florian Faber
12 * <faber@faberman.de>
13 *
14 * Modified 2009-04-14 for native float support by Florian Faber
15 * <faber@faberman.de>
16 *
17 * Modified 2009-04-26 fixed bug in rms metering by Florian Faber
18 * <faber@faberman.de>
19 *
20 * Modified 2009-04-30 added hw serial number support by Florian Faber
21 *
22 * Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth
23 *
24 * Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth
25 *
763f356c
TI		 26 * This program is free software; you can redistribute it and/or modify
27 * it under the terms of the GNU General Public License as published by
28 * the Free Software Foundation; either version 2 of the License, or
29 * (at your option) any later version.
30 *
31 * This program is distributed in the hope that it will be useful,
32 * but WITHOUT ANY WARRANTY; without even the implied warranty of
33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
34 * GNU General Public License for more details.
35 *
36 * You should have received a copy of the GNU General Public License
37 * along with this program; if not, write to the Free Software
38 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
39 *
40 */
69358fca
MD		 41
42/* ************* Register Documentation *******************************************************
43 *
44 * Work in progress! Documentation is based on the code in this file.
45 *
46 * --------- HDSPM_controlRegister ---------
47 * :7654.3210:7654.3210:7654.3210:7654.3210: bit number per byte
48 * :||||.||||:||||.||||:||||.||||:||||.||||:
49 * :3322.2222:2222.1111:1111.1100:0000.0000: bit number
50 * :1098.7654:3210.9876:5432.1098:7654.3210: 0..31
51 * :||||.||||:||||.||||:||||.||||:||||.||||:
52 * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit
53 * : . : . : . : x . : HDSPM_AudioInterruptEnable \_ setting both bits
54 * : . : . : . : . x: HDSPM_Start / enables audio IO
55 * : . : . : . : x. : HDSPM_ClockModeMaster - 1: Master, 0: Slave
56 * : . : . : . : .210 : HDSPM_LatencyMask - 3 Bit value for latency
57 * : . : . : . : . : 0:64, 1:128, 2:256, 3:512,
58 * : . : . : . : . : 4:1024, 5:2048, 6:4096, 7:8192
59 * :x . : . : . x:xx . : HDSPM_FrequencyMask
60 * : . : . : . :10 . : HDSPM_Frequency1|HDSPM_Frequency0: 1=32K,2=44.1K,3=48K,0=??
61 * : . : . : . x: . : <MADI> HDSPM_DoubleSpeed
62 * :x . : . : . : . : <MADI> HDSPM_QuadSpeed
63 * : . 3 : . 10: 2 . : . : HDSPM_SyncRefMask :
64 * : . : . x: . : . : HDSPM_SyncRef0
65 * : . : . x : . : . : HDSPM_SyncRef1
66 * : . : . : x . : . : <AES32> HDSPM_SyncRef2
67 * : . x : . : . : . : <AES32> HDSPM_SyncRef3
68 * : . : . 10: . : . : <MADI> sync ref: 0:WC, 1:Madi, 2:TCO, 3:SyncIn
69 * : . 3 : . 10: 2 . : . : <AES32> 0:WC, 1:AES1 ... 8:AES8, 9: TCO, 10:SyncIn?
70 * : . x : . : . : . : <MADIe> HDSPe_FLOAT_FORMAT
71 * : . : . : x . : . : <MADI> HDSPM_InputSelect0 : 0=optical,1=coax
72 * : . : . :x . : . : <MADI> HDSPM_InputSelect1
73 * : . : .x : . : . : <MADI> HDSPM_clr_tms
74 * : . : . : . x : . : <MADI> HDSPM_TX_64ch
75 * : . : . : . x : . : <AES32> HDSPM_Emphasis
76 * : . : . : .x : . : <MADI> HDSPM_AutoInp
77 * : . : . x : . : . : <MADI> HDSPM_SMUX
78 * : . : .x : . : . : <MADI> HDSPM_clr_tms
79 * : . : x. : . : . : <MADI> HDSPM_taxi_reset
80 * : . x: . : . : . : <MADI> HDSPM_LineOut
81 * : . x: . : . : . : <AES32> ??????????????????
82 * : . : x. : . : . : <AES32> HDSPM_WCK48
83 * : . : . : .x : . : <AES32> HDSPM_Dolby
84 * : . : x . : . : . : HDSPM_Midi0InterruptEnable
85 * : . :x . : . : . : HDSPM_Midi1InterruptEnable
86 * : . : x . : . : . : HDSPM_Midi2InterruptEnable
87 * : . x : . : . : . : <MADI> HDSPM_Midi3InterruptEnable
88 * : . x : . : . : . : <AES32> HDSPM_DS_DoubleWire
89 * : .x : . : . : . : <AES32> HDSPM_QS_DoubleWire
90 * : x. : . : . : . : <AES32> HDSPM_QS_QuadWire
91 * : . : . : . x : . : <AES32> HDSPM_Professional
92 * : x . : . : . : . : HDSPM_wclk_sel
93 * : . : . : . : . :
94 * :7654.3210:7654.3210:7654.3210:7654.3210: bit number per byte
95 * :||||.||||:||||.||||:||||.||||:||||.||||:
96 * :3322.2222:2222.1111:1111.1100:0000.0000: bit number
97 * :1098.7654:3210.9876:5432.1098:7654.3210: 0..31
98 * :||||.||||:||||.||||:||||.||||:||||.||||:
99 * :8421.8421:8421.8421:8421.8421:8421.8421:hex digit
100 *
101 *
102 *
103 * AIO / RayDAT only
104 *
105 * ------------ HDSPM_WR_SETTINGS ----------
106 * :3322.2222:2222.1111:1111.1100:0000.0000: bit number per byte
107 * :1098.7654:3210.9876:5432.1098:7654.3210:
108 * :||||.||||:||||.||||:||||.||||:||||.||||: bit number
109 * :7654.3210:7654.3210:7654.3210:7654.3210: 0..31
110 * :||||.||||:||||.||||:||||.||||:||||.||||:
111 * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit
112 * : . : . : . : . x: HDSPM_c0Master 1: Master, 0: Slave
113 * : . : . : . : . x : HDSPM_c0_SyncRef0
114 * : . : . : . : . x : HDSPM_c0_SyncRef1
115 * : . : . : . : .x : HDSPM_c0_SyncRef2
116 * : . : . : . : x. : HDSPM_c0_SyncRef3
117 * : . : . : . : 3.210 : HDSPM_c0_SyncRefMask:
118 * : . : . : . : . : RayDat: 0:WC, 1:AES, 2:SPDIF, 3..6: ADAT1..4,
119 * : . : . : . : . : 9:TCO, 10:SyncIn
120 * : . : . : . : . : AIO: 0:WC, 1:AES, 2: SPDIF, 3: ATAT,
121 * : . : . : . : . : 9:TCO, 10:SyncIn
122 * : . : . : . : . :
123 * : . : . : . : . :
124 * :3322.2222:2222.1111:1111.1100:0000.0000: bit number per byte
125 * :1098.7654:3210.9876:5432.1098:7654.3210:
126 * :||||.||||:||||.||||:||||.||||:||||.||||: bit number
127 * :7654.3210:7654.3210:7654.3210:7654.3210: 0..31
128 * :||||.||||:||||.||||:||||.||||:||||.||||:
129 * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit
130 *
131 */
763f356c
TI		 132#include <linux/init.h>
133#include <linux/delay.h>
134#include <linux/interrupt.h>
65a77217 135#include <linux/module.h>
763f356c
TI		 136#include <linux/slab.h>
137#include <linux/pci.h>
3f7440a6 138#include <linux/math64.h>
6cbbfe1c 139#include <linux/io.h>
763f356c
TI		 140
141#include <sound/core.h>
142#include <sound/control.h>
143#include <sound/pcm.h>
0dca1793 144#include <sound/pcm_params.h>
763f356c
TI		 145#include <sound/info.h>
146#include <sound/asoundef.h>
147#include <sound/rawmidi.h>
148#include <sound/hwdep.h>
149#include <sound/initval.h>
150
151#include <sound/hdspm.h>
152
153static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
154static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
a67ff6a5 155static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
763f356c 156
763f356c
TI		 157module_param_array(index, int, NULL, 0444);
158MODULE_PARM_DESC(index, "Index value for RME HDSPM interface.");
159
160module_param_array(id, charp, NULL, 0444);
161MODULE_PARM_DESC(id, "ID string for RME HDSPM interface.");
162
163module_param_array(enable, bool, NULL, 0444);
164MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards.");
165
763f356c
TI		 166
167MODULE_AUTHOR
0dca1793
AK		 168(
169 "Winfried Ritsch <ritsch_AT_iem.at>, "
170 "Paul Davis <paul@linuxaudiosystems.com>, "
171 "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, "
172 "Remy Bruno <remy.bruno@trinnov.com>, "
173 "Florian Faber <faberman@linuxproaudio.org>, "
174 "Adrian Knoth <adi@drcomp.erfurt.thur.de>"
175);
763f356c
TI		 176MODULE_DESCRIPTION("RME HDSPM");
177MODULE_LICENSE("GPL");
178MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}");
179
0dca1793 180/* --- Write registers. ---
763f356c
TI		 181 These are defined as byte-offsets from the iobase value. */
182
0dca1793
AK		 183#define HDSPM_WR_SETTINGS 0
184#define HDSPM_outputBufferAddress 32
185#define HDSPM_inputBufferAddress 36
763f356c
TI		 186#define HDSPM_controlRegister 64
187#define HDSPM_interruptConfirmation 96
188#define HDSPM_control2Reg 256 /* not in specs ???????? */
69358fca 189#define HDSPM_freqReg 256 /* for setting arbitrary clock values (DDS feature) */
0dca1793
AK		 190#define HDSPM_midiDataOut0 352 /* just believe in old code */
191#define HDSPM_midiDataOut1 356
ffb2c3c0 192#define HDSPM_eeprom_wr 384 /* for AES32 */
763f356c
TI		 193
194/* DMA enable for 64 channels, only Bit 0 is relevant */
0dca1793 195#define HDSPM_outputEnableBase 512 /* 512-767 input DMA */
763f356c
TI		 196#define HDSPM_inputEnableBase 768 /* 768-1023 output DMA */
197
0dca1793 198/* 16 page addresses for each of the 64 channels DMA buffer in and out
763f356c
TI		 199 (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */
200#define HDSPM_pageAddressBufferOut 8192
201#define HDSPM_pageAddressBufferIn (HDSPM_pageAddressBufferOut+64*16*4)
202
203#define HDSPM_MADI_mixerBase 32768 /* 32768-65535 for 2x64x64 Fader */
204
205#define HDSPM_MATRIX_MIXER_SIZE 8192 /* = 2*64*64 * 4 Byte => 32kB */
206
207/* --- Read registers. ---
208 These are defined as byte-offsets from the iobase value */
209#define HDSPM_statusRegister 0
3cee5a60
RB		 210/*#define HDSPM_statusRegister2 96 */
211/* after RME Windows driver sources, status2 is 4-byte word # 48 = word at
212 * offset 192, for AES32 *and* MADI
213 * => need to check that offset 192 is working on MADI */
214#define HDSPM_statusRegister2 192
215#define HDSPM_timecodeRegister 128
763f356c 216
0dca1793
AK		 217/* AIO, RayDAT */
218#define HDSPM_RD_STATUS_0 0
219#define HDSPM_RD_STATUS_1 64
220#define HDSPM_RD_STATUS_2 128
221#define HDSPM_RD_STATUS_3 192
222
223#define HDSPM_RD_TCO 256
224#define HDSPM_RD_PLL_FREQ 512
225#define HDSPM_WR_TCO 128
226
227#define HDSPM_TCO1_TCO_lock 0x00000001
228#define HDSPM_TCO1_WCK_Input_Range_LSB 0x00000002
229#define HDSPM_TCO1_WCK_Input_Range_MSB 0x00000004
230#define HDSPM_TCO1_LTC_Input_valid 0x00000008
231#define HDSPM_TCO1_WCK_Input_valid 0x00000010
232#define HDSPM_TCO1_Video_Input_Format_NTSC 0x00000020
233#define HDSPM_TCO1_Video_Input_Format_PAL 0x00000040
234
235#define HDSPM_TCO1_set_TC 0x00000100
236#define HDSPM_TCO1_set_drop_frame_flag 0x00000200
237#define HDSPM_TCO1_LTC_Format_LSB 0x00000400
238#define HDSPM_TCO1_LTC_Format_MSB 0x00000800
239
240#define HDSPM_TCO2_TC_run 0x00010000
241#define HDSPM_TCO2_WCK_IO_ratio_LSB 0x00020000
242#define HDSPM_TCO2_WCK_IO_ratio_MSB 0x00040000
243#define HDSPM_TCO2_set_num_drop_frames_LSB 0x00080000
244#define HDSPM_TCO2_set_num_drop_frames_MSB 0x00100000
245#define HDSPM_TCO2_set_jam_sync 0x00200000
246#define HDSPM_TCO2_set_flywheel 0x00400000
247
248#define HDSPM_TCO2_set_01_4 0x01000000
249#define HDSPM_TCO2_set_pull_down 0x02000000
250#define HDSPM_TCO2_set_pull_up 0x04000000
251#define HDSPM_TCO2_set_freq 0x08000000
252#define HDSPM_TCO2_set_term_75R 0x10000000
253#define HDSPM_TCO2_set_input_LSB 0x20000000
254#define HDSPM_TCO2_set_input_MSB 0x40000000
255#define HDSPM_TCO2_set_freq_from_app 0x80000000
256
257
258#define HDSPM_midiDataOut0 352
259#define HDSPM_midiDataOut1 356
260#define HDSPM_midiDataOut2 368
261
763f356c
TI		 262#define HDSPM_midiDataIn0 360
263#define HDSPM_midiDataIn1 364
0dca1793
AK		 264#define HDSPM_midiDataIn2 372
265#define HDSPM_midiDataIn3 376
763f356c
TI		 266
267/* status is data bytes in MIDI-FIFO (0-128) */
0dca1793
AK		 268#define HDSPM_midiStatusOut0 384
269#define HDSPM_midiStatusOut1 388
270#define HDSPM_midiStatusOut2 400
271
272#define HDSPM_midiStatusIn0 392
273#define HDSPM_midiStatusIn1 396
274#define HDSPM_midiStatusIn2 404
275#define HDSPM_midiStatusIn3 408
763f356c
TI		 276
277
278/* the meters are regular i/o-mapped registers, but offset
279 considerably from the rest. the peak registers are reset
0dca1793 280 when read; the least-significant 4 bits are full-scale counters;
763f356c
TI		 281 the actual peak value is in the most-significant 24 bits.
282*/
0dca1793
AK		 283
284#define HDSPM_MADI_INPUT_PEAK 4096
285#define HDSPM_MADI_PLAYBACK_PEAK 4352
286#define HDSPM_MADI_OUTPUT_PEAK 4608
287
288#define HDSPM_MADI_INPUT_RMS_L 6144
289#define HDSPM_MADI_PLAYBACK_RMS_L 6400
290#define HDSPM_MADI_OUTPUT_RMS_L 6656
291
292#define HDSPM_MADI_INPUT_RMS_H 7168
293#define HDSPM_MADI_PLAYBACK_RMS_H 7424
294#define HDSPM_MADI_OUTPUT_RMS_H 7680
763f356c
TI		 295
296/* --- Control Register bits --------- */
297#define HDSPM_Start (1<<0) /* start engine */
298
299#define HDSPM_Latency0 (1<<1) /* buffer size = 2^n */
300#define HDSPM_Latency1 (1<<2) /* where n is defined */
301#define HDSPM_Latency2 (1<<3) /* by Latency{2,1,0} */
302
0dca1793
AK		 303#define HDSPM_ClockModeMaster (1<<4) /* 1=Master, 0=Autosync */
304#define HDSPM_c0Master 0x1 /* Master clock bit in settings
305 register [RayDAT, AIO] */
763f356c
TI		 306
307#define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */
308
309#define HDSPM_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */
310#define HDSPM_Frequency1 (1<<7) /* 0=32kHz/64kHz */
311#define HDSPM_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */
3cee5a60 312#define HDSPM_QuadSpeed (1<<31) /* quad speed bit */
763f356c 313
3cee5a60 314#define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */
763f356c 315#define HDSPM_TX_64ch (1<<10) /* Output 64channel MODE=1,
3cee5a60
RB		 316 56channelMODE=0 */ /* MADI ONLY*/
317#define HDSPM_Emphasis (1<<10) /* Emphasis */ /* AES32 ONLY */
763f356c 318
0dca1793 319#define HDSPM_AutoInp (1<<11) /* Auto Input (takeover) == Safe Mode,
3cee5a60
RB		 320 0=off, 1=on */ /* MADI ONLY */
321#define HDSPM_Dolby (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */
763f356c 322
ef5fa1a4
TI		 323#define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax
324 * -- MADI ONLY
325 */
763f356c
TI		 326#define HDSPM_InputSelect1 (1<<15) /* should be 0 */
327
3cee5a60
RB		 328#define HDSPM_SyncRef2 (1<<13)
329#define HDSPM_SyncRef3 (1<<25)
763f356c 330
3cee5a60 331#define HDSPM_SMUX (1<<18) /* Frame ??? */ /* MADI ONY */
0dca1793 332#define HDSPM_clr_tms (1<<19) /* clear track marker, do not use
763f356c
TI		 333 AES additional bits in
334 lower 5 Audiodatabits ??? */
3cee5a60
RB		 335#define HDSPM_taxi_reset (1<<20) /* ??? */ /* MADI ONLY ? */
336#define HDSPM_WCK48 (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */
763f356c 337
0dca1793
AK		 338#define HDSPM_Midi0InterruptEnable 0x0400000
339#define HDSPM_Midi1InterruptEnable 0x0800000
340#define HDSPM_Midi2InterruptEnable 0x0200000
341#define HDSPM_Midi3InterruptEnable 0x4000000
763f356c
TI		 342
343#define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */
0dca1793 344#define HDSPe_FLOAT_FORMAT 0x2000000
763f356c 345
3cee5a60
RB		 346#define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */
347#define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */
348#define HDSPM_QS_QuadWire (1<<28) /* AES32 ONLY */
349
350#define HDSPM_wclk_sel (1<<30)
763f356c 351
384f778f
AK		 352/* additional control register bits for AIO*/
353#define HDSPM_c0_Wck48 0x20 /* also RayDAT */
354#define HDSPM_c0_Input0 0x1000
355#define HDSPM_c0_Input1 0x2000
356#define HDSPM_c0_Spdif_Opt 0x4000
357#define HDSPM_c0_Pro 0x8000
358#define HDSPM_c0_clr_tms 0x10000
359#define HDSPM_c0_AEB1 0x20000
360#define HDSPM_c0_AEB2 0x40000
361#define HDSPM_c0_LineOut 0x80000
362#define HDSPM_c0_AD_GAIN0 0x100000
363#define HDSPM_c0_AD_GAIN1 0x200000
364#define HDSPM_c0_DA_GAIN0 0x400000
365#define HDSPM_c0_DA_GAIN1 0x800000
366#define HDSPM_c0_PH_GAIN0 0x1000000
367#define HDSPM_c0_PH_GAIN1 0x2000000
368#define HDSPM_c0_Sym6db 0x4000000
369
370
763f356c
TI		 371/* --- bit helper defines */
372#define HDSPM_LatencyMask (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2)
ef5fa1a4
TI		 373#define HDSPM_FrequencyMask (HDSPM_Frequency0|HDSPM_Frequency1|\
374 HDSPM_DoubleSpeed|HDSPM_QuadSpeed)
763f356c
TI		 375#define HDSPM_InputMask (HDSPM_InputSelect0|HDSPM_InputSelect1)
376#define HDSPM_InputOptical 0
377#define HDSPM_InputCoaxial (HDSPM_InputSelect0)
ef5fa1a4
TI		 378#define HDSPM_SyncRefMask (HDSPM_SyncRef0|HDSPM_SyncRef1|\
379 HDSPM_SyncRef2|HDSPM_SyncRef3)
763f356c 380
0dca1793
AK		 381#define HDSPM_c0_SyncRef0 0x2
382#define HDSPM_c0_SyncRef1 0x4
383#define HDSPM_c0_SyncRef2 0x8
384#define HDSPM_c0_SyncRef3 0x10
385#define HDSPM_c0_SyncRefMask (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\
386 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3)
387
388#define HDSPM_SYNC_FROM_WORD 0 /* Preferred sync reference */
389#define HDSPM_SYNC_FROM_MADI 1 /* choices - used by "pref_sync_ref" */
390#define HDSPM_SYNC_FROM_TCO 2
391#define HDSPM_SYNC_FROM_SYNC_IN 3
763f356c
TI		 392
393#define HDSPM_Frequency32KHz HDSPM_Frequency0
394#define HDSPM_Frequency44_1KHz HDSPM_Frequency1
395#define HDSPM_Frequency48KHz (HDSPM_Frequency1|HDSPM_Frequency0)
396#define HDSPM_Frequency64KHz (HDSPM_DoubleSpeed|HDSPM_Frequency0)
397#define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1)
ef5fa1a4
TI		 398#define HDSPM_Frequency96KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1|\
399 HDSPM_Frequency0)
3cee5a60
RB		 400#define HDSPM_Frequency128KHz (HDSPM_QuadSpeed|HDSPM_Frequency0)
401#define HDSPM_Frequency176_4KHz (HDSPM_QuadSpeed|HDSPM_Frequency1)
ef5fa1a4
TI		 402#define HDSPM_Frequency192KHz (HDSPM_QuadSpeed|HDSPM_Frequency1|\
403 HDSPM_Frequency0)
763f356c 404
763f356c
TI		 405
406/* Synccheck Status */
407#define HDSPM_SYNC_CHECK_NO_LOCK 0
408#define HDSPM_SYNC_CHECK_LOCK 1
409#define HDSPM_SYNC_CHECK_SYNC 2
410
411/* AutoSync References - used by "autosync_ref" control switch */
412#define HDSPM_AUTOSYNC_FROM_WORD 0
413#define HDSPM_AUTOSYNC_FROM_MADI 1
0dca1793
AK		 414#define HDSPM_AUTOSYNC_FROM_TCO 2
415#define HDSPM_AUTOSYNC_FROM_SYNC_IN 3
416#define HDSPM_AUTOSYNC_FROM_NONE 4
763f356c
TI		 417
418/* Possible sources of MADI input */
419#define HDSPM_OPTICAL 0 /* optical */
420#define HDSPM_COAXIAL 1 /* BNC */
421
422#define hdspm_encode_latency(x) (((x)<<1) & HDSPM_LatencyMask)
0dca1793 423#define hdspm_decode_latency(x) ((((x) & HDSPM_LatencyMask)>>1))
763f356c
TI		 424
425#define hdspm_encode_in(x) (((x)&0x3)<<14)
426#define hdspm_decode_in(x) (((x)>>14)&0x3)
427
428/* --- control2 register bits --- */
429#define HDSPM_TMS (1<<0)
430#define HDSPM_TCK (1<<1)
431#define HDSPM_TDI (1<<2)
432#define HDSPM_JTAG (1<<3)
433#define HDSPM_PWDN (1<<4)
434#define HDSPM_PROGRAM (1<<5)
435#define HDSPM_CONFIG_MODE_0 (1<<6)
436#define HDSPM_CONFIG_MODE_1 (1<<7)
437/*#define HDSPM_VERSION_BIT (1<<8) not defined any more*/
438#define HDSPM_BIGENDIAN_MODE (1<<9)
439#define HDSPM_RD_MULTIPLE (1<<10)
440
3cee5a60 441/* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and
ef5fa1a4
TI		 442 that do not conflict with specific bits for AES32 seem to be valid also
443 for the AES32
444 */
763f356c 445#define HDSPM_audioIRQPending (1<<0) /* IRQ is high and pending */
ef5fa1a4
TI		 446#define HDSPM_RX_64ch (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */
447#define HDSPM_AB_int (1<<2) /* InputChannel Opt=0, Coax=1
448 * (like inp0)
449 */
0dca1793 450
763f356c 451#define HDSPM_madiLock (1<<3) /* MADI Locked =1, no=0 */
0dca1793
AK		 452#define HDSPM_madiSync (1<<18) /* MADI is in sync */
453
b0bf5504
AK		 454#define HDSPM_tcoLockMadi 0x00000020 /* Optional TCO locked status for HDSPe MADI*/
455#define HDSPM_tcoSync 0x10000000 /* Optional TCO sync status for HDSPe MADI and AES32!*/
0dca1793 456
b0bf5504
AK		 457#define HDSPM_syncInLock 0x00010000 /* Sync In lock status for HDSPe MADI! */
458#define HDSPM_syncInSync 0x00020000 /* Sync In sync status for HDSPe MADI! */
763f356c
TI		 459
460#define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
0dca1793
AK		 461 /* since 64byte accurate, last 6 bits are not used */
462
463
763f356c 464
763f356c
TI		 465#define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */
466
467#define HDSPM_madiFreq0 (1<<22) /* system freq 0=error */
468#define HDSPM_madiFreq1 (1<<23) /* 1=32, 2=44.1 3=48 */
469#define HDSPM_madiFreq2 (1<<24) /* 4=64, 5=88.2 6=96 */
470#define HDSPM_madiFreq3 (1<<25) /* 7=128, 8=176.4 9=192 */
471
ef5fa1a4
TI		 472#define HDSPM_BufferID (1<<26) /* (Double)Buffer ID toggles with
473 * Interrupt
474 */
0dca1793 475#define HDSPM_tco_detect 0x08000000
b0bf5504 476#define HDSPM_tcoLockAes 0x20000000 /* Optional TCO locked status for HDSPe AES */
0dca1793
AK		 477
478#define HDSPM_s2_tco_detect 0x00000040
479#define HDSPM_s2_AEBO_D 0x00000080
480#define HDSPM_s2_AEBI_D 0x00000100
481
482
483#define HDSPM_midi0IRQPending 0x40000000
484#define HDSPM_midi1IRQPending 0x80000000
485#define HDSPM_midi2IRQPending 0x20000000
486#define HDSPM_midi2IRQPendingAES 0x00000020
487#define HDSPM_midi3IRQPending 0x00200000
763f356c
TI		 488
489/* --- status bit helpers */
ef5fa1a4
TI		 490#define HDSPM_madiFreqMask (HDSPM_madiFreq0|HDSPM_madiFreq1|\
491 HDSPM_madiFreq2|HDSPM_madiFreq3)
763f356c
TI		 492#define HDSPM_madiFreq32 (HDSPM_madiFreq0)
493#define HDSPM_madiFreq44_1 (HDSPM_madiFreq1)
494#define HDSPM_madiFreq48 (HDSPM_madiFreq0|HDSPM_madiFreq1)
495#define HDSPM_madiFreq64 (HDSPM_madiFreq2)
496#define HDSPM_madiFreq88_2 (HDSPM_madiFreq0|HDSPM_madiFreq2)
497#define HDSPM_madiFreq96 (HDSPM_madiFreq1|HDSPM_madiFreq2)
498#define HDSPM_madiFreq128 (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2)
499#define HDSPM_madiFreq176_4 (HDSPM_madiFreq3)
500#define HDSPM_madiFreq192 (HDSPM_madiFreq3|HDSPM_madiFreq0)
501
3cee5a60 502/* Status2 Register bits */ /* MADI ONLY */
763f356c 503
25985edc 504#define HDSPM_version0 (1<<0) /* not really defined but I guess */
763f356c
TI		 505#define HDSPM_version1 (1<<1) /* in former cards it was ??? */
506#define HDSPM_version2 (1<<2)
507
508#define HDSPM_wcLock (1<<3) /* Wordclock is detected and locked */
509#define HDSPM_wcSync (1<<4) /* Wordclock is in sync with systemclock */
510
511#define HDSPM_wc_freq0 (1<<5) /* input freq detected via autosync */
512#define HDSPM_wc_freq1 (1<<6) /* 001=32, 010==44.1, 011=48, */
a8cd7148
AK		 513#define HDSPM_wc_freq2 (1<<7) /* 100=64, 101=88.2, 110=96, 111=128 */
514#define HDSPM_wc_freq3 0x800 /* 1000=176.4, 1001=192 */
763f356c 515
0dca1793
AK		 516#define HDSPM_SyncRef0 0x10000 /* Sync Reference */
517#define HDSPM_SyncRef1 0x20000
518
519#define HDSPM_SelSyncRef0 (1<<8) /* AutoSync Source */
763f356c
TI		 520#define HDSPM_SelSyncRef1 (1<<9) /* 000=word, 001=MADI, */
521#define HDSPM_SelSyncRef2 (1<<10) /* 111=no valid signal */
522
523#define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync)
524
a8cd7148
AK		 525#define HDSPM_wcFreqMask (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2|\
526 HDSPM_wc_freq3)
763f356c
TI		 527#define HDSPM_wcFreq32 (HDSPM_wc_freq0)
528#define HDSPM_wcFreq44_1 (HDSPM_wc_freq1)
529#define HDSPM_wcFreq48 (HDSPM_wc_freq0|HDSPM_wc_freq1)
530#define HDSPM_wcFreq64 (HDSPM_wc_freq2)
531#define HDSPM_wcFreq88_2 (HDSPM_wc_freq0|HDSPM_wc_freq2)
532#define HDSPM_wcFreq96 (HDSPM_wc_freq1|HDSPM_wc_freq2)
a8cd7148
AK		 533#define HDSPM_wcFreq128 (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2)
534#define HDSPM_wcFreq176_4 (HDSPM_wc_freq3)
535#define HDSPM_wcFreq192 (HDSPM_wc_freq0|HDSPM_wc_freq3)
763f356c 536
0dca1793
AK		 537#define HDSPM_status1_F_0 0x0400000
538#define HDSPM_status1_F_1 0x0800000
539#define HDSPM_status1_F_2 0x1000000
540#define HDSPM_status1_F_3 0x2000000
541#define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3)
542
763f356c 543
ef5fa1a4
TI		 544#define HDSPM_SelSyncRefMask (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
545 HDSPM_SelSyncRef2)
763f356c
TI		 546#define HDSPM_SelSyncRef_WORD 0
547#define HDSPM_SelSyncRef_MADI (HDSPM_SelSyncRef0)
0dca1793
AK		 548#define HDSPM_SelSyncRef_TCO (HDSPM_SelSyncRef1)
549#define HDSPM_SelSyncRef_SyncIn (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1)
ef5fa1a4
TI		 550#define HDSPM_SelSyncRef_NVALID (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
551 HDSPM_SelSyncRef2)
763f356c 552
3cee5a60
RB		 553/*
554 For AES32, bits for status, status2 and timecode are different
555*/
556/* status */
557#define HDSPM_AES32_wcLock 0x0200000
56bde0f3 558#define HDSPM_AES32_wcSync 0x0100000
3cee5a60 559#define HDSPM_AES32_wcFreq_bit 22
0dca1793 560/* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function
3cee5a60
RB		 561 HDSPM_bit2freq */
562#define HDSPM_AES32_syncref_bit 16
563/* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */
564
565#define HDSPM_AES32_AUTOSYNC_FROM_WORD 0
566#define HDSPM_AES32_AUTOSYNC_FROM_AES1 1
567#define HDSPM_AES32_AUTOSYNC_FROM_AES2 2
568#define HDSPM_AES32_AUTOSYNC_FROM_AES3 3
569#define HDSPM_AES32_AUTOSYNC_FROM_AES4 4
570#define HDSPM_AES32_AUTOSYNC_FROM_AES5 5
571#define HDSPM_AES32_AUTOSYNC_FROM_AES6 6
572#define HDSPM_AES32_AUTOSYNC_FROM_AES7 7
573#define HDSPM_AES32_AUTOSYNC_FROM_AES8 8
b0bf5504
AK		 574#define HDSPM_AES32_AUTOSYNC_FROM_TCO 9
575#define HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN 10
576#define HDSPM_AES32_AUTOSYNC_FROM_NONE 11
3cee5a60
RB		 577
578/* status2 */
579/* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */
580#define HDSPM_LockAES 0x80
581#define HDSPM_LockAES1 0x80
582#define HDSPM_LockAES2 0x40
583#define HDSPM_LockAES3 0x20
584#define HDSPM_LockAES4 0x10
585#define HDSPM_LockAES5 0x8
586#define HDSPM_LockAES6 0x4
587#define HDSPM_LockAES7 0x2
588#define HDSPM_LockAES8 0x1
589/*
590 Timecode
591 After windows driver sources, bits 4*i to 4*i+3 give the input frequency on
592 AES i+1
593 bits 3210
594 0001 32kHz
595 0010 44.1kHz
596 0011 48kHz
597 0100 64kHz
598 0101 88.2kHz
599 0110 96kHz
600 0111 128kHz
601 1000 176.4kHz
602 1001 192kHz
603 NB: Timecode register doesn't seem to work on AES32 card revision 230
604*/
605
763f356c
TI		 606/* Mixer Values */
607#define UNITY_GAIN 32768 /* = 65536/2 */
608#define MINUS_INFINITY_GAIN 0
609
763f356c
TI		 610/* Number of channels for different Speed Modes */
611#define MADI_SS_CHANNELS 64
612#define MADI_DS_CHANNELS 32
613#define MADI_QS_CHANNELS 16
614
0dca1793
AK		 615#define RAYDAT_SS_CHANNELS 36
616#define RAYDAT_DS_CHANNELS 20
617#define RAYDAT_QS_CHANNELS 12
618
619#define AIO_IN_SS_CHANNELS 14
620#define AIO_IN_DS_CHANNELS 10
621#define AIO_IN_QS_CHANNELS 8
622#define AIO_OUT_SS_CHANNELS 16
623#define AIO_OUT_DS_CHANNELS 12
624#define AIO_OUT_QS_CHANNELS 10
625
d2d10a21
AK		 626#define AES32_CHANNELS 16
627
763f356c
TI		 628/* the size of a substream (1 mono data stream) */
629#define HDSPM_CHANNEL_BUFFER_SAMPLES (16*1024)
630#define HDSPM_CHANNEL_BUFFER_BYTES (4*HDSPM_CHANNEL_BUFFER_SAMPLES)
631
632/* the size of the area we need to allocate for DMA transfers. the
633 size is the same regardless of the number of channels, and
0dca1793 634 also the latency to use.
763f356c
TI		 635 for one direction !!!
636*/
ffb2c3c0 637#define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES)
763f356c
TI		 638#define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024)
639
0dca1793
AK		 640#define HDSPM_RAYDAT_REV 211
641#define HDSPM_AIO_REV 212
642#define HDSPM_MADIFACE_REV 213
3cee5a60 643
6534599d
RB		 644/* speed factor modes */
645#define HDSPM_SPEED_SINGLE 0
646#define HDSPM_SPEED_DOUBLE 1
647#define HDSPM_SPEED_QUAD 2
0dca1793 648
6534599d
RB		 649/* names for speed modes */
650static char *hdspm_speed_names[] = { "single", "double", "quad" };
651
eb0d4dbf 652static const char *const texts_autosync_aes_tco[] = { "Word Clock",
0dca1793
AK		 653 "AES1", "AES2", "AES3", "AES4",
654 "AES5", "AES6", "AES7", "AES8",
db2d1a91
AK		 655 "TCO", "Sync In"
656};
eb0d4dbf 657static const char *const texts_autosync_aes[] = { "Word Clock",
0dca1793 658 "AES1", "AES2", "AES3", "AES4",
db2d1a91
AK		 659 "AES5", "AES6", "AES7", "AES8",
660 "Sync In"
661};
eb0d4dbf 662static const char *const texts_autosync_madi_tco[] = { "Word Clock",
0dca1793 663 "MADI", "TCO", "Sync In" };
eb0d4dbf 664static const char *const texts_autosync_madi[] = { "Word Clock",
0dca1793
AK		 665 "MADI", "Sync In" };
666
eb0d4dbf 667static const char *const texts_autosync_raydat_tco[] = {
0dca1793
AK		 668 "Word Clock",
669 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
670 "AES", "SPDIF", "TCO", "Sync In"
671};
eb0d4dbf 672static const char *const texts_autosync_raydat[] = {
0dca1793
AK		 673 "Word Clock",
674 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
675 "AES", "SPDIF", "Sync In"
676};
eb0d4dbf 677static const char *const texts_autosync_aio_tco[] = {
0dca1793
AK		 678 "Word Clock",
679 "ADAT", "AES", "SPDIF", "TCO", "Sync In"
680};
eb0d4dbf 681static const char *const texts_autosync_aio[] = { "Word Clock",
0dca1793
AK		 682 "ADAT", "AES", "SPDIF", "Sync In" };
683
38816545 684static const char *const texts_freq[] = {
0dca1793
AK		 685 "No Lock",
686 "32 kHz",
687 "44.1 kHz",
688 "48 kHz",
689 "64 kHz",
690 "88.2 kHz",
691 "96 kHz",
692 "128 kHz",
693 "176.4 kHz",
694 "192 kHz"
695};
696
0dca1793
AK		 697static char *texts_ports_madi[] = {
698 "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6",
699 "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12",
700 "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18",
701 "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24",
702 "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30",
703 "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36",
704 "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42",
705 "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48",
706 "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54",
707 "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60",
708 "MADI.61", "MADI.62", "MADI.63", "MADI.64",
709};
710
711
712static char *texts_ports_raydat_ss[] = {
713 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6",
714 "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
715 "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2",
716 "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8",
717 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6",
718 "ADAT4.7", "ADAT4.8",
719 "AES.L", "AES.R",
720 "SPDIF.L", "SPDIF.R"
721};
722
723static char *texts_ports_raydat_ds[] = {
724 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4",
725 "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
726 "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4",
727 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4",
728 "AES.L", "AES.R",
729 "SPDIF.L", "SPDIF.R"
730};
731
732static char *texts_ports_raydat_qs[] = {
733 "ADAT1.1", "ADAT1.2",
734 "ADAT2.1", "ADAT2.2",
735 "ADAT3.1", "ADAT3.2",
736 "ADAT4.1", "ADAT4.2",
737 "AES.L", "AES.R",
738 "SPDIF.L", "SPDIF.R"
739};
740
741
742static char *texts_ports_aio_in_ss[] = {
743 "Analogue.L", "Analogue.R",
744 "AES.L", "AES.R",
745 "SPDIF.L", "SPDIF.R",
746 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
3de9db26
AK		 747 "ADAT.7", "ADAT.8",
748 "AEB.1", "AEB.2", "AEB.3", "AEB.4"
0dca1793
AK		 749};
750
751static char *texts_ports_aio_out_ss[] = {
752 "Analogue.L", "Analogue.R",
753 "AES.L", "AES.R",
754 "SPDIF.L", "SPDIF.R",
755 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
756 "ADAT.7", "ADAT.8",
3de9db26
AK		 757 "Phone.L", "Phone.R",
758 "AEB.1", "AEB.2", "AEB.3", "AEB.4"
0dca1793
AK		 759};
760
761static char *texts_ports_aio_in_ds[] = {
762 "Analogue.L", "Analogue.R",
763 "AES.L", "AES.R",
764 "SPDIF.L", "SPDIF.R",
3de9db26
AK		 765 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
766 "AEB.1", "AEB.2", "AEB.3", "AEB.4"
0dca1793
AK		 767};
768
769static char *texts_ports_aio_out_ds[] = {
770 "Analogue.L", "Analogue.R",
771 "AES.L", "AES.R",
772 "SPDIF.L", "SPDIF.R",
773 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
3de9db26
AK		 774 "Phone.L", "Phone.R",
775 "AEB.1", "AEB.2", "AEB.3", "AEB.4"
0dca1793
AK		 776};
777
778static char *texts_ports_aio_in_qs[] = {
779 "Analogue.L", "Analogue.R",
780 "AES.L", "AES.R",
781 "SPDIF.L", "SPDIF.R",
3de9db26
AK		 782 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
783 "AEB.1", "AEB.2", "AEB.3", "AEB.4"
0dca1793
AK		 784};
785
786static char *texts_ports_aio_out_qs[] = {
787 "Analogue.L", "Analogue.R",
788 "AES.L", "AES.R",
789 "SPDIF.L", "SPDIF.R",
790 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
3de9db26
AK		 791 "Phone.L", "Phone.R",
792 "AEB.1", "AEB.2", "AEB.3", "AEB.4"
0dca1793
AK		 793};
794
432d2500
AK		 795static char *texts_ports_aes32[] = {
796 "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7",
797 "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14",
798 "AES.15", "AES.16"
799};
800
55a57606
AK		 801/* These tables map the ALSA channels 1..N to the channels that we
802 need to use in order to find the relevant channel buffer. RME
803 refers to this kind of mapping as between "the ADAT channel and
804 the DMA channel." We index it using the logical audio channel,
805 and the value is the DMA channel (i.e. channel buffer number)
806 where the data for that channel can be read/written from/to.
807*/
808
809static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = {
810 0, 1, 2, 3, 4, 5, 6, 7,
811 8, 9, 10, 11, 12, 13, 14, 15,
812 16, 17, 18, 19, 20, 21, 22, 23,
813 24, 25, 26, 27, 28, 29, 30, 31,
814 32, 33, 34, 35, 36, 37, 38, 39,
815 40, 41, 42, 43, 44, 45, 46, 47,
816 48, 49, 50, 51, 52, 53, 54, 55,
817 56, 57, 58, 59, 60, 61, 62, 63
818};
819
55a57606
AK		 820static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = {
821 4, 5, 6, 7, 8, 9, 10, 11, /* ADAT 1 */
822 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */
823 20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */
824 28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */
825 0, 1, /* AES */
826 2, 3, /* SPDIF */
827 -1, -1, -1, -1,
828 -1, -1, -1, -1, -1, -1, -1, -1,
829 -1, -1, -1, -1, -1, -1, -1, -1,
830 -1, -1, -1, -1, -1, -1, -1, -1,
831};
832
833static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = {
834 4, 5, 6, 7, /* ADAT 1 */
835 8, 9, 10, 11, /* ADAT 2 */
836 12, 13, 14, 15, /* ADAT 3 */
837 16, 17, 18, 19, /* ADAT 4 */
838 0, 1, /* AES */
839 2, 3, /* SPDIF */
840 -1, -1, -1, -1,
841 -1, -1, -1, -1, -1, -1, -1, -1,
842 -1, -1, -1, -1, -1, -1, -1, -1,
843 -1, -1, -1, -1, -1, -1, -1, -1,
844 -1, -1, -1, -1, -1, -1, -1, -1,
845 -1, -1, -1, -1, -1, -1, -1, -1,
846};
847
848static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = {
849 4, 5, /* ADAT 1 */
850 6, 7, /* ADAT 2 */
851 8, 9, /* ADAT 3 */
852 10, 11, /* ADAT 4 */
853 0, 1, /* AES */
854 2, 3, /* SPDIF */
855 -1, -1, -1, -1,
856 -1, -1, -1, -1, -1, -1, -1, -1,
857 -1, -1, -1, -1, -1, -1, -1, -1,
858 -1, -1, -1, -1, -1, -1, -1, -1,
859 -1, -1, -1, -1, -1, -1, -1, -1,
860 -1, -1, -1, -1, -1, -1, -1, -1,
861 -1, -1, -1, -1, -1, -1, -1, -1,
862};
863
864static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = {
865 0, 1, /* line in */
866 8, 9, /* aes in, */
867 10, 11, /* spdif in */
868 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */
3de9db26
AK		 869 2, 3, 4, 5, /* AEB */
870 -1, -1, -1, -1, -1, -1,
55a57606
AK		 871 -1, -1, -1, -1, -1, -1, -1, -1,
872 -1, -1, -1, -1, -1, -1, -1, -1,
873 -1, -1, -1, -1, -1, -1, -1, -1,
874 -1, -1, -1, -1, -1, -1, -1, -1,
875 -1, -1, -1, -1, -1, -1, -1, -1,
876};
877
878static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = {
879 0, 1, /* line out */
880 8, 9, /* aes out */
881 10, 11, /* spdif out */
882 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */
883 6, 7, /* phone out */
3de9db26
AK		 884 2, 3, 4, 5, /* AEB */
885 -1, -1, -1, -1,
55a57606
AK		 886 -1, -1, -1, -1, -1, -1, -1, -1,
887 -1, -1, -1, -1, -1, -1, -1, -1,
888 -1, -1, -1, -1, -1, -1, -1, -1,
889 -1, -1, -1, -1, -1, -1, -1, -1,
890 -1, -1, -1, -1, -1, -1, -1, -1,
891};
892
893static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = {
894 0, 1, /* line in */
895 8, 9, /* aes in */
896 10, 11, /* spdif in */
897 12, 14, 16, 18, /* adat in */
3de9db26
AK		 898 2, 3, 4, 5, /* AEB */
899 -1, -1,
55a57606
AK		 900 -1, -1, -1, -1, -1, -1, -1, -1,
901 -1, -1, -1, -1, -1, -1, -1, -1,
902 -1, -1, -1, -1, -1, -1, -1, -1,
903 -1, -1, -1, -1, -1, -1, -1, -1,
904 -1, -1, -1, -1, -1, -1, -1, -1,
905 -1, -1, -1, -1, -1, -1, -1, -1
906};
907
908static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = {
909 0, 1, /* line out */
910 8, 9, /* aes out */
911 10, 11, /* spdif out */
912 12, 14, 16, 18, /* adat out */
913 6, 7, /* phone out */
3de9db26 914 2, 3, 4, 5, /* AEB */
55a57606
AK		 915 -1, -1, -1, -1, -1, -1, -1, -1,
916 -1, -1, -1, -1, -1, -1, -1, -1,
917 -1, -1, -1, -1, -1, -1, -1, -1,
918 -1, -1, -1, -1, -1, -1, -1, -1,
919 -1, -1, -1, -1, -1, -1, -1, -1,
920 -1, -1, -1, -1, -1, -1, -1, -1
921};
922
923static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = {
924 0, 1, /* line in */
925 8, 9, /* aes in */
926 10, 11, /* spdif in */
927 12, 16, /* adat in */
3de9db26
AK		 928 2, 3, 4, 5, /* AEB */
929 -1, -1, -1, -1,
55a57606
AK		 930 -1, -1, -1, -1, -1, -1, -1, -1,
931 -1, -1, -1, -1, -1, -1, -1, -1,
932 -1, -1, -1, -1, -1, -1, -1, -1,
933 -1, -1, -1, -1, -1, -1, -1, -1,
934 -1, -1, -1, -1, -1, -1, -1, -1,
935 -1, -1, -1, -1, -1, -1, -1, -1
936};
937
938static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = {
939 0, 1, /* line out */
940 8, 9, /* aes out */
941 10, 11, /* spdif out */
942 12, 16, /* adat out */
943 6, 7, /* phone out */
3de9db26
AK		 944 2, 3, 4, 5, /* AEB */
945 -1, -1,
55a57606
AK		 946 -1, -1, -1, -1, -1, -1, -1, -1,
947 -1, -1, -1, -1, -1, -1, -1, -1,
948 -1, -1, -1, -1, -1, -1, -1, -1,
949 -1, -1, -1, -1, -1, -1, -1, -1,
950 -1, -1, -1, -1, -1, -1, -1, -1,
951 -1, -1, -1, -1, -1, -1, -1, -1
952};
953
432d2500
AK		 954static char channel_map_aes32[HDSPM_MAX_CHANNELS] = {
955 0, 1, 2, 3, 4, 5, 6, 7,
956 8, 9, 10, 11, 12, 13, 14, 15,
957 -1, -1, -1, -1, -1, -1, -1, -1,
958 -1, -1, -1, -1, -1, -1, -1, -1,
959 -1, -1, -1, -1, -1, -1, -1, -1,
960 -1, -1, -1, -1, -1, -1, -1, -1,
961 -1, -1, -1, -1, -1, -1, -1, -1,
962 -1, -1, -1, -1, -1, -1, -1, -1
963};
964
98274f07
TI		 965struct hdspm_midi {
966 struct hdspm *hdspm;
763f356c 967 int id;
98274f07
TI		 968 struct snd_rawmidi *rmidi;
969 struct snd_rawmidi_substream *input;
970 struct snd_rawmidi_substream *output;
763f356c
TI		 971 char istimer; /* timer in use */
972 struct timer_list timer;
973 spinlock_t lock;
974 int pending;
0dca1793
AK		 975 int dataIn;
976 int statusIn;
977 int dataOut;
978 int statusOut;
979 int ie;
980 int irq;
981};
982
983struct hdspm_tco {
69358fca
MD		 984 int input; /* 0: LTC, 1:Video, 2: WC*/
985 int framerate; /* 0=24, 1=25, 2=29.97, 3=29.97d, 4=30, 5=30d */
986 int wordclock; /* 0=1:1, 1=44.1->48, 2=48->44.1 */
987 int samplerate; /* 0=44.1, 1=48, 2= freq from app */
988 int pull; /* 0=0, 1=+0.1%, 2=-0.1%, 3=+4%, 4=-4%*/
0dca1793 989 int term; /* 0 = off, 1 = on */
763f356c
TI		 990};
991
98274f07 992struct hdspm {
763f356c 993 spinlock_t lock;
ef5fa1a4
TI		 994 /* only one playback and/or capture stream */
995 struct snd_pcm_substream *capture_substream;
996 struct snd_pcm_substream *playback_substream;
763f356c
TI		 997
998 char *card_name; /* for procinfo */
3cee5a60
RB		 999 unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/
1000
0dca1793 1001 uint8_t io_type;
763f356c 1002
763f356c
TI		 1003 int monitor_outs; /* set up monitoring outs init flag */
1004
1005 u32 control_register; /* cached value */
1006 u32 control2_register; /* cached value */
69358fca 1007 u32 settings_register; /* cached value for AIO / RayDat (sync reference, master/slave) */
763f356c 1008
0dca1793 1009 struct hdspm_midi midi[4];
763f356c
TI		 1010 struct tasklet_struct midi_tasklet;
1011
1012 size_t period_bytes;
0dca1793
AK		 1013 unsigned char ss_in_channels;
1014 unsigned char ds_in_channels;
1015 unsigned char qs_in_channels;
1016 unsigned char ss_out_channels;
1017 unsigned char ds_out_channels;
1018 unsigned char qs_out_channels;
1019
1020 unsigned char max_channels_in;
1021 unsigned char max_channels_out;
1022
286bed0f
TI		 1023 signed char *channel_map_in;
1024 signed char *channel_map_out;
0dca1793 1025
286bed0f
TI		 1026 signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs;
1027 signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs;
0dca1793
AK		 1028
1029 char **port_names_in;
1030 char **port_names_out;
1031
1032 char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs;
1033 char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs;
763f356c
TI		 1034
1035 unsigned char *playback_buffer; /* suitably aligned address */
1036 unsigned char *capture_buffer; /* suitably aligned address */
1037
1038 pid_t capture_pid; /* process id which uses capture */
1039 pid_t playback_pid; /* process id which uses capture */
1040 int running; /* running status */
1041
1042 int last_external_sample_rate; /* samplerate mystic ... */
1043 int last_internal_sample_rate;
1044 int system_sample_rate;
1045
763f356c
TI		 1046 int dev; /* Hardware vars... */
1047 int irq;
1048 unsigned long port;
1049 void __iomem *iobase;
1050
1051 int irq_count; /* for debug */
0dca1793 1052 int midiPorts;
763f356c 1053
98274f07
TI		 1054 struct snd_card *card; /* one card */
1055 struct snd_pcm *pcm; /* has one pcm */
1056 struct snd_hwdep *hwdep; /* and a hwdep for additional ioctl */
763f356c
TI		 1057 struct pci_dev *pci; /* and an pci info */
1058
1059 /* Mixer vars */
ef5fa1a4
TI		 1060 /* fast alsa mixer */
1061 struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS];
1062 /* but input to much, so not used */
1063 struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS];
25985edc 1064 /* full mixer accessible over mixer ioctl or hwdep-device */
ef5fa1a4 1065 struct hdspm_mixer *mixer;
763f356c 1066
0dca1793 1067 struct hdspm_tco *tco; /* NULL if no TCO detected */
763f356c 1068
eb0d4dbf 1069 const char *const *texts_autosync;
0dca1793 1070 int texts_autosync_items;
763f356c 1071
0dca1793 1072 cycles_t last_interrupt;
730a5865 1073
7d53a631
AK		 1074 unsigned int serial;
1075
730a5865 1076 struct hdspm_peak_rms peak_rms;
763f356c
TI		 1077};
1078
763f356c 1079
9baa3c34 1080static const struct pci_device_id snd_hdspm_ids[] = {
763f356c
TI		 1081 {
1082 .vendor = PCI_VENDOR_ID_XILINX,
1083 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI,
1084 .subvendor = PCI_ANY_ID,
1085 .subdevice = PCI_ANY_ID,
1086 .class = 0,
1087 .class_mask = 0,
1088 .driver_data = 0},
1089 {0,}
1090};
1091
1092MODULE_DEVICE_TABLE(pci, snd_hdspm_ids);
1093
1094/* prototypes */
e23e7a14
BP		 1095static int snd_hdspm_create_alsa_devices(struct snd_card *card,
1096 struct hdspm *hdspm);
1097static int snd_hdspm_create_pcm(struct snd_card *card,
1098 struct hdspm *hdspm);
98274f07 1099
0dca1793 1100static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm);
3f7bf918 1101static inline int hdspm_get_pll_freq(struct hdspm *hdspm);
0dca1793
AK		 1102static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm);
1103static int hdspm_autosync_ref(struct hdspm *hdspm);
34be7ebb 1104static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out);
0dca1793 1105static int snd_hdspm_set_defaults(struct hdspm *hdspm);
21a164df 1106static int hdspm_system_clock_mode(struct hdspm *hdspm);
0dca1793 1107static void hdspm_set_sgbuf(struct hdspm *hdspm,
77a23f26 1108 struct snd_pcm_substream *substream,
763f356c
TI		 1109 unsigned int reg, int channels);
1110
5b266354
AK		 1111static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx);
1112static int hdspm_wc_sync_check(struct hdspm *hdspm);
1113static int hdspm_tco_sync_check(struct hdspm *hdspm);
1114static int hdspm_sync_in_sync_check(struct hdspm *hdspm);
1115
1116static int hdspm_get_aes_sample_rate(struct hdspm *hdspm, int index);
1117static int hdspm_get_tco_sample_rate(struct hdspm *hdspm);
1118static int hdspm_get_wc_sample_rate(struct hdspm *hdspm);
1119
1120
1121
3cee5a60
RB		 1122static inline int HDSPM_bit2freq(int n)
1123{
62cef821
DV		 1124 static const int bit2freq_tab[] = {
1125 0, 32000, 44100, 48000, 64000, 88200,
3cee5a60
RB		 1126 96000, 128000, 176400, 192000 };
1127 if (n < 1 || n > 9)
1128 return 0;
1129 return bit2freq_tab[n];
1130}
1131
b2ed6326
AK		 1132static bool hdspm_is_raydat_or_aio(struct hdspm *hdspm)
1133{
1134 return ((AIO == hdspm->io_type) || (RayDAT == hdspm->io_type));
1135}
1136
1137
0dca1793 1138/* Write/read to/from HDSPM with Adresses in Bytes
763f356c
TI		 1139 not words but only 32Bit writes are allowed */
1140
98274f07 1141static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg,
763f356c
TI		 1142 unsigned int val)
1143{
1144 writel(val, hdspm->iobase + reg);
1145}
1146
98274f07 1147static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg)
763f356c
TI		 1148{
1149 return readl(hdspm->iobase + reg);
1150}
1151
0dca1793
AK		 1152/* for each output channel (chan) I have an Input (in) and Playback (pb) Fader
1153 mixer is write only on hardware so we have to cache him for read
763f356c
TI		 1154 each fader is a u32, but uses only the first 16 bit */
1155
98274f07 1156static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan,
763f356c
TI		 1157 unsigned int in)
1158{
5bab2482 1159 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
763f356c
TI		 1160 return 0;
1161
1162 return hdspm->mixer->ch[chan].in[in];
1163}
1164
98274f07 1165static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan,
763f356c
TI		 1166 unsigned int pb)
1167{
5bab2482 1168 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
763f356c
TI		 1169 return 0;
1170 return hdspm->mixer->ch[chan].pb[pb];
1171}
1172
62cef821 1173static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan,
763f356c
TI		 1174 unsigned int in, unsigned short data)
1175{
1176 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1177 return -1;
1178
1179 hdspm_write(hdspm,
1180 HDSPM_MADI_mixerBase +
1181 ((in + 128 * chan) * sizeof(u32)),
1182 (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF));
1183 return 0;
1184}
1185
62cef821 1186static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan,
763f356c
TI		 1187 unsigned int pb, unsigned short data)
1188{
1189 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1190 return -1;
1191
1192 hdspm_write(hdspm,
1193 HDSPM_MADI_mixerBase +
1194 ((64 + pb + 128 * chan) * sizeof(u32)),
1195 (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF));
1196 return 0;
1197}
1198
1199
1200/* enable DMA for specific channels, now available for DSP-MADI */
98274f07 1201static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v)
763f356c
TI		 1202{
1203 hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v);
1204}
1205
98274f07 1206static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v)
763f356c
TI		 1207{
1208 hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v);
1209}
1210
1211/* check if same process is writing and reading */
62cef821 1212static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm)
763f356c
TI		 1213{
1214 unsigned long flags;
1215 int ret = 1;
1216
1217 spin_lock_irqsave(&hdspm->lock, flags);
1218 if ((hdspm->playback_pid != hdspm->capture_pid) &&
1219 (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) {
1220 ret = 0;
1221 }
1222 spin_unlock_irqrestore(&hdspm->lock, flags);
1223 return ret;
1224}
1225
fcdc4ba1
AK		 1226/* round arbitary sample rates to commonly known rates */
1227static int hdspm_round_frequency(int rate)
1228{
1229 if (rate < 38050)
1230 return 32000;
1231 if (rate < 46008)
1232 return 44100;
1233 else
1234 return 48000;
1235}
1236
a8a729fa
AK		 1237/* QS and DS rates normally can not be detected
1238 * automatically by the card. Only exception is MADI
1239 * in 96k frame mode.
1240 *
1241 * So if we read SS values (32 .. 48k), check for
1242 * user-provided DS/QS bits in the control register
1243 * and multiply the base frequency accordingly.
1244 */
1245static int hdspm_rate_multiplier(struct hdspm *hdspm, int rate)
1246{
1247 if (rate <= 48000) {
1248 if (hdspm->control_register & HDSPM_QuadSpeed)
1249 return rate * 4;
1250 else if (hdspm->control_register &
1251 HDSPM_DoubleSpeed)
1252 return rate * 2;
68593c93 1253 }
a8a729fa
AK		 1254 return rate;
1255}
1256
5b266354 1257/* check for external sample rate, returns the sample rate in Hz*/
62cef821 1258static int hdspm_external_sample_rate(struct hdspm *hdspm)
763f356c 1259{
df57de17 1260 unsigned int status, status2;
0dca1793 1261 int syncref, rate = 0, rate_bits;
3cee5a60 1262
0dca1793
AK		 1263 switch (hdspm->io_type) {
1264 case AES32:
1265 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1266 status = hdspm_read(hdspm, HDSPM_statusRegister);
0dca1793
AK		 1267
1268 syncref = hdspm_autosync_ref(hdspm);
dbae4a0c
AK		 1269 switch (syncref) {
1270 case HDSPM_AES32_AUTOSYNC_FROM_WORD:
1271 /* Check WC sync and get sample rate */
1272 if (hdspm_wc_sync_check(hdspm))
1273 return HDSPM_bit2freq(hdspm_get_wc_sample_rate(hdspm));
1274 break;
1275
1276 case HDSPM_AES32_AUTOSYNC_FROM_AES1:
1277 case HDSPM_AES32_AUTOSYNC_FROM_AES2:
1278 case HDSPM_AES32_AUTOSYNC_FROM_AES3:
1279 case HDSPM_AES32_AUTOSYNC_FROM_AES4:
1280 case HDSPM_AES32_AUTOSYNC_FROM_AES5:
1281 case HDSPM_AES32_AUTOSYNC_FROM_AES6:
1282 case HDSPM_AES32_AUTOSYNC_FROM_AES7:
1283 case HDSPM_AES32_AUTOSYNC_FROM_AES8:
1284 /* Check AES sync and get sample rate */
1285 if (hdspm_aes_sync_check(hdspm, syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1))
1286 return HDSPM_bit2freq(hdspm_get_aes_sample_rate(hdspm,
1287 syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1));
1288 break;
1289
1290
1291 case HDSPM_AES32_AUTOSYNC_FROM_TCO:
1292 /* Check TCO sync and get sample rate */
1293 if (hdspm_tco_sync_check(hdspm))
1294 return HDSPM_bit2freq(hdspm_get_tco_sample_rate(hdspm));
1295 break;
1296 default:
1297 return 0;
1298 } /* end switch(syncref) */
0dca1793
AK		 1299 break;
1300
1301 case MADIface:
1302 status = hdspm_read(hdspm, HDSPM_statusRegister);
1303
1304 if (!(status & HDSPM_madiLock)) {
1305 rate = 0; /* no lock */
1306 } else {
1307 switch (status & (HDSPM_status1_freqMask)) {
1308 case HDSPM_status1_F_0*1:
1309 rate = 32000; break;
1310 case HDSPM_status1_F_0*2:
1311 rate = 44100; break;
1312 case HDSPM_status1_F_0*3:
1313 rate = 48000; break;
1314 case HDSPM_status1_F_0*4:
1315 rate = 64000; break;
1316 case HDSPM_status1_F_0*5:
1317 rate = 88200; break;
1318 case HDSPM_status1_F_0*6:
1319 rate = 96000; break;
1320 case HDSPM_status1_F_0*7:
1321 rate = 128000; break;
1322 case HDSPM_status1_F_0*8:
1323 rate = 176400; break;
1324 case HDSPM_status1_F_0*9:
1325 rate = 192000; break;
1326 default:
1327 rate = 0; break;
1328 }
1329 }
1330
1331 break;
1332
1333 case MADI:
1334 case AIO:
1335 case RayDAT:
1336 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1337 status = hdspm_read(hdspm, HDSPM_statusRegister);
1338 rate = 0;
763f356c 1339
3cee5a60
RB		 1340 /* if wordclock has synced freq and wordclock is valid */
1341 if ((status2 & HDSPM_wcLock) != 0 &&
fedf1535 1342 (status2 & HDSPM_SelSyncRef0) == 0) {
763f356c 1343
3cee5a60 1344 rate_bits = status2 & HDSPM_wcFreqMask;
763f356c 1345
0dca1793 1346
3cee5a60
RB		 1347 switch (rate_bits) {
1348 case HDSPM_wcFreq32:
1349 rate = 32000;
1350 break;
1351 case HDSPM_wcFreq44_1:
1352 rate = 44100;
1353 break;
1354 case HDSPM_wcFreq48:
1355 rate = 48000;
1356 break;
1357 case HDSPM_wcFreq64:
1358 rate = 64000;
1359 break;
1360 case HDSPM_wcFreq88_2:
1361 rate = 88200;
1362 break;
1363 case HDSPM_wcFreq96:
1364 rate = 96000;
1365 break;
a8cd7148
AK		 1366 case HDSPM_wcFreq128:
1367 rate = 128000;
1368 break;
1369 case HDSPM_wcFreq176_4:
1370 rate = 176400;
1371 break;
1372 case HDSPM_wcFreq192:
1373 rate = 192000;
1374 break;
3cee5a60
RB		 1375 default:
1376 rate = 0;
1377 break;
1378 }
763f356c 1379 }
763f356c 1380
ef5fa1a4
TI		 1381 /* if rate detected and Syncref is Word than have it,
1382 * word has priority to MADI
1383 */
3cee5a60 1384 if (rate != 0 &&
0dca1793 1385 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD)
7b559397 1386 return hdspm_rate_multiplier(hdspm, rate);
763f356c 1387
0dca1793 1388 /* maybe a madi input (which is taken if sel sync is madi) */
3cee5a60
RB		 1389 if (status & HDSPM_madiLock) {
1390 rate_bits = status & HDSPM_madiFreqMask;
763f356c 1391
3cee5a60
RB		 1392 switch (rate_bits) {
1393 case HDSPM_madiFreq32:
1394 rate = 32000;
1395 break;
1396 case HDSPM_madiFreq44_1:
1397 rate = 44100;
1398 break;
1399 case HDSPM_madiFreq48:
1400 rate = 48000;
1401 break;
1402 case HDSPM_madiFreq64:
1403 rate = 64000;
1404 break;
1405 case HDSPM_madiFreq88_2:
1406 rate = 88200;
1407 break;
1408 case HDSPM_madiFreq96:
1409 rate = 96000;
1410 break;
1411 case HDSPM_madiFreq128:
1412 rate = 128000;
1413 break;
1414 case HDSPM_madiFreq176_4:
1415 rate = 176400;
1416 break;
1417 case HDSPM_madiFreq192:
1418 rate = 192000;
1419 break;
1420 default:
1421 rate = 0;
1422 break;
1423 }
d12c51d8 1424
fcdc4ba1
AK		 1425 } /* endif HDSPM_madiLock */
1426
1427 /* check sample rate from TCO or SYNC_IN */
1428 {
1429 bool is_valid_input = 0;
1430 bool has_sync = 0;
1431
1432 syncref = hdspm_autosync_ref(hdspm);
1433 if (HDSPM_AUTOSYNC_FROM_TCO == syncref) {
1434 is_valid_input = 1;
1435 has_sync = (HDSPM_SYNC_CHECK_SYNC ==
1436 hdspm_tco_sync_check(hdspm));
1437 } else if (HDSPM_AUTOSYNC_FROM_SYNC_IN == syncref) {
1438 is_valid_input = 1;
1439 has_sync = (HDSPM_SYNC_CHECK_SYNC ==
1440 hdspm_sync_in_sync_check(hdspm));
d12c51d8 1441 }
fcdc4ba1
AK		 1442
1443 if (is_valid_input && has_sync) {
1444 rate = hdspm_round_frequency(
1445 hdspm_get_pll_freq(hdspm));
1446 }
1447 }
1448
a8a729fa
AK		 1449 rate = hdspm_rate_multiplier(hdspm, rate);
1450
0dca1793 1451 break;
763f356c 1452 }
0dca1793
AK		 1453
1454 return rate;
763f356c
TI		 1455}
1456
7cb155ff
AK		 1457/* return latency in samples per period */
1458static int hdspm_get_latency(struct hdspm *hdspm)
1459{
1460 int n;
1461
1462 n = hdspm_decode_latency(hdspm->control_register);
1463
1464 /* Special case for new RME cards with 32 samples period size.
1465 * The three latency bits in the control register
1466 * (HDSP_LatencyMask) encode latency values of 64 samples as
1467 * 0, 128 samples as 1 ... 4096 samples as 6. For old cards, 7
1468 * denotes 8192 samples, but on new cards like RayDAT or AIO,
1469 * it corresponds to 32 samples.
1470 */
1471 if ((7 == n) && (RayDAT == hdspm->io_type || AIO == hdspm->io_type))
1472 n = -1;
1473
1474 return 1 << (n + 6);
1475}
1476
763f356c 1477/* Latency function */
0dca1793 1478static inline void hdspm_compute_period_size(struct hdspm *hdspm)
763f356c 1479{
7cb155ff 1480 hdspm->period_bytes = 4 * hdspm_get_latency(hdspm);
763f356c
TI		 1481}
1482
0dca1793
AK		 1483
1484static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm)
763f356c
TI		 1485{
1486 int position;
1487
1488 position = hdspm_read(hdspm, HDSPM_statusRegister);
483cee77
AK		 1489
1490 switch (hdspm->io_type) {
1491 case RayDAT:
1492 case AIO:
1493 position &= HDSPM_BufferPositionMask;
1494 position /= 4; /* Bytes per sample */
1495 break;
1496 default:
1497 position = (position & HDSPM_BufferID) ?
1498 (hdspm->period_bytes / 4) : 0;
1499 }
763f356c
TI		 1500
1501 return position;
1502}
1503
1504
98274f07 1505static inline void hdspm_start_audio(struct hdspm * s)
763f356c
TI		 1506{
1507 s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start);
1508 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1509}
1510
98274f07 1511static inline void hdspm_stop_audio(struct hdspm * s)
763f356c
TI		 1512{
1513 s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable);
1514 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1515}
1516
1517/* should I silence all or only opened ones ? doit all for first even is 4MB*/
62cef821 1518static void hdspm_silence_playback(struct hdspm *hdspm)
763f356c
TI		 1519{
1520 int i;
1521 int n = hdspm->period_bytes;
1522 void *buf = hdspm->playback_buffer;
1523
3cee5a60
RB		 1524 if (buf == NULL)
1525 return;
763f356c
TI		 1526
1527 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
1528 memset(buf, 0, n);
1529 buf += HDSPM_CHANNEL_BUFFER_BYTES;
1530 }
1531}
1532
0dca1793 1533static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames)
763f356c
TI		 1534{
1535 int n;
1536
1537 spin_lock_irq(&s->lock);
1538
2e610270
AK		 1539 if (32 == frames) {
1540 /* Special case for new RME cards like RayDAT/AIO which
1541 * support period sizes of 32 samples. Since latency is
1542 * encoded in the three bits of HDSP_LatencyMask, we can only
1543 * have values from 0 .. 7. While 0 still means 64 samples and
1544 * 6 represents 4096 samples on all cards, 7 represents 8192
1545 * on older cards and 32 samples on new cards.
1546 *
1547 * In other words, period size in samples is calculated by
1548 * 2^(n+6) with n ranging from 0 .. 7.
1549 */
1550 n = 7;
1551 } else {
1552 frames >>= 7;
1553 n = 0;
1554 while (frames) {
1555 n++;
1556 frames >>= 1;
1557 }
763f356c 1558 }
2e610270 1559
763f356c
TI		 1560 s->control_register &= ~HDSPM_LatencyMask;
1561 s->control_register |= hdspm_encode_latency(n);
1562
1563 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1564
1565 hdspm_compute_period_size(s);
1566
1567 spin_unlock_irq(&s->lock);
1568
1569 return 0;
1570}
1571
0dca1793
AK		 1572static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period)
1573{
1574 u64 freq_const;
1575
1576 if (period == 0)
1577 return 0;
1578
1579 switch (hdspm->io_type) {
1580 case MADI:
1581 case AES32:
1582 freq_const = 110069313433624ULL;
1583 break;
1584 case RayDAT:
1585 case AIO:
1586 freq_const = 104857600000000ULL;
1587 break;
1588 case MADIface:
1589 freq_const = 131072000000000ULL;
3d56c8e6
TI		 1590 break;
1591 default:
1592 snd_BUG();
1593 return 0;
0dca1793
AK		 1594 }
1595
1596 return div_u64(freq_const, period);
1597}
1598
1599
ffb2c3c0
RB		 1600static void hdspm_set_dds_value(struct hdspm *hdspm, int rate)
1601{
1602 u64 n;
0dca1793 1603
c1099c32
TI		 1604 if (snd_BUG_ON(rate <= 0))
1605 return;
1606
ffb2c3c0
RB		 1607 if (rate >= 112000)
1608 rate /= 4;
1609 else if (rate >= 56000)
1610 rate /= 2;
1611
0dca1793
AK		 1612 switch (hdspm->io_type) {
1613 case MADIface:
3d56c8e6
TI		 1614 n = 131072000000000ULL; /* 125 MHz */
1615 break;
0dca1793
AK		 1616 case MADI:
1617 case AES32:
3d56c8e6
TI		 1618 n = 110069313433624ULL; /* 105 MHz */
1619 break;
0dca1793
AK		 1620 case RayDAT:
1621 case AIO:
3d56c8e6
TI		 1622 n = 104857600000000ULL; /* 100 MHz */
1623 break;
1624 default:
1625 snd_BUG();
1626 return;
0dca1793
AK		 1627 }
1628
3f7440a6 1629 n = div_u64(n, rate);
ffb2c3c0 1630 /* n should be less than 2^32 for being written to FREQ register */
da3cec35 1631 snd_BUG_ON(n >> 32);
ffb2c3c0
RB		 1632 hdspm_write(hdspm, HDSPM_freqReg, (u32)n);
1633}
763f356c
TI		 1634
1635/* dummy set rate lets see what happens */
98274f07 1636static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally)
763f356c 1637{
763f356c
TI		 1638 int current_rate;
1639 int rate_bits;
1640 int not_set = 0;
6534599d 1641 int current_speed, target_speed;
763f356c
TI		 1642
1643 /* ASSUMPTION: hdspm->lock is either set, or there is no need for
1644 it (e.g. during module initialization).
1645 */
1646
1647 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) {
1648
0dca1793 1649 /* SLAVE --- */
763f356c
TI		 1650 if (called_internally) {
1651
0dca1793
AK		 1652 /* request from ctl or card initialization
1653 just make a warning an remember setting
1654 for future master mode switching */
1655
e3a471d6
TI		 1656 dev_warn(hdspm->card->dev,
1657 "Warning: device is not running as a clock master.\n");
763f356c
TI		 1658 not_set = 1;
1659 } else {
1660
1661 /* hw_param request while in AutoSync mode */
1662 int external_freq =
1663 hdspm_external_sample_rate(hdspm);
1664
ef5fa1a4
TI		 1665 if (hdspm_autosync_ref(hdspm) ==
1666 HDSPM_AUTOSYNC_FROM_NONE) {
763f356c 1667
e3a471d6 1668 dev_warn(hdspm->card->dev,
07cb3272 1669 "Detected no External Sync\n");
763f356c
TI		 1670 not_set = 1;
1671
1672 } else if (rate != external_freq) {
1673
e3a471d6
TI		 1674 dev_warn(hdspm->card->dev,
1675 "Warning: No AutoSync source for requested rate\n");
763f356c
TI		 1676 not_set = 1;
1677 }
1678 }
1679 }
1680
1681 current_rate = hdspm->system_sample_rate;
1682
1683 /* Changing between Singe, Double and Quad speed is not
1684 allowed if any substreams are open. This is because such a change
1685 causes a shift in the location of the DMA buffers and a reduction
1686 in the number of available buffers.
1687
1688 Note that a similar but essentially insoluble problem exists for
1689 externally-driven rate changes. All we can do is to flag rate
0dca1793 1690 changes in the read/write routines.
763f356c
TI		 1691 */
1692
6534599d
RB		 1693 if (current_rate <= 48000)
1694 current_speed = HDSPM_SPEED_SINGLE;
1695 else if (current_rate <= 96000)
1696 current_speed = HDSPM_SPEED_DOUBLE;
1697 else
1698 current_speed = HDSPM_SPEED_QUAD;
1699
1700 if (rate <= 48000)
1701 target_speed = HDSPM_SPEED_SINGLE;
1702 else if (rate <= 96000)
1703 target_speed = HDSPM_SPEED_DOUBLE;
1704 else
1705 target_speed = HDSPM_SPEED_QUAD;
3cee5a60 1706
763f356c
TI		 1707 switch (rate) {
1708 case 32000:
763f356c
TI		 1709 rate_bits = HDSPM_Frequency32KHz;
1710 break;
1711 case 44100:
763f356c
TI		 1712 rate_bits = HDSPM_Frequency44_1KHz;
1713 break;
1714 case 48000:
763f356c
TI		 1715 rate_bits = HDSPM_Frequency48KHz;
1716 break;
1717 case 64000:
763f356c
TI		 1718 rate_bits = HDSPM_Frequency64KHz;
1719 break;
1720 case 88200:
763f356c
TI		 1721 rate_bits = HDSPM_Frequency88_2KHz;
1722 break;
1723 case 96000:
763f356c
TI		 1724 rate_bits = HDSPM_Frequency96KHz;
1725 break;
3cee5a60 1726 case 128000:
3cee5a60
RB		 1727 rate_bits = HDSPM_Frequency128KHz;
1728 break;
1729 case 176400:
3cee5a60
RB		 1730 rate_bits = HDSPM_Frequency176_4KHz;
1731 break;
1732 case 192000:
3cee5a60
RB		 1733 rate_bits = HDSPM_Frequency192KHz;
1734 break;
763f356c
TI		 1735 default:
1736 return -EINVAL;
1737 }
1738
6534599d 1739 if (current_speed != target_speed
763f356c 1740 && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) {
e3a471d6
TI		 1741 dev_err(hdspm->card->dev,
1742 "cannot change from %s speed to %s speed mode (capture PID = %d, playback PID = %d)\n",
1743 hdspm_speed_names[current_speed],
1744 hdspm_speed_names[target_speed],
1745 hdspm->capture_pid, hdspm->playback_pid);
763f356c
TI		 1746 return -EBUSY;
1747 }
1748
1749 hdspm->control_register &= ~HDSPM_FrequencyMask;
1750 hdspm->control_register |= rate_bits;
1751 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1752
ffb2c3c0
RB		 1753 /* For AES32, need to set DDS value in FREQ register
1754 For MADI, also apparently */
1755 hdspm_set_dds_value(hdspm, rate);
0dca1793
AK		 1756
1757 if (AES32 == hdspm->io_type && rate != current_rate)
ffb2c3c0 1758 hdspm_write(hdspm, HDSPM_eeprom_wr, 0);
763f356c
TI		 1759
1760 hdspm->system_sample_rate = rate;
1761
0dca1793
AK		 1762 if (rate <= 48000) {
1763 hdspm->channel_map_in = hdspm->channel_map_in_ss;
1764 hdspm->channel_map_out = hdspm->channel_map_out_ss;
1765 hdspm->max_channels_in = hdspm->ss_in_channels;
1766 hdspm->max_channels_out = hdspm->ss_out_channels;
1767 hdspm->port_names_in = hdspm->port_names_in_ss;
1768 hdspm->port_names_out = hdspm->port_names_out_ss;
1769 } else if (rate <= 96000) {
1770 hdspm->channel_map_in = hdspm->channel_map_in_ds;
1771 hdspm->channel_map_out = hdspm->channel_map_out_ds;
1772 hdspm->max_channels_in = hdspm->ds_in_channels;
1773 hdspm->max_channels_out = hdspm->ds_out_channels;
1774 hdspm->port_names_in = hdspm->port_names_in_ds;
1775 hdspm->port_names_out = hdspm->port_names_out_ds;
1776 } else {
1777 hdspm->channel_map_in = hdspm->channel_map_in_qs;
1778 hdspm->channel_map_out = hdspm->channel_map_out_qs;
1779 hdspm->max_channels_in = hdspm->qs_in_channels;
1780 hdspm->max_channels_out = hdspm->qs_out_channels;
1781 hdspm->port_names_in = hdspm->port_names_in_qs;
1782 hdspm->port_names_out = hdspm->port_names_out_qs;
1783 }
1784
763f356c
TI		 1785 if (not_set != 0)
1786 return -1;
1787
1788 return 0;
1789}
1790
1791/* mainly for init to 0 on load */
98274f07 1792static void all_in_all_mixer(struct hdspm * hdspm, int sgain)
763f356c
TI		 1793{
1794 int i, j;
ef5fa1a4
TI		 1795 unsigned int gain;
1796
1797 if (sgain > UNITY_GAIN)
1798 gain = UNITY_GAIN;
1799 else if (sgain < 0)
1800 gain = 0;
1801 else
1802 gain = sgain;
763f356c
TI		 1803
1804 for (i = 0; i < HDSPM_MIXER_CHANNELS; i++)
1805 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) {
1806 hdspm_write_in_gain(hdspm, i, j, gain);
1807 hdspm_write_pb_gain(hdspm, i, j, gain);
1808 }
1809}
1810
1811/*----------------------------------------------------------------------------
1812 MIDI
1813 ----------------------------------------------------------------------------*/
1814
ef5fa1a4
TI		 1815static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm,
1816 int id)
763f356c
TI		 1817{
1818 /* the hardware already does the relevant bit-mask with 0xff */
0dca1793 1819 return hdspm_read(hdspm, hdspm->midi[id].dataIn);
763f356c
TI		 1820}
1821
ef5fa1a4
TI		 1822static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id,
1823 int val)
763f356c
TI		 1824{
1825 /* the hardware already does the relevant bit-mask with 0xff */
0dca1793 1826 return hdspm_write(hdspm, hdspm->midi[id].dataOut, val);
763f356c
TI		 1827}
1828
98274f07 1829static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id)
763f356c 1830{
0dca1793 1831 return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF;
763f356c
TI		 1832}
1833
98274f07 1834static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id)
763f356c
TI		 1835{
1836 int fifo_bytes_used;
1837
0dca1793 1838 fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF;
763f356c
TI		 1839
1840 if (fifo_bytes_used < 128)
1841 return 128 - fifo_bytes_used;
1842 else
1843 return 0;
1844}
1845
62cef821 1846static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id)
763f356c
TI		 1847{
1848 while (snd_hdspm_midi_input_available (hdspm, id))
1849 snd_hdspm_midi_read_byte (hdspm, id);
1850}
1851
98274f07 1852static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi)
763f356c
TI		 1853{
1854 unsigned long flags;
1855 int n_pending;
1856 int to_write;
1857 int i;
1858 unsigned char buf[128];
1859
1860 /* Output is not interrupt driven */
0dca1793 1861
763f356c 1862 spin_lock_irqsave (&hmidi->lock, flags);
ef5fa1a4
TI		 1863 if (hmidi->output &&
1864 !snd_rawmidi_transmit_empty (hmidi->output)) {
1865 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm,
1866 hmidi->id);
1867 if (n_pending > 0) {
1868 if (n_pending > (int)sizeof (buf))
1869 n_pending = sizeof (buf);
0dca1793 1870
ef5fa1a4
TI		 1871 to_write = snd_rawmidi_transmit (hmidi->output, buf,
1872 n_pending);
1873 if (to_write > 0) {
0dca1793 1874 for (i = 0; i < to_write; ++i)
ef5fa1a4
TI		 1875 snd_hdspm_midi_write_byte (hmidi->hdspm,
1876 hmidi->id,
1877 buf[i]);
763f356c
TI		 1878 }
1879 }
1880 }
1881 spin_unlock_irqrestore (&hmidi->lock, flags);
1882 return 0;
1883}
1884
98274f07 1885static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi)
763f356c 1886{
ef5fa1a4
TI		 1887 unsigned char buf[128]; /* this buffer is designed to match the MIDI
1888 * input FIFO size
1889 */
763f356c
TI		 1890 unsigned long flags;
1891 int n_pending;
1892 int i;
1893
1894 spin_lock_irqsave (&hmidi->lock, flags);
ef5fa1a4
TI		 1895 n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id);
1896 if (n_pending > 0) {
763f356c 1897 if (hmidi->input) {
ef5fa1a4 1898 if (n_pending > (int)sizeof (buf))
763f356c 1899 n_pending = sizeof (buf);
ef5fa1a4
TI		 1900 for (i = 0; i < n_pending; ++i)
1901 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm,
1902 hmidi->id);
1903 if (n_pending)
1904 snd_rawmidi_receive (hmidi->input, buf,
1905 n_pending);
763f356c
TI		 1906 } else {
1907 /* flush the MIDI input FIFO */
ef5fa1a4
TI		 1908 while (n_pending--)
1909 snd_hdspm_midi_read_byte (hmidi->hdspm,
1910 hmidi->id);
763f356c
TI		 1911 }
1912 }
1913 hmidi->pending = 0;
c0da0014 1914 spin_unlock_irqrestore(&hmidi->lock, flags);
0dca1793 1915
c0da0014 1916 spin_lock_irqsave(&hmidi->hdspm->lock, flags);
0dca1793 1917 hmidi->hdspm->control_register |= hmidi->ie;
ef5fa1a4
TI		 1918 hdspm_write(hmidi->hdspm, HDSPM_controlRegister,
1919 hmidi->hdspm->control_register);
c0da0014 1920 spin_unlock_irqrestore(&hmidi->hdspm->lock, flags);
0dca1793 1921
763f356c
TI		 1922 return snd_hdspm_midi_output_write (hmidi);
1923}
1924
ef5fa1a4
TI		 1925static void
1926snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
763f356c 1927{
98274f07
TI		 1928 struct hdspm *hdspm;
1929 struct hdspm_midi *hmidi;
763f356c 1930 unsigned long flags;
763f356c 1931
ef5fa1a4 1932 hmidi = substream->rmidi->private_data;
763f356c 1933 hdspm = hmidi->hdspm;
0dca1793 1934
763f356c
TI		 1935 spin_lock_irqsave (&hdspm->lock, flags);
1936 if (up) {
0dca1793 1937 if (!(hdspm->control_register & hmidi->ie)) {
763f356c 1938 snd_hdspm_flush_midi_input (hdspm, hmidi->id);
0dca1793 1939 hdspm->control_register |= hmidi->ie;
763f356c
TI		 1940 }
1941 } else {
0dca1793 1942 hdspm->control_register &= ~hmidi->ie;
763f356c
TI		 1943 }
1944
1945 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1946 spin_unlock_irqrestore (&hdspm->lock, flags);
1947}
1948
1949static void snd_hdspm_midi_output_timer(unsigned long data)
1950{
98274f07 1951 struct hdspm_midi *hmidi = (struct hdspm_midi *) data;
763f356c 1952 unsigned long flags;
0dca1793 1953
763f356c
TI		 1954 snd_hdspm_midi_output_write(hmidi);
1955 spin_lock_irqsave (&hmidi->lock, flags);
1956
1957 /* this does not bump hmidi->istimer, because the
1958 kernel automatically removed the timer when it
1959 expired, and we are now adding it back, thus
0dca1793 1960 leaving istimer wherever it was set before.
763f356c
TI		 1961 */
1962
04018e13
TI		 1963 if (hmidi->istimer)
1964 mod_timer(&hmidi->timer, 1 + jiffies);
763f356c
TI		 1965
1966 spin_unlock_irqrestore (&hmidi->lock, flags);
1967}
1968
ef5fa1a4
TI		 1969static void
1970snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
763f356c 1971{
98274f07 1972 struct hdspm_midi *hmidi;
763f356c
TI		 1973 unsigned long flags;
1974
ef5fa1a4 1975 hmidi = substream->rmidi->private_data;
763f356c
TI		 1976 spin_lock_irqsave (&hmidi->lock, flags);
1977 if (up) {
1978 if (!hmidi->istimer) {
04018e13
TI		 1979 setup_timer(&hmidi->timer, snd_hdspm_midi_output_timer,
1980 (unsigned long) hmidi);
1981 mod_timer(&hmidi->timer, 1 + jiffies);
763f356c
TI		 1982 hmidi->istimer++;
1983 }
1984 } else {
ef5fa1a4 1985 if (hmidi->istimer && --hmidi->istimer <= 0)
763f356c 1986 del_timer (&hmidi->timer);
763f356c
TI		 1987 }
1988 spin_unlock_irqrestore (&hmidi->lock, flags);
1989 if (up)
1990 snd_hdspm_midi_output_write(hmidi);
1991}
1992
98274f07 1993static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream)
763f356c 1994{
98274f07 1995 struct hdspm_midi *hmidi;
763f356c 1996
ef5fa1a4 1997 hmidi = substream->rmidi->private_data;
763f356c
TI		 1998 spin_lock_irq (&hmidi->lock);
1999 snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id);
2000 hmidi->input = substream;
2001 spin_unlock_irq (&hmidi->lock);
2002
2003 return 0;
2004}
2005
98274f07 2006static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream)
763f356c 2007{
98274f07 2008 struct hdspm_midi *hmidi;
763f356c 2009
ef5fa1a4 2010 hmidi = substream->rmidi->private_data;
763f356c
TI		 2011 spin_lock_irq (&hmidi->lock);
2012 hmidi->output = substream;
2013 spin_unlock_irq (&hmidi->lock);
2014
2015 return 0;
2016}
2017
98274f07 2018static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream)
763f356c 2019{
98274f07 2020 struct hdspm_midi *hmidi;
763f356c
TI		 2021
2022 snd_hdspm_midi_input_trigger (substream, 0);
2023
ef5fa1a4 2024 hmidi = substream->rmidi->private_data;
763f356c
TI		 2025 spin_lock_irq (&hmidi->lock);
2026 hmidi->input = NULL;
2027 spin_unlock_irq (&hmidi->lock);
2028
2029 return 0;
2030}
2031
98274f07 2032static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream)
763f356c 2033{
98274f07 2034 struct hdspm_midi *hmidi;
763f356c
TI		 2035
2036 snd_hdspm_midi_output_trigger (substream, 0);
2037
ef5fa1a4 2038 hmidi = substream->rmidi->private_data;
763f356c
TI		 2039 spin_lock_irq (&hmidi->lock);
2040 hmidi->output = NULL;
2041 spin_unlock_irq (&hmidi->lock);
2042
2043 return 0;
2044}
2045
485885b9 2046static const struct snd_rawmidi_ops snd_hdspm_midi_output =
763f356c
TI		 2047{
2048 .open = snd_hdspm_midi_output_open,
2049 .close = snd_hdspm_midi_output_close,
2050 .trigger = snd_hdspm_midi_output_trigger,
2051};
2052
485885b9 2053static const struct snd_rawmidi_ops snd_hdspm_midi_input =
763f356c
TI		 2054{
2055 .open = snd_hdspm_midi_input_open,
2056 .close = snd_hdspm_midi_input_close,
2057 .trigger = snd_hdspm_midi_input_trigger,
2058};
2059
e23e7a14
BP		 2060static int snd_hdspm_create_midi(struct snd_card *card,
2061 struct hdspm *hdspm, int id)
763f356c
TI		 2062{
2063 int err;
7ad210ac 2064 char buf[64];
763f356c
TI		 2065
2066 hdspm->midi[id].id = id;
763f356c 2067 hdspm->midi[id].hdspm = hdspm;
763f356c
TI		 2068 spin_lock_init (&hdspm->midi[id].lock);
2069
0dca1793
AK		 2070 if (0 == id) {
2071 if (MADIface == hdspm->io_type) {
2072 /* MIDI-over-MADI on HDSPe MADIface */
2073 hdspm->midi[0].dataIn = HDSPM_midiDataIn2;
2074 hdspm->midi[0].statusIn = HDSPM_midiStatusIn2;
2075 hdspm->midi[0].dataOut = HDSPM_midiDataOut2;
2076 hdspm->midi[0].statusOut = HDSPM_midiStatusOut2;
2077 hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable;
2078 hdspm->midi[0].irq = HDSPM_midi2IRQPending;
2079 } else {
2080 hdspm->midi[0].dataIn = HDSPM_midiDataIn0;
2081 hdspm->midi[0].statusIn = HDSPM_midiStatusIn0;
2082 hdspm->midi[0].dataOut = HDSPM_midiDataOut0;
2083 hdspm->midi[0].statusOut = HDSPM_midiStatusOut0;
2084 hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable;
2085 hdspm->midi[0].irq = HDSPM_midi0IRQPending;
2086 }
2087 } else if (1 == id) {
2088 hdspm->midi[1].dataIn = HDSPM_midiDataIn1;
2089 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1;
2090 hdspm->midi[1].dataOut = HDSPM_midiDataOut1;
2091 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1;
2092 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable;
2093 hdspm->midi[1].irq = HDSPM_midi1IRQPending;
2094 } else if ((2 == id) && (MADI == hdspm->io_type)) {
2095 /* MIDI-over-MADI on HDSPe MADI */
2096 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
2097 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
2098 hdspm->midi[2].dataOut = HDSPM_midiDataOut2;
2099 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2;
2100 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
2101 hdspm->midi[2].irq = HDSPM_midi2IRQPending;
2102 } else if (2 == id) {
2103 /* TCO MTC, read only */
2104 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
2105 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
2106 hdspm->midi[2].dataOut = -1;
2107 hdspm->midi[2].statusOut = -1;
2108 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
2109 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES;
2110 } else if (3 == id) {
2111 /* TCO MTC on HDSPe MADI */
2112 hdspm->midi[3].dataIn = HDSPM_midiDataIn3;
2113 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3;
2114 hdspm->midi[3].dataOut = -1;
2115 hdspm->midi[3].statusOut = -1;
2116 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable;
2117 hdspm->midi[3].irq = HDSPM_midi3IRQPending;
2118 }
2119
2120 if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) ||
2121 (MADIface == hdspm->io_type)))) {
2122 if ((id == 0) && (MADIface == hdspm->io_type)) {
7ad210ac
AB		 2123 snprintf(buf, sizeof(buf), "%s MIDIoverMADI",
2124 card->shortname);
0dca1793 2125 } else if ((id == 2) && (MADI == hdspm->io_type)) {
7ad210ac
AB		 2126 snprintf(buf, sizeof(buf), "%s MIDIoverMADI",
2127 card->shortname);
0dca1793 2128 } else {
7ad210ac
AB		 2129 snprintf(buf, sizeof(buf), "%s MIDI %d",
2130 card->shortname, id+1);
0dca1793
AK		 2131 }
2132 err = snd_rawmidi_new(card, buf, id, 1, 1,
2133 &hdspm->midi[id].rmidi);
2134 if (err < 0)
2135 return err;
763f356c 2136
7ad210ac
AB		 2137 snprintf(hdspm->midi[id].rmidi->name,
2138 sizeof(hdspm->midi[id].rmidi->name),
2139 "%s MIDI %d", card->id, id+1);
0dca1793
AK		 2140 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
2141
2142 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2143 SNDRV_RAWMIDI_STREAM_OUTPUT,
2144 &snd_hdspm_midi_output);
2145 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2146 SNDRV_RAWMIDI_STREAM_INPUT,
2147 &snd_hdspm_midi_input);
2148
2149 hdspm->midi[id].rmidi->info_flags |=
2150 SNDRV_RAWMIDI_INFO_OUTPUT |
2151 SNDRV_RAWMIDI_INFO_INPUT |
2152 SNDRV_RAWMIDI_INFO_DUPLEX;
2153 } else {
2154 /* TCO MTC, read only */
7ad210ac
AB		 2155 snprintf(buf, sizeof(buf), "%s MTC %d",
2156 card->shortname, id+1);
0dca1793
AK		 2157 err = snd_rawmidi_new(card, buf, id, 1, 1,
2158 &hdspm->midi[id].rmidi);
2159 if (err < 0)
2160 return err;
2161
7ad210ac
AB		 2162 snprintf(hdspm->midi[id].rmidi->name,
2163 sizeof(hdspm->midi[id].rmidi->name),
2164 "%s MTC %d", card->id, id+1);
0dca1793 2165 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
763f356c 2166
0dca1793
AK		 2167 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2168 SNDRV_RAWMIDI_STREAM_INPUT,
2169 &snd_hdspm_midi_input);
763f356c 2170
0dca1793
AK		 2171 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT;
2172 }
763f356c
TI		 2173
2174 return 0;
2175}
2176
2177
2178static void hdspm_midi_tasklet(unsigned long arg)
2179{
98274f07 2180 struct hdspm *hdspm = (struct hdspm *)arg;
0dca1793
AK		 2181 int i = 0;
2182
2183 while (i < hdspm->midiPorts) {
2184 if (hdspm->midi[i].pending)
2185 snd_hdspm_midi_input_read(&hdspm->midi[i]);
2186
2187 i++;
2188 }
2189}
763f356c
TI		 2190
2191
2192/*-----------------------------------------------------------------------------
2193 Status Interface
2194 ----------------------------------------------------------------------------*/
2195
2196/* get the system sample rate which is set */
2197
0dca1793 2198
3f7bf918
AK		 2199static inline int hdspm_get_pll_freq(struct hdspm *hdspm)
2200{
2201 unsigned int period, rate;
2202
2203 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
2204 rate = hdspm_calc_dds_value(hdspm, period);
2205
2206 return rate;
2207}
2208
ddcecf6b 2209/*
0dca1793
AK		 2210 * Calculate the real sample rate from the
2211 * current DDS value.
ddcecf6b 2212 */
0dca1793
AK		 2213static int hdspm_get_system_sample_rate(struct hdspm *hdspm)
2214{
3f7bf918 2215 unsigned int rate;
0dca1793 2216
3f7bf918 2217 rate = hdspm_get_pll_freq(hdspm);
0dca1793 2218
a97bda7d 2219 if (rate > 207000) {
21a164df
AK		 2220 /* Unreasonable high sample rate as seen on PCI MADI cards. */
2221 if (0 == hdspm_system_clock_mode(hdspm)) {
2222 /* master mode, return internal sample rate */
2223 rate = hdspm->system_sample_rate;
2224 } else {
2225 /* slave mode, return external sample rate */
2226 rate = hdspm_external_sample_rate(hdspm);
c1099c32
TI		 2227 if (!rate)
2228 rate = hdspm->system_sample_rate;
21a164df 2229 }
a97bda7d
AK		 2230 }
2231
0dca1793
AK		 2232 return rate;
2233}
2234
2235
763f356c 2236#define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \
f27a64f9
AK		 2237{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2238 .name = xname, \
2239 .index = xindex, \
2240 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2241 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2242 .info = snd_hdspm_info_system_sample_rate, \
2243 .put = snd_hdspm_put_system_sample_rate, \
2244 .get = snd_hdspm_get_system_sample_rate \
763f356c
TI		 2245}
2246
98274f07
TI		 2247static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol,
2248 struct snd_ctl_elem_info *uinfo)
763f356c
TI		 2249{
2250 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2251 uinfo->count = 1;
0dca1793
AK		 2252 uinfo->value.integer.min = 27000;
2253 uinfo->value.integer.max = 207000;
2254 uinfo->value.integer.step = 1;
763f356c
TI		 2255 return 0;
2256}
2257
0dca1793 2258
98274f07
TI		 2259static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol,
2260 struct snd_ctl_elem_value *
763f356c
TI		 2261 ucontrol)
2262{
98274f07 2263 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c 2264
0dca1793
AK		 2265 ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm);
2266 return 0;
2267}
2268
41285a98
AK		 2269static int snd_hdspm_put_system_sample_rate(struct snd_kcontrol *kcontrol,
2270 struct snd_ctl_elem_value *
2271 ucontrol)
2272{
2273 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
c1099c32 2274 int rate = ucontrol->value.integer.value[0];
41285a98 2275
c1099c32
TI		 2276 if (rate < 27000 || rate > 207000)
2277 return -EINVAL;
537e4813 2278 hdspm_set_dds_value(hdspm, ucontrol->value.integer.value[0]);
41285a98
AK		 2279 return 0;
2280}
2281
0dca1793 2282
ddcecf6b 2283/*
0dca1793 2284 * Returns the WordClock sample rate class for the given card.
ddcecf6b 2285 */
0dca1793
AK		 2286static int hdspm_get_wc_sample_rate(struct hdspm *hdspm)
2287{
2288 int status;
2289
2290 switch (hdspm->io_type) {
2291 case RayDAT:
2292 case AIO:
2293 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2294 return (status >> 16) & 0xF;
2295 break;
a57fea8e
AK		 2296 case AES32:
2297 status = hdspm_read(hdspm, HDSPM_statusRegister);
2298 return (status >> HDSPM_AES32_wcFreq_bit) & 0xF;
0dca1793
AK		 2299 default:
2300 break;
2301 }
2302
2303
2304 return 0;
2305}
2306
2307
ddcecf6b 2308/*
0dca1793 2309 * Returns the TCO sample rate class for the given card.
ddcecf6b 2310 */
0dca1793
AK		 2311static int hdspm_get_tco_sample_rate(struct hdspm *hdspm)
2312{
2313 int status;
2314
2315 if (hdspm->tco) {
2316 switch (hdspm->io_type) {
2317 case RayDAT:
2318 case AIO:
2319 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2320 return (status >> 20) & 0xF;
2321 break;
051c44fe
AK		 2322 case AES32:
2323 status = hdspm_read(hdspm, HDSPM_statusRegister);
2324 return (status >> 1) & 0xF;
0dca1793
AK		 2325 default:
2326 break;
2327 }
2328 }
2329
2330 return 0;
2331}
2332
2333
ddcecf6b 2334/*
0dca1793 2335 * Returns the SYNC_IN sample rate class for the given card.
ddcecf6b 2336 */
0dca1793
AK		 2337static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm)
2338{
2339 int status;
2340
2341 if (hdspm->tco) {
2342 switch (hdspm->io_type) {
2343 case RayDAT:
2344 case AIO:
2345 status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2346 return (status >> 12) & 0xF;
2347 break;
2348 default:
2349 break;
2350 }
2351 }
2352
763f356c
TI		 2353 return 0;
2354}
2355
ddcecf6b 2356/*
d3c36ed8 2357 * Returns the AES sample rate class for the given card.
ddcecf6b 2358 */
d3c36ed8
AK		 2359static int hdspm_get_aes_sample_rate(struct hdspm *hdspm, int index)
2360{
2361 int timecode;
2362
2363 switch (hdspm->io_type) {
2364 case AES32:
2365 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
2366 return (timecode >> (4*index)) & 0xF;
2367 break;
2368 default:
2369 break;
2370 }
2371 return 0;
2372}
0dca1793 2373
ddcecf6b 2374/*
0dca1793
AK		 2375 * Returns the sample rate class for input source <idx> for
2376 * 'new style' cards like the AIO and RayDAT.
ddcecf6b 2377 */
0dca1793
AK		 2378static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx)
2379{
2380 int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2381
2382 return (status >> (idx*4)) & 0xF;
2383}
2384
8cea5710 2385#define ENUMERATED_CTL_INFO(info, texts) \
38816545 2386 snd_ctl_enum_info(info, 1, ARRAY_SIZE(texts), texts)
8cea5710 2387
0dca1793 2388
2336142f
AK		 2389/* Helper function to query the external sample rate and return the
2390 * corresponding enum to be returned to userspace.
2391 */
2392static int hdspm_external_rate_to_enum(struct hdspm *hdspm)
2393{
2394 int rate = hdspm_external_sample_rate(hdspm);
2395 int i, selected_rate = 0;
2396 for (i = 1; i < 10; i++)
2397 if (HDSPM_bit2freq(i) == rate) {
2398 selected_rate = i;
2399 break;
2400 }
2401 return selected_rate;
2402}
2403
0dca1793 2404
763f356c 2405#define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
0dca1793
AK		 2406{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2407 .name = xname, \
2408 .private_value = xindex, \
2409 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2410 .info = snd_hdspm_info_autosync_sample_rate, \
2411 .get = snd_hdspm_get_autosync_sample_rate \
763f356c
TI		 2412}
2413
0dca1793 2414
98274f07
TI		 2415static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2416 struct snd_ctl_elem_info *uinfo)
763f356c 2417{
e5b7b1fe 2418 ENUMERATED_CTL_INFO(uinfo, texts_freq);
763f356c
TI		 2419 return 0;
2420}
2421
0dca1793 2422
98274f07
TI		 2423static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2424 struct snd_ctl_elem_value *
763f356c
TI		 2425 ucontrol)
2426{
98274f07 2427 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c 2428
0dca1793
AK		 2429 switch (hdspm->io_type) {
2430 case RayDAT:
2431 switch (kcontrol->private_value) {
2432 case 0:
2433 ucontrol->value.enumerated.item[0] =
2434 hdspm_get_wc_sample_rate(hdspm);
2435 break;
2436 case 7:
2437 ucontrol->value.enumerated.item[0] =
2438 hdspm_get_tco_sample_rate(hdspm);
2439 break;
2440 case 8:
2441 ucontrol->value.enumerated.item[0] =
2442 hdspm_get_sync_in_sample_rate(hdspm);
2443 break;
2444 default:
2445 ucontrol->value.enumerated.item[0] =
2446 hdspm_get_s1_sample_rate(hdspm,
2447 kcontrol->private_value-1);
2448 }
d681deaa 2449 break;
763f356c 2450
0dca1793
AK		 2451 case AIO:
2452 switch (kcontrol->private_value) {
2453 case 0: /* WC */
2454 ucontrol->value.enumerated.item[0] =
2455 hdspm_get_wc_sample_rate(hdspm);
2456 break;
2457 case 4: /* TCO */
2458 ucontrol->value.enumerated.item[0] =
2459 hdspm_get_tco_sample_rate(hdspm);
2460 break;
2461 case 5: /* SYNC_IN */
2462 ucontrol->value.enumerated.item[0] =
2463 hdspm_get_sync_in_sample_rate(hdspm);
2464 break;
2465 default:
2466 ucontrol->value.enumerated.item[0] =
2467 hdspm_get_s1_sample_rate(hdspm,
1cb7dbf4 2468 kcontrol->private_value-1);
0dca1793 2469 }
d681deaa 2470 break;
7c4a95b5
AK		 2471
2472 case AES32:
2473
2474 switch (kcontrol->private_value) {
2475 case 0: /* WC */
2476 ucontrol->value.enumerated.item[0] =
2477 hdspm_get_wc_sample_rate(hdspm);
2478 break;
2479 case 9: /* TCO */
2480 ucontrol->value.enumerated.item[0] =
2481 hdspm_get_tco_sample_rate(hdspm);
2482 break;
2483 case 10: /* SYNC_IN */
2484 ucontrol->value.enumerated.item[0] =
2485 hdspm_get_sync_in_sample_rate(hdspm);
2486 break;
2d63ec38
AK		 2487 case 11: /* External Rate */
2488 ucontrol->value.enumerated.item[0] =
2489 hdspm_external_rate_to_enum(hdspm);
2490 break;
7c4a95b5
AK		 2491 default: /* AES1 to AES8 */
2492 ucontrol->value.enumerated.item[0] =
2d63ec38
AK		 2493 hdspm_get_aes_sample_rate(hdspm,
2494 kcontrol->private_value -
2495 HDSPM_AES32_AUTOSYNC_FROM_AES1);
7c4a95b5 2496 break;
7c4a95b5 2497 }
d681deaa 2498 break;
b8812c55
AK		 2499
2500 case MADI:
2501 case MADIface:
2336142f
AK		 2502 ucontrol->value.enumerated.item[0] =
2503 hdspm_external_rate_to_enum(hdspm);
b8812c55 2504 break;
763f356c 2505 default:
0dca1793 2506 break;
763f356c 2507 }
763f356c 2508
0dca1793 2509 return 0;
763f356c
TI		 2510}
2511
2512
0dca1793
AK		 2513#define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \
2514{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2515 .name = xname, \
2516 .index = xindex, \
2517 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2518 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2519 .info = snd_hdspm_info_system_clock_mode, \
2520 .get = snd_hdspm_get_system_clock_mode, \
2521 .put = snd_hdspm_put_system_clock_mode, \
2522}
2523
2524
ddcecf6b 2525/*
0dca1793
AK		 2526 * Returns the system clock mode for the given card.
2527 * @returns 0 - master, 1 - slave
ddcecf6b 2528 */
0dca1793
AK		 2529static int hdspm_system_clock_mode(struct hdspm *hdspm)
2530{
2531 switch (hdspm->io_type) {
2532 case AIO:
2533 case RayDAT:
2534 if (hdspm->settings_register & HDSPM_c0Master)
2535 return 0;
2536 break;
763f356c 2537
0dca1793
AK		 2538 default:
2539 if (hdspm->control_register & HDSPM_ClockModeMaster)
2540 return 0;
2541 }
763f356c 2542
763f356c
TI		 2543 return 1;
2544}
2545
0dca1793 2546
ddcecf6b 2547/*
0dca1793
AK		 2548 * Sets the system clock mode.
2549 * @param mode 0 - master, 1 - slave
ddcecf6b 2550 */
0dca1793
AK		 2551static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode)
2552{
34be7ebb
AK		 2553 hdspm_set_toggle_setting(hdspm,
2554 (hdspm_is_raydat_or_aio(hdspm)) ?
2555 HDSPM_c0Master : HDSPM_ClockModeMaster,
2556 (0 == mode));
0dca1793
AK		 2557}
2558
2559
2560static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol,
98274f07 2561 struct snd_ctl_elem_info *uinfo)
763f356c 2562{
38816545 2563 static const char *const texts[] = { "Master", "AutoSync" };
e5b7b1fe 2564 ENUMERATED_CTL_INFO(uinfo, texts);
763f356c
TI		 2565 return 0;
2566}
2567
98274f07
TI		 2568static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol,
2569 struct snd_ctl_elem_value *ucontrol)
763f356c 2570{
98274f07 2571 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c 2572
0dca1793 2573 ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm);
763f356c
TI		 2574 return 0;
2575}
2576
0dca1793
AK		 2577static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol,
2578 struct snd_ctl_elem_value *ucontrol)
2579{
2580 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2581 int val;
2582
2583 if (!snd_hdspm_use_is_exclusive(hdspm))
2584 return -EBUSY;
2585
2586 val = ucontrol->value.enumerated.item[0];
2587 if (val < 0)
2588 val = 0;
2589 else if (val > 1)
2590 val = 1;
2591
2592 hdspm_set_system_clock_mode(hdspm, val);
2593
2594 return 0;
2595}
2596
2597
2598#define HDSPM_INTERNAL_CLOCK(xname, xindex) \
2599{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2600 .name = xname, \
2601 .index = xindex, \
2602 .info = snd_hdspm_info_clock_source, \
2603 .get = snd_hdspm_get_clock_source, \
2604 .put = snd_hdspm_put_clock_source \
763f356c
TI		 2605}
2606
0dca1793 2607
98274f07 2608static int hdspm_clock_source(struct hdspm * hdspm)
763f356c 2609{
0dca1793
AK		 2610 switch (hdspm->system_sample_rate) {
2611 case 32000: return 0;
2612 case 44100: return 1;
2613 case 48000: return 2;
2614 case 64000: return 3;
2615 case 88200: return 4;
2616 case 96000: return 5;
2617 case 128000: return 6;
2618 case 176400: return 7;
2619 case 192000: return 8;
763f356c 2620 }
0dca1793
AK		 2621
2622 return -1;
763f356c
TI		 2623}
2624
98274f07 2625static int hdspm_set_clock_source(struct hdspm * hdspm, int mode)
763f356c
TI		 2626{
2627 int rate;
2628 switch (mode) {
0dca1793
AK		 2629 case 0:
2630 rate = 32000; break;
2631 case 1:
2632 rate = 44100; break;
2633 case 2:
2634 rate = 48000; break;
2635 case 3:
2636 rate = 64000; break;
2637 case 4:
2638 rate = 88200; break;
2639 case 5:
2640 rate = 96000; break;
2641 case 6:
2642 rate = 128000; break;
2643 case 7:
2644 rate = 176400; break;
2645 case 8:
2646 rate = 192000; break;
763f356c 2647 default:
0dca1793 2648 rate = 48000;
763f356c 2649 }
763f356c
TI		 2650 hdspm_set_rate(hdspm, rate, 1);
2651 return 0;
2652}
2653
98274f07
TI		 2654static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol,
2655 struct snd_ctl_elem_info *uinfo)
763f356c 2656{
c69a637b 2657 return snd_ctl_enum_info(uinfo, 1, 9, texts_freq + 1);
763f356c
TI		 2658}
2659
98274f07
TI		 2660static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol,
2661 struct snd_ctl_elem_value *ucontrol)
763f356c 2662{
98274f07 2663 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c
TI		 2664
2665 ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm);
2666 return 0;
2667}
2668
98274f07
TI		 2669static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol,
2670 struct snd_ctl_elem_value *ucontrol)
763f356c 2671{
98274f07 2672 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c
TI		 2673 int change;
2674 int val;
2675
2676 if (!snd_hdspm_use_is_exclusive(hdspm))
2677 return -EBUSY;
2678 val = ucontrol->value.enumerated.item[0];
2679 if (val < 0)
2680 val = 0;
6534599d
RB		 2681 if (val > 9)
2682 val = 9;
763f356c
TI		 2683 spin_lock_irq(&hdspm->lock);
2684 if (val != hdspm_clock_source(hdspm))
2685 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0;
2686 else
2687 change = 0;
2688 spin_unlock_irq(&hdspm->lock);
2689 return change;
2690}
2691
763f356c 2692
0dca1793 2693#define HDSPM_PREF_SYNC_REF(xname, xindex) \
f27a64f9 2694{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
0dca1793
AK		 2695 .name = xname, \
2696 .index = xindex, \
2697 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2698 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2699 .info = snd_hdspm_info_pref_sync_ref, \
2700 .get = snd_hdspm_get_pref_sync_ref, \
2701 .put = snd_hdspm_put_pref_sync_ref \
2702}
2703
2704
ddcecf6b 2705/*
0dca1793
AK		 2706 * Returns the current preferred sync reference setting.
2707 * The semantics of the return value are depending on the
2708 * card, please see the comments for clarification.
ddcecf6b 2709 */
98274f07 2710static int hdspm_pref_sync_ref(struct hdspm * hdspm)
763f356c 2711{
0dca1793
AK		 2712 switch (hdspm->io_type) {
2713 case AES32:
3cee5a60 2714 switch (hdspm->control_register & HDSPM_SyncRefMask) {
0dca1793
AK		 2715 case 0: return 0; /* WC */
2716 case HDSPM_SyncRef0: return 1; /* AES 1 */
2717 case HDSPM_SyncRef1: return 2; /* AES 2 */
2718 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */
2719 case HDSPM_SyncRef2: return 4; /* AES 4 */
2720 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */
2721 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */
2722 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0:
2723 return 7; /* AES 7 */
2724 case HDSPM_SyncRef3: return 8; /* AES 8 */
2725 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */
3cee5a60 2726 }
0dca1793
AK		 2727 break;
2728
2729 case MADI:
2730 case MADIface:
2731 if (hdspm->tco) {
2732 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2733 case 0: return 0; /* WC */
2734 case HDSPM_SyncRef0: return 1; /* MADI */
2735 case HDSPM_SyncRef1: return 2; /* TCO */
2736 case HDSPM_SyncRef1+HDSPM_SyncRef0:
2737 return 3; /* SYNC_IN */
2738 }
2739 } else {
2740 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2741 case 0: return 0; /* WC */
2742 case HDSPM_SyncRef0: return 1; /* MADI */
2743 case HDSPM_SyncRef1+HDSPM_SyncRef0:
2744 return 2; /* SYNC_IN */
2745 }
2746 }
2747 break;
2748
2749 case RayDAT:
2750 if (hdspm->tco) {
2751 switch ((hdspm->settings_register &
2752 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2753 case 0: return 0; /* WC */
2754 case 3: return 1; /* ADAT 1 */
2755 case 4: return 2; /* ADAT 2 */
2756 case 5: return 3; /* ADAT 3 */
2757 case 6: return 4; /* ADAT 4 */
2758 case 1: return 5; /* AES */
2759 case 2: return 6; /* SPDIF */
2760 case 9: return 7; /* TCO */
2761 case 10: return 8; /* SYNC_IN */
2762 }
2763 } else {
2764 switch ((hdspm->settings_register &
2765 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2766 case 0: return 0; /* WC */
2767 case 3: return 1; /* ADAT 1 */
2768 case 4: return 2; /* ADAT 2 */
2769 case 5: return 3; /* ADAT 3 */
2770 case 6: return 4; /* ADAT 4 */
2771 case 1: return 5; /* AES */
2772 case 2: return 6; /* SPDIF */
2773 case 10: return 7; /* SYNC_IN */
2774 }
3cee5a60 2775 }
0dca1793
AK		 2776
2777 break;
2778
2779 case AIO:
2780 if (hdspm->tco) {
2781 switch ((hdspm->settings_register &
2782 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2783 case 0: return 0; /* WC */
2784 case 3: return 1; /* ADAT */
2785 case 1: return 2; /* AES */
2786 case 2: return 3; /* SPDIF */
2787 case 9: return 4; /* TCO */
2788 case 10: return 5; /* SYNC_IN */
2789 }
2790 } else {
2791 switch ((hdspm->settings_register &
2792 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2793 case 0: return 0; /* WC */
2794 case 3: return 1; /* ADAT */
2795 case 1: return 2; /* AES */
2796 case 2: return 3; /* SPDIF */
2797 case 10: return 4; /* SYNC_IN */
2798 }
2799 }
2800
2801 break;
763f356c
TI		 2802 }
2803
0dca1793 2804 return -1;
763f356c
TI		 2805}
2806
0dca1793 2807
ddcecf6b 2808/*
0dca1793
AK		 2809 * Set the preferred sync reference to <pref>. The semantics
2810 * of <pref> are depending on the card type, see the comments
2811 * for clarification.
ddcecf6b 2812 */
98274f07 2813static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref)
763f356c 2814{
0dca1793 2815 int p = 0;
763f356c 2816
0dca1793
AK		 2817 switch (hdspm->io_type) {
2818 case AES32:
2819 hdspm->control_register &= ~HDSPM_SyncRefMask;
3cee5a60 2820 switch (pref) {
0dca1793
AK		 2821 case 0: /* WC */
2822 break;
2823 case 1: /* AES 1 */
2824 hdspm->control_register |= HDSPM_SyncRef0;
2825 break;
2826 case 2: /* AES 2 */
2827 hdspm->control_register |= HDSPM_SyncRef1;
2828 break;
2829 case 3: /* AES 3 */
2830 hdspm->control_register |=
2831 HDSPM_SyncRef1+HDSPM_SyncRef0;
2832 break;
2833 case 4: /* AES 4 */
2834 hdspm->control_register |= HDSPM_SyncRef2;
2835 break;
2836 case 5: /* AES 5 */
2837 hdspm->control_register |=
2838 HDSPM_SyncRef2+HDSPM_SyncRef0;
2839 break;
2840 case 6: /* AES 6 */
2841 hdspm->control_register |=
2842 HDSPM_SyncRef2+HDSPM_SyncRef1;
2843 break;
2844 case 7: /* AES 7 */
2845 hdspm->control_register |=
2846 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0;
3cee5a60 2847 break;
0dca1793
AK		 2848 case 8: /* AES 8 */
2849 hdspm->control_register |= HDSPM_SyncRef3;
2850 break;
2851 case 9: /* TCO */
2852 hdspm->control_register |=
2853 HDSPM_SyncRef3+HDSPM_SyncRef0;
3cee5a60
RB		 2854 break;
2855 default:
2856 return -1;
2857 }
0dca1793
AK		 2858
2859 break;
2860
2861 case MADI:
2862 case MADIface:
2863 hdspm->control_register &= ~HDSPM_SyncRefMask;
2864 if (hdspm->tco) {
2865 switch (pref) {
2866 case 0: /* WC */
2867 break;
2868 case 1: /* MADI */
2869 hdspm->control_register |= HDSPM_SyncRef0;
2870 break;
2871 case 2: /* TCO */
2872 hdspm->control_register |= HDSPM_SyncRef1;
2873 break;
2874 case 3: /* SYNC_IN */
2875 hdspm->control_register |=
2876 HDSPM_SyncRef0+HDSPM_SyncRef1;
2877 break;
2878 default:
2879 return -1;
2880 }
2881 } else {
2882 switch (pref) {
2883 case 0: /* WC */
2884 break;
2885 case 1: /* MADI */
2886 hdspm->control_register |= HDSPM_SyncRef0;
2887 break;
2888 case 2: /* SYNC_IN */
2889 hdspm->control_register |=
2890 HDSPM_SyncRef0+HDSPM_SyncRef1;
2891 break;
2892 default:
2893 return -1;
2894 }
2895 }
2896
2897 break;
2898
2899 case RayDAT:
2900 if (hdspm->tco) {
2901 switch (pref) {
2902 case 0: p = 0; break; /* WC */
2903 case 1: p = 3; break; /* ADAT 1 */
2904 case 2: p = 4; break; /* ADAT 2 */
2905 case 3: p = 5; break; /* ADAT 3 */
2906 case 4: p = 6; break; /* ADAT 4 */
2907 case 5: p = 1; break; /* AES */
2908 case 6: p = 2; break; /* SPDIF */
2909 case 7: p = 9; break; /* TCO */
2910 case 8: p = 10; break; /* SYNC_IN */
2911 default: return -1;
2912 }
2913 } else {
2914 switch (pref) {
2915 case 0: p = 0; break; /* WC */
2916 case 1: p = 3; break; /* ADAT 1 */
2917 case 2: p = 4; break; /* ADAT 2 */
2918 case 3: p = 5; break; /* ADAT 3 */
2919 case 4: p = 6; break; /* ADAT 4 */
2920 case 5: p = 1; break; /* AES */
2921 case 6: p = 2; break; /* SPDIF */
2922 case 7: p = 10; break; /* SYNC_IN */
2923 default: return -1;
2924 }
2925 }
2926 break;
2927
2928 case AIO:
2929 if (hdspm->tco) {
2930 switch (pref) {
2931 case 0: p = 0; break; /* WC */
2932 case 1: p = 3; break; /* ADAT */
2933 case 2: p = 1; break; /* AES */
2934 case 3: p = 2; break; /* SPDIF */
2935 case 4: p = 9; break; /* TCO */
2936 case 5: p = 10; break; /* SYNC_IN */
2937 default: return -1;
2938 }
2939 } else {
2940 switch (pref) {
2941 case 0: p = 0; break; /* WC */
2942 case 1: p = 3; break; /* ADAT */
2943 case 2: p = 1; break; /* AES */
2944 case 3: p = 2; break; /* SPDIF */
2945 case 4: p = 10; break; /* SYNC_IN */
2946 default: return -1;
2947 }
2948 }
2949 break;
763f356c 2950 }
0dca1793
AK		 2951
2952 switch (hdspm->io_type) {
2953 case RayDAT:
2954 case AIO:
2955 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask;
2956 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p;
2957 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2958 break;
2959
2960 case MADI:
2961 case MADIface:
2962 case AES32:
2963 hdspm_write(hdspm, HDSPM_controlRegister,
2964 hdspm->control_register);
2965 }
2966
763f356c
TI		 2967 return 0;
2968}
2969
0dca1793 2970
98274f07
TI		 2971static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol,
2972 struct snd_ctl_elem_info *uinfo)
763f356c 2973{
3cee5a60 2974 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c 2975
eb0d4dbf 2976 snd_ctl_enum_info(uinfo, 1, hdspm->texts_autosync_items, hdspm->texts_autosync);
3cee5a60 2977
763f356c
TI		 2978 return 0;
2979}
2980
98274f07
TI		 2981static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol,
2982 struct snd_ctl_elem_value *ucontrol)
763f356c 2983{
98274f07 2984 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
0dca1793 2985 int psf = hdspm_pref_sync_ref(hdspm);
763f356c 2986
0dca1793
AK		 2987 if (psf >= 0) {
2988 ucontrol->value.enumerated.item[0] = psf;
2989 return 0;
2990 }
2991
2992 return -1;
763f356c
TI		 2993}
2994
98274f07
TI		 2995static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol,
2996 struct snd_ctl_elem_value *ucontrol)
763f356c 2997{
98274f07 2998 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
0dca1793 2999 int val, change = 0;
763f356c
TI		 3000
3001 if (!snd_hdspm_use_is_exclusive(hdspm))
3002 return -EBUSY;
3003
0dca1793
AK		 3004 val = ucontrol->value.enumerated.item[0];
3005
3006 if (val < 0)
3007 val = 0;
3008 else if (val >= hdspm->texts_autosync_items)
3009 val = hdspm->texts_autosync_items-1;
763f356c
TI		 3010
3011 spin_lock_irq(&hdspm->lock);
0dca1793
AK		 3012 if (val != hdspm_pref_sync_ref(hdspm))
3013 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0;
3014
763f356c
TI		 3015 spin_unlock_irq(&hdspm->lock);
3016 return change;
3017}
3018
0dca1793 3019
763f356c 3020#define HDSPM_AUTOSYNC_REF(xname, xindex) \
f27a64f9
AK		 3021{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3022 .name = xname, \
3023 .index = xindex, \
3024 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
3025 .info = snd_hdspm_info_autosync_ref, \
3026 .get = snd_hdspm_get_autosync_ref, \
763f356c
TI		 3027}
3028
0dca1793 3029static int hdspm_autosync_ref(struct hdspm *hdspm)
763f356c 3030{
2d60fc7f 3031 /* This looks at the autosync selected sync reference */
0dca1793 3032 if (AES32 == hdspm->io_type) {
2d60fc7f 3033
3cee5a60 3034 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
2d60fc7f
AK		 3035 unsigned int syncref = (status >> HDSPM_AES32_syncref_bit) & 0xF;
3036 if ((syncref >= HDSPM_AES32_AUTOSYNC_FROM_WORD) &&
3037 (syncref <= HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN)) {
3cee5a60 3038 return syncref;
2d60fc7f 3039 }
3cee5a60 3040 return HDSPM_AES32_AUTOSYNC_FROM_NONE;
2d60fc7f 3041
0dca1793 3042 } else if (MADI == hdspm->io_type) {
3cee5a60 3043
2d60fc7f 3044 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3cee5a60
RB		 3045 switch (status2 & HDSPM_SelSyncRefMask) {
3046 case HDSPM_SelSyncRef_WORD:
3047 return HDSPM_AUTOSYNC_FROM_WORD;
3048 case HDSPM_SelSyncRef_MADI:
3049 return HDSPM_AUTOSYNC_FROM_MADI;
0dca1793
AK		 3050 case HDSPM_SelSyncRef_TCO:
3051 return HDSPM_AUTOSYNC_FROM_TCO;
3052 case HDSPM_SelSyncRef_SyncIn:
3053 return HDSPM_AUTOSYNC_FROM_SYNC_IN;
3cee5a60
RB		 3054 case HDSPM_SelSyncRef_NVALID:
3055 return HDSPM_AUTOSYNC_FROM_NONE;
3056 default:
e71b95ad 3057 return HDSPM_AUTOSYNC_FROM_NONE;
3cee5a60 3058 }
763f356c 3059
763f356c 3060 }
0dca1793 3061 return 0;
763f356c
TI		 3062}
3063
0dca1793 3064
98274f07
TI		 3065static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol,
3066 struct snd_ctl_elem_info *uinfo)
763f356c 3067{
3cee5a60 3068 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c 3069
0dca1793 3070 if (AES32 == hdspm->io_type) {
04659f9e 3071 static const char *const texts[] = { "WordClock", "AES1", "AES2", "AES3",
db2d1a91 3072 "AES4", "AES5", "AES6", "AES7", "AES8", "TCO", "Sync In", "None"};
3cee5a60 3073
04659f9e 3074 ENUMERATED_CTL_INFO(uinfo, texts);
0dca1793 3075 } else if (MADI == hdspm->io_type) {
04659f9e 3076 static const char *const texts[] = {"Word Clock", "MADI", "TCO",
0dca1793 3077 "Sync In", "None" };
3cee5a60 3078
04659f9e 3079 ENUMERATED_CTL_INFO(uinfo, texts);
3cee5a60 3080 }
763f356c
TI		 3081 return 0;
3082}
3083
98274f07
TI		 3084static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol,
3085 struct snd_ctl_elem_value *ucontrol)
763f356c 3086{
98274f07 3087 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c 3088
6534599d 3089 ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm);
763f356c
TI		 3090 return 0;
3091}
3092
f99c7881
AK		 3093
3094
3095#define HDSPM_TCO_VIDEO_INPUT_FORMAT(xname, xindex) \
3096{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3097 .name = xname, \
3098 .access = SNDRV_CTL_ELEM_ACCESS_READ |\
3099 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3100 .info = snd_hdspm_info_tco_video_input_format, \
3101 .get = snd_hdspm_get_tco_video_input_format, \
3102}
3103
3104static int snd_hdspm_info_tco_video_input_format(struct snd_kcontrol *kcontrol,
3105 struct snd_ctl_elem_info *uinfo)
3106{
38816545 3107 static const char *const texts[] = {"No video", "NTSC", "PAL"};
f99c7881
AK		 3108 ENUMERATED_CTL_INFO(uinfo, texts);
3109 return 0;
3110}
3111
3112static int snd_hdspm_get_tco_video_input_format(struct snd_kcontrol *kcontrol,
3113 struct snd_ctl_elem_value *ucontrol)
3114{
3115 u32 status;
3116 int ret = 0;
3117
3118 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3119 status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3120 switch (status & (HDSPM_TCO1_Video_Input_Format_NTSC |
3121 HDSPM_TCO1_Video_Input_Format_PAL)) {
3122 case HDSPM_TCO1_Video_Input_Format_NTSC:
3123 /* ntsc */
3124 ret = 1;
3125 break;
3126 case HDSPM_TCO1_Video_Input_Format_PAL:
3127 /* pal */
3128 ret = 2;
3129 break;
3130 default:
3131 /* no video */
3132 ret = 0;
3133 break;
3134 }
3135 ucontrol->value.enumerated.item[0] = ret;
3136 return 0;
3137}
3138
3139
3140
3141#define HDSPM_TCO_LTC_FRAMES(xname, xindex) \
3142{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3143 .name = xname, \
3144 .access = SNDRV_CTL_ELEM_ACCESS_READ |\
3145 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3146 .info = snd_hdspm_info_tco_ltc_frames, \
3147 .get = snd_hdspm_get_tco_ltc_frames, \
3148}
3149
3150static int snd_hdspm_info_tco_ltc_frames(struct snd_kcontrol *kcontrol,
3151 struct snd_ctl_elem_info *uinfo)
3152{
38816545 3153 static const char *const texts[] = {"No lock", "24 fps", "25 fps", "29.97 fps",
f99c7881
AK		 3154 "30 fps"};
3155 ENUMERATED_CTL_INFO(uinfo, texts);
3156 return 0;
3157}
3158
3159static int hdspm_tco_ltc_frames(struct hdspm *hdspm)
3160{
3161 u32 status;
3162 int ret = 0;
3163
3164 status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3165 if (status & HDSPM_TCO1_LTC_Input_valid) {
3166 switch (status & (HDSPM_TCO1_LTC_Format_LSB |
3167 HDSPM_TCO1_LTC_Format_MSB)) {
3168 case 0:
3169 /* 24 fps */
1568b880 3170 ret = fps_24;
f99c7881
AK		 3171 break;
3172 case HDSPM_TCO1_LTC_Format_LSB:
3173 /* 25 fps */
1568b880 3174 ret = fps_25;
f99c7881
AK		 3175 break;
3176 case HDSPM_TCO1_LTC_Format_MSB:
1568b880
AK		 3177 /* 29.97 fps */
3178 ret = fps_2997;
f99c7881
AK		 3179 break;
3180 default:
3181 /* 30 fps */
1568b880 3182 ret = fps_30;
f99c7881
AK		 3183 break;
3184 }
3185 }
3186
3187 return ret;
3188}
3189
3190static int snd_hdspm_get_tco_ltc_frames(struct snd_kcontrol *kcontrol,
3191 struct snd_ctl_elem_value *ucontrol)
3192{
3193 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3194
3195 ucontrol->value.enumerated.item[0] = hdspm_tco_ltc_frames(hdspm);
3196 return 0;
3197}
3198
bf0ff87b
AK		 3199#define HDSPM_TOGGLE_SETTING(xname, xindex) \
3200{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3201 .name = xname, \
3202 .private_value = xindex, \
3203 .info = snd_hdspm_info_toggle_setting, \
3204 .get = snd_hdspm_get_toggle_setting, \
3205 .put = snd_hdspm_put_toggle_setting \
3206}
3207
3208static int hdspm_toggle_setting(struct hdspm *hdspm, u32 regmask)
3209{
ce13f3f3
AK		 3210 u32 reg;
3211
3212 if (hdspm_is_raydat_or_aio(hdspm))
3213 reg = hdspm->settings_register;
3214 else
3215 reg = hdspm->control_register;
3216
3217 return (reg & regmask) ? 1 : 0;
bf0ff87b
AK		 3218}
3219
3220static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out)
3221{
ce13f3f3
AK		 3222 u32 *reg;
3223 u32 target_reg;
3224
3225 if (hdspm_is_raydat_or_aio(hdspm)) {
3226 reg = &(hdspm->settings_register);
3227 target_reg = HDSPM_WR_SETTINGS;
3228 } else {
3229 reg = &(hdspm->control_register);
3230 target_reg = HDSPM_controlRegister;
3231 }
3232
bf0ff87b 3233 if (out)
ce13f3f3 3234 *reg |= regmask;
bf0ff87b 3235 else
ce13f3f3
AK		 3236 *reg &= ~regmask;
3237
3238 hdspm_write(hdspm, target_reg, *reg);
bf0ff87b
AK		 3239
3240 return 0;
3241}
3242
3243#define snd_hdspm_info_toggle_setting snd_ctl_boolean_mono_info
3244
3245static int snd_hdspm_get_toggle_setting(struct snd_kcontrol *kcontrol,
3246 struct snd_ctl_elem_value *ucontrol)
3247{
3248 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3249 u32 regmask = kcontrol->private_value;
3250
3251 spin_lock_irq(&hdspm->lock);
3252 ucontrol->value.integer.value[0] = hdspm_toggle_setting(hdspm, regmask);
3253 spin_unlock_irq(&hdspm->lock);
3254 return 0;
3255}
3256
3257static int snd_hdspm_put_toggle_setting(struct snd_kcontrol *kcontrol,
3258 struct snd_ctl_elem_value *ucontrol)
3259{
3260 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3261 u32 regmask = kcontrol->private_value;
3262 int change;
3263 unsigned int val;
3264
3265 if (!snd_hdspm_use_is_exclusive(hdspm))
3266 return -EBUSY;
3267 val = ucontrol->value.integer.value[0] & 1;
3268 spin_lock_irq(&hdspm->lock);
3269 change = (int) val != hdspm_toggle_setting(hdspm, regmask);
3270 hdspm_set_toggle_setting(hdspm, regmask, val);
3271 spin_unlock_irq(&hdspm->lock);
3272 return change;
3273}
3274
3cee5a60 3275#define HDSPM_INPUT_SELECT(xname, xindex) \
f27a64f9
AK		 3276{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3277 .name = xname, \
3278 .index = xindex, \
3279 .info = snd_hdspm_info_input_select, \
3280 .get = snd_hdspm_get_input_select, \
3281 .put = snd_hdspm_put_input_select \
3cee5a60
RB		 3282}
3283
3284static int hdspm_input_select(struct hdspm * hdspm)
3285{
3286 return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0;
3287}
3288
3289static int hdspm_set_input_select(struct hdspm * hdspm, int out)
3290{
3291 if (out)
3292 hdspm->control_register |= HDSPM_InputSelect0;
3293 else
3294 hdspm->control_register &= ~HDSPM_InputSelect0;
3295 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3296
3297 return 0;
3298}
3299
3300static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol,
3301 struct snd_ctl_elem_info *uinfo)
3302{
38816545 3303 static const char *const texts[] = { "optical", "coaxial" };
e5b7b1fe 3304 ENUMERATED_CTL_INFO(uinfo, texts);
3cee5a60
RB		 3305 return 0;
3306}
3307
3308static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol,
3309 struct snd_ctl_elem_value *ucontrol)
3310{
3311 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3312
3313 spin_lock_irq(&hdspm->lock);
3314 ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm);
3315 spin_unlock_irq(&hdspm->lock);
3316 return 0;
3317}
3318
3319static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol,
3320 struct snd_ctl_elem_value *ucontrol)
3321{
3322 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3323 int change;
3324 unsigned int val;
3325
3326 if (!snd_hdspm_use_is_exclusive(hdspm))
3327 return -EBUSY;
3328 val = ucontrol->value.integer.value[0] & 1;
3329 spin_lock_irq(&hdspm->lock);
3330 change = (int) val != hdspm_input_select(hdspm);
3331 hdspm_set_input_select(hdspm, val);
3332 spin_unlock_irq(&hdspm->lock);
3333 return change;
3334}
3335
0dca1793 3336
3cee5a60 3337#define HDSPM_DS_WIRE(xname, xindex) \
f27a64f9
AK		 3338{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3339 .name = xname, \
3340 .index = xindex, \
3341 .info = snd_hdspm_info_ds_wire, \
3342 .get = snd_hdspm_get_ds_wire, \
3343 .put = snd_hdspm_put_ds_wire \
3cee5a60
RB		 3344}
3345
3346static int hdspm_ds_wire(struct hdspm * hdspm)
763f356c 3347{
3cee5a60 3348 return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0;
763f356c
TI		 3349}
3350
3cee5a60 3351static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds)
763f356c 3352{
3cee5a60
RB		 3353 if (ds)
3354 hdspm->control_register |= HDSPM_DS_DoubleWire;
763f356c 3355 else
3cee5a60 3356 hdspm->control_register &= ~HDSPM_DS_DoubleWire;
763f356c
TI		 3357 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3358
3359 return 0;
3360}
3361
3cee5a60
RB		 3362static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol,
3363 struct snd_ctl_elem_info *uinfo)
763f356c 3364{
38816545 3365 static const char *const texts[] = { "Single", "Double" };
e5b7b1fe 3366 ENUMERATED_CTL_INFO(uinfo, texts);
763f356c
TI		 3367 return 0;
3368}
3369
3cee5a60
RB		 3370static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol,
3371 struct snd_ctl_elem_value *ucontrol)
763f356c 3372{
98274f07 3373 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c
TI		 3374
3375 spin_lock_irq(&hdspm->lock);
3cee5a60 3376 ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm);
763f356c
TI		 3377 spin_unlock_irq(&hdspm->lock);
3378 return 0;
3379}
3380
3cee5a60
RB		 3381static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol,
3382 struct snd_ctl_elem_value *ucontrol)
763f356c 3383{
98274f07 3384 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c
TI		 3385 int change;
3386 unsigned int val;
3387
3388 if (!snd_hdspm_use_is_exclusive(hdspm))
3389 return -EBUSY;
3390 val = ucontrol->value.integer.value[0] & 1;
3391 spin_lock_irq(&hdspm->lock);
3cee5a60
RB		 3392 change = (int) val != hdspm_ds_wire(hdspm);
3393 hdspm_set_ds_wire(hdspm, val);
763f356c
TI		 3394 spin_unlock_irq(&hdspm->lock);
3395 return change;
3396}
3397
0dca1793 3398
3cee5a60 3399#define HDSPM_QS_WIRE(xname, xindex) \
f27a64f9
AK		 3400{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3401 .name = xname, \
3402 .index = xindex, \
3403 .info = snd_hdspm_info_qs_wire, \
3404 .get = snd_hdspm_get_qs_wire, \
3405 .put = snd_hdspm_put_qs_wire \
763f356c
TI		 3406}
3407
3cee5a60 3408static int hdspm_qs_wire(struct hdspm * hdspm)
763f356c 3409{
3cee5a60
RB		 3410 if (hdspm->control_register & HDSPM_QS_DoubleWire)
3411 return 1;
3412 if (hdspm->control_register & HDSPM_QS_QuadWire)
3413 return 2;
3414 return 0;
763f356c
TI		 3415}
3416
3cee5a60 3417static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode)
763f356c 3418{
3cee5a60
RB		 3419 hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire);
3420 switch (mode) {
3421 case 0:
3422 break;
3423 case 1:
3424 hdspm->control_register |= HDSPM_QS_DoubleWire;
3425 break;
3426 case 2:
3427 hdspm->control_register |= HDSPM_QS_QuadWire;
3428 break;
3429 }
763f356c
TI		 3430 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3431
3432 return 0;
3433}
3434
3cee5a60 3435static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol,
98274f07 3436 struct snd_ctl_elem_info *uinfo)
763f356c 3437{
38816545 3438 static const char *const texts[] = { "Single", "Double", "Quad" };
e5b7b1fe 3439 ENUMERATED_CTL_INFO(uinfo, texts);
763f356c
TI		 3440 return 0;
3441}
3442
3cee5a60 3443static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol,
98274f07 3444 struct snd_ctl_elem_value *ucontrol)
763f356c 3445{
98274f07 3446 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c
TI		 3447
3448 spin_lock_irq(&hdspm->lock);
3cee5a60 3449 ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm);
763f356c
TI		 3450 spin_unlock_irq(&hdspm->lock);
3451 return 0;
3452}
3453
3cee5a60 3454static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol,
98274f07 3455 struct snd_ctl_elem_value *ucontrol)
763f356c 3456{
98274f07 3457 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c 3458 int change;
3cee5a60 3459 int val;
763f356c
TI		 3460
3461 if (!snd_hdspm_use_is_exclusive(hdspm))
3462 return -EBUSY;
3cee5a60
RB		 3463 val = ucontrol->value.integer.value[0];
3464 if (val < 0)
3465 val = 0;
3466 if (val > 2)
3467 val = 2;
763f356c 3468 spin_lock_irq(&hdspm->lock);
ef5fa1a4 3469 change = val != hdspm_qs_wire(hdspm);
3cee5a60 3470 hdspm_set_qs_wire(hdspm, val);
763f356c
TI		 3471 spin_unlock_irq(&hdspm->lock);
3472 return change;
3473}
3474
acf14767
AK		 3475#define HDSPM_CONTROL_TRISTATE(xname, xindex) \
3476{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3477 .name = xname, \
3478 .private_value = xindex, \
3479 .info = snd_hdspm_info_tristate, \
3480 .get = snd_hdspm_get_tristate, \
3481 .put = snd_hdspm_put_tristate \
3482}
3483
3484static int hdspm_tristate(struct hdspm *hdspm, u32 regmask)
3485{
3486 u32 reg = hdspm->settings_register & (regmask * 3);
3487 return reg / regmask;
3488}
3489
3490static int hdspm_set_tristate(struct hdspm *hdspm, int mode, u32 regmask)
3491{
3492 hdspm->settings_register &= ~(regmask * 3);
3493 hdspm->settings_register |= (regmask * mode);
3494 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
3495
3496 return 0;
3497}
3498
3499static int snd_hdspm_info_tristate(struct snd_kcontrol *kcontrol,
3500 struct snd_ctl_elem_info *uinfo)
3501{
3502 u32 regmask = kcontrol->private_value;
3503
38816545
AK		 3504 static const char *const texts_spdif[] = { "Optical", "Coaxial", "Internal" };
3505 static const char *const texts_levels[] = { "Hi Gain", "+4 dBu", "-10 dBV" };
acf14767
AK		 3506
3507 switch (regmask) {
3508 case HDSPM_c0_Input0:
3509 ENUMERATED_CTL_INFO(uinfo, texts_spdif);
3510 break;
3511 default:
3512 ENUMERATED_CTL_INFO(uinfo, texts_levels);
3513 break;
3514 }
3515 return 0;
3516}
3517
3518static int snd_hdspm_get_tristate(struct snd_kcontrol *kcontrol,
3519 struct snd_ctl_elem_value *ucontrol)
3520{
3521 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3522 u32 regmask = kcontrol->private_value;
3523
3524 spin_lock_irq(&hdspm->lock);
3525 ucontrol->value.enumerated.item[0] = hdspm_tristate(hdspm, regmask);
3526 spin_unlock_irq(&hdspm->lock);
3527 return 0;
3528}
3529
3530static int snd_hdspm_put_tristate(struct snd_kcontrol *kcontrol,
3531 struct snd_ctl_elem_value *ucontrol)
3532{
3533 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3534 u32 regmask = kcontrol->private_value;
3535 int change;
3536 int val;
3537
3538 if (!snd_hdspm_use_is_exclusive(hdspm))
3539 return -EBUSY;
3540 val = ucontrol->value.integer.value[0];
3541 if (val < 0)
3542 val = 0;
3543 if (val > 2)
3544 val = 2;
3545
3546 spin_lock_irq(&hdspm->lock);
3547 change = val != hdspm_tristate(hdspm, regmask);
3548 hdspm_set_tristate(hdspm, val, regmask);
3549 spin_unlock_irq(&hdspm->lock);
3550 return change;
3551}
3552
700d1ef3
AK		 3553#define HDSPM_MADI_SPEEDMODE(xname, xindex) \
3554{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3555 .name = xname, \
3556 .index = xindex, \
3557 .info = snd_hdspm_info_madi_speedmode, \
3558 .get = snd_hdspm_get_madi_speedmode, \
3559 .put = snd_hdspm_put_madi_speedmode \
3560}
3561
3562static int hdspm_madi_speedmode(struct hdspm *hdspm)
3563{
3564 if (hdspm->control_register & HDSPM_QuadSpeed)
3565 return 2;
3566 if (hdspm->control_register & HDSPM_DoubleSpeed)
3567 return 1;
3568 return 0;
3569}
3570
3571static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode)
3572{
3573 hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed);
3574 switch (mode) {
3575 case 0:
3576 break;
3577 case 1:
3578 hdspm->control_register |= HDSPM_DoubleSpeed;
3579 break;
3580 case 2:
3581 hdspm->control_register |= HDSPM_QuadSpeed;
3582 break;
3583 }
3584 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3585
3586 return 0;
3587}
3588
3589static int snd_hdspm_info_madi_speedmode(struct snd_kcontrol *kcontrol,
3590 struct snd_ctl_elem_info *uinfo)
3591{
38816545 3592 static const char *const texts[] = { "Single", "Double", "Quad" };
e5b7b1fe 3593 ENUMERATED_CTL_INFO(uinfo, texts);
700d1ef3
AK		 3594 return 0;
3595}
3596
3597static int snd_hdspm_get_madi_speedmode(struct snd_kcontrol *kcontrol,
3598 struct snd_ctl_elem_value *ucontrol)
3599{
3600 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3601
3602 spin_lock_irq(&hdspm->lock);
3603 ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm);
3604 spin_unlock_irq(&hdspm->lock);
3605 return 0;
3606}
3607
3608static int snd_hdspm_put_madi_speedmode(struct snd_kcontrol *kcontrol,
3609 struct snd_ctl_elem_value *ucontrol)
3610{
3611 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3612 int change;
3613 int val;
3614
3615 if (!snd_hdspm_use_is_exclusive(hdspm))
3616 return -EBUSY;
3617 val = ucontrol->value.integer.value[0];
3618 if (val < 0)
3619 val = 0;
3620 if (val > 2)
3621 val = 2;
3622 spin_lock_irq(&hdspm->lock);
3623 change = val != hdspm_madi_speedmode(hdspm);
3624 hdspm_set_madi_speedmode(hdspm, val);
3625 spin_unlock_irq(&hdspm->lock);
3626 return change;
3627}
763f356c
TI		 3628
3629#define HDSPM_MIXER(xname, xindex) \
f27a64f9
AK		 3630{ .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3631 .name = xname, \
3632 .index = xindex, \
3633 .device = 0, \
3634 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3635 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3636 .info = snd_hdspm_info_mixer, \
3637 .get = snd_hdspm_get_mixer, \
3638 .put = snd_hdspm_put_mixer \
763f356c
TI		 3639}
3640
98274f07
TI		 3641static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol,
3642 struct snd_ctl_elem_info *uinfo)
763f356c
TI		 3643{
3644 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3645 uinfo->count = 3;
3646 uinfo->value.integer.min = 0;
3647 uinfo->value.integer.max = 65535;
3648 uinfo->value.integer.step = 1;
3649 return 0;
3650}
3651
98274f07
TI		 3652static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol,
3653 struct snd_ctl_elem_value *ucontrol)
763f356c 3654{
98274f07 3655 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c
TI		 3656 int source;
3657 int destination;
3658
3659 source = ucontrol->value.integer.value[0];
3660 if (source < 0)
3661 source = 0;
3662 else if (source >= 2 * HDSPM_MAX_CHANNELS)
3663 source = 2 * HDSPM_MAX_CHANNELS - 1;
3664
3665 destination = ucontrol->value.integer.value[1];
3666 if (destination < 0)
3667 destination = 0;
3668 else if (destination >= HDSPM_MAX_CHANNELS)
3669 destination = HDSPM_MAX_CHANNELS - 1;
3670
3671 spin_lock_irq(&hdspm->lock);
3672 if (source >= HDSPM_MAX_CHANNELS)
3673 ucontrol->value.integer.value[2] =
3674 hdspm_read_pb_gain(hdspm, destination,
3675 source - HDSPM_MAX_CHANNELS);
3676 else
3677 ucontrol->value.integer.value[2] =
3678 hdspm_read_in_gain(hdspm, destination, source);
3679
3680 spin_unlock_irq(&hdspm->lock);
3681
3682 return 0;
3683}
3684
98274f07
TI		 3685static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol,
3686 struct snd_ctl_elem_value *ucontrol)
763f356c 3687{
98274f07 3688 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c
TI		 3689 int change;
3690 int source;
3691 int destination;
3692 int gain;
3693
3694 if (!snd_hdspm_use_is_exclusive(hdspm))
3695 return -EBUSY;
3696
3697 source = ucontrol->value.integer.value[0];
3698 destination = ucontrol->value.integer.value[1];
3699
3700 if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS)
3701 return -1;
3702 if (destination < 0 || destination >= HDSPM_MAX_CHANNELS)
3703 return -1;
3704
3705 gain = ucontrol->value.integer.value[2];
3706
3707 spin_lock_irq(&hdspm->lock);
3708
3709 if (source >= HDSPM_MAX_CHANNELS)
3710 change = gain != hdspm_read_pb_gain(hdspm, destination,
3711 source -
3712 HDSPM_MAX_CHANNELS);
3713 else
ef5fa1a4
TI		 3714 change = gain != hdspm_read_in_gain(hdspm, destination,
3715 source);
763f356c
TI		 3716
3717 if (change) {
3718 if (source >= HDSPM_MAX_CHANNELS)
3719 hdspm_write_pb_gain(hdspm, destination,
3720 source - HDSPM_MAX_CHANNELS,
3721 gain);
3722 else
3723 hdspm_write_in_gain(hdspm, destination, source,
3724 gain);
3725 }
3726 spin_unlock_irq(&hdspm->lock);
3727
3728 return change;
3729}
3730
3731/* The simple mixer control(s) provide gain control for the
3732 basic 1:1 mappings of playback streams to output
0dca1793 3733 streams.
763f356c
TI		 3734*/
3735
3736#define HDSPM_PLAYBACK_MIXER \
f27a64f9
AK		 3737{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3738 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \
3739 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3740 .info = snd_hdspm_info_playback_mixer, \
3741 .get = snd_hdspm_get_playback_mixer, \
3742 .put = snd_hdspm_put_playback_mixer \
763f356c
TI		 3743}
3744
98274f07
TI		 3745static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol,
3746 struct snd_ctl_elem_info *uinfo)
763f356c
TI		 3747{
3748 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3749 uinfo->count = 1;
3750 uinfo->value.integer.min = 0;
0dca1793 3751 uinfo->value.integer.max = 64;
763f356c
TI		 3752 uinfo->value.integer.step = 1;
3753 return 0;
3754}
3755
98274f07
TI		 3756static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol,
3757 struct snd_ctl_elem_value *ucontrol)
763f356c 3758{
98274f07 3759 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c 3760 int channel;
763f356c
TI		 3761
3762 channel = ucontrol->id.index - 1;
3763
da3cec35
TI		 3764 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3765 return -EINVAL;
763f356c 3766
763f356c
TI		 3767 spin_lock_irq(&hdspm->lock);
3768 ucontrol->value.integer.value[0] =
0dca1793 3769 (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN;
763f356c
TI		 3770 spin_unlock_irq(&hdspm->lock);
3771
763f356c
TI		 3772 return 0;
3773}
3774
98274f07
TI		 3775static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol,
3776 struct snd_ctl_elem_value *ucontrol)
763f356c 3777{
98274f07 3778 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c
TI		 3779 int change;
3780 int channel;
763f356c
TI		 3781 int gain;
3782
3783 if (!snd_hdspm_use_is_exclusive(hdspm))
3784 return -EBUSY;
3785
3786 channel = ucontrol->id.index - 1;
3787
da3cec35
TI		 3788 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3789 return -EINVAL;
763f356c 3790
0dca1793 3791 gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64;
763f356c
TI		 3792
3793 spin_lock_irq(&hdspm->lock);
3794 change =
0dca1793
AK		 3795 gain != hdspm_read_pb_gain(hdspm, channel,
3796 channel);
763f356c 3797 if (change)
0dca1793 3798 hdspm_write_pb_gain(hdspm, channel, channel,
763f356c
TI		 3799 gain);
3800 spin_unlock_irq(&hdspm->lock);
3801 return change;
3802}
3803
0dca1793
AK		 3804#define HDSPM_SYNC_CHECK(xname, xindex) \
3805{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3806 .name = xname, \
3807 .private_value = xindex, \
3808 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3809 .info = snd_hdspm_info_sync_check, \
3810 .get = snd_hdspm_get_sync_check \
763f356c
TI		 3811}
3812
34542213
AK		 3813#define HDSPM_TCO_LOCK_CHECK(xname, xindex) \
3814{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3815 .name = xname, \
3816 .private_value = xindex, \
3817 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3818 .info = snd_hdspm_tco_info_lock_check, \
3819 .get = snd_hdspm_get_sync_check \
3820}
3821
3822
0dca1793 3823
98274f07
TI		 3824static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol,
3825 struct snd_ctl_elem_info *uinfo)
763f356c 3826{
38816545 3827 static const char *const texts[] = { "No Lock", "Lock", "Sync", "N/A" };
e5b7b1fe 3828 ENUMERATED_CTL_INFO(uinfo, texts);
763f356c
TI		 3829 return 0;
3830}
3831
34542213
AK		 3832static int snd_hdspm_tco_info_lock_check(struct snd_kcontrol *kcontrol,
3833 struct snd_ctl_elem_info *uinfo)
3834{
38816545 3835 static const char *const texts[] = { "No Lock", "Lock" };
34542213
AK		 3836 ENUMERATED_CTL_INFO(uinfo, texts);
3837 return 0;
3838}
3839
0dca1793 3840static int hdspm_wc_sync_check(struct hdspm *hdspm)
763f356c 3841{
0dca1793
AK		 3842 int status, status2;
3843
3844 switch (hdspm->io_type) {
3845 case AES32:
3846 status = hdspm_read(hdspm, HDSPM_statusRegister);
56bde0f3
AS		 3847 if (status & HDSPM_AES32_wcLock) {
3848 if (status & HDSPM_AES32_wcSync)
3849 return 2;
3850 else
3851 return 1;
3852 }
3cee5a60 3853 return 0;
0dca1793
AK		 3854 break;
3855
3856 case MADI:
3857 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3cee5a60
RB		 3858 if (status2 & HDSPM_wcLock) {
3859 if (status2 & HDSPM_wcSync)
3860 return 2;
3861 else
3862 return 1;
3863 }
3864 return 0;
0dca1793 3865 break;
763f356c 3866
0dca1793
AK		 3867 case RayDAT:
3868 case AIO:
3869 status = hdspm_read(hdspm, HDSPM_statusRegister);
763f356c 3870
0dca1793
AK		 3871 if (status & 0x2000000)
3872 return 2;
3873 else if (status & 0x1000000)
3874 return 1;
3875 return 0;
763f356c 3876
0dca1793 3877 break;
763f356c 3878
0dca1793
AK		 3879 case MADIface:
3880 break;
3881 }
3882
3883
3884 return 3;
763f356c
TI		 3885}
3886
0dca1793
AK		 3887
3888static int hdspm_madi_sync_check(struct hdspm *hdspm)
763f356c
TI		 3889{
3890 int status = hdspm_read(hdspm, HDSPM_statusRegister);
3891 if (status & HDSPM_madiLock) {
3892 if (status & HDSPM_madiSync)
3893 return 2;
3894 else
3895 return 1;
3896 }
3897 return 0;
3898}
3899
763f356c 3900
0dca1793
AK		 3901static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx)
3902{
3903 int status, lock, sync;
763f356c 3904
0dca1793 3905 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
763f356c 3906
0dca1793
AK		 3907 lock = (status & (0x1<<idx)) ? 1 : 0;
3908 sync = (status & (0x100<<idx)) ? 1 : 0;
3cee5a60 3909
0dca1793 3910 if (lock && sync)
3cee5a60 3911 return 2;
0dca1793
AK		 3912 else if (lock)
3913 return 1;
3cee5a60
RB		 3914 return 0;
3915}
3916
0dca1793
AK		 3917
3918static int hdspm_sync_in_sync_check(struct hdspm *hdspm)
3919{
3920 int status, lock = 0, sync = 0;
3921
3922 switch (hdspm->io_type) {
3923 case RayDAT:
3924 case AIO:
3925 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3);
3926 lock = (status & 0x400) ? 1 : 0;
3927 sync = (status & 0x800) ? 1 : 0;
3928 break;
3929
3930 case MADI:
2e0452f5
AK		 3931 status = hdspm_read(hdspm, HDSPM_statusRegister);
3932 lock = (status & HDSPM_syncInLock) ? 1 : 0;
3933 sync = (status & HDSPM_syncInSync) ? 1 : 0;
3934 break;
3935
0dca1793
AK		 3936 case AES32:
3937 status = hdspm_read(hdspm, HDSPM_statusRegister2);
9a215f47
AK		 3938 lock = (status & 0x100000) ? 1 : 0;
3939 sync = (status & 0x200000) ? 1 : 0;
0dca1793
AK		 3940 break;
3941
3942 case MADIface:
3943 break;
3944 }
3945
3946 if (lock && sync)
3947 return 2;
3948 else if (lock)
3949 return 1;
3950
3951 return 0;
3952}
3953
3954static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx)
3955{
3956 int status2, lock, sync;
3957 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3958
3959 lock = (status2 & (0x0080 >> idx)) ? 1 : 0;
3960 sync = (status2 & (0x8000 >> idx)) ? 1 : 0;
3961
3962 if (sync)
3963 return 2;
3964 else if (lock)
3965 return 1;
3966 return 0;
3967}
3968
34542213
AK		 3969static int hdspm_tco_input_check(struct hdspm *hdspm, u32 mask)
3970{
3971 u32 status;
3972 status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3973
3974 return (status & mask) ? 1 : 0;
3975}
3976
0dca1793
AK		 3977
3978static int hdspm_tco_sync_check(struct hdspm *hdspm)
3979{
3980 int status;
3981
3982 if (hdspm->tco) {
3983 switch (hdspm->io_type) {
3984 case MADI:
b0bf5504
AK		 3985 status = hdspm_read(hdspm, HDSPM_statusRegister);
3986 if (status & HDSPM_tcoLockMadi) {
3987 if (status & HDSPM_tcoSync)
3988 return 2;
3989 else
3990 return 1;
3991 }
3992 return 0;
0dca1793
AK		 3993 case AES32:
3994 status = hdspm_read(hdspm, HDSPM_statusRegister);
b0bf5504 3995 if (status & HDSPM_tcoLockAes) {
0dca1793
AK		 3996 if (status & HDSPM_tcoSync)
3997 return 2;
3998 else
3999 return 1;
4000 }
4001 return 0;
0dca1793
AK		 4002 case RayDAT:
4003 case AIO:
4004 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
4005
4006 if (status & 0x8000000)
4007 return 2; /* Sync */
4008 if (status & 0x4000000)
4009 return 1; /* Lock */
4010 return 0; /* No signal */
0dca1793
AK		 4011
4012 default:
4013 break;
4014 }
4015 }
4016
4017 return 3; /* N/A */
4018}
4019
4020
4021static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol,
4022 struct snd_ctl_elem_value *ucontrol)
4023{
4024 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4025 int val = -1;
4026
4027 switch (hdspm->io_type) {
4028 case RayDAT:
4029 switch (kcontrol->private_value) {
4030 case 0: /* WC */
4031 val = hdspm_wc_sync_check(hdspm); break;
4032 case 7: /* TCO */
4033 val = hdspm_tco_sync_check(hdspm); break;
4034 case 8: /* SYNC IN */
4035 val = hdspm_sync_in_sync_check(hdspm); break;
4036 default:
d1a3c98d
AK		 4037 val = hdspm_s1_sync_check(hdspm,
4038 kcontrol->private_value-1);
0dca1793 4039 }
fba30fd3 4040 break;
0dca1793
AK		 4041
4042 case AIO:
4043 switch (kcontrol->private_value) {
4044 case 0: /* WC */
4045 val = hdspm_wc_sync_check(hdspm); break;
4046 case 4: /* TCO */
4047 val = hdspm_tco_sync_check(hdspm); break;
4048 case 5: /* SYNC IN */
4049 val = hdspm_sync_in_sync_check(hdspm); break;
4050 default:
1cb7dbf4
AK		 4051 val = hdspm_s1_sync_check(hdspm,
4052 kcontrol->private_value-1);
0dca1793 4053 }
fba30fd3 4054 break;
0dca1793
AK		 4055
4056 case MADI:
4057 switch (kcontrol->private_value) {
4058 case 0: /* WC */
4059 val = hdspm_wc_sync_check(hdspm); break;
4060 case 1: /* MADI */
4061 val = hdspm_madi_sync_check(hdspm); break;
4062 case 2: /* TCO */
4063 val = hdspm_tco_sync_check(hdspm); break;
4064 case 3: /* SYNC_IN */
4065 val = hdspm_sync_in_sync_check(hdspm); break;
4066 }
fba30fd3 4067 break;
0dca1793
AK		 4068
4069 case MADIface:
4070 val = hdspm_madi_sync_check(hdspm); /* MADI */
4071 break;
4072
4073 case AES32:
4074 switch (kcontrol->private_value) {
4075 case 0: /* WC */
4076 val = hdspm_wc_sync_check(hdspm); break;
4077 case 9: /* TCO */
4078 val = hdspm_tco_sync_check(hdspm); break;
4079 case 10 /* SYNC IN */:
4080 val = hdspm_sync_in_sync_check(hdspm); break;
7c4a95b5 4081 default: /* AES1 to AES8 */
0dca1793 4082 val = hdspm_aes_sync_check(hdspm,
7c4a95b5 4083 kcontrol->private_value-1);
0dca1793 4084 }
fba30fd3 4085 break;
0dca1793
AK		 4086
4087 }
4088
34542213
AK		 4089 if (hdspm->tco) {
4090 switch (kcontrol->private_value) {
4091 case 11:
4092 /* Check TCO for lock state of its current input */
4093 val = hdspm_tco_input_check(hdspm, HDSPM_TCO1_TCO_lock);
4094 break;
4095 case 12:
4096 /* Check TCO for valid time code on LTC input. */
4097 val = hdspm_tco_input_check(hdspm,
4098 HDSPM_TCO1_LTC_Input_valid);
4099 break;
4100 default:
4101 break;
4102 }
4103 }
4104
0dca1793
AK		 4105 if (-1 == val)
4106 val = 3;
4107
4108 ucontrol->value.enumerated.item[0] = val;
4109 return 0;
4110}
4111
4112
4113
ddcecf6b 4114/*
0dca1793 4115 * TCO controls
ddcecf6b 4116 */
0dca1793
AK		 4117static void hdspm_tco_write(struct hdspm *hdspm)
4118{
4119 unsigned int tc[4] = { 0, 0, 0, 0};
4120
4121 switch (hdspm->tco->input) {
4122 case 0:
4123 tc[2] |= HDSPM_TCO2_set_input_MSB;
4124 break;
4125 case 1:
4126 tc[2] |= HDSPM_TCO2_set_input_LSB;
4127 break;
4128 default:
4129 break;
4130 }
4131
4132 switch (hdspm->tco->framerate) {
4133 case 1:
4134 tc[1] |= HDSPM_TCO1_LTC_Format_LSB;
4135 break;
4136 case 2:
4137 tc[1] |= HDSPM_TCO1_LTC_Format_MSB;
4138 break;
4139 case 3:
4140 tc[1] |= HDSPM_TCO1_LTC_Format_MSB +
4141 HDSPM_TCO1_set_drop_frame_flag;
4142 break;
4143 case 4:
4144 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
4145 HDSPM_TCO1_LTC_Format_MSB;
4146 break;
4147 case 5:
4148 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
4149 HDSPM_TCO1_LTC_Format_MSB +
4150 HDSPM_TCO1_set_drop_frame_flag;
4151 break;
4152 default:
4153 break;
4154 }
4155
4156 switch (hdspm->tco->wordclock) {
4157 case 1:
4158 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB;
4159 break;
4160 case 2:
4161 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB;
4162 break;
4163 default:
4164 break;
4165 }
4166
4167 switch (hdspm->tco->samplerate) {
4168 case 1:
4169 tc[2] |= HDSPM_TCO2_set_freq;
4170 break;
4171 case 2:
4172 tc[2] |= HDSPM_TCO2_set_freq_from_app;
4173 break;
4174 default:
4175 break;
4176 }
4177
4178 switch (hdspm->tco->pull) {
4179 case 1:
4180 tc[2] |= HDSPM_TCO2_set_pull_up;
4181 break;
4182 case 2:
4183 tc[2] |= HDSPM_TCO2_set_pull_down;
4184 break;
4185 case 3:
4186 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4;
4187 break;
4188 case 4:
4189 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4;
4190 break;
4191 default:
4192 break;
4193 }
4194
4195 if (1 == hdspm->tco->term) {
4196 tc[2] |= HDSPM_TCO2_set_term_75R;
4197 }
4198
4199 hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]);
4200 hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]);
4201 hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]);
4202 hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]);
4203}
4204
4205
4206#define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \
4207{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4208 .name = xname, \
4209 .index = xindex, \
4210 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4211 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4212 .info = snd_hdspm_info_tco_sample_rate, \
4213 .get = snd_hdspm_get_tco_sample_rate, \
4214 .put = snd_hdspm_put_tco_sample_rate \
4215}
4216
4217static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol,
4218 struct snd_ctl_elem_info *uinfo)
4219{
69358fca 4220 /* TODO freq from app could be supported here, see tco->samplerate */
38816545 4221 static const char *const texts[] = { "44.1 kHz", "48 kHz" };
e5b7b1fe 4222 ENUMERATED_CTL_INFO(uinfo, texts);
0dca1793
AK		 4223 return 0;
4224}
4225
4226static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol,
4227 struct snd_ctl_elem_value *ucontrol)
4228{
4229 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4230
4231 ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate;
4232
4233 return 0;
4234}
4235
4236static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol,
4237 struct snd_ctl_elem_value *ucontrol)
4238{
4239 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4240
4241 if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) {
4242 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0];
4243
4244 hdspm_tco_write(hdspm);
4245
4246 return 1;
4247 }
4248
4249 return 0;
4250}
4251
4252
4253#define HDSPM_TCO_PULL(xname, xindex) \
4254{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4255 .name = xname, \
4256 .index = xindex, \
4257 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4258 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4259 .info = snd_hdspm_info_tco_pull, \
4260 .get = snd_hdspm_get_tco_pull, \
4261 .put = snd_hdspm_put_tco_pull \
4262}
4263
4264static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol,
4265 struct snd_ctl_elem_info *uinfo)
4266{
38816545
AK		 4267 static const char *const texts[] = { "0", "+ 0.1 %", "- 0.1 %",
4268 "+ 4 %", "- 4 %" };
e5b7b1fe 4269 ENUMERATED_CTL_INFO(uinfo, texts);
0dca1793
AK		 4270 return 0;
4271}
4272
4273static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol,
4274 struct snd_ctl_elem_value *ucontrol)
4275{
4276 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4277
4278 ucontrol->value.enumerated.item[0] = hdspm->tco->pull;
4279
4280 return 0;
4281}
4282
4283static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol,
4284 struct snd_ctl_elem_value *ucontrol)
4285{
4286 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4287
4288 if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) {
4289 hdspm->tco->pull = ucontrol->value.enumerated.item[0];
4290
4291 hdspm_tco_write(hdspm);
4292
4293 return 1;
4294 }
4295
4296 return 0;
4297}
4298
4299#define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \
4300{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4301 .name = xname, \
4302 .index = xindex, \
4303 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4304 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4305 .info = snd_hdspm_info_tco_wck_conversion, \
4306 .get = snd_hdspm_get_tco_wck_conversion, \
4307 .put = snd_hdspm_put_tco_wck_conversion \
4308}
4309
4310static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4311 struct snd_ctl_elem_info *uinfo)
4312{
38816545 4313 static const char *const texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" };
e5b7b1fe 4314 ENUMERATED_CTL_INFO(uinfo, texts);
0dca1793
AK		 4315 return 0;
4316}
4317
4318static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4319 struct snd_ctl_elem_value *ucontrol)
4320{
4321 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4322
4323 ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock;
4324
4325 return 0;
4326}
4327
4328static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4329 struct snd_ctl_elem_value *ucontrol)
4330{
4331 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4332
4333 if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) {
4334 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0];
4335
4336 hdspm_tco_write(hdspm);
4337
4338 return 1;
4339 }
4340
4341 return 0;
4342}
4343
4344
4345#define HDSPM_TCO_FRAME_RATE(xname, xindex) \
4346{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4347 .name = xname, \
4348 .index = xindex, \
4349 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4350 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4351 .info = snd_hdspm_info_tco_frame_rate, \
4352 .get = snd_hdspm_get_tco_frame_rate, \
4353 .put = snd_hdspm_put_tco_frame_rate \
4354}
4355
4356static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol,
4357 struct snd_ctl_elem_info *uinfo)
4358{
38816545 4359 static const char *const texts[] = { "24 fps", "25 fps", "29.97fps",
0dca1793 4360 "29.97 dfps", "30 fps", "30 dfps" };
e5b7b1fe 4361 ENUMERATED_CTL_INFO(uinfo, texts);
0dca1793
AK		 4362 return 0;
4363}
4364
4365static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol,
3cee5a60
RB		 4366 struct snd_ctl_elem_value *ucontrol)
4367{
3cee5a60
RB		 4368 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4369
0dca1793 4370 ucontrol->value.enumerated.item[0] = hdspm->tco->framerate;
3cee5a60 4371
3cee5a60
RB		 4372 return 0;
4373}
763f356c 4374
0dca1793
AK		 4375static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol,
4376 struct snd_ctl_elem_value *ucontrol)
4377{
4378 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
763f356c 4379
0dca1793
AK		 4380 if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) {
4381 hdspm->tco->framerate = ucontrol->value.enumerated.item[0];
763f356c 4382
0dca1793
AK		 4383 hdspm_tco_write(hdspm);
4384
4385 return 1;
4386 }
4387
4388 return 0;
4389}
763f356c 4390
0dca1793
AK		 4391
4392#define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \
4393{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4394 .name = xname, \
4395 .index = xindex, \
4396 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4397 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4398 .info = snd_hdspm_info_tco_sync_source, \
4399 .get = snd_hdspm_get_tco_sync_source, \
4400 .put = snd_hdspm_put_tco_sync_source \
4401}
4402
4403static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol,
4404 struct snd_ctl_elem_info *uinfo)
4405{
38816545 4406 static const char *const texts[] = { "LTC", "Video", "WCK" };
e5b7b1fe 4407 ENUMERATED_CTL_INFO(uinfo, texts);
0dca1793
AK		 4408 return 0;
4409}
4410
4411static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol,
4412 struct snd_ctl_elem_value *ucontrol)
4413{
4414 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4415
4416 ucontrol->value.enumerated.item[0] = hdspm->tco->input;
4417
4418 return 0;
4419}
4420
4421static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol,
4422 struct snd_ctl_elem_value *ucontrol)
4423{
4424 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4425
4426 if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) {
4427 hdspm->tco->input = ucontrol->value.enumerated.item[0];
4428
4429 hdspm_tco_write(hdspm);
4430
4431 return 1;
4432 }
4433
4434 return 0;
4435}
4436
4437
4438#define HDSPM_TCO_WORD_TERM(xname, xindex) \
4439{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4440 .name = xname, \
4441 .index = xindex, \
4442 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4443 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4444 .info = snd_hdspm_info_tco_word_term, \
4445 .get = snd_hdspm_get_tco_word_term, \
4446 .put = snd_hdspm_put_tco_word_term \
4447}
4448
4449static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol,
4450 struct snd_ctl_elem_info *uinfo)
4451{
4452 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
4453 uinfo->count = 1;
4454 uinfo->value.integer.min = 0;
4455 uinfo->value.integer.max = 1;
4456
4457 return 0;
4458}
4459
4460
4461static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol,
4462 struct snd_ctl_elem_value *ucontrol)
4463{
4464 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4465
537e4813 4466 ucontrol->value.integer.value[0] = hdspm->tco->term;
0dca1793
AK		 4467
4468 return 0;
4469}
4470
4471
4472static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol,
4473 struct snd_ctl_elem_value *ucontrol)
4474{
4475 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4476
537e4813
TI		 4477 if (hdspm->tco->term != ucontrol->value.integer.value[0]) {
4478 hdspm->tco->term = ucontrol->value.integer.value[0];
0dca1793
AK		 4479
4480 hdspm_tco_write(hdspm);
4481
4482 return 1;
4483 }
4484
4485 return 0;
4486}
4487
4488
4489
4490
4491static struct snd_kcontrol_new snd_hdspm_controls_madi[] = {
4492 HDSPM_MIXER("Mixer", 0),
4493 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
763f356c
TI		 4494 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4495 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4496 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4497 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
b8812c55 4498 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
0dca1793
AK		 4499 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4500 HDSPM_SYNC_CHECK("MADI SyncCheck", 1),
930f4ff0 4501 HDSPM_SYNC_CHECK("TCO SyncCheck", 2),
0dca1793 4502 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3),
c9e1668c
AK		 4503 HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut),
4504 HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch),
696be0fb 4505 HDSPM_TOGGLE_SETTING("Disable 96K frames", HDSPM_SMUX),
c9e1668c
AK		 4506 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4507 HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp),
700d1ef3
AK		 4508 HDSPM_INPUT_SELECT("Input Select", 0),
4509 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
0dca1793
AK		 4510};
4511
4512
4513static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = {
4514 HDSPM_MIXER("Mixer", 0),
4515 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4516 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4517 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4518 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4519 HDSPM_SYNC_CHECK("MADI SyncCheck", 0),
c9e1668c
AK		 4520 HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch),
4521 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4522 HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp),
700d1ef3 4523 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
763f356c
TI		 4524};
4525
0dca1793
AK		 4526static struct snd_kcontrol_new snd_hdspm_controls_aio[] = {
4527 HDSPM_MIXER("Mixer", 0),
4528 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4529 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4530 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
0dca1793
AK		 4531 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4532 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4533 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4534 HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4535 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4536 HDSPM_SYNC_CHECK("ADAT SyncCheck", 3),
4537 HDSPM_SYNC_CHECK("TCO SyncCheck", 4),
4538 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5),
4539 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4540 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4541 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4542 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3),
4543 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4),
fb0f121e 4544 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5),
42f4c12d 4545 HDSPM_CONTROL_TRISTATE("S/PDIF Input", HDSPM_c0_Input0),
fb0f121e
AK		 4546 HDSPM_TOGGLE_SETTING("S/PDIF Out Optical", HDSPM_c0_Spdif_Opt),
4547 HDSPM_TOGGLE_SETTING("S/PDIF Out Professional", HDSPM_c0_Pro),
4548 HDSPM_TOGGLE_SETTING("ADAT internal (AEB/TEB)", HDSPM_c0_AEB1),
4549 HDSPM_TOGGLE_SETTING("XLR Breakout Cable", HDSPM_c0_Sym6db),
42f4c12d
AK		 4550 HDSPM_TOGGLE_SETTING("Single Speed WordClock Out", HDSPM_c0_Wck48),
4551 HDSPM_CONTROL_TRISTATE("Input Level", HDSPM_c0_AD_GAIN0),
4552 HDSPM_CONTROL_TRISTATE("Output Level", HDSPM_c0_DA_GAIN0),
4553 HDSPM_CONTROL_TRISTATE("Phones Level", HDSPM_c0_PH_GAIN0)
0dca1793
AK		 4554
4555 /*
4556 HDSPM_INPUT_SELECT("Input Select", 0),
4557 HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0),
4558 HDSPM_PROFESSIONAL("SPDIF Out Professional", 0);
4559 HDSPM_SPDIF_IN("SPDIF In", 0);
4560 HDSPM_BREAKOUT_CABLE("Breakout Cable", 0);
4561 HDSPM_INPUT_LEVEL("Input Level", 0);
4562 HDSPM_OUTPUT_LEVEL("Output Level", 0);
4563 HDSPM_PHONES("Phones", 0);
4564 */
4565};
3cee5a60 4566
0dca1793
AK		 4567static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = {
4568 HDSPM_MIXER("Mixer", 0),
4569 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4570 HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0),
4571 HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0),
4572 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4573 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4574 HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4575 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4576 HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3),
4577 HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4),
4578 HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5),
4579 HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6),
4580 HDSPM_SYNC_CHECK("TCO SyncCheck", 7),
4581 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8),
4582 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4583 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4584 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4585 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3),
4586 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4),
4587 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5),
4588 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6),
4589 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7),
11a5cd3c
AK		 4590 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8),
4591 HDSPM_TOGGLE_SETTING("S/PDIF Out Professional", HDSPM_c0_Pro),
4592 HDSPM_TOGGLE_SETTING("Single Speed WordClock Out", HDSPM_c0_Wck48)
0dca1793
AK		 4593};
4594
4595static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = {
3cee5a60 4596 HDSPM_MIXER("Mixer", 0),
0dca1793 4597 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
3cee5a60
RB		 4598 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4599 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4600 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4601 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
2d63ec38 4602 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 11),
0dca1793
AK		 4603 HDSPM_SYNC_CHECK("WC Sync Check", 0),
4604 HDSPM_SYNC_CHECK("AES1 Sync Check", 1),
4605 HDSPM_SYNC_CHECK("AES2 Sync Check", 2),
4606 HDSPM_SYNC_CHECK("AES3 Sync Check", 3),
4607 HDSPM_SYNC_CHECK("AES4 Sync Check", 4),
4608 HDSPM_SYNC_CHECK("AES5 Sync Check", 5),
4609 HDSPM_SYNC_CHECK("AES6 Sync Check", 6),
4610 HDSPM_SYNC_CHECK("AES7 Sync Check", 7),
4611 HDSPM_SYNC_CHECK("AES8 Sync Check", 8),
4612 HDSPM_SYNC_CHECK("TCO Sync Check", 9),
4613 HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10),
4614 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4615 HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1),
4616 HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2),
4617 HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3),
4618 HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4),
4619 HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5),
4620 HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6),
4621 HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7),
4622 HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8),
4623 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9),
4624 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10),
c9e1668c
AK		 4625 HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut),
4626 HDSPM_TOGGLE_SETTING("Emphasis", HDSPM_Emphasis),
4627 HDSPM_TOGGLE_SETTING("Non Audio", HDSPM_Dolby),
4628 HDSPM_TOGGLE_SETTING("Professional", HDSPM_Professional),
4629 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
3cee5a60
RB		 4630 HDSPM_DS_WIRE("Double Speed Wire Mode", 0),
4631 HDSPM_QS_WIRE("Quad Speed Wire Mode", 0),
4632};
4633
0dca1793
AK		 4634
4635
4636/* Control elements for the optional TCO module */
4637static struct snd_kcontrol_new snd_hdspm_controls_tco[] = {
4638 HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0),
4639 HDSPM_TCO_PULL("TCO Pull", 0),
4640 HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0),
4641 HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0),
4642 HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0),
a817650e
AK		 4643 HDSPM_TCO_WORD_TERM("TCO Word Term", 0),
4644 HDSPM_TCO_LOCK_CHECK("TCO Input Check", 11),
4645 HDSPM_TCO_LOCK_CHECK("TCO LTC Valid", 12),
4646 HDSPM_TCO_LTC_FRAMES("TCO Detected Frame Rate", 0),
4647 HDSPM_TCO_VIDEO_INPUT_FORMAT("Video Input Format", 0)
0dca1793
AK		 4648};
4649
4650
98274f07 4651static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER;
763f356c
TI		 4652
4653
98274f07 4654static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm)
763f356c
TI		 4655{
4656 int i;
4657
0dca1793 4658 for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) {
763f356c
TI		 4659 if (hdspm->system_sample_rate > 48000) {
4660 hdspm->playback_mixer_ctls[i]->vd[0].access =
0dca1793
AK		 4661 SNDRV_CTL_ELEM_ACCESS_INACTIVE |
4662 SNDRV_CTL_ELEM_ACCESS_READ |
4663 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
763f356c
TI		 4664 } else {
4665 hdspm->playback_mixer_ctls[i]->vd[0].access =
0dca1793
AK		 4666 SNDRV_CTL_ELEM_ACCESS_READWRITE |
4667 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
763f356c
TI		 4668 }
4669 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE |
0dca1793
AK		 4670 SNDRV_CTL_EVENT_MASK_INFO,
4671 &hdspm->playback_mixer_ctls[i]->id);
763f356c
TI		 4672 }
4673
4674 return 0;
4675}
4676
4677
0dca1793
AK		 4678static int snd_hdspm_create_controls(struct snd_card *card,
4679 struct hdspm *hdspm)
763f356c
TI		 4680{
4681 unsigned int idx, limit;
4682 int err;
98274f07 4683 struct snd_kcontrol *kctl;
0dca1793 4684 struct snd_kcontrol_new *list = NULL;
763f356c 4685
0dca1793
AK		 4686 switch (hdspm->io_type) {
4687 case MADI:
4688 list = snd_hdspm_controls_madi;
4689 limit = ARRAY_SIZE(snd_hdspm_controls_madi);
4690 break;
4691 case MADIface:
4692 list = snd_hdspm_controls_madiface;
4693 limit = ARRAY_SIZE(snd_hdspm_controls_madiface);
4694 break;
4695 case AIO:
4696 list = snd_hdspm_controls_aio;
4697 limit = ARRAY_SIZE(snd_hdspm_controls_aio);
4698 break;
4699 case RayDAT:
4700 list = snd_hdspm_controls_raydat;
4701 limit = ARRAY_SIZE(snd_hdspm_controls_raydat);
4702 break;
4703 case AES32:
4704 list = snd_hdspm_controls_aes32;
4705 limit = ARRAY_SIZE(snd_hdspm_controls_aes32);
4706 break;
4707 }
3cee5a60 4708
0dca1793
AK		 4709 if (NULL != list) {
4710 for (idx = 0; idx < limit; idx++) {
3cee5a60 4711 err = snd_ctl_add(card,
0dca1793 4712 snd_ctl_new1(&list[idx], hdspm));
3cee5a60
RB		 4713 if (err < 0)
4714 return err;
763f356c
TI		 4715 }
4716 }
4717
763f356c 4718
0dca1793 4719 /* create simple 1:1 playback mixer controls */
763f356c 4720 snd_hdspm_playback_mixer.name = "Chn";
0dca1793
AK		 4721 if (hdspm->system_sample_rate >= 128000) {
4722 limit = hdspm->qs_out_channels;
4723 } else if (hdspm->system_sample_rate >= 64000) {
4724 limit = hdspm->ds_out_channels;
4725 } else {
4726 limit = hdspm->ss_out_channels;
4727 }
763f356c
TI		 4728 for (idx = 0; idx < limit; ++idx) {
4729 snd_hdspm_playback_mixer.index = idx + 1;
ef5fa1a4
TI		 4730 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm);
4731 err = snd_ctl_add(card, kctl);
4732 if (err < 0)
763f356c 4733 return err;
763f356c
TI		 4734 hdspm->playback_mixer_ctls[idx] = kctl;
4735 }
4736
0dca1793
AK		 4737
4738 if (hdspm->tco) {
4739 /* add tco control elements */
4740 list = snd_hdspm_controls_tco;
4741 limit = ARRAY_SIZE(snd_hdspm_controls_tco);
4742 for (idx = 0; idx < limit; idx++) {
4743 err = snd_ctl_add(card,
4744 snd_ctl_new1(&list[idx], hdspm));
4745 if (err < 0)
4746 return err;
4747 }
4748 }
4749
763f356c
TI		 4750 return 0;
4751}
4752
4753/*------------------------------------------------------------
0dca1793 4754 /proc interface
763f356c
TI		 4755 ------------------------------------------------------------*/
4756
4757static void
5760107c
AK		 4758snd_hdspm_proc_read_tco(struct snd_info_entry *entry,
4759 struct snd_info_buffer *buffer)
763f356c 4760{
ef5fa1a4 4761 struct hdspm *hdspm = entry->private_data;
5760107c 4762 unsigned int status, control;
0dca1793
AK		 4763 int a, ltc, frames, seconds, minutes, hours;
4764 unsigned int period;
4765 u64 freq_const = 0;
4766 u32 rate;
4767
5760107c
AK		 4768 snd_iprintf(buffer, "--- TCO ---\n");
4769
763f356c 4770 status = hdspm_read(hdspm, HDSPM_statusRegister);
0dca1793 4771 control = hdspm->control_register;
763f356c 4772
763f356c 4773
0dca1793
AK		 4774 if (status & HDSPM_tco_detect) {
4775 snd_iprintf(buffer, "TCO module detected.\n");
4776 a = hdspm_read(hdspm, HDSPM_RD_TCO+4);
4777 if (a & HDSPM_TCO1_LTC_Input_valid) {
4778 snd_iprintf(buffer, " LTC valid, ");
4779 switch (a & (HDSPM_TCO1_LTC_Format_LSB |
4780 HDSPM_TCO1_LTC_Format_MSB)) {
4781 case 0:
4782 snd_iprintf(buffer, "24 fps, ");
4783 break;
4784 case HDSPM_TCO1_LTC_Format_LSB:
4785 snd_iprintf(buffer, "25 fps, ");
4786 break;
4787 case HDSPM_TCO1_LTC_Format_MSB:
4788 snd_iprintf(buffer, "29.97 fps, ");
4789 break;
4790 default:
4791 snd_iprintf(buffer, "30 fps, ");
4792 break;
4793 }
4794 if (a & HDSPM_TCO1_set_drop_frame_flag) {
4795 snd_iprintf(buffer, "drop frame\n");
4796 } else {
4797 snd_iprintf(buffer, "full frame\n");
4798 }
4799 } else {
4800 snd_iprintf(buffer, " no LTC\n");
4801 }
4802 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) {
4803 snd_iprintf(buffer, " Video: NTSC\n");
4804 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) {
4805 snd_iprintf(buffer, " Video: PAL\n");
4806 } else {
4807 snd_iprintf(buffer, " No video\n");
4808 }
4809 if (a & HDSPM_TCO1_TCO_lock) {
4810 snd_iprintf(buffer, " Sync: lock\n");
4811 } else {
4812 snd_iprintf(buffer, " Sync: no lock\n");
4813 }
4814
4815 switch (hdspm->io_type) {
4816 case MADI:
4817 case AES32:
4818 freq_const = 110069313433624ULL;
4819 break;
4820 case RayDAT:
4821 case AIO:
4822 freq_const = 104857600000000ULL;
4823 break;
4824 case MADIface:
4825 break; /* no TCO possible */
4826 }
4827
4828 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
4829 snd_iprintf(buffer, " period: %u\n", period);
4830
4831
4832 /* rate = freq_const/period; */
4833 rate = div_u64(freq_const, period);
4834
4835 if (control & HDSPM_QuadSpeed) {
4836 rate *= 4;
4837 } else if (control & HDSPM_DoubleSpeed) {
4838 rate *= 2;
4839 }
4840
4841 snd_iprintf(buffer, " Frequency: %u Hz\n",
4842 (unsigned int) rate);
4843
4844 ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
4845 frames = ltc & 0xF;
4846 ltc >>= 4;
4847 frames += (ltc & 0x3) * 10;
4848 ltc >>= 4;
4849 seconds = ltc & 0xF;
4850 ltc >>= 4;
4851 seconds += (ltc & 0x7) * 10;
4852 ltc >>= 4;
4853 minutes = ltc & 0xF;
4854 ltc >>= 4;
4855 minutes += (ltc & 0x7) * 10;
4856 ltc >>= 4;
4857 hours = ltc & 0xF;
4858 ltc >>= 4;
4859 hours += (ltc & 0x3) * 10;
4860 snd_iprintf(buffer,
4861 " LTC In: %02d:%02d:%02d:%02d\n",
4862 hours, minutes, seconds, frames);
4863
4864 } else {
4865 snd_iprintf(buffer, "No TCO module detected.\n");
4866 }
5760107c
AK		 4867}
4868
4869static void
4870snd_hdspm_proc_read_madi(struct snd_info_entry *entry,
4871 struct snd_info_buffer *buffer)
4872{
4873 struct hdspm *hdspm = entry->private_data;
df57de17 4874 unsigned int status, status2;
5760107c
AK		 4875
4876 char *pref_sync_ref;
4877 char *autosync_ref;
4878 char *system_clock_mode;
5760107c
AK		 4879 int x, x2;
4880
4881 status = hdspm_read(hdspm, HDSPM_statusRegister);
4882 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
5760107c
AK		 4883
4884 snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n",
4885 hdspm->card_name, hdspm->card->number + 1,
4886 hdspm->firmware_rev,
4887 (status2 & HDSPM_version0) |
4888 (status2 & HDSPM_version1) | (status2 &
4889 HDSPM_version2));
4890
4891 snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n",
4892 (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF,
4893 hdspm->serial);
4894
4895 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4896 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4897
4898 snd_iprintf(buffer, "--- System ---\n");
4899
4900 snd_iprintf(buffer,
4901 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4902 status & HDSPM_audioIRQPending,
4903 (status & HDSPM_midi0IRQPending) ? 1 : 0,
4904 (status & HDSPM_midi1IRQPending) ? 1 : 0,
4905 hdspm->irq_count);
4906 snd_iprintf(buffer,
4907 "HW pointer: id = %d, rawptr = %d (%d->%d) "
4908 "estimated= %ld (bytes)\n",
4909 ((status & HDSPM_BufferID) ? 1 : 0),
4910 (status & HDSPM_BufferPositionMask),
4911 (status & HDSPM_BufferPositionMask) %
4912 (2 * (int)hdspm->period_bytes),
4913 ((status & HDSPM_BufferPositionMask) - 64) %
4914 (2 * (int)hdspm->period_bytes),
4915 (long) hdspm_hw_pointer(hdspm) * 4);
4916
4917 snd_iprintf(buffer,
4918 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4919 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4920 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4921 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4922 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4923 snd_iprintf(buffer,
4924 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4925 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4926 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4927 snd_iprintf(buffer,
4928 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4929 "status2=0x%x\n",
4930 hdspm->control_register, hdspm->control2_register,
4931 status, status2);
4932
763f356c
TI		 4933
4934 snd_iprintf(buffer, "--- Settings ---\n");
4935
7cb155ff 4936 x = hdspm_get_latency(hdspm);
763f356c
TI		 4937
4938 snd_iprintf(buffer,
0dca1793
AK		 4939 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4940 x, (unsigned long) hdspm->period_bytes);
763f356c 4941
0dca1793
AK		 4942 snd_iprintf(buffer, "Line out: %s\n",
4943 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off");
763f356c 4944
763f356c 4945 snd_iprintf(buffer,
0dca1793
AK		 4946 "ClearTrackMarker = %s, Transmit in %s Channel Mode, "
4947 "Auto Input %s\n",
4948 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off",
4949 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56",
4950 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off");
4951
763f356c 4952
3cee5a60 4953 if (!(hdspm->control_register & HDSPM_ClockModeMaster))
0dca1793 4954 system_clock_mode = "AutoSync";
3cee5a60 4955 else
763f356c 4956 system_clock_mode = "Master";
0dca1793 4957 snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode);
763f356c
TI		 4958
4959 switch (hdspm_pref_sync_ref(hdspm)) {
4960 case HDSPM_SYNC_FROM_WORD:
4961 pref_sync_ref = "Word Clock";
4962 break;
4963 case HDSPM_SYNC_FROM_MADI:
4964 pref_sync_ref = "MADI Sync";
4965 break;
0dca1793
AK		 4966 case HDSPM_SYNC_FROM_TCO:
4967 pref_sync_ref = "TCO";
4968 break;
4969 case HDSPM_SYNC_FROM_SYNC_IN:
4970 pref_sync_ref = "Sync In";
4971 break;
763f356c
TI		 4972 default:
4973 pref_sync_ref = "XXXX Clock";
4974 break;
4975 }
4976 snd_iprintf(buffer, "Preferred Sync Reference: %s\n",
0dca1793 4977 pref_sync_ref);
763f356c
TI		 4978
4979 snd_iprintf(buffer, "System Clock Frequency: %d\n",
0dca1793 4980 hdspm->system_sample_rate);
763f356c
TI		 4981
4982
4983 snd_iprintf(buffer, "--- Status:\n");
4984
4985 x = status & HDSPM_madiSync;
4986 x2 = status2 & HDSPM_wcSync;
4987
4988 snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n",
0dca1793
AK		 4989 (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") :
4990 "NoLock",
4991 (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") :
4992 "NoLock");
763f356c
TI		 4993
4994 switch (hdspm_autosync_ref(hdspm)) {
0dca1793
AK		 4995 case HDSPM_AUTOSYNC_FROM_SYNC_IN:
4996 autosync_ref = "Sync In";
4997 break;
4998 case HDSPM_AUTOSYNC_FROM_TCO:
4999 autosync_ref = "TCO";
5000 break;
763f356c
TI		 5001 case HDSPM_AUTOSYNC_FROM_WORD:
5002 autosync_ref = "Word Clock";
5003 break;
5004 case HDSPM_AUTOSYNC_FROM_MADI:
5005 autosync_ref = "MADI Sync";
5006 break;
5007 case HDSPM_AUTOSYNC_FROM_NONE:
5008 autosync_ref = "Input not valid";
5009 break;
5010 default:
5011 autosync_ref = "---";
5012 break;
5013 }
5014 snd_iprintf(buffer,
0dca1793
AK		 5015 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n",
5016 autosync_ref, hdspm_external_sample_rate(hdspm),
5017 (status & HDSPM_madiFreqMask) >> 22,
5018 (status2 & HDSPM_wcFreqMask) >> 5);
763f356c
TI		 5019
5020 snd_iprintf(buffer, "Input: %s, Mode=%s\n",
0dca1793
AK		 5021 (status & HDSPM_AB_int) ? "Coax" : "Optical",
5022 (status & HDSPM_RX_64ch) ? "64 channels" :
5023 "56 channels");
763f356c 5024
5760107c
AK		 5025 /* call readout function for TCO specific status */
5026 snd_hdspm_proc_read_tco(entry, buffer);
5027
763f356c
TI		 5028 snd_iprintf(buffer, "\n");
5029}
5030
3cee5a60
RB		 5031static void
5032snd_hdspm_proc_read_aes32(struct snd_info_entry * entry,
5033 struct snd_info_buffer *buffer)
5034{
ef5fa1a4 5035 struct hdspm *hdspm = entry->private_data;
3cee5a60
RB		 5036 unsigned int status;
5037 unsigned int status2;
5038 unsigned int timecode;
56bde0f3 5039 unsigned int wcLock, wcSync;
3cee5a60
RB		 5040 int pref_syncref;
5041 char *autosync_ref;
3cee5a60
RB		 5042 int x;
5043
5044 status = hdspm_read(hdspm, HDSPM_statusRegister);
5045 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
5046 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
5047
5048 snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n",
5049 hdspm->card_name, hdspm->card->number + 1,
5050 hdspm->firmware_rev);
5051
5052 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
5053 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
5054
5055 snd_iprintf(buffer, "--- System ---\n");
5056
5057 snd_iprintf(buffer,
5058 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
5059 status & HDSPM_audioIRQPending,
5060 (status & HDSPM_midi0IRQPending) ? 1 : 0,
5061 (status & HDSPM_midi1IRQPending) ? 1 : 0,
5062 hdspm->irq_count);
5063 snd_iprintf(buffer,
ef5fa1a4
TI		 5064 "HW pointer: id = %d, rawptr = %d (%d->%d) "
5065 "estimated= %ld (bytes)\n",
3cee5a60
RB		 5066 ((status & HDSPM_BufferID) ? 1 : 0),
5067 (status & HDSPM_BufferPositionMask),
ef5fa1a4
TI		 5068 (status & HDSPM_BufferPositionMask) %
5069 (2 * (int)hdspm->period_bytes),
5070 ((status & HDSPM_BufferPositionMask) - 64) %
5071 (2 * (int)hdspm->period_bytes),
3cee5a60
RB		 5072 (long) hdspm_hw_pointer(hdspm) * 4);
5073
5074 snd_iprintf(buffer,
5075 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
5076 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
5077 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
5078 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
5079 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
5080 snd_iprintf(buffer,
0dca1793
AK		 5081 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
5082 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
5083 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
5084 snd_iprintf(buffer,
5085 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
5086 "status2=0x%x\n",
5087 hdspm->control_register, hdspm->control2_register,
5088 status, status2);
3cee5a60
RB		 5089
5090 snd_iprintf(buffer, "--- Settings ---\n");
5091
7cb155ff 5092 x = hdspm_get_latency(hdspm);
3cee5a60
RB		 5093
5094 snd_iprintf(buffer,
5095 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
5096 x, (unsigned long) hdspm->period_bytes);
5097
0dca1793 5098 snd_iprintf(buffer, "Line out: %s\n",
3cee5a60 5099 (hdspm->
0dca1793 5100 control_register & HDSPM_LineOut) ? "on " : "off");
3cee5a60
RB		 5101
5102 snd_iprintf(buffer,
5103 "ClearTrackMarker %s, Emphasis %s, Dolby %s\n",
5104 (hdspm->
5105 control_register & HDSPM_clr_tms) ? "on" : "off",
5106 (hdspm->
5107 control_register & HDSPM_Emphasis) ? "on" : "off",
5108 (hdspm->
5109 control_register & HDSPM_Dolby) ? "on" : "off");
5110
3cee5a60
RB		 5111
5112 pref_syncref = hdspm_pref_sync_ref(hdspm);
5113 if (pref_syncref == 0)
5114 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n");
5115 else
5116 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n",
5117 pref_syncref);
5118
5119 snd_iprintf(buffer, "System Clock Frequency: %d\n",
5120 hdspm->system_sample_rate);
5121
5122 snd_iprintf(buffer, "Double speed: %s\n",
5123 hdspm->control_register & HDSPM_DS_DoubleWire?
5124 "Double wire" : "Single wire");
5125 snd_iprintf(buffer, "Quad speed: %s\n",
5126 hdspm->control_register & HDSPM_QS_DoubleWire?
5127 "Double wire" :
5128 hdspm->control_register & HDSPM_QS_QuadWire?
5129 "Quad wire" : "Single wire");
5130
5131 snd_iprintf(buffer, "--- Status:\n");
5132
56bde0f3
AS		 5133 wcLock = status & HDSPM_AES32_wcLock;
5134 wcSync = wcLock && (status & HDSPM_AES32_wcSync);
5135
3cee5a60 5136 snd_iprintf(buffer, "Word: %s Frequency: %d\n",
56bde0f3 5137 (wcLock) ? (wcSync ? "Sync " : "Lock ") : "No Lock",
ef5fa1a4 5138 HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF));
3cee5a60
RB		 5139
5140 for (x = 0; x < 8; x++) {
5141 snd_iprintf(buffer, "AES%d: %s Frequency: %d\n",
ef5fa1a4
TI		 5142 x+1,
5143 (status2 & (HDSPM_LockAES >> x)) ?
0dca1793 5144 "Sync " : "No Lock",
ef5fa1a4 5145 HDSPM_bit2freq((timecode >> (4*x)) & 0xF));
3cee5a60
RB		 5146 }
5147
5148 switch (hdspm_autosync_ref(hdspm)) {
0dca1793
AK		 5149 case HDSPM_AES32_AUTOSYNC_FROM_NONE:
5150 autosync_ref = "None"; break;
5151 case HDSPM_AES32_AUTOSYNC_FROM_WORD:
5152 autosync_ref = "Word Clock"; break;
5153 case HDSPM_AES32_AUTOSYNC_FROM_AES1:
5154 autosync_ref = "AES1"; break;
5155 case HDSPM_AES32_AUTOSYNC_FROM_AES2:
5156 autosync_ref = "AES2"; break;
5157 case HDSPM_AES32_AUTOSYNC_FROM_AES3:
5158 autosync_ref = "AES3"; break;
5159 case HDSPM_AES32_AUTOSYNC_FROM_AES4:
5160 autosync_ref = "AES4"; break;
5161 case HDSPM_AES32_AUTOSYNC_FROM_AES5:
5162 autosync_ref = "AES5"; break;
5163 case HDSPM_AES32_AUTOSYNC_FROM_AES6:
5164 autosync_ref = "AES6"; break;
5165 case HDSPM_AES32_AUTOSYNC_FROM_AES7:
5166 autosync_ref = "AES7"; break;
5167 case HDSPM_AES32_AUTOSYNC_FROM_AES8:
5168 autosync_ref = "AES8"; break;
194062da
AK		 5169 case HDSPM_AES32_AUTOSYNC_FROM_TCO:
5170 autosync_ref = "TCO"; break;
5171 case HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN:
5172 autosync_ref = "Sync In"; break;
0dca1793
AK		 5173 default:
5174 autosync_ref = "---"; break;
3cee5a60
RB		 5175 }
5176 snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref);
5177
194062da
AK		 5178 /* call readout function for TCO specific status */
5179 snd_hdspm_proc_read_tco(entry, buffer);
5180
3cee5a60
RB		 5181 snd_iprintf(buffer, "\n");
5182}
5183
0dca1793
AK		 5184static void
5185snd_hdspm_proc_read_raydat(struct snd_info_entry *entry,
5186 struct snd_info_buffer *buffer)
5187{
5188 struct hdspm *hdspm = entry->private_data;
df57de17 5189 unsigned int status1, status2, status3, i;
0dca1793
AK		 5190 unsigned int lock, sync;
5191
5192 status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */
5193 status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */
5194 status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */
5195
0dca1793
AK		 5196 snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1);
5197 snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2);
5198 snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3);
5199
5200
5201 snd_iprintf(buffer, "\n*** CLOCK MODE\n\n");
5202
5203 snd_iprintf(buffer, "Clock mode : %s\n",
5204 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave");
5205 snd_iprintf(buffer, "System frequency: %d Hz\n",
5206 hdspm_get_system_sample_rate(hdspm));
5207
5208 snd_iprintf(buffer, "\n*** INPUT STATUS\n\n");
5209
5210 lock = 0x1;
5211 sync = 0x100;
5212
5213 for (i = 0; i < 8; i++) {
5214 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n",
5215 i,
5216 (status1 & lock) ? 1 : 0,
5217 (status1 & sync) ? 1 : 0,
5218 texts_freq[(status2 >> (i * 4)) & 0xF]);
5219
5220 lock = lock<<1;
5221 sync = sync<<1;
5222 }
5223
5224 snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n",
5225 (status1 & 0x1000000) ? 1 : 0,
5226 (status1 & 0x2000000) ? 1 : 0,
5227 texts_freq[(status1 >> 16) & 0xF]);
5228
5229 snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n",
5230 (status1 & 0x4000000) ? 1 : 0,
5231 (status1 & 0x8000000) ? 1 : 0,
5232 texts_freq[(status1 >> 20) & 0xF]);
5233
5234 snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n",
5235 (status3 & 0x400) ? 1 : 0,
5236 (status3 & 0x800) ? 1 : 0,
5237 texts_freq[(status2 >> 12) & 0xF]);
5238
5239}
5240
3cee5a60
RB		 5241#ifdef CONFIG_SND_DEBUG
5242static void
0dca1793 5243snd_hdspm_proc_read_debug(struct snd_info_entry *entry,
3cee5a60
RB		 5244 struct snd_info_buffer *buffer)
5245{
ef5fa1a4 5246 struct hdspm *hdspm = entry->private_data;
3cee5a60
RB		 5247
5248 int j,i;
5249
ef5fa1a4 5250 for (i = 0; i < 256 /* 1024*64 */; i += j) {
3cee5a60
RB		 5251 snd_iprintf(buffer, "0x%08X: ", i);
5252 for (j = 0; j < 16; j += 4)
5253 snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j));
5254 snd_iprintf(buffer, "\n");
5255 }
5256}
5257#endif
5258
5259
0dca1793
AK		 5260static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry,
5261 struct snd_info_buffer *buffer)
5262{
5263 struct hdspm *hdspm = entry->private_data;
5264 int i;
5265
5266 snd_iprintf(buffer, "# generated by hdspm\n");
5267
5268 for (i = 0; i < hdspm->max_channels_in; i++) {
5269 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]);
5270 }
5271}
5272
5273static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry,
5274 struct snd_info_buffer *buffer)
5275{
5276 struct hdspm *hdspm = entry->private_data;
5277 int i;
5278
5279 snd_iprintf(buffer, "# generated by hdspm\n");
5280
5281 for (i = 0; i < hdspm->max_channels_out; i++) {
5282 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]);
5283 }
5284}
5285
3cee5a60 5286
e23e7a14 5287static void snd_hdspm_proc_init(struct hdspm *hdspm)
763f356c 5288{
98274f07 5289 struct snd_info_entry *entry;
763f356c 5290
0dca1793
AK		 5291 if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) {
5292 switch (hdspm->io_type) {
5293 case AES32:
5294 snd_info_set_text_ops(entry, hdspm,
5295 snd_hdspm_proc_read_aes32);
5296 break;
5297 case MADI:
5298 snd_info_set_text_ops(entry, hdspm,
5299 snd_hdspm_proc_read_madi);
5300 break;
5301 case MADIface:
5302 /* snd_info_set_text_ops(entry, hdspm,
5303 snd_hdspm_proc_read_madiface); */
5304 break;
5305 case RayDAT:
5306 snd_info_set_text_ops(entry, hdspm,
5307 snd_hdspm_proc_read_raydat);
5308 break;
5309 case AIO:
5310 break;
5311 }
5312 }
5313
5314 if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) {
5315 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in);
5316 }
5317
5318 if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) {
5319 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out);
5320 }
5321
3cee5a60
RB		 5322#ifdef CONFIG_SND_DEBUG
5323 /* debug file to read all hdspm registers */
5324 if (!snd_card_proc_new(hdspm->card, "debug", &entry))
5325 snd_info_set_text_ops(entry, hdspm,
5326 snd_hdspm_proc_read_debug);
5327#endif
763f356c
TI		 5328}
5329
5330/*------------------------------------------------------------
0dca1793 5331 hdspm intitialize
763f356c
TI		 5332 ------------------------------------------------------------*/
5333
98274f07 5334static int snd_hdspm_set_defaults(struct hdspm * hdspm)
763f356c 5335{
763f356c 5336 /* ASSUMPTION: hdspm->lock is either held, or there is no need to
561de31a 5337 hold it (e.g. during module initialization).
0dca1793 5338 */
763f356c
TI		 5339
5340 /* set defaults: */
5341
0dca1793
AK		 5342 hdspm->settings_register = 0;
5343
5344 switch (hdspm->io_type) {
5345 case MADI:
5346 case MADIface:
5347 hdspm->control_register =
5348 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5349 break;
5350
5351 case RayDAT:
5352 case AIO:
5353 hdspm->settings_register = 0x1 + 0x1000;
5354 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0,
5355 * line_out */
5356 hdspm->control_register =
5357 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5358 break;
5359
5360 case AES32:
ef5fa1a4 5361 hdspm->control_register =
e71b95ad 5362 HDSPM_ClockModeMaster | /* Master Clock Mode on */
0dca1793 5363 hdspm_encode_latency(7) | /* latency max=8192samples */
3cee5a60
RB		 5364 HDSPM_SyncRef0 | /* AES1 is syncclock */
5365 HDSPM_LineOut | /* Analog output in */
5366 HDSPM_Professional; /* Professional mode */
0dca1793
AK		 5367 break;
5368 }
763f356c
TI		 5369
5370 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5371
0dca1793 5372 if (AES32 == hdspm->io_type) {
ffb2c3c0 5373 /* No control2 register for AES32 */
763f356c 5374#ifdef SNDRV_BIG_ENDIAN
ffb2c3c0 5375 hdspm->control2_register = HDSPM_BIGENDIAN_MODE;
763f356c 5376#else
ffb2c3c0 5377 hdspm->control2_register = 0;
763f356c
TI		 5378#endif
5379
ffb2c3c0
RB		 5380 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register);
5381 }
763f356c
TI		 5382 hdspm_compute_period_size(hdspm);
5383
5384 /* silence everything */
5385
5386 all_in_all_mixer(hdspm, 0 * UNITY_GAIN);
5387
b2ed6326 5388 if (hdspm_is_raydat_or_aio(hdspm))
0dca1793 5389 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
763f356c
TI		 5390
5391 /* set a default rate so that the channel map is set up. */
0dca1793 5392 hdspm_set_rate(hdspm, 48000, 1);
763f356c
TI		 5393
5394 return 0;
5395}
5396
5397
5398/*------------------------------------------------------------
0dca1793 5399 interrupt
763f356c
TI		 5400 ------------------------------------------------------------*/
5401
7d12e780 5402static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id)
763f356c 5403{
98274f07 5404 struct hdspm *hdspm = (struct hdspm *) dev_id;
763f356c 5405 unsigned int status;
0dca1793
AK		 5406 int i, audio, midi, schedule = 0;
5407 /* cycles_t now; */
763f356c
TI		 5408
5409 status = hdspm_read(hdspm, HDSPM_statusRegister);
5410
5411 audio = status & HDSPM_audioIRQPending;
0dca1793
AK		 5412 midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending |
5413 HDSPM_midi2IRQPending | HDSPM_midi3IRQPending);
5414
5415 /* now = get_cycles(); */
ddcecf6b 5416 /*
0dca1793
AK		 5417 * LAT_2..LAT_0 period counter (win) counter (mac)
5418 * 6 4096 ~256053425 ~514672358
5419 * 5 2048 ~128024983 ~257373821
5420 * 4 1024 ~64023706 ~128718089
5421 * 3 512 ~32005945 ~64385999
5422 * 2 256 ~16003039 ~32260176
5423 * 1 128 ~7998738 ~16194507
5424 * 0 64 ~3998231 ~8191558
ddcecf6b 5425 */
0dca1793 5426 /*
e3a471d6 5427 dev_info(hdspm->card->dev, "snd_hdspm_interrupt %llu @ %llx\n",
0dca1793
AK		 5428 now-hdspm->last_interrupt, status & 0xFFC0);
5429 hdspm->last_interrupt = now;
5430 */
763f356c 5431
0dca1793 5432 if (!audio && !midi)
763f356c
TI		 5433 return IRQ_NONE;
5434
5435 hdspm_write(hdspm, HDSPM_interruptConfirmation, 0);
5436 hdspm->irq_count++;
5437
763f356c
TI		 5438
5439 if (audio) {
763f356c 5440 if (hdspm->capture_substream)
ef5fa1a4 5441 snd_pcm_period_elapsed(hdspm->capture_substream);
763f356c
TI		 5442
5443 if (hdspm->playback_substream)
ef5fa1a4 5444 snd_pcm_period_elapsed(hdspm->playback_substream);
763f356c
TI		 5445 }
5446
0dca1793
AK		 5447 if (midi) {
5448 i = 0;
5449 while (i < hdspm->midiPorts) {
5450 if ((hdspm_read(hdspm,
5451 hdspm->midi[i].statusIn) & 0xff) &&
5452 (status & hdspm->midi[i].irq)) {
5453 /* we disable interrupts for this input until
5454 * processing is done
5455 */
5456 hdspm->control_register &= ~hdspm->midi[i].ie;
5457 hdspm_write(hdspm, HDSPM_controlRegister,
5458 hdspm->control_register);
5459 hdspm->midi[i].pending = 1;
5460 schedule = 1;
5461 }
5462
5463 i++;
5464 }
5465
5466 if (schedule)
5467 tasklet_hi_schedule(&hdspm->midi_tasklet);
763f356c 5468 }
0dca1793 5469
763f356c
TI		 5470 return IRQ_HANDLED;
5471}
5472
5473/*------------------------------------------------------------
0dca1793 5474 pcm interface
763f356c
TI		 5475 ------------------------------------------------------------*/
5476
5477
0dca1793
AK		 5478static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream
5479 *substream)
763f356c 5480{
98274f07 5481 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
763f356c
TI		 5482 return hdspm_hw_pointer(hdspm);
5483}
5484
763f356c 5485
98274f07 5486static int snd_hdspm_reset(struct snd_pcm_substream *substream)
763f356c 5487{
98274f07
TI		 5488 struct snd_pcm_runtime *runtime = substream->runtime;
5489 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5490 struct snd_pcm_substream *other;
763f356c
TI		 5491
5492 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5493 other = hdspm->capture_substream;
5494 else
5495 other = hdspm->playback_substream;
5496
5497 if (hdspm->running)
5498 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm);
5499 else
5500 runtime->status->hw_ptr = 0;
5501 if (other) {
98274f07
TI		 5502 struct snd_pcm_substream *s;
5503 struct snd_pcm_runtime *oruntime = other->runtime;
ef991b95 5504 snd_pcm_group_for_each_entry(s, substream) {
763f356c
TI		 5505 if (s == other) {
5506 oruntime->status->hw_ptr =
0dca1793 5507 runtime->status->hw_ptr;
763f356c
TI		 5508 break;
5509 }
5510 }
5511 }
5512 return 0;
5513}
5514
98274f07
TI		 5515static int snd_hdspm_hw_params(struct snd_pcm_substream *substream,
5516 struct snd_pcm_hw_params *params)
763f356c 5517{
98274f07 5518 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
763f356c
TI		 5519 int err;
5520 int i;
5521 pid_t this_pid;
5522 pid_t other_pid;
763f356c
TI		 5523
5524 spin_lock_irq(&hdspm->lock);
5525
5526 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5527 this_pid = hdspm->playback_pid;
5528 other_pid = hdspm->capture_pid;
5529 } else {
5530 this_pid = hdspm->capture_pid;
5531 other_pid = hdspm->playback_pid;
5532 }
5533
ef5fa1a4 5534 if (other_pid > 0 && this_pid != other_pid) {
763f356c
TI		 5535
5536 /* The other stream is open, and not by the same
5537 task as this one. Make sure that the parameters
5538 that matter are the same.
0dca1793 5539 */
763f356c
TI		 5540
5541 if (params_rate(params) != hdspm->system_sample_rate) {
5542 spin_unlock_irq(&hdspm->lock);
5543 _snd_pcm_hw_param_setempty(params,
0dca1793 5544 SNDRV_PCM_HW_PARAM_RATE);
763f356c
TI		 5545 return -EBUSY;
5546 }
5547
5548 if (params_period_size(params) != hdspm->period_bytes / 4) {
5549 spin_unlock_irq(&hdspm->lock);
5550 _snd_pcm_hw_param_setempty(params,
0dca1793 5551 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
763f356c
TI		 5552 return -EBUSY;
5553 }
5554
5555 }
5556 /* We're fine. */
5557 spin_unlock_irq(&hdspm->lock);
5558
5559 /* how to make sure that the rate matches an externally-set one ? */
5560
5561 spin_lock_irq(&hdspm->lock);
ef5fa1a4
TI		 5562 err = hdspm_set_rate(hdspm, params_rate(params), 0);
5563 if (err < 0) {
e3a471d6 5564 dev_info(hdspm->card->dev, "err on hdspm_set_rate: %d\n", err);
763f356c
TI		 5565 spin_unlock_irq(&hdspm->lock);
5566 _snd_pcm_hw_param_setempty(params,
0dca1793 5567 SNDRV_PCM_HW_PARAM_RATE);
763f356c
TI		 5568 return err;
5569 }
5570 spin_unlock_irq(&hdspm->lock);
5571
ef5fa1a4 5572 err = hdspm_set_interrupt_interval(hdspm,
0dca1793 5573 params_period_size(params));
ef5fa1a4 5574 if (err < 0) {
e3a471d6
TI		 5575 dev_info(hdspm->card->dev,
5576 "err on hdspm_set_interrupt_interval: %d\n", err);
763f356c 5577 _snd_pcm_hw_param_setempty(params,
0dca1793 5578 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
763f356c
TI		 5579 return err;
5580 }
5581
ef5fa1a4
TI		 5582 /* Memory allocation, takashi's method, dont know if we should
5583 * spinlock
5584 */
763f356c 5585 /* malloc all buffer even if not enabled to get sure */
ffb2c3c0
RB		 5586 /* Update for MADI rev 204: we need to allocate for all channels,
5587 * otherwise it doesn't work at 96kHz */
0dca1793 5588
763f356c 5589 err =
0dca1793
AK		 5590 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES);
5591 if (err < 0) {
e3a471d6
TI		 5592 dev_info(hdspm->card->dev,
5593 "err on snd_pcm_lib_malloc_pages: %d\n", err);
763f356c 5594 return err;
0dca1793 5595 }
763f356c 5596
763f356c
TI		 5597 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5598
77a23f26 5599 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut,
763f356c
TI		 5600 params_channels(params));
5601
5602 for (i = 0; i < params_channels(params); ++i)
5603 snd_hdspm_enable_out(hdspm, i, 1);
5604
5605 hdspm->playback_buffer =
0dca1793 5606 (unsigned char *) substream->runtime->dma_area;
e3a471d6
TI		 5607 dev_dbg(hdspm->card->dev,
5608 "Allocated sample buffer for playback at %p\n",
3cee5a60 5609 hdspm->playback_buffer);
763f356c 5610 } else {
77a23f26 5611 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn,
763f356c
TI		 5612 params_channels(params));
5613
5614 for (i = 0; i < params_channels(params); ++i)
5615 snd_hdspm_enable_in(hdspm, i, 1);
5616
5617 hdspm->capture_buffer =
0dca1793 5618 (unsigned char *) substream->runtime->dma_area;
e3a471d6
TI		 5619 dev_dbg(hdspm->card->dev,
5620 "Allocated sample buffer for capture at %p\n",
3cee5a60 5621 hdspm->capture_buffer);
763f356c 5622 }
0dca1793 5623
3cee5a60 5624 /*
e3a471d6
TI		 5625 dev_dbg(hdspm->card->dev,
5626 "Allocated sample buffer for %s at 0x%08X\n",
3cee5a60
RB		 5627 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5628 "playback" : "capture",
77a23f26 5629 snd_pcm_sgbuf_get_addr(substream, 0));
0dca1793 5630 */
ffb2c3c0 5631 /*
e3a471d6
TI		 5632 dev_dbg(hdspm->card->dev,
5633 "set_hwparams: %s %d Hz, %d channels, bs = %d\n",
0dca1793
AK		 5634 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5635 "playback" : "capture",
5636 params_rate(params), params_channels(params),
5637 params_buffer_size(params));
5638 */
5639
5640
3ac9b0ac
AK		 5641 /* For AES cards, the float format bit is the same as the
5642 * preferred sync reference. Since we don't want to break
5643 * sync settings, we have to skip the remaining part of this
5644 * function.
5645 */
5646 if (hdspm->io_type == AES32) {
5647 return 0;
5648 }
5649
5650
0dca1793
AK		 5651 /* Switch to native float format if requested */
5652 if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) {
5653 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT))
e3a471d6
TI		 5654 dev_info(hdspm->card->dev,
5655 "Switching to native 32bit LE float format.\n");
0dca1793
AK		 5656
5657 hdspm->control_register |= HDSPe_FLOAT_FORMAT;
5658 } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) {
5659 if (hdspm->control_register & HDSPe_FLOAT_FORMAT)
e3a471d6
TI		 5660 dev_info(hdspm->card->dev,
5661 "Switching to native 32bit LE integer format.\n");
0dca1793
AK		 5662
5663 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT;
5664 }
5665 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5666
763f356c
TI		 5667 return 0;
5668}
5669
98274f07 5670static int snd_hdspm_hw_free(struct snd_pcm_substream *substream)
763f356c
TI		 5671{
5672 int i;
98274f07 5673 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
763f356c
TI		 5674
5675 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5676
0dca1793 5677 /* params_channels(params) should be enough,
763f356c 5678 but to get sure in case of error */
0dca1793 5679 for (i = 0; i < hdspm->max_channels_out; ++i)
763f356c
TI		 5680 snd_hdspm_enable_out(hdspm, i, 0);
5681
5682 hdspm->playback_buffer = NULL;
5683 } else {
0dca1793 5684 for (i = 0; i < hdspm->max_channels_in; ++i)
763f356c
TI		 5685 snd_hdspm_enable_in(hdspm, i, 0);
5686
5687 hdspm->capture_buffer = NULL;
5688
5689 }
5690
5691 snd_pcm_lib_free_pages(substream);
5692
5693 return 0;
5694}
5695
0dca1793 5696
98274f07 5697static int snd_hdspm_channel_info(struct snd_pcm_substream *substream,
0dca1793 5698 struct snd_pcm_channel_info *info)
763f356c 5699{
98274f07 5700 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
763f356c 5701
0dca1793
AK		 5702 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5703 if (snd_BUG_ON(info->channel >= hdspm->max_channels_out)) {
e3a471d6
TI		 5704 dev_info(hdspm->card->dev,
5705 "snd_hdspm_channel_info: output channel out of range (%d)\n",
5706 info->channel);
0dca1793
AK		 5707 return -EINVAL;
5708 }
763f356c 5709
0dca1793 5710 if (hdspm->channel_map_out[info->channel] < 0) {
e3a471d6
TI		 5711 dev_info(hdspm->card->dev,
5712 "snd_hdspm_channel_info: output channel %d mapped out\n",
5713 info->channel);
0dca1793
AK		 5714 return -EINVAL;
5715 }
5716
5717 info->offset = hdspm->channel_map_out[info->channel] *
5718 HDSPM_CHANNEL_BUFFER_BYTES;
5719 } else {
5720 if (snd_BUG_ON(info->channel >= hdspm->max_channels_in)) {
e3a471d6
TI		 5721 dev_info(hdspm->card->dev,
5722 "snd_hdspm_channel_info: input channel out of range (%d)\n",
5723 info->channel);
0dca1793
AK		 5724 return -EINVAL;
5725 }
5726
5727 if (hdspm->channel_map_in[info->channel] < 0) {
e3a471d6
TI		 5728 dev_info(hdspm->card->dev,
5729 "snd_hdspm_channel_info: input channel %d mapped out\n",
5730 info->channel);
0dca1793
AK		 5731 return -EINVAL;
5732 }
5733
5734 info->offset = hdspm->channel_map_in[info->channel] *
5735 HDSPM_CHANNEL_BUFFER_BYTES;
5736 }
763f356c 5737
763f356c
TI		 5738 info->first = 0;
5739 info->step = 32;
5740 return 0;
5741}
5742
0dca1793 5743
98274f07 5744static int snd_hdspm_ioctl(struct snd_pcm_substream *substream,
0dca1793 5745 unsigned int cmd, void *arg)
763f356c
TI		 5746{
5747 switch (cmd) {
5748 case SNDRV_PCM_IOCTL1_RESET:
ef5fa1a4 5749 return snd_hdspm_reset(substream);
763f356c
TI		 5750
5751 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
0dca1793
AK		 5752 {
5753 struct snd_pcm_channel_info *info = arg;
5754 return snd_hdspm_channel_info(substream, info);
5755 }
763f356c
TI		 5756 default:
5757 break;
5758 }
5759
5760 return snd_pcm_lib_ioctl(substream, cmd, arg);
5761}
5762
98274f07 5763static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd)
763f356c 5764{
98274f07
TI		 5765 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5766 struct snd_pcm_substream *other;
763f356c
TI		 5767 int running;
5768
5769 spin_lock(&hdspm->lock);
5770 running = hdspm->running;
5771 switch (cmd) {
5772 case SNDRV_PCM_TRIGGER_START:
5773 running |= 1 << substream->stream;
5774 break;
5775 case SNDRV_PCM_TRIGGER_STOP:
5776 running &= ~(1 << substream->stream);
5777 break;
5778 default:
5779 snd_BUG();
5780 spin_unlock(&hdspm->lock);
5781 return -EINVAL;
5782 }
5783 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5784 other = hdspm->capture_substream;
5785 else
5786 other = hdspm->playback_substream;
5787
5788 if (other) {
98274f07 5789 struct snd_pcm_substream *s;
ef991b95 5790 snd_pcm_group_for_each_entry(s, substream) {
763f356c
TI		 5791 if (s == other) {
5792 snd_pcm_trigger_done(s, substream);
5793 if (cmd == SNDRV_PCM_TRIGGER_START)
5794 running |= 1 << s->stream;
5795 else
5796 running &= ~(1 << s->stream);
5797 goto _ok;
5798 }
5799 }
5800 if (cmd == SNDRV_PCM_TRIGGER_START) {
5801 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK))
0dca1793
AK		 5802 && substream->stream ==
5803 SNDRV_PCM_STREAM_CAPTURE)
763f356c
TI		 5804 hdspm_silence_playback(hdspm);
5805 } else {
5806 if (running &&
0dca1793 5807 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
763f356c
TI		 5808 hdspm_silence_playback(hdspm);
5809 }
5810 } else {
5811 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
5812 hdspm_silence_playback(hdspm);
5813 }
0dca1793 5814_ok:
763f356c
TI		 5815 snd_pcm_trigger_done(substream, substream);
5816 if (!hdspm->running && running)
5817 hdspm_start_audio(hdspm);
5818 else if (hdspm->running && !running)
5819 hdspm_stop_audio(hdspm);
5820 hdspm->running = running;
5821 spin_unlock(&hdspm->lock);
5822
5823 return 0;
5824}
5825
98274f07 5826static int snd_hdspm_prepare(struct snd_pcm_substream *substream)
763f356c
TI		 5827{
5828 return 0;
5829}
5830
98274f07 5831static struct snd_pcm_hardware snd_hdspm_playback_subinfo = {
763f356c
TI		 5832 .info = (SNDRV_PCM_INFO_MMAP |
5833 SNDRV_PCM_INFO_MMAP_VALID |
5834 SNDRV_PCM_INFO_NONINTERLEAVED |
5835 SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE),
5836 .formats = SNDRV_PCM_FMTBIT_S32_LE,
5837 .rates = (SNDRV_PCM_RATE_32000 |
5838 SNDRV_PCM_RATE_44100 |
5839 SNDRV_PCM_RATE_48000 |
5840 SNDRV_PCM_RATE_64000 |
3cee5a60
RB		 5841 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5842 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ),
763f356c 5843 .rate_min = 32000,
3cee5a60 5844 .rate_max = 192000,
763f356c
TI		 5845 .channels_min = 1,
5846 .channels_max = HDSPM_MAX_CHANNELS,
5847 .buffer_bytes_max =
5848 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
1b6fa108 5849 .period_bytes_min = (32 * 4),
52e6fb48 5850 .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
763f356c 5851 .periods_min = 2,
0dca1793 5852 .periods_max = 512,
763f356c
TI		 5853 .fifo_size = 0
5854};
5855
98274f07 5856static struct snd_pcm_hardware snd_hdspm_capture_subinfo = {
763f356c
TI		 5857 .info = (SNDRV_PCM_INFO_MMAP |
5858 SNDRV_PCM_INFO_MMAP_VALID |
5859 SNDRV_PCM_INFO_NONINTERLEAVED |
5860 SNDRV_PCM_INFO_SYNC_START),
5861 .formats = SNDRV_PCM_FMTBIT_S32_LE,
5862 .rates = (SNDRV_PCM_RATE_32000 |
5863 SNDRV_PCM_RATE_44100 |
5864 SNDRV_PCM_RATE_48000 |
5865 SNDRV_PCM_RATE_64000 |
3cee5a60
RB		 5866 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5867 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000),
763f356c 5868 .rate_min = 32000,
3cee5a60 5869 .rate_max = 192000,
763f356c
TI		 5870 .channels_min = 1,
5871 .channels_max = HDSPM_MAX_CHANNELS,
5872 .buffer_bytes_max =
5873 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
1b6fa108 5874 .period_bytes_min = (32 * 4),
52e6fb48 5875 .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
763f356c 5876 .periods_min = 2,
0dca1793 5877 .periods_max = 512,
763f356c
TI		 5878 .fifo_size = 0
5879};
5880
0dca1793
AK		 5881static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
5882 struct snd_pcm_hw_rule *rule)
5883{
5884 struct hdspm *hdspm = rule->private;
5885 struct snd_interval *c =
5886 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5887 struct snd_interval *r =
5888 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5889
5890 if (r->min > 96000 && r->max <= 192000) {
5891 struct snd_interval t = {
5892 .min = hdspm->qs_in_channels,
5893 .max = hdspm->qs_in_channels,
5894 .integer = 1,
5895 };
5896 return snd_interval_refine(c, &t);
5897 } else if (r->min > 48000 && r->max <= 96000) {
5898 struct snd_interval t = {
5899 .min = hdspm->ds_in_channels,
5900 .max = hdspm->ds_in_channels,
5901 .integer = 1,
5902 };
5903 return snd_interval_refine(c, &t);
5904 } else if (r->max < 64000) {
5905 struct snd_interval t = {
5906 .min = hdspm->ss_in_channels,
5907 .max = hdspm->ss_in_channels,
5908 .integer = 1,
5909 };
5910 return snd_interval_refine(c, &t);
5911 }
5912
5913 return 0;
5914}
763f356c 5915
0dca1793 5916static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
98274f07 5917 struct snd_pcm_hw_rule * rule)
763f356c 5918{
98274f07
TI		 5919 struct hdspm *hdspm = rule->private;
5920 struct snd_interval *c =
763f356c 5921 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
98274f07 5922 struct snd_interval *r =
763f356c
TI		 5923 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5924
0dca1793
AK		 5925 if (r->min > 96000 && r->max <= 192000) {
5926 struct snd_interval t = {
5927 .min = hdspm->qs_out_channels,
5928 .max = hdspm->qs_out_channels,
5929 .integer = 1,
5930 };
5931 return snd_interval_refine(c, &t);
5932 } else if (r->min > 48000 && r->max <= 96000) {
98274f07 5933 struct snd_interval t = {
0dca1793
AK		 5934 .min = hdspm->ds_out_channels,
5935 .max = hdspm->ds_out_channels,
763f356c
TI		 5936 .integer = 1,
5937 };
5938 return snd_interval_refine(c, &t);
5939 } else if (r->max < 64000) {
98274f07 5940 struct snd_interval t = {
0dca1793
AK		 5941 .min = hdspm->ss_out_channels,
5942 .max = hdspm->ss_out_channels,
763f356c
TI		 5943 .integer = 1,
5944 };
5945 return snd_interval_refine(c, &t);
0dca1793 5946 } else {
763f356c
TI		 5947 }
5948 return 0;
5949}
5950
0dca1793 5951static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
98274f07 5952 struct snd_pcm_hw_rule * rule)
763f356c 5953{
98274f07
TI		 5954 struct hdspm *hdspm = rule->private;
5955 struct snd_interval *c =
763f356c 5956 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
98274f07 5957 struct snd_interval *r =
763f356c
TI		 5958 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5959
0dca1793 5960 if (c->min >= hdspm->ss_in_channels) {
98274f07 5961 struct snd_interval t = {
763f356c
TI		 5962 .min = 32000,
5963 .max = 48000,
5964 .integer = 1,
5965 };
5966 return snd_interval_refine(r, &t);
0dca1793
AK		 5967 } else if (c->max <= hdspm->qs_in_channels) {
5968 struct snd_interval t = {
5969 .min = 128000,
5970 .max = 192000,
5971 .integer = 1,
5972 };
5973 return snd_interval_refine(r, &t);
5974 } else if (c->max <= hdspm->ds_in_channels) {
98274f07 5975 struct snd_interval t = {
763f356c
TI		 5976 .min = 64000,
5977 .max = 96000,
5978 .integer = 1,
5979 };
0dca1793
AK		 5980 return snd_interval_refine(r, &t);
5981 }
5982
5983 return 0;
5984}
5985static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
5986 struct snd_pcm_hw_rule *rule)
5987{
5988 struct hdspm *hdspm = rule->private;
5989 struct snd_interval *c =
5990 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5991 struct snd_interval *r =
5992 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
763f356c 5993
0dca1793
AK		 5994 if (c->min >= hdspm->ss_out_channels) {
5995 struct snd_interval t = {
5996 .min = 32000,
5997 .max = 48000,
5998 .integer = 1,
5999 };
6000 return snd_interval_refine(r, &t);
6001 } else if (c->max <= hdspm->qs_out_channels) {
6002 struct snd_interval t = {
6003 .min = 128000,
6004 .max = 192000,
6005 .integer = 1,
6006 };
6007 return snd_interval_refine(r, &t);
6008 } else if (c->max <= hdspm->ds_out_channels) {
6009 struct snd_interval t = {
6010 .min = 64000,
6011 .max = 96000,
6012 .integer = 1,
6013 };
763f356c
TI		 6014 return snd_interval_refine(r, &t);
6015 }
0dca1793 6016
763f356c
TI		 6017 return 0;
6018}
6019
0dca1793 6020static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params,
ffb2c3c0
RB		 6021 struct snd_pcm_hw_rule *rule)
6022{
6023 unsigned int list[3];
6024 struct hdspm *hdspm = rule->private;
6025 struct snd_interval *c = hw_param_interval(params,
6026 SNDRV_PCM_HW_PARAM_CHANNELS);
0dca1793
AK		 6027
6028 list[0] = hdspm->qs_in_channels;
6029 list[1] = hdspm->ds_in_channels;
6030 list[2] = hdspm->ss_in_channels;
6031 return snd_interval_list(c, 3, list, 0);
6032}
6033
6034static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params,
6035 struct snd_pcm_hw_rule *rule)
6036{
6037 unsigned int list[3];
6038 struct hdspm *hdspm = rule->private;
6039 struct snd_interval *c = hw_param_interval(params,
6040 SNDRV_PCM_HW_PARAM_CHANNELS);
6041
6042 list[0] = hdspm->qs_out_channels;
6043 list[1] = hdspm->ds_out_channels;
6044 list[2] = hdspm->ss_out_channels;
6045 return snd_interval_list(c, 3, list, 0);
ffb2c3c0
RB		 6046}
6047
6048
bdf84db7 6049static const unsigned int hdspm_aes32_sample_rates[] = {
ef5fa1a4
TI		 6050 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000
6051};
ffb2c3c0 6052
bdf84db7 6053static const struct snd_pcm_hw_constraint_list
ef5fa1a4 6054hdspm_hw_constraints_aes32_sample_rates = {
ffb2c3c0
RB		 6055 .count = ARRAY_SIZE(hdspm_aes32_sample_rates),
6056 .list = hdspm_aes32_sample_rates,
6057 .mask = 0
6058};
6059
5ecc5dc7 6060static int snd_hdspm_open(struct snd_pcm_substream *substream)
763f356c 6061{
98274f07
TI		 6062 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6063 struct snd_pcm_runtime *runtime = substream->runtime;
5ecc5dc7 6064 bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
763f356c 6065
763f356c 6066 spin_lock_irq(&hdspm->lock);
763f356c 6067 snd_pcm_set_sync(substream);
5ecc5dc7
AK		 6068 runtime->hw = (playback) ? snd_hdspm_playback_subinfo :
6069 snd_hdspm_capture_subinfo;
763f356c 6070
5ecc5dc7
AK		 6071 if (playback) {
6072 if (hdspm->capture_substream == NULL)
6073 hdspm_stop_audio(hdspm);
0dca1793 6074
5ecc5dc7
AK		 6075 hdspm->playback_pid = current->pid;
6076 hdspm->playback_substream = substream;
6077 } else {
6078 if (hdspm->playback_substream == NULL)
6079 hdspm_stop_audio(hdspm);
763f356c 6080
5ecc5dc7
AK		 6081 hdspm->capture_pid = current->pid;
6082 hdspm->capture_substream = substream;
6083 }
763f356c
TI		 6084
6085 spin_unlock_irq(&hdspm->lock);
6086
6087 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
d877681d 6088 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
763f356c 6089
0dca1793
AK		 6090 switch (hdspm->io_type) {
6091 case AIO:
6092 case RayDAT:
d877681d
TI		 6093 snd_pcm_hw_constraint_minmax(runtime,
6094 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6095 32, 4096);
6096 /* RayDAT & AIO have a fixed buffer of 16384 samples per channel */
b4ffc1be 6097 snd_pcm_hw_constraint_single(runtime,
d877681d 6098 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
b4ffc1be 6099 16384);
0dca1793
AK		 6100 break;
6101
6102 default:
d877681d
TI		 6103 snd_pcm_hw_constraint_minmax(runtime,
6104 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6105 64, 8192);
b4ffc1be
LPC		 6106 snd_pcm_hw_constraint_single(runtime,
6107 SNDRV_PCM_HW_PARAM_PERIODS, 2);
d877681d 6108 break;
0dca1793 6109 }
763f356c 6110
0dca1793 6111 if (AES32 == hdspm->io_type) {
3fa9e3d2 6112 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
ffb2c3c0
RB		 6113 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6114 &hdspm_hw_constraints_aes32_sample_rates);
6115 } else {
ffb2c3c0 6116 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
5ecc5dc7
AK		 6117 (playback ?
6118 snd_hdspm_hw_rule_rate_out_channels :
6119 snd_hdspm_hw_rule_rate_in_channels), hdspm,
0dca1793 6120 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
ffb2c3c0 6121 }
88fabbfc
AK		 6122
6123 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
5ecc5dc7
AK		 6124 (playback ? snd_hdspm_hw_rule_out_channels :
6125 snd_hdspm_hw_rule_in_channels), hdspm,
88fabbfc
AK		 6126 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6127
6128 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
5ecc5dc7
AK		 6129 (playback ? snd_hdspm_hw_rule_out_channels_rate :
6130 snd_hdspm_hw_rule_in_channels_rate), hdspm,
88fabbfc
AK		 6131 SNDRV_PCM_HW_PARAM_RATE, -1);
6132
763f356c
TI		 6133 return 0;
6134}
6135
8b73b867 6136static int snd_hdspm_release(struct snd_pcm_substream *substream)
763f356c 6137{
98274f07 6138 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
8b73b867 6139 bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
763f356c
TI		 6140
6141 spin_lock_irq(&hdspm->lock);
6142
8b73b867
AK		 6143 if (playback) {
6144 hdspm->playback_pid = -1;
6145 hdspm->playback_substream = NULL;
6146 } else {
6147 hdspm->capture_pid = -1;
6148 hdspm->capture_substream = NULL;
6149 }
763f356c
TI		 6150
6151 spin_unlock_irq(&hdspm->lock);
6152
6153 return 0;
6154}
6155
0dca1793
AK		 6156static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file)
6157{
6158 /* we have nothing to initialize but the call is required */
6159 return 0;
6160}
6161
6162static inline int copy_u32_le(void __user *dest, void __iomem *src)
6163{
6164 u32 val = readl(src);
6165 return copy_to_user(dest, &val, 4);
6166}
6167
6168static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file,
2ca595ab 6169 unsigned int cmd, unsigned long arg)
763f356c 6170{
0dca1793 6171 void __user *argp = (void __user *)arg;
ef5fa1a4 6172 struct hdspm *hdspm = hw->private_data;
98274f07 6173 struct hdspm_mixer_ioctl mixer;
0dca1793
AK		 6174 struct hdspm_config info;
6175 struct hdspm_status status;
98274f07 6176 struct hdspm_version hdspm_version;
730a5865 6177 struct hdspm_peak_rms *levels;
0dca1793
AK		 6178 struct hdspm_ltc ltc;
6179 unsigned int statusregister;
6180 long unsigned int s;
6181 int i = 0;
763f356c
TI		 6182
6183 switch (cmd) {
6184
763f356c 6185 case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS:
730a5865 6186 levels = &hdspm->peak_rms;
0dca1793 6187 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
730a5865 6188 levels->input_peaks[i] =
0dca1793
AK		 6189 readl(hdspm->iobase +
6190 HDSPM_MADI_INPUT_PEAK + i*4);
730a5865 6191 levels->playback_peaks[i] =
0dca1793
AK		 6192 readl(hdspm->iobase +
6193 HDSPM_MADI_PLAYBACK_PEAK + i*4);
730a5865 6194 levels->output_peaks[i] =
0dca1793
AK		 6195 readl(hdspm->iobase +
6196 HDSPM_MADI_OUTPUT_PEAK + i*4);
6197
730a5865 6198 levels->input_rms[i] =
0dca1793
AK		 6199 ((uint64_t) readl(hdspm->iobase +
6200 HDSPM_MADI_INPUT_RMS_H + i*4) << 32) |
6201 (uint64_t) readl(hdspm->iobase +
6202 HDSPM_MADI_INPUT_RMS_L + i*4);
730a5865 6203 levels->playback_rms[i] =
0dca1793
AK		 6204 ((uint64_t)readl(hdspm->iobase +
6205 HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) |
6206 (uint64_t)readl(hdspm->iobase +
6207 HDSPM_MADI_PLAYBACK_RMS_L + i*4);
730a5865 6208 levels->output_rms[i] =
0dca1793
AK		 6209 ((uint64_t)readl(hdspm->iobase +
6210 HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) |
6211 (uint64_t)readl(hdspm->iobase +
6212 HDSPM_MADI_OUTPUT_RMS_L + i*4);
6213 }
6214
6215 if (hdspm->system_sample_rate > 96000) {
730a5865 6216 levels->speed = qs;
0dca1793 6217 } else if (hdspm->system_sample_rate > 48000) {
730a5865 6218 levels->speed = ds;
0dca1793 6219 } else {
730a5865 6220 levels->speed = ss;
0dca1793 6221 }
730a5865 6222 levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
0dca1793 6223
730a5865 6224 s = copy_to_user(argp, levels, sizeof(struct hdspm_peak_rms));
0dca1793 6225 if (0 != s) {
e3a471d6 6226 /* dev_err(hdspm->card->dev, "copy_to_user(.., .., %lu): %lu
0dca1793
AK		 6227 [Levels]\n", sizeof(struct hdspm_peak_rms), s);
6228 */
763f356c 6229 return -EFAULT;
0dca1793
AK		 6230 }
6231 break;
6232
6233 case SNDRV_HDSPM_IOCTL_GET_LTC:
6234 ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
6235 i = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
6236 if (i & HDSPM_TCO1_LTC_Input_valid) {
6237 switch (i & (HDSPM_TCO1_LTC_Format_LSB |
6238 HDSPM_TCO1_LTC_Format_MSB)) {
6239 case 0:
6240 ltc.format = fps_24;
6241 break;
6242 case HDSPM_TCO1_LTC_Format_LSB:
6243 ltc.format = fps_25;
6244 break;
6245 case HDSPM_TCO1_LTC_Format_MSB:
6246 ltc.format = fps_2997;
6247 break;
6248 default:
17d2f008 6249 ltc.format = fps_30;
0dca1793
AK		 6250 break;
6251 }
6252 if (i & HDSPM_TCO1_set_drop_frame_flag) {
6253 ltc.frame = drop_frame;
6254 } else {
6255 ltc.frame = full_frame;
6256 }
6257 } else {
6258 ltc.format = format_invalid;
6259 ltc.frame = frame_invalid;
6260 }
6261 if (i & HDSPM_TCO1_Video_Input_Format_NTSC) {
6262 ltc.input_format = ntsc;
6263 } else if (i & HDSPM_TCO1_Video_Input_Format_PAL) {
6264 ltc.input_format = pal;
6265 } else {
6266 ltc.input_format = no_video;
6267 }
6268
6269 s = copy_to_user(argp, &ltc, sizeof(struct hdspm_ltc));
6270 if (0 != s) {
6271 /*
e3a471d6 6272 dev_err(hdspm->card->dev, "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */
763f356c 6273 return -EFAULT;
0dca1793 6274 }
763f356c
TI		 6275
6276 break;
763f356c 6277
0dca1793 6278 case SNDRV_HDSPM_IOCTL_GET_CONFIG:
763f356c 6279
4ab69a2b 6280 memset(&info, 0, sizeof(info));
763f356c 6281 spin_lock_irq(&hdspm->lock);
ef5fa1a4
TI		 6282 info.pref_sync_ref = hdspm_pref_sync_ref(hdspm);
6283 info.wordclock_sync_check = hdspm_wc_sync_check(hdspm);
763f356c
TI		 6284
6285 info.system_sample_rate = hdspm->system_sample_rate;
6286 info.autosync_sample_rate =
0dca1793 6287 hdspm_external_sample_rate(hdspm);
ef5fa1a4
TI		 6288 info.system_clock_mode = hdspm_system_clock_mode(hdspm);
6289 info.clock_source = hdspm_clock_source(hdspm);
6290 info.autosync_ref = hdspm_autosync_ref(hdspm);
c9e1668c 6291 info.line_out = hdspm_toggle_setting(hdspm, HDSPM_LineOut);
763f356c
TI		 6292 info.passthru = 0;
6293 spin_unlock_irq(&hdspm->lock);
2ca595ab 6294 if (copy_to_user(argp, &info, sizeof(info)))
763f356c
TI		 6295 return -EFAULT;
6296 break;
6297
0dca1793 6298 case SNDRV_HDSPM_IOCTL_GET_STATUS:
643d6bbb
DC		 6299 memset(&status, 0, sizeof(status));
6300
0dca1793
AK		 6301 status.card_type = hdspm->io_type;
6302
6303 status.autosync_source = hdspm_autosync_ref(hdspm);
6304
6305 status.card_clock = 110069313433624ULL;
6306 status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
6307
6308 switch (hdspm->io_type) {
6309 case MADI:
6310 case MADIface:
6311 status.card_specific.madi.sync_wc =
6312 hdspm_wc_sync_check(hdspm);
6313 status.card_specific.madi.sync_madi =
6314 hdspm_madi_sync_check(hdspm);
6315 status.card_specific.madi.sync_tco =
6316 hdspm_tco_sync_check(hdspm);
6317 status.card_specific.madi.sync_in =
6318 hdspm_sync_in_sync_check(hdspm);
6319
6320 statusregister =
6321 hdspm_read(hdspm, HDSPM_statusRegister);
6322 status.card_specific.madi.madi_input =
6323 (statusregister & HDSPM_AB_int) ? 1 : 0;
6324 status.card_specific.madi.channel_format =
9e6ff520 6325 (statusregister & HDSPM_RX_64ch) ? 1 : 0;
0dca1793
AK		 6326 /* TODO: Mac driver sets it when f_s>48kHz */
6327 status.card_specific.madi.frame_format = 0;
6328
6329 default:
6330 break;
6331 }
6332
2ca595ab 6333 if (copy_to_user(argp, &status, sizeof(status)))
0dca1793
AK		 6334 return -EFAULT;
6335
6336
6337 break;
6338
763f356c 6339 case SNDRV_HDSPM_IOCTL_GET_VERSION:
643d6bbb
DC		 6340 memset(&hdspm_version, 0, sizeof(hdspm_version));
6341
0dca1793 6342 hdspm_version.card_type = hdspm->io_type;
57a4451d 6343 strlcpy(hdspm_version.cardname, hdspm->card_name,
0dca1793 6344 sizeof(hdspm_version.cardname));
7d53a631 6345 hdspm_version.serial = hdspm->serial;
763f356c 6346 hdspm_version.firmware_rev = hdspm->firmware_rev;
0dca1793
AK		 6347 hdspm_version.addons = 0;
6348 if (hdspm->tco)
6349 hdspm_version.addons |= HDSPM_ADDON_TCO;
6350
2ca595ab 6351 if (copy_to_user(argp, &hdspm_version,
0dca1793 6352 sizeof(hdspm_version)))
763f356c
TI		 6353 return -EFAULT;
6354 break;
6355
6356 case SNDRV_HDSPM_IOCTL_GET_MIXER:
2ca595ab 6357 if (copy_from_user(&mixer, argp, sizeof(mixer)))
763f356c 6358 return -EFAULT;
ef5fa1a4 6359 if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer,
0dca1793 6360 sizeof(struct hdspm_mixer)))
763f356c
TI		 6361 return -EFAULT;
6362 break;
6363
6364 default:
6365 return -EINVAL;
6366 }
6367 return 0;
6368}
6369
6769e988 6370static const struct snd_pcm_ops snd_hdspm_ops = {
5ecc5dc7 6371 .open = snd_hdspm_open,
8b73b867 6372 .close = snd_hdspm_release,
763f356c
TI		 6373 .ioctl = snd_hdspm_ioctl,
6374 .hw_params = snd_hdspm_hw_params,
6375 .hw_free = snd_hdspm_hw_free,
6376 .prepare = snd_hdspm_prepare,
6377 .trigger = snd_hdspm_trigger,
6378 .pointer = snd_hdspm_hw_pointer,
763f356c
TI		 6379 .page = snd_pcm_sgbuf_ops_page,
6380};
6381
e23e7a14
BP		 6382static int snd_hdspm_create_hwdep(struct snd_card *card,
6383 struct hdspm *hdspm)
763f356c 6384{
98274f07 6385 struct snd_hwdep *hw;
763f356c
TI		 6386 int err;
6387
ef5fa1a4
TI		 6388 err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw);
6389 if (err < 0)
763f356c
TI		 6390 return err;
6391
6392 hdspm->hwdep = hw;
6393 hw->private_data = hdspm;
6394 strcpy(hw->name, "HDSPM hwdep interface");
6395
0dca1793 6396 hw->ops.open = snd_hdspm_hwdep_dummy_op;
763f356c 6397 hw->ops.ioctl = snd_hdspm_hwdep_ioctl;
8de5d6f1 6398 hw->ops.ioctl_compat = snd_hdspm_hwdep_ioctl;
0dca1793 6399 hw->ops.release = snd_hdspm_hwdep_dummy_op;
763f356c
TI		 6400
6401 return 0;
6402}
6403
6404
6405/*------------------------------------------------------------
0dca1793 6406 memory interface
763f356c 6407 ------------------------------------------------------------*/
e23e7a14 6408static int snd_hdspm_preallocate_memory(struct hdspm *hdspm)
763f356c
TI		 6409{
6410 int err;
98274f07 6411 struct snd_pcm *pcm;
763f356c
TI		 6412 size_t wanted;
6413
6414 pcm = hdspm->pcm;
6415
3cee5a60 6416 wanted = HDSPM_DMA_AREA_BYTES;
763f356c 6417
ef5fa1a4 6418 err =
763f356c 6419 snd_pcm_lib_preallocate_pages_for_all(pcm,
0dca1793 6420 SNDRV_DMA_TYPE_DEV_SG,
763f356c
TI		 6421 snd_dma_pci_data(hdspm->pci),
6422 wanted,
ef5fa1a4
TI		 6423 wanted);
6424 if (err < 0) {
e3a471d6
TI		 6425 dev_dbg(hdspm->card->dev,
6426 "Could not preallocate %zd Bytes\n", wanted);
763f356c
TI		 6427
6428 return err;
6429 } else
e3a471d6
TI		 6430 dev_dbg(hdspm->card->dev,
6431 " Preallocated %zd Bytes\n", wanted);
763f356c
TI		 6432
6433 return 0;
6434}
6435
0dca1793
AK		 6436
6437static void hdspm_set_sgbuf(struct hdspm *hdspm,
77a23f26 6438 struct snd_pcm_substream *substream,
763f356c
TI		 6439 unsigned int reg, int channels)
6440{
6441 int i;
0dca1793
AK		 6442
6443 /* continuous memory segment */
763f356c
TI		 6444 for (i = 0; i < (channels * 16); i++)
6445 hdspm_write(hdspm, reg + 4 * i,
0dca1793 6446 snd_pcm_sgbuf_get_addr(substream, 4096 * i));
763f356c
TI		 6447}
6448
0dca1793 6449
763f356c 6450/* ------------- ALSA Devices ---------------------------- */
e23e7a14
BP		 6451static int snd_hdspm_create_pcm(struct snd_card *card,
6452 struct hdspm *hdspm)
763f356c 6453{
98274f07 6454 struct snd_pcm *pcm;
763f356c
TI		 6455 int err;
6456
ef5fa1a4
TI		 6457 err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm);
6458 if (err < 0)
763f356c
TI		 6459 return err;
6460
6461 hdspm->pcm = pcm;
6462 pcm->private_data = hdspm;
6463 strcpy(pcm->name, hdspm->card_name);
6464
6465 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
0c8d9485 6466 &snd_hdspm_ops);
763f356c 6467 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
0c8d9485 6468 &snd_hdspm_ops);
763f356c
TI		 6469
6470 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
6471
ef5fa1a4
TI		 6472 err = snd_hdspm_preallocate_memory(hdspm);
6473 if (err < 0)
763f356c
TI		 6474 return err;
6475
6476 return 0;
6477}
6478
98274f07 6479static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm)
763f356c 6480{
7c7102b7
AK		 6481 int i;
6482
6483 for (i = 0; i < hdspm->midiPorts; i++)
6484 snd_hdspm_flush_midi_input(hdspm, i);
763f356c
TI		 6485}
6486
e23e7a14
BP		 6487static int snd_hdspm_create_alsa_devices(struct snd_card *card,
6488 struct hdspm *hdspm)
763f356c 6489{
0dca1793 6490 int err, i;
763f356c 6491
e3a471d6 6492 dev_dbg(card->dev, "Create card...\n");
ef5fa1a4
TI		 6493 err = snd_hdspm_create_pcm(card, hdspm);
6494 if (err < 0)
763f356c
TI		 6495 return err;
6496
0dca1793
AK		 6497 i = 0;
6498 while (i < hdspm->midiPorts) {
6499 err = snd_hdspm_create_midi(card, hdspm, i);
6500 if (err < 0) {
6501 return err;
6502 }
6503 i++;
6504 }
763f356c 6505
ef5fa1a4
TI		 6506 err = snd_hdspm_create_controls(card, hdspm);
6507 if (err < 0)
763f356c
TI		 6508 return err;
6509
ef5fa1a4
TI		 6510 err = snd_hdspm_create_hwdep(card, hdspm);
6511 if (err < 0)
763f356c
TI		 6512 return err;
6513
e3a471d6 6514 dev_dbg(card->dev, "proc init...\n");
763f356c
TI		 6515 snd_hdspm_proc_init(hdspm);
6516
6517 hdspm->system_sample_rate = -1;
6518 hdspm->last_external_sample_rate = -1;
6519 hdspm->last_internal_sample_rate = -1;
6520 hdspm->playback_pid = -1;
6521 hdspm->capture_pid = -1;
6522 hdspm->capture_substream = NULL;
6523 hdspm->playback_substream = NULL;
6524
e3a471d6 6525 dev_dbg(card->dev, "Set defaults...\n");
ef5fa1a4
TI		 6526 err = snd_hdspm_set_defaults(hdspm);
6527 if (err < 0)
763f356c
TI		 6528 return err;
6529
e3a471d6 6530 dev_dbg(card->dev, "Update mixer controls...\n");
763f356c
TI		 6531 hdspm_update_simple_mixer_controls(hdspm);
6532
e3a471d6 6533 dev_dbg(card->dev, "Initializeing complete ???\n");
763f356c 6534
ef5fa1a4
TI		 6535 err = snd_card_register(card);
6536 if (err < 0) {
e3a471d6 6537 dev_err(card->dev, "error registering card\n");
763f356c
TI		 6538 return err;
6539 }
6540
e3a471d6 6541 dev_dbg(card->dev, "... yes now\n");
763f356c
TI		 6542
6543 return 0;
6544}
6545
e23e7a14
BP		 6546static int snd_hdspm_create(struct snd_card *card,
6547 struct hdspm *hdspm)
6548{
0dca1793 6549
763f356c
TI		 6550 struct pci_dev *pci = hdspm->pci;
6551 int err;
763f356c
TI		 6552 unsigned long io_extent;
6553
6554 hdspm->irq = -1;
763f356c
TI		 6555 hdspm->card = card;
6556
6557 spin_lock_init(&hdspm->lock);
6558
763f356c 6559 pci_read_config_word(hdspm->pci,
0dca1793 6560 PCI_CLASS_REVISION, &hdspm->firmware_rev);
3cee5a60 6561
763f356c 6562 strcpy(card->mixername, "Xilinx FPGA");
0dca1793
AK		 6563 strcpy(card->driver, "HDSPM");
6564
6565 switch (hdspm->firmware_rev) {
0dca1793
AK		 6566 case HDSPM_RAYDAT_REV:
6567 hdspm->io_type = RayDAT;
6568 hdspm->card_name = "RME RayDAT";
6569 hdspm->midiPorts = 2;
6570 break;
6571 case HDSPM_AIO_REV:
6572 hdspm->io_type = AIO;
6573 hdspm->card_name = "RME AIO";
6574 hdspm->midiPorts = 1;
6575 break;
6576 case HDSPM_MADIFACE_REV:
6577 hdspm->io_type = MADIface;
6578 hdspm->card_name = "RME MADIface";
6579 hdspm->midiPorts = 1;
6580 break;
5027f347 6581 default:
c09403dc
AK		 6582 if ((hdspm->firmware_rev == 0xf0) ||
6583 ((hdspm->firmware_rev >= 0xe6) &&
6584 (hdspm->firmware_rev <= 0xea))) {
6585 hdspm->io_type = AES32;
6586 hdspm->card_name = "RME AES32";
6587 hdspm->midiPorts = 2;
05c7cc9c 6588 } else if ((hdspm->firmware_rev == 0xd2) ||
c09403dc
AK		 6589 ((hdspm->firmware_rev >= 0xc8) &&
6590 (hdspm->firmware_rev <= 0xcf))) {
6591 hdspm->io_type = MADI;
6592 hdspm->card_name = "RME MADI";
6593 hdspm->midiPorts = 3;
6594 } else {
e3a471d6
TI		 6595 dev_err(card->dev,
6596 "unknown firmware revision %x\n",
5027f347 6597 hdspm->firmware_rev);
c09403dc
AK		 6598 return -ENODEV;
6599 }
3cee5a60 6600 }
763f356c 6601
ef5fa1a4
TI		 6602 err = pci_enable_device(pci);
6603 if (err < 0)
763f356c
TI		 6604 return err;
6605
6606 pci_set_master(hdspm->pci);
6607
ef5fa1a4
TI		 6608 err = pci_request_regions(pci, "hdspm");
6609 if (err < 0)
763f356c
TI		 6610 return err;
6611
6612 hdspm->port = pci_resource_start(pci, 0);
6613 io_extent = pci_resource_len(pci, 0);
6614
e3a471d6 6615 dev_dbg(card->dev, "grabbed memory region 0x%lx-0x%lx\n",
0dca1793 6616 hdspm->port, hdspm->port + io_extent - 1);
763f356c 6617
ef5fa1a4
TI		 6618 hdspm->iobase = ioremap_nocache(hdspm->port, io_extent);
6619 if (!hdspm->iobase) {
e3a471d6 6620 dev_err(card->dev, "unable to remap region 0x%lx-0x%lx\n",
0dca1793 6621 hdspm->port, hdspm->port + io_extent - 1);
763f356c
TI		 6622 return -EBUSY;
6623 }
e3a471d6 6624 dev_dbg(card->dev, "remapped region (0x%lx) 0x%lx-0x%lx\n",
0dca1793
AK		 6625 (unsigned long)hdspm->iobase, hdspm->port,
6626 hdspm->port + io_extent - 1);
763f356c
TI		 6627
6628 if (request_irq(pci->irq, snd_hdspm_interrupt,
934c2b6d 6629 IRQF_SHARED, KBUILD_MODNAME, hdspm)) {
e3a471d6 6630 dev_err(card->dev, "unable to use IRQ %d\n", pci->irq);
763f356c
TI		 6631 return -EBUSY;
6632 }
6633
e3a471d6 6634 dev_dbg(card->dev, "use IRQ %d\n", pci->irq);
763f356c
TI		 6635
6636 hdspm->irq = pci->irq;
763f356c 6637
e3a471d6 6638 dev_dbg(card->dev, "kmalloc Mixer memory of %zd Bytes\n",
0dca1793 6639 sizeof(struct hdspm_mixer));
ef5fa1a4
TI		 6640 hdspm->mixer = kzalloc(sizeof(struct hdspm_mixer), GFP_KERNEL);
6641 if (!hdspm->mixer) {
e3a471d6
TI		 6642 dev_err(card->dev,
6643 "unable to kmalloc Mixer memory of %d Bytes\n",
0dca1793 6644 (int)sizeof(struct hdspm_mixer));
b17cbdd8 6645 return -ENOMEM;
763f356c
TI		 6646 }
6647
0dca1793
AK		 6648 hdspm->port_names_in = NULL;
6649 hdspm->port_names_out = NULL;
6650
6651 switch (hdspm->io_type) {
6652 case AES32:
d2d10a21
AK		 6653 hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS;
6654 hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS;
6655 hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS;
432d2500
AK		 6656
6657 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6658 channel_map_aes32;
6659 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6660 channel_map_aes32;
6661 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6662 channel_map_aes32;
6663 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6664 texts_ports_aes32;
6665 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6666 texts_ports_aes32;
6667 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6668 texts_ports_aes32;
6669
d2d10a21
AK		 6670 hdspm->max_channels_out = hdspm->max_channels_in =
6671 AES32_CHANNELS;
432d2500
AK		 6672 hdspm->port_names_in = hdspm->port_names_out =
6673 texts_ports_aes32;
6674 hdspm->channel_map_in = hdspm->channel_map_out =
6675 channel_map_aes32;
6676
0dca1793
AK		 6677 break;
6678
6679 case MADI:
6680 case MADIface:
6681 hdspm->ss_in_channels = hdspm->ss_out_channels =
6682 MADI_SS_CHANNELS;
6683 hdspm->ds_in_channels = hdspm->ds_out_channels =
6684 MADI_DS_CHANNELS;
6685 hdspm->qs_in_channels = hdspm->qs_out_channels =
6686 MADI_QS_CHANNELS;
6687
6688 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6689 channel_map_unity_ss;
01e96078 6690 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
0dca1793 6691 channel_map_unity_ss;
01e96078 6692 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
0dca1793
AK		 6693 channel_map_unity_ss;
6694
6695 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6696 texts_ports_madi;
6697 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6698 texts_ports_madi;
6699 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6700 texts_ports_madi;
6701 break;
6702
6703 case AIO:
0dca1793
AK		 6704 hdspm->ss_in_channels = AIO_IN_SS_CHANNELS;
6705 hdspm->ds_in_channels = AIO_IN_DS_CHANNELS;
6706 hdspm->qs_in_channels = AIO_IN_QS_CHANNELS;
6707 hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS;
6708 hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS;
6709 hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS;
6710
3de9db26 6711 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) {
e3a471d6 6712 dev_info(card->dev, "AEB input board found\n");
3de9db26
AK		 6713 hdspm->ss_in_channels += 4;
6714 hdspm->ds_in_channels += 4;
6715 hdspm->qs_in_channels += 4;
6716 }
6717
6718 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBO_D)) {
e3a471d6 6719 dev_info(card->dev, "AEB output board found\n");
3de9db26
AK		 6720 hdspm->ss_out_channels += 4;
6721 hdspm->ds_out_channels += 4;
6722 hdspm->qs_out_channels += 4;
6723 }
6724
0dca1793
AK		 6725 hdspm->channel_map_out_ss = channel_map_aio_out_ss;
6726 hdspm->channel_map_out_ds = channel_map_aio_out_ds;
6727 hdspm->channel_map_out_qs = channel_map_aio_out_qs;
6728
6729 hdspm->channel_map_in_ss = channel_map_aio_in_ss;
6730 hdspm->channel_map_in_ds = channel_map_aio_in_ds;
6731 hdspm->channel_map_in_qs = channel_map_aio_in_qs;
6732
6733 hdspm->port_names_in_ss = texts_ports_aio_in_ss;
6734 hdspm->port_names_out_ss = texts_ports_aio_out_ss;
6735 hdspm->port_names_in_ds = texts_ports_aio_in_ds;
6736 hdspm->port_names_out_ds = texts_ports_aio_out_ds;
6737 hdspm->port_names_in_qs = texts_ports_aio_in_qs;
6738 hdspm->port_names_out_qs = texts_ports_aio_out_qs;
6739
6740 break;
6741
6742 case RayDAT:
6743 hdspm->ss_in_channels = hdspm->ss_out_channels =
6744 RAYDAT_SS_CHANNELS;
6745 hdspm->ds_in_channels = hdspm->ds_out_channels =
6746 RAYDAT_DS_CHANNELS;
6747 hdspm->qs_in_channels = hdspm->qs_out_channels =
6748 RAYDAT_QS_CHANNELS;
6749
6750 hdspm->max_channels_in = RAYDAT_SS_CHANNELS;
6751 hdspm->max_channels_out = RAYDAT_SS_CHANNELS;
6752
6753 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6754 channel_map_raydat_ss;
6755 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6756 channel_map_raydat_ds;
6757 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6758 channel_map_raydat_qs;
6759 hdspm->channel_map_in = hdspm->channel_map_out =
6760 channel_map_raydat_ss;
6761
6762 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6763 texts_ports_raydat_ss;
6764 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6765 texts_ports_raydat_ds;
6766 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6767 texts_ports_raydat_qs;
6768
6769
6770 break;
6771
6772 }
6773
6774 /* TCO detection */
6775 switch (hdspm->io_type) {
6776 case AIO:
6777 case RayDAT:
6778 if (hdspm_read(hdspm, HDSPM_statusRegister2) &
6779 HDSPM_s2_tco_detect) {
6780 hdspm->midiPorts++;
6781 hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6782 GFP_KERNEL);
6783 if (NULL != hdspm->tco) {
6784 hdspm_tco_write(hdspm);
6785 }
e3a471d6 6786 dev_info(card->dev, "AIO/RayDAT TCO module found\n");
0dca1793
AK		 6787 } else {
6788 hdspm->tco = NULL;
6789 }
6790 break;
6791
6792 case MADI:
0dc831b9 6793 case AES32:
0dca1793
AK		 6794 if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) {
6795 hdspm->midiPorts++;
6796 hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6797 GFP_KERNEL);
6798 if (NULL != hdspm->tco) {
6799 hdspm_tco_write(hdspm);
6800 }
e3a471d6 6801 dev_info(card->dev, "MADI/AES TCO module found\n");
0dca1793
AK		 6802 } else {
6803 hdspm->tco = NULL;
6804 }
6805 break;
6806
6807 default:
6808 hdspm->tco = NULL;
6809 }
6810
6811 /* texts */
6812 switch (hdspm->io_type) {
6813 case AES32:
6814 if (hdspm->tco) {
6815 hdspm->texts_autosync = texts_autosync_aes_tco;
e71b95ad
AK		 6816 hdspm->texts_autosync_items =
6817 ARRAY_SIZE(texts_autosync_aes_tco);
0dca1793
AK		 6818 } else {
6819 hdspm->texts_autosync = texts_autosync_aes;
e71b95ad
AK		 6820 hdspm->texts_autosync_items =
6821 ARRAY_SIZE(texts_autosync_aes);
0dca1793
AK		 6822 }
6823 break;
6824
6825 case MADI:
6826 if (hdspm->tco) {
6827 hdspm->texts_autosync = texts_autosync_madi_tco;
6828 hdspm->texts_autosync_items = 4;
6829 } else {
6830 hdspm->texts_autosync = texts_autosync_madi;
6831 hdspm->texts_autosync_items = 3;
6832 }
6833 break;
6834
6835 case MADIface:
6836
6837 break;
6838
6839 case RayDAT:
6840 if (hdspm->tco) {
6841 hdspm->texts_autosync = texts_autosync_raydat_tco;
6842 hdspm->texts_autosync_items = 9;
6843 } else {
6844 hdspm->texts_autosync = texts_autosync_raydat;
6845 hdspm->texts_autosync_items = 8;
6846 }
6847 break;
6848
6849 case AIO:
6850 if (hdspm->tco) {
6851 hdspm->texts_autosync = texts_autosync_aio_tco;
6852 hdspm->texts_autosync_items = 6;
6853 } else {
6854 hdspm->texts_autosync = texts_autosync_aio;
6855 hdspm->texts_autosync_items = 5;
6856 }
6857 break;
6858
6859 }
6860
6861 tasklet_init(&hdspm->midi_tasklet,
6862 hdspm_midi_tasklet, (unsigned long) hdspm);
763f356c 6863
f7de8ba3
AK		 6864
6865 if (hdspm->io_type != MADIface) {
6866 hdspm->serial = (hdspm_read(hdspm,
6867 HDSPM_midiStatusIn0)>>8) & 0xFFFFFF;
6868 /* id contains either a user-provided value or the default
6869 * NULL. If it's the default, we're safe to
6870 * fill card->id with the serial number.
6871 *
6872 * If the serial number is 0xFFFFFF, then we're dealing with
6873 * an old PCI revision that comes without a sane number. In
6874 * this case, we don't set card->id to avoid collisions
6875 * when running with multiple cards.
6876 */
6877 if (NULL == id[hdspm->dev] && hdspm->serial != 0xFFFFFF) {
7ad210ac
AB		 6878 snprintf(card->id, sizeof(card->id),
6879 "HDSPMx%06x", hdspm->serial);
f7de8ba3
AK		 6880 snd_card_set_id(card, card->id);
6881 }
6882 }
6883
e3a471d6 6884 dev_dbg(card->dev, "create alsa devices.\n");
ef5fa1a4
TI		 6885 err = snd_hdspm_create_alsa_devices(card, hdspm);
6886 if (err < 0)
763f356c
TI		 6887 return err;
6888
6889 snd_hdspm_initialize_midi_flush(hdspm);
6890
6891 return 0;
6892}
6893
0dca1793 6894
98274f07 6895static int snd_hdspm_free(struct hdspm * hdspm)
763f356c
TI		 6896{
6897
6898 if (hdspm->port) {
6899
6900 /* stop th audio, and cancel all interrupts */
6901 hdspm->control_register &=
ef5fa1a4 6902 ~(HDSPM_Start | HDSPM_AudioInterruptEnable |
0dca1793
AK		 6903 HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable |
6904 HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable);
763f356c
TI		 6905 hdspm_write(hdspm, HDSPM_controlRegister,
6906 hdspm->control_register);
6907 }
6908
6909 if (hdspm->irq >= 0)
6910 free_irq(hdspm->irq, (void *) hdspm);
6911
fc58422a 6912 kfree(hdspm->mixer);
ff6defa6 6913 iounmap(hdspm->iobase);
763f356c 6914
763f356c
TI		 6915 if (hdspm->port)
6916 pci_release_regions(hdspm->pci);
6917
6918 pci_disable_device(hdspm->pci);
6919 return 0;
6920}
6921
0dca1793 6922
98274f07 6923static void snd_hdspm_card_free(struct snd_card *card)
763f356c 6924{
ef5fa1a4 6925 struct hdspm *hdspm = card->private_data;
763f356c
TI		 6926
6927 if (hdspm)
6928 snd_hdspm_free(hdspm);
6929}
6930
0dca1793 6931
e23e7a14
BP		 6932static int snd_hdspm_probe(struct pci_dev *pci,
6933 const struct pci_device_id *pci_id)
763f356c
TI		 6934{
6935 static int dev;
98274f07
TI		 6936 struct hdspm *hdspm;
6937 struct snd_card *card;
763f356c
TI		 6938 int err;
6939
6940 if (dev >= SNDRV_CARDS)
6941 return -ENODEV;
6942 if (!enable[dev]) {
6943 dev++;
6944 return -ENOENT;
6945 }
6946
60c5772b
TI		 6947 err = snd_card_new(&pci->dev, index[dev], id[dev],
6948 THIS_MODULE, sizeof(struct hdspm), &card);
e58de7ba
TI		 6949 if (err < 0)
6950 return err;
763f356c 6951
ef5fa1a4 6952 hdspm = card->private_data;
763f356c
TI		 6953 card->private_free = snd_hdspm_card_free;
6954 hdspm->dev = dev;
6955 hdspm->pci = pci;
6956
0dca1793 6957 err = snd_hdspm_create(card, hdspm);
ef5fa1a4 6958 if (err < 0) {
763f356c
TI		 6959 snd_card_free(card);
6960 return err;
6961 }
6962
0dca1793 6963 if (hdspm->io_type != MADIface) {
7ad210ac
AB		 6964 snprintf(card->shortname, sizeof(card->shortname), "%s_%x",
6965 hdspm->card_name, hdspm->serial);
6966 snprintf(card->longname, sizeof(card->longname),
6967 "%s S/N 0x%x at 0x%lx, irq %d",
6968 hdspm->card_name, hdspm->serial,
6969 hdspm->port, hdspm->irq);
0dca1793 6970 } else {
7ad210ac
AB		 6971 snprintf(card->shortname, sizeof(card->shortname), "%s",
6972 hdspm->card_name);
6973 snprintf(card->longname, sizeof(card->longname),
6974 "%s at 0x%lx, irq %d",
6975 hdspm->card_name, hdspm->port, hdspm->irq);
0dca1793 6976 }
763f356c 6977
ef5fa1a4
TI		 6978 err = snd_card_register(card);
6979 if (err < 0) {
763f356c
TI		 6980 snd_card_free(card);
6981 return err;
6982 }
6983
6984 pci_set_drvdata(pci, card);
6985
6986 dev++;
6987 return 0;
6988}
6989
e23e7a14 6990static void snd_hdspm_remove(struct pci_dev *pci)
763f356c
TI		 6991{
6992 snd_card_free(pci_get_drvdata(pci));
763f356c
TI		 6993}
6994
e9f66d9b 6995static struct pci_driver hdspm_driver = {
3733e424 6996 .name = KBUILD_MODNAME,
763f356c
TI		 6997 .id_table = snd_hdspm_ids,
6998 .probe = snd_hdspm_probe,
e23e7a14 6999 .remove = snd_hdspm_remove,
763f356c
TI		 7000};
7001
e9f66d9b 7002module_pci_driver(hdspm_driver);
Linux 6.x block layer and io_uring tree(s)