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1a59d1b8 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
1da177e4 LT |
2 | /* |
3 | * ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio | |
4 | * interfaces | |
5 | * | |
6 | * Copyright (c) 2000, 2001 Anders Torger <torger@ludd.luth.se> | |
7 | * | |
8 | * Thanks to Henk Hesselink <henk@anda.nl> for the analog volume control | |
9 | * code. | |
1da177e4 LT |
10 | */ |
11 | ||
1da177e4 LT |
12 | #include <linux/delay.h> |
13 | #include <linux/init.h> | |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/pci.h> | |
65a77217 | 16 | #include <linux/module.h> |
a8cc2099 | 17 | #include <linux/vmalloc.h> |
6cbbfe1c | 18 | #include <linux/io.h> |
1da177e4 LT |
19 | |
20 | #include <sound/core.h> | |
21 | #include <sound/info.h> | |
22 | #include <sound/control.h> | |
23 | #include <sound/pcm.h> | |
24 | #include <sound/pcm_params.h> | |
25 | #include <sound/asoundef.h> | |
26 | #include <sound/initval.h> | |
27 | ||
1da177e4 LT |
28 | /* note, two last pcis should be equal, it is not a bug */ |
29 | ||
30 | MODULE_AUTHOR("Anders Torger <torger@ludd.luth.se>"); | |
31 | MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, " | |
32 | "Digi96/8 PAD"); | |
33 | MODULE_LICENSE("GPL"); | |
1da177e4 LT |
34 | |
35 | static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ | |
36 | static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ | |
a67ff6a5 | 37 | static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ |
1da177e4 LT |
38 | |
39 | module_param_array(index, int, NULL, 0444); | |
40 | MODULE_PARM_DESC(index, "Index value for RME Digi96 soundcard."); | |
41 | module_param_array(id, charp, NULL, 0444); | |
42 | MODULE_PARM_DESC(id, "ID string for RME Digi96 soundcard."); | |
43 | module_param_array(enable, bool, NULL, 0444); | |
44 | MODULE_PARM_DESC(enable, "Enable RME Digi96 soundcard."); | |
45 | ||
46 | /* | |
47 | * Defines for RME Digi96 series, from internal RME reference documents | |
48 | * dated 12.01.00 | |
49 | */ | |
50 | ||
51 | #define RME96_SPDIF_NCHANNELS 2 | |
52 | ||
53 | /* Playback and capture buffer size */ | |
54 | #define RME96_BUFFER_SIZE 0x10000 | |
55 | ||
56 | /* IO area size */ | |
57 | #define RME96_IO_SIZE 0x60000 | |
58 | ||
59 | /* IO area offsets */ | |
60 | #define RME96_IO_PLAY_BUFFER 0x0 | |
61 | #define RME96_IO_REC_BUFFER 0x10000 | |
62 | #define RME96_IO_CONTROL_REGISTER 0x20000 | |
63 | #define RME96_IO_ADDITIONAL_REG 0x20004 | |
64 | #define RME96_IO_CONFIRM_PLAY_IRQ 0x20008 | |
65 | #define RME96_IO_CONFIRM_REC_IRQ 0x2000C | |
66 | #define RME96_IO_SET_PLAY_POS 0x40000 | |
67 | #define RME96_IO_RESET_PLAY_POS 0x4FFFC | |
68 | #define RME96_IO_SET_REC_POS 0x50000 | |
69 | #define RME96_IO_RESET_REC_POS 0x5FFFC | |
70 | #define RME96_IO_GET_PLAY_POS 0x20000 | |
71 | #define RME96_IO_GET_REC_POS 0x30000 | |
72 | ||
73 | /* Write control register bits */ | |
74 | #define RME96_WCR_START (1 << 0) | |
75 | #define RME96_WCR_START_2 (1 << 1) | |
76 | #define RME96_WCR_GAIN_0 (1 << 2) | |
77 | #define RME96_WCR_GAIN_1 (1 << 3) | |
78 | #define RME96_WCR_MODE24 (1 << 4) | |
79 | #define RME96_WCR_MODE24_2 (1 << 5) | |
80 | #define RME96_WCR_BM (1 << 6) | |
81 | #define RME96_WCR_BM_2 (1 << 7) | |
82 | #define RME96_WCR_ADAT (1 << 8) | |
83 | #define RME96_WCR_FREQ_0 (1 << 9) | |
84 | #define RME96_WCR_FREQ_1 (1 << 10) | |
85 | #define RME96_WCR_DS (1 << 11) | |
86 | #define RME96_WCR_PRO (1 << 12) | |
87 | #define RME96_WCR_EMP (1 << 13) | |
88 | #define RME96_WCR_SEL (1 << 14) | |
89 | #define RME96_WCR_MASTER (1 << 15) | |
90 | #define RME96_WCR_PD (1 << 16) | |
91 | #define RME96_WCR_INP_0 (1 << 17) | |
92 | #define RME96_WCR_INP_1 (1 << 18) | |
93 | #define RME96_WCR_THRU_0 (1 << 19) | |
94 | #define RME96_WCR_THRU_1 (1 << 20) | |
95 | #define RME96_WCR_THRU_2 (1 << 21) | |
96 | #define RME96_WCR_THRU_3 (1 << 22) | |
97 | #define RME96_WCR_THRU_4 (1 << 23) | |
98 | #define RME96_WCR_THRU_5 (1 << 24) | |
99 | #define RME96_WCR_THRU_6 (1 << 25) | |
100 | #define RME96_WCR_THRU_7 (1 << 26) | |
101 | #define RME96_WCR_DOLBY (1 << 27) | |
102 | #define RME96_WCR_MONITOR_0 (1 << 28) | |
103 | #define RME96_WCR_MONITOR_1 (1 << 29) | |
104 | #define RME96_WCR_ISEL (1 << 30) | |
105 | #define RME96_WCR_IDIS (1 << 31) | |
106 | ||
107 | #define RME96_WCR_BITPOS_GAIN_0 2 | |
108 | #define RME96_WCR_BITPOS_GAIN_1 3 | |
109 | #define RME96_WCR_BITPOS_FREQ_0 9 | |
110 | #define RME96_WCR_BITPOS_FREQ_1 10 | |
111 | #define RME96_WCR_BITPOS_INP_0 17 | |
112 | #define RME96_WCR_BITPOS_INP_1 18 | |
113 | #define RME96_WCR_BITPOS_MONITOR_0 28 | |
114 | #define RME96_WCR_BITPOS_MONITOR_1 29 | |
115 | ||
116 | /* Read control register bits */ | |
117 | #define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF | |
118 | #define RME96_RCR_IRQ_2 (1 << 16) | |
119 | #define RME96_RCR_T_OUT (1 << 17) | |
120 | #define RME96_RCR_DEV_ID_0 (1 << 21) | |
121 | #define RME96_RCR_DEV_ID_1 (1 << 22) | |
122 | #define RME96_RCR_LOCK (1 << 23) | |
123 | #define RME96_RCR_VERF (1 << 26) | |
124 | #define RME96_RCR_F0 (1 << 27) | |
125 | #define RME96_RCR_F1 (1 << 28) | |
126 | #define RME96_RCR_F2 (1 << 29) | |
127 | #define RME96_RCR_AUTOSYNC (1 << 30) | |
128 | #define RME96_RCR_IRQ (1 << 31) | |
129 | ||
130 | #define RME96_RCR_BITPOS_F0 27 | |
131 | #define RME96_RCR_BITPOS_F1 28 | |
132 | #define RME96_RCR_BITPOS_F2 29 | |
133 | ||
25985edc | 134 | /* Additional register bits */ |
1da177e4 LT |
135 | #define RME96_AR_WSEL (1 << 0) |
136 | #define RME96_AR_ANALOG (1 << 1) | |
137 | #define RME96_AR_FREQPAD_0 (1 << 2) | |
138 | #define RME96_AR_FREQPAD_1 (1 << 3) | |
139 | #define RME96_AR_FREQPAD_2 (1 << 4) | |
140 | #define RME96_AR_PD2 (1 << 5) | |
141 | #define RME96_AR_DAC_EN (1 << 6) | |
142 | #define RME96_AR_CLATCH (1 << 7) | |
143 | #define RME96_AR_CCLK (1 << 8) | |
144 | #define RME96_AR_CDATA (1 << 9) | |
145 | ||
146 | #define RME96_AR_BITPOS_F0 2 | |
147 | #define RME96_AR_BITPOS_F1 3 | |
148 | #define RME96_AR_BITPOS_F2 4 | |
149 | ||
150 | /* Monitor tracks */ | |
151 | #define RME96_MONITOR_TRACKS_1_2 0 | |
152 | #define RME96_MONITOR_TRACKS_3_4 1 | |
153 | #define RME96_MONITOR_TRACKS_5_6 2 | |
154 | #define RME96_MONITOR_TRACKS_7_8 3 | |
155 | ||
156 | /* Attenuation */ | |
157 | #define RME96_ATTENUATION_0 0 | |
158 | #define RME96_ATTENUATION_6 1 | |
159 | #define RME96_ATTENUATION_12 2 | |
160 | #define RME96_ATTENUATION_18 3 | |
161 | ||
162 | /* Input types */ | |
163 | #define RME96_INPUT_OPTICAL 0 | |
164 | #define RME96_INPUT_COAXIAL 1 | |
165 | #define RME96_INPUT_INTERNAL 2 | |
166 | #define RME96_INPUT_XLR 3 | |
167 | #define RME96_INPUT_ANALOG 4 | |
168 | ||
169 | /* Clock modes */ | |
170 | #define RME96_CLOCKMODE_SLAVE 0 | |
171 | #define RME96_CLOCKMODE_MASTER 1 | |
172 | #define RME96_CLOCKMODE_WORDCLOCK 2 | |
173 | ||
174 | /* Block sizes in bytes */ | |
175 | #define RME96_SMALL_BLOCK_SIZE 2048 | |
176 | #define RME96_LARGE_BLOCK_SIZE 8192 | |
177 | ||
178 | /* Volume control */ | |
179 | #define RME96_AD1852_VOL_BITS 14 | |
180 | #define RME96_AD1855_VOL_BITS 10 | |
181 | ||
b892ca1c KP |
182 | /* Defines for snd_rme96_trigger */ |
183 | #define RME96_TB_START_PLAYBACK 1 | |
184 | #define RME96_TB_START_CAPTURE 2 | |
185 | #define RME96_TB_STOP_PLAYBACK 4 | |
186 | #define RME96_TB_STOP_CAPTURE 8 | |
187 | #define RME96_TB_RESET_PLAYPOS 16 | |
188 | #define RME96_TB_RESET_CAPTUREPOS 32 | |
189 | #define RME96_TB_CLEAR_PLAYBACK_IRQ 64 | |
190 | #define RME96_TB_CLEAR_CAPTURE_IRQ 128 | |
191 | #define RME96_RESUME_PLAYBACK (RME96_TB_START_PLAYBACK) | |
192 | #define RME96_RESUME_CAPTURE (RME96_TB_START_CAPTURE) | |
193 | #define RME96_RESUME_BOTH (RME96_RESUME_PLAYBACK \ | |
194 | | RME96_RESUME_CAPTURE) | |
195 | #define RME96_START_PLAYBACK (RME96_TB_START_PLAYBACK \ | |
196 | | RME96_TB_RESET_PLAYPOS) | |
197 | #define RME96_START_CAPTURE (RME96_TB_START_CAPTURE \ | |
198 | | RME96_TB_RESET_CAPTUREPOS) | |
199 | #define RME96_START_BOTH (RME96_START_PLAYBACK \ | |
200 | | RME96_START_CAPTURE) | |
201 | #define RME96_STOP_PLAYBACK (RME96_TB_STOP_PLAYBACK \ | |
202 | | RME96_TB_CLEAR_PLAYBACK_IRQ) | |
203 | #define RME96_STOP_CAPTURE (RME96_TB_STOP_CAPTURE \ | |
204 | | RME96_TB_CLEAR_CAPTURE_IRQ) | |
205 | #define RME96_STOP_BOTH (RME96_STOP_PLAYBACK \ | |
206 | | RME96_STOP_CAPTURE) | |
1da177e4 | 207 | |
a3aefd88 | 208 | struct rme96 { |
1da177e4 LT |
209 | spinlock_t lock; |
210 | int irq; | |
211 | unsigned long port; | |
212 | void __iomem *iobase; | |
213 | ||
214 | u32 wcreg; /* cached write control register value */ | |
215 | u32 wcreg_spdif; /* S/PDIF setup */ | |
216 | u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */ | |
217 | u32 rcreg; /* cached read control register value */ | |
218 | u32 areg; /* cached additional register value */ | |
219 | u16 vol[2]; /* cached volume of analog output */ | |
220 | ||
221 | u8 rev; /* card revision number */ | |
222 | ||
a932be91 | 223 | #ifdef CONFIG_PM_SLEEP |
528ba522 KP |
224 | u32 playback_pointer; |
225 | u32 capture_pointer; | |
226 | void *playback_suspend_buffer; | |
227 | void *capture_suspend_buffer; | |
228 | #endif | |
229 | ||
a3aefd88 TI |
230 | struct snd_pcm_substream *playback_substream; |
231 | struct snd_pcm_substream *capture_substream; | |
1da177e4 LT |
232 | |
233 | int playback_frlog; /* log2 of framesize */ | |
234 | int capture_frlog; | |
235 | ||
236 | size_t playback_periodsize; /* in bytes, zero if not used */ | |
237 | size_t capture_periodsize; /* in bytes, zero if not used */ | |
238 | ||
a3aefd88 TI |
239 | struct snd_card *card; |
240 | struct snd_pcm *spdif_pcm; | |
241 | struct snd_pcm *adat_pcm; | |
1da177e4 | 242 | struct pci_dev *pci; |
a3aefd88 TI |
243 | struct snd_kcontrol *spdif_ctl; |
244 | }; | |
1da177e4 | 245 | |
9baa3c34 | 246 | static const struct pci_device_id snd_rme96_ids[] = { |
28d27aae JP |
247 | { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96), 0, }, |
248 | { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8), 0, }, | |
249 | { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PRO), 0, }, | |
250 | { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST), 0, }, | |
1da177e4 LT |
251 | { 0, } |
252 | }; | |
253 | ||
254 | MODULE_DEVICE_TABLE(pci, snd_rme96_ids); | |
255 | ||
256 | #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START) | |
257 | #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2) | |
8b7fc421 RD |
258 | #define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST) |
259 | #define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO || \ | |
260 | (rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST) | |
1da177e4 | 261 | #define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4) |
8b7fc421 RD |
262 | #define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \ |
263 | ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO && (rme96)->rev == 2)) | |
1da177e4 LT |
264 | #define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1) |
265 | ||
266 | static int | |
a3aefd88 | 267 | snd_rme96_playback_prepare(struct snd_pcm_substream *substream); |
1da177e4 LT |
268 | |
269 | static int | |
a3aefd88 | 270 | snd_rme96_capture_prepare(struct snd_pcm_substream *substream); |
1da177e4 LT |
271 | |
272 | static int | |
a3aefd88 | 273 | snd_rme96_playback_trigger(struct snd_pcm_substream *substream, |
1da177e4 LT |
274 | int cmd); |
275 | ||
276 | static int | |
a3aefd88 | 277 | snd_rme96_capture_trigger(struct snd_pcm_substream *substream, |
1da177e4 LT |
278 | int cmd); |
279 | ||
280 | static snd_pcm_uframes_t | |
a3aefd88 | 281 | snd_rme96_playback_pointer(struct snd_pcm_substream *substream); |
1da177e4 LT |
282 | |
283 | static snd_pcm_uframes_t | |
a3aefd88 | 284 | snd_rme96_capture_pointer(struct snd_pcm_substream *substream); |
1da177e4 | 285 | |
e23e7a14 | 286 | static void snd_rme96_proc_init(struct rme96 *rme96); |
1da177e4 LT |
287 | |
288 | static int | |
a3aefd88 TI |
289 | snd_rme96_create_switches(struct snd_card *card, |
290 | struct rme96 *rme96); | |
1da177e4 LT |
291 | |
292 | static int | |
a3aefd88 | 293 | snd_rme96_getinputtype(struct rme96 *rme96); |
1da177e4 LT |
294 | |
295 | static inline unsigned int | |
a3aefd88 | 296 | snd_rme96_playback_ptr(struct rme96 *rme96) |
1da177e4 LT |
297 | { |
298 | return (readl(rme96->iobase + RME96_IO_GET_PLAY_POS) | |
299 | & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->playback_frlog; | |
300 | } | |
301 | ||
302 | static inline unsigned int | |
a3aefd88 | 303 | snd_rme96_capture_ptr(struct rme96 *rme96) |
1da177e4 LT |
304 | { |
305 | return (readl(rme96->iobase + RME96_IO_GET_REC_POS) | |
306 | & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->capture_frlog; | |
307 | } | |
308 | ||
1da177e4 | 309 | static int |
a3aefd88 | 310 | snd_rme96_playback_silence(struct snd_pcm_substream *substream, |
53945f5b | 311 | int channel, unsigned long pos, unsigned long count) |
1da177e4 | 312 | { |
a3aefd88 | 313 | struct rme96 *rme96 = snd_pcm_substream_chip(substream); |
53945f5b | 314 | |
1da177e4 LT |
315 | memset_io(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, |
316 | 0, count); | |
317 | return 0; | |
318 | } | |
319 | ||
320 | static int | |
a3aefd88 | 321 | snd_rme96_playback_copy(struct snd_pcm_substream *substream, |
53945f5b TI |
322 | int channel, unsigned long pos, |
323 | void __user *src, unsigned long count) | |
1da177e4 | 324 | { |
a3aefd88 | 325 | struct rme96 *rme96 = snd_pcm_substream_chip(substream); |
53945f5b TI |
326 | |
327 | return copy_from_user_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, | |
328 | src, count); | |
329 | } | |
330 | ||
331 | static int | |
332 | snd_rme96_playback_copy_kernel(struct snd_pcm_substream *substream, | |
333 | int channel, unsigned long pos, | |
334 | void *src, unsigned long count) | |
335 | { | |
336 | struct rme96 *rme96 = snd_pcm_substream_chip(substream); | |
337 | ||
338 | memcpy_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, src, count); | |
339 | return 0; | |
1da177e4 LT |
340 | } |
341 | ||
342 | static int | |
a3aefd88 | 343 | snd_rme96_capture_copy(struct snd_pcm_substream *substream, |
53945f5b TI |
344 | int channel, unsigned long pos, |
345 | void __user *dst, unsigned long count) | |
1da177e4 | 346 | { |
a3aefd88 | 347 | struct rme96 *rme96 = snd_pcm_substream_chip(substream); |
53945f5b TI |
348 | |
349 | return copy_to_user_fromio(dst, | |
350 | rme96->iobase + RME96_IO_REC_BUFFER + pos, | |
2026d24e | 351 | count); |
1da177e4 LT |
352 | } |
353 | ||
53945f5b TI |
354 | static int |
355 | snd_rme96_capture_copy_kernel(struct snd_pcm_substream *substream, | |
356 | int channel, unsigned long pos, | |
357 | void *dst, unsigned long count) | |
358 | { | |
359 | struct rme96 *rme96 = snd_pcm_substream_chip(substream); | |
360 | ||
361 | memcpy_fromio(dst, rme96->iobase + RME96_IO_REC_BUFFER + pos, count); | |
362 | return 0; | |
363 | } | |
364 | ||
1da177e4 | 365 | /* |
7f927fcc | 366 | * Digital output capabilities (S/PDIF) |
1da177e4 | 367 | */ |
dee49895 | 368 | static const struct snd_pcm_hardware snd_rme96_playback_spdif_info = |
1da177e4 LT |
369 | { |
370 | .info = (SNDRV_PCM_INFO_MMAP_IOMEM | | |
371 | SNDRV_PCM_INFO_MMAP_VALID | | |
b892ca1c | 372 | SNDRV_PCM_INFO_SYNC_START | |
528ba522 | 373 | SNDRV_PCM_INFO_RESUME | |
1da177e4 LT |
374 | SNDRV_PCM_INFO_INTERLEAVED | |
375 | SNDRV_PCM_INFO_PAUSE), | |
376 | .formats = (SNDRV_PCM_FMTBIT_S16_LE | | |
377 | SNDRV_PCM_FMTBIT_S32_LE), | |
378 | .rates = (SNDRV_PCM_RATE_32000 | | |
379 | SNDRV_PCM_RATE_44100 | | |
380 | SNDRV_PCM_RATE_48000 | | |
381 | SNDRV_PCM_RATE_64000 | | |
382 | SNDRV_PCM_RATE_88200 | | |
383 | SNDRV_PCM_RATE_96000), | |
384 | .rate_min = 32000, | |
385 | .rate_max = 96000, | |
386 | .channels_min = 2, | |
387 | .channels_max = 2, | |
388 | .buffer_bytes_max = RME96_BUFFER_SIZE, | |
389 | .period_bytes_min = RME96_SMALL_BLOCK_SIZE, | |
390 | .period_bytes_max = RME96_LARGE_BLOCK_SIZE, | |
391 | .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, | |
392 | .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, | |
393 | .fifo_size = 0, | |
394 | }; | |
395 | ||
396 | /* | |
7f927fcc | 397 | * Digital input capabilities (S/PDIF) |
1da177e4 | 398 | */ |
dee49895 | 399 | static const struct snd_pcm_hardware snd_rme96_capture_spdif_info = |
1da177e4 LT |
400 | { |
401 | .info = (SNDRV_PCM_INFO_MMAP_IOMEM | | |
402 | SNDRV_PCM_INFO_MMAP_VALID | | |
b892ca1c | 403 | SNDRV_PCM_INFO_SYNC_START | |
528ba522 | 404 | SNDRV_PCM_INFO_RESUME | |
1da177e4 LT |
405 | SNDRV_PCM_INFO_INTERLEAVED | |
406 | SNDRV_PCM_INFO_PAUSE), | |
407 | .formats = (SNDRV_PCM_FMTBIT_S16_LE | | |
408 | SNDRV_PCM_FMTBIT_S32_LE), | |
409 | .rates = (SNDRV_PCM_RATE_32000 | | |
410 | SNDRV_PCM_RATE_44100 | | |
411 | SNDRV_PCM_RATE_48000 | | |
412 | SNDRV_PCM_RATE_64000 | | |
413 | SNDRV_PCM_RATE_88200 | | |
414 | SNDRV_PCM_RATE_96000), | |
415 | .rate_min = 32000, | |
416 | .rate_max = 96000, | |
417 | .channels_min = 2, | |
418 | .channels_max = 2, | |
419 | .buffer_bytes_max = RME96_BUFFER_SIZE, | |
420 | .period_bytes_min = RME96_SMALL_BLOCK_SIZE, | |
421 | .period_bytes_max = RME96_LARGE_BLOCK_SIZE, | |
422 | .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, | |
423 | .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, | |
424 | .fifo_size = 0, | |
425 | }; | |
426 | ||
427 | /* | |
7f927fcc | 428 | * Digital output capabilities (ADAT) |
1da177e4 | 429 | */ |
dee49895 | 430 | static const struct snd_pcm_hardware snd_rme96_playback_adat_info = |
1da177e4 LT |
431 | { |
432 | .info = (SNDRV_PCM_INFO_MMAP_IOMEM | | |
433 | SNDRV_PCM_INFO_MMAP_VALID | | |
b892ca1c | 434 | SNDRV_PCM_INFO_SYNC_START | |
528ba522 | 435 | SNDRV_PCM_INFO_RESUME | |
1da177e4 LT |
436 | SNDRV_PCM_INFO_INTERLEAVED | |
437 | SNDRV_PCM_INFO_PAUSE), | |
438 | .formats = (SNDRV_PCM_FMTBIT_S16_LE | | |
439 | SNDRV_PCM_FMTBIT_S32_LE), | |
440 | .rates = (SNDRV_PCM_RATE_44100 | | |
441 | SNDRV_PCM_RATE_48000), | |
442 | .rate_min = 44100, | |
443 | .rate_max = 48000, | |
444 | .channels_min = 8, | |
445 | .channels_max = 8, | |
446 | .buffer_bytes_max = RME96_BUFFER_SIZE, | |
447 | .period_bytes_min = RME96_SMALL_BLOCK_SIZE, | |
448 | .period_bytes_max = RME96_LARGE_BLOCK_SIZE, | |
449 | .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, | |
450 | .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, | |
451 | .fifo_size = 0, | |
452 | }; | |
453 | ||
454 | /* | |
7f927fcc | 455 | * Digital input capabilities (ADAT) |
1da177e4 | 456 | */ |
dee49895 | 457 | static const struct snd_pcm_hardware snd_rme96_capture_adat_info = |
1da177e4 LT |
458 | { |
459 | .info = (SNDRV_PCM_INFO_MMAP_IOMEM | | |
460 | SNDRV_PCM_INFO_MMAP_VALID | | |
b892ca1c | 461 | SNDRV_PCM_INFO_SYNC_START | |
528ba522 | 462 | SNDRV_PCM_INFO_RESUME | |
1da177e4 LT |
463 | SNDRV_PCM_INFO_INTERLEAVED | |
464 | SNDRV_PCM_INFO_PAUSE), | |
465 | .formats = (SNDRV_PCM_FMTBIT_S16_LE | | |
466 | SNDRV_PCM_FMTBIT_S32_LE), | |
467 | .rates = (SNDRV_PCM_RATE_44100 | | |
468 | SNDRV_PCM_RATE_48000), | |
469 | .rate_min = 44100, | |
470 | .rate_max = 48000, | |
471 | .channels_min = 8, | |
472 | .channels_max = 8, | |
473 | .buffer_bytes_max = RME96_BUFFER_SIZE, | |
474 | .period_bytes_min = RME96_SMALL_BLOCK_SIZE, | |
475 | .period_bytes_max = RME96_LARGE_BLOCK_SIZE, | |
476 | .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, | |
477 | .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, | |
478 | .fifo_size = 0, | |
479 | }; | |
480 | ||
481 | /* | |
482 | * The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface | |
483 | * of the AD1852 or AD1852 D/A converter on the board. CDATA must be set up | |
484 | * on the falling edge of CCLK and be stable on the rising edge. The rising | |
485 | * edge of CLATCH after the last data bit clocks in the whole data word. | |
486 | * A fast processor could probably drive the SPI interface faster than the | |
487 | * DAC can handle (3MHz for the 1855, unknown for the 1852). The udelay(1) | |
488 | * limits the data rate to 500KHz and only causes a delay of 33 microsecs. | |
489 | * | |
490 | * NOTE: increased delay from 1 to 10, since there where problems setting | |
491 | * the volume. | |
492 | */ | |
493 | static void | |
a3aefd88 | 494 | snd_rme96_write_SPI(struct rme96 *rme96, u16 val) |
1da177e4 LT |
495 | { |
496 | int i; | |
497 | ||
498 | for (i = 0; i < 16; i++) { | |
499 | if (val & 0x8000) { | |
500 | rme96->areg |= RME96_AR_CDATA; | |
501 | } else { | |
502 | rme96->areg &= ~RME96_AR_CDATA; | |
503 | } | |
504 | rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CLATCH); | |
505 | writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); | |
506 | udelay(10); | |
507 | rme96->areg |= RME96_AR_CCLK; | |
508 | writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); | |
509 | udelay(10); | |
510 | val <<= 1; | |
511 | } | |
512 | rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CDATA); | |
513 | rme96->areg |= RME96_AR_CLATCH; | |
514 | writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); | |
515 | udelay(10); | |
516 | rme96->areg &= ~RME96_AR_CLATCH; | |
517 | writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); | |
518 | } | |
519 | ||
520 | static void | |
a3aefd88 | 521 | snd_rme96_apply_dac_volume(struct rme96 *rme96) |
1da177e4 LT |
522 | { |
523 | if (RME96_DAC_IS_1852(rme96)) { | |
524 | snd_rme96_write_SPI(rme96, (rme96->vol[0] << 2) | 0x0); | |
525 | snd_rme96_write_SPI(rme96, (rme96->vol[1] << 2) | 0x2); | |
526 | } else if (RME96_DAC_IS_1855(rme96)) { | |
527 | snd_rme96_write_SPI(rme96, (rme96->vol[0] & 0x3FF) | 0x000); | |
528 | snd_rme96_write_SPI(rme96, (rme96->vol[1] & 0x3FF) | 0x400); | |
529 | } | |
530 | } | |
531 | ||
532 | static void | |
a3aefd88 | 533 | snd_rme96_reset_dac(struct rme96 *rme96) |
1da177e4 LT |
534 | { |
535 | writel(rme96->wcreg | RME96_WCR_PD, | |
536 | rme96->iobase + RME96_IO_CONTROL_REGISTER); | |
537 | writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); | |
538 | } | |
539 | ||
540 | static int | |
a3aefd88 | 541 | snd_rme96_getmontracks(struct rme96 *rme96) |
1da177e4 LT |
542 | { |
543 | return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) + | |
544 | (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1); | |
545 | } | |
546 | ||
547 | static int | |
a3aefd88 | 548 | snd_rme96_setmontracks(struct rme96 *rme96, |
1da177e4 LT |
549 | int montracks) |
550 | { | |
551 | if (montracks & 1) { | |
552 | rme96->wcreg |= RME96_WCR_MONITOR_0; | |
553 | } else { | |
554 | rme96->wcreg &= ~RME96_WCR_MONITOR_0; | |
555 | } | |
556 | if (montracks & 2) { | |
557 | rme96->wcreg |= RME96_WCR_MONITOR_1; | |
558 | } else { | |
559 | rme96->wcreg &= ~RME96_WCR_MONITOR_1; | |
560 | } | |
561 | writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); | |
562 | return 0; | |
563 | } | |
564 | ||
565 | static int | |
a3aefd88 | 566 | snd_rme96_getattenuation(struct rme96 *rme96) |
1da177e4 LT |
567 | { |
568 | return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) + | |
569 | (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1); | |
570 | } | |
571 | ||
572 | static int | |
a3aefd88 | 573 | snd_rme96_setattenuation(struct rme96 *rme96, |
1da177e4 LT |
574 | int attenuation) |
575 | { | |
576 | switch (attenuation) { | |
577 | case 0: | |
578 | rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) & | |
579 | ~RME96_WCR_GAIN_1; | |
580 | break; | |
581 | case 1: | |
582 | rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) & | |
583 | ~RME96_WCR_GAIN_1; | |
584 | break; | |
585 | case 2: | |
586 | rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) | | |
587 | RME96_WCR_GAIN_1; | |
588 | break; | |
589 | case 3: | |
590 | rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) | | |
591 | RME96_WCR_GAIN_1; | |
592 | break; | |
593 | default: | |
594 | return -EINVAL; | |
595 | } | |
596 | writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); | |
597 | return 0; | |
598 | } | |
599 | ||
600 | static int | |
a3aefd88 | 601 | snd_rme96_capture_getrate(struct rme96 *rme96, |
1da177e4 LT |
602 | int *is_adat) |
603 | { | |
604 | int n, rate; | |
605 | ||
606 | *is_adat = 0; | |
607 | if (rme96->areg & RME96_AR_ANALOG) { | |
608 | /* Analog input, overrides S/PDIF setting */ | |
609 | n = ((rme96->areg >> RME96_AR_BITPOS_F0) & 1) + | |
610 | (((rme96->areg >> RME96_AR_BITPOS_F1) & 1) << 1); | |
611 | switch (n) { | |
612 | case 1: | |
613 | rate = 32000; | |
614 | break; | |
615 | case 2: | |
616 | rate = 44100; | |
617 | break; | |
618 | case 3: | |
619 | rate = 48000; | |
620 | break; | |
621 | default: | |
622 | return -1; | |
623 | } | |
624 | return (rme96->areg & RME96_AR_BITPOS_F2) ? rate << 1 : rate; | |
625 | } | |
626 | ||
627 | rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); | |
628 | if (rme96->rcreg & RME96_RCR_LOCK) { | |
629 | /* ADAT rate */ | |
630 | *is_adat = 1; | |
631 | if (rme96->rcreg & RME96_RCR_T_OUT) { | |
632 | return 48000; | |
633 | } | |
634 | return 44100; | |
635 | } | |
636 | ||
637 | if (rme96->rcreg & RME96_RCR_VERF) { | |
638 | return -1; | |
639 | } | |
640 | ||
641 | /* S/PDIF rate */ | |
642 | n = ((rme96->rcreg >> RME96_RCR_BITPOS_F0) & 1) + | |
643 | (((rme96->rcreg >> RME96_RCR_BITPOS_F1) & 1) << 1) + | |
644 | (((rme96->rcreg >> RME96_RCR_BITPOS_F2) & 1) << 2); | |
645 | ||
646 | switch (n) { | |
647 | case 0: | |
648 | if (rme96->rcreg & RME96_RCR_T_OUT) { | |
649 | return 64000; | |
650 | } | |
651 | return -1; | |
652 | case 3: return 96000; | |
653 | case 4: return 88200; | |
654 | case 5: return 48000; | |
655 | case 6: return 44100; | |
656 | case 7: return 32000; | |
657 | default: | |
658 | break; | |
659 | } | |
660 | return -1; | |
661 | } | |
662 | ||
663 | static int | |
a3aefd88 | 664 | snd_rme96_playback_getrate(struct rme96 *rme96) |
1da177e4 LT |
665 | { |
666 | int rate, dummy; | |
667 | ||
668 | if (!(rme96->wcreg & RME96_WCR_MASTER) && | |
da8eedb1 TI |
669 | snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG) { |
670 | rate = snd_rme96_capture_getrate(rme96, &dummy); | |
671 | if (rate > 0) { | |
672 | /* slave clock */ | |
673 | return rate; | |
674 | } | |
1da177e4 | 675 | } |
da8eedb1 | 676 | |
1da177e4 LT |
677 | rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) + |
678 | (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1); | |
679 | switch (rate) { | |
680 | case 1: | |
681 | rate = 32000; | |
682 | break; | |
683 | case 2: | |
684 | rate = 44100; | |
685 | break; | |
686 | case 3: | |
687 | rate = 48000; | |
688 | break; | |
689 | default: | |
690 | return -1; | |
691 | } | |
692 | return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate; | |
693 | } | |
694 | ||
695 | static int | |
a3aefd88 | 696 | snd_rme96_playback_setrate(struct rme96 *rme96, |
1da177e4 LT |
697 | int rate) |
698 | { | |
699 | int ds; | |
700 | ||
701 | ds = rme96->wcreg & RME96_WCR_DS; | |
702 | switch (rate) { | |
703 | case 32000: | |
704 | rme96->wcreg &= ~RME96_WCR_DS; | |
705 | rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) & | |
706 | ~RME96_WCR_FREQ_1; | |
707 | break; | |
708 | case 44100: | |
709 | rme96->wcreg &= ~RME96_WCR_DS; | |
710 | rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) & | |
711 | ~RME96_WCR_FREQ_0; | |
712 | break; | |
713 | case 48000: | |
714 | rme96->wcreg &= ~RME96_WCR_DS; | |
715 | rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) | | |
716 | RME96_WCR_FREQ_1; | |
717 | break; | |
718 | case 64000: | |
719 | rme96->wcreg |= RME96_WCR_DS; | |
720 | rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) & | |
721 | ~RME96_WCR_FREQ_1; | |
722 | break; | |
723 | case 88200: | |
724 | rme96->wcreg |= RME96_WCR_DS; | |
725 | rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) & | |
726 | ~RME96_WCR_FREQ_0; | |
727 | break; | |
728 | case 96000: | |
729 | rme96->wcreg |= RME96_WCR_DS; | |
730 | rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) | | |
731 | RME96_WCR_FREQ_1; | |
732 | break; | |
733 | default: | |
734 | return -EINVAL; | |
735 | } | |
736 | if ((!ds && rme96->wcreg & RME96_WCR_DS) || | |
737 | (ds && !(rme96->wcreg & RME96_WCR_DS))) | |
738 | { | |
739 | /* change to/from double-speed: reset the DAC (if available) */ | |
740 | snd_rme96_reset_dac(rme96); | |
a74a8216 | 741 | return 1; /* need to restore volume */ |
1da177e4 LT |
742 | } else { |
743 | writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); | |
a74a8216 | 744 | return 0; |
1da177e4 | 745 | } |
1da177e4 LT |
746 | } |
747 | ||
748 | static int | |
a3aefd88 | 749 | snd_rme96_capture_analog_setrate(struct rme96 *rme96, |
1da177e4 LT |
750 | int rate) |
751 | { | |
752 | switch (rate) { | |
753 | case 32000: | |
754 | rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) & | |
755 | ~RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2; | |
756 | break; | |
757 | case 44100: | |
758 | rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) | | |
759 | RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2; | |
760 | break; | |
761 | case 48000: | |
762 | rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) | | |
763 | RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2; | |
764 | break; | |
765 | case 64000: | |
766 | if (rme96->rev < 4) { | |
767 | return -EINVAL; | |
768 | } | |
769 | rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) & | |
770 | ~RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2; | |
771 | break; | |
772 | case 88200: | |
773 | if (rme96->rev < 4) { | |
774 | return -EINVAL; | |
775 | } | |
776 | rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) | | |
777 | RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2; | |
778 | break; | |
779 | case 96000: | |
780 | rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) | | |
781 | RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2; | |
782 | break; | |
783 | default: | |
784 | return -EINVAL; | |
785 | } | |
786 | writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); | |
787 | return 0; | |
788 | } | |
789 | ||
790 | static int | |
a3aefd88 | 791 | snd_rme96_setclockmode(struct rme96 *rme96, |
1da177e4 LT |
792 | int mode) |
793 | { | |
794 | switch (mode) { | |
795 | case RME96_CLOCKMODE_SLAVE: | |
796 | /* AutoSync */ | |
797 | rme96->wcreg &= ~RME96_WCR_MASTER; | |
798 | rme96->areg &= ~RME96_AR_WSEL; | |
799 | break; | |
800 | case RME96_CLOCKMODE_MASTER: | |
801 | /* Internal */ | |
802 | rme96->wcreg |= RME96_WCR_MASTER; | |
803 | rme96->areg &= ~RME96_AR_WSEL; | |
804 | break; | |
805 | case RME96_CLOCKMODE_WORDCLOCK: | |
806 | /* Word clock is a master mode */ | |
807 | rme96->wcreg |= RME96_WCR_MASTER; | |
808 | rme96->areg |= RME96_AR_WSEL; | |
809 | break; | |
810 | default: | |
811 | return -EINVAL; | |
812 | } | |
813 | writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); | |
814 | writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); | |
815 | return 0; | |
816 | } | |
817 | ||
818 | static int | |
a3aefd88 | 819 | snd_rme96_getclockmode(struct rme96 *rme96) |
1da177e4 LT |
820 | { |
821 | if (rme96->areg & RME96_AR_WSEL) { | |
822 | return RME96_CLOCKMODE_WORDCLOCK; | |
823 | } | |
824 | return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER : | |
825 | RME96_CLOCKMODE_SLAVE; | |
826 | } | |
827 | ||
828 | static int | |
a3aefd88 | 829 | snd_rme96_setinputtype(struct rme96 *rme96, |
1da177e4 LT |
830 | int type) |
831 | { | |
832 | int n; | |
833 | ||
834 | switch (type) { | |
835 | case RME96_INPUT_OPTICAL: | |
836 | rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) & | |
837 | ~RME96_WCR_INP_1; | |
838 | break; | |
839 | case RME96_INPUT_COAXIAL: | |
840 | rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) & | |
841 | ~RME96_WCR_INP_1; | |
842 | break; | |
843 | case RME96_INPUT_INTERNAL: | |
844 | rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) | | |
845 | RME96_WCR_INP_1; | |
846 | break; | |
847 | case RME96_INPUT_XLR: | |
8b7fc421 RD |
848 | if ((rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && |
849 | rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PRO) || | |
850 | (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && | |
1da177e4 LT |
851 | rme96->rev > 4)) |
852 | { | |
853 | /* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */ | |
854 | return -EINVAL; | |
855 | } | |
856 | rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) | | |
857 | RME96_WCR_INP_1; | |
858 | break; | |
859 | case RME96_INPUT_ANALOG: | |
860 | if (!RME96_HAS_ANALOG_IN(rme96)) { | |
861 | return -EINVAL; | |
862 | } | |
863 | rme96->areg |= RME96_AR_ANALOG; | |
864 | writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); | |
865 | if (rme96->rev < 4) { | |
866 | /* | |
867 | * Revision less than 004 does not support 64 and | |
868 | * 88.2 kHz | |
869 | */ | |
870 | if (snd_rme96_capture_getrate(rme96, &n) == 88200) { | |
871 | snd_rme96_capture_analog_setrate(rme96, 44100); | |
872 | } | |
873 | if (snd_rme96_capture_getrate(rme96, &n) == 64000) { | |
874 | snd_rme96_capture_analog_setrate(rme96, 32000); | |
875 | } | |
876 | } | |
877 | return 0; | |
878 | default: | |
879 | return -EINVAL; | |
880 | } | |
881 | if (type != RME96_INPUT_ANALOG && RME96_HAS_ANALOG_IN(rme96)) { | |
882 | rme96->areg &= ~RME96_AR_ANALOG; | |
883 | writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); | |
884 | } | |
885 | writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); | |
886 | return 0; | |
887 | } | |
888 | ||
889 | static int | |
a3aefd88 | 890 | snd_rme96_getinputtype(struct rme96 *rme96) |
1da177e4 LT |
891 | { |
892 | if (rme96->areg & RME96_AR_ANALOG) { | |
893 | return RME96_INPUT_ANALOG; | |
894 | } | |
895 | return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) + | |
896 | (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1); | |
897 | } | |
898 | ||
899 | static void | |
a3aefd88 | 900 | snd_rme96_setframelog(struct rme96 *rme96, |
1da177e4 LT |
901 | int n_channels, |
902 | int is_playback) | |
903 | { | |
904 | int frlog; | |
905 | ||
906 | if (n_channels == 2) { | |
907 | frlog = 1; | |
908 | } else { | |
909 | /* assume 8 channels */ | |
910 | frlog = 3; | |
911 | } | |
912 | if (is_playback) { | |
913 | frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1; | |
914 | rme96->playback_frlog = frlog; | |
915 | } else { | |
916 | frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1; | |
917 | rme96->capture_frlog = frlog; | |
918 | } | |
919 | } | |
920 | ||
921 | static int | |
6c869d30 | 922 | snd_rme96_playback_setformat(struct rme96 *rme96, snd_pcm_format_t format) |
1da177e4 LT |
923 | { |
924 | switch (format) { | |
925 | case SNDRV_PCM_FORMAT_S16_LE: | |
926 | rme96->wcreg &= ~RME96_WCR_MODE24; | |
927 | break; | |
928 | case SNDRV_PCM_FORMAT_S32_LE: | |
929 | rme96->wcreg |= RME96_WCR_MODE24; | |
930 | break; | |
931 | default: | |
932 | return -EINVAL; | |
933 | } | |
934 | writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); | |
935 | return 0; | |
936 | } | |
937 | ||
938 | static int | |
6c869d30 | 939 | snd_rme96_capture_setformat(struct rme96 *rme96, snd_pcm_format_t format) |
1da177e4 LT |
940 | { |
941 | switch (format) { | |
942 | case SNDRV_PCM_FORMAT_S16_LE: | |
943 | rme96->wcreg &= ~RME96_WCR_MODE24_2; | |
944 | break; | |
945 | case SNDRV_PCM_FORMAT_S32_LE: | |
946 | rme96->wcreg |= RME96_WCR_MODE24_2; | |
947 | break; | |
948 | default: | |
949 | return -EINVAL; | |
950 | } | |
951 | writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); | |
952 | return 0; | |
953 | } | |
954 | ||
955 | static void | |
a3aefd88 | 956 | snd_rme96_set_period_properties(struct rme96 *rme96, |
1da177e4 LT |
957 | size_t period_bytes) |
958 | { | |
959 | switch (period_bytes) { | |
960 | case RME96_LARGE_BLOCK_SIZE: | |
961 | rme96->wcreg &= ~RME96_WCR_ISEL; | |
962 | break; | |
963 | case RME96_SMALL_BLOCK_SIZE: | |
964 | rme96->wcreg |= RME96_WCR_ISEL; | |
965 | break; | |
966 | default: | |
967 | snd_BUG(); | |
968 | break; | |
969 | } | |
970 | rme96->wcreg &= ~RME96_WCR_IDIS; | |
971 | writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); | |
972 | } | |
973 | ||
974 | static int | |
a3aefd88 TI |
975 | snd_rme96_playback_hw_params(struct snd_pcm_substream *substream, |
976 | struct snd_pcm_hw_params *params) | |
1da177e4 | 977 | { |
a3aefd88 TI |
978 | struct rme96 *rme96 = snd_pcm_substream_chip(substream); |
979 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 | 980 | int err, rate, dummy; |
a74a8216 | 981 | bool apply_dac_volume = false; |
1da177e4 | 982 | |
4d23359b CL |
983 | runtime->dma_area = (void __force *)(rme96->iobase + |
984 | RME96_IO_PLAY_BUFFER); | |
1da177e4 LT |
985 | runtime->dma_addr = rme96->port + RME96_IO_PLAY_BUFFER; |
986 | runtime->dma_bytes = RME96_BUFFER_SIZE; | |
987 | ||
988 | spin_lock_irq(&rme96->lock); | |
da8eedb1 | 989 | rate = 0; |
1da177e4 | 990 | if (!(rme96->wcreg & RME96_WCR_MASTER) && |
da8eedb1 TI |
991 | snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG) |
992 | rate = snd_rme96_capture_getrate(rme96, &dummy); | |
993 | if (rate > 0) { | |
1da177e4 LT |
994 | /* slave clock */ |
995 | if ((int)params_rate(params) != rate) { | |
a74a8216 TI |
996 | err = -EIO; |
997 | goto error; | |
998 | } | |
999 | } else { | |
1000 | err = snd_rme96_playback_setrate(rme96, params_rate(params)); | |
1001 | if (err < 0) | |
1002 | goto error; | |
1003 | apply_dac_volume = err > 0; /* need to restore volume later? */ | |
1da177e4 | 1004 | } |
a74a8216 TI |
1005 | |
1006 | err = snd_rme96_playback_setformat(rme96, params_format(params)); | |
1007 | if (err < 0) | |
1008 | goto error; | |
1da177e4 LT |
1009 | snd_rme96_setframelog(rme96, params_channels(params), 1); |
1010 | if (rme96->capture_periodsize != 0) { | |
1011 | if (params_period_size(params) << rme96->playback_frlog != | |
1012 | rme96->capture_periodsize) | |
1013 | { | |
a74a8216 TI |
1014 | err = -EBUSY; |
1015 | goto error; | |
1da177e4 LT |
1016 | } |
1017 | } | |
1018 | rme96->playback_periodsize = | |
1019 | params_period_size(params) << rme96->playback_frlog; | |
1020 | snd_rme96_set_period_properties(rme96, rme96->playback_periodsize); | |
1021 | /* S/PDIF setup */ | |
1022 | if ((rme96->wcreg & RME96_WCR_ADAT) == 0) { | |
1023 | rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP); | |
1024 | writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER); | |
1025 | } | |
a74a8216 TI |
1026 | |
1027 | err = 0; | |
1028 | error: | |
1da177e4 | 1029 | spin_unlock_irq(&rme96->lock); |
a74a8216 TI |
1030 | if (apply_dac_volume) { |
1031 | usleep_range(3000, 10000); | |
1032 | snd_rme96_apply_dac_volume(rme96); | |
1033 | } | |
1034 | ||
1035 | return err; | |
1da177e4 LT |
1036 | } |
1037 | ||
1038 | static int | |
a3aefd88 TI |
1039 | snd_rme96_capture_hw_params(struct snd_pcm_substream *substream, |
1040 | struct snd_pcm_hw_params *params) | |
1da177e4 | 1041 | { |
a3aefd88 TI |
1042 | struct rme96 *rme96 = snd_pcm_substream_chip(substream); |
1043 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 LT |
1044 | int err, isadat, rate; |
1045 | ||
4d23359b CL |
1046 | runtime->dma_area = (void __force *)(rme96->iobase + |
1047 | RME96_IO_REC_BUFFER); | |
1da177e4 LT |
1048 | runtime->dma_addr = rme96->port + RME96_IO_REC_BUFFER; |
1049 | runtime->dma_bytes = RME96_BUFFER_SIZE; | |
1050 | ||
1051 | spin_lock_irq(&rme96->lock); | |
da8eedb1 TI |
1052 | err = snd_rme96_capture_setformat(rme96, params_format(params)); |
1053 | if (err < 0) { | |
1da177e4 LT |
1054 | spin_unlock_irq(&rme96->lock); |
1055 | return err; | |
1056 | } | |
1057 | if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) { | |
da8eedb1 TI |
1058 | err = snd_rme96_capture_analog_setrate(rme96, params_rate(params)); |
1059 | if (err < 0) { | |
1da177e4 LT |
1060 | spin_unlock_irq(&rme96->lock); |
1061 | return err; | |
1062 | } | |
da8eedb1 TI |
1063 | } else { |
1064 | rate = snd_rme96_capture_getrate(rme96, &isadat); | |
1065 | if (rate > 0) { | |
1066 | if ((int)params_rate(params) != rate) { | |
1067 | spin_unlock_irq(&rme96->lock); | |
1068 | return -EIO; | |
1069 | } | |
1070 | if ((isadat && runtime->hw.channels_min == 2) || | |
1071 | (!isadat && runtime->hw.channels_min == 8)) { | |
1072 | spin_unlock_irq(&rme96->lock); | |
1073 | return -EIO; | |
1074 | } | |
1075 | } | |
1da177e4 LT |
1076 | } |
1077 | snd_rme96_setframelog(rme96, params_channels(params), 0); | |
1078 | if (rme96->playback_periodsize != 0) { | |
1079 | if (params_period_size(params) << rme96->capture_frlog != | |
1080 | rme96->playback_periodsize) | |
1081 | { | |
1082 | spin_unlock_irq(&rme96->lock); | |
1083 | return -EBUSY; | |
1084 | } | |
1085 | } | |
1086 | rme96->capture_periodsize = | |
1087 | params_period_size(params) << rme96->capture_frlog; | |
1088 | snd_rme96_set_period_properties(rme96, rme96->capture_periodsize); | |
1089 | spin_unlock_irq(&rme96->lock); | |
1090 | ||
1091 | return 0; | |
1092 | } | |
1093 | ||
1094 | static void | |
b892ca1c KP |
1095 | snd_rme96_trigger(struct rme96 *rme96, |
1096 | int op) | |
1da177e4 | 1097 | { |
b892ca1c | 1098 | if (op & RME96_TB_RESET_PLAYPOS) |
1da177e4 | 1099 | writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS); |
b892ca1c | 1100 | if (op & RME96_TB_RESET_CAPTUREPOS) |
1da177e4 | 1101 | writel(0, rme96->iobase + RME96_IO_RESET_REC_POS); |
b892ca1c KP |
1102 | if (op & RME96_TB_CLEAR_PLAYBACK_IRQ) { |
1103 | rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); | |
1104 | if (rme96->rcreg & RME96_RCR_IRQ) | |
1105 | writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ); | |
1da177e4 | 1106 | } |
b892ca1c KP |
1107 | if (op & RME96_TB_CLEAR_CAPTURE_IRQ) { |
1108 | rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); | |
1109 | if (rme96->rcreg & RME96_RCR_IRQ_2) | |
1110 | writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ); | |
1111 | } | |
1112 | if (op & RME96_TB_START_PLAYBACK) | |
1113 | rme96->wcreg |= RME96_WCR_START; | |
1114 | if (op & RME96_TB_STOP_PLAYBACK) | |
1115 | rme96->wcreg &= ~RME96_WCR_START; | |
1116 | if (op & RME96_TB_START_CAPTURE) | |
1117 | rme96->wcreg |= RME96_WCR_START_2; | |
1118 | if (op & RME96_TB_STOP_CAPTURE) | |
1119 | rme96->wcreg &= ~RME96_WCR_START_2; | |
1da177e4 LT |
1120 | writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); |
1121 | } | |
1122 | ||
1da177e4 | 1123 | |
1da177e4 LT |
1124 | |
1125 | static irqreturn_t | |
1126 | snd_rme96_interrupt(int irq, | |
7d12e780 | 1127 | void *dev_id) |
1da177e4 | 1128 | { |
a3aefd88 | 1129 | struct rme96 *rme96 = (struct rme96 *)dev_id; |
1da177e4 LT |
1130 | |
1131 | rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); | |
1132 | /* fastpath out, to ease interrupt sharing */ | |
1133 | if (!((rme96->rcreg & RME96_RCR_IRQ) || | |
1134 | (rme96->rcreg & RME96_RCR_IRQ_2))) | |
1135 | { | |
1136 | return IRQ_NONE; | |
1137 | } | |
1138 | ||
1139 | if (rme96->rcreg & RME96_RCR_IRQ) { | |
1140 | /* playback */ | |
1141 | snd_pcm_period_elapsed(rme96->playback_substream); | |
1142 | writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ); | |
1143 | } | |
1144 | if (rme96->rcreg & RME96_RCR_IRQ_2) { | |
1145 | /* capture */ | |
1146 | snd_pcm_period_elapsed(rme96->capture_substream); | |
1147 | writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ); | |
1148 | } | |
1149 | return IRQ_HANDLED; | |
1150 | } | |
1151 | ||
84e7b998 | 1152 | static const unsigned int period_bytes[] = { RME96_SMALL_BLOCK_SIZE, RME96_LARGE_BLOCK_SIZE }; |
1da177e4 | 1153 | |
84e7b998 | 1154 | static const struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = { |
1da177e4 LT |
1155 | .count = ARRAY_SIZE(period_bytes), |
1156 | .list = period_bytes, | |
1157 | .mask = 0 | |
1158 | }; | |
1159 | ||
2ce7fb57 TI |
1160 | static void |
1161 | rme96_set_buffer_size_constraint(struct rme96 *rme96, | |
1162 | struct snd_pcm_runtime *runtime) | |
1163 | { | |
1164 | unsigned int size; | |
1165 | ||
1a8e41ef LPC |
1166 | snd_pcm_hw_constraint_single(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, |
1167 | RME96_BUFFER_SIZE); | |
da8eedb1 TI |
1168 | size = rme96->playback_periodsize; |
1169 | if (!size) | |
1170 | size = rme96->capture_periodsize; | |
1171 | if (size) | |
1a8e41ef | 1172 | snd_pcm_hw_constraint_single(runtime, |
2ce7fb57 | 1173 | SNDRV_PCM_HW_PARAM_PERIOD_BYTES, |
1a8e41ef | 1174 | size); |
2ce7fb57 TI |
1175 | else |
1176 | snd_pcm_hw_constraint_list(runtime, 0, | |
1177 | SNDRV_PCM_HW_PARAM_PERIOD_BYTES, | |
1178 | &hw_constraints_period_bytes); | |
1179 | } | |
1180 | ||
1da177e4 | 1181 | static int |
a3aefd88 | 1182 | snd_rme96_playback_spdif_open(struct snd_pcm_substream *substream) |
1da177e4 LT |
1183 | { |
1184 | int rate, dummy; | |
a3aefd88 TI |
1185 | struct rme96 *rme96 = snd_pcm_substream_chip(substream); |
1186 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 | 1187 | |
b892ca1c | 1188 | snd_pcm_set_sync(substream); |
1da177e4 | 1189 | spin_lock_irq(&rme96->lock); |
2cb98d01 | 1190 | if (rme96->playback_substream) { |
1da177e4 LT |
1191 | spin_unlock_irq(&rme96->lock); |
1192 | return -EBUSY; | |
1193 | } | |
1194 | rme96->wcreg &= ~RME96_WCR_ADAT; | |
1195 | writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); | |
1196 | rme96->playback_substream = substream; | |
1197 | spin_unlock_irq(&rme96->lock); | |
1198 | ||
1199 | runtime->hw = snd_rme96_playback_spdif_info; | |
1200 | if (!(rme96->wcreg & RME96_WCR_MASTER) && | |
da8eedb1 TI |
1201 | snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG) { |
1202 | rate = snd_rme96_capture_getrate(rme96, &dummy); | |
1203 | if (rate > 0) { | |
1204 | /* slave clock */ | |
1205 | runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); | |
1206 | runtime->hw.rate_min = rate; | |
1207 | runtime->hw.rate_max = rate; | |
1208 | } | |
1da177e4 | 1209 | } |
2ce7fb57 | 1210 | rme96_set_buffer_size_constraint(rme96, runtime); |
1da177e4 LT |
1211 | |
1212 | rme96->wcreg_spdif_stream = rme96->wcreg_spdif; | |
1213 | rme96->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; | |
1214 | snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE | | |
1215 | SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id); | |
1216 | return 0; | |
1217 | } | |
1218 | ||
1219 | static int | |
a3aefd88 | 1220 | snd_rme96_capture_spdif_open(struct snd_pcm_substream *substream) |
1da177e4 LT |
1221 | { |
1222 | int isadat, rate; | |
a3aefd88 TI |
1223 | struct rme96 *rme96 = snd_pcm_substream_chip(substream); |
1224 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 | 1225 | |
b892ca1c | 1226 | snd_pcm_set_sync(substream); |
1da177e4 | 1227 | runtime->hw = snd_rme96_capture_spdif_info; |
da8eedb1 TI |
1228 | if (snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG) { |
1229 | rate = snd_rme96_capture_getrate(rme96, &isadat); | |
1230 | if (rate > 0) { | |
1231 | if (isadat) | |
1232 | return -EIO; | |
1233 | runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); | |
1234 | runtime->hw.rate_min = rate; | |
1235 | runtime->hw.rate_max = rate; | |
1236 | } | |
1237 | } | |
1da177e4 LT |
1238 | |
1239 | spin_lock_irq(&rme96->lock); | |
2cb98d01 | 1240 | if (rme96->capture_substream) { |
1da177e4 LT |
1241 | spin_unlock_irq(&rme96->lock); |
1242 | return -EBUSY; | |
1243 | } | |
1244 | rme96->capture_substream = substream; | |
1245 | spin_unlock_irq(&rme96->lock); | |
1246 | ||
2ce7fb57 | 1247 | rme96_set_buffer_size_constraint(rme96, runtime); |
1da177e4 LT |
1248 | return 0; |
1249 | } | |
1250 | ||
1251 | static int | |
a3aefd88 | 1252 | snd_rme96_playback_adat_open(struct snd_pcm_substream *substream) |
1da177e4 LT |
1253 | { |
1254 | int rate, dummy; | |
a3aefd88 TI |
1255 | struct rme96 *rme96 = snd_pcm_substream_chip(substream); |
1256 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 | 1257 | |
b892ca1c | 1258 | snd_pcm_set_sync(substream); |
1da177e4 | 1259 | spin_lock_irq(&rme96->lock); |
2cb98d01 | 1260 | if (rme96->playback_substream) { |
1da177e4 LT |
1261 | spin_unlock_irq(&rme96->lock); |
1262 | return -EBUSY; | |
1263 | } | |
1264 | rme96->wcreg |= RME96_WCR_ADAT; | |
1265 | writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); | |
1266 | rme96->playback_substream = substream; | |
1267 | spin_unlock_irq(&rme96->lock); | |
1268 | ||
1269 | runtime->hw = snd_rme96_playback_adat_info; | |
1270 | if (!(rme96->wcreg & RME96_WCR_MASTER) && | |
da8eedb1 TI |
1271 | snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG) { |
1272 | rate = snd_rme96_capture_getrate(rme96, &dummy); | |
1273 | if (rate > 0) { | |
1274 | /* slave clock */ | |
1275 | runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); | |
1276 | runtime->hw.rate_min = rate; | |
1277 | runtime->hw.rate_max = rate; | |
1278 | } | |
1279 | } | |
1280 | ||
2ce7fb57 | 1281 | rme96_set_buffer_size_constraint(rme96, runtime); |
1da177e4 LT |
1282 | return 0; |
1283 | } | |
1284 | ||
1285 | static int | |
a3aefd88 | 1286 | snd_rme96_capture_adat_open(struct snd_pcm_substream *substream) |
1da177e4 LT |
1287 | { |
1288 | int isadat, rate; | |
a3aefd88 TI |
1289 | struct rme96 *rme96 = snd_pcm_substream_chip(substream); |
1290 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 | 1291 | |
b892ca1c | 1292 | snd_pcm_set_sync(substream); |
1da177e4 LT |
1293 | runtime->hw = snd_rme96_capture_adat_info; |
1294 | if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) { | |
1295 | /* makes no sense to use analog input. Note that analog | |
1296 | expension cards AEB4/8-I are RME96_INPUT_INTERNAL */ | |
1297 | return -EIO; | |
1298 | } | |
da8eedb1 TI |
1299 | rate = snd_rme96_capture_getrate(rme96, &isadat); |
1300 | if (rate > 0) { | |
1da177e4 LT |
1301 | if (!isadat) { |
1302 | return -EIO; | |
1303 | } | |
918f3a0e | 1304 | runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); |
1da177e4 LT |
1305 | runtime->hw.rate_min = rate; |
1306 | runtime->hw.rate_max = rate; | |
1307 | } | |
1308 | ||
1309 | spin_lock_irq(&rme96->lock); | |
2cb98d01 | 1310 | if (rme96->capture_substream) { |
1da177e4 LT |
1311 | spin_unlock_irq(&rme96->lock); |
1312 | return -EBUSY; | |
1313 | } | |
1314 | rme96->capture_substream = substream; | |
1315 | spin_unlock_irq(&rme96->lock); | |
1316 | ||
2ce7fb57 | 1317 | rme96_set_buffer_size_constraint(rme96, runtime); |
1da177e4 LT |
1318 | return 0; |
1319 | } | |
1320 | ||
1321 | static int | |
a3aefd88 | 1322 | snd_rme96_playback_close(struct snd_pcm_substream *substream) |
1da177e4 | 1323 | { |
a3aefd88 | 1324 | struct rme96 *rme96 = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1325 | int spdif = 0; |
1326 | ||
1327 | spin_lock_irq(&rme96->lock); | |
1328 | if (RME96_ISPLAYING(rme96)) { | |
b892ca1c | 1329 | snd_rme96_trigger(rme96, RME96_STOP_PLAYBACK); |
1da177e4 LT |
1330 | } |
1331 | rme96->playback_substream = NULL; | |
1332 | rme96->playback_periodsize = 0; | |
1333 | spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0; | |
1334 | spin_unlock_irq(&rme96->lock); | |
1335 | if (spdif) { | |
1336 | rme96->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; | |
1337 | snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE | | |
1338 | SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id); | |
1339 | } | |
1340 | return 0; | |
1341 | } | |
1342 | ||
1343 | static int | |
a3aefd88 | 1344 | snd_rme96_capture_close(struct snd_pcm_substream *substream) |
1da177e4 | 1345 | { |
a3aefd88 | 1346 | struct rme96 *rme96 = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1347 | |
1348 | spin_lock_irq(&rme96->lock); | |
1349 | if (RME96_ISRECORDING(rme96)) { | |
b892ca1c | 1350 | snd_rme96_trigger(rme96, RME96_STOP_CAPTURE); |
1da177e4 LT |
1351 | } |
1352 | rme96->capture_substream = NULL; | |
1353 | rme96->capture_periodsize = 0; | |
1354 | spin_unlock_irq(&rme96->lock); | |
1355 | return 0; | |
1356 | } | |
1357 | ||
1358 | static int | |
a3aefd88 | 1359 | snd_rme96_playback_prepare(struct snd_pcm_substream *substream) |
1da177e4 | 1360 | { |
a3aefd88 | 1361 | struct rme96 *rme96 = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1362 | |
1363 | spin_lock_irq(&rme96->lock); | |
1364 | if (RME96_ISPLAYING(rme96)) { | |
b892ca1c | 1365 | snd_rme96_trigger(rme96, RME96_STOP_PLAYBACK); |
1da177e4 LT |
1366 | } |
1367 | writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS); | |
1368 | spin_unlock_irq(&rme96->lock); | |
1369 | return 0; | |
1370 | } | |
1371 | ||
1372 | static int | |
a3aefd88 | 1373 | snd_rme96_capture_prepare(struct snd_pcm_substream *substream) |
1da177e4 | 1374 | { |
a3aefd88 | 1375 | struct rme96 *rme96 = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1376 | |
1377 | spin_lock_irq(&rme96->lock); | |
1378 | if (RME96_ISRECORDING(rme96)) { | |
b892ca1c | 1379 | snd_rme96_trigger(rme96, RME96_STOP_CAPTURE); |
1da177e4 LT |
1380 | } |
1381 | writel(0, rme96->iobase + RME96_IO_RESET_REC_POS); | |
1382 | spin_unlock_irq(&rme96->lock); | |
1383 | return 0; | |
1384 | } | |
1385 | ||
1386 | static int | |
a3aefd88 | 1387 | snd_rme96_playback_trigger(struct snd_pcm_substream *substream, |
1da177e4 LT |
1388 | int cmd) |
1389 | { | |
a3aefd88 | 1390 | struct rme96 *rme96 = snd_pcm_substream_chip(substream); |
b892ca1c KP |
1391 | struct snd_pcm_substream *s; |
1392 | bool sync; | |
1393 | ||
1394 | snd_pcm_group_for_each_entry(s, substream) { | |
1395 | if (snd_pcm_substream_chip(s) == rme96) | |
1396 | snd_pcm_trigger_done(s, substream); | |
1397 | } | |
1398 | ||
1399 | sync = (rme96->playback_substream && rme96->capture_substream) && | |
1400 | (rme96->playback_substream->group == | |
1401 | rme96->capture_substream->group); | |
1da177e4 LT |
1402 | |
1403 | switch (cmd) { | |
1404 | case SNDRV_PCM_TRIGGER_START: | |
1405 | if (!RME96_ISPLAYING(rme96)) { | |
b892ca1c | 1406 | if (substream != rme96->playback_substream) |
1da177e4 | 1407 | return -EBUSY; |
b892ca1c KP |
1408 | snd_rme96_trigger(rme96, sync ? RME96_START_BOTH |
1409 | : RME96_START_PLAYBACK); | |
1da177e4 LT |
1410 | } |
1411 | break; | |
1412 | ||
528ba522 | 1413 | case SNDRV_PCM_TRIGGER_SUSPEND: |
1da177e4 LT |
1414 | case SNDRV_PCM_TRIGGER_STOP: |
1415 | if (RME96_ISPLAYING(rme96)) { | |
b892ca1c | 1416 | if (substream != rme96->playback_substream) |
1da177e4 | 1417 | return -EBUSY; |
b892ca1c KP |
1418 | snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH |
1419 | : RME96_STOP_PLAYBACK); | |
1da177e4 LT |
1420 | } |
1421 | break; | |
1422 | ||
1423 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
b892ca1c KP |
1424 | if (RME96_ISPLAYING(rme96)) |
1425 | snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH | |
1426 | : RME96_STOP_PLAYBACK); | |
1da177e4 LT |
1427 | break; |
1428 | ||
528ba522 | 1429 | case SNDRV_PCM_TRIGGER_RESUME: |
1da177e4 | 1430 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
b892ca1c KP |
1431 | if (!RME96_ISPLAYING(rme96)) |
1432 | snd_rme96_trigger(rme96, sync ? RME96_RESUME_BOTH | |
1433 | : RME96_RESUME_PLAYBACK); | |
1da177e4 | 1434 | break; |
b892ca1c | 1435 | |
1da177e4 LT |
1436 | default: |
1437 | return -EINVAL; | |
1438 | } | |
b892ca1c | 1439 | |
1da177e4 LT |
1440 | return 0; |
1441 | } | |
1442 | ||
1443 | static int | |
a3aefd88 | 1444 | snd_rme96_capture_trigger(struct snd_pcm_substream *substream, |
1da177e4 LT |
1445 | int cmd) |
1446 | { | |
a3aefd88 | 1447 | struct rme96 *rme96 = snd_pcm_substream_chip(substream); |
b892ca1c KP |
1448 | struct snd_pcm_substream *s; |
1449 | bool sync; | |
1450 | ||
1451 | snd_pcm_group_for_each_entry(s, substream) { | |
1452 | if (snd_pcm_substream_chip(s) == rme96) | |
1453 | snd_pcm_trigger_done(s, substream); | |
1454 | } | |
1455 | ||
1456 | sync = (rme96->playback_substream && rme96->capture_substream) && | |
1457 | (rme96->playback_substream->group == | |
1458 | rme96->capture_substream->group); | |
1da177e4 LT |
1459 | |
1460 | switch (cmd) { | |
1461 | case SNDRV_PCM_TRIGGER_START: | |
1462 | if (!RME96_ISRECORDING(rme96)) { | |
b892ca1c | 1463 | if (substream != rme96->capture_substream) |
1da177e4 | 1464 | return -EBUSY; |
b892ca1c KP |
1465 | snd_rme96_trigger(rme96, sync ? RME96_START_BOTH |
1466 | : RME96_START_CAPTURE); | |
1da177e4 LT |
1467 | } |
1468 | break; | |
1469 | ||
528ba522 | 1470 | case SNDRV_PCM_TRIGGER_SUSPEND: |
1da177e4 LT |
1471 | case SNDRV_PCM_TRIGGER_STOP: |
1472 | if (RME96_ISRECORDING(rme96)) { | |
b892ca1c | 1473 | if (substream != rme96->capture_substream) |
1da177e4 | 1474 | return -EBUSY; |
b892ca1c KP |
1475 | snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH |
1476 | : RME96_STOP_CAPTURE); | |
1da177e4 LT |
1477 | } |
1478 | break; | |
1479 | ||
1480 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
b892ca1c KP |
1481 | if (RME96_ISRECORDING(rme96)) |
1482 | snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH | |
1483 | : RME96_STOP_CAPTURE); | |
1da177e4 LT |
1484 | break; |
1485 | ||
528ba522 | 1486 | case SNDRV_PCM_TRIGGER_RESUME: |
1da177e4 | 1487 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
b892ca1c KP |
1488 | if (!RME96_ISRECORDING(rme96)) |
1489 | snd_rme96_trigger(rme96, sync ? RME96_RESUME_BOTH | |
1490 | : RME96_RESUME_CAPTURE); | |
1da177e4 | 1491 | break; |
b892ca1c | 1492 | |
1da177e4 LT |
1493 | default: |
1494 | return -EINVAL; | |
1495 | } | |
1496 | ||
1497 | return 0; | |
1498 | } | |
1499 | ||
1500 | static snd_pcm_uframes_t | |
a3aefd88 | 1501 | snd_rme96_playback_pointer(struct snd_pcm_substream *substream) |
1da177e4 | 1502 | { |
a3aefd88 | 1503 | struct rme96 *rme96 = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1504 | return snd_rme96_playback_ptr(rme96); |
1505 | } | |
1506 | ||
1507 | static snd_pcm_uframes_t | |
a3aefd88 | 1508 | snd_rme96_capture_pointer(struct snd_pcm_substream *substream) |
1da177e4 | 1509 | { |
a3aefd88 | 1510 | struct rme96 *rme96 = snd_pcm_substream_chip(substream); |
1da177e4 LT |
1511 | return snd_rme96_capture_ptr(rme96); |
1512 | } | |
1513 | ||
6769e988 | 1514 | static const struct snd_pcm_ops snd_rme96_playback_spdif_ops = { |
1da177e4 LT |
1515 | .open = snd_rme96_playback_spdif_open, |
1516 | .close = snd_rme96_playback_close, | |
1da177e4 LT |
1517 | .hw_params = snd_rme96_playback_hw_params, |
1518 | .prepare = snd_rme96_playback_prepare, | |
1519 | .trigger = snd_rme96_playback_trigger, | |
1520 | .pointer = snd_rme96_playback_pointer, | |
53945f5b TI |
1521 | .copy_user = snd_rme96_playback_copy, |
1522 | .copy_kernel = snd_rme96_playback_copy_kernel, | |
1523 | .fill_silence = snd_rme96_playback_silence, | |
1da177e4 LT |
1524 | .mmap = snd_pcm_lib_mmap_iomem, |
1525 | }; | |
1526 | ||
6769e988 | 1527 | static const struct snd_pcm_ops snd_rme96_capture_spdif_ops = { |
1da177e4 LT |
1528 | .open = snd_rme96_capture_spdif_open, |
1529 | .close = snd_rme96_capture_close, | |
1da177e4 LT |
1530 | .hw_params = snd_rme96_capture_hw_params, |
1531 | .prepare = snd_rme96_capture_prepare, | |
1532 | .trigger = snd_rme96_capture_trigger, | |
1533 | .pointer = snd_rme96_capture_pointer, | |
53945f5b TI |
1534 | .copy_user = snd_rme96_capture_copy, |
1535 | .copy_kernel = snd_rme96_capture_copy_kernel, | |
1da177e4 LT |
1536 | .mmap = snd_pcm_lib_mmap_iomem, |
1537 | }; | |
1538 | ||
6769e988 | 1539 | static const struct snd_pcm_ops snd_rme96_playback_adat_ops = { |
1da177e4 LT |
1540 | .open = snd_rme96_playback_adat_open, |
1541 | .close = snd_rme96_playback_close, | |
1da177e4 LT |
1542 | .hw_params = snd_rme96_playback_hw_params, |
1543 | .prepare = snd_rme96_playback_prepare, | |
1544 | .trigger = snd_rme96_playback_trigger, | |
1545 | .pointer = snd_rme96_playback_pointer, | |
53945f5b TI |
1546 | .copy_user = snd_rme96_playback_copy, |
1547 | .copy_kernel = snd_rme96_playback_copy_kernel, | |
1548 | .fill_silence = snd_rme96_playback_silence, | |
1da177e4 LT |
1549 | .mmap = snd_pcm_lib_mmap_iomem, |
1550 | }; | |
1551 | ||
6769e988 | 1552 | static const struct snd_pcm_ops snd_rme96_capture_adat_ops = { |
1da177e4 LT |
1553 | .open = snd_rme96_capture_adat_open, |
1554 | .close = snd_rme96_capture_close, | |
1da177e4 LT |
1555 | .hw_params = snd_rme96_capture_hw_params, |
1556 | .prepare = snd_rme96_capture_prepare, | |
1557 | .trigger = snd_rme96_capture_trigger, | |
1558 | .pointer = snd_rme96_capture_pointer, | |
53945f5b TI |
1559 | .copy_user = snd_rme96_capture_copy, |
1560 | .copy_kernel = snd_rme96_capture_copy_kernel, | |
1da177e4 LT |
1561 | .mmap = snd_pcm_lib_mmap_iomem, |
1562 | }; | |
1563 | ||
1564 | static void | |
df06df7c | 1565 | snd_rme96_free(struct rme96 *rme96) |
1da177e4 | 1566 | { |
1da177e4 | 1567 | if (rme96->irq >= 0) { |
b892ca1c | 1568 | snd_rme96_trigger(rme96, RME96_STOP_BOTH); |
1da177e4 LT |
1569 | rme96->areg &= ~RME96_AR_DAC_EN; |
1570 | writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); | |
1da177e4 | 1571 | } |
a932be91 | 1572 | #ifdef CONFIG_PM_SLEEP |
528ba522 KP |
1573 | vfree(rme96->playback_suspend_buffer); |
1574 | vfree(rme96->capture_suspend_buffer); | |
1575 | #endif | |
1da177e4 LT |
1576 | } |
1577 | ||
1578 | static void | |
a3aefd88 | 1579 | snd_rme96_free_spdif_pcm(struct snd_pcm *pcm) |
1da177e4 | 1580 | { |
9fe856e4 | 1581 | struct rme96 *rme96 = pcm->private_data; |
1da177e4 LT |
1582 | rme96->spdif_pcm = NULL; |
1583 | } | |
1584 | ||
1585 | static void | |
a3aefd88 | 1586 | snd_rme96_free_adat_pcm(struct snd_pcm *pcm) |
1da177e4 | 1587 | { |
9fe856e4 | 1588 | struct rme96 *rme96 = pcm->private_data; |
1da177e4 LT |
1589 | rme96->adat_pcm = NULL; |
1590 | } | |
1591 | ||
e23e7a14 | 1592 | static int |
a3aefd88 | 1593 | snd_rme96_create(struct rme96 *rme96) |
1da177e4 LT |
1594 | { |
1595 | struct pci_dev *pci = rme96->pci; | |
1596 | int err; | |
1597 | ||
1598 | rme96->irq = -1; | |
1599 | spin_lock_init(&rme96->lock); | |
1600 | ||
df06df7c | 1601 | err = pcim_enable_device(pci); |
da8eedb1 | 1602 | if (err < 0) |
1da177e4 LT |
1603 | return err; |
1604 | ||
da8eedb1 TI |
1605 | err = pci_request_regions(pci, "RME96"); |
1606 | if (err < 0) | |
1da177e4 LT |
1607 | return err; |
1608 | rme96->port = pci_resource_start(rme96->pci, 0); | |
1609 | ||
df06df7c | 1610 | rme96->iobase = devm_ioremap(&pci->dev, rme96->port, RME96_IO_SIZE); |
44977b71 | 1611 | if (!rme96->iobase) { |
342cd934 TI |
1612 | dev_err(rme96->card->dev, |
1613 | "unable to remap memory region 0x%lx-0x%lx\n", | |
1614 | rme96->port, rme96->port + RME96_IO_SIZE - 1); | |
df06df7c | 1615 | return -EBUSY; |
688956f2 TI |
1616 | } |
1617 | ||
df06df7c TI |
1618 | if (devm_request_irq(&pci->dev, pci->irq, snd_rme96_interrupt, |
1619 | IRQF_SHARED, KBUILD_MODNAME, rme96)) { | |
342cd934 | 1620 | dev_err(rme96->card->dev, "unable to grab IRQ %d\n", pci->irq); |
1da177e4 LT |
1621 | return -EBUSY; |
1622 | } | |
1623 | rme96->irq = pci->irq; | |
5fcf46bc | 1624 | rme96->card->sync_irq = rme96->irq; |
1da177e4 | 1625 | |
1da177e4 LT |
1626 | /* read the card's revision number */ |
1627 | pci_read_config_byte(pci, 8, &rme96->rev); | |
1628 | ||
1629 | /* set up ALSA pcm device for S/PDIF */ | |
da8eedb1 TI |
1630 | err = snd_pcm_new(rme96->card, "Digi96 IEC958", 0, |
1631 | 1, 1, &rme96->spdif_pcm); | |
1632 | if (err < 0) | |
1da177e4 | 1633 | return err; |
da8eedb1 | 1634 | |
1da177e4 LT |
1635 | rme96->spdif_pcm->private_data = rme96; |
1636 | rme96->spdif_pcm->private_free = snd_rme96_free_spdif_pcm; | |
1637 | strcpy(rme96->spdif_pcm->name, "Digi96 IEC958"); | |
1638 | snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_spdif_ops); | |
1639 | snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_spdif_ops); | |
1640 | ||
1641 | rme96->spdif_pcm->info_flags = 0; | |
1642 | ||
1643 | /* set up ALSA pcm device for ADAT */ | |
8b7fc421 | 1644 | if (pci->device == PCI_DEVICE_ID_RME_DIGI96) { |
1da177e4 LT |
1645 | /* ADAT is not available on the base model */ |
1646 | rme96->adat_pcm = NULL; | |
1647 | } else { | |
da8eedb1 TI |
1648 | err = snd_pcm_new(rme96->card, "Digi96 ADAT", 1, |
1649 | 1, 1, &rme96->adat_pcm); | |
1650 | if (err < 0) | |
1da177e4 | 1651 | return err; |
1da177e4 LT |
1652 | rme96->adat_pcm->private_data = rme96; |
1653 | rme96->adat_pcm->private_free = snd_rme96_free_adat_pcm; | |
1654 | strcpy(rme96->adat_pcm->name, "Digi96 ADAT"); | |
1655 | snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_adat_ops); | |
1656 | snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_adat_ops); | |
1657 | ||
1658 | rme96->adat_pcm->info_flags = 0; | |
1659 | } | |
1660 | ||
1661 | rme96->playback_periodsize = 0; | |
1662 | rme96->capture_periodsize = 0; | |
1663 | ||
1664 | /* make sure playback/capture is stopped, if by some reason active */ | |
b892ca1c | 1665 | snd_rme96_trigger(rme96, RME96_STOP_BOTH); |
1da177e4 LT |
1666 | |
1667 | /* set default values in registers */ | |
1668 | rme96->wcreg = | |
1669 | RME96_WCR_FREQ_1 | /* set 44.1 kHz playback */ | |
1670 | RME96_WCR_SEL | /* normal playback */ | |
1671 | RME96_WCR_MASTER | /* set to master clock mode */ | |
1672 | RME96_WCR_INP_0; /* set coaxial input */ | |
1673 | ||
1674 | rme96->areg = RME96_AR_FREQPAD_1; /* set 44.1 kHz analog capture */ | |
1675 | ||
1676 | writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); | |
1677 | writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); | |
1678 | ||
1679 | /* reset the ADC */ | |
1680 | writel(rme96->areg | RME96_AR_PD2, | |
1681 | rme96->iobase + RME96_IO_ADDITIONAL_REG); | |
1682 | writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); | |
1683 | ||
1684 | /* reset and enable the DAC (order is important). */ | |
1685 | snd_rme96_reset_dac(rme96); | |
1686 | rme96->areg |= RME96_AR_DAC_EN; | |
1687 | writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); | |
1688 | ||
1689 | /* reset playback and record buffer pointers */ | |
1690 | writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS); | |
1691 | writel(0, rme96->iobase + RME96_IO_RESET_REC_POS); | |
1692 | ||
1693 | /* reset volume */ | |
1694 | rme96->vol[0] = rme96->vol[1] = 0; | |
1695 | if (RME96_HAS_ANALOG_OUT(rme96)) { | |
1696 | snd_rme96_apply_dac_volume(rme96); | |
1697 | } | |
1698 | ||
1699 | /* init switch interface */ | |
da8eedb1 TI |
1700 | err = snd_rme96_create_switches(rme96->card, rme96); |
1701 | if (err < 0) | |
1da177e4 | 1702 | return err; |
1da177e4 LT |
1703 | |
1704 | /* init proc interface */ | |
1705 | snd_rme96_proc_init(rme96); | |
1706 | ||
1707 | return 0; | |
1708 | } | |
1709 | ||
1710 | /* | |
1711 | * proc interface | |
1712 | */ | |
1713 | ||
1714 | static void | |
a3aefd88 | 1715 | snd_rme96_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer) |
1da177e4 LT |
1716 | { |
1717 | int n; | |
9fe856e4 | 1718 | struct rme96 *rme96 = entry->private_data; |
1da177e4 LT |
1719 | |
1720 | rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); | |
1721 | ||
1722 | snd_iprintf(buffer, rme96->card->longname); | |
1723 | snd_iprintf(buffer, " (index #%d)\n", rme96->card->number + 1); | |
1724 | ||
1725 | snd_iprintf(buffer, "\nGeneral settings\n"); | |
1726 | if (rme96->wcreg & RME96_WCR_IDIS) { | |
1727 | snd_iprintf(buffer, " period size: N/A (interrupts " | |
1728 | "disabled)\n"); | |
1729 | } else if (rme96->wcreg & RME96_WCR_ISEL) { | |
1730 | snd_iprintf(buffer, " period size: 2048 bytes\n"); | |
1731 | } else { | |
1732 | snd_iprintf(buffer, " period size: 8192 bytes\n"); | |
1733 | } | |
1734 | snd_iprintf(buffer, "\nInput settings\n"); | |
1735 | switch (snd_rme96_getinputtype(rme96)) { | |
1736 | case RME96_INPUT_OPTICAL: | |
1737 | snd_iprintf(buffer, " input: optical"); | |
1738 | break; | |
1739 | case RME96_INPUT_COAXIAL: | |
1740 | snd_iprintf(buffer, " input: coaxial"); | |
1741 | break; | |
1742 | case RME96_INPUT_INTERNAL: | |
1743 | snd_iprintf(buffer, " input: internal"); | |
1744 | break; | |
1745 | case RME96_INPUT_XLR: | |
1746 | snd_iprintf(buffer, " input: XLR"); | |
1747 | break; | |
1748 | case RME96_INPUT_ANALOG: | |
1749 | snd_iprintf(buffer, " input: analog"); | |
1750 | break; | |
1751 | } | |
1752 | if (snd_rme96_capture_getrate(rme96, &n) < 0) { | |
1753 | snd_iprintf(buffer, "\n sample rate: no valid signal\n"); | |
1754 | } else { | |
1755 | if (n) { | |
1756 | snd_iprintf(buffer, " (8 channels)\n"); | |
1757 | } else { | |
1758 | snd_iprintf(buffer, " (2 channels)\n"); | |
1759 | } | |
1760 | snd_iprintf(buffer, " sample rate: %d Hz\n", | |
1761 | snd_rme96_capture_getrate(rme96, &n)); | |
1762 | } | |
1763 | if (rme96->wcreg & RME96_WCR_MODE24_2) { | |
1764 | snd_iprintf(buffer, " sample format: 24 bit\n"); | |
1765 | } else { | |
1766 | snd_iprintf(buffer, " sample format: 16 bit\n"); | |
1767 | } | |
1768 | ||
1769 | snd_iprintf(buffer, "\nOutput settings\n"); | |
1770 | if (rme96->wcreg & RME96_WCR_SEL) { | |
1771 | snd_iprintf(buffer, " output signal: normal playback\n"); | |
1772 | } else { | |
1773 | snd_iprintf(buffer, " output signal: same as input\n"); | |
1774 | } | |
1775 | snd_iprintf(buffer, " sample rate: %d Hz\n", | |
1776 | snd_rme96_playback_getrate(rme96)); | |
1777 | if (rme96->wcreg & RME96_WCR_MODE24) { | |
1778 | snd_iprintf(buffer, " sample format: 24 bit\n"); | |
1779 | } else { | |
1780 | snd_iprintf(buffer, " sample format: 16 bit\n"); | |
1781 | } | |
1782 | if (rme96->areg & RME96_AR_WSEL) { | |
1783 | snd_iprintf(buffer, " sample clock source: word clock\n"); | |
1784 | } else if (rme96->wcreg & RME96_WCR_MASTER) { | |
1785 | snd_iprintf(buffer, " sample clock source: internal\n"); | |
1786 | } else if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) { | |
1787 | snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to analog input setting)\n"); | |
1788 | } else if (snd_rme96_capture_getrate(rme96, &n) < 0) { | |
1789 | snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to no valid signal)\n"); | |
1790 | } else { | |
1791 | snd_iprintf(buffer, " sample clock source: autosync\n"); | |
1792 | } | |
1793 | if (rme96->wcreg & RME96_WCR_PRO) { | |
1794 | snd_iprintf(buffer, " format: AES/EBU (professional)\n"); | |
1795 | } else { | |
1796 | snd_iprintf(buffer, " format: IEC958 (consumer)\n"); | |
1797 | } | |
1798 | if (rme96->wcreg & RME96_WCR_EMP) { | |
1799 | snd_iprintf(buffer, " emphasis: on\n"); | |
1800 | } else { | |
1801 | snd_iprintf(buffer, " emphasis: off\n"); | |
1802 | } | |
1803 | if (rme96->wcreg & RME96_WCR_DOLBY) { | |
1804 | snd_iprintf(buffer, " non-audio (dolby): on\n"); | |
1805 | } else { | |
1806 | snd_iprintf(buffer, " non-audio (dolby): off\n"); | |
1807 | } | |
1808 | if (RME96_HAS_ANALOG_IN(rme96)) { | |
1809 | snd_iprintf(buffer, "\nAnalog output settings\n"); | |
1810 | switch (snd_rme96_getmontracks(rme96)) { | |
1811 | case RME96_MONITOR_TRACKS_1_2: | |
1812 | snd_iprintf(buffer, " monitored ADAT tracks: 1+2\n"); | |
1813 | break; | |
1814 | case RME96_MONITOR_TRACKS_3_4: | |
1815 | snd_iprintf(buffer, " monitored ADAT tracks: 3+4\n"); | |
1816 | break; | |
1817 | case RME96_MONITOR_TRACKS_5_6: | |
1818 | snd_iprintf(buffer, " monitored ADAT tracks: 5+6\n"); | |
1819 | break; | |
1820 | case RME96_MONITOR_TRACKS_7_8: | |
1821 | snd_iprintf(buffer, " monitored ADAT tracks: 7+8\n"); | |
1822 | break; | |
1823 | } | |
1824 | switch (snd_rme96_getattenuation(rme96)) { | |
1825 | case RME96_ATTENUATION_0: | |
1826 | snd_iprintf(buffer, " attenuation: 0 dB\n"); | |
1827 | break; | |
1828 | case RME96_ATTENUATION_6: | |
1829 | snd_iprintf(buffer, " attenuation: -6 dB\n"); | |
1830 | break; | |
1831 | case RME96_ATTENUATION_12: | |
1832 | snd_iprintf(buffer, " attenuation: -12 dB\n"); | |
1833 | break; | |
1834 | case RME96_ATTENUATION_18: | |
1835 | snd_iprintf(buffer, " attenuation: -18 dB\n"); | |
1836 | break; | |
1837 | } | |
1838 | snd_iprintf(buffer, " volume left: %u\n", rme96->vol[0]); | |
1839 | snd_iprintf(buffer, " volume right: %u\n", rme96->vol[1]); | |
1840 | } | |
1841 | } | |
1842 | ||
e23e7a14 | 1843 | static void snd_rme96_proc_init(struct rme96 *rme96) |
1da177e4 | 1844 | { |
47f2769b | 1845 | snd_card_ro_proc_new(rme96->card, "rme96", rme96, snd_rme96_proc_read); |
1da177e4 LT |
1846 | } |
1847 | ||
1848 | /* | |
1849 | * control interface | |
1850 | */ | |
1851 | ||
a5ce8890 TI |
1852 | #define snd_rme96_info_loopback_control snd_ctl_boolean_mono_info |
1853 | ||
1da177e4 | 1854 | static int |
a3aefd88 | 1855 | snd_rme96_get_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1856 | { |
a3aefd88 | 1857 | struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1858 | |
1859 | spin_lock_irq(&rme96->lock); | |
1860 | ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1; | |
1861 | spin_unlock_irq(&rme96->lock); | |
1862 | return 0; | |
1863 | } | |
1864 | static int | |
a3aefd88 | 1865 | snd_rme96_put_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1866 | { |
a3aefd88 | 1867 | struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1868 | unsigned int val; |
1869 | int change; | |
1870 | ||
1871 | val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL; | |
1872 | spin_lock_irq(&rme96->lock); | |
1873 | val = (rme96->wcreg & ~RME96_WCR_SEL) | val; | |
1874 | change = val != rme96->wcreg; | |
1875 | rme96->wcreg = val; | |
1876 | writel(val, rme96->iobase + RME96_IO_CONTROL_REGISTER); | |
1877 | spin_unlock_irq(&rme96->lock); | |
1878 | return change; | |
1879 | } | |
1880 | ||
1881 | static int | |
a3aefd88 | 1882 | snd_rme96_info_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1da177e4 | 1883 | { |
9c30d46a TI |
1884 | static const char * const _texts[5] = { |
1885 | "Optical", "Coaxial", "Internal", "XLR", "Analog" | |
1886 | }; | |
a3aefd88 | 1887 | struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); |
9c30d46a TI |
1888 | const char *texts[5] = { |
1889 | _texts[0], _texts[1], _texts[2], _texts[3], _texts[4] | |
1890 | }; | |
1891 | int num_items; | |
1da177e4 | 1892 | |
1da177e4 | 1893 | switch (rme96->pci->device) { |
8b7fc421 RD |
1894 | case PCI_DEVICE_ID_RME_DIGI96: |
1895 | case PCI_DEVICE_ID_RME_DIGI96_8: | |
9c30d46a | 1896 | num_items = 3; |
1da177e4 | 1897 | break; |
8b7fc421 | 1898 | case PCI_DEVICE_ID_RME_DIGI96_8_PRO: |
9c30d46a | 1899 | num_items = 4; |
1da177e4 | 1900 | break; |
8b7fc421 | 1901 | case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST: |
1da177e4 LT |
1902 | if (rme96->rev > 4) { |
1903 | /* PST */ | |
9c30d46a | 1904 | num_items = 4; |
1da177e4 LT |
1905 | texts[3] = _texts[4]; /* Analog instead of XLR */ |
1906 | } else { | |
1907 | /* PAD */ | |
9c30d46a | 1908 | num_items = 5; |
1da177e4 LT |
1909 | } |
1910 | break; | |
1911 | default: | |
1912 | snd_BUG(); | |
9c30d46a | 1913 | return -EINVAL; |
1da177e4 | 1914 | } |
9c30d46a | 1915 | return snd_ctl_enum_info(uinfo, 1, num_items, texts); |
1da177e4 LT |
1916 | } |
1917 | static int | |
a3aefd88 | 1918 | snd_rme96_get_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1919 | { |
a3aefd88 | 1920 | struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1921 | unsigned int items = 3; |
1922 | ||
1923 | spin_lock_irq(&rme96->lock); | |
1924 | ucontrol->value.enumerated.item[0] = snd_rme96_getinputtype(rme96); | |
1925 | ||
1926 | switch (rme96->pci->device) { | |
8b7fc421 RD |
1927 | case PCI_DEVICE_ID_RME_DIGI96: |
1928 | case PCI_DEVICE_ID_RME_DIGI96_8: | |
1da177e4 LT |
1929 | items = 3; |
1930 | break; | |
8b7fc421 | 1931 | case PCI_DEVICE_ID_RME_DIGI96_8_PRO: |
1da177e4 LT |
1932 | items = 4; |
1933 | break; | |
8b7fc421 | 1934 | case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST: |
1da177e4 LT |
1935 | if (rme96->rev > 4) { |
1936 | /* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */ | |
1937 | if (ucontrol->value.enumerated.item[0] == RME96_INPUT_ANALOG) { | |
1938 | ucontrol->value.enumerated.item[0] = RME96_INPUT_XLR; | |
1939 | } | |
1940 | items = 4; | |
1941 | } else { | |
1942 | items = 5; | |
1943 | } | |
1944 | break; | |
1945 | default: | |
1946 | snd_BUG(); | |
1947 | break; | |
1948 | } | |
1949 | if (ucontrol->value.enumerated.item[0] >= items) { | |
1950 | ucontrol->value.enumerated.item[0] = items - 1; | |
1951 | } | |
1952 | ||
1953 | spin_unlock_irq(&rme96->lock); | |
1954 | return 0; | |
1955 | } | |
1956 | static int | |
a3aefd88 | 1957 | snd_rme96_put_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 1958 | { |
a3aefd88 | 1959 | struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
1960 | unsigned int val; |
1961 | int change, items = 3; | |
1962 | ||
1963 | switch (rme96->pci->device) { | |
8b7fc421 RD |
1964 | case PCI_DEVICE_ID_RME_DIGI96: |
1965 | case PCI_DEVICE_ID_RME_DIGI96_8: | |
1da177e4 LT |
1966 | items = 3; |
1967 | break; | |
8b7fc421 | 1968 | case PCI_DEVICE_ID_RME_DIGI96_8_PRO: |
1da177e4 LT |
1969 | items = 4; |
1970 | break; | |
8b7fc421 | 1971 | case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST: |
1da177e4 LT |
1972 | if (rme96->rev > 4) { |
1973 | items = 4; | |
1974 | } else { | |
1975 | items = 5; | |
1976 | } | |
1977 | break; | |
1978 | default: | |
1979 | snd_BUG(); | |
1980 | break; | |
1981 | } | |
1982 | val = ucontrol->value.enumerated.item[0] % items; | |
1983 | ||
1984 | /* special case for PST */ | |
8b7fc421 | 1985 | if (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && rme96->rev > 4) { |
1da177e4 LT |
1986 | if (val == RME96_INPUT_XLR) { |
1987 | val = RME96_INPUT_ANALOG; | |
1988 | } | |
1989 | } | |
1990 | ||
1991 | spin_lock_irq(&rme96->lock); | |
1992 | change = (int)val != snd_rme96_getinputtype(rme96); | |
1993 | snd_rme96_setinputtype(rme96, val); | |
1994 | spin_unlock_irq(&rme96->lock); | |
1995 | return change; | |
1996 | } | |
1997 | ||
1998 | static int | |
a3aefd88 | 1999 | snd_rme96_info_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1da177e4 | 2000 | { |
9c30d46a | 2001 | static const char * const texts[3] = { "AutoSync", "Internal", "Word" }; |
1da177e4 | 2002 | |
9c30d46a | 2003 | return snd_ctl_enum_info(uinfo, 1, 3, texts); |
1da177e4 LT |
2004 | } |
2005 | static int | |
a3aefd88 | 2006 | snd_rme96_get_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2007 | { |
a3aefd88 | 2008 | struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2009 | |
2010 | spin_lock_irq(&rme96->lock); | |
2011 | ucontrol->value.enumerated.item[0] = snd_rme96_getclockmode(rme96); | |
2012 | spin_unlock_irq(&rme96->lock); | |
2013 | return 0; | |
2014 | } | |
2015 | static int | |
a3aefd88 | 2016 | snd_rme96_put_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2017 | { |
a3aefd88 | 2018 | struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2019 | unsigned int val; |
2020 | int change; | |
2021 | ||
2022 | val = ucontrol->value.enumerated.item[0] % 3; | |
2023 | spin_lock_irq(&rme96->lock); | |
2024 | change = (int)val != snd_rme96_getclockmode(rme96); | |
2025 | snd_rme96_setclockmode(rme96, val); | |
2026 | spin_unlock_irq(&rme96->lock); | |
2027 | return change; | |
2028 | } | |
2029 | ||
2030 | static int | |
a3aefd88 | 2031 | snd_rme96_info_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1da177e4 | 2032 | { |
9c30d46a TI |
2033 | static const char * const texts[4] = { |
2034 | "0 dB", "-6 dB", "-12 dB", "-18 dB" | |
2035 | }; | |
1da177e4 | 2036 | |
9c30d46a | 2037 | return snd_ctl_enum_info(uinfo, 1, 4, texts); |
1da177e4 LT |
2038 | } |
2039 | static int | |
a3aefd88 | 2040 | snd_rme96_get_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2041 | { |
a3aefd88 | 2042 | struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2043 | |
2044 | spin_lock_irq(&rme96->lock); | |
2045 | ucontrol->value.enumerated.item[0] = snd_rme96_getattenuation(rme96); | |
2046 | spin_unlock_irq(&rme96->lock); | |
2047 | return 0; | |
2048 | } | |
2049 | static int | |
a3aefd88 | 2050 | snd_rme96_put_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2051 | { |
a3aefd88 | 2052 | struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2053 | unsigned int val; |
2054 | int change; | |
2055 | ||
2056 | val = ucontrol->value.enumerated.item[0] % 4; | |
2057 | spin_lock_irq(&rme96->lock); | |
2058 | ||
2059 | change = (int)val != snd_rme96_getattenuation(rme96); | |
2060 | snd_rme96_setattenuation(rme96, val); | |
2061 | spin_unlock_irq(&rme96->lock); | |
2062 | return change; | |
2063 | } | |
2064 | ||
2065 | static int | |
a3aefd88 | 2066 | snd_rme96_info_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1da177e4 | 2067 | { |
9c30d46a | 2068 | static const char * const texts[4] = { "1+2", "3+4", "5+6", "7+8" }; |
1da177e4 | 2069 | |
9c30d46a | 2070 | return snd_ctl_enum_info(uinfo, 1, 4, texts); |
1da177e4 LT |
2071 | } |
2072 | static int | |
a3aefd88 | 2073 | snd_rme96_get_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2074 | { |
a3aefd88 | 2075 | struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2076 | |
2077 | spin_lock_irq(&rme96->lock); | |
2078 | ucontrol->value.enumerated.item[0] = snd_rme96_getmontracks(rme96); | |
2079 | spin_unlock_irq(&rme96->lock); | |
2080 | return 0; | |
2081 | } | |
2082 | static int | |
a3aefd88 | 2083 | snd_rme96_put_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2084 | { |
a3aefd88 | 2085 | struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2086 | unsigned int val; |
2087 | int change; | |
2088 | ||
2089 | val = ucontrol->value.enumerated.item[0] % 4; | |
2090 | spin_lock_irq(&rme96->lock); | |
2091 | change = (int)val != snd_rme96_getmontracks(rme96); | |
2092 | snd_rme96_setmontracks(rme96, val); | |
2093 | spin_unlock_irq(&rme96->lock); | |
2094 | return change; | |
2095 | } | |
2096 | ||
a3aefd88 | 2097 | static u32 snd_rme96_convert_from_aes(struct snd_aes_iec958 *aes) |
1da177e4 LT |
2098 | { |
2099 | u32 val = 0; | |
2100 | val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME96_WCR_PRO : 0; | |
2101 | val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME96_WCR_DOLBY : 0; | |
2102 | if (val & RME96_WCR_PRO) | |
2103 | val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME96_WCR_EMP : 0; | |
2104 | else | |
2105 | val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME96_WCR_EMP : 0; | |
2106 | return val; | |
2107 | } | |
2108 | ||
a3aefd88 | 2109 | static void snd_rme96_convert_to_aes(struct snd_aes_iec958 *aes, u32 val) |
1da177e4 LT |
2110 | { |
2111 | aes->status[0] = ((val & RME96_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0) | | |
2112 | ((val & RME96_WCR_DOLBY) ? IEC958_AES0_NONAUDIO : 0); | |
2113 | if (val & RME96_WCR_PRO) | |
2114 | aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0; | |
2115 | else | |
2116 | aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0; | |
2117 | } | |
2118 | ||
a3aefd88 | 2119 | static int snd_rme96_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1da177e4 LT |
2120 | { |
2121 | uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; | |
2122 | uinfo->count = 1; | |
2123 | return 0; | |
2124 | } | |
2125 | ||
a3aefd88 | 2126 | static int snd_rme96_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2127 | { |
a3aefd88 | 2128 | struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2129 | |
2130 | snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif); | |
2131 | return 0; | |
2132 | } | |
2133 | ||
a3aefd88 | 2134 | static int snd_rme96_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2135 | { |
a3aefd88 | 2136 | struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2137 | int change; |
2138 | u32 val; | |
2139 | ||
2140 | val = snd_rme96_convert_from_aes(&ucontrol->value.iec958); | |
2141 | spin_lock_irq(&rme96->lock); | |
2142 | change = val != rme96->wcreg_spdif; | |
2143 | rme96->wcreg_spdif = val; | |
2144 | spin_unlock_irq(&rme96->lock); | |
2145 | return change; | |
2146 | } | |
2147 | ||
a3aefd88 | 2148 | static int snd_rme96_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1da177e4 LT |
2149 | { |
2150 | uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; | |
2151 | uinfo->count = 1; | |
2152 | return 0; | |
2153 | } | |
2154 | ||
a3aefd88 | 2155 | static int snd_rme96_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2156 | { |
a3aefd88 | 2157 | struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2158 | |
2159 | snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif_stream); | |
2160 | return 0; | |
2161 | } | |
2162 | ||
a3aefd88 | 2163 | static int snd_rme96_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 | 2164 | { |
a3aefd88 | 2165 | struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2166 | int change; |
2167 | u32 val; | |
2168 | ||
2169 | val = snd_rme96_convert_from_aes(&ucontrol->value.iec958); | |
2170 | spin_lock_irq(&rme96->lock); | |
2171 | change = val != rme96->wcreg_spdif_stream; | |
2172 | rme96->wcreg_spdif_stream = val; | |
2173 | rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP); | |
2174 | rme96->wcreg |= val; | |
2175 | writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); | |
2176 | spin_unlock_irq(&rme96->lock); | |
2177 | return change; | |
2178 | } | |
2179 | ||
a3aefd88 | 2180 | static int snd_rme96_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1da177e4 LT |
2181 | { |
2182 | uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; | |
2183 | uinfo->count = 1; | |
2184 | return 0; | |
2185 | } | |
2186 | ||
a3aefd88 | 2187 | static int snd_rme96_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1da177e4 LT |
2188 | { |
2189 | ucontrol->value.iec958.status[0] = kcontrol->private_value; | |
2190 | return 0; | |
2191 | } | |
2192 | ||
2193 | static int | |
a3aefd88 | 2194 | snd_rme96_dac_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1da177e4 | 2195 | { |
a3aefd88 | 2196 | struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2197 | |
2198 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; | |
2199 | uinfo->count = 2; | |
2200 | uinfo->value.integer.min = 0; | |
2201 | uinfo->value.integer.max = RME96_185X_MAX_OUT(rme96); | |
2202 | return 0; | |
2203 | } | |
2204 | ||
2205 | static int | |
a3aefd88 | 2206 | snd_rme96_dac_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u) |
1da177e4 | 2207 | { |
a3aefd88 | 2208 | struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); |
1da177e4 LT |
2209 | |
2210 | spin_lock_irq(&rme96->lock); | |
2211 | u->value.integer.value[0] = rme96->vol[0]; | |
2212 | u->value.integer.value[1] = rme96->vol[1]; | |
2213 | spin_unlock_irq(&rme96->lock); | |
2214 | ||
2215 | return 0; | |
2216 | } | |
2217 | ||
2218 | static int | |
a3aefd88 | 2219 | snd_rme96_dac_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u) |
1da177e4 | 2220 | { |
a3aefd88 | 2221 | struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); |
1da177e4 | 2222 | int change = 0; |
4e98d6a7 | 2223 | unsigned int vol, maxvol; |
1da177e4 | 2224 | |
4e98d6a7 TI |
2225 | |
2226 | if (!RME96_HAS_ANALOG_OUT(rme96)) | |
1da177e4 | 2227 | return -EINVAL; |
4e98d6a7 | 2228 | maxvol = RME96_185X_MAX_OUT(rme96); |
1da177e4 | 2229 | spin_lock_irq(&rme96->lock); |
4e98d6a7 TI |
2230 | vol = u->value.integer.value[0]; |
2231 | if (vol != rme96->vol[0] && vol <= maxvol) { | |
2232 | rme96->vol[0] = vol; | |
2233 | change = 1; | |
2234 | } | |
2235 | vol = u->value.integer.value[1]; | |
2236 | if (vol != rme96->vol[1] && vol <= maxvol) { | |
2237 | rme96->vol[1] = vol; | |
2238 | change = 1; | |
1da177e4 | 2239 | } |
4e98d6a7 TI |
2240 | if (change) |
2241 | snd_rme96_apply_dac_volume(rme96); | |
1da177e4 LT |
2242 | spin_unlock_irq(&rme96->lock); |
2243 | ||
2244 | return change; | |
2245 | } | |
2246 | ||
b4e5e707 | 2247 | static const struct snd_kcontrol_new snd_rme96_controls[] = { |
1da177e4 LT |
2248 | { |
2249 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, | |
2250 | .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), | |
2251 | .info = snd_rme96_control_spdif_info, | |
2252 | .get = snd_rme96_control_spdif_get, | |
2253 | .put = snd_rme96_control_spdif_put | |
2254 | }, | |
2255 | { | |
2256 | .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE, | |
2257 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, | |
2258 | .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), | |
2259 | .info = snd_rme96_control_spdif_stream_info, | |
2260 | .get = snd_rme96_control_spdif_stream_get, | |
2261 | .put = snd_rme96_control_spdif_stream_put | |
2262 | }, | |
2263 | { | |
2264 | .access = SNDRV_CTL_ELEM_ACCESS_READ, | |
67ed4161 | 2265 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, |
1da177e4 LT |
2266 | .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK), |
2267 | .info = snd_rme96_control_spdif_mask_info, | |
2268 | .get = snd_rme96_control_spdif_mask_get, | |
2269 | .private_value = IEC958_AES0_NONAUDIO | | |
2270 | IEC958_AES0_PROFESSIONAL | | |
2271 | IEC958_AES0_CON_EMPHASIS | |
2272 | }, | |
2273 | { | |
2274 | .access = SNDRV_CTL_ELEM_ACCESS_READ, | |
67ed4161 | 2275 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, |
1da177e4 LT |
2276 | .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK), |
2277 | .info = snd_rme96_control_spdif_mask_info, | |
2278 | .get = snd_rme96_control_spdif_mask_get, | |
2279 | .private_value = IEC958_AES0_NONAUDIO | | |
2280 | IEC958_AES0_PROFESSIONAL | | |
2281 | IEC958_AES0_PRO_EMPHASIS | |
2282 | }, | |
2283 | { | |
2284 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
2285 | .name = "Input Connector", | |
2286 | .info = snd_rme96_info_inputtype_control, | |
2287 | .get = snd_rme96_get_inputtype_control, | |
2288 | .put = snd_rme96_put_inputtype_control | |
2289 | }, | |
2290 | { | |
2291 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
2292 | .name = "Loopback Input", | |
2293 | .info = snd_rme96_info_loopback_control, | |
2294 | .get = snd_rme96_get_loopback_control, | |
2295 | .put = snd_rme96_put_loopback_control | |
2296 | }, | |
2297 | { | |
2298 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
2299 | .name = "Sample Clock Source", | |
2300 | .info = snd_rme96_info_clockmode_control, | |
2301 | .get = snd_rme96_get_clockmode_control, | |
2302 | .put = snd_rme96_put_clockmode_control | |
2303 | }, | |
2304 | { | |
2305 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
2306 | .name = "Monitor Tracks", | |
2307 | .info = snd_rme96_info_montracks_control, | |
2308 | .get = snd_rme96_get_montracks_control, | |
2309 | .put = snd_rme96_put_montracks_control | |
2310 | }, | |
2311 | { | |
2312 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
2313 | .name = "Attenuation", | |
2314 | .info = snd_rme96_info_attenuation_control, | |
2315 | .get = snd_rme96_get_attenuation_control, | |
2316 | .put = snd_rme96_put_attenuation_control | |
2317 | }, | |
2318 | { | |
2319 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
2320 | .name = "DAC Playback Volume", | |
2321 | .info = snd_rme96_dac_volume_info, | |
2322 | .get = snd_rme96_dac_volume_get, | |
2323 | .put = snd_rme96_dac_volume_put | |
2324 | } | |
2325 | }; | |
2326 | ||
2327 | static int | |
a3aefd88 TI |
2328 | snd_rme96_create_switches(struct snd_card *card, |
2329 | struct rme96 *rme96) | |
1da177e4 LT |
2330 | { |
2331 | int idx, err; | |
a3aefd88 | 2332 | struct snd_kcontrol *kctl; |
1da177e4 LT |
2333 | |
2334 | for (idx = 0; idx < 7; idx++) { | |
da8eedb1 TI |
2335 | kctl = snd_ctl_new1(&snd_rme96_controls[idx], rme96); |
2336 | err = snd_ctl_add(card, kctl); | |
2337 | if (err < 0) | |
1da177e4 LT |
2338 | return err; |
2339 | if (idx == 1) /* IEC958 (S/PDIF) Stream */ | |
2340 | rme96->spdif_ctl = kctl; | |
2341 | } | |
2342 | ||
2343 | if (RME96_HAS_ANALOG_OUT(rme96)) { | |
da8eedb1 TI |
2344 | for (idx = 7; idx < 10; idx++) { |
2345 | err = snd_ctl_add(card, snd_ctl_new1(&snd_rme96_controls[idx], rme96)); | |
2346 | if (err < 0) | |
1da177e4 | 2347 | return err; |
da8eedb1 | 2348 | } |
1da177e4 LT |
2349 | } |
2350 | ||
2351 | return 0; | |
2352 | } | |
2353 | ||
2354 | /* | |
2355 | * Card initialisation | |
2356 | */ | |
2357 | ||
a932be91 | 2358 | #ifdef CONFIG_PM_SLEEP |
528ba522 | 2359 | |
a932be91 | 2360 | static int rme96_suspend(struct device *dev) |
528ba522 | 2361 | { |
a932be91 | 2362 | struct snd_card *card = dev_get_drvdata(dev); |
528ba522 KP |
2363 | struct rme96 *rme96 = card->private_data; |
2364 | ||
2365 | snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); | |
528ba522 KP |
2366 | |
2367 | /* save capture & playback pointers */ | |
2368 | rme96->playback_pointer = readl(rme96->iobase + RME96_IO_GET_PLAY_POS) | |
2369 | & RME96_RCR_AUDIO_ADDR_MASK; | |
2370 | rme96->capture_pointer = readl(rme96->iobase + RME96_IO_GET_REC_POS) | |
2371 | & RME96_RCR_AUDIO_ADDR_MASK; | |
2372 | ||
2373 | /* save playback and capture buffers */ | |
2374 | memcpy_fromio(rme96->playback_suspend_buffer, | |
2375 | rme96->iobase + RME96_IO_PLAY_BUFFER, RME96_BUFFER_SIZE); | |
2376 | memcpy_fromio(rme96->capture_suspend_buffer, | |
2377 | rme96->iobase + RME96_IO_REC_BUFFER, RME96_BUFFER_SIZE); | |
2378 | ||
2379 | /* disable the DAC */ | |
2380 | rme96->areg &= ~RME96_AR_DAC_EN; | |
2381 | writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); | |
528ba522 KP |
2382 | return 0; |
2383 | } | |
2384 | ||
a932be91 | 2385 | static int rme96_resume(struct device *dev) |
528ba522 | 2386 | { |
a932be91 | 2387 | struct snd_card *card = dev_get_drvdata(dev); |
528ba522 KP |
2388 | struct rme96 *rme96 = card->private_data; |
2389 | ||
528ba522 KP |
2390 | /* reset playback and record buffer pointers */ |
2391 | writel(0, rme96->iobase + RME96_IO_SET_PLAY_POS | |
2392 | + rme96->playback_pointer); | |
2393 | writel(0, rme96->iobase + RME96_IO_SET_REC_POS | |
2394 | + rme96->capture_pointer); | |
2395 | ||
2396 | /* restore playback and capture buffers */ | |
2397 | memcpy_toio(rme96->iobase + RME96_IO_PLAY_BUFFER, | |
2398 | rme96->playback_suspend_buffer, RME96_BUFFER_SIZE); | |
2399 | memcpy_toio(rme96->iobase + RME96_IO_REC_BUFFER, | |
2400 | rme96->capture_suspend_buffer, RME96_BUFFER_SIZE); | |
2401 | ||
2402 | /* reset the ADC */ | |
2403 | writel(rme96->areg | RME96_AR_PD2, | |
2404 | rme96->iobase + RME96_IO_ADDITIONAL_REG); | |
2405 | writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); | |
2406 | ||
2407 | /* reset and enable DAC, restore analog volume */ | |
2408 | snd_rme96_reset_dac(rme96); | |
2409 | rme96->areg |= RME96_AR_DAC_EN; | |
2410 | writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); | |
2411 | if (RME96_HAS_ANALOG_OUT(rme96)) { | |
2412 | usleep_range(3000, 10000); | |
2413 | snd_rme96_apply_dac_volume(rme96); | |
2414 | } | |
2415 | ||
2416 | snd_power_change_state(card, SNDRV_CTL_POWER_D0); | |
2417 | ||
2418 | return 0; | |
2419 | } | |
2420 | ||
a932be91 TI |
2421 | static SIMPLE_DEV_PM_OPS(rme96_pm, rme96_suspend, rme96_resume); |
2422 | #define RME96_PM_OPS &rme96_pm | |
2423 | #else | |
2424 | #define RME96_PM_OPS NULL | |
2425 | #endif /* CONFIG_PM_SLEEP */ | |
528ba522 | 2426 | |
a3aefd88 | 2427 | static void snd_rme96_card_free(struct snd_card *card) |
1da177e4 LT |
2428 | { |
2429 | snd_rme96_free(card->private_data); | |
2430 | } | |
2431 | ||
e23e7a14 | 2432 | static int |
93b884f8 TI |
2433 | __snd_rme96_probe(struct pci_dev *pci, |
2434 | const struct pci_device_id *pci_id) | |
1da177e4 LT |
2435 | { |
2436 | static int dev; | |
a3aefd88 TI |
2437 | struct rme96 *rme96; |
2438 | struct snd_card *card; | |
1da177e4 LT |
2439 | int err; |
2440 | u8 val; | |
2441 | ||
2442 | if (dev >= SNDRV_CARDS) { | |
2443 | return -ENODEV; | |
2444 | } | |
2445 | if (!enable[dev]) { | |
2446 | dev++; | |
2447 | return -ENOENT; | |
2448 | } | |
df06df7c TI |
2449 | err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, |
2450 | sizeof(*rme96), &card); | |
e58de7ba TI |
2451 | if (err < 0) |
2452 | return err; | |
1da177e4 | 2453 | card->private_free = snd_rme96_card_free; |
9fe856e4 | 2454 | rme96 = card->private_data; |
1da177e4 LT |
2455 | rme96->card = card; |
2456 | rme96->pci = pci; | |
d72a8010 ME |
2457 | err = snd_rme96_create(rme96); |
2458 | if (err) | |
df06df7c | 2459 | return err; |
1da177e4 | 2460 | |
a932be91 | 2461 | #ifdef CONFIG_PM_SLEEP |
528ba522 | 2462 | rme96->playback_suspend_buffer = vmalloc(RME96_BUFFER_SIZE); |
df06df7c TI |
2463 | if (!rme96->playback_suspend_buffer) |
2464 | return -ENOMEM; | |
528ba522 | 2465 | rme96->capture_suspend_buffer = vmalloc(RME96_BUFFER_SIZE); |
df06df7c TI |
2466 | if (!rme96->capture_suspend_buffer) |
2467 | return -ENOMEM; | |
528ba522 KP |
2468 | #endif |
2469 | ||
1da177e4 LT |
2470 | strcpy(card->driver, "Digi96"); |
2471 | switch (rme96->pci->device) { | |
8b7fc421 | 2472 | case PCI_DEVICE_ID_RME_DIGI96: |
1da177e4 LT |
2473 | strcpy(card->shortname, "RME Digi96"); |
2474 | break; | |
8b7fc421 | 2475 | case PCI_DEVICE_ID_RME_DIGI96_8: |
1da177e4 LT |
2476 | strcpy(card->shortname, "RME Digi96/8"); |
2477 | break; | |
8b7fc421 | 2478 | case PCI_DEVICE_ID_RME_DIGI96_8_PRO: |
1da177e4 LT |
2479 | strcpy(card->shortname, "RME Digi96/8 PRO"); |
2480 | break; | |
8b7fc421 | 2481 | case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST: |
1da177e4 LT |
2482 | pci_read_config_byte(rme96->pci, 8, &val); |
2483 | if (val < 5) { | |
2484 | strcpy(card->shortname, "RME Digi96/8 PAD"); | |
2485 | } else { | |
2486 | strcpy(card->shortname, "RME Digi96/8 PST"); | |
2487 | } | |
2488 | break; | |
2489 | } | |
2490 | sprintf(card->longname, "%s at 0x%lx, irq %d", card->shortname, | |
2491 | rme96->port, rme96->irq); | |
d72a8010 ME |
2492 | err = snd_card_register(card); |
2493 | if (err) | |
df06df7c | 2494 | return err; |
d72a8010 | 2495 | |
1da177e4 LT |
2496 | pci_set_drvdata(pci, card); |
2497 | dev++; | |
2498 | return 0; | |
1da177e4 LT |
2499 | } |
2500 | ||
93b884f8 TI |
2501 | static int snd_rme96_probe(struct pci_dev *pci, |
2502 | const struct pci_device_id *pci_id) | |
2503 | { | |
2504 | return snd_card_free_on_error(&pci->dev, __snd_rme96_probe(pci, pci_id)); | |
2505 | } | |
2506 | ||
e9f66d9b | 2507 | static struct pci_driver rme96_driver = { |
3733e424 | 2508 | .name = KBUILD_MODNAME, |
1da177e4 LT |
2509 | .id_table = snd_rme96_ids, |
2510 | .probe = snd_rme96_probe, | |
a932be91 TI |
2511 | .driver = { |
2512 | .pm = RME96_PM_OPS, | |
2513 | }, | |
1da177e4 LT |
2514 | }; |
2515 | ||
e9f66d9b | 2516 | module_pci_driver(rme96_driver); |