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ALSA: rme32: Remove superfluous snd_dma_continuous_data()
[linux-2.6-block.git] / sound / pci / rme32.c
CommitLineData
74ba9207 1// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4
LT		 2/*
3 * ALSA driver for RME Digi32, Digi32/8 and Digi32 PRO audio interfaces
4 *
5 * Copyright (c) 2002-2004 Martin Langer <martin-langer@gmx.de>,
6 * Pilo Chambert <pilo.c@wanadoo.fr>
7 *
8 * Thanks to : Anders Torger <torger@ludd.luth.se>,
9 * Henk Hesselink <henk@anda.nl>
10 * for writing the digi96-driver
11 * and RME for all informations.
1da177e4
LT		 12 *
13 * ****************************************************************************
14 *
15 * Note #1 "Sek'd models" ................................... martin 2002-12-07
16 *
17 * Identical soundcards by Sek'd were labeled:
18 * RME Digi 32 = Sek'd Prodif 32
19 * RME Digi 32 Pro = Sek'd Prodif 96
20 * RME Digi 32/8 = Sek'd Prodif Gold
21 *
22 * ****************************************************************************
23 *
24 * Note #2 "full duplex mode" ............................... martin 2002-12-07
25 *
26 * Full duplex doesn't work. All cards (32, 32/8, 32Pro) are working identical
27 * in this mode. Rec data and play data are using the same buffer therefore. At
28 * first you have got the playing bits in the buffer and then (after playing
29 * them) they were overwitten by the captured sound of the CS8412/14. Both
30 * modes (play/record) are running harmonically hand in hand in the same buffer
31 * and you have only one start bit plus one interrupt bit to control this
32 * paired action.
33 * This is opposite to the latter rme96 where playing and capturing is totally
34 * separated and so their full duplex mode is supported by alsa (using two
35 * start bits and two interrupts for two different buffers).
36 * But due to the wrong sequence of playing and capturing ALSA shows no solved
37 * full duplex support for the rme32 at the moment. That's bad, but I'm not
38 * able to solve it. Are you motivated enough to solve this problem now? Your
39 * patch would be welcome!
40 *
41 * ****************************************************************************
42 *
43 * "The story after the long seeking" -- tiwai
44 *
45 * Ok, the situation regarding the full duplex is now improved a bit.
46 * In the fullduplex mode (given by the module parameter), the hardware buffer
47 * is split to halves for read and write directions at the DMA pointer.
48 * That is, the half above the current DMA pointer is used for write, and
49 * the half below is used for read. To mangle this strange behavior, an
50 * software intermediate buffer is introduced. This is, of course, not good
51 * from the viewpoint of the data transfer efficiency. However, this allows
52 * you to use arbitrary buffer sizes, instead of the fixed I/O buffer size.
53 *
54 * ****************************************************************************
55 */
56
57
1da177e4 58#include <linux/delay.h>
5a0e3ad6 59#include <linux/gfp.h>
1da177e4
LT		 60#include <linux/init.h>
61#include <linux/interrupt.h>
62#include <linux/pci.h>
65a77217 63#include <linux/module.h>
6cbbfe1c 64#include <linux/io.h>
1da177e4
LT		 65
66#include <sound/core.h>
67#include <sound/info.h>
68#include <sound/control.h>
69#include <sound/pcm.h>
70#include <sound/pcm_params.h>
71#include <sound/pcm-indirect.h>
72#include <sound/asoundef.h>
73#include <sound/initval.h>
74
1da177e4
LT		 75static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
76static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
a67ff6a5
RR		 77static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
78static bool fullduplex[SNDRV_CARDS]; // = {[0 ... (SNDRV_CARDS - 1)] = 1};
1da177e4
LT		 79
80module_param_array(index, int, NULL, 0444);
81MODULE_PARM_DESC(index, "Index value for RME Digi32 soundcard.");
82module_param_array(id, charp, NULL, 0444);
83MODULE_PARM_DESC(id, "ID string for RME Digi32 soundcard.");
84module_param_array(enable, bool, NULL, 0444);
85MODULE_PARM_DESC(enable, "Enable RME Digi32 soundcard.");
86module_param_array(fullduplex, bool, NULL, 0444);
87MODULE_PARM_DESC(fullduplex, "Support full-duplex mode.");
88MODULE_AUTHOR("Martin Langer <martin-langer@gmx.de>, Pilo Chambert <pilo.c@wanadoo.fr>");
89MODULE_DESCRIPTION("RME Digi32, Digi32/8, Digi32 PRO");
90MODULE_LICENSE("GPL");
91MODULE_SUPPORTED_DEVICE("{{RME,Digi32}," "{RME,Digi32/8}," "{RME,Digi32 PRO}}");
92
93/* Defines for RME Digi32 series */
94#define RME32_SPDIF_NCHANNELS 2
95
96/* Playback and capture buffer size */
97#define RME32_BUFFER_SIZE 0x20000
98
99/* IO area size */
100#define RME32_IO_SIZE 0x30000
101
102/* IO area offsets */
103#define RME32_IO_DATA_BUFFER 0x0
104#define RME32_IO_CONTROL_REGISTER 0x20000
105#define RME32_IO_GET_POS 0x20000
106#define RME32_IO_CONFIRM_ACTION_IRQ 0x20004
107#define RME32_IO_RESET_POS 0x20100
108
109/* Write control register bits */
110#define RME32_WCR_START (1 << 0) /* startbit */
111#define RME32_WCR_MONO (1 << 1) /* 0=stereo, 1=mono
112 Setting the whole card to mono
113 doesn't seem to be very useful.
114 A software-solution can handle
115 full-duplex with one direction in
116 stereo and the other way in mono.
117 So, the hardware should work all
118 the time in stereo! */
119#define RME32_WCR_MODE24 (1 << 2) /* 0=16bit, 1=32bit */
120#define RME32_WCR_SEL (1 << 3) /* 0=input on output, 1=normal playback/capture */
121#define RME32_WCR_FREQ_0 (1 << 4) /* frequency (play) */
122#define RME32_WCR_FREQ_1 (1 << 5)
123#define RME32_WCR_INP_0 (1 << 6) /* input switch */
124#define RME32_WCR_INP_1 (1 << 7)
125#define RME32_WCR_RESET (1 << 8) /* Reset address */
126#define RME32_WCR_MUTE (1 << 9) /* digital mute for output */
127#define RME32_WCR_PRO (1 << 10) /* 1=professional, 0=consumer */
128#define RME32_WCR_DS_BM (1 << 11) /* 1=DoubleSpeed (only PRO-Version); 1=BlockMode (only Adat-Version) */
129#define RME32_WCR_ADAT (1 << 12) /* Adat Mode (only Adat-Version) */
130#define RME32_WCR_AUTOSYNC (1 << 13) /* AutoSync */
131#define RME32_WCR_PD (1 << 14) /* DAC Reset (only PRO-Version) */
132#define RME32_WCR_EMP (1 << 15) /* 1=Emphasis on (only PRO-Version) */
133
134#define RME32_WCR_BITPOS_FREQ_0 4
135#define RME32_WCR_BITPOS_FREQ_1 5
136#define RME32_WCR_BITPOS_INP_0 6
137#define RME32_WCR_BITPOS_INP_1 7
138
139/* Read control register bits */
140#define RME32_RCR_AUDIO_ADDR_MASK 0x1ffff
141#define RME32_RCR_LOCK (1 << 23) /* 1=locked, 0=not locked */
142#define RME32_RCR_ERF (1 << 26) /* 1=Error, 0=no Error */
143#define RME32_RCR_FREQ_0 (1 << 27) /* CS841x frequency (record) */
144#define RME32_RCR_FREQ_1 (1 << 28)
145#define RME32_RCR_FREQ_2 (1 << 29)
146#define RME32_RCR_KMODE (1 << 30) /* card mode: 1=PLL, 0=quartz */
147#define RME32_RCR_IRQ (1 << 31) /* interrupt */
148
149#define RME32_RCR_BITPOS_F0 27
150#define RME32_RCR_BITPOS_F1 28
151#define RME32_RCR_BITPOS_F2 29
152
153/* Input types */
154#define RME32_INPUT_OPTICAL 0
155#define RME32_INPUT_COAXIAL 1
156#define RME32_INPUT_INTERNAL 2
157#define RME32_INPUT_XLR 3
158
159/* Clock modes */
160#define RME32_CLOCKMODE_SLAVE 0
161#define RME32_CLOCKMODE_MASTER_32 1
162#define RME32_CLOCKMODE_MASTER_44 2
163#define RME32_CLOCKMODE_MASTER_48 3
164
165/* Block sizes in bytes */
166#define RME32_BLOCK_SIZE 8192
167
168/* Software intermediate buffer (max) size */
169#define RME32_MID_BUFFER_SIZE (1024*1024)
170
171/* Hardware revisions */
172#define RME32_32_REVISION 192
173#define RME32_328_REVISION_OLD 100
174#define RME32_328_REVISION_NEW 101
175#define RME32_PRO_REVISION_WITH_8412 192
176#define RME32_PRO_REVISION_WITH_8414 150
177
178
017ce802 179struct rme32 {
1da177e4
LT		 180 spinlock_t lock;
181 int irq;
182 unsigned long port;
183 void __iomem *iobase;
184
185 u32 wcreg; /* cached write control register value */
186 u32 wcreg_spdif; /* S/PDIF setup */
187 u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */
188 u32 rcreg; /* cached read control register value */
189
190 u8 rev; /* card revision number */
191
017ce802
TI		 192 struct snd_pcm_substream *playback_substream;
193 struct snd_pcm_substream *capture_substream;
1da177e4
LT		 194
195 int playback_frlog; /* log2 of framesize */
196 int capture_frlog;
197
198 size_t playback_periodsize; /* in bytes, zero if not used */
199 size_t capture_periodsize; /* in bytes, zero if not used */
200
201 unsigned int fullduplex_mode;
202 int running;
203
017ce802
TI		 204 struct snd_pcm_indirect playback_pcm;
205 struct snd_pcm_indirect capture_pcm;
1da177e4 206
017ce802
TI		 207 struct snd_card *card;
208 struct snd_pcm *spdif_pcm;
209 struct snd_pcm *adat_pcm;
1da177e4 210 struct pci_dev *pci;
017ce802
TI		 211 struct snd_kcontrol *spdif_ctl;
212};
1da177e4 213
9baa3c34 214static const struct pci_device_id snd_rme32_ids[] = {
28d27aae
JP		 215 {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32), 0,},
216 {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_8), 0,},
217 {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_PRO), 0,},
1da177e4
LT		 218 {0,}
219};
220
221MODULE_DEVICE_TABLE(pci, snd_rme32_ids);
222
223#define RME32_ISWORKING(rme32) ((rme32)->wcreg & RME32_WCR_START)
8b7fc421 224#define RME32_PRO_WITH_8414(rme32) ((rme32)->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO && (rme32)->rev == RME32_PRO_REVISION_WITH_8414)
1da177e4 225
017ce802 226static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream);
1da177e4 227
017ce802 228static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream);
1da177e4 229
017ce802 230static int snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd);
1da177e4 231
017ce802 232static void snd_rme32_proc_init(struct rme32 * rme32);
1da177e4 233
017ce802 234static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32);
1da177e4 235
017ce802 236static inline unsigned int snd_rme32_pcm_byteptr(struct rme32 * rme32)
1da177e4
LT		 237{
238 return (readl(rme32->iobase + RME32_IO_GET_POS)
239 & RME32_RCR_AUDIO_ADDR_MASK);
240}
241
1da177e4 242/* silence callback for halfduplex mode */
032db751
TI		 243static int snd_rme32_playback_silence(struct snd_pcm_substream *substream,
244 int channel, unsigned long pos,
245 unsigned long count)
1da177e4 246{
017ce802 247 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
032db751 248
1da177e4
LT		 249 memset_io(rme32->iobase + RME32_IO_DATA_BUFFER + pos, 0, count);
250 return 0;
251}
252
253/* copy callback for halfduplex mode */
032db751
TI		 254static int snd_rme32_playback_copy(struct snd_pcm_substream *substream,
255 int channel, unsigned long pos,
256 void __user *src, unsigned long count)
1da177e4 257{
017ce802 258 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
032db751 259
1da177e4 260 if (copy_from_user_toio(rme32->iobase + RME32_IO_DATA_BUFFER + pos,
032db751 261 src, count))
1da177e4
LT		 262 return -EFAULT;
263 return 0;
264}
265
032db751
TI		 266static int snd_rme32_playback_copy_kernel(struct snd_pcm_substream *substream,
267 int channel, unsigned long pos,
268 void *src, unsigned long count)
269{
270 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
271
272 memcpy_toio(rme32->iobase + RME32_IO_DATA_BUFFER + pos, src, count);
273 return 0;
274}
275
1da177e4 276/* copy callback for halfduplex mode */
032db751
TI		 277static int snd_rme32_capture_copy(struct snd_pcm_substream *substream,
278 int channel, unsigned long pos,
279 void __user *dst, unsigned long count)
1da177e4 280{
017ce802 281 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
032db751 282
1da177e4
LT		 283 if (copy_to_user_fromio(dst,
284 rme32->iobase + RME32_IO_DATA_BUFFER + pos,
285 count))
286 return -EFAULT;
287 return 0;
288}
289
032db751
TI		 290static int snd_rme32_capture_copy_kernel(struct snd_pcm_substream *substream,
291 int channel, unsigned long pos,
292 void *dst, unsigned long count)
293{
294 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
295
296 memcpy_fromio(dst, rme32->iobase + RME32_IO_DATA_BUFFER + pos, count);
297 return 0;
298}
299
1da177e4 300/*
7f927fcc 301 * SPDIF I/O capabilities (half-duplex mode)
1da177e4 302 */
dee49895 303static const struct snd_pcm_hardware snd_rme32_spdif_info = {
1da177e4
LT		 304 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
305 SNDRV_PCM_INFO_MMAP_VALID |
306 SNDRV_PCM_INFO_INTERLEAVED |
307 SNDRV_PCM_INFO_PAUSE |
38ce57ad
TI		 308 SNDRV_PCM_INFO_SYNC_START |
309 SNDRV_PCM_INFO_SYNC_APPLPTR),
1da177e4
LT		 310 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
311 SNDRV_PCM_FMTBIT_S32_LE),
312 .rates = (SNDRV_PCM_RATE_32000 |
313 SNDRV_PCM_RATE_44100 |
314 SNDRV_PCM_RATE_48000),
315 .rate_min = 32000,
316 .rate_max = 48000,
317 .channels_min = 2,
318 .channels_max = 2,
319 .buffer_bytes_max = RME32_BUFFER_SIZE,
320 .period_bytes_min = RME32_BLOCK_SIZE,
321 .period_bytes_max = RME32_BLOCK_SIZE,
322 .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
323 .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
324 .fifo_size = 0,
325};
326
327/*
7f927fcc 328 * ADAT I/O capabilities (half-duplex mode)
1da177e4 329 */
dee49895 330static const struct snd_pcm_hardware snd_rme32_adat_info =
1da177e4
LT		 331{
332 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
333 SNDRV_PCM_INFO_MMAP_VALID |
334 SNDRV_PCM_INFO_INTERLEAVED |
335 SNDRV_PCM_INFO_PAUSE |
38ce57ad
TI		 336 SNDRV_PCM_INFO_SYNC_START |
337 SNDRV_PCM_INFO_SYNC_APPLPTR),
1da177e4
LT		 338 .formats= SNDRV_PCM_FMTBIT_S16_LE,
339 .rates = (SNDRV_PCM_RATE_44100 |
340 SNDRV_PCM_RATE_48000),
341 .rate_min = 44100,
342 .rate_max = 48000,
343 .channels_min = 8,
344 .channels_max = 8,
345 .buffer_bytes_max = RME32_BUFFER_SIZE,
346 .period_bytes_min = RME32_BLOCK_SIZE,
347 .period_bytes_max = RME32_BLOCK_SIZE,
348 .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
349 .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
350 .fifo_size = 0,
351};
352
353/*
7f927fcc 354 * SPDIF I/O capabilities (full-duplex mode)
1da177e4 355 */
dee49895 356static const struct snd_pcm_hardware snd_rme32_spdif_fd_info = {
1da177e4
LT		 357 .info = (SNDRV_PCM_INFO_MMAP |
358 SNDRV_PCM_INFO_MMAP_VALID |
359 SNDRV_PCM_INFO_INTERLEAVED |
360 SNDRV_PCM_INFO_PAUSE |
38ce57ad
TI		 361 SNDRV_PCM_INFO_SYNC_START |
362 SNDRV_PCM_INFO_SYNC_APPLPTR),
1da177e4
LT		 363 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
364 SNDRV_PCM_FMTBIT_S32_LE),
365 .rates = (SNDRV_PCM_RATE_32000 |
366 SNDRV_PCM_RATE_44100 |
367 SNDRV_PCM_RATE_48000),
368 .rate_min = 32000,
369 .rate_max = 48000,
370 .channels_min = 2,
371 .channels_max = 2,
372 .buffer_bytes_max = RME32_MID_BUFFER_SIZE,
373 .period_bytes_min = RME32_BLOCK_SIZE,
374 .period_bytes_max = RME32_BLOCK_SIZE,
375 .periods_min = 2,
376 .periods_max = RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE,
377 .fifo_size = 0,
378};
379
380/*
7f927fcc 381 * ADAT I/O capabilities (full-duplex mode)
1da177e4 382 */
dee49895 383static const struct snd_pcm_hardware snd_rme32_adat_fd_info =
1da177e4
LT		 384{
385 .info = (SNDRV_PCM_INFO_MMAP |
386 SNDRV_PCM_INFO_MMAP_VALID |
387 SNDRV_PCM_INFO_INTERLEAVED |
388 SNDRV_PCM_INFO_PAUSE |
38ce57ad
TI		 389 SNDRV_PCM_INFO_SYNC_START |
390 SNDRV_PCM_INFO_SYNC_APPLPTR),
1da177e4
LT		 391 .formats= SNDRV_PCM_FMTBIT_S16_LE,
392 .rates = (SNDRV_PCM_RATE_44100 |
393 SNDRV_PCM_RATE_48000),
394 .rate_min = 44100,
395 .rate_max = 48000,
396 .channels_min = 8,
397 .channels_max = 8,
398 .buffer_bytes_max = RME32_MID_BUFFER_SIZE,
399 .period_bytes_min = RME32_BLOCK_SIZE,
400 .period_bytes_max = RME32_BLOCK_SIZE,
401 .periods_min = 2,
402 .periods_max = RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE,
403 .fifo_size = 0,
404};
405
017ce802 406static void snd_rme32_reset_dac(struct rme32 *rme32)
1da177e4
LT		 407{
408 writel(rme32->wcreg | RME32_WCR_PD,
409 rme32->iobase + RME32_IO_CONTROL_REGISTER);
410 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
411}
412
017ce802 413static int snd_rme32_playback_getrate(struct rme32 * rme32)
1da177e4
LT		 414{
415 int rate;
416
417 rate = ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) +
418 (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1);
419 switch (rate) {
420 case 1:
421 rate = 32000;
422 break;
423 case 2:
424 rate = 44100;
425 break;
426 case 3:
427 rate = 48000;
428 break;
429 default:
430 return -1;
431 }
432 return (rme32->wcreg & RME32_WCR_DS_BM) ? rate << 1 : rate;
433}
434
017ce802 435static int snd_rme32_capture_getrate(struct rme32 * rme32, int *is_adat)
1da177e4
LT		 436{
437 int n;
438
439 *is_adat = 0;
440 if (rme32->rcreg & RME32_RCR_LOCK) {
441 /* ADAT rate */
442 *is_adat = 1;
443 }
444 if (rme32->rcreg & RME32_RCR_ERF) {
445 return -1;
446 }
447
448 /* S/PDIF rate */
449 n = ((rme32->rcreg >> RME32_RCR_BITPOS_F0) & 1) +
450 (((rme32->rcreg >> RME32_RCR_BITPOS_F1) & 1) << 1) +
451 (((rme32->rcreg >> RME32_RCR_BITPOS_F2) & 1) << 2);
452
453 if (RME32_PRO_WITH_8414(rme32))
454 switch (n) { /* supporting the CS8414 */
455 case 0:
456 case 1:
457 case 2:
458 return -1;
459 case 3:
460 return 96000;
461 case 4:
462 return 88200;
463 case 5:
464 return 48000;
465 case 6:
466 return 44100;
467 case 7:
468 return 32000;
469 default:
470 return -1;
471 break;
472 }
473 else
474 switch (n) { /* supporting the CS8412 */
475 case 0:
476 return -1;
477 case 1:
478 return 48000;
479 case 2:
480 return 44100;
481 case 3:
482 return 32000;
483 case 4:
484 return 48000;
485 case 5:
486 return 44100;
487 case 6:
488 return 44056;
489 case 7:
490 return 32000;
491 default:
492 break;
493 }
494 return -1;
495}
496
017ce802 497static int snd_rme32_playback_setrate(struct rme32 * rme32, int rate)
1da177e4
LT		 498{
499 int ds;
500
501 ds = rme32->wcreg & RME32_WCR_DS_BM;
502 switch (rate) {
503 case 32000:
504 rme32->wcreg &= ~RME32_WCR_DS_BM;
505 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
506 ~RME32_WCR_FREQ_1;
507 break;
508 case 44100:
509 rme32->wcreg &= ~RME32_WCR_DS_BM;
510 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) &
511 ~RME32_WCR_FREQ_0;
512 break;
513 case 48000:
514 rme32->wcreg &= ~RME32_WCR_DS_BM;
515 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
516 RME32_WCR_FREQ_1;
517 break;
518 case 64000:
8b7fc421 519 if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
1da177e4
LT		 520 return -EINVAL;
521 rme32->wcreg |= RME32_WCR_DS_BM;
522 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
523 ~RME32_WCR_FREQ_1;
524 break;
525 case 88200:
8b7fc421 526 if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
1da177e4
LT		 527 return -EINVAL;
528 rme32->wcreg |= RME32_WCR_DS_BM;
529 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) &
530 ~RME32_WCR_FREQ_0;
531 break;
532 case 96000:
8b7fc421 533 if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
1da177e4
LT		 534 return -EINVAL;
535 rme32->wcreg |= RME32_WCR_DS_BM;
536 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
537 RME32_WCR_FREQ_1;
538 break;
539 default:
540 return -EINVAL;
541 }
542 if ((!ds && rme32->wcreg & RME32_WCR_DS_BM) ||
543 (ds && !(rme32->wcreg & RME32_WCR_DS_BM)))
544 {
545 /* change to/from double-speed: reset the DAC (if available) */
546 snd_rme32_reset_dac(rme32);
547 } else {
548 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
549 }
550 return 0;
551}
552
017ce802 553static int snd_rme32_setclockmode(struct rme32 * rme32, int mode)
1da177e4
LT		 554{
555 switch (mode) {
556 case RME32_CLOCKMODE_SLAVE:
557 /* AutoSync */
558 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) &
559 ~RME32_WCR_FREQ_1;
560 break;
561 case RME32_CLOCKMODE_MASTER_32:
562 /* Internal 32.0kHz */
563 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
564 ~RME32_WCR_FREQ_1;
565 break;
566 case RME32_CLOCKMODE_MASTER_44:
567 /* Internal 44.1kHz */
568 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) |
569 RME32_WCR_FREQ_1;
570 break;
571 case RME32_CLOCKMODE_MASTER_48:
572 /* Internal 48.0kHz */
573 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
574 RME32_WCR_FREQ_1;
575 break;
576 default:
577 return -EINVAL;
578 }
579 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
580 return 0;
581}
582
017ce802 583static int snd_rme32_getclockmode(struct rme32 * rme32)
1da177e4
LT		 584{
585 return ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) +
586 (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1);
587}
588
017ce802 589static int snd_rme32_setinputtype(struct rme32 * rme32, int type)
1da177e4
LT		 590{
591 switch (type) {
592 case RME32_INPUT_OPTICAL:
593 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) &
594 ~RME32_WCR_INP_1;
595 break;
596 case RME32_INPUT_COAXIAL:
597 rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) &
598 ~RME32_WCR_INP_1;
599 break;
600 case RME32_INPUT_INTERNAL:
601 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) |
602 RME32_WCR_INP_1;
603 break;
604 case RME32_INPUT_XLR:
605 rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) |
606 RME32_WCR_INP_1;
607 break;
608 default:
609 return -EINVAL;
610 }
611 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
612 return 0;
613}
614
017ce802 615static int snd_rme32_getinputtype(struct rme32 * rme32)
1da177e4
LT		 616{
617 return ((rme32->wcreg >> RME32_WCR_BITPOS_INP_0) & 1) +
618 (((rme32->wcreg >> RME32_WCR_BITPOS_INP_1) & 1) << 1);
619}
620
621static void
017ce802 622snd_rme32_setframelog(struct rme32 * rme32, int n_channels, int is_playback)
1da177e4
LT		 623{
624 int frlog;
625
626 if (n_channels == 2) {
627 frlog = 1;
628 } else {
629 /* assume 8 channels */
630 frlog = 3;
631 }
632 if (is_playback) {
633 frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1;
634 rme32->playback_frlog = frlog;
635 } else {
636 frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1;
637 rme32->capture_frlog = frlog;
638 }
639}
640
6c869d30 641static int snd_rme32_setformat(struct rme32 *rme32, snd_pcm_format_t format)
1da177e4
LT		 642{
643 switch (format) {
644 case SNDRV_PCM_FORMAT_S16_LE:
645 rme32->wcreg &= ~RME32_WCR_MODE24;
646 break;
647 case SNDRV_PCM_FORMAT_S32_LE:
648 rme32->wcreg |= RME32_WCR_MODE24;
649 break;
650 default:
651 return -EINVAL;
652 }
653 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
654 return 0;
655}
656
657static int
017ce802
TI		 658snd_rme32_playback_hw_params(struct snd_pcm_substream *substream,
659 struct snd_pcm_hw_params *params)
1da177e4
LT		 660{
661 int err, rate, dummy;
017ce802
TI		 662 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
663 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 664
665 if (rme32->fullduplex_mode) {
666 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
667 if (err < 0)
668 return err;
669 } else {
4d23359b
CL		 670 runtime->dma_area = (void __force *)(rme32->iobase +
671 RME32_IO_DATA_BUFFER);
1da177e4
LT		 672 runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER;
673 runtime->dma_bytes = RME32_BUFFER_SIZE;
674 }
675
676 spin_lock_irq(&rme32->lock);
677 if ((rme32->rcreg & RME32_RCR_KMODE) &&
678 (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
679 /* AutoSync */
680 if ((int)params_rate(params) != rate) {
681 spin_unlock_irq(&rme32->lock);
682 return -EIO;
683 }
684 } else if ((err = snd_rme32_playback_setrate(rme32, params_rate(params))) < 0) {
685 spin_unlock_irq(&rme32->lock);
686 return err;
687 }
688 if ((err = snd_rme32_setformat(rme32, params_format(params))) < 0) {
689 spin_unlock_irq(&rme32->lock);
690 return err;
691 }
692
693 snd_rme32_setframelog(rme32, params_channels(params), 1);
694 if (rme32->capture_periodsize != 0) {
695 if (params_period_size(params) << rme32->playback_frlog != rme32->capture_periodsize) {
696 spin_unlock_irq(&rme32->lock);
697 return -EBUSY;
698 }
699 }
700 rme32->playback_periodsize = params_period_size(params) << rme32->playback_frlog;
701 /* S/PDIF setup */
702 if ((rme32->wcreg & RME32_WCR_ADAT) == 0) {
703 rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP);
704 rme32->wcreg |= rme32->wcreg_spdif_stream;
705 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
706 }
707 spin_unlock_irq(&rme32->lock);
708
709 return 0;
710}
711
712static int
017ce802
TI		 713snd_rme32_capture_hw_params(struct snd_pcm_substream *substream,
714 struct snd_pcm_hw_params *params)
1da177e4
LT		 715{
716 int err, isadat, rate;
017ce802
TI		 717 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
718 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 719
720 if (rme32->fullduplex_mode) {
721 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
722 if (err < 0)
723 return err;
724 } else {
4d23359b
CL		 725 runtime->dma_area = (void __force *)rme32->iobase +
726 RME32_IO_DATA_BUFFER;
1da177e4
LT		 727 runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER;
728 runtime->dma_bytes = RME32_BUFFER_SIZE;
729 }
730
731 spin_lock_irq(&rme32->lock);
732 /* enable AutoSync for record-preparing */
733 rme32->wcreg |= RME32_WCR_AUTOSYNC;
734 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
735
736 if ((err = snd_rme32_setformat(rme32, params_format(params))) < 0) {
737 spin_unlock_irq(&rme32->lock);
738 return err;
739 }
740 if ((err = snd_rme32_playback_setrate(rme32, params_rate(params))) < 0) {
741 spin_unlock_irq(&rme32->lock);
742 return err;
743 }
744 if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
745 if ((int)params_rate(params) != rate) {
746 spin_unlock_irq(&rme32->lock);
747 return -EIO;
748 }
749 if ((isadat && runtime->hw.channels_min == 2) ||
750 (!isadat && runtime->hw.channels_min == 8)) {
751 spin_unlock_irq(&rme32->lock);
752 return -EIO;
753 }
754 }
755 /* AutoSync off for recording */
756 rme32->wcreg &= ~RME32_WCR_AUTOSYNC;
757 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
758
759 snd_rme32_setframelog(rme32, params_channels(params), 0);
760 if (rme32->playback_periodsize != 0) {
761 if (params_period_size(params) << rme32->capture_frlog !=
762 rme32->playback_periodsize) {
763 spin_unlock_irq(&rme32->lock);
764 return -EBUSY;
765 }
766 }
767 rme32->capture_periodsize =
768 params_period_size(params) << rme32->capture_frlog;
769 spin_unlock_irq(&rme32->lock);
770
771 return 0;
772}
773
017ce802 774static int snd_rme32_pcm_hw_free(struct snd_pcm_substream *substream)
1da177e4 775{
017ce802 776 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1da177e4
LT		 777 if (! rme32->fullduplex_mode)
778 return 0;
779 return snd_pcm_lib_free_pages(substream);
780}
781
017ce802 782static void snd_rme32_pcm_start(struct rme32 * rme32, int from_pause)
1da177e4
LT		 783{
784 if (!from_pause) {
785 writel(0, rme32->iobase + RME32_IO_RESET_POS);
786 }
787
788 rme32->wcreg |= RME32_WCR_START;
789 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
790}
791
017ce802 792static void snd_rme32_pcm_stop(struct rme32 * rme32, int to_pause)
1da177e4
LT		 793{
794 /*
795 * Check if there is an unconfirmed IRQ, if so confirm it, or else
796 * the hardware will not stop generating interrupts
797 */
798 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
799 if (rme32->rcreg & RME32_RCR_IRQ) {
800 writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ);
801 }
802 rme32->wcreg &= ~RME32_WCR_START;
803 if (rme32->wcreg & RME32_WCR_SEL)
804 rme32->wcreg |= RME32_WCR_MUTE;
805 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
806 if (! to_pause)
807 writel(0, rme32->iobase + RME32_IO_RESET_POS);
808}
809
7d12e780 810static irqreturn_t snd_rme32_interrupt(int irq, void *dev_id)
1da177e4 811{
017ce802 812 struct rme32 *rme32 = (struct rme32 *) dev_id;
1da177e4
LT		 813
814 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
815 if (!(rme32->rcreg & RME32_RCR_IRQ)) {
816 return IRQ_NONE;
817 } else {
818 if (rme32->capture_substream) {
819 snd_pcm_period_elapsed(rme32->capture_substream);
820 }
821 if (rme32->playback_substream) {
822 snd_pcm_period_elapsed(rme32->playback_substream);
823 }
824 writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ);
825 }
826 return IRQ_HANDLED;
827}
828
a7f8009d 829static const unsigned int period_bytes[] = { RME32_BLOCK_SIZE };
1da177e4 830
a7f8009d 831static const struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = {
1da177e4
LT		 832 .count = ARRAY_SIZE(period_bytes),
833 .list = period_bytes,
834 .mask = 0
835};
836
017ce802 837static void snd_rme32_set_buffer_constraint(struct rme32 *rme32, struct snd_pcm_runtime *runtime)
1da177e4
LT		 838{
839 if (! rme32->fullduplex_mode) {
80ec8893 840 snd_pcm_hw_constraint_single(runtime,
1da177e4 841 SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
80ec8893 842 RME32_BUFFER_SIZE);
1da177e4
LT		 843 snd_pcm_hw_constraint_list(runtime, 0,
844 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
845 &hw_constraints_period_bytes);
846 }
847}
848
017ce802 849static int snd_rme32_playback_spdif_open(struct snd_pcm_substream *substream)
1da177e4
LT		 850{
851 int rate, dummy;
017ce802
TI		 852 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
853 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 854
855 snd_pcm_set_sync(substream);
856
857 spin_lock_irq(&rme32->lock);
858 if (rme32->playback_substream != NULL) {
859 spin_unlock_irq(&rme32->lock);
860 return -EBUSY;
861 }
862 rme32->wcreg &= ~RME32_WCR_ADAT;
863 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
864 rme32->playback_substream = substream;
865 spin_unlock_irq(&rme32->lock);
866
867 if (rme32->fullduplex_mode)
868 runtime->hw = snd_rme32_spdif_fd_info;
869 else
870 runtime->hw = snd_rme32_spdif_info;
8b7fc421 871 if (rme32->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO) {
1da177e4
LT		 872 runtime->hw.rates |= SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000;
873 runtime->hw.rate_max = 96000;
874 }
875 if ((rme32->rcreg & RME32_RCR_KMODE) &&
876 (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
877 /* AutoSync */
918f3a0e 878 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1da177e4
LT		 879 runtime->hw.rate_min = rate;
880 runtime->hw.rate_max = rate;
881 }
882
883 snd_rme32_set_buffer_constraint(rme32, runtime);
884
885 rme32->wcreg_spdif_stream = rme32->wcreg_spdif;
886 rme32->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
887 snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE |
888 SNDRV_CTL_EVENT_MASK_INFO, &rme32->spdif_ctl->id);
889 return 0;
890}
891
017ce802 892static int snd_rme32_capture_spdif_open(struct snd_pcm_substream *substream)
1da177e4
LT		 893{
894 int isadat, rate;
017ce802
TI		 895 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
896 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 897
898 snd_pcm_set_sync(substream);
899
900 spin_lock_irq(&rme32->lock);
901 if (rme32->capture_substream != NULL) {
902 spin_unlock_irq(&rme32->lock);
903 return -EBUSY;
904 }
905 rme32->capture_substream = substream;
906 spin_unlock_irq(&rme32->lock);
907
908 if (rme32->fullduplex_mode)
909 runtime->hw = snd_rme32_spdif_fd_info;
910 else
911 runtime->hw = snd_rme32_spdif_info;
912 if (RME32_PRO_WITH_8414(rme32)) {
913 runtime->hw.rates |= SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000;
914 runtime->hw.rate_max = 96000;
915 }
916 if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
917 if (isadat) {
918 return -EIO;
919 }
918f3a0e 920 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1da177e4
LT		 921 runtime->hw.rate_min = rate;
922 runtime->hw.rate_max = rate;
923 }
924
925 snd_rme32_set_buffer_constraint(rme32, runtime);
926
927 return 0;
928}
929
930static int
017ce802 931snd_rme32_playback_adat_open(struct snd_pcm_substream *substream)
1da177e4
LT		 932{
933 int rate, dummy;
017ce802
TI		 934 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
935 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 936
937 snd_pcm_set_sync(substream);
938
939 spin_lock_irq(&rme32->lock);
940 if (rme32->playback_substream != NULL) {
941 spin_unlock_irq(&rme32->lock);
942 return -EBUSY;
943 }
944 rme32->wcreg |= RME32_WCR_ADAT;
945 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
946 rme32->playback_substream = substream;
947 spin_unlock_irq(&rme32->lock);
948
949 if (rme32->fullduplex_mode)
950 runtime->hw = snd_rme32_adat_fd_info;
951 else
952 runtime->hw = snd_rme32_adat_info;
953 if ((rme32->rcreg & RME32_RCR_KMODE) &&
954 (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
955 /* AutoSync */
918f3a0e 956 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1da177e4
LT		 957 runtime->hw.rate_min = rate;
958 runtime->hw.rate_max = rate;
959 }
960
961 snd_rme32_set_buffer_constraint(rme32, runtime);
962 return 0;
963}
964
965static int
017ce802 966snd_rme32_capture_adat_open(struct snd_pcm_substream *substream)
1da177e4
LT		 967{
968 int isadat, rate;
017ce802
TI		 969 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
970 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 971
972 if (rme32->fullduplex_mode)
973 runtime->hw = snd_rme32_adat_fd_info;
974 else
975 runtime->hw = snd_rme32_adat_info;
976 if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
977 if (!isadat) {
978 return -EIO;
979 }
918f3a0e 980 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1da177e4
LT		 981 runtime->hw.rate_min = rate;
982 runtime->hw.rate_max = rate;
983 }
984
985 snd_pcm_set_sync(substream);
986
987 spin_lock_irq(&rme32->lock);
988 if (rme32->capture_substream != NULL) {
989 spin_unlock_irq(&rme32->lock);
990 return -EBUSY;
991 }
992 rme32->capture_substream = substream;
993 spin_unlock_irq(&rme32->lock);
994
995 snd_rme32_set_buffer_constraint(rme32, runtime);
996 return 0;
997}
998
017ce802 999static int snd_rme32_playback_close(struct snd_pcm_substream *substream)
1da177e4 1000{
017ce802 1001 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1002 int spdif = 0;
1003
1004 spin_lock_irq(&rme32->lock);
1005 rme32->playback_substream = NULL;
1006 rme32->playback_periodsize = 0;
1007 spdif = (rme32->wcreg & RME32_WCR_ADAT) == 0;
1008 spin_unlock_irq(&rme32->lock);
1009 if (spdif) {
1010 rme32->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1011 snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE |
1012 SNDRV_CTL_EVENT_MASK_INFO,
1013 &rme32->spdif_ctl->id);
1014 }
1015 return 0;
1016}
1017
017ce802 1018static int snd_rme32_capture_close(struct snd_pcm_substream *substream)
1da177e4 1019{
017ce802 1020 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1021
1022 spin_lock_irq(&rme32->lock);
1023 rme32->capture_substream = NULL;
1024 rme32->capture_periodsize = 0;
f49a59c4 1025 spin_unlock_irq(&rme32->lock);
1da177e4
LT		 1026 return 0;
1027}
1028
017ce802 1029static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream)
1da177e4 1030{
017ce802 1031 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1032
1033 spin_lock_irq(&rme32->lock);
1034 if (rme32->fullduplex_mode) {
1035 memset(&rme32->playback_pcm, 0, sizeof(rme32->playback_pcm));
1036 rme32->playback_pcm.hw_buffer_size = RME32_BUFFER_SIZE;
1037 rme32->playback_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1038 } else {
1039 writel(0, rme32->iobase + RME32_IO_RESET_POS);
1040 }
1041 if (rme32->wcreg & RME32_WCR_SEL)
1042 rme32->wcreg &= ~RME32_WCR_MUTE;
1043 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1044 spin_unlock_irq(&rme32->lock);
1045 return 0;
1046}
1047
017ce802 1048static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream)
1da177e4 1049{
017ce802 1050 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1051
1052 spin_lock_irq(&rme32->lock);
1053 if (rme32->fullduplex_mode) {
1054 memset(&rme32->capture_pcm, 0, sizeof(rme32->capture_pcm));
1055 rme32->capture_pcm.hw_buffer_size = RME32_BUFFER_SIZE;
1056 rme32->capture_pcm.hw_queue_size = RME32_BUFFER_SIZE / 2;
1057 rme32->capture_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1058 } else {
1059 writel(0, rme32->iobase + RME32_IO_RESET_POS);
1060 }
1061 spin_unlock_irq(&rme32->lock);
1062 return 0;
1063}
1064
1065static int
017ce802 1066snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4 1067{
017ce802 1068 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
017ce802 1069 struct snd_pcm_substream *s;
1da177e4
LT		 1070
1071 spin_lock(&rme32->lock);
ef991b95 1072 snd_pcm_group_for_each_entry(s, substream) {
1da177e4
LT		 1073 if (s != rme32->playback_substream &&
1074 s != rme32->capture_substream)
1075 continue;
1076 switch (cmd) {
1077 case SNDRV_PCM_TRIGGER_START:
1078 rme32->running |= (1 << s->stream);
1079 if (rme32->fullduplex_mode) {
1080 /* remember the current DMA position */
1081 if (s == rme32->playback_substream) {
1082 rme32->playback_pcm.hw_io =
1083 rme32->playback_pcm.hw_data = snd_rme32_pcm_byteptr(rme32);
1084 } else {
1085 rme32->capture_pcm.hw_io =
1086 rme32->capture_pcm.hw_data = snd_rme32_pcm_byteptr(rme32);
1087 }
1088 }
1089 break;
1090 case SNDRV_PCM_TRIGGER_STOP:
1091 rme32->running &= ~(1 << s->stream);
1092 break;
1093 }
1094 snd_pcm_trigger_done(s, substream);
1095 }
1096
1da177e4
LT		 1097 switch (cmd) {
1098 case SNDRV_PCM_TRIGGER_START:
1099 if (rme32->running && ! RME32_ISWORKING(rme32))
1100 snd_rme32_pcm_start(rme32, 0);
1101 break;
1102 case SNDRV_PCM_TRIGGER_STOP:
1103 if (! rme32->running && RME32_ISWORKING(rme32))
1104 snd_rme32_pcm_stop(rme32, 0);
1105 break;
1106 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1107 if (rme32->running && RME32_ISWORKING(rme32))
1108 snd_rme32_pcm_stop(rme32, 1);
1109 break;
1110 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1111 if (rme32->running && ! RME32_ISWORKING(rme32))
1112 snd_rme32_pcm_start(rme32, 1);
1113 break;
1114 }
1115 spin_unlock(&rme32->lock);
1116 return 0;
1117}
1118
1119/* pointer callback for halfduplex mode */
1120static snd_pcm_uframes_t
017ce802 1121snd_rme32_playback_pointer(struct snd_pcm_substream *substream)
1da177e4 1122{
017ce802 1123 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1124 return snd_rme32_pcm_byteptr(rme32) >> rme32->playback_frlog;
1125}
1126
1127static snd_pcm_uframes_t
017ce802 1128snd_rme32_capture_pointer(struct snd_pcm_substream *substream)
1da177e4 1129{
017ce802 1130 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1131 return snd_rme32_pcm_byteptr(rme32) >> rme32->capture_frlog;
1132}
1133
1134
1135/* ack and pointer callbacks for fullduplex mode */
017ce802
TI		 1136static void snd_rme32_pb_trans_copy(struct snd_pcm_substream *substream,
1137 struct snd_pcm_indirect *rec, size_t bytes)
1da177e4 1138{
017ce802 1139 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1140 memcpy_toio(rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data,
1141 substream->runtime->dma_area + rec->sw_data, bytes);
1142}
1143
017ce802 1144static int snd_rme32_playback_fd_ack(struct snd_pcm_substream *substream)
1da177e4 1145{
017ce802
TI		 1146 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1147 struct snd_pcm_indirect *rec, *cprec;
1da177e4
LT		 1148
1149 rec = &rme32->playback_pcm;
1150 cprec = &rme32->capture_pcm;
1151 spin_lock(&rme32->lock);
1152 rec->hw_queue_size = RME32_BUFFER_SIZE;
1153 if (rme32->running & (1 << SNDRV_PCM_STREAM_CAPTURE))
1154 rec->hw_queue_size -= cprec->hw_ready;
1155 spin_unlock(&rme32->lock);
3e02c5a6
TI		 1156 return snd_pcm_indirect_playback_transfer(substream, rec,
1157 snd_rme32_pb_trans_copy);
1da177e4
LT		 1158}
1159
017ce802
TI		 1160static void snd_rme32_cp_trans_copy(struct snd_pcm_substream *substream,
1161 struct snd_pcm_indirect *rec, size_t bytes)
1da177e4 1162{
017ce802 1163 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1164 memcpy_fromio(substream->runtime->dma_area + rec->sw_data,
1165 rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data,
1166 bytes);
1167}
1168
017ce802 1169static int snd_rme32_capture_fd_ack(struct snd_pcm_substream *substream)
1da177e4 1170{
017ce802 1171 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
3e02c5a6
TI		 1172 return snd_pcm_indirect_capture_transfer(substream, &rme32->capture_pcm,
1173 snd_rme32_cp_trans_copy);
1da177e4
LT		 1174}
1175
1176static snd_pcm_uframes_t
017ce802 1177snd_rme32_playback_fd_pointer(struct snd_pcm_substream *substream)
1da177e4 1178{
017ce802 1179 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1180 return snd_pcm_indirect_playback_pointer(substream, &rme32->playback_pcm,
1181 snd_rme32_pcm_byteptr(rme32));
1182}
1183
1184static snd_pcm_uframes_t
017ce802 1185snd_rme32_capture_fd_pointer(struct snd_pcm_substream *substream)
1da177e4 1186{
017ce802 1187 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1188 return snd_pcm_indirect_capture_pointer(substream, &rme32->capture_pcm,
1189 snd_rme32_pcm_byteptr(rme32));
1190}
1191
1192/* for halfduplex mode */
6769e988 1193static const struct snd_pcm_ops snd_rme32_playback_spdif_ops = {
1da177e4
LT		 1194 .open = snd_rme32_playback_spdif_open,
1195 .close = snd_rme32_playback_close,
1196 .ioctl = snd_pcm_lib_ioctl,
1197 .hw_params = snd_rme32_playback_hw_params,
1198 .hw_free = snd_rme32_pcm_hw_free,
1199 .prepare = snd_rme32_playback_prepare,
1200 .trigger = snd_rme32_pcm_trigger,
1201 .pointer = snd_rme32_playback_pointer,
032db751
TI		 1202 .copy_user = snd_rme32_playback_copy,
1203 .copy_kernel = snd_rme32_playback_copy_kernel,
1204 .fill_silence = snd_rme32_playback_silence,
1da177e4
LT		 1205 .mmap = snd_pcm_lib_mmap_iomem,
1206};
1207
6769e988 1208static const struct snd_pcm_ops snd_rme32_capture_spdif_ops = {
1da177e4
LT		 1209 .open = snd_rme32_capture_spdif_open,
1210 .close = snd_rme32_capture_close,
1211 .ioctl = snd_pcm_lib_ioctl,
1212 .hw_params = snd_rme32_capture_hw_params,
1213 .hw_free = snd_rme32_pcm_hw_free,
1214 .prepare = snd_rme32_capture_prepare,
1215 .trigger = snd_rme32_pcm_trigger,
1216 .pointer = snd_rme32_capture_pointer,
032db751
TI		 1217 .copy_user = snd_rme32_capture_copy,
1218 .copy_kernel = snd_rme32_capture_copy_kernel,
1da177e4
LT		 1219 .mmap = snd_pcm_lib_mmap_iomem,
1220};
1221
6769e988 1222static const struct snd_pcm_ops snd_rme32_playback_adat_ops = {
1da177e4
LT		 1223 .open = snd_rme32_playback_adat_open,
1224 .close = snd_rme32_playback_close,
1225 .ioctl = snd_pcm_lib_ioctl,
1226 .hw_params = snd_rme32_playback_hw_params,
1227 .prepare = snd_rme32_playback_prepare,
1228 .trigger = snd_rme32_pcm_trigger,
1229 .pointer = snd_rme32_playback_pointer,
032db751
TI		 1230 .copy_user = snd_rme32_playback_copy,
1231 .copy_kernel = snd_rme32_playback_copy_kernel,
1232 .fill_silence = snd_rme32_playback_silence,
1da177e4
LT		 1233 .mmap = snd_pcm_lib_mmap_iomem,
1234};
1235
6769e988 1236static const struct snd_pcm_ops snd_rme32_capture_adat_ops = {
1da177e4
LT		 1237 .open = snd_rme32_capture_adat_open,
1238 .close = snd_rme32_capture_close,
1239 .ioctl = snd_pcm_lib_ioctl,
1240 .hw_params = snd_rme32_capture_hw_params,
1241 .prepare = snd_rme32_capture_prepare,
1242 .trigger = snd_rme32_pcm_trigger,
1243 .pointer = snd_rme32_capture_pointer,
032db751
TI		 1244 .copy_user = snd_rme32_capture_copy,
1245 .copy_kernel = snd_rme32_capture_copy_kernel,
1da177e4
LT		 1246 .mmap = snd_pcm_lib_mmap_iomem,
1247};
1248
1249/* for fullduplex mode */
6769e988 1250static const struct snd_pcm_ops snd_rme32_playback_spdif_fd_ops = {
1da177e4
LT		 1251 .open = snd_rme32_playback_spdif_open,
1252 .close = snd_rme32_playback_close,
1253 .ioctl = snd_pcm_lib_ioctl,
1254 .hw_params = snd_rme32_playback_hw_params,
1255 .hw_free = snd_rme32_pcm_hw_free,
1256 .prepare = snd_rme32_playback_prepare,
1257 .trigger = snd_rme32_pcm_trigger,
1258 .pointer = snd_rme32_playback_fd_pointer,
1259 .ack = snd_rme32_playback_fd_ack,
1260};
1261
6769e988 1262static const struct snd_pcm_ops snd_rme32_capture_spdif_fd_ops = {
1da177e4
LT		 1263 .open = snd_rme32_capture_spdif_open,
1264 .close = snd_rme32_capture_close,
1265 .ioctl = snd_pcm_lib_ioctl,
1266 .hw_params = snd_rme32_capture_hw_params,
1267 .hw_free = snd_rme32_pcm_hw_free,
1268 .prepare = snd_rme32_capture_prepare,
1269 .trigger = snd_rme32_pcm_trigger,
1270 .pointer = snd_rme32_capture_fd_pointer,
1271 .ack = snd_rme32_capture_fd_ack,
1272};
1273
6769e988 1274static const struct snd_pcm_ops snd_rme32_playback_adat_fd_ops = {
1da177e4
LT		 1275 .open = snd_rme32_playback_adat_open,
1276 .close = snd_rme32_playback_close,
1277 .ioctl = snd_pcm_lib_ioctl,
1278 .hw_params = snd_rme32_playback_hw_params,
1279 .prepare = snd_rme32_playback_prepare,
1280 .trigger = snd_rme32_pcm_trigger,
1281 .pointer = snd_rme32_playback_fd_pointer,
1282 .ack = snd_rme32_playback_fd_ack,
1283};
1284
6769e988 1285static const struct snd_pcm_ops snd_rme32_capture_adat_fd_ops = {
1da177e4
LT		 1286 .open = snd_rme32_capture_adat_open,
1287 .close = snd_rme32_capture_close,
1288 .ioctl = snd_pcm_lib_ioctl,
1289 .hw_params = snd_rme32_capture_hw_params,
1290 .prepare = snd_rme32_capture_prepare,
1291 .trigger = snd_rme32_pcm_trigger,
1292 .pointer = snd_rme32_capture_fd_pointer,
1293 .ack = snd_rme32_capture_fd_ack,
1294};
1295
1296static void snd_rme32_free(void *private_data)
1297{
017ce802 1298 struct rme32 *rme32 = (struct rme32 *) private_data;
1da177e4
LT		 1299
1300 if (rme32 == NULL) {
1301 return;
1302 }
1303 if (rme32->irq >= 0) {
1304 snd_rme32_pcm_stop(rme32, 0);
1305 free_irq(rme32->irq, (void *) rme32);
1306 rme32->irq = -1;
1307 }
1308 if (rme32->iobase) {
1309 iounmap(rme32->iobase);
1310 rme32->iobase = NULL;
1311 }
1312 if (rme32->port) {
1313 pci_release_regions(rme32->pci);
1314 rme32->port = 0;
1315 }
1316 pci_disable_device(rme32->pci);
1317}
1318
017ce802 1319static void snd_rme32_free_spdif_pcm(struct snd_pcm *pcm)
1da177e4 1320{
017ce802 1321 struct rme32 *rme32 = (struct rme32 *) pcm->private_data;
1da177e4
LT		 1322 rme32->spdif_pcm = NULL;
1323}
1324
1325static void
017ce802 1326snd_rme32_free_adat_pcm(struct snd_pcm *pcm)
1da177e4 1327{
017ce802 1328 struct rme32 *rme32 = (struct rme32 *) pcm->private_data;
1da177e4
LT		 1329 rme32->adat_pcm = NULL;
1330}
1331
e23e7a14 1332static int snd_rme32_create(struct rme32 *rme32)
1da177e4
LT		 1333{
1334 struct pci_dev *pci = rme32->pci;
1335 int err;
1336
1337 rme32->irq = -1;
1338 spin_lock_init(&rme32->lock);
1339
1340 if ((err = pci_enable_device(pci)) < 0)
1341 return err;
1342
1343 if ((err = pci_request_regions(pci, "RME32")) < 0)
1344 return err;
1345 rme32->port = pci_resource_start(rme32->pci, 0);
1346
4db9e4f2
HH		 1347 rme32->iobase = ioremap_nocache(rme32->port, RME32_IO_SIZE);
1348 if (!rme32->iobase) {
03952a3e
TI		 1349 dev_err(rme32->card->dev,
1350 "unable to remap memory region 0x%lx-0x%lx\n",
1da177e4
LT		 1351 rme32->port, rme32->port + RME32_IO_SIZE - 1);
1352 return -ENOMEM;
1353 }
1354
437a5a46 1355 if (request_irq(pci->irq, snd_rme32_interrupt, IRQF_SHARED,
934c2b6d 1356 KBUILD_MODNAME, rme32)) {
03952a3e 1357 dev_err(rme32->card->dev, "unable to grab IRQ %d\n", pci->irq);
688956f2
TI		 1358 return -EBUSY;
1359 }
1360 rme32->irq = pci->irq;
1361
1da177e4
LT		 1362 /* read the card's revision number */
1363 pci_read_config_byte(pci, 8, &rme32->rev);
1364
1365 /* set up ALSA pcm device for S/PDIF */
1366 if ((err = snd_pcm_new(rme32->card, "Digi32 IEC958", 0, 1, 1, &rme32->spdif_pcm)) < 0) {
1367 return err;
1368 }
1369 rme32->spdif_pcm->private_data = rme32;
1370 rme32->spdif_pcm->private_free = snd_rme32_free_spdif_pcm;
1371 strcpy(rme32->spdif_pcm->name, "Digi32 IEC958");
1372 if (rme32->fullduplex_mode) {
1373 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1374 &snd_rme32_playback_spdif_fd_ops);
1375 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE,
1376 &snd_rme32_capture_spdif_fd_ops);
1377 snd_pcm_lib_preallocate_pages_for_all(rme32->spdif_pcm, SNDRV_DMA_TYPE_CONTINUOUS,
1422bc50 1378 NULL,
1da177e4
LT		 1379 0, RME32_MID_BUFFER_SIZE);
1380 rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
1381 } else {
1382 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1383 &snd_rme32_playback_spdif_ops);
1384 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE,
1385 &snd_rme32_capture_spdif_ops);
1386 rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
1387 }
1388
1389 /* set up ALSA pcm device for ADAT */
8b7fc421
RD		 1390 if ((pci->device == PCI_DEVICE_ID_RME_DIGI32) ||
1391 (pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO)) {
1da177e4
LT		 1392 /* ADAT is not available on DIGI32 and DIGI32 Pro */
1393 rme32->adat_pcm = NULL;
1394 }
1395 else {
1396 if ((err = snd_pcm_new(rme32->card, "Digi32 ADAT", 1,
1397 1, 1, &rme32->adat_pcm)) < 0)
1398 {
1399 return err;
1400 }
1401 rme32->adat_pcm->private_data = rme32;
1402 rme32->adat_pcm->private_free = snd_rme32_free_adat_pcm;
1403 strcpy(rme32->adat_pcm->name, "Digi32 ADAT");
1404 if (rme32->fullduplex_mode) {
1405 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1406 &snd_rme32_playback_adat_fd_ops);
1407 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE,
1408 &snd_rme32_capture_adat_fd_ops);
1409 snd_pcm_lib_preallocate_pages_for_all(rme32->adat_pcm, SNDRV_DMA_TYPE_CONTINUOUS,
1422bc50 1410 NULL,
1da177e4
LT		 1411 0, RME32_MID_BUFFER_SIZE);
1412 rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
1413 } else {
1414 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1415 &snd_rme32_playback_adat_ops);
1416 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE,
1417 &snd_rme32_capture_adat_ops);
1418 rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
1419 }
1420 }
1421
1422
1423 rme32->playback_periodsize = 0;
1424 rme32->capture_periodsize = 0;
1425
1426 /* make sure playback/capture is stopped, if by some reason active */
1427 snd_rme32_pcm_stop(rme32, 0);
1428
1429 /* reset DAC */
1430 snd_rme32_reset_dac(rme32);
1431
1432 /* reset buffer pointer */
1433 writel(0, rme32->iobase + RME32_IO_RESET_POS);
1434
1435 /* set default values in registers */
1436 rme32->wcreg = RME32_WCR_SEL | /* normal playback */
1437 RME32_WCR_INP_0 | /* input select */
1438 RME32_WCR_MUTE; /* muting on */
1439 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1440
1441
1442 /* init switch interface */
1443 if ((err = snd_rme32_create_switches(rme32->card, rme32)) < 0) {
1444 return err;
1445 }
1446
1447 /* init proc interface */
1448 snd_rme32_proc_init(rme32);
1449
1450 rme32->capture_substream = NULL;
1451 rme32->playback_substream = NULL;
1452
1453 return 0;
1454}
1455
1456/*
1457 * proc interface
1458 */
1459
1460static void
017ce802 1461snd_rme32_proc_read(struct snd_info_entry * entry, struct snd_info_buffer *buffer)
1da177e4
LT		 1462{
1463 int n;
017ce802 1464 struct rme32 *rme32 = (struct rme32 *) entry->private_data;
1da177e4
LT		 1465
1466 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
1467
1468 snd_iprintf(buffer, rme32->card->longname);
1469 snd_iprintf(buffer, " (index #%d)\n", rme32->card->number + 1);
1470
1471 snd_iprintf(buffer, "\nGeneral settings\n");
1472 if (rme32->fullduplex_mode)
1473 snd_iprintf(buffer, " Full-duplex mode\n");
1474 else
1475 snd_iprintf(buffer, " Half-duplex mode\n");
1476 if (RME32_PRO_WITH_8414(rme32)) {
1477 snd_iprintf(buffer, " receiver: CS8414\n");
1478 } else {
1479 snd_iprintf(buffer, " receiver: CS8412\n");
1480 }
1481 if (rme32->wcreg & RME32_WCR_MODE24) {
1482 snd_iprintf(buffer, " format: 24 bit");
1483 } else {
1484 snd_iprintf(buffer, " format: 16 bit");
1485 }
1486 if (rme32->wcreg & RME32_WCR_MONO) {
1487 snd_iprintf(buffer, ", Mono\n");
1488 } else {
1489 snd_iprintf(buffer, ", Stereo\n");
1490 }
1491
1492 snd_iprintf(buffer, "\nInput settings\n");
1493 switch (snd_rme32_getinputtype(rme32)) {
1494 case RME32_INPUT_OPTICAL:
1495 snd_iprintf(buffer, " input: optical");
1496 break;
1497 case RME32_INPUT_COAXIAL:
1498 snd_iprintf(buffer, " input: coaxial");
1499 break;
1500 case RME32_INPUT_INTERNAL:
1501 snd_iprintf(buffer, " input: internal");
1502 break;
1503 case RME32_INPUT_XLR:
1504 snd_iprintf(buffer, " input: XLR");
1505 break;
1506 }
1507 if (snd_rme32_capture_getrate(rme32, &n) < 0) {
1508 snd_iprintf(buffer, "\n sample rate: no valid signal\n");
1509 } else {
1510 if (n) {
1511 snd_iprintf(buffer, " (8 channels)\n");
1512 } else {
1513 snd_iprintf(buffer, " (2 channels)\n");
1514 }
1515 snd_iprintf(buffer, " sample rate: %d Hz\n",
1516 snd_rme32_capture_getrate(rme32, &n));
1517 }
1518
1519 snd_iprintf(buffer, "\nOutput settings\n");
1520 if (rme32->wcreg & RME32_WCR_SEL) {
1521 snd_iprintf(buffer, " output signal: normal playback");
1522 } else {
1523 snd_iprintf(buffer, " output signal: same as input");
1524 }
1525 if (rme32->wcreg & RME32_WCR_MUTE) {
1526 snd_iprintf(buffer, " (muted)\n");
1527 } else {
1528 snd_iprintf(buffer, "\n");
1529 }
1530
1531 /* master output frequency */
1532 if (!
1533 ((!(rme32->wcreg & RME32_WCR_FREQ_0))
1534 && (!(rme32->wcreg & RME32_WCR_FREQ_1)))) {
1535 snd_iprintf(buffer, " sample rate: %d Hz\n",
1536 snd_rme32_playback_getrate(rme32));
1537 }
1538 if (rme32->rcreg & RME32_RCR_KMODE) {
1539 snd_iprintf(buffer, " sample clock source: AutoSync\n");
1540 } else {
1541 snd_iprintf(buffer, " sample clock source: Internal\n");
1542 }
1543 if (rme32->wcreg & RME32_WCR_PRO) {
1544 snd_iprintf(buffer, " format: AES/EBU (professional)\n");
1545 } else {
1546 snd_iprintf(buffer, " format: IEC958 (consumer)\n");
1547 }
1548 if (rme32->wcreg & RME32_WCR_EMP) {
1549 snd_iprintf(buffer, " emphasis: on\n");
1550 } else {
1551 snd_iprintf(buffer, " emphasis: off\n");
1552 }
1553}
1554
e23e7a14 1555static void snd_rme32_proc_init(struct rme32 *rme32)
1da177e4 1556{
47f2769b 1557 snd_card_ro_proc_new(rme32->card, "rme32", rme32, snd_rme32_proc_read);
1da177e4
LT		 1558}
1559
1560/*
1561 * control interface
1562 */
1563
a5ce8890
TI		 1564#define snd_rme32_info_loopback_control snd_ctl_boolean_mono_info
1565
1da177e4 1566static int
017ce802
TI		 1567snd_rme32_get_loopback_control(struct snd_kcontrol *kcontrol,
1568 struct snd_ctl_elem_value *ucontrol)
1da177e4 1569{
017ce802 1570 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1571
1572 spin_lock_irq(&rme32->lock);
1573 ucontrol->value.integer.value[0] =
1574 rme32->wcreg & RME32_WCR_SEL ? 0 : 1;
1575 spin_unlock_irq(&rme32->lock);
1576 return 0;
1577}
1578static int
017ce802
TI		 1579snd_rme32_put_loopback_control(struct snd_kcontrol *kcontrol,
1580 struct snd_ctl_elem_value *ucontrol)
1da177e4 1581{
017ce802 1582 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1583 unsigned int val;
1584 int change;
1585
1586 val = ucontrol->value.integer.value[0] ? 0 : RME32_WCR_SEL;
1587 spin_lock_irq(&rme32->lock);
1588 val = (rme32->wcreg & ~RME32_WCR_SEL) | val;
1589 change = val != rme32->wcreg;
1590 if (ucontrol->value.integer.value[0])
1591 val &= ~RME32_WCR_MUTE;
1592 else
1593 val |= RME32_WCR_MUTE;
1594 rme32->wcreg = val;
1595 writel(val, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1596 spin_unlock_irq(&rme32->lock);
1597 return change;
1598}
1599
1600static int
017ce802
TI		 1601snd_rme32_info_inputtype_control(struct snd_kcontrol *kcontrol,
1602 struct snd_ctl_elem_info *uinfo)
1da177e4 1603{
017ce802 1604 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
11c6ef7c
TI		 1605 static const char * const texts[4] = {
1606 "Optical", "Coaxial", "Internal", "XLR"
1607 };
1608 int num_items;
1da177e4 1609
1da177e4 1610 switch (rme32->pci->device) {
8b7fc421
RD		 1611 case PCI_DEVICE_ID_RME_DIGI32:
1612 case PCI_DEVICE_ID_RME_DIGI32_8:
11c6ef7c 1613 num_items = 3;
1da177e4 1614 break;
8b7fc421 1615 case PCI_DEVICE_ID_RME_DIGI32_PRO:
11c6ef7c 1616 num_items = 4;
1da177e4
LT		 1617 break;
1618 default:
1619 snd_BUG();
11c6ef7c 1620 return -EINVAL;
1da177e4 1621 }
11c6ef7c 1622 return snd_ctl_enum_info(uinfo, 1, num_items, texts);
1da177e4
LT		 1623}
1624static int
017ce802
TI		 1625snd_rme32_get_inputtype_control(struct snd_kcontrol *kcontrol,
1626 struct snd_ctl_elem_value *ucontrol)
1da177e4 1627{
017ce802 1628 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1629 unsigned int items = 3;
1630
1631 spin_lock_irq(&rme32->lock);
1632 ucontrol->value.enumerated.item[0] = snd_rme32_getinputtype(rme32);
1633
1634 switch (rme32->pci->device) {
8b7fc421
RD		 1635 case PCI_DEVICE_ID_RME_DIGI32:
1636 case PCI_DEVICE_ID_RME_DIGI32_8:
1da177e4
LT		 1637 items = 3;
1638 break;
8b7fc421 1639 case PCI_DEVICE_ID_RME_DIGI32_PRO:
1da177e4
LT		 1640 items = 4;
1641 break;
1642 default:
1643 snd_BUG();
1644 break;
1645 }
1646 if (ucontrol->value.enumerated.item[0] >= items) {
1647 ucontrol->value.enumerated.item[0] = items - 1;
1648 }
1649
1650 spin_unlock_irq(&rme32->lock);
1651 return 0;
1652}
1653static int
017ce802
TI		 1654snd_rme32_put_inputtype_control(struct snd_kcontrol *kcontrol,
1655 struct snd_ctl_elem_value *ucontrol)
1da177e4 1656{
017ce802 1657 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1658 unsigned int val;
1659 int change, items = 3;
1660
1661 switch (rme32->pci->device) {
8b7fc421
RD		 1662 case PCI_DEVICE_ID_RME_DIGI32:
1663 case PCI_DEVICE_ID_RME_DIGI32_8:
1da177e4
LT		 1664 items = 3;
1665 break;
8b7fc421 1666 case PCI_DEVICE_ID_RME_DIGI32_PRO:
1da177e4
LT		 1667 items = 4;
1668 break;
1669 default:
1670 snd_BUG();
1671 break;
1672 }
1673 val = ucontrol->value.enumerated.item[0] % items;
1674
1675 spin_lock_irq(&rme32->lock);
1676 change = val != (unsigned int)snd_rme32_getinputtype(rme32);
1677 snd_rme32_setinputtype(rme32, val);
1678 spin_unlock_irq(&rme32->lock);
1679 return change;
1680}
1681
1682static int
017ce802
TI		 1683snd_rme32_info_clockmode_control(struct snd_kcontrol *kcontrol,
1684 struct snd_ctl_elem_info *uinfo)
1da177e4 1685{
11c6ef7c 1686 static const char * const texts[4] = { "AutoSync",
1da177e4
LT		 1687 "Internal 32.0kHz",
1688 "Internal 44.1kHz",
1689 "Internal 48.0kHz" };
1690
11c6ef7c 1691 return snd_ctl_enum_info(uinfo, 1, 4, texts);
1da177e4
LT		 1692}
1693static int
017ce802
TI		 1694snd_rme32_get_clockmode_control(struct snd_kcontrol *kcontrol,
1695 struct snd_ctl_elem_value *ucontrol)
1da177e4 1696{
017ce802 1697 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1698
1699 spin_lock_irq(&rme32->lock);
1700 ucontrol->value.enumerated.item[0] = snd_rme32_getclockmode(rme32);
1701 spin_unlock_irq(&rme32->lock);
1702 return 0;
1703}
1704static int
017ce802
TI		 1705snd_rme32_put_clockmode_control(struct snd_kcontrol *kcontrol,
1706 struct snd_ctl_elem_value *ucontrol)
1da177e4 1707{
017ce802 1708 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1709 unsigned int val;
1710 int change;
1711
1712 val = ucontrol->value.enumerated.item[0] % 3;
1713 spin_lock_irq(&rme32->lock);
1714 change = val != (unsigned int)snd_rme32_getclockmode(rme32);
1715 snd_rme32_setclockmode(rme32, val);
1716 spin_unlock_irq(&rme32->lock);
1717 return change;
1718}
1719
017ce802 1720static u32 snd_rme32_convert_from_aes(struct snd_aes_iec958 * aes)
1da177e4
LT		 1721{
1722 u32 val = 0;
1723 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME32_WCR_PRO : 0;
1724 if (val & RME32_WCR_PRO)
1725 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME32_WCR_EMP : 0;
1726 else
1727 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME32_WCR_EMP : 0;
1728 return val;
1729}
1730
017ce802 1731static void snd_rme32_convert_to_aes(struct snd_aes_iec958 * aes, u32 val)
1da177e4
LT		 1732{
1733 aes->status[0] = ((val & RME32_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0);
1734 if (val & RME32_WCR_PRO)
1735 aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1736 else
1737 aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1738}
1739
017ce802
TI		 1740static int snd_rme32_control_spdif_info(struct snd_kcontrol *kcontrol,
1741 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1742{
1743 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1744 uinfo->count = 1;
1745 return 0;
1746}
1747
017ce802
TI		 1748static int snd_rme32_control_spdif_get(struct snd_kcontrol *kcontrol,
1749 struct snd_ctl_elem_value *ucontrol)
1da177e4 1750{
017ce802 1751 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1752
1753 snd_rme32_convert_to_aes(&ucontrol->value.iec958,
1754 rme32->wcreg_spdif);
1755 return 0;
1756}
1757
017ce802
TI		 1758static int snd_rme32_control_spdif_put(struct snd_kcontrol *kcontrol,
1759 struct snd_ctl_elem_value *ucontrol)
1da177e4 1760{
017ce802 1761 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1762 int change;
1763 u32 val;
1764
1765 val = snd_rme32_convert_from_aes(&ucontrol->value.iec958);
1766 spin_lock_irq(&rme32->lock);
1767 change = val != rme32->wcreg_spdif;
1768 rme32->wcreg_spdif = val;
1769 spin_unlock_irq(&rme32->lock);
1770 return change;
1771}
1772
017ce802
TI		 1773static int snd_rme32_control_spdif_stream_info(struct snd_kcontrol *kcontrol,
1774 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1775{
1776 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1777 uinfo->count = 1;
1778 return 0;
1779}
1780
017ce802
TI		 1781static int snd_rme32_control_spdif_stream_get(struct snd_kcontrol *kcontrol,
1782 struct snd_ctl_elem_value *
1da177e4
LT		 1783 ucontrol)
1784{
017ce802 1785 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1786
1787 snd_rme32_convert_to_aes(&ucontrol->value.iec958,
1788 rme32->wcreg_spdif_stream);
1789 return 0;
1790}
1791
017ce802
TI		 1792static int snd_rme32_control_spdif_stream_put(struct snd_kcontrol *kcontrol,
1793 struct snd_ctl_elem_value *
1da177e4
LT		 1794 ucontrol)
1795{
017ce802 1796 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1797 int change;
1798 u32 val;
1799
1800 val = snd_rme32_convert_from_aes(&ucontrol->value.iec958);
1801 spin_lock_irq(&rme32->lock);
1802 change = val != rme32->wcreg_spdif_stream;
1803 rme32->wcreg_spdif_stream = val;
1804 rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP);
1805 rme32->wcreg |= val;
1806 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1807 spin_unlock_irq(&rme32->lock);
1808 return change;
1809}
1810
017ce802
TI		 1811static int snd_rme32_control_spdif_mask_info(struct snd_kcontrol *kcontrol,
1812 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1813{
1814 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1815 uinfo->count = 1;
1816 return 0;
1817}
1818
017ce802
TI		 1819static int snd_rme32_control_spdif_mask_get(struct snd_kcontrol *kcontrol,
1820 struct snd_ctl_elem_value *
1da177e4
LT		 1821 ucontrol)
1822{
1823 ucontrol->value.iec958.status[0] = kcontrol->private_value;
1824 return 0;
1825}
1826
017ce802 1827static struct snd_kcontrol_new snd_rme32_controls[] = {
1da177e4
LT		 1828 {
1829 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1830 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1831 .info = snd_rme32_control_spdif_info,
1832 .get = snd_rme32_control_spdif_get,
1833 .put = snd_rme32_control_spdif_put
1834 },
1835 {
1836 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1837 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1838 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM),
1839 .info = snd_rme32_control_spdif_stream_info,
1840 .get = snd_rme32_control_spdif_stream_get,
1841 .put = snd_rme32_control_spdif_stream_put
1842 },
1843 {
1844 .access = SNDRV_CTL_ELEM_ACCESS_READ,
67ed4161 1845 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1da177e4
LT		 1846 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
1847 .info = snd_rme32_control_spdif_mask_info,
1848 .get = snd_rme32_control_spdif_mask_get,
1849 .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_CON_EMPHASIS
1850 },
1851 {
1852 .access = SNDRV_CTL_ELEM_ACCESS_READ,
67ed4161 1853 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1da177e4
LT		 1854 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK),
1855 .info = snd_rme32_control_spdif_mask_info,
1856 .get = snd_rme32_control_spdif_mask_get,
1857 .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_PRO_EMPHASIS
1858 },
1859 {
1860 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1861 .name = "Input Connector",
1862 .info = snd_rme32_info_inputtype_control,
1863 .get = snd_rme32_get_inputtype_control,
1864 .put = snd_rme32_put_inputtype_control
1865 },
1866 {
1867 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1868 .name = "Loopback Input",
1869 .info = snd_rme32_info_loopback_control,
1870 .get = snd_rme32_get_loopback_control,
1871 .put = snd_rme32_put_loopback_control
1872 },
1873 {
1874 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1875 .name = "Sample Clock Source",
1876 .info = snd_rme32_info_clockmode_control,
1877 .get = snd_rme32_get_clockmode_control,
1878 .put = snd_rme32_put_clockmode_control
1879 }
1880};
1881
017ce802 1882static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32)
1da177e4
LT		 1883{
1884 int idx, err;
017ce802 1885 struct snd_kcontrol *kctl;
1da177e4
LT		 1886
1887 for (idx = 0; idx < (int)ARRAY_SIZE(snd_rme32_controls); idx++) {
1888 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme32_controls[idx], rme32))) < 0)
1889 return err;
1890 if (idx == 1) /* IEC958 (S/PDIF) Stream */
1891 rme32->spdif_ctl = kctl;
1892 }
1893
1894 return 0;
1895}
1896
1897/*
1898 * Card initialisation
1899 */
1900
017ce802 1901static void snd_rme32_card_free(struct snd_card *card)
1da177e4
LT		 1902{
1903 snd_rme32_free(card->private_data);
1904}
1905
e23e7a14 1906static int
1da177e4
LT		 1907snd_rme32_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
1908{
1909 static int dev;
017ce802
TI		 1910 struct rme32 *rme32;
1911 struct snd_card *card;
1da177e4
LT		 1912 int err;
1913
1914 if (dev >= SNDRV_CARDS) {
1915 return -ENODEV;
1916 }
1917 if (!enable[dev]) {
1918 dev++;
1919 return -ENOENT;
1920 }
1921
60c5772b
TI		 1922 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1923 sizeof(struct rme32), &card);
e58de7ba
TI		 1924 if (err < 0)
1925 return err;
1da177e4 1926 card->private_free = snd_rme32_card_free;
017ce802 1927 rme32 = (struct rme32 *) card->private_data;
1da177e4
LT		 1928 rme32->card = card;
1929 rme32->pci = pci;
1da177e4
LT		 1930 if (fullduplex[dev])
1931 rme32->fullduplex_mode = 1;
1932 if ((err = snd_rme32_create(rme32)) < 0) {
1933 snd_card_free(card);
1934 return err;
1935 }
1936
1937 strcpy(card->driver, "Digi32");
1938 switch (rme32->pci->device) {
8b7fc421 1939 case PCI_DEVICE_ID_RME_DIGI32:
1da177e4
LT		 1940 strcpy(card->shortname, "RME Digi32");
1941 break;
8b7fc421 1942 case PCI_DEVICE_ID_RME_DIGI32_8:
1da177e4
LT		 1943 strcpy(card->shortname, "RME Digi32/8");
1944 break;
8b7fc421 1945 case PCI_DEVICE_ID_RME_DIGI32_PRO:
1da177e4
LT		 1946 strcpy(card->shortname, "RME Digi32 PRO");
1947 break;
1948 }
1949 sprintf(card->longname, "%s (Rev. %d) at 0x%lx, irq %d",
1950 card->shortname, rme32->rev, rme32->port, rme32->irq);
1951
1952 if ((err = snd_card_register(card)) < 0) {
1953 snd_card_free(card);
1954 return err;
1955 }
1956 pci_set_drvdata(pci, card);
1957 dev++;
1958 return 0;
1959}
1960
e23e7a14 1961static void snd_rme32_remove(struct pci_dev *pci)
1da177e4
LT		 1962{
1963 snd_card_free(pci_get_drvdata(pci));
1da177e4
LT		 1964}
1965
e9f66d9b 1966static struct pci_driver rme32_driver = {
3733e424 1967 .name = KBUILD_MODNAME,
1da177e4
LT		 1968 .id_table = snd_rme32_ids,
1969 .probe = snd_rme32_probe,
e23e7a14 1970 .remove = snd_rme32_remove,
1da177e4
LT		 1971};
1972
e9f66d9b 1973module_pci_driver(rme32_driver);
Linux 6.x block layer and io_uring tree(s)