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1a59d1b8 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
e12229b4 MB |
2 | /* |
3 | * Driver for Digigram pcxhr compatible soundcards | |
4 | * | |
5 | * main file with alsa callbacks | |
6 | * | |
7 | * Copyright (c) 2004 by Digigram <alsa@digigram.com> | |
e12229b4 MB |
8 | */ |
9 | ||
10 | ||
e12229b4 MB |
11 | #include <linux/init.h> |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/slab.h> | |
14 | #include <linux/pci.h> | |
9d2f928d | 15 | #include <linux/dma-mapping.h> |
e12229b4 | 16 | #include <linux/delay.h> |
65a77217 | 17 | #include <linux/module.h> |
62932df8 IM |
18 | #include <linux/mutex.h> |
19 | ||
e12229b4 MB |
20 | #include <sound/core.h> |
21 | #include <sound/initval.h> | |
22 | #include <sound/info.h> | |
23 | #include <sound/control.h> | |
24 | #include <sound/pcm.h> | |
25 | #include <sound/pcm_params.h> | |
26 | #include "pcxhr.h" | |
27 | #include "pcxhr_mixer.h" | |
28 | #include "pcxhr_hwdep.h" | |
29 | #include "pcxhr_core.h" | |
9d948d27 | 30 | #include "pcxhr_mix22.h" |
e12229b4 MB |
31 | |
32 | #define DRIVER_NAME "pcxhr" | |
33 | ||
9d948d27 MB |
34 | MODULE_AUTHOR("Markus Bollinger <bollinger@digigram.com>, " |
35 | "Marc Titinger <titinger@digigram.com>"); | |
e12229b4 MB |
36 | MODULE_DESCRIPTION("Digigram " DRIVER_NAME " " PCXHR_DRIVER_VERSION_STRING); |
37 | MODULE_LICENSE("GPL"); | |
e12229b4 | 38 | |
9d948d27 MB |
39 | static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ |
40 | static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ | |
a67ff6a5 RR |
41 | static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */ |
42 | static bool mono[SNDRV_CARDS]; /* capture mono only */ | |
e12229b4 MB |
43 | |
44 | module_param_array(index, int, NULL, 0444); | |
45 | MODULE_PARM_DESC(index, "Index value for Digigram " DRIVER_NAME " soundcard"); | |
46 | module_param_array(id, charp, NULL, 0444); | |
47 | MODULE_PARM_DESC(id, "ID string for Digigram " DRIVER_NAME " soundcard"); | |
48 | module_param_array(enable, bool, NULL, 0444); | |
49 | MODULE_PARM_DESC(enable, "Enable Digigram " DRIVER_NAME " soundcard"); | |
50 | module_param_array(mono, bool, NULL, 0444); | |
51 | MODULE_PARM_DESC(mono, "Mono capture mode (default is stereo)"); | |
52 | ||
53 | enum { | |
54 | PCI_ID_VX882HR, | |
55 | PCI_ID_PCX882HR, | |
56 | PCI_ID_VX881HR, | |
57 | PCI_ID_PCX881HR, | |
9d948d27 MB |
58 | PCI_ID_VX882E, |
59 | PCI_ID_PCX882E, | |
60 | PCI_ID_VX881E, | |
61 | PCI_ID_PCX881E, | |
62 | PCI_ID_VX1222HR, | |
e12229b4 | 63 | PCI_ID_PCX1222HR, |
9d948d27 | 64 | PCI_ID_VX1221HR, |
e12229b4 | 65 | PCI_ID_PCX1221HR, |
9d948d27 MB |
66 | PCI_ID_VX1222E, |
67 | PCI_ID_PCX1222E, | |
68 | PCI_ID_VX1221E, | |
69 | PCI_ID_PCX1221E, | |
70 | PCI_ID_VX222HR, | |
71 | PCI_ID_VX222E, | |
72 | PCI_ID_PCX22HR, | |
73 | PCI_ID_PCX22E, | |
74 | PCI_ID_VX222HRMIC, | |
75 | PCI_ID_VX222E_MIC, | |
76 | PCI_ID_PCX924HR, | |
77 | PCI_ID_PCX924E, | |
78 | PCI_ID_PCX924HRMIC, | |
79 | PCI_ID_PCX924E_MIC, | |
8c3f1b1c MB |
80 | PCI_ID_VX442HR, |
81 | PCI_ID_PCX442HR, | |
82 | PCI_ID_VX442E, | |
83 | PCI_ID_PCX442E, | |
84 | PCI_ID_VX822HR, | |
85 | PCI_ID_PCX822HR, | |
86 | PCI_ID_VX822E, | |
87 | PCI_ID_PCX822E, | |
e12229b4 MB |
88 | PCI_ID_LAST |
89 | }; | |
90 | ||
9baa3c34 | 91 | static const struct pci_device_id pcxhr_ids[] = { |
9d948d27 MB |
92 | { 0x10b5, 0x9656, 0x1369, 0xb001, 0, 0, PCI_ID_VX882HR, }, |
93 | { 0x10b5, 0x9656, 0x1369, 0xb101, 0, 0, PCI_ID_PCX882HR, }, | |
94 | { 0x10b5, 0x9656, 0x1369, 0xb201, 0, 0, PCI_ID_VX881HR, }, | |
95 | { 0x10b5, 0x9656, 0x1369, 0xb301, 0, 0, PCI_ID_PCX881HR, }, | |
96 | { 0x10b5, 0x9056, 0x1369, 0xb021, 0, 0, PCI_ID_VX882E, }, | |
97 | { 0x10b5, 0x9056, 0x1369, 0xb121, 0, 0, PCI_ID_PCX882E, }, | |
98 | { 0x10b5, 0x9056, 0x1369, 0xb221, 0, 0, PCI_ID_VX881E, }, | |
99 | { 0x10b5, 0x9056, 0x1369, 0xb321, 0, 0, PCI_ID_PCX881E, }, | |
100 | { 0x10b5, 0x9656, 0x1369, 0xb401, 0, 0, PCI_ID_VX1222HR, }, | |
101 | { 0x10b5, 0x9656, 0x1369, 0xb501, 0, 0, PCI_ID_PCX1222HR, }, | |
102 | { 0x10b5, 0x9656, 0x1369, 0xb601, 0, 0, PCI_ID_VX1221HR, }, | |
103 | { 0x10b5, 0x9656, 0x1369, 0xb701, 0, 0, PCI_ID_PCX1221HR, }, | |
104 | { 0x10b5, 0x9056, 0x1369, 0xb421, 0, 0, PCI_ID_VX1222E, }, | |
105 | { 0x10b5, 0x9056, 0x1369, 0xb521, 0, 0, PCI_ID_PCX1222E, }, | |
106 | { 0x10b5, 0x9056, 0x1369, 0xb621, 0, 0, PCI_ID_VX1221E, }, | |
107 | { 0x10b5, 0x9056, 0x1369, 0xb721, 0, 0, PCI_ID_PCX1221E, }, | |
108 | { 0x10b5, 0x9056, 0x1369, 0xba01, 0, 0, PCI_ID_VX222HR, }, | |
109 | { 0x10b5, 0x9056, 0x1369, 0xba21, 0, 0, PCI_ID_VX222E, }, | |
110 | { 0x10b5, 0x9056, 0x1369, 0xbd01, 0, 0, PCI_ID_PCX22HR, }, | |
111 | { 0x10b5, 0x9056, 0x1369, 0xbd21, 0, 0, PCI_ID_PCX22E, }, | |
112 | { 0x10b5, 0x9056, 0x1369, 0xbc01, 0, 0, PCI_ID_VX222HRMIC, }, | |
113 | { 0x10b5, 0x9056, 0x1369, 0xbc21, 0, 0, PCI_ID_VX222E_MIC, }, | |
114 | { 0x10b5, 0x9056, 0x1369, 0xbb01, 0, 0, PCI_ID_PCX924HR, }, | |
115 | { 0x10b5, 0x9056, 0x1369, 0xbb21, 0, 0, PCI_ID_PCX924E, }, | |
116 | { 0x10b5, 0x9056, 0x1369, 0xbf01, 0, 0, PCI_ID_PCX924HRMIC, }, | |
117 | { 0x10b5, 0x9056, 0x1369, 0xbf21, 0, 0, PCI_ID_PCX924E_MIC, }, | |
8c3f1b1c MB |
118 | { 0x10b5, 0x9656, 0x1369, 0xd001, 0, 0, PCI_ID_VX442HR, }, |
119 | { 0x10b5, 0x9656, 0x1369, 0xd101, 0, 0, PCI_ID_PCX442HR, }, | |
120 | { 0x10b5, 0x9056, 0x1369, 0xd021, 0, 0, PCI_ID_VX442E, }, | |
121 | { 0x10b5, 0x9056, 0x1369, 0xd121, 0, 0, PCI_ID_PCX442E, }, | |
122 | { 0x10b5, 0x9656, 0x1369, 0xd201, 0, 0, PCI_ID_VX822HR, }, | |
123 | { 0x10b5, 0x9656, 0x1369, 0xd301, 0, 0, PCI_ID_PCX822HR, }, | |
124 | { 0x10b5, 0x9056, 0x1369, 0xd221, 0, 0, PCI_ID_VX822E, }, | |
125 | { 0x10b5, 0x9056, 0x1369, 0xd321, 0, 0, PCI_ID_PCX822E, }, | |
e12229b4 MB |
126 | { 0, } |
127 | }; | |
128 | ||
129 | MODULE_DEVICE_TABLE(pci, pcxhr_ids); | |
130 | ||
131 | struct board_parameters { | |
132 | char* board_name; | |
133 | short playback_chips; | |
134 | short capture_chips; | |
9d948d27 | 135 | short fw_file_set; |
e12229b4 MB |
136 | short firmware_num; |
137 | }; | |
98fd5398 | 138 | static const struct board_parameters pcxhr_board_params[] = { |
9d948d27 MB |
139 | [PCI_ID_VX882HR] = { "VX882HR", 4, 4, 0, 41 }, |
140 | [PCI_ID_PCX882HR] = { "PCX882HR", 4, 4, 0, 41 }, | |
141 | [PCI_ID_VX881HR] = { "VX881HR", 4, 4, 0, 41 }, | |
142 | [PCI_ID_PCX881HR] = { "PCX881HR", 4, 4, 0, 41 }, | |
143 | [PCI_ID_VX882E] = { "VX882e", 4, 4, 1, 41 }, | |
144 | [PCI_ID_PCX882E] = { "PCX882e", 4, 4, 1, 41 }, | |
145 | [PCI_ID_VX881E] = { "VX881e", 4, 4, 1, 41 }, | |
146 | [PCI_ID_PCX881E] = { "PCX881e", 4, 4, 1, 41 }, | |
147 | [PCI_ID_VX1222HR] = { "VX1222HR", 6, 1, 2, 42 }, | |
148 | [PCI_ID_PCX1222HR] = { "PCX1222HR", 6, 1, 2, 42 }, | |
149 | [PCI_ID_VX1221HR] = { "VX1221HR", 6, 1, 2, 42 }, | |
150 | [PCI_ID_PCX1221HR] = { "PCX1221HR", 6, 1, 2, 42 }, | |
151 | [PCI_ID_VX1222E] = { "VX1222e", 6, 1, 3, 42 }, | |
152 | [PCI_ID_PCX1222E] = { "PCX1222e", 6, 1, 3, 42 }, | |
153 | [PCI_ID_VX1221E] = { "VX1221e", 6, 1, 3, 42 }, | |
154 | [PCI_ID_PCX1221E] = { "PCX1221e", 6, 1, 3, 42 }, | |
155 | [PCI_ID_VX222HR] = { "VX222HR", 1, 1, 4, 44 }, | |
156 | [PCI_ID_VX222E] = { "VX222e", 1, 1, 4, 44 }, | |
157 | [PCI_ID_PCX22HR] = { "PCX22HR", 1, 0, 4, 44 }, | |
158 | [PCI_ID_PCX22E] = { "PCX22e", 1, 0, 4, 44 }, | |
159 | [PCI_ID_VX222HRMIC] = { "VX222HR-Mic", 1, 1, 5, 44 }, | |
160 | [PCI_ID_VX222E_MIC] = { "VX222e-Mic", 1, 1, 5, 44 }, | |
161 | [PCI_ID_PCX924HR] = { "PCX924HR", 1, 1, 5, 44 }, | |
162 | [PCI_ID_PCX924E] = { "PCX924e", 1, 1, 5, 44 }, | |
163 | [PCI_ID_PCX924HRMIC] = { "PCX924HR-Mic", 1, 1, 5, 44 }, | |
164 | [PCI_ID_PCX924E_MIC] = { "PCX924e-Mic", 1, 1, 5, 44 }, | |
8c3f1b1c MB |
165 | [PCI_ID_VX442HR] = { "VX442HR", 2, 2, 0, 41 }, |
166 | [PCI_ID_PCX442HR] = { "PCX442HR", 2, 2, 0, 41 }, | |
167 | [PCI_ID_VX442E] = { "VX442e", 2, 2, 1, 41 }, | |
168 | [PCI_ID_PCX442E] = { "PCX442e", 2, 2, 1, 41 }, | |
169 | [PCI_ID_VX822HR] = { "VX822HR", 4, 1, 2, 42 }, | |
170 | [PCI_ID_PCX822HR] = { "PCX822HR", 4, 1, 2, 42 }, | |
171 | [PCI_ID_VX822E] = { "VX822e", 4, 1, 3, 42 }, | |
172 | [PCI_ID_PCX822E] = { "PCX822e", 4, 1, 3, 42 }, | |
e12229b4 MB |
173 | }; |
174 | ||
9d948d27 MB |
175 | /* boards without hw AES1 and SRC onboard are all using fw_file_set==4 */ |
176 | /* VX222HR, VX222e, PCX22HR and PCX22e */ | |
177 | #define PCXHR_BOARD_HAS_AES1(x) (x->fw_file_set != 4) | |
178 | /* some boards do not support 192kHz on digital AES input plugs */ | |
179 | #define PCXHR_BOARD_AESIN_NO_192K(x) ((x->capture_chips == 0) || \ | |
180 | (x->fw_file_set == 0) || \ | |
181 | (x->fw_file_set == 2)) | |
e12229b4 MB |
182 | |
183 | static int pcxhr_pll_freq_register(unsigned int freq, unsigned int* pllreg, | |
184 | unsigned int* realfreq) | |
185 | { | |
186 | unsigned int reg; | |
187 | ||
9d948d27 | 188 | if (freq < 6900 || freq > 110000) |
e12229b4 | 189 | return -EINVAL; |
9d948d27 MB |
190 | reg = (28224000 * 2) / freq; |
191 | reg = (reg - 1) / 2; | |
e12229b4 MB |
192 | if (reg < 0x200) |
193 | *pllreg = reg + 0x800; | |
194 | else if (reg < 0x400) | |
195 | *pllreg = reg & 0x1ff; | |
196 | else if (reg < 0x800) { | |
197 | *pllreg = ((reg >> 1) & 0x1ff) + 0x200; | |
198 | reg &= ~1; | |
199 | } else { | |
200 | *pllreg = ((reg >> 2) & 0x1ff) + 0x400; | |
201 | reg &= ~3; | |
202 | } | |
203 | if (realfreq) | |
9d948d27 | 204 | *realfreq = (28224000 / (reg + 1)); |
e12229b4 MB |
205 | return 0; |
206 | } | |
207 | ||
208 | ||
209 | #define PCXHR_FREQ_REG_MASK 0x1f | |
210 | #define PCXHR_FREQ_QUARTZ_48000 0x00 | |
211 | #define PCXHR_FREQ_QUARTZ_24000 0x01 | |
212 | #define PCXHR_FREQ_QUARTZ_12000 0x09 | |
213 | #define PCXHR_FREQ_QUARTZ_32000 0x08 | |
214 | #define PCXHR_FREQ_QUARTZ_16000 0x04 | |
215 | #define PCXHR_FREQ_QUARTZ_8000 0x0c | |
216 | #define PCXHR_FREQ_QUARTZ_44100 0x02 | |
217 | #define PCXHR_FREQ_QUARTZ_22050 0x0a | |
218 | #define PCXHR_FREQ_QUARTZ_11025 0x06 | |
219 | #define PCXHR_FREQ_PLL 0x05 | |
220 | #define PCXHR_FREQ_QUARTZ_192000 0x10 | |
221 | #define PCXHR_FREQ_QUARTZ_96000 0x18 | |
222 | #define PCXHR_FREQ_QUARTZ_176400 0x14 | |
223 | #define PCXHR_FREQ_QUARTZ_88200 0x1c | |
224 | #define PCXHR_FREQ_QUARTZ_128000 0x12 | |
225 | #define PCXHR_FREQ_QUARTZ_64000 0x1a | |
226 | ||
227 | #define PCXHR_FREQ_WORD_CLOCK 0x0f | |
228 | #define PCXHR_FREQ_SYNC_AES 0x0e | |
229 | #define PCXHR_FREQ_AES_1 0x07 | |
230 | #define PCXHR_FREQ_AES_2 0x0b | |
231 | #define PCXHR_FREQ_AES_3 0x03 | |
232 | #define PCXHR_FREQ_AES_4 0x0d | |
233 | ||
e12229b4 MB |
234 | static int pcxhr_get_clock_reg(struct pcxhr_mgr *mgr, unsigned int rate, |
235 | unsigned int *reg, unsigned int *freq) | |
236 | { | |
237 | unsigned int val, realfreq, pllreg; | |
238 | struct pcxhr_rmh rmh; | |
239 | int err; | |
240 | ||
241 | realfreq = rate; | |
242 | switch (mgr->use_clock_type) { | |
243 | case PCXHR_CLOCK_TYPE_INTERNAL : /* clock by quartz or pll */ | |
244 | switch (rate) { | |
245 | case 48000 : val = PCXHR_FREQ_QUARTZ_48000; break; | |
246 | case 24000 : val = PCXHR_FREQ_QUARTZ_24000; break; | |
247 | case 12000 : val = PCXHR_FREQ_QUARTZ_12000; break; | |
248 | case 32000 : val = PCXHR_FREQ_QUARTZ_32000; break; | |
249 | case 16000 : val = PCXHR_FREQ_QUARTZ_16000; break; | |
250 | case 8000 : val = PCXHR_FREQ_QUARTZ_8000; break; | |
251 | case 44100 : val = PCXHR_FREQ_QUARTZ_44100; break; | |
252 | case 22050 : val = PCXHR_FREQ_QUARTZ_22050; break; | |
253 | case 11025 : val = PCXHR_FREQ_QUARTZ_11025; break; | |
254 | case 192000 : val = PCXHR_FREQ_QUARTZ_192000; break; | |
255 | case 96000 : val = PCXHR_FREQ_QUARTZ_96000; break; | |
256 | case 176400 : val = PCXHR_FREQ_QUARTZ_176400; break; | |
257 | case 88200 : val = PCXHR_FREQ_QUARTZ_88200; break; | |
258 | case 128000 : val = PCXHR_FREQ_QUARTZ_128000; break; | |
259 | case 64000 : val = PCXHR_FREQ_QUARTZ_64000; break; | |
260 | default : | |
261 | val = PCXHR_FREQ_PLL; | |
262 | /* get the value for the pll register */ | |
263 | err = pcxhr_pll_freq_register(rate, &pllreg, &realfreq); | |
264 | if (err) | |
265 | return err; | |
266 | pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); | |
267 | rmh.cmd[0] |= IO_NUM_REG_GENCLK; | |
268 | rmh.cmd[1] = pllreg & MASK_DSP_WORD; | |
269 | rmh.cmd[2] = pllreg >> 24; | |
270 | rmh.cmd_len = 3; | |
271 | err = pcxhr_send_msg(mgr, &rmh); | |
272 | if (err < 0) { | |
b59bb8ef | 273 | dev_err(&mgr->pci->dev, |
9d948d27 MB |
274 | "error CMD_ACCESS_IO_WRITE " |
275 | "for PLL register : %x!\n", err); | |
e12229b4 MB |
276 | return err; |
277 | } | |
278 | } | |
279 | break; | |
9d948d27 MB |
280 | case PCXHR_CLOCK_TYPE_WORD_CLOCK: |
281 | val = PCXHR_FREQ_WORD_CLOCK; | |
282 | break; | |
283 | case PCXHR_CLOCK_TYPE_AES_SYNC: | |
284 | val = PCXHR_FREQ_SYNC_AES; | |
285 | break; | |
286 | case PCXHR_CLOCK_TYPE_AES_1: | |
287 | val = PCXHR_FREQ_AES_1; | |
288 | break; | |
289 | case PCXHR_CLOCK_TYPE_AES_2: | |
290 | val = PCXHR_FREQ_AES_2; | |
291 | break; | |
292 | case PCXHR_CLOCK_TYPE_AES_3: | |
293 | val = PCXHR_FREQ_AES_3; | |
294 | break; | |
295 | case PCXHR_CLOCK_TYPE_AES_4: | |
296 | val = PCXHR_FREQ_AES_4; | |
297 | break; | |
298 | default: | |
299 | return -EINVAL; | |
e12229b4 MB |
300 | } |
301 | *reg = val; | |
302 | *freq = realfreq; | |
303 | return 0; | |
304 | } | |
305 | ||
306 | ||
9d948d27 MB |
307 | static int pcxhr_sub_set_clock(struct pcxhr_mgr *mgr, |
308 | unsigned int rate, | |
309 | int *changed) | |
e12229b4 MB |
310 | { |
311 | unsigned int val, realfreq, speed; | |
312 | struct pcxhr_rmh rmh; | |
9d948d27 | 313 | int err; |
e12229b4 MB |
314 | |
315 | err = pcxhr_get_clock_reg(mgr, rate, &val, &realfreq); | |
316 | if (err) | |
317 | return err; | |
318 | ||
319 | /* codec speed modes */ | |
320 | if (rate < 55000) | |
321 | speed = 0; /* single speed */ | |
322 | else if (rate < 100000) | |
323 | speed = 1; /* dual speed */ | |
324 | else | |
325 | speed = 2; /* quad speed */ | |
326 | if (mgr->codec_speed != speed) { | |
9d948d27 | 327 | pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); /* mute outputs */ |
e12229b4 | 328 | rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT; |
9d948d27 MB |
329 | if (DSP_EXT_CMD_SET(mgr)) { |
330 | rmh.cmd[1] = 1; | |
331 | rmh.cmd_len = 2; | |
332 | } | |
e12229b4 MB |
333 | err = pcxhr_send_msg(mgr, &rmh); |
334 | if (err) | |
335 | return err; | |
336 | ||
9d948d27 | 337 | pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); /* set speed ratio */ |
e12229b4 MB |
338 | rmh.cmd[0] |= IO_NUM_SPEED_RATIO; |
339 | rmh.cmd[1] = speed; | |
340 | rmh.cmd_len = 2; | |
341 | err = pcxhr_send_msg(mgr, &rmh); | |
342 | if (err) | |
343 | return err; | |
344 | } | |
345 | /* set the new frequency */ | |
b59bb8ef | 346 | dev_dbg(&mgr->pci->dev, "clock register : set %x\n", val); |
9d948d27 MB |
347 | err = pcxhr_write_io_num_reg_cont(mgr, PCXHR_FREQ_REG_MASK, |
348 | val, changed); | |
e12229b4 MB |
349 | if (err) |
350 | return err; | |
9d948d27 | 351 | |
e12229b4 MB |
352 | mgr->sample_rate_real = realfreq; |
353 | mgr->cur_clock_type = mgr->use_clock_type; | |
354 | ||
355 | /* unmute after codec speed modes */ | |
356 | if (mgr->codec_speed != speed) { | |
9d948d27 | 357 | pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ); /* unmute outputs */ |
e12229b4 | 358 | rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT; |
9d948d27 MB |
359 | if (DSP_EXT_CMD_SET(mgr)) { |
360 | rmh.cmd[1] = 1; | |
361 | rmh.cmd_len = 2; | |
362 | } | |
e12229b4 MB |
363 | err = pcxhr_send_msg(mgr, &rmh); |
364 | if (err) | |
365 | return err; | |
9d948d27 | 366 | mgr->codec_speed = speed; /* save new codec speed */ |
e12229b4 MB |
367 | } |
368 | ||
b59bb8ef | 369 | dev_dbg(&mgr->pci->dev, "pcxhr_sub_set_clock to %dHz (realfreq=%d)\n", |
9d948d27 MB |
370 | rate, realfreq); |
371 | return 0; | |
372 | } | |
373 | ||
374 | #define PCXHR_MODIFY_CLOCK_S_BIT 0x04 | |
375 | ||
376 | #define PCXHR_IRQ_TIMER_FREQ 92000 | |
377 | #define PCXHR_IRQ_TIMER_PERIOD 48 | |
378 | ||
379 | int pcxhr_set_clock(struct pcxhr_mgr *mgr, unsigned int rate) | |
380 | { | |
381 | struct pcxhr_rmh rmh; | |
382 | int err, changed; | |
383 | ||
384 | if (rate == 0) | |
385 | return 0; /* nothing to do */ | |
386 | ||
387 | if (mgr->is_hr_stereo) | |
388 | err = hr222_sub_set_clock(mgr, rate, &changed); | |
389 | else | |
390 | err = pcxhr_sub_set_clock(mgr, rate, &changed); | |
391 | ||
392 | if (err) | |
393 | return err; | |
394 | ||
e12229b4 MB |
395 | if (changed) { |
396 | pcxhr_init_rmh(&rmh, CMD_MODIFY_CLOCK); | |
9d948d27 | 397 | rmh.cmd[0] |= PCXHR_MODIFY_CLOCK_S_BIT; /* resync fifos */ |
e12229b4 MB |
398 | if (rate < PCXHR_IRQ_TIMER_FREQ) |
399 | rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD; | |
400 | else | |
401 | rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD * 2; | |
402 | rmh.cmd[2] = rate; | |
403 | rmh.cmd_len = 3; | |
404 | err = pcxhr_send_msg(mgr, &rmh); | |
405 | if (err) | |
406 | return err; | |
407 | } | |
e12229b4 MB |
408 | return 0; |
409 | } | |
410 | ||
411 | ||
9d948d27 MB |
412 | static int pcxhr_sub_get_external_clock(struct pcxhr_mgr *mgr, |
413 | enum pcxhr_clock_type clock_type, | |
414 | int *sample_rate) | |
e12229b4 MB |
415 | { |
416 | struct pcxhr_rmh rmh; | |
417 | unsigned char reg; | |
418 | int err, rate; | |
419 | ||
420 | switch (clock_type) { | |
9d948d27 MB |
421 | case PCXHR_CLOCK_TYPE_WORD_CLOCK: |
422 | reg = REG_STATUS_WORD_CLOCK; | |
423 | break; | |
424 | case PCXHR_CLOCK_TYPE_AES_SYNC: | |
425 | reg = REG_STATUS_AES_SYNC; | |
426 | break; | |
427 | case PCXHR_CLOCK_TYPE_AES_1: | |
428 | reg = REG_STATUS_AES_1; | |
429 | break; | |
430 | case PCXHR_CLOCK_TYPE_AES_2: | |
431 | reg = REG_STATUS_AES_2; | |
432 | break; | |
433 | case PCXHR_CLOCK_TYPE_AES_3: | |
434 | reg = REG_STATUS_AES_3; | |
435 | break; | |
436 | case PCXHR_CLOCK_TYPE_AES_4: | |
437 | reg = REG_STATUS_AES_4; | |
438 | break; | |
439 | default: | |
440 | return -EINVAL; | |
e12229b4 MB |
441 | } |
442 | pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ); | |
443 | rmh.cmd_len = 2; | |
444 | rmh.cmd[0] |= IO_NUM_REG_STATUS; | |
445 | if (mgr->last_reg_stat != reg) { | |
446 | rmh.cmd[1] = reg; | |
447 | err = pcxhr_send_msg(mgr, &rmh); | |
448 | if (err) | |
449 | return err; | |
9d948d27 | 450 | udelay(100); /* wait minimum 2 sample_frames at 32kHz ! */ |
e12229b4 MB |
451 | mgr->last_reg_stat = reg; |
452 | } | |
453 | rmh.cmd[1] = REG_STATUS_CURRENT; | |
454 | err = pcxhr_send_msg(mgr, &rmh); | |
455 | if (err) | |
456 | return err; | |
457 | switch (rmh.stat[1] & 0x0f) { | |
458 | case REG_STATUS_SYNC_32000 : rate = 32000; break; | |
459 | case REG_STATUS_SYNC_44100 : rate = 44100; break; | |
460 | case REG_STATUS_SYNC_48000 : rate = 48000; break; | |
461 | case REG_STATUS_SYNC_64000 : rate = 64000; break; | |
462 | case REG_STATUS_SYNC_88200 : rate = 88200; break; | |
463 | case REG_STATUS_SYNC_96000 : rate = 96000; break; | |
464 | case REG_STATUS_SYNC_128000 : rate = 128000; break; | |
465 | case REG_STATUS_SYNC_176400 : rate = 176400; break; | |
466 | case REG_STATUS_SYNC_192000 : rate = 192000; break; | |
467 | default: rate = 0; | |
468 | } | |
b59bb8ef | 469 | dev_dbg(&mgr->pci->dev, "External clock is at %d Hz\n", rate); |
e12229b4 MB |
470 | *sample_rate = rate; |
471 | return 0; | |
472 | } | |
473 | ||
474 | ||
9d948d27 MB |
475 | int pcxhr_get_external_clock(struct pcxhr_mgr *mgr, |
476 | enum pcxhr_clock_type clock_type, | |
477 | int *sample_rate) | |
478 | { | |
479 | if (mgr->is_hr_stereo) | |
480 | return hr222_get_external_clock(mgr, clock_type, | |
481 | sample_rate); | |
482 | else | |
483 | return pcxhr_sub_get_external_clock(mgr, clock_type, | |
484 | sample_rate); | |
485 | } | |
486 | ||
e12229b4 MB |
487 | /* |
488 | * start or stop playback/capture substream | |
489 | */ | |
f48a6df2 TI |
490 | static int pcxhr_set_stream_state(struct snd_pcxhr *chip, |
491 | struct pcxhr_stream *stream) | |
e12229b4 MB |
492 | { |
493 | int err; | |
e12229b4 MB |
494 | struct pcxhr_rmh rmh; |
495 | int stream_mask, start; | |
496 | ||
497 | if (stream->status == PCXHR_STREAM_STATUS_SCHEDULE_RUN) | |
498 | start = 1; | |
499 | else { | |
500 | if (stream->status != PCXHR_STREAM_STATUS_SCHEDULE_STOP) { | |
f48a6df2 TI |
501 | dev_err(chip->card->dev, |
502 | "pcxhr_set_stream_state CANNOT be stopped\n"); | |
e12229b4 MB |
503 | return -EINVAL; |
504 | } | |
505 | start = 0; | |
506 | } | |
507 | if (!stream->substream) | |
508 | return -EINVAL; | |
509 | ||
510 | stream->timer_abs_periods = 0; | |
9d948d27 | 511 | stream->timer_period_frag = 0; /* reset theoretical stream pos */ |
e12229b4 MB |
512 | stream->timer_buf_periods = 0; |
513 | stream->timer_is_synced = 0; | |
514 | ||
9d948d27 MB |
515 | stream_mask = |
516 | stream->pipe->is_capture ? 1 : 1<<stream->substream->number; | |
e12229b4 MB |
517 | |
518 | pcxhr_init_rmh(&rmh, start ? CMD_START_STREAM : CMD_STOP_STREAM); | |
519 | pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture, | |
520 | stream->pipe->first_audio, 0, stream_mask); | |
521 | ||
522 | chip = snd_pcm_substream_chip(stream->substream); | |
523 | ||
524 | err = pcxhr_send_msg(chip->mgr, &rmh); | |
525 | if (err) | |
b59bb8ef TI |
526 | dev_err(chip->card->dev, |
527 | "ERROR pcxhr_set_stream_state err=%x;\n", err); | |
9d948d27 MB |
528 | stream->status = |
529 | start ? PCXHR_STREAM_STATUS_STARTED : PCXHR_STREAM_STATUS_STOPPED; | |
e12229b4 MB |
530 | return err; |
531 | } | |
532 | ||
533 | #define HEADER_FMT_BASE_LIN 0xfed00000 | |
534 | #define HEADER_FMT_BASE_FLOAT 0xfad00000 | |
535 | #define HEADER_FMT_INTEL 0x00008000 | |
536 | #define HEADER_FMT_24BITS 0x00004000 | |
537 | #define HEADER_FMT_16BITS 0x00002000 | |
538 | #define HEADER_FMT_UPTO11 0x00000200 | |
539 | #define HEADER_FMT_UPTO32 0x00000100 | |
540 | #define HEADER_FMT_MONO 0x00000080 | |
541 | ||
542 | static int pcxhr_set_format(struct pcxhr_stream *stream) | |
543 | { | |
544 | int err, is_capture, sample_rate, stream_num; | |
545 | struct snd_pcxhr *chip; | |
546 | struct pcxhr_rmh rmh; | |
547 | unsigned int header; | |
548 | ||
f48a6df2 | 549 | chip = snd_pcm_substream_chip(stream->substream); |
e12229b4 MB |
550 | switch (stream->format) { |
551 | case SNDRV_PCM_FORMAT_U8: | |
552 | header = HEADER_FMT_BASE_LIN; | |
553 | break; | |
554 | case SNDRV_PCM_FORMAT_S16_LE: | |
9d948d27 MB |
555 | header = HEADER_FMT_BASE_LIN | |
556 | HEADER_FMT_16BITS | HEADER_FMT_INTEL; | |
e12229b4 MB |
557 | break; |
558 | case SNDRV_PCM_FORMAT_S16_BE: | |
559 | header = HEADER_FMT_BASE_LIN | HEADER_FMT_16BITS; | |
560 | break; | |
561 | case SNDRV_PCM_FORMAT_S24_3LE: | |
9d948d27 MB |
562 | header = HEADER_FMT_BASE_LIN | |
563 | HEADER_FMT_24BITS | HEADER_FMT_INTEL; | |
e12229b4 MB |
564 | break; |
565 | case SNDRV_PCM_FORMAT_S24_3BE: | |
566 | header = HEADER_FMT_BASE_LIN | HEADER_FMT_24BITS; | |
567 | break; | |
568 | case SNDRV_PCM_FORMAT_FLOAT_LE: | |
569 | header = HEADER_FMT_BASE_FLOAT | HEADER_FMT_INTEL; | |
570 | break; | |
571 | default: | |
f48a6df2 TI |
572 | dev_err(chip->card->dev, |
573 | "error pcxhr_set_format() : unknown format\n"); | |
e12229b4 MB |
574 | return -EINVAL; |
575 | } | |
e12229b4 MB |
576 | |
577 | sample_rate = chip->mgr->sample_rate; | |
578 | if (sample_rate <= 32000 && sample_rate !=0) { | |
579 | if (sample_rate <= 11025) | |
580 | header |= HEADER_FMT_UPTO11; | |
581 | else | |
582 | header |= HEADER_FMT_UPTO32; | |
583 | } | |
584 | if (stream->channels == 1) | |
585 | header |= HEADER_FMT_MONO; | |
586 | ||
587 | is_capture = stream->pipe->is_capture; | |
588 | stream_num = is_capture ? 0 : stream->substream->number; | |
589 | ||
9d948d27 MB |
590 | pcxhr_init_rmh(&rmh, is_capture ? |
591 | CMD_FORMAT_STREAM_IN : CMD_FORMAT_STREAM_OUT); | |
592 | pcxhr_set_pipe_cmd_params(&rmh, is_capture, stream->pipe->first_audio, | |
593 | stream_num, 0); | |
594 | if (is_capture) { | |
595 | /* bug with old dsp versions: */ | |
596 | /* bit 12 also sets the format of the playback stream */ | |
597 | if (DSP_EXT_CMD_SET(chip->mgr)) | |
598 | rmh.cmd[0] |= 1<<10; | |
599 | else | |
600 | rmh.cmd[0] |= 1<<12; | |
601 | } | |
e12229b4 | 602 | rmh.cmd[1] = 0; |
9d948d27 MB |
603 | rmh.cmd_len = 2; |
604 | if (DSP_EXT_CMD_SET(chip->mgr)) { | |
605 | /* add channels and set bit 19 if channels>2 */ | |
606 | rmh.cmd[1] = stream->channels; | |
607 | if (!is_capture) { | |
608 | /* playback : add channel mask to command */ | |
609 | rmh.cmd[2] = (stream->channels == 1) ? 0x01 : 0x03; | |
610 | rmh.cmd_len = 3; | |
611 | } | |
612 | } | |
613 | rmh.cmd[rmh.cmd_len++] = header >> 8; | |
614 | rmh.cmd[rmh.cmd_len++] = (header & 0xff) << 16; | |
e12229b4 MB |
615 | err = pcxhr_send_msg(chip->mgr, &rmh); |
616 | if (err) | |
b59bb8ef TI |
617 | dev_err(chip->card->dev, |
618 | "ERROR pcxhr_set_format err=%x;\n", err); | |
e12229b4 MB |
619 | return err; |
620 | } | |
621 | ||
622 | static int pcxhr_update_r_buffer(struct pcxhr_stream *stream) | |
623 | { | |
624 | int err, is_capture, stream_num; | |
625 | struct pcxhr_rmh rmh; | |
626 | struct snd_pcm_substream *subs = stream->substream; | |
627 | struct snd_pcxhr *chip = snd_pcm_substream_chip(subs); | |
628 | ||
629 | is_capture = (subs->stream == SNDRV_PCM_STREAM_CAPTURE); | |
630 | stream_num = is_capture ? 0 : subs->number; | |
631 | ||
f48a6df2 TI |
632 | dev_dbg(chip->card->dev, |
633 | "pcxhr_update_r_buffer(pcm%c%d) : addr(%p) bytes(%zx) subs(%d)\n", | |
634 | is_capture ? 'c' : 'p', | |
635 | chip->chip_idx, (void *)(long)subs->runtime->dma_addr, | |
636 | subs->runtime->dma_bytes, subs->number); | |
e12229b4 MB |
637 | |
638 | pcxhr_init_rmh(&rmh, CMD_UPDATE_R_BUFFERS); | |
9d948d27 MB |
639 | pcxhr_set_pipe_cmd_params(&rmh, is_capture, stream->pipe->first_audio, |
640 | stream_num, 0); | |
e12229b4 | 641 | |
da3cec35 TI |
642 | /* max buffer size is 2 MByte */ |
643 | snd_BUG_ON(subs->runtime->dma_bytes >= 0x200000); | |
9d948d27 MB |
644 | /* size in bits */ |
645 | rmh.cmd[1] = subs->runtime->dma_bytes * 8; | |
646 | /* most significant byte */ | |
647 | rmh.cmd[2] = subs->runtime->dma_addr >> 24; | |
648 | /* this is a circular buffer */ | |
649 | rmh.cmd[2] |= 1<<19; | |
650 | /* least 3 significant bytes */ | |
651 | rmh.cmd[3] = subs->runtime->dma_addr & MASK_DSP_WORD; | |
e12229b4 MB |
652 | rmh.cmd_len = 4; |
653 | err = pcxhr_send_msg(chip->mgr, &rmh); | |
654 | if (err) | |
b59bb8ef | 655 | dev_err(chip->card->dev, |
9d948d27 | 656 | "ERROR CMD_UPDATE_R_BUFFERS err=%x;\n", err); |
e12229b4 MB |
657 | return err; |
658 | } | |
659 | ||
660 | ||
661 | #if 0 | |
9d948d27 MB |
662 | static int pcxhr_pipe_sample_count(struct pcxhr_stream *stream, |
663 | snd_pcm_uframes_t *sample_count) | |
e12229b4 MB |
664 | { |
665 | struct pcxhr_rmh rmh; | |
666 | int err; | |
667 | pcxhr_t *chip = snd_pcm_substream_chip(stream->substream); | |
668 | pcxhr_init_rmh(&rmh, CMD_PIPE_SAMPLE_COUNT); | |
669 | pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture, 0, 0, | |
670 | 1<<stream->pipe->first_audio); | |
671 | err = pcxhr_send_msg(chip->mgr, &rmh); | |
672 | if (err == 0) { | |
673 | *sample_count = ((snd_pcm_uframes_t)rmh.stat[0]) << 24; | |
674 | *sample_count += (snd_pcm_uframes_t)rmh.stat[1]; | |
675 | } | |
f48a6df2 | 676 | dev_dbg(chip->card->dev, "PIPE_SAMPLE_COUNT = %lx\n", *sample_count); |
e12229b4 MB |
677 | return err; |
678 | } | |
679 | #endif | |
680 | ||
681 | static inline int pcxhr_stream_scheduled_get_pipe(struct pcxhr_stream *stream, | |
682 | struct pcxhr_pipe **pipe) | |
683 | { | |
684 | if (stream->status == PCXHR_STREAM_STATUS_SCHEDULE_RUN) { | |
685 | *pipe = stream->pipe; | |
686 | return 1; | |
687 | } | |
688 | return 0; | |
689 | } | |
690 | ||
9bef72bd | 691 | static void pcxhr_start_linked_stream(struct pcxhr_mgr *mgr) |
e12229b4 | 692 | { |
e12229b4 MB |
693 | int i, j, err; |
694 | struct pcxhr_pipe *pipe; | |
695 | struct snd_pcxhr *chip; | |
e12229b4 MB |
696 | int capture_mask = 0; |
697 | int playback_mask = 0; | |
698 | ||
62cf872a | 699 | #ifdef CONFIG_SND_DEBUG_VERBOSE |
326f0480 AM |
700 | ktime_t start_time, stop_time, diff_time; |
701 | ||
702 | start_time = ktime_get(); | |
e12229b4 | 703 | #endif |
62932df8 | 704 | mutex_lock(&mgr->setup_mutex); |
e12229b4 MB |
705 | |
706 | /* check the pipes concerned and build pipe_array */ | |
707 | for (i = 0; i < mgr->num_cards; i++) { | |
708 | chip = mgr->chip[i]; | |
709 | for (j = 0; j < chip->nb_streams_capt; j++) { | |
710 | if (pcxhr_stream_scheduled_get_pipe(&chip->capture_stream[j], &pipe)) | |
711 | capture_mask |= (1 << pipe->first_audio); | |
712 | } | |
713 | for (j = 0; j < chip->nb_streams_play; j++) { | |
714 | if (pcxhr_stream_scheduled_get_pipe(&chip->playback_stream[j], &pipe)) { | |
715 | playback_mask |= (1 << pipe->first_audio); | |
9d948d27 MB |
716 | break; /* add only once, as all playback |
717 | * streams of one chip use the same pipe | |
e12229b4 MB |
718 | */ |
719 | } | |
720 | } | |
721 | } | |
722 | if (capture_mask == 0 && playback_mask == 0) { | |
62932df8 | 723 | mutex_unlock(&mgr->setup_mutex); |
9bef72bd | 724 | dev_err(&mgr->pci->dev, "pcxhr_start_linked_stream : no pipes\n"); |
e12229b4 MB |
725 | return; |
726 | } | |
727 | ||
9bef72bd | 728 | dev_dbg(&mgr->pci->dev, "pcxhr_start_linked_stream : " |
9d948d27 | 729 | "playback_mask=%x capture_mask=%x\n", |
e12229b4 MB |
730 | playback_mask, capture_mask); |
731 | ||
732 | /* synchronous stop of all the pipes concerned */ | |
733 | err = pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 0); | |
734 | if (err) { | |
62932df8 | 735 | mutex_unlock(&mgr->setup_mutex); |
9bef72bd | 736 | dev_err(&mgr->pci->dev, "pcxhr_start_linked_stream : " |
9d948d27 | 737 | "error stop pipes (P%x C%x)\n", |
e12229b4 MB |
738 | playback_mask, capture_mask); |
739 | return; | |
740 | } | |
741 | ||
9d948d27 | 742 | /* the dsp lost format and buffer info with the stop pipe */ |
e12229b4 MB |
743 | for (i = 0; i < mgr->num_cards; i++) { |
744 | struct pcxhr_stream *stream; | |
745 | chip = mgr->chip[i]; | |
746 | for (j = 0; j < chip->nb_streams_capt; j++) { | |
747 | stream = &chip->capture_stream[j]; | |
748 | if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) { | |
749 | err = pcxhr_set_format(stream); | |
750 | err = pcxhr_update_r_buffer(stream); | |
751 | } | |
752 | } | |
753 | for (j = 0; j < chip->nb_streams_play; j++) { | |
754 | stream = &chip->playback_stream[j]; | |
755 | if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) { | |
756 | err = pcxhr_set_format(stream); | |
757 | err = pcxhr_update_r_buffer(stream); | |
758 | } | |
759 | } | |
760 | } | |
761 | /* start all the streams */ | |
762 | for (i = 0; i < mgr->num_cards; i++) { | |
763 | struct pcxhr_stream *stream; | |
764 | chip = mgr->chip[i]; | |
765 | for (j = 0; j < chip->nb_streams_capt; j++) { | |
766 | stream = &chip->capture_stream[j]; | |
767 | if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) | |
f48a6df2 | 768 | err = pcxhr_set_stream_state(chip, stream); |
e12229b4 MB |
769 | } |
770 | for (j = 0; j < chip->nb_streams_play; j++) { | |
771 | stream = &chip->playback_stream[j]; | |
772 | if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) | |
f48a6df2 | 773 | err = pcxhr_set_stream_state(chip, stream); |
e12229b4 MB |
774 | } |
775 | } | |
776 | ||
777 | /* synchronous start of all the pipes concerned */ | |
778 | err = pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 1); | |
779 | if (err) { | |
62932df8 | 780 | mutex_unlock(&mgr->setup_mutex); |
9bef72bd | 781 | dev_err(&mgr->pci->dev, "pcxhr_start_linked_stream : " |
9d948d27 | 782 | "error start pipes (P%x C%x)\n", |
e12229b4 MB |
783 | playback_mask, capture_mask); |
784 | return; | |
785 | } | |
786 | ||
9d948d27 MB |
787 | /* put the streams into the running state now |
788 | * (increment pointer by interrupt) | |
789 | */ | |
9bef72bd | 790 | mutex_lock(&mgr->lock); |
e12229b4 MB |
791 | for ( i =0; i < mgr->num_cards; i++) { |
792 | struct pcxhr_stream *stream; | |
793 | chip = mgr->chip[i]; | |
794 | for(j = 0; j < chip->nb_streams_capt; j++) { | |
795 | stream = &chip->capture_stream[j]; | |
796 | if(stream->status == PCXHR_STREAM_STATUS_STARTED) | |
797 | stream->status = PCXHR_STREAM_STATUS_RUNNING; | |
798 | } | |
799 | for (j = 0; j < chip->nb_streams_play; j++) { | |
800 | stream = &chip->playback_stream[j]; | |
801 | if (stream->status == PCXHR_STREAM_STATUS_STARTED) { | |
802 | /* playback will already have advanced ! */ | |
9d948d27 | 803 | stream->timer_period_frag += mgr->granularity; |
e12229b4 MB |
804 | stream->status = PCXHR_STREAM_STATUS_RUNNING; |
805 | } | |
806 | } | |
807 | } | |
9bef72bd | 808 | mutex_unlock(&mgr->lock); |
e12229b4 | 809 | |
62932df8 | 810 | mutex_unlock(&mgr->setup_mutex); |
e12229b4 | 811 | |
62cf872a | 812 | #ifdef CONFIG_SND_DEBUG_VERBOSE |
326f0480 AM |
813 | stop_time = ktime_get(); |
814 | diff_time = ktime_sub(stop_time, start_time); | |
9bef72bd | 815 | dev_dbg(&mgr->pci->dev, "***TRIGGER START*** TIME = %ld (err = %x)\n", |
326f0480 | 816 | (long)(ktime_to_ns(diff_time)), err); |
e12229b4 MB |
817 | #endif |
818 | } | |
819 | ||
820 | ||
821 | /* | |
822 | * trigger callback | |
823 | */ | |
824 | static int pcxhr_trigger(struct snd_pcm_substream *subs, int cmd) | |
825 | { | |
826 | struct pcxhr_stream *stream; | |
e12229b4 | 827 | struct snd_pcm_substream *s; |
f48a6df2 | 828 | struct snd_pcxhr *chip = snd_pcm_substream_chip(subs); |
e12229b4 MB |
829 | |
830 | switch (cmd) { | |
831 | case SNDRV_PCM_TRIGGER_START: | |
f48a6df2 | 832 | dev_dbg(chip->card->dev, "SNDRV_PCM_TRIGGER_START\n"); |
b07a14a5 | 833 | if (snd_pcm_stream_linked(subs)) { |
b07a14a5 | 834 | snd_pcm_group_for_each_entry(s, subs) { |
29998d24 CL |
835 | if (snd_pcm_substream_chip(s) != chip) |
836 | continue; | |
b07a14a5 TI |
837 | stream = s->runtime->private_data; |
838 | stream->status = | |
839 | PCXHR_STREAM_STATUS_SCHEDULE_RUN; | |
840 | snd_pcm_trigger_done(s, subs); | |
841 | } | |
9bef72bd | 842 | pcxhr_start_linked_stream(chip->mgr); |
b07a14a5 TI |
843 | } else { |
844 | stream = subs->runtime->private_data; | |
f48a6df2 | 845 | dev_dbg(chip->card->dev, "Only one Substream %c %d\n", |
e12229b4 MB |
846 | stream->pipe->is_capture ? 'C' : 'P', |
847 | stream->pipe->first_audio); | |
848 | if (pcxhr_set_format(stream)) | |
849 | return -EINVAL; | |
850 | if (pcxhr_update_r_buffer(stream)) | |
851 | return -EINVAL; | |
852 | ||
768d8c7d | 853 | stream->status = PCXHR_STREAM_STATUS_SCHEDULE_RUN; |
f48a6df2 | 854 | if (pcxhr_set_stream_state(chip, stream)) |
e12229b4 MB |
855 | return -EINVAL; |
856 | stream->status = PCXHR_STREAM_STATUS_RUNNING; | |
e12229b4 MB |
857 | } |
858 | break; | |
859 | case SNDRV_PCM_TRIGGER_STOP: | |
f48a6df2 | 860 | dev_dbg(chip->card->dev, "SNDRV_PCM_TRIGGER_STOP\n"); |
ef991b95 | 861 | snd_pcm_group_for_each_entry(s, subs) { |
e12229b4 MB |
862 | stream = s->runtime->private_data; |
863 | stream->status = PCXHR_STREAM_STATUS_SCHEDULE_STOP; | |
f48a6df2 | 864 | if (pcxhr_set_stream_state(chip, stream)) |
e12229b4 MB |
865 | return -EINVAL; |
866 | snd_pcm_trigger_done(s, subs); | |
867 | } | |
868 | break; | |
869 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
870 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
871 | /* TODO */ | |
872 | default: | |
873 | return -EINVAL; | |
874 | } | |
875 | return 0; | |
876 | } | |
877 | ||
878 | ||
879 | static int pcxhr_hardware_timer(struct pcxhr_mgr *mgr, int start) | |
880 | { | |
881 | struct pcxhr_rmh rmh; | |
882 | int err; | |
883 | ||
884 | pcxhr_init_rmh(&rmh, CMD_SET_TIMER_INTERRUPT); | |
885 | if (start) { | |
9d948d27 MB |
886 | /* last dsp time invalid */ |
887 | mgr->dsp_time_last = PCXHR_DSP_TIME_INVALID; | |
888 | rmh.cmd[0] |= mgr->granularity; | |
e12229b4 MB |
889 | } |
890 | err = pcxhr_send_msg(mgr, &rmh); | |
891 | if (err < 0) | |
b59bb8ef | 892 | dev_err(&mgr->pci->dev, "error pcxhr_hardware_timer err(%x)\n", |
9d948d27 | 893 | err); |
e12229b4 MB |
894 | return err; |
895 | } | |
896 | ||
897 | /* | |
898 | * prepare callback for all pcms | |
899 | */ | |
900 | static int pcxhr_prepare(struct snd_pcm_substream *subs) | |
901 | { | |
902 | struct snd_pcxhr *chip = snd_pcm_substream_chip(subs); | |
903 | struct pcxhr_mgr *mgr = chip->mgr; | |
e12229b4 MB |
904 | int err = 0; |
905 | ||
b59bb8ef TI |
906 | dev_dbg(chip->card->dev, |
907 | "pcxhr_prepare : period_size(%lx) periods(%x) buffer_size(%lx)\n", | |
e12229b4 MB |
908 | subs->runtime->period_size, subs->runtime->periods, |
909 | subs->runtime->buffer_size); | |
910 | ||
62932df8 | 911 | mutex_lock(&mgr->setup_mutex); |
e12229b4 MB |
912 | |
913 | do { | |
e12229b4 | 914 | /* only the first stream can choose the sample rate */ |
e12229b4 | 915 | /* set the clock only once (first stream) */ |
8937fd88 | 916 | if (mgr->sample_rate != subs->runtime->rate) { |
e12229b4 MB |
917 | err = pcxhr_set_clock(mgr, subs->runtime->rate); |
918 | if (err) | |
919 | break; | |
8937fd88 TI |
920 | if (mgr->sample_rate == 0) |
921 | /* start the DSP-timer */ | |
922 | err = pcxhr_hardware_timer(mgr, 1); | |
e12229b4 | 923 | mgr->sample_rate = subs->runtime->rate; |
e12229b4 MB |
924 | } |
925 | } while(0); /* do only once (so we can use break instead of goto) */ | |
926 | ||
62932df8 | 927 | mutex_unlock(&mgr->setup_mutex); |
e12229b4 MB |
928 | |
929 | return err; | |
930 | } | |
931 | ||
932 | ||
933 | /* | |
934 | * HW_PARAMS callback for all pcms | |
935 | */ | |
936 | static int pcxhr_hw_params(struct snd_pcm_substream *subs, | |
937 | struct snd_pcm_hw_params *hw) | |
938 | { | |
939 | struct snd_pcxhr *chip = snd_pcm_substream_chip(subs); | |
940 | struct pcxhr_mgr *mgr = chip->mgr; | |
941 | struct pcxhr_stream *stream = subs->runtime->private_data; | |
e12229b4 | 942 | |
62932df8 | 943 | mutex_lock(&mgr->setup_mutex); |
e12229b4 | 944 | |
dd21bf51 TI |
945 | /* set up channels */ |
946 | stream->channels = params_channels(hw); | |
947 | /* set up format for the stream */ | |
948 | stream->format = params_format(hw); | |
e12229b4 | 949 | |
62932df8 | 950 | mutex_unlock(&mgr->setup_mutex); |
e12229b4 | 951 | |
e12229b4 MB |
952 | return 0; |
953 | } | |
954 | ||
955 | ||
956 | /* | |
957 | * CONFIGURATION SPACE for all pcms, mono pcm must update channels_max | |
958 | */ | |
ecc6a044 | 959 | static const struct snd_pcm_hardware pcxhr_caps = |
e12229b4 | 960 | { |
9d948d27 MB |
961 | .info = (SNDRV_PCM_INFO_MMAP | |
962 | SNDRV_PCM_INFO_INTERLEAVED | | |
963 | SNDRV_PCM_INFO_MMAP_VALID | | |
964 | SNDRV_PCM_INFO_SYNC_START), | |
965 | .formats = (SNDRV_PCM_FMTBIT_U8 | | |
966 | SNDRV_PCM_FMTBIT_S16_LE | | |
967 | SNDRV_PCM_FMTBIT_S16_BE | | |
968 | SNDRV_PCM_FMTBIT_S24_3LE | | |
969 | SNDRV_PCM_FMTBIT_S24_3BE | | |
970 | SNDRV_PCM_FMTBIT_FLOAT_LE), | |
971 | .rates = (SNDRV_PCM_RATE_CONTINUOUS | | |
972 | SNDRV_PCM_RATE_8000_192000), | |
e12229b4 MB |
973 | .rate_min = 8000, |
974 | .rate_max = 192000, | |
975 | .channels_min = 1, | |
976 | .channels_max = 2, | |
977 | .buffer_bytes_max = (32*1024), | |
978 | /* 1 byte == 1 frame U8 mono (PCXHR_GRANULARITY is frames!) */ | |
979 | .period_bytes_min = (2*PCXHR_GRANULARITY), | |
980 | .period_bytes_max = (16*1024), | |
981 | .periods_min = 2, | |
982 | .periods_max = (32*1024/PCXHR_GRANULARITY), | |
983 | }; | |
984 | ||
985 | ||
986 | static int pcxhr_open(struct snd_pcm_substream *subs) | |
987 | { | |
988 | struct snd_pcxhr *chip = snd_pcm_substream_chip(subs); | |
989 | struct pcxhr_mgr *mgr = chip->mgr; | |
990 | struct snd_pcm_runtime *runtime = subs->runtime; | |
991 | struct pcxhr_stream *stream; | |
9d948d27 | 992 | int err; |
e12229b4 | 993 | |
62932df8 | 994 | mutex_lock(&mgr->setup_mutex); |
e12229b4 MB |
995 | |
996 | /* copy the struct snd_pcm_hardware struct */ | |
997 | runtime->hw = pcxhr_caps; | |
998 | ||
999 | if( subs->stream == SNDRV_PCM_STREAM_PLAYBACK ) { | |
b59bb8ef | 1000 | dev_dbg(chip->card->dev, "pcxhr_open playback chip%d subs%d\n", |
e12229b4 | 1001 | chip->chip_idx, subs->number); |
e12229b4 MB |
1002 | stream = &chip->playback_stream[subs->number]; |
1003 | } else { | |
b59bb8ef | 1004 | dev_dbg(chip->card->dev, "pcxhr_open capture chip%d subs%d\n", |
e12229b4 | 1005 | chip->chip_idx, subs->number); |
e12229b4 MB |
1006 | if (mgr->mono_capture) |
1007 | runtime->hw.channels_max = 1; | |
1008 | else | |
1009 | runtime->hw.channels_min = 2; | |
1010 | stream = &chip->capture_stream[subs->number]; | |
1011 | } | |
1012 | if (stream->status != PCXHR_STREAM_STATUS_FREE){ | |
1013 | /* streams in use */ | |
b59bb8ef | 1014 | dev_err(chip->card->dev, "pcxhr_open chip%d subs%d in use\n", |
e12229b4 | 1015 | chip->chip_idx, subs->number); |
62932df8 | 1016 | mutex_unlock(&mgr->setup_mutex); |
e12229b4 MB |
1017 | return -EBUSY; |
1018 | } | |
1019 | ||
9d948d27 MB |
1020 | /* float format support is in some cases buggy on stereo cards */ |
1021 | if (mgr->is_hr_stereo) | |
1022 | runtime->hw.formats &= ~SNDRV_PCM_FMTBIT_FLOAT_LE; | |
1023 | ||
1024 | /* buffer-size should better be multiple of period-size */ | |
1025 | err = snd_pcm_hw_constraint_integer(runtime, | |
1026 | SNDRV_PCM_HW_PARAM_PERIODS); | |
1027 | if (err < 0) { | |
1028 | mutex_unlock(&mgr->setup_mutex); | |
1029 | return err; | |
1030 | } | |
1031 | ||
e12229b4 MB |
1032 | /* if a sample rate is already used or fixed by external clock, |
1033 | * the stream cannot change | |
1034 | */ | |
1035 | if (mgr->sample_rate) | |
1036 | runtime->hw.rate_min = runtime->hw.rate_max = mgr->sample_rate; | |
1037 | else { | |
1038 | if (mgr->use_clock_type != PCXHR_CLOCK_TYPE_INTERNAL) { | |
1039 | int external_rate; | |
1040 | if (pcxhr_get_external_clock(mgr, mgr->use_clock_type, | |
1041 | &external_rate) || | |
1042 | external_rate == 0) { | |
1043 | /* cannot detect the external clock rate */ | |
62932df8 | 1044 | mutex_unlock(&mgr->setup_mutex); |
e12229b4 MB |
1045 | return -EBUSY; |
1046 | } | |
9d948d27 MB |
1047 | runtime->hw.rate_min = external_rate; |
1048 | runtime->hw.rate_max = external_rate; | |
e12229b4 MB |
1049 | } |
1050 | } | |
1051 | ||
1052 | stream->status = PCXHR_STREAM_STATUS_OPEN; | |
1053 | stream->substream = subs; | |
1054 | stream->channels = 0; /* not configured yet */ | |
1055 | ||
1056 | runtime->private_data = stream; | |
1057 | ||
9d948d27 MB |
1058 | /* better get a divisor of granularity values (96 or 192) */ |
1059 | snd_pcm_hw_constraint_step(runtime, 0, | |
1060 | SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 32); | |
1061 | snd_pcm_hw_constraint_step(runtime, 0, | |
1062 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 32); | |
b83f346b CL |
1063 | snd_pcm_set_sync(subs); |
1064 | ||
e12229b4 MB |
1065 | mgr->ref_count_rate++; |
1066 | ||
62932df8 | 1067 | mutex_unlock(&mgr->setup_mutex); |
e12229b4 MB |
1068 | return 0; |
1069 | } | |
1070 | ||
1071 | ||
1072 | static int pcxhr_close(struct snd_pcm_substream *subs) | |
1073 | { | |
1074 | struct snd_pcxhr *chip = snd_pcm_substream_chip(subs); | |
1075 | struct pcxhr_mgr *mgr = chip->mgr; | |
1076 | struct pcxhr_stream *stream = subs->runtime->private_data; | |
1077 | ||
62932df8 | 1078 | mutex_lock(&mgr->setup_mutex); |
e12229b4 | 1079 | |
b59bb8ef | 1080 | dev_dbg(chip->card->dev, "pcxhr_close chip%d subs%d\n", |
9d948d27 | 1081 | chip->chip_idx, subs->number); |
e12229b4 MB |
1082 | |
1083 | /* sample rate released */ | |
1084 | if (--mgr->ref_count_rate == 0) { | |
9d948d27 | 1085 | mgr->sample_rate = 0; /* the sample rate is no more locked */ |
e12229b4 MB |
1086 | pcxhr_hardware_timer(mgr, 0); /* stop the DSP-timer */ |
1087 | } | |
1088 | ||
1089 | stream->status = PCXHR_STREAM_STATUS_FREE; | |
1090 | stream->substream = NULL; | |
1091 | ||
62932df8 | 1092 | mutex_unlock(&mgr->setup_mutex); |
e12229b4 MB |
1093 | |
1094 | return 0; | |
1095 | } | |
1096 | ||
1097 | ||
1098 | static snd_pcm_uframes_t pcxhr_stream_pointer(struct snd_pcm_substream *subs) | |
1099 | { | |
e12229b4 MB |
1100 | u_int32_t timer_period_frag; |
1101 | int timer_buf_periods; | |
1102 | struct snd_pcxhr *chip = snd_pcm_substream_chip(subs); | |
1103 | struct snd_pcm_runtime *runtime = subs->runtime; | |
1104 | struct pcxhr_stream *stream = runtime->private_data; | |
1105 | ||
9bef72bd | 1106 | mutex_lock(&chip->mgr->lock); |
e12229b4 MB |
1107 | |
1108 | /* get the period fragment and the nb of periods in the buffer */ | |
1109 | timer_period_frag = stream->timer_period_frag; | |
1110 | timer_buf_periods = stream->timer_buf_periods; | |
1111 | ||
9bef72bd | 1112 | mutex_unlock(&chip->mgr->lock); |
e12229b4 MB |
1113 | |
1114 | return (snd_pcm_uframes_t)((timer_buf_periods * runtime->period_size) + | |
1115 | timer_period_frag); | |
1116 | } | |
1117 | ||
1118 | ||
6769e988 | 1119 | static const struct snd_pcm_ops pcxhr_ops = { |
e12229b4 MB |
1120 | .open = pcxhr_open, |
1121 | .close = pcxhr_close, | |
e12229b4 MB |
1122 | .prepare = pcxhr_prepare, |
1123 | .hw_params = pcxhr_hw_params, | |
e12229b4 MB |
1124 | .trigger = pcxhr_trigger, |
1125 | .pointer = pcxhr_stream_pointer, | |
1126 | }; | |
1127 | ||
1128 | /* | |
1129 | */ | |
1130 | int pcxhr_create_pcm(struct snd_pcxhr *chip) | |
1131 | { | |
1132 | int err; | |
1133 | struct snd_pcm *pcm; | |
1134 | char name[32]; | |
1135 | ||
50517352 | 1136 | snprintf(name, sizeof(name), "pcxhr %d", chip->chip_idx); |
4327ad25 TI |
1137 | err = snd_pcm_new(chip->card, name, 0, |
1138 | chip->nb_streams_play, | |
1139 | chip->nb_streams_capt, &pcm); | |
1140 | if (err < 0) { | |
b59bb8ef | 1141 | dev_err(chip->card->dev, "cannot create pcm %s\n", name); |
e12229b4 MB |
1142 | return err; |
1143 | } | |
1144 | pcm->private_data = chip; | |
1145 | ||
1146 | if (chip->nb_streams_play) | |
1147 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &pcxhr_ops); | |
1148 | if (chip->nb_streams_capt) | |
1149 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &pcxhr_ops); | |
1150 | ||
1151 | pcm->info_flags = 0; | |
9bef72bd | 1152 | pcm->nonatomic = true; |
e12229b4 MB |
1153 | strcpy(pcm->name, name); |
1154 | ||
dd21bf51 TI |
1155 | snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, |
1156 | &chip->mgr->pci->dev, | |
1157 | 32*1024, 32*1024); | |
e12229b4 MB |
1158 | chip->pcm = pcm; |
1159 | return 0; | |
1160 | } | |
1161 | ||
1162 | static int pcxhr_chip_free(struct snd_pcxhr *chip) | |
1163 | { | |
1164 | kfree(chip); | |
1165 | return 0; | |
1166 | } | |
1167 | ||
1168 | static int pcxhr_chip_dev_free(struct snd_device *device) | |
1169 | { | |
1170 | struct snd_pcxhr *chip = device->device_data; | |
1171 | return pcxhr_chip_free(chip); | |
1172 | } | |
1173 | ||
1174 | ||
1175 | /* | |
1176 | */ | |
e23e7a14 BP |
1177 | static int pcxhr_create(struct pcxhr_mgr *mgr, |
1178 | struct snd_card *card, int idx) | |
e12229b4 MB |
1179 | { |
1180 | int err; | |
1181 | struct snd_pcxhr *chip; | |
efb0ad25 | 1182 | static const struct snd_device_ops ops = { |
e12229b4 MB |
1183 | .dev_free = pcxhr_chip_dev_free, |
1184 | }; | |
1185 | ||
73f6a12e | 1186 | chip = kzalloc(sizeof(*chip), GFP_KERNEL); |
c38774d8 | 1187 | if (!chip) |
e12229b4 | 1188 | return -ENOMEM; |
e12229b4 MB |
1189 | |
1190 | chip->card = card; | |
1191 | chip->chip_idx = idx; | |
1192 | chip->mgr = mgr; | |
271213ef | 1193 | card->sync_irq = mgr->irq; |
e12229b4 MB |
1194 | |
1195 | if (idx < mgr->playback_chips) | |
1196 | /* stereo or mono streams */ | |
1197 | chip->nb_streams_play = PCXHR_PLAYBACK_STREAMS; | |
1198 | ||
1199 | if (idx < mgr->capture_chips) { | |
1200 | if (mgr->mono_capture) | |
9d948d27 | 1201 | chip->nb_streams_capt = 2; /* 2 mono streams */ |
e12229b4 MB |
1202 | else |
1203 | chip->nb_streams_capt = 1; /* or 1 stereo stream */ | |
1204 | } | |
1205 | ||
4327ad25 TI |
1206 | err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); |
1207 | if (err < 0) { | |
e12229b4 MB |
1208 | pcxhr_chip_free(chip); |
1209 | return err; | |
1210 | } | |
1211 | ||
73f6a12e | 1212 | mgr->chip[idx] = chip; |
e12229b4 MB |
1213 | |
1214 | return 0; | |
1215 | } | |
1216 | ||
1217 | /* proc interface */ | |
9d948d27 MB |
1218 | static void pcxhr_proc_info(struct snd_info_entry *entry, |
1219 | struct snd_info_buffer *buffer) | |
e12229b4 MB |
1220 | { |
1221 | struct snd_pcxhr *chip = entry->private_data; | |
1222 | struct pcxhr_mgr *mgr = chip->mgr; | |
1223 | ||
50517352 | 1224 | snd_iprintf(buffer, "\n%s\n", mgr->name); |
e12229b4 MB |
1225 | |
1226 | /* stats available when embedded DSP is running */ | |
1227 | if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) { | |
1228 | struct pcxhr_rmh rmh; | |
1229 | short ver_maj = (mgr->dsp_version >> 16) & 0xff; | |
1230 | short ver_min = (mgr->dsp_version >> 8) & 0xff; | |
1231 | short ver_build = mgr->dsp_version & 0xff; | |
9d948d27 MB |
1232 | snd_iprintf(buffer, "module version %s\n", |
1233 | PCXHR_DRIVER_VERSION_STRING); | |
1234 | snd_iprintf(buffer, "dsp version %d.%d.%d\n", | |
1235 | ver_maj, ver_min, ver_build); | |
e12229b4 MB |
1236 | if (mgr->board_has_analog) |
1237 | snd_iprintf(buffer, "analog io available\n"); | |
1238 | else | |
1239 | snd_iprintf(buffer, "digital only board\n"); | |
1240 | ||
1241 | /* calc cpu load of the dsp */ | |
1242 | pcxhr_init_rmh(&rmh, CMD_GET_DSP_RESOURCES); | |
1243 | if( ! pcxhr_send_msg(mgr, &rmh) ) { | |
1244 | int cur = rmh.stat[0]; | |
1245 | int ref = rmh.stat[1]; | |
1246 | if (ref > 0) { | |
1247 | if (mgr->sample_rate_real != 0 && | |
1248 | mgr->sample_rate_real != 48000) { | |
9d948d27 MB |
1249 | ref = (ref * 48000) / |
1250 | mgr->sample_rate_real; | |
1251 | if (mgr->sample_rate_real >= | |
1252 | PCXHR_IRQ_TIMER_FREQ) | |
e12229b4 MB |
1253 | ref *= 2; |
1254 | } | |
1255 | cur = 100 - (100 * cur) / ref; | |
1256 | snd_iprintf(buffer, "cpu load %d%%\n", cur); | |
9d948d27 | 1257 | snd_iprintf(buffer, "buffer pool %d/%d\n", |
e12229b4 MB |
1258 | rmh.stat[2], rmh.stat[3]); |
1259 | } | |
1260 | } | |
9d948d27 MB |
1261 | snd_iprintf(buffer, "dma granularity : %d\n", |
1262 | mgr->granularity); | |
1263 | snd_iprintf(buffer, "dsp time errors : %d\n", | |
1264 | mgr->dsp_time_err); | |
e12229b4 MB |
1265 | snd_iprintf(buffer, "dsp async pipe xrun errors : %d\n", |
1266 | mgr->async_err_pipe_xrun); | |
1267 | snd_iprintf(buffer, "dsp async stream xrun errors : %d\n", | |
1268 | mgr->async_err_stream_xrun); | |
1269 | snd_iprintf(buffer, "dsp async last other error : %x\n", | |
1270 | mgr->async_err_other_last); | |
1271 | /* debug zone dsp */ | |
1272 | rmh.cmd[0] = 0x4200 + PCXHR_SIZE_MAX_STATUS; | |
1273 | rmh.cmd_len = 1; | |
1274 | rmh.stat_len = PCXHR_SIZE_MAX_STATUS; | |
1275 | rmh.dsp_stat = 0; | |
1276 | rmh.cmd_idx = CMD_LAST_INDEX; | |
1277 | if( ! pcxhr_send_msg(mgr, &rmh) ) { | |
1278 | int i; | |
9d948d27 MB |
1279 | if (rmh.stat_len > 8) |
1280 | rmh.stat_len = 8; | |
e12229b4 | 1281 | for (i = 0; i < rmh.stat_len; i++) |
9d948d27 MB |
1282 | snd_iprintf(buffer, "debug[%02d] = %06x\n", |
1283 | i, rmh.stat[i]); | |
e12229b4 MB |
1284 | } |
1285 | } else | |
1286 | snd_iprintf(buffer, "no firmware loaded\n"); | |
1287 | snd_iprintf(buffer, "\n"); | |
1288 | } | |
9d948d27 MB |
1289 | static void pcxhr_proc_sync(struct snd_info_entry *entry, |
1290 | struct snd_info_buffer *buffer) | |
e12229b4 MB |
1291 | { |
1292 | struct snd_pcxhr *chip = entry->private_data; | |
1293 | struct pcxhr_mgr *mgr = chip->mgr; | |
9d948d27 MB |
1294 | static const char *textsHR22[3] = { |
1295 | "Internal", "AES Sync", "AES 1" | |
1296 | }; | |
1297 | static const char *textsPCXHR[7] = { | |
1298 | "Internal", "Word", "AES Sync", | |
1299 | "AES 1", "AES 2", "AES 3", "AES 4" | |
e12229b4 | 1300 | }; |
9d948d27 MB |
1301 | const char **texts; |
1302 | int max_clock; | |
1303 | if (mgr->is_hr_stereo) { | |
1304 | texts = textsHR22; | |
1305 | max_clock = HR22_CLOCK_TYPE_MAX; | |
1306 | } else { | |
1307 | texts = textsPCXHR; | |
1308 | max_clock = PCXHR_CLOCK_TYPE_MAX; | |
1309 | } | |
e12229b4 | 1310 | |
50517352 | 1311 | snd_iprintf(buffer, "\n%s\n", mgr->name); |
9d948d27 MB |
1312 | snd_iprintf(buffer, "Current Sample Clock\t: %s\n", |
1313 | texts[mgr->cur_clock_type]); | |
1314 | snd_iprintf(buffer, "Current Sample Rate\t= %d\n", | |
1315 | mgr->sample_rate_real); | |
e12229b4 MB |
1316 | /* commands available when embedded DSP is running */ |
1317 | if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) { | |
1318 | int i, err, sample_rate; | |
9d948d27 | 1319 | for (i = 1; i <= max_clock; i++) { |
e12229b4 MB |
1320 | err = pcxhr_get_external_clock(mgr, i, &sample_rate); |
1321 | if (err) | |
1322 | break; | |
9d948d27 MB |
1323 | snd_iprintf(buffer, "%s Clock\t\t= %d\n", |
1324 | texts[i], sample_rate); | |
e12229b4 MB |
1325 | } |
1326 | } else | |
1327 | snd_iprintf(buffer, "no firmware loaded\n"); | |
1328 | snd_iprintf(buffer, "\n"); | |
1329 | } | |
1330 | ||
55aef450 MB |
1331 | static void pcxhr_proc_gpio_read(struct snd_info_entry *entry, |
1332 | struct snd_info_buffer *buffer) | |
1333 | { | |
1334 | struct snd_pcxhr *chip = entry->private_data; | |
1335 | struct pcxhr_mgr *mgr = chip->mgr; | |
1336 | /* commands available when embedded DSP is running */ | |
1337 | if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) { | |
1338 | /* gpio ports on stereo boards only available */ | |
1339 | int value = 0; | |
1340 | hr222_read_gpio(mgr, 1, &value); /* GPI */ | |
1341 | snd_iprintf(buffer, "GPI: 0x%x\n", value); | |
1342 | hr222_read_gpio(mgr, 0, &value); /* GP0 */ | |
1343 | snd_iprintf(buffer, "GPO: 0x%x\n", value); | |
1344 | } else | |
1345 | snd_iprintf(buffer, "no firmware loaded\n"); | |
1346 | snd_iprintf(buffer, "\n"); | |
1347 | } | |
1348 | static void pcxhr_proc_gpo_write(struct snd_info_entry *entry, | |
1349 | struct snd_info_buffer *buffer) | |
1350 | { | |
1351 | struct snd_pcxhr *chip = entry->private_data; | |
1352 | struct pcxhr_mgr *mgr = chip->mgr; | |
1353 | char line[64]; | |
1354 | int value; | |
1355 | /* commands available when embedded DSP is running */ | |
1356 | if (!(mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX))) | |
1357 | return; | |
1358 | while (!snd_info_get_line(buffer, line, sizeof(line))) { | |
1359 | if (sscanf(line, "GPO: 0x%x", &value) != 1) | |
1360 | continue; | |
1361 | hr222_write_gpo(mgr, value); /* GP0 */ | |
1362 | } | |
1363 | } | |
1364 | ||
fdfbaf69 MB |
1365 | /* Access to the results of the CMD_GET_TIME_CODE RMH */ |
1366 | #define TIME_CODE_VALID_MASK 0x00800000 | |
1367 | #define TIME_CODE_NEW_MASK 0x00400000 | |
1368 | #define TIME_CODE_BACK_MASK 0x00200000 | |
1369 | #define TIME_CODE_WAIT_MASK 0x00100000 | |
1370 | ||
1371 | /* Values for the CMD_MANAGE_SIGNAL RMH */ | |
1372 | #define MANAGE_SIGNAL_TIME_CODE 0x01 | |
1373 | #define MANAGE_SIGNAL_MIDI 0x02 | |
1374 | ||
1375 | /* linear time code read proc*/ | |
1376 | static void pcxhr_proc_ltc(struct snd_info_entry *entry, | |
1377 | struct snd_info_buffer *buffer) | |
1378 | { | |
1379 | struct snd_pcxhr *chip = entry->private_data; | |
1380 | struct pcxhr_mgr *mgr = chip->mgr; | |
1381 | struct pcxhr_rmh rmh; | |
1382 | unsigned int ltcHrs, ltcMin, ltcSec, ltcFrm; | |
1383 | int err; | |
1384 | /* commands available when embedded DSP is running */ | |
1385 | if (!(mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX))) { | |
1386 | snd_iprintf(buffer, "no firmware loaded\n"); | |
1387 | return; | |
1388 | } | |
1389 | if (!mgr->capture_ltc) { | |
1390 | pcxhr_init_rmh(&rmh, CMD_MANAGE_SIGNAL); | |
1391 | rmh.cmd[0] |= MANAGE_SIGNAL_TIME_CODE; | |
1392 | err = pcxhr_send_msg(mgr, &rmh); | |
1393 | if (err) { | |
1394 | snd_iprintf(buffer, "ltc not activated (%d)\n", err); | |
1395 | return; | |
1396 | } | |
1397 | if (mgr->is_hr_stereo) | |
1398 | hr222_manage_timecode(mgr, 1); | |
1399 | else | |
1400 | pcxhr_write_io_num_reg_cont(mgr, REG_CONT_VALSMPTE, | |
1401 | REG_CONT_VALSMPTE, NULL); | |
1402 | mgr->capture_ltc = 1; | |
1403 | } | |
1404 | pcxhr_init_rmh(&rmh, CMD_GET_TIME_CODE); | |
1405 | err = pcxhr_send_msg(mgr, &rmh); | |
1406 | if (err) { | |
1407 | snd_iprintf(buffer, "ltc read error (err=%d)\n", err); | |
1408 | return ; | |
1409 | } | |
1410 | ltcHrs = 10*((rmh.stat[0] >> 8) & 0x3) + (rmh.stat[0] & 0xf); | |
1411 | ltcMin = 10*((rmh.stat[1] >> 16) & 0x7) + ((rmh.stat[1] >> 8) & 0xf); | |
1412 | ltcSec = 10*(rmh.stat[1] & 0x7) + ((rmh.stat[2] >> 16) & 0xf); | |
1413 | ltcFrm = 10*((rmh.stat[2] >> 8) & 0x3) + (rmh.stat[2] & 0xf); | |
1414 | ||
1415 | snd_iprintf(buffer, "timecode: %02u:%02u:%02u-%02u\n", | |
1416 | ltcHrs, ltcMin, ltcSec, ltcFrm); | |
1417 | snd_iprintf(buffer, "raw: 0x%04x%06x%06x\n", rmh.stat[0] & 0x00ffff, | |
1418 | rmh.stat[1] & 0xffffff, rmh.stat[2] & 0xffffff); | |
1419 | /*snd_iprintf(buffer, "dsp ref time: 0x%06x%06x\n", | |
1420 | rmh.stat[3] & 0xffffff, rmh.stat[4] & 0xffffff);*/ | |
1421 | if (!(rmh.stat[0] & TIME_CODE_VALID_MASK)) { | |
1422 | snd_iprintf(buffer, "warning: linear timecode not valid\n"); | |
1423 | } | |
1424 | } | |
1425 | ||
e23e7a14 | 1426 | static void pcxhr_proc_init(struct snd_pcxhr *chip) |
e12229b4 | 1427 | { |
47f2769b TI |
1428 | snd_card_ro_proc_new(chip->card, "info", chip, pcxhr_proc_info); |
1429 | snd_card_ro_proc_new(chip->card, "sync", chip, pcxhr_proc_sync); | |
55aef450 | 1430 | /* gpio available on stereo sound cards only */ |
47f2769b TI |
1431 | if (chip->mgr->is_hr_stereo) |
1432 | snd_card_rw_proc_new(chip->card, "gpio", chip, | |
1433 | pcxhr_proc_gpio_read, | |
1434 | pcxhr_proc_gpo_write); | |
1435 | snd_card_ro_proc_new(chip->card, "ltc", chip, pcxhr_proc_ltc); | |
e12229b4 MB |
1436 | } |
1437 | /* end of proc interface */ | |
1438 | ||
1439 | /* | |
1440 | * release all the cards assigned to a manager instance | |
1441 | */ | |
1442 | static int pcxhr_free(struct pcxhr_mgr *mgr) | |
1443 | { | |
1444 | unsigned int i; | |
1445 | ||
1446 | for (i = 0; i < mgr->num_cards; i++) { | |
1447 | if (mgr->chip[i]) | |
1448 | snd_card_free(mgr->chip[i]->card); | |
1449 | } | |
1450 | ||
1451 | /* reset board if some firmware was loaded */ | |
1452 | if(mgr->dsp_loaded) { | |
1453 | pcxhr_reset_board(mgr); | |
b59bb8ef | 1454 | dev_dbg(&mgr->pci->dev, "reset pcxhr !\n"); |
e12229b4 MB |
1455 | } |
1456 | ||
1457 | /* release irq */ | |
1458 | if (mgr->irq >= 0) | |
1459 | free_irq(mgr->irq, mgr); | |
1460 | ||
1461 | pci_release_regions(mgr->pci); | |
1462 | ||
1463 | /* free hostport purgebuffer */ | |
1464 | if (mgr->hostport.area) { | |
1465 | snd_dma_free_pages(&mgr->hostport); | |
1466 | mgr->hostport.area = NULL; | |
1467 | } | |
1468 | ||
1469 | kfree(mgr->prmh); | |
1470 | ||
1471 | pci_disable_device(mgr->pci); | |
1472 | kfree(mgr); | |
1473 | return 0; | |
1474 | } | |
1475 | ||
1476 | /* | |
1477 | * probe function - creates the card manager | |
1478 | */ | |
e23e7a14 BP |
1479 | static int pcxhr_probe(struct pci_dev *pci, |
1480 | const struct pci_device_id *pci_id) | |
e12229b4 MB |
1481 | { |
1482 | static int dev; | |
1483 | struct pcxhr_mgr *mgr; | |
1484 | unsigned int i; | |
1485 | int err; | |
1486 | size_t size; | |
1487 | char *card_name; | |
1488 | ||
1489 | if (dev >= SNDRV_CARDS) | |
1490 | return -ENODEV; | |
1491 | if (! enable[dev]) { | |
1492 | dev++; | |
1493 | return -ENOENT; | |
1494 | } | |
1495 | ||
1496 | /* enable PCI device */ | |
4327ad25 TI |
1497 | err = pci_enable_device(pci); |
1498 | if (err < 0) | |
e12229b4 MB |
1499 | return err; |
1500 | pci_set_master(pci); | |
1501 | ||
1502 | /* check if we can restrict PCI DMA transfers to 32 bits */ | |
412b979c | 1503 | if (dma_set_mask(&pci->dev, DMA_BIT_MASK(32)) < 0) { |
b59bb8ef TI |
1504 | dev_err(&pci->dev, |
1505 | "architecture does not support 32bit PCI busmaster DMA\n"); | |
e12229b4 MB |
1506 | pci_disable_device(pci); |
1507 | return -ENXIO; | |
1508 | } | |
1509 | ||
1510 | /* alloc card manager */ | |
1511 | mgr = kzalloc(sizeof(*mgr), GFP_KERNEL); | |
1512 | if (! mgr) { | |
1513 | pci_disable_device(pci); | |
1514 | return -ENOMEM; | |
1515 | } | |
1516 | ||
d6f35e3f JL |
1517 | if (snd_BUG_ON(pci_id->driver_data >= PCI_ID_LAST)) { |
1518 | kfree(mgr); | |
1519 | pci_disable_device(pci); | |
da3cec35 | 1520 | return -ENODEV; |
d6f35e3f | 1521 | } |
9d948d27 MB |
1522 | card_name = |
1523 | pcxhr_board_params[pci_id->driver_data].board_name; | |
1524 | mgr->playback_chips = | |
1525 | pcxhr_board_params[pci_id->driver_data].playback_chips; | |
1526 | mgr->capture_chips = | |
1527 | pcxhr_board_params[pci_id->driver_data].capture_chips; | |
1528 | mgr->fw_file_set = | |
1529 | pcxhr_board_params[pci_id->driver_data].fw_file_set; | |
1530 | mgr->firmware_num = | |
1531 | pcxhr_board_params[pci_id->driver_data].firmware_num; | |
e12229b4 | 1532 | mgr->mono_capture = mono[dev]; |
9d948d27 MB |
1533 | mgr->is_hr_stereo = (mgr->playback_chips == 1); |
1534 | mgr->board_has_aes1 = PCXHR_BOARD_HAS_AES1(mgr); | |
1535 | mgr->board_aes_in_192k = !PCXHR_BOARD_AESIN_NO_192K(mgr); | |
1536 | ||
1537 | if (mgr->is_hr_stereo) | |
1538 | mgr->granularity = PCXHR_GRANULARITY_HR22; | |
1539 | else | |
1540 | mgr->granularity = PCXHR_GRANULARITY; | |
e12229b4 MB |
1541 | |
1542 | /* resource assignment */ | |
4327ad25 TI |
1543 | err = pci_request_regions(pci, card_name); |
1544 | if (err < 0) { | |
e12229b4 MB |
1545 | kfree(mgr); |
1546 | pci_disable_device(pci); | |
1547 | return err; | |
1548 | } | |
1549 | for (i = 0; i < 3; i++) | |
1550 | mgr->port[i] = pci_resource_start(pci, i); | |
1551 | ||
1552 | mgr->pci = pci; | |
1553 | mgr->irq = -1; | |
1554 | ||
9bef72bd TI |
1555 | if (request_threaded_irq(pci->irq, pcxhr_interrupt, |
1556 | pcxhr_threaded_irq, IRQF_SHARED, | |
1557 | KBUILD_MODNAME, mgr)) { | |
b59bb8ef | 1558 | dev_err(&pci->dev, "unable to grab IRQ %d\n", pci->irq); |
e12229b4 MB |
1559 | pcxhr_free(mgr); |
1560 | return -EBUSY; | |
1561 | } | |
1562 | mgr->irq = pci->irq; | |
1563 | ||
50517352 AB |
1564 | snprintf(mgr->name, sizeof(mgr->name), |
1565 | "Digigram at 0x%lx & 0x%lx, 0x%lx irq %i", | |
1566 | mgr->port[0], mgr->port[1], mgr->port[2], mgr->irq); | |
e12229b4 | 1567 | |
9bef72bd TI |
1568 | /* ISR lock */ |
1569 | mutex_init(&mgr->lock); | |
1570 | mutex_init(&mgr->msg_lock); | |
e12229b4 MB |
1571 | |
1572 | /* init setup mutex*/ | |
62932df8 | 1573 | mutex_init(&mgr->setup_mutex); |
e12229b4 | 1574 | |
e12229b4 | 1575 | mgr->prmh = kmalloc(sizeof(*mgr->prmh) + |
9d948d27 MB |
1576 | sizeof(u32) * (PCXHR_SIZE_MAX_LONG_STATUS - |
1577 | PCXHR_SIZE_MAX_STATUS), | |
e12229b4 MB |
1578 | GFP_KERNEL); |
1579 | if (! mgr->prmh) { | |
1580 | pcxhr_free(mgr); | |
1581 | return -ENOMEM; | |
1582 | } | |
1583 | ||
1584 | for (i=0; i < PCXHR_MAX_CARDS; i++) { | |
1585 | struct snd_card *card; | |
1586 | char tmpid[16]; | |
1587 | int idx; | |
1588 | ||
1589 | if (i >= max(mgr->playback_chips, mgr->capture_chips)) | |
1590 | break; | |
1591 | mgr->num_cards++; | |
1592 | ||
1593 | if (index[dev] < 0) | |
1594 | idx = index[dev]; | |
1595 | else | |
1596 | idx = index[dev] + i; | |
1597 | ||
9d948d27 MB |
1598 | snprintf(tmpid, sizeof(tmpid), "%s-%d", |
1599 | id[dev] ? id[dev] : card_name, i); | |
60c5772b TI |
1600 | err = snd_card_new(&pci->dev, idx, tmpid, THIS_MODULE, |
1601 | 0, &card); | |
e12229b4 | 1602 | |
e58de7ba | 1603 | if (err < 0) { |
6e1d7a51 | 1604 | dev_err(&pci->dev, "cannot allocate the card %d\n", i); |
e12229b4 | 1605 | pcxhr_free(mgr); |
e58de7ba | 1606 | return err; |
e12229b4 MB |
1607 | } |
1608 | ||
1609 | strcpy(card->driver, DRIVER_NAME); | |
50517352 AB |
1610 | snprintf(card->shortname, sizeof(card->shortname), |
1611 | "Digigram [PCM #%d]", i); | |
1612 | snprintf(card->longname, sizeof(card->longname), | |
1613 | "%s [PCM #%d]", mgr->name, i); | |
e12229b4 | 1614 | |
4327ad25 TI |
1615 | err = pcxhr_create(mgr, card, i); |
1616 | if (err < 0) { | |
73f6a12e | 1617 | snd_card_free(card); |
e12229b4 MB |
1618 | pcxhr_free(mgr); |
1619 | return err; | |
1620 | } | |
1621 | ||
1622 | if (i == 0) | |
1623 | /* init proc interface only for chip0 */ | |
1624 | pcxhr_proc_init(mgr->chip[i]); | |
1625 | ||
4327ad25 TI |
1626 | err = snd_card_register(card); |
1627 | if (err < 0) { | |
e12229b4 MB |
1628 | pcxhr_free(mgr); |
1629 | return err; | |
1630 | } | |
1631 | } | |
1632 | ||
1633 | /* create hostport purgebuffer */ | |
1634 | size = PAGE_ALIGN(sizeof(struct pcxhr_hostport)); | |
6974f8ad | 1635 | if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev, |
e12229b4 MB |
1636 | size, &mgr->hostport) < 0) { |
1637 | pcxhr_free(mgr); | |
1638 | return -ENOMEM; | |
1639 | } | |
1640 | /* init purgebuffer */ | |
1641 | memset(mgr->hostport.area, 0, size); | |
1642 | ||
1643 | /* create a DSP loader */ | |
1644 | err = pcxhr_setup_firmware(mgr); | |
1645 | if (err < 0) { | |
1646 | pcxhr_free(mgr); | |
1647 | return err; | |
1648 | } | |
1649 | ||
1650 | pci_set_drvdata(pci, mgr); | |
1651 | dev++; | |
1652 | return 0; | |
1653 | } | |
1654 | ||
e23e7a14 | 1655 | static void pcxhr_remove(struct pci_dev *pci) |
e12229b4 MB |
1656 | { |
1657 | pcxhr_free(pci_get_drvdata(pci)); | |
e12229b4 MB |
1658 | } |
1659 | ||
e9f66d9b | 1660 | static struct pci_driver pcxhr_driver = { |
3733e424 | 1661 | .name = KBUILD_MODNAME, |
e12229b4 MB |
1662 | .id_table = pcxhr_ids, |
1663 | .probe = pcxhr_probe, | |
e23e7a14 | 1664 | .remove = pcxhr_remove, |
e12229b4 MB |
1665 | }; |
1666 | ||
e9f66d9b | 1667 | module_pci_driver(pcxhr_driver); |