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Merge branch 'fix/misc' into for-linus
[linux-2.6-block.git] / sound / pci / oxygen / oxygen_pcm.c
CommitLineData
d0ce9946
CL		 1/*
2 * C-Media CMI8788 driver - PCM code
3 *
4 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
5 *
6 *
7 * This driver is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License, version 2.
9 *
10 * This driver is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this driver; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
d0ce9946
CL		 20#include <linux/pci.h>
21#include <sound/control.h>
22#include <sound/core.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include "oxygen.h"
26
d55d7a1c
CL		 27/* most DMA channels have a 16-bit counter for 32-bit words */
28#define BUFFER_BYTES_MAX ((1 << 16) * 4)
29/* the multichannel DMA channel has a 24-bit counter */
30#define BUFFER_BYTES_MAX_MULTICH ((1 << 24) * 4)
31
32#define PERIOD_BYTES_MIN 64
33
34#define DEFAULT_BUFFER_BYTES (BUFFER_BYTES_MAX / 2)
35#define DEFAULT_BUFFER_BYTES_MULTICH (1024 * 1024)
36
c57cccc0
CL		 37static const struct snd_pcm_hardware oxygen_stereo_hardware = {
38 .info = SNDRV_PCM_INFO_MMAP |
39 SNDRV_PCM_INFO_MMAP_VALID |
40 SNDRV_PCM_INFO_INTERLEAVED |
41 SNDRV_PCM_INFO_PAUSE |
42 SNDRV_PCM_INFO_SYNC_START,
43 .formats = SNDRV_PCM_FMTBIT_S16_LE |
44 SNDRV_PCM_FMTBIT_S32_LE,
45 .rates = SNDRV_PCM_RATE_32000 |
46 SNDRV_PCM_RATE_44100 |
47 SNDRV_PCM_RATE_48000 |
48 SNDRV_PCM_RATE_64000 |
49 SNDRV_PCM_RATE_88200 |
50 SNDRV_PCM_RATE_96000 |
51 SNDRV_PCM_RATE_176400 |
52 SNDRV_PCM_RATE_192000,
53 .rate_min = 32000,
54 .rate_max = 192000,
55 .channels_min = 2,
56 .channels_max = 2,
d55d7a1c
CL		 57 .buffer_bytes_max = BUFFER_BYTES_MAX,
58 .period_bytes_min = PERIOD_BYTES_MIN,
59 .period_bytes_max = BUFFER_BYTES_MAX / 2,
c57cccc0 60 .periods_min = 2,
d55d7a1c 61 .periods_max = BUFFER_BYTES_MAX / PERIOD_BYTES_MIN,
c57cccc0
CL		 62};
63static const struct snd_pcm_hardware oxygen_multichannel_hardware = {
64 .info = SNDRV_PCM_INFO_MMAP |
65 SNDRV_PCM_INFO_MMAP_VALID |
66 SNDRV_PCM_INFO_INTERLEAVED |
67 SNDRV_PCM_INFO_PAUSE |
68 SNDRV_PCM_INFO_SYNC_START,
69 .formats = SNDRV_PCM_FMTBIT_S16_LE |
70 SNDRV_PCM_FMTBIT_S32_LE,
71 .rates = SNDRV_PCM_RATE_32000 |
72 SNDRV_PCM_RATE_44100 |
73 SNDRV_PCM_RATE_48000 |
74 SNDRV_PCM_RATE_64000 |
75 SNDRV_PCM_RATE_88200 |
76 SNDRV_PCM_RATE_96000 |
77 SNDRV_PCM_RATE_176400 |
78 SNDRV_PCM_RATE_192000,
79 .rate_min = 32000,
80 .rate_max = 192000,
81 .channels_min = 2,
82 .channels_max = 8,
d55d7a1c
CL		 83 .buffer_bytes_max = BUFFER_BYTES_MAX_MULTICH,
84 .period_bytes_min = PERIOD_BYTES_MIN,
85 .period_bytes_max = BUFFER_BYTES_MAX_MULTICH / 2,
c57cccc0 86 .periods_min = 2,
d55d7a1c 87 .periods_max = BUFFER_BYTES_MAX_MULTICH / PERIOD_BYTES_MIN,
c57cccc0
CL		 88};
89static const struct snd_pcm_hardware oxygen_ac97_hardware = {
90 .info = SNDRV_PCM_INFO_MMAP |
91 SNDRV_PCM_INFO_MMAP_VALID |
92 SNDRV_PCM_INFO_INTERLEAVED |
93 SNDRV_PCM_INFO_PAUSE |
94 SNDRV_PCM_INFO_SYNC_START,
95 .formats = SNDRV_PCM_FMTBIT_S16_LE,
96 .rates = SNDRV_PCM_RATE_48000,
97 .rate_min = 48000,
98 .rate_max = 48000,
99 .channels_min = 2,
100 .channels_max = 2,
d55d7a1c
CL		 101 .buffer_bytes_max = BUFFER_BYTES_MAX,
102 .period_bytes_min = PERIOD_BYTES_MIN,
103 .period_bytes_max = BUFFER_BYTES_MAX / 2,
c57cccc0 104 .periods_min = 2,
d55d7a1c 105 .periods_max = BUFFER_BYTES_MAX / PERIOD_BYTES_MIN,
c57cccc0
CL		 106};
107
108static const struct snd_pcm_hardware *const oxygen_hardware[PCM_COUNT] = {
109 [PCM_A] = &oxygen_stereo_hardware,
110 [PCM_B] = &oxygen_stereo_hardware,
111 [PCM_C] = &oxygen_stereo_hardware,
112 [PCM_SPDIF] = &oxygen_stereo_hardware,
113 [PCM_MULTICH] = &oxygen_multichannel_hardware,
114 [PCM_AC97] = &oxygen_ac97_hardware,
d0ce9946
CL		 115};
116
740eb835
CL		 117static inline unsigned int
118oxygen_substream_channel(struct snd_pcm_substream *substream)
119{
120 return (unsigned int)(uintptr_t)substream->runtime->private_data;
121}
122
d0ce9946
CL		 123static int oxygen_open(struct snd_pcm_substream *substream,
124 unsigned int channel)
125{
126 struct oxygen *chip = snd_pcm_substream_chip(substream);
127 struct snd_pcm_runtime *runtime = substream->runtime;
128 int err;
129
740eb835 130 runtime->private_data = (void *)(uintptr_t)channel;
5f7b9b45 131 if (channel == PCM_B && chip->has_ac97_1 &&
d76596b1 132 (chip->model.device_config & CAPTURE_2_FROM_AC97_1))
5f7b9b45
CL		 133 runtime->hw = oxygen_ac97_hardware;
134 else
135 runtime->hw = *oxygen_hardware[channel];
976cd627
CL		 136 switch (channel) {
137 case PCM_C:
33c646e4
CL		 138 runtime->hw.rates &= ~(SNDRV_PCM_RATE_32000 |
139 SNDRV_PCM_RATE_64000);
140 runtime->hw.rate_min = 44100;
976cd627
CL		 141 break;
142 case PCM_MULTICH:
9bd6a73a 143 runtime->hw.channels_max = chip->model.dac_channels;
976cd627 144 break;
33c646e4 145 }
9bd6a73a
CL		 146 if (chip->model.pcm_hardware_filter)
147 chip->model.pcm_hardware_filter(channel, &runtime->hw);
d0ce9946
CL		 148 err = snd_pcm_hw_constraint_step(runtime, 0,
149 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 32);
150 if (err < 0)
151 return err;
152 err = snd_pcm_hw_constraint_step(runtime, 0,
153 SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 32);
154 if (err < 0)
155 return err;
156 if (runtime->hw.formats & SNDRV_PCM_FMTBIT_S32_LE) {
157 err = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
158 if (err < 0)
159 return err;
160 }
161 if (runtime->hw.channels_max > 2) {
162 err = snd_pcm_hw_constraint_step(runtime, 0,
163 SNDRV_PCM_HW_PARAM_CHANNELS,
164 2);
165 if (err < 0)
ca1f30ad
CL		 166 return err;
167 }
168 if (channel == PCM_MULTICH) {
169 err = snd_pcm_hw_constraint_minmax
170 (runtime, SNDRV_PCM_HW_PARAM_PERIOD_TIME, 0, 8192000);
171 if (err < 0)
d0ce9946
CL		 172 return err;
173 }
174 snd_pcm_set_sync(substream);
175 chip->streams[channel] = substream;
176
177 mutex_lock(&chip->mutex);
178 chip->pcm_active |= 1 << channel;
179 if (channel == PCM_SPDIF) {
180 chip->spdif_pcm_bits = chip->spdif_bits;
01a3affb 181 chip->controls[CONTROL_SPDIF_PCM]->vd[0].access &=
d0ce9946
CL		 182 ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
183 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
184 SNDRV_CTL_EVENT_MASK_INFO,
01a3affb 185 &chip->controls[CONTROL_SPDIF_PCM]->id);
d0ce9946
CL		 186 }
187 mutex_unlock(&chip->mutex);
188
189 return 0;
190}
191
192static int oxygen_rec_a_open(struct snd_pcm_substream *substream)
193{
194 return oxygen_open(substream, PCM_A);
195}
196
197static int oxygen_rec_b_open(struct snd_pcm_substream *substream)
198{
199 return oxygen_open(substream, PCM_B);
200}
201
202static int oxygen_rec_c_open(struct snd_pcm_substream *substream)
203{
204 return oxygen_open(substream, PCM_C);
205}
206
207static int oxygen_spdif_open(struct snd_pcm_substream *substream)
208{
209 return oxygen_open(substream, PCM_SPDIF);
210}
211
212static int oxygen_multich_open(struct snd_pcm_substream *substream)
213{
214 return oxygen_open(substream, PCM_MULTICH);
215}
216
217static int oxygen_ac97_open(struct snd_pcm_substream *substream)
218{
219 return oxygen_open(substream, PCM_AC97);
220}
221
222static int oxygen_close(struct snd_pcm_substream *substream)
223{
224 struct oxygen *chip = snd_pcm_substream_chip(substream);
740eb835 225 unsigned int channel = oxygen_substream_channel(substream);
d0ce9946
CL		 226
227 mutex_lock(&chip->mutex);
228 chip->pcm_active &= ~(1 << channel);
229 if (channel == PCM_SPDIF) {
01a3affb 230 chip->controls[CONTROL_SPDIF_PCM]->vd[0].access |=
d0ce9946
CL		 231 SNDRV_CTL_ELEM_ACCESS_INACTIVE;
232 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
233 SNDRV_CTL_EVENT_MASK_INFO,
01a3affb 234 &chip->controls[CONTROL_SPDIF_PCM]->id);
d0ce9946
CL		 235 }
236 if (channel == PCM_SPDIF || channel == PCM_MULTICH)
237 oxygen_update_spdif_source(chip);
238 mutex_unlock(&chip->mutex);
239
240 chip->streams[channel] = NULL;
241 return 0;
242}
243
244static unsigned int oxygen_format(struct snd_pcm_hw_params *hw_params)
245{
246 if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE)
247 return OXYGEN_FORMAT_24;
248 else
249 return OXYGEN_FORMAT_16;
250}
251
252static unsigned int oxygen_rate(struct snd_pcm_hw_params *hw_params)
253{
254 switch (params_rate(hw_params)) {
255 case 32000:
256 return OXYGEN_RATE_32000;
257 case 44100:
258 return OXYGEN_RATE_44100;
259 default: /* 48000 */
260 return OXYGEN_RATE_48000;
261 case 64000:
262 return OXYGEN_RATE_64000;
263 case 88200:
264 return OXYGEN_RATE_88200;
265 case 96000:
266 return OXYGEN_RATE_96000;
267 case 176400:
268 return OXYGEN_RATE_176400;
269 case 192000:
270 return OXYGEN_RATE_192000;
271 }
272}
273
c2353a08 274static unsigned int oxygen_i2s_mclk(struct snd_pcm_hw_params *hw_params)
d0ce9946 275{
b78e3dbb
CL		 276 if (params_rate(hw_params) <= 96000)
277 return OXYGEN_I2S_MCLK_256;
278 else
279 return OXYGEN_I2S_MCLK_128;
d0ce9946
CL		 280}
281
05855ba3 282static unsigned int oxygen_i2s_bits(struct snd_pcm_hw_params *hw_params)
d0ce9946
CL		 283{
284 if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE)
05855ba3 285 return OXYGEN_I2S_BITS_24;
d0ce9946 286 else
05855ba3 287 return OXYGEN_I2S_BITS_16;
d0ce9946
CL		 288}
289
290static unsigned int oxygen_play_channels(struct snd_pcm_hw_params *hw_params)
291{
292 switch (params_channels(hw_params)) {
293 default: /* 2 */
294 return OXYGEN_PLAY_CHANNELS_2;
295 case 4:
296 return OXYGEN_PLAY_CHANNELS_4;
297 case 6:
298 return OXYGEN_PLAY_CHANNELS_6;
299 case 8:
300 return OXYGEN_PLAY_CHANNELS_8;
301 }
302}
303
304static const unsigned int channel_base_registers[PCM_COUNT] = {
305 [PCM_A] = OXYGEN_DMA_A_ADDRESS,
306 [PCM_B] = OXYGEN_DMA_B_ADDRESS,
307 [PCM_C] = OXYGEN_DMA_C_ADDRESS,
308 [PCM_SPDIF] = OXYGEN_DMA_SPDIF_ADDRESS,
309 [PCM_MULTICH] = OXYGEN_DMA_MULTICH_ADDRESS,
310 [PCM_AC97] = OXYGEN_DMA_AC97_ADDRESS,
311};
312
313static int oxygen_hw_params(struct snd_pcm_substream *substream,
314 struct snd_pcm_hw_params *hw_params)
315{
316 struct oxygen *chip = snd_pcm_substream_chip(substream);
740eb835 317 unsigned int channel = oxygen_substream_channel(substream);
d0ce9946
CL		 318 int err;
319
320 err = snd_pcm_lib_malloc_pages(substream,
321 params_buffer_bytes(hw_params));
322 if (err < 0)
323 return err;
324
325 oxygen_write32(chip, channel_base_registers[channel],
326 (u32)substream->runtime->dma_addr);
327 if (channel == PCM_MULTICH) {
328 oxygen_write32(chip, OXYGEN_DMA_MULTICH_COUNT,
329 params_buffer_bytes(hw_params) / 4 - 1);
330 oxygen_write32(chip, OXYGEN_DMA_MULTICH_TCOUNT,
331 params_period_bytes(hw_params) / 4 - 1);
332 } else {
333 oxygen_write16(chip, channel_base_registers[channel] + 4,
334 params_buffer_bytes(hw_params) / 4 - 1);
335 oxygen_write16(chip, channel_base_registers[channel] + 6,
336 params_period_bytes(hw_params) / 4 - 1);
337 }
338 return 0;
339}
340
341static int oxygen_rec_a_hw_params(struct snd_pcm_substream *substream,
342 struct snd_pcm_hw_params *hw_params)
343{
344 struct oxygen *chip = snd_pcm_substream_chip(substream);
345 int err;
346
347 err = oxygen_hw_params(substream, hw_params);
348 if (err < 0)
349 return err;
350
351 spin_lock_irq(&chip->reg_lock);
352 oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
353 oxygen_format(hw_params) << OXYGEN_REC_FORMAT_A_SHIFT,
354 OXYGEN_REC_FORMAT_A_MASK);
05855ba3
CL		 355 oxygen_write16_masked(chip, OXYGEN_I2S_A_FORMAT,
356 oxygen_rate(hw_params) |
c2353a08 357 oxygen_i2s_mclk(hw_params) |
9bd6a73a 358 chip->model.adc_i2s_format |
05855ba3
CL		 359 oxygen_i2s_bits(hw_params),
360 OXYGEN_I2S_RATE_MASK |
361 OXYGEN_I2S_FORMAT_MASK |
c2353a08 362 OXYGEN_I2S_MCLK_MASK |
05855ba3 363 OXYGEN_I2S_BITS_MASK);
d0ce9946
CL		 364 spin_unlock_irq(&chip->reg_lock);
365
366 mutex_lock(&chip->mutex);
9bd6a73a 367 chip->model.set_adc_params(chip, hw_params);
d0ce9946
CL		 368 mutex_unlock(&chip->mutex);
369 return 0;
370}
371
372static int oxygen_rec_b_hw_params(struct snd_pcm_substream *substream,
373 struct snd_pcm_hw_params *hw_params)
374{
375 struct oxygen *chip = snd_pcm_substream_chip(substream);
5f7b9b45 376 int is_ac97;
d0ce9946
CL		 377 int err;
378
379 err = oxygen_hw_params(substream, hw_params);
380 if (err < 0)
381 return err;
382
5f7b9b45 383 is_ac97 = chip->has_ac97_1 &&
d76596b1 384 (chip->model.device_config & CAPTURE_2_FROM_AC97_1);
5f7b9b45 385
d0ce9946
CL		 386 spin_lock_irq(&chip->reg_lock);
387 oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
388 oxygen_format(hw_params) << OXYGEN_REC_FORMAT_B_SHIFT,
389 OXYGEN_REC_FORMAT_B_MASK);
5f7b9b45
CL		 390 if (!is_ac97)
391 oxygen_write16_masked(chip, OXYGEN_I2S_B_FORMAT,
392 oxygen_rate(hw_params) |
393 oxygen_i2s_mclk(hw_params) |
9bd6a73a 394 chip->model.adc_i2s_format |
5f7b9b45
CL		 395 oxygen_i2s_bits(hw_params),
396 OXYGEN_I2S_RATE_MASK |
397 OXYGEN_I2S_FORMAT_MASK |
398 OXYGEN_I2S_MCLK_MASK |
399 OXYGEN_I2S_BITS_MASK);
d0ce9946
CL		 400 spin_unlock_irq(&chip->reg_lock);
401
5f7b9b45
CL		 402 if (!is_ac97) {
403 mutex_lock(&chip->mutex);
9bd6a73a 404 chip->model.set_adc_params(chip, hw_params);
5f7b9b45
CL		 405 mutex_unlock(&chip->mutex);
406 }
d0ce9946
CL		 407 return 0;
408}
409
410static int oxygen_rec_c_hw_params(struct snd_pcm_substream *substream,
411 struct snd_pcm_hw_params *hw_params)
412{
413 struct oxygen *chip = snd_pcm_substream_chip(substream);
414 int err;
415
416 err = oxygen_hw_params(substream, hw_params);
417 if (err < 0)
418 return err;
419
420 spin_lock_irq(&chip->reg_lock);
421 oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
422 oxygen_format(hw_params) << OXYGEN_REC_FORMAT_C_SHIFT,
423 OXYGEN_REC_FORMAT_C_MASK);
d0ce9946
CL		 424 spin_unlock_irq(&chip->reg_lock);
425 return 0;
426}
427
428static int oxygen_spdif_hw_params(struct snd_pcm_substream *substream,
429 struct snd_pcm_hw_params *hw_params)
430{
431 struct oxygen *chip = snd_pcm_substream_chip(substream);
432 int err;
433
434 err = oxygen_hw_params(substream, hw_params);
435 if (err < 0)
436 return err;
437
438 spin_lock_irq(&chip->reg_lock);
439 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
440 OXYGEN_SPDIF_OUT_ENABLE);
441 oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
442 oxygen_format(hw_params) << OXYGEN_SPDIF_FORMAT_SHIFT,
443 OXYGEN_SPDIF_FORMAT_MASK);
444 oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
445 oxygen_rate(hw_params) << OXYGEN_SPDIF_OUT_RATE_SHIFT,
446 OXYGEN_SPDIF_OUT_RATE_MASK);
447 oxygen_update_spdif_source(chip);
448 spin_unlock_irq(&chip->reg_lock);
449 return 0;
450}
451
452static int oxygen_multich_hw_params(struct snd_pcm_substream *substream,
453 struct snd_pcm_hw_params *hw_params)
454{
455 struct oxygen *chip = snd_pcm_substream_chip(substream);
456 int err;
457
458 err = oxygen_hw_params(substream, hw_params);
459 if (err < 0)
460 return err;
461
462 spin_lock_irq(&chip->reg_lock);
463 oxygen_write8_masked(chip, OXYGEN_PLAY_CHANNELS,
464 oxygen_play_channels(hw_params),
465 OXYGEN_PLAY_CHANNELS_MASK);
466 oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
467 oxygen_format(hw_params) << OXYGEN_MULTICH_FORMAT_SHIFT,
468 OXYGEN_MULTICH_FORMAT_MASK);
469 oxygen_write16_masked(chip, OXYGEN_I2S_MULTICH_FORMAT,
05855ba3 470 oxygen_rate(hw_params) |
9bd6a73a 471 chip->model.dac_i2s_format |
05855ba3
CL		 472 oxygen_i2s_bits(hw_params),
473 OXYGEN_I2S_RATE_MASK |
474 OXYGEN_I2S_FORMAT_MASK |
475 OXYGEN_I2S_BITS_MASK);
d0ce9946
CL		 476 oxygen_update_dac_routing(chip);
477 oxygen_update_spdif_source(chip);
478 spin_unlock_irq(&chip->reg_lock);
479
480 mutex_lock(&chip->mutex);
9bd6a73a 481 chip->model.set_dac_params(chip, hw_params);
d0ce9946
CL		 482 mutex_unlock(&chip->mutex);
483 return 0;
484}
485
d0ce9946
CL		 486static int oxygen_hw_free(struct snd_pcm_substream *substream)
487{
488 struct oxygen *chip = snd_pcm_substream_chip(substream);
740eb835 489 unsigned int channel = oxygen_substream_channel(substream);
d0ce9946
CL		 490
491 spin_lock_irq(&chip->reg_lock);
492 chip->interrupt_mask &= ~(1 << channel);
493 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
494 spin_unlock_irq(&chip->reg_lock);
495
496 return snd_pcm_lib_free_pages(substream);
497}
498
499static int oxygen_spdif_hw_free(struct snd_pcm_substream *substream)
500{
501 struct oxygen *chip = snd_pcm_substream_chip(substream);
502
503 spin_lock_irq(&chip->reg_lock);
504 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
505 OXYGEN_SPDIF_OUT_ENABLE);
506 spin_unlock_irq(&chip->reg_lock);
507 return oxygen_hw_free(substream);
508}
509
510static int oxygen_prepare(struct snd_pcm_substream *substream)
511{
512 struct oxygen *chip = snd_pcm_substream_chip(substream);
740eb835 513 unsigned int channel = oxygen_substream_channel(substream);
d0ce9946
CL		 514 unsigned int channel_mask = 1 << channel;
515
516 spin_lock_irq(&chip->reg_lock);
517 oxygen_set_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
518 oxygen_clear_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
519
520 chip->interrupt_mask |= channel_mask;
521 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
522 spin_unlock_irq(&chip->reg_lock);
523 return 0;
524}
525
526static int oxygen_trigger(struct snd_pcm_substream *substream, int cmd)
527{
528 struct oxygen *chip = snd_pcm_substream_chip(substream);
529 struct snd_pcm_substream *s;
530 unsigned int mask = 0;
db2396d4 531 int pausing;
d0ce9946
CL		 532
533 switch (cmd) {
534 case SNDRV_PCM_TRIGGER_STOP:
d0ce9946 535 case SNDRV_PCM_TRIGGER_START:
4a4bc53b 536 case SNDRV_PCM_TRIGGER_SUSPEND:
db2396d4
CL		 537 pausing = 0;
538 break;
539 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
d0ce9946 540 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
db2396d4 541 pausing = 1;
d0ce9946
CL		 542 break;
543 default:
544 return -EINVAL;
545 }
546
547 snd_pcm_group_for_each_entry(s, substream) {
548 if (snd_pcm_substream_chip(s) == chip) {
740eb835 549 mask |= 1 << oxygen_substream_channel(s);
d0ce9946
CL		 550 snd_pcm_trigger_done(s, substream);
551 }
552 }
553
554 spin_lock(&chip->reg_lock);
db2396d4
CL		 555 if (!pausing) {
556 if (cmd == SNDRV_PCM_TRIGGER_START)
557 chip->pcm_running |= mask;
558 else
559 chip->pcm_running &= ~mask;
560 oxygen_write8(chip, OXYGEN_DMA_STATUS, chip->pcm_running);
561 } else {
562 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
563 oxygen_set_bits8(chip, OXYGEN_DMA_PAUSE, mask);
564 else
565 oxygen_clear_bits8(chip, OXYGEN_DMA_PAUSE, mask);
566 }
d0ce9946
CL		 567 spin_unlock(&chip->reg_lock);
568 return 0;
569}
570
571static snd_pcm_uframes_t oxygen_pointer(struct snd_pcm_substream *substream)
572{
573 struct oxygen *chip = snd_pcm_substream_chip(substream);
574 struct snd_pcm_runtime *runtime = substream->runtime;
740eb835 575 unsigned int channel = oxygen_substream_channel(substream);
d0ce9946
CL		 576 u32 curr_addr;
577
578 /* no spinlock, this read should be atomic */
579 curr_addr = oxygen_read32(chip, channel_base_registers[channel]);
580 return bytes_to_frames(runtime, curr_addr - (u32)runtime->dma_addr);
581}
582
583static struct snd_pcm_ops oxygen_rec_a_ops = {
584 .open = oxygen_rec_a_open,
585 .close = oxygen_close,
586 .ioctl = snd_pcm_lib_ioctl,
587 .hw_params = oxygen_rec_a_hw_params,
588 .hw_free = oxygen_hw_free,
589 .prepare = oxygen_prepare,
590 .trigger = oxygen_trigger,
591 .pointer = oxygen_pointer,
592};
593
594static struct snd_pcm_ops oxygen_rec_b_ops = {
595 .open = oxygen_rec_b_open,
596 .close = oxygen_close,
597 .ioctl = snd_pcm_lib_ioctl,
598 .hw_params = oxygen_rec_b_hw_params,
599 .hw_free = oxygen_hw_free,
600 .prepare = oxygen_prepare,
601 .trigger = oxygen_trigger,
602 .pointer = oxygen_pointer,
603};
604
605static struct snd_pcm_ops oxygen_rec_c_ops = {
606 .open = oxygen_rec_c_open,
607 .close = oxygen_close,
608 .ioctl = snd_pcm_lib_ioctl,
609 .hw_params = oxygen_rec_c_hw_params,
610 .hw_free = oxygen_hw_free,
611 .prepare = oxygen_prepare,
612 .trigger = oxygen_trigger,
613 .pointer = oxygen_pointer,
614};
615
616static struct snd_pcm_ops oxygen_spdif_ops = {
617 .open = oxygen_spdif_open,
618 .close = oxygen_close,
619 .ioctl = snd_pcm_lib_ioctl,
620 .hw_params = oxygen_spdif_hw_params,
621 .hw_free = oxygen_spdif_hw_free,
622 .prepare = oxygen_prepare,
623 .trigger = oxygen_trigger,
624 .pointer = oxygen_pointer,
625};
626
627static struct snd_pcm_ops oxygen_multich_ops = {
628 .open = oxygen_multich_open,
629 .close = oxygen_close,
630 .ioctl = snd_pcm_lib_ioctl,
631 .hw_params = oxygen_multich_hw_params,
632 .hw_free = oxygen_hw_free,
633 .prepare = oxygen_prepare,
634 .trigger = oxygen_trigger,
635 .pointer = oxygen_pointer,
636};
637
638static struct snd_pcm_ops oxygen_ac97_ops = {
639 .open = oxygen_ac97_open,
640 .close = oxygen_close,
641 .ioctl = snd_pcm_lib_ioctl,
c2353a08 642 .hw_params = oxygen_hw_params,
d0ce9946
CL		 643 .hw_free = oxygen_hw_free,
644 .prepare = oxygen_prepare,
645 .trigger = oxygen_trigger,
646 .pointer = oxygen_pointer,
647};
648
649static void oxygen_pcm_free(struct snd_pcm *pcm)
650{
651 snd_pcm_lib_preallocate_free_for_all(pcm);
652}
653
f007dc04 654int oxygen_pcm_init(struct oxygen *chip)
d0ce9946
CL		 655{
656 struct snd_pcm *pcm;
e85e0925 657 int outs, ins;
d0ce9946
CL		 658 int err;
659
d76596b1
CL		 660 outs = !!(chip->model.device_config & PLAYBACK_0_TO_I2S);
661 ins = !!(chip->model.device_config & (CAPTURE_0_FROM_I2S_1 |
662 CAPTURE_0_FROM_I2S_2));
f009ad9b 663 if (outs | ins) {
79c50e23
CL		 664 err = snd_pcm_new(chip->card, "Multichannel",
665 0, outs, ins, &pcm);
f009ad9b
CL		 666 if (err < 0)
667 return err;
668 if (outs)
669 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
670 &oxygen_multich_ops);
d76596b1 671 if (chip->model.device_config & CAPTURE_0_FROM_I2S_1)
f009ad9b
CL		 672 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
673 &oxygen_rec_a_ops);
d76596b1 674 else if (chip->model.device_config & CAPTURE_0_FROM_I2S_2)
f009ad9b
CL		 675 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
676 &oxygen_rec_b_ops);
677 pcm->private_data = chip;
678 pcm->private_free = oxygen_pcm_free;
79c50e23 679 strcpy(pcm->name, "Multichannel");
f009ad9b
CL		 680 if (outs)
681 snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream,
682 SNDRV_DMA_TYPE_DEV,
683 snd_dma_pci_data(chip->pci),
d55d7a1c
CL		 684 DEFAULT_BUFFER_BYTES_MULTICH,
685 BUFFER_BYTES_MAX_MULTICH);
f009ad9b
CL		 686 if (ins)
687 snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream,
688 SNDRV_DMA_TYPE_DEV,
689 snd_dma_pci_data(chip->pci),
d55d7a1c
CL		 690 DEFAULT_BUFFER_BYTES,
691 BUFFER_BYTES_MAX);
f009ad9b
CL		 692 }
693
d76596b1
CL		 694 outs = !!(chip->model.device_config & PLAYBACK_1_TO_SPDIF);
695 ins = !!(chip->model.device_config & CAPTURE_1_FROM_SPDIF);
e85e0925
CL		 696 if (outs | ins) {
697 err = snd_pcm_new(chip->card, "Digital", 1, outs, ins, &pcm);
698 if (err < 0)
699 return err;
700 if (outs)
701 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
702 &oxygen_spdif_ops);
703 if (ins)
704 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
705 &oxygen_rec_c_ops);
706 pcm->private_data = chip;
707 pcm->private_free = oxygen_pcm_free;
708 strcpy(pcm->name, "Digital");
709 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
710 snd_dma_pci_data(chip->pci),
d55d7a1c
CL		 711 DEFAULT_BUFFER_BYTES,
712 BUFFER_BYTES_MAX);
e85e0925
CL		 713 }
714
f009ad9b 715 if (chip->has_ac97_1) {
d76596b1
CL		 716 outs = !!(chip->model.device_config & PLAYBACK_2_TO_AC97_1);
717 ins = !!(chip->model.device_config & CAPTURE_2_FROM_AC97_1);
f009ad9b
CL		 718 } else {
719 outs = 0;
d76596b1 720 ins = !!(chip->model.device_config & CAPTURE_2_FROM_I2S_2);
f009ad9b 721 }
e85e0925 722 if (outs | ins) {
5f7b9b45 723 err = snd_pcm_new(chip->card, outs ? "AC97" : "Analog2",
e85e0925 724 2, outs, ins, &pcm);
d0ce9946
CL		 725 if (err < 0)
726 return err;
5f7b9b45 727 if (outs) {
e85e0925
CL		 728 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
729 &oxygen_ac97_ops);
5f7b9b45
CL		 730 oxygen_write8_masked(chip, OXYGEN_REC_ROUTING,
731 OXYGEN_REC_B_ROUTE_AC97_1,
732 OXYGEN_REC_B_ROUTE_MASK);
733 }
e85e0925
CL		 734 if (ins)
735 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
736 &oxygen_rec_b_ops);
d0ce9946
CL		 737 pcm->private_data = chip;
738 pcm->private_free = oxygen_pcm_free;
5f7b9b45 739 strcpy(pcm->name, outs ? "Front Panel" : "Analog 2");
d0ce9946
CL		 740 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
741 snd_dma_pci_data(chip->pci),
d55d7a1c
CL		 742 DEFAULT_BUFFER_BYTES,
743 BUFFER_BYTES_MAX);
d0ce9946
CL		 744 }
745 return 0;
746}
Linux 6.x block layer and io_uring tree(s)