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Merge branch 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tytso/ext4
[linux-2.6-block.git] / sound / pci / oxygen / oxygen_lib.c
CommitLineData
d0ce9946
CL		 1/*
2 * C-Media CMI8788 driver - main driver module
3 *
4 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
5 *
6 *
7 * This driver is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License, version 2.
9 *
10 * This driver is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this driver; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
d0ce9946
CL		 20#include <linux/delay.h>
21#include <linux/interrupt.h>
22#include <linux/mutex.h>
23#include <linux/pci.h>
24#include <sound/ac97_codec.h>
25#include <sound/asoundef.h>
26#include <sound/core.h>
27#include <sound/info.h>
28#include <sound/mpu401.h>
29#include <sound/pcm.h>
30#include "oxygen.h"
878ac3ee 31#include "cm9780.h"
d0ce9946
CL		 32
33MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
34MODULE_DESCRIPTION("C-Media CMI8788 helper library");
d023dc0a 35MODULE_LICENSE("GPL v2");
d0ce9946
CL		 36
37
38static irqreturn_t oxygen_interrupt(int dummy, void *dev_id)
39{
40 struct oxygen *chip = dev_id;
41 unsigned int status, clear, elapsed_streams, i;
42
43 status = oxygen_read16(chip, OXYGEN_INTERRUPT_STATUS);
44 if (!status)
45 return IRQ_NONE;
46
47 spin_lock(&chip->reg_lock);
48
49 clear = status & (OXYGEN_CHANNEL_A |
50 OXYGEN_CHANNEL_B |
51 OXYGEN_CHANNEL_C |
52 OXYGEN_CHANNEL_SPDIF |
53 OXYGEN_CHANNEL_MULTICH |
54 OXYGEN_CHANNEL_AC97 |
c2353a08 55 OXYGEN_INT_SPDIF_IN_DETECT |
1e821dd2
CL		 56 OXYGEN_INT_GPIO |
57 OXYGEN_INT_AC97);
d0ce9946 58 if (clear) {
c2353a08
CL		 59 if (clear & OXYGEN_INT_SPDIF_IN_DETECT)
60 chip->interrupt_mask &= ~OXYGEN_INT_SPDIF_IN_DETECT;
d0ce9946
CL		 61 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
62 chip->interrupt_mask & ~clear);
63 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
64 chip->interrupt_mask);
65 }
66
67 elapsed_streams = status & chip->pcm_running;
68
69 spin_unlock(&chip->reg_lock);
70
71 for (i = 0; i < PCM_COUNT; ++i)
72 if ((elapsed_streams & (1 << i)) && chip->streams[i])
73 snd_pcm_period_elapsed(chip->streams[i]);
74
c2353a08 75 if (status & OXYGEN_INT_SPDIF_IN_DETECT) {
d0ce9946
CL		 76 spin_lock(&chip->reg_lock);
77 i = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
7f0b8946
CL		 78 if (i & (OXYGEN_SPDIF_SENSE_INT | OXYGEN_SPDIF_LOCK_INT |
79 OXYGEN_SPDIF_RATE_INT)) {
80 /* write the interrupt bit(s) to clear */
d0ce9946
CL		 81 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, i);
82 schedule_work(&chip->spdif_input_bits_work);
83 }
84 spin_unlock(&chip->reg_lock);
85 }
86
87 if (status & OXYGEN_INT_GPIO)
7c014159 88 schedule_work(&chip->gpio_work);
d0ce9946
CL		 89
90 if ((status & OXYGEN_INT_MIDI) && chip->midi)
91 snd_mpu401_uart_interrupt(0, chip->midi->private_data);
92
1e821dd2
CL		 93 if (status & OXYGEN_INT_AC97)
94 wake_up(&chip->ac97_waitqueue);
95
d0ce9946
CL		 96 return IRQ_HANDLED;
97}
98
99static void oxygen_spdif_input_bits_changed(struct work_struct *work)
100{
101 struct oxygen *chip = container_of(work, struct oxygen,
102 spdif_input_bits_work);
7f0b8946 103 u32 reg;
d0ce9946 104
7f0b8946
CL		 105 /*
106 * This function gets called when there is new activity on the SPDIF
107 * input, or when we lose lock on the input signal, or when the rate
108 * changes.
109 */
d0ce9946 110 msleep(1);
7f0b8946
CL		 111 spin_lock_irq(&chip->reg_lock);
112 reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
113 if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
114 OXYGEN_SPDIF_LOCK_STATUS))
115 == OXYGEN_SPDIF_SENSE_STATUS) {
116 /*
117 * If we detect activity on the SPDIF input but cannot lock to
118 * a signal, the clock bit is likely to be wrong.
119 */
120 reg ^= OXYGEN_SPDIF_IN_CLOCK_MASK;
121 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
d0ce9946
CL		 122 spin_unlock_irq(&chip->reg_lock);
123 msleep(1);
7f0b8946
CL		 124 spin_lock_irq(&chip->reg_lock);
125 reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
126 if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
127 OXYGEN_SPDIF_LOCK_STATUS))
128 == OXYGEN_SPDIF_SENSE_STATUS) {
129 /* nothing detected with either clock; give up */
130 if ((reg & OXYGEN_SPDIF_IN_CLOCK_MASK)
131 == OXYGEN_SPDIF_IN_CLOCK_192) {
132 /*
133 * Reset clock to <= 96 kHz because this is
134 * more likely to be received next time.
135 */
136 reg &= ~OXYGEN_SPDIF_IN_CLOCK_MASK;
137 reg |= OXYGEN_SPDIF_IN_CLOCK_96;
138 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
139 }
d0ce9946
CL		 140 }
141 }
7f0b8946 142 spin_unlock_irq(&chip->reg_lock);
d0ce9946 143
01a3affb 144 if (chip->controls[CONTROL_SPDIF_INPUT_BITS]) {
d0ce9946 145 spin_lock_irq(&chip->reg_lock);
c2353a08 146 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
d0ce9946
CL		 147 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
148 chip->interrupt_mask);
149 spin_unlock_irq(&chip->reg_lock);
150
7f0b8946
CL		 151 /*
152 * We don't actually know that any channel status bits have
153 * changed, but let's send a notification just to be sure.
154 */
d0ce9946 155 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
01a3affb 156 &chip->controls[CONTROL_SPDIF_INPUT_BITS]->id);
d0ce9946
CL		 157 }
158}
159
7c014159
CL		 160static void oxygen_gpio_changed(struct work_struct *work)
161{
162 struct oxygen *chip = container_of(work, struct oxygen, gpio_work);
163
164 if (chip->model->gpio_changed)
165 chip->model->gpio_changed(chip);
166}
167
d0ce9946
CL		 168#ifdef CONFIG_PROC_FS
169static void oxygen_proc_read(struct snd_info_entry *entry,
170 struct snd_info_buffer *buffer)
171{
172 struct oxygen *chip = entry->private_data;
173 int i, j;
174
175 snd_iprintf(buffer, "CMI8788\n\n");
c1365007 176 for (i = 0; i < OXYGEN_IO_SIZE; i += 0x10) {
d0ce9946
CL		 177 snd_iprintf(buffer, "%02x:", i);
178 for (j = 0; j < 0x10; ++j)
179 snd_iprintf(buffer, " %02x", oxygen_read8(chip, i + j));
180 snd_iprintf(buffer, "\n");
181 }
182 if (mutex_lock_interruptible(&chip->mutex) < 0)
183 return;
31c77643
CL		 184 if (chip->has_ac97_0) {
185 snd_iprintf(buffer, "\nAC97\n");
186 for (i = 0; i < 0x80; i += 0x10) {
187 snd_iprintf(buffer, "%02x:", i);
188 for (j = 0; j < 0x10; j += 2)
189 snd_iprintf(buffer, " %04x",
190 oxygen_read_ac97(chip, 0, i + j));
191 snd_iprintf(buffer, "\n");
192 }
193 }
194 if (chip->has_ac97_1) {
195 snd_iprintf(buffer, "\nAC97 2\n");
196 for (i = 0; i < 0x80; i += 0x10) {
197 snd_iprintf(buffer, "%02x:", i);
198 for (j = 0; j < 0x10; j += 2)
199 snd_iprintf(buffer, " %04x",
200 oxygen_read_ac97(chip, 1, i + j));
201 snd_iprintf(buffer, "\n");
202 }
d0ce9946
CL		 203 }
204 mutex_unlock(&chip->mutex);
205}
206
f007dc04 207static void oxygen_proc_init(struct oxygen *chip)
d0ce9946
CL		 208{
209 struct snd_info_entry *entry;
210
211 if (!snd_card_proc_new(chip->card, "cmi8788", &entry))
212 snd_info_set_text_ops(entry, chip, oxygen_proc_read);
213}
214#else
215#define oxygen_proc_init(chip)
216#endif
217
f007dc04 218static void oxygen_init(struct oxygen *chip)
d0ce9946
CL		 219{
220 unsigned int i;
221
222 chip->dac_routing = 1;
223 for (i = 0; i < 8; ++i)
e983532e
CL		 224 chip->dac_volume[i] = chip->model->dac_volume_min;
225 chip->dac_mute = 1;
d0ce9946
CL		 226 chip->spdif_playback_enable = 1;
227 chip->spdif_bits = OXYGEN_SPDIF_C | OXYGEN_SPDIF_ORIGINAL |
228 (IEC958_AES1_CON_PCM_CODER << OXYGEN_SPDIF_CATEGORY_SHIFT);
229 chip->spdif_pcm_bits = chip->spdif_bits;
230
231 if (oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_REVISION_2)
232 chip->revision = 2;
233 else
234 chip->revision = 1;
235
236 if (chip->revision == 1)
c2353a08
CL		 237 oxygen_set_bits8(chip, OXYGEN_MISC,
238 OXYGEN_MISC_PCI_MEM_W_1_CLOCK);
d0ce9946 239
31c77643
CL		 240 i = oxygen_read16(chip, OXYGEN_AC97_CONTROL);
241 chip->has_ac97_0 = (i & OXYGEN_AC97_CODEC_0) != 0;
242 chip->has_ac97_1 = (i & OXYGEN_AC97_CODEC_1) != 0;
243
b78e3dbb 244 oxygen_write8_masked(chip, OXYGEN_FUNCTION,
87eedd2f
CL		 245 OXYGEN_FUNCTION_RESET_CODEC |
246 chip->model->function_flags,
247 OXYGEN_FUNCTION_RESET_CODEC |
248 OXYGEN_FUNCTION_2WIRE_SPI_MASK |
249 OXYGEN_FUNCTION_ENABLE_SPI_4_5);
b78e3dbb
CL		 250 oxygen_write8(chip, OXYGEN_DMA_STATUS, 0);
251 oxygen_write8(chip, OXYGEN_DMA_PAUSE, 0);
252 oxygen_write8(chip, OXYGEN_PLAY_CHANNELS,
253 OXYGEN_PLAY_CHANNELS_2 |
254 OXYGEN_DMA_A_BURST_8 |
255 OXYGEN_DMA_MULTICH_BURST_8);
256 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
db12b8e3
CL		 257 oxygen_write8_masked(chip, OXYGEN_MISC,
258 chip->model->misc_flags,
b78e3dbb
CL		 259 OXYGEN_MISC_WRITE_PCI_SUBID |
260 OXYGEN_MISC_REC_C_FROM_SPDIF |
261 OXYGEN_MISC_REC_B_FROM_AC97 |
db12b8e3
CL		 262 OXYGEN_MISC_REC_A_FROM_MULTICH |
263 OXYGEN_MISC_MIDI);
b78e3dbb
CL		 264 oxygen_write8(chip, OXYGEN_REC_FORMAT,
265 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_A_SHIFT) |
266 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_B_SHIFT) |
267 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_C_SHIFT));
268 oxygen_write8(chip, OXYGEN_PLAY_FORMAT,
269 (OXYGEN_FORMAT_16 << OXYGEN_SPDIF_FORMAT_SHIFT) |
270 (OXYGEN_FORMAT_16 << OXYGEN_MULTICH_FORMAT_SHIFT));
271 oxygen_write8(chip, OXYGEN_REC_CHANNELS, OXYGEN_REC_CHANNELS_2_2_2);
c9946b2c 272 oxygen_write16(chip, OXYGEN_I2S_MULTICH_FORMAT,
fa5d8106
CL		 273 OXYGEN_RATE_48000 | chip->model->dac_i2s_format |
274 OXYGEN_I2S_MCLK_256 | OXYGEN_I2S_BITS_16 |
c9946b2c 275 OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
43dd89c7
CL		 276 if (chip->model->pcm_dev_cfg & CAPTURE_0_FROM_I2S_1)
277 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
278 OXYGEN_RATE_48000 | chip->model->adc_i2s_format |
279 OXYGEN_I2S_MCLK_256 | OXYGEN_I2S_BITS_16 |
280 OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
281 else
282 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
283 OXYGEN_I2S_MASTER | OXYGEN_I2S_MUTE_MCLK);
284 if (chip->model->pcm_dev_cfg & (CAPTURE_0_FROM_I2S_2 |
285 CAPTURE_2_FROM_I2S_2))
286 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
287 OXYGEN_RATE_48000 | chip->model->adc_i2s_format |
288 OXYGEN_I2S_MCLK_256 | OXYGEN_I2S_BITS_16 |
289 OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
290 else
291 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
292 OXYGEN_I2S_MASTER | OXYGEN_I2S_MUTE_MCLK);
c9946b2c 293 oxygen_write16(chip, OXYGEN_I2S_C_FORMAT,
43dd89c7 294 OXYGEN_I2S_MASTER | OXYGEN_I2S_MUTE_MCLK);
1d98c7d4
CL		 295 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
296 OXYGEN_SPDIF_OUT_ENABLE |
297 OXYGEN_SPDIF_LOOPBACK);
298 if (chip->model->pcm_dev_cfg & CAPTURE_1_FROM_SPDIF)
299 oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
300 OXYGEN_SPDIF_SENSE_MASK |
301 OXYGEN_SPDIF_LOCK_MASK |
302 OXYGEN_SPDIF_RATE_MASK |
303 OXYGEN_SPDIF_LOCK_PAR |
304 OXYGEN_SPDIF_IN_CLOCK_96,
305 OXYGEN_SPDIF_SENSE_MASK |
306 OXYGEN_SPDIF_LOCK_MASK |
307 OXYGEN_SPDIF_RATE_MASK |
308 OXYGEN_SPDIF_SENSE_PAR |
309 OXYGEN_SPDIF_LOCK_PAR |
310 OXYGEN_SPDIF_IN_CLOCK_MASK);
311 else
312 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
313 OXYGEN_SPDIF_SENSE_MASK |
314 OXYGEN_SPDIF_LOCK_MASK |
315 OXYGEN_SPDIF_RATE_MASK);
d0ce9946 316 oxygen_write32(chip, OXYGEN_SPDIF_OUTPUT_BITS, chip->spdif_bits);
4a4bc53b
CL		 317 oxygen_write16(chip, OXYGEN_2WIRE_BUS_STATUS,
318 OXYGEN_2WIRE_LENGTH_8 |
319 OXYGEN_2WIRE_INTERRUPT_MASK |
320 OXYGEN_2WIRE_SPEED_STANDARD);
b78e3dbb
CL		 321 oxygen_clear_bits8(chip, OXYGEN_MPU401_CONTROL, OXYGEN_MPU401_LOOPBACK);
322 oxygen_write8(chip, OXYGEN_GPI_INTERRUPT_MASK, 0);
323 oxygen_write16(chip, OXYGEN_GPIO_INTERRUPT_MASK, 0);
c9946b2c 324 oxygen_write16(chip, OXYGEN_PLAY_ROUTING,
b78e3dbb
CL		 325 OXYGEN_PLAY_MULTICH_I2S_DAC |
326 OXYGEN_PLAY_SPDIF_SPDIF |
c9946b2c
CL		 327 (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) |
328 (1 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT) |
329 (2 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT) |
330 (3 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT));
331 oxygen_write8(chip, OXYGEN_REC_ROUTING,
332 OXYGEN_REC_A_ROUTE_I2S_ADC_1 |
b78e3dbb 333 OXYGEN_REC_B_ROUTE_I2S_ADC_2 |
c9946b2c
CL		 334 OXYGEN_REC_C_ROUTE_SPDIF);
335 oxygen_write8(chip, OXYGEN_ADC_MONITOR, 0);
336 oxygen_write8(chip, OXYGEN_A_MONITOR_ROUTING,
337 (0 << OXYGEN_A_MONITOR_ROUTE_0_SHIFT) |
338 (1 << OXYGEN_A_MONITOR_ROUTE_1_SHIFT) |
339 (2 << OXYGEN_A_MONITOR_ROUTE_2_SHIFT) |
340 (3 << OXYGEN_A_MONITOR_ROUTE_3_SHIFT));
d0ce9946 341
1d98c7d4
CL		 342 if (chip->has_ac97_0 | chip->has_ac97_1)
343 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK,
344 OXYGEN_AC97_INT_READ_DONE |
345 OXYGEN_AC97_INT_WRITE_DONE);
346 else
347 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, 0);
b78e3dbb
CL		 348 oxygen_write32(chip, OXYGEN_AC97_OUT_CONFIG, 0);
349 oxygen_write32(chip, OXYGEN_AC97_IN_CONFIG, 0);
350 if (!(chip->has_ac97_0 | chip->has_ac97_1))
351 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
352 OXYGEN_AC97_CLOCK_DISABLE);
353 if (!chip->has_ac97_0) {
354 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
355 OXYGEN_AC97_NO_CODEC_0);
356 } else {
31c77643
CL		 357 oxygen_write_ac97(chip, 0, AC97_RESET, 0);
358 msleep(1);
878ac3ee
CL		 359 oxygen_ac97_set_bits(chip, 0, CM9780_GPIO_SETUP,
360 CM9780_GPIO0IO | CM9780_GPIO1IO);
361 oxygen_ac97_set_bits(chip, 0, CM9780_MIXER,
362 CM9780_BSTSEL | CM9780_STRO_MIC |
363 CM9780_MIX2FR | CM9780_PCBSW);
364 oxygen_ac97_set_bits(chip, 0, CM9780_JACK,
365 CM9780_RSOE | CM9780_CBOE |
366 CM9780_SSOE | CM9780_FROE |
367 CM9780_MIC2MIC | CM9780_LI2LI);
31c77643
CL		 368 oxygen_write_ac97(chip, 0, AC97_MASTER, 0x0000);
369 oxygen_write_ac97(chip, 0, AC97_PC_BEEP, 0x8000);
370 oxygen_write_ac97(chip, 0, AC97_MIC, 0x8808);
371 oxygen_write_ac97(chip, 0, AC97_LINE, 0x0808);
372 oxygen_write_ac97(chip, 0, AC97_CD, 0x8808);
373 oxygen_write_ac97(chip, 0, AC97_VIDEO, 0x8808);
374 oxygen_write_ac97(chip, 0, AC97_AUX, 0x8808);
375 oxygen_write_ac97(chip, 0, AC97_REC_GAIN, 0x8000);
376 oxygen_write_ac97(chip, 0, AC97_CENTER_LFE_MASTER, 0x8080);
377 oxygen_write_ac97(chip, 0, AC97_SURROUND_MASTER, 0x8080);
e97f7999
CL		 378 oxygen_ac97_clear_bits(chip, 0, CM9780_GPIO_STATUS,
379 CM9780_GPO0);
31c77643
CL		 380 /* power down unused ADCs and DACs */
381 oxygen_ac97_set_bits(chip, 0, AC97_POWERDOWN,
382 AC97_PD_PR0 | AC97_PD_PR1);
383 oxygen_ac97_set_bits(chip, 0, AC97_EXTENDED_STATUS,
384 AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK);
385 }
b78e3dbb
CL		 386 if (chip->has_ac97_1) {
387 oxygen_set_bits32(chip, OXYGEN_AC97_OUT_CONFIG,
388 OXYGEN_AC97_CODEC1_SLOT3 |
389 OXYGEN_AC97_CODEC1_SLOT4);
390 oxygen_write_ac97(chip, 1, AC97_RESET, 0);
391 msleep(1);
392 oxygen_write_ac97(chip, 1, AC97_MASTER, 0x0000);
393 oxygen_write_ac97(chip, 1, AC97_HEADPHONE, 0x8000);
394 oxygen_write_ac97(chip, 1, AC97_PC_BEEP, 0x8000);
395 oxygen_write_ac97(chip, 1, AC97_MIC, 0x8808);
396 oxygen_write_ac97(chip, 1, AC97_LINE, 0x8808);
397 oxygen_write_ac97(chip, 1, AC97_CD, 0x8808);
398 oxygen_write_ac97(chip, 1, AC97_VIDEO, 0x8808);
399 oxygen_write_ac97(chip, 1, AC97_AUX, 0x8808);
400 oxygen_write_ac97(chip, 1, AC97_PCM, 0x0808);
401 oxygen_write_ac97(chip, 1, AC97_REC_SEL, 0x0000);
a3601560 402 oxygen_write_ac97(chip, 1, AC97_REC_GAIN, 0x0000);
b78e3dbb
CL		 403 oxygen_ac97_set_bits(chip, 1, 0x6a, 0x0040);
404 }
d0ce9946
CL		 405}
406
407static void oxygen_card_free(struct snd_card *card)
408{
409 struct oxygen *chip = card->private_data;
410
411 spin_lock_irq(&chip->reg_lock);
412 chip->interrupt_mask = 0;
413 chip->pcm_running = 0;
414 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
415 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
416 spin_unlock_irq(&chip->reg_lock);
f000fd80 417 if (chip->irq >= 0)
d0ce9946 418 free_irq(chip->irq, chip);
d0ce9946
CL		 419 flush_scheduled_work();
420 chip->model->cleanup(chip);
421 mutex_destroy(&chip->mutex);
422 pci_release_regions(chip->pci);
423 pci_disable_device(chip->pci);
424}
425
f007dc04 426int oxygen_pci_probe(struct pci_dev *pci, int index, char *id,
db12b8e3 427 const struct oxygen_model *model)
d0ce9946
CL		 428{
429 struct snd_card *card;
430 struct oxygen *chip;
431 int err;
432
7ef37cd9
CL		 433 card = snd_card_new(index, id, model->owner,
434 sizeof *chip + model->model_data_size);
d0ce9946
CL		 435 if (!card)
436 return -ENOMEM;
437
438 chip = card->private_data;
439 chip->card = card;
440 chip->pci = pci;
441 chip->irq = -1;
442 chip->model = model;
7ef37cd9 443 chip->model_data = chip + 1;
d0ce9946
CL		 444 spin_lock_init(&chip->reg_lock);
445 mutex_init(&chip->mutex);
446 INIT_WORK(&chip->spdif_input_bits_work,
447 oxygen_spdif_input_bits_changed);
7c014159 448 INIT_WORK(&chip->gpio_work, oxygen_gpio_changed);
1e821dd2 449 init_waitqueue_head(&chip->ac97_waitqueue);
d0ce9946
CL		 450
451 err = pci_enable_device(pci);
452 if (err < 0)
453 goto err_card;
454
455 err = pci_request_regions(pci, model->chip);
456 if (err < 0) {
457 snd_printk(KERN_ERR "cannot reserve PCI resources\n");
458 goto err_pci_enable;
459 }
460
461 if (!(pci_resource_flags(pci, 0) & IORESOURCE_IO) ||
c1365007 462 pci_resource_len(pci, 0) < OXYGEN_IO_SIZE) {
d0ce9946
CL		 463 snd_printk(KERN_ERR "invalid PCI I/O range\n");
464 err = -ENXIO;
465 goto err_pci_regions;
466 }
467 chip->addr = pci_resource_start(pci, 0);
468
469 pci_set_master(pci);
470 snd_card_set_dev(card, &pci->dev);
471 card->private_free = oxygen_card_free;
472
473 oxygen_init(chip);
474 model->init(chip);
475
476 err = request_irq(pci->irq, oxygen_interrupt, IRQF_SHARED,
477 model->chip, chip);
478 if (err < 0) {
479 snd_printk(KERN_ERR "cannot grab interrupt %d\n", pci->irq);
480 goto err_card;
481 }
482 chip->irq = pci->irq;
483
484 strcpy(card->driver, model->chip);
485 strcpy(card->shortname, model->shortname);
486 sprintf(card->longname, "%s (rev %u) at %#lx, irq %i",
487 model->longname, chip->revision, chip->addr, chip->irq);
488 strcpy(card->mixername, model->chip);
489 snd_component_add(card, model->chip);
490
491 err = oxygen_pcm_init(chip);
492 if (err < 0)
493 goto err_card;
494
495 err = oxygen_mixer_init(chip);
496 if (err < 0)
497 goto err_card;
498
db12b8e3 499 if (model->misc_flags & OXYGEN_MISC_MIDI) {
d0ce9946
CL		 500 err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
501 chip->addr + OXYGEN_MPU401,
502 MPU401_INFO_INTEGRATED, 0, 0,
503 &chip->midi);
504 if (err < 0)
505 goto err_card;
506 }
507
508 oxygen_proc_init(chip);
509
510 spin_lock_irq(&chip->reg_lock);
1d98c7d4
CL		 511 if (chip->model->pcm_dev_cfg & CAPTURE_1_FROM_SPDIF)
512 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
513 if (chip->has_ac97_0 | chip->has_ac97_1)
514 chip->interrupt_mask |= OXYGEN_INT_AC97;
d0ce9946
CL		 515 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
516 spin_unlock_irq(&chip->reg_lock);
517
518 err = snd_card_register(card);
519 if (err < 0)
520 goto err_card;
521
522 pci_set_drvdata(pci, card);
523 return 0;
524
525err_pci_regions:
526 pci_release_regions(pci);
527err_pci_enable:
528 pci_disable_device(pci);
529err_card:
530 snd_card_free(card);
531 return err;
532}
533EXPORT_SYMBOL(oxygen_pci_probe);
534
f007dc04 535void oxygen_pci_remove(struct pci_dev *pci)
d0ce9946
CL		 536{
537 snd_card_free(pci_get_drvdata(pci));
538 pci_set_drvdata(pci, NULL);
539}
540EXPORT_SYMBOL(oxygen_pci_remove);
4a4bc53b
CL		 541
542#ifdef CONFIG_PM
543int oxygen_pci_suspend(struct pci_dev *pci, pm_message_t state)
544{
545 struct snd_card *card = pci_get_drvdata(pci);
546 struct oxygen *chip = card->private_data;
547 unsigned int i, saved_interrupt_mask;
548
549 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
550
551 for (i = 0; i < PCM_COUNT; ++i)
552 if (chip->streams[i])
553 snd_pcm_suspend(chip->streams[i]);
554
555 if (chip->model->suspend)
556 chip->model->suspend(chip);
557
558 spin_lock_irq(&chip->reg_lock);
559 saved_interrupt_mask = chip->interrupt_mask;
560 chip->interrupt_mask = 0;
561 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
562 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
563 spin_unlock_irq(&chip->reg_lock);
564
565 synchronize_irq(chip->irq);
566 flush_scheduled_work();
567 chip->interrupt_mask = saved_interrupt_mask;
568
569 pci_disable_device(pci);
570 pci_save_state(pci);
571 pci_set_power_state(pci, pci_choose_state(pci, state));
572 return 0;
573}
574EXPORT_SYMBOL(oxygen_pci_suspend);
575
576static const u32 registers_to_restore[OXYGEN_IO_SIZE / 32] = {
577 0xffffffff, 0x00ff077f, 0x00011d08, 0x007f00ff,
578 0x00300000, 0x00000fe4, 0x0ff7001f, 0x00000000
579};
580static const u32 ac97_registers_to_restore[2][0x40 / 32] = {
581 { 0x18284fa2, 0x03060000 },
582 { 0x00007fa6, 0x00200000 }
583};
584
585static inline int is_bit_set(const u32 *bitmap, unsigned int bit)
586{
587 return bitmap[bit / 32] & (1 << (bit & 31));
588}
589
590static void oxygen_restore_ac97(struct oxygen *chip, unsigned int codec)
591{
592 unsigned int i;
593
594 oxygen_write_ac97(chip, codec, AC97_RESET, 0);
595 msleep(1);
596 for (i = 1; i < 0x40; ++i)
597 if (is_bit_set(ac97_registers_to_restore[codec], i))
598 oxygen_write_ac97(chip, codec, i * 2,
599 chip->saved_ac97_registers[codec][i]);
600}
601
602int oxygen_pci_resume(struct pci_dev *pci)
603{
604 struct snd_card *card = pci_get_drvdata(pci);
605 struct oxygen *chip = card->private_data;
606 unsigned int i;
607
608 pci_set_power_state(pci, PCI_D0);
609 pci_restore_state(pci);
610 if (pci_enable_device(pci) < 0) {
611 snd_printk(KERN_ERR "cannot reenable device");
612 snd_card_disconnect(card);
613 return -EIO;
614 }
615 pci_set_master(pci);
616
617 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
618 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
619 for (i = 0; i < OXYGEN_IO_SIZE; ++i)
620 if (is_bit_set(registers_to_restore, i))
621 oxygen_write8(chip, i, chip->saved_registers._8[i]);
622 if (chip->has_ac97_0)
623 oxygen_restore_ac97(chip, 0);
624 if (chip->has_ac97_1)
625 oxygen_restore_ac97(chip, 1);
626
627 if (chip->model->resume)
628 chip->model->resume(chip);
629
630 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
631
632 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
633 return 0;
634}
635EXPORT_SYMBOL(oxygen_pci_resume);
636#endif /* CONFIG_PM */
Linux 6.x block layer and io_uring tree(s)