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ALSA: virtuoso: fix front panel routing for D1/DX/ST(X)
[linux-2.6-block.git] / sound / pci / oxygen / oxygen.c
CommitLineData
d0ce9946 1/*
873591db 2 * C-Media CMI8788 driver for C-Media's reference design and similar models
d0ce9946
CL		 3 *
4 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
5 *
6 *
7 * This driver is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License, version 2.
9 *
10 * This driver is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this driver; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20/*
dc0adf48
CL		 21 * CMI8788:
22 *
d0ce9946 23 * SPI 0 -> 1st AK4396 (front)
7113e958 24 * SPI 1 -> 2nd AK4396 (surround)
d0ce9946
CL		 25 * SPI 2 -> 3rd AK4396 (center/LFE)
26 * SPI 3 -> WM8785
7113e958 27 * SPI 4 -> 4th AK4396 (back)
d0ce9946
CL		 28 *
29 * GPIO 0 -> DFS0 of AK5385
30 * GPIO 1 -> DFS1 of AK5385
873591db 31 * GPIO 8 -> enable headphone amplifier on HT-Omega models
dc0adf48
CL		 32 *
33 * CM9780:
34 *
35 * GPO 0 -> route line-in (0) or AC97 output (1) to ADC input
d0ce9946
CL		 36 */
37
df91bc23 38#include <linux/delay.h>
902b05c1 39#include <linux/mutex.h>
d0ce9946 40#include <linux/pci.h>
902b05c1 41#include <sound/ac97_codec.h>
ccc80fb4 42#include <sound/control.h>
d0ce9946
CL		 43#include <sound/core.h>
44#include <sound/initval.h>
45#include <sound/pcm.h>
46#include <sound/pcm_params.h>
47#include <sound/tlv.h>
48#include "oxygen.h"
c626026d 49#include "ak4396.h"
f5b2368b 50#include "wm8785.h"
d0ce9946
CL		 51
52MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
53MODULE_DESCRIPTION("C-Media CMI8788 driver");
d023dc0a 54MODULE_LICENSE("GPL v2");
d0ce9946
CL		 55MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8788}}");
56
57static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
58static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
59static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
60
61module_param_array(index, int, NULL, 0444);
62MODULE_PARM_DESC(index, "card index");
63module_param_array(id, charp, NULL, 0444);
64MODULE_PARM_DESC(id, "ID string");
65module_param_array(enable, bool, NULL, 0444);
66MODULE_PARM_DESC(enable, "enable card");
67
2f1b0ec7 68enum {
18f24839
CL		 69 MODEL_CMEDIA_REF,
70 MODEL_MERIDIAN,
71 MODEL_CLARO,
72 MODEL_CLARO_HALO,
2146dcfd
CL		 73 MODEL_FANTASIA,
74 MODEL_2CH_OUTPUT,
2f1b0ec7
CL		 75};
76
cebe41d4 77static DEFINE_PCI_DEVICE_TABLE(oxygen_ids) = {
18f24839 78 /* C-Media's reference design */
2f1b0ec7
CL		 79 { OXYGEN_PCI_SUBID(0x10b0, 0x0216), .driver_data = MODEL_CMEDIA_REF },
80 { OXYGEN_PCI_SUBID(0x10b0, 0x0218), .driver_data = MODEL_CMEDIA_REF },
81 { OXYGEN_PCI_SUBID(0x10b0, 0x0219), .driver_data = MODEL_CMEDIA_REF },
82 { OXYGEN_PCI_SUBID(0x13f6, 0x0001), .driver_data = MODEL_CMEDIA_REF },
83 { OXYGEN_PCI_SUBID(0x13f6, 0x0010), .driver_data = MODEL_CMEDIA_REF },
84 { OXYGEN_PCI_SUBID(0x13f6, 0x8788), .driver_data = MODEL_CMEDIA_REF },
85 { OXYGEN_PCI_SUBID(0x147a, 0xa017), .driver_data = MODEL_CMEDIA_REF },
18f24839
CL		 86 { OXYGEN_PCI_SUBID(0x1a58, 0x0910), .driver_data = MODEL_CMEDIA_REF },
87 /* Kuroutoshikou CMI8787-HG2PCI */
2146dcfd 88 { OXYGEN_PCI_SUBID(0x13f6, 0xffff), .driver_data = MODEL_2CH_OUTPUT },
18f24839 89 /* TempoTec HiFier Fantasia */
2146dcfd
CL		 90 { OXYGEN_PCI_SUBID(0x14c3, 0x1710), .driver_data = MODEL_FANTASIA },
91 /* TempoTec HiFier Serenade */
92 { OXYGEN_PCI_SUBID(0x14c3, 0x1711), .driver_data = MODEL_2CH_OUTPUT },
18f24839 93 /* AuzenTech X-Meridian */
2f1b0ec7 94 { OXYGEN_PCI_SUBID(0x415a, 0x5431), .driver_data = MODEL_MERIDIAN },
18f24839 95 /* HT-Omega Claro */
873591db 96 { OXYGEN_PCI_SUBID(0x7284, 0x9761), .driver_data = MODEL_CLARO },
18f24839 97 /* HT-Omega Claro halo */
873591db 98 { OXYGEN_PCI_SUBID(0x7284, 0x9781), .driver_data = MODEL_CLARO_HALO },
d0ce9946
CL		 99 { }
100};
101MODULE_DEVICE_TABLE(pci, oxygen_ids);
102
878ac3ee
CL		 103
104#define GPIO_AK5385_DFS_MASK 0x0003
105#define GPIO_AK5385_DFS_NORMAL 0x0000
106#define GPIO_AK5385_DFS_DOUBLE 0x0001
107#define GPIO_AK5385_DFS_QUAD 0x0002
108
873591db
CL		 109#define GPIO_CLARO_HP 0x0100
110
7ef37cd9 111struct generic_data {
45c1de8e 112 unsigned int dacs;
6f0de3ce 113 u8 ak4396_regs[4][5];
1ff04886 114 u16 wm8785_regs[3];
7ef37cd9
CL		 115};
116
d0ce9946
CL		 117static void ak4396_write(struct oxygen *chip, unsigned int codec,
118 u8 reg, u8 value)
119{
120 /* maps ALSA channel pair number to SPI output */
121 static const u8 codec_spi_map[4] = {
7113e958 122 0, 1, 2, 4
d0ce9946 123 };
6f0de3ce
CL		 124 struct generic_data *data = chip->model_data;
125
c2353a08 126 oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER |
d0ce9946 127 OXYGEN_SPI_DATA_LENGTH_2 |
2ea85986 128 OXYGEN_SPI_CLOCK_160 |
d0ce9946 129 (codec_spi_map[codec] << OXYGEN_SPI_CODEC_SHIFT) |
c2353a08 130 OXYGEN_SPI_CEN_LATCH_CLOCK_HI,
d0ce9946 131 AK4396_WRITE | (reg << 8) | value);
6f0de3ce
CL		 132 data->ak4396_regs[codec][reg] = value;
133}
134
135static void ak4396_write_cached(struct oxygen *chip, unsigned int codec,
136 u8 reg, u8 value)
137{
138 struct generic_data *data = chip->model_data;
139
140 if (value != data->ak4396_regs[codec][reg])
141 ak4396_write(chip, codec, reg, value);
d0ce9946
CL		 142}
143
144static void wm8785_write(struct oxygen *chip, u8 reg, unsigned int value)
145{
e58aee95
CL		 146 struct generic_data *data = chip->model_data;
147
c2353a08 148 oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER |
d0ce9946 149 OXYGEN_SPI_DATA_LENGTH_2 |
2ea85986 150 OXYGEN_SPI_CLOCK_160 |
c2353a08
CL		 151 (3 << OXYGEN_SPI_CODEC_SHIFT) |
152 OXYGEN_SPI_CEN_LATCH_CLOCK_LO,
d0ce9946 153 (reg << 9) | value);
6f0de3ce
CL		 154 if (reg < ARRAY_SIZE(data->wm8785_regs))
155 data->wm8785_regs[reg] = value;
bbbfb552
CL		 156}
157
75146fc0 158static void ak4396_registers_init(struct oxygen *chip)
d0ce9946 159{
7ef37cd9 160 struct generic_data *data = chip->model_data;
d0ce9946
CL		 161 unsigned int i;
162
45c1de8e 163 for (i = 0; i < data->dacs; ++i) {
6f0de3ce
CL		 164 ak4396_write(chip, i, AK4396_CONTROL_1,
165 AK4396_DIF_24_MSB | AK4396_RSTN);
166 ak4396_write(chip, i, AK4396_CONTROL_2,
167 data->ak4396_regs[0][AK4396_CONTROL_2]);
168 ak4396_write(chip, i, AK4396_CONTROL_3,
169 AK4396_PCM);
170 ak4396_write(chip, i, AK4396_LCH_ATT,
171 chip->dac_volume[i * 2]);
172 ak4396_write(chip, i, AK4396_RCH_ATT,
173 chip->dac_volume[i * 2 + 1]);
d0ce9946 174 }
75146fc0
CL		 175}
176
177static void ak4396_init(struct oxygen *chip)
178{
179 struct generic_data *data = chip->model_data;
180
45c1de8e 181 data->dacs = chip->model.dac_channels / 2;
6f0de3ce
CL		 182 data->ak4396_regs[0][AK4396_CONTROL_2] =
183 AK4396_SMUTE | AK4396_DEM_OFF | AK4396_DFS_NORMAL;
75146fc0 184 ak4396_registers_init(chip);
d0ce9946
CL		 185 snd_component_add(chip->card, "AK4396");
186}
187
188static void ak5385_init(struct oxygen *chip)
189{
878ac3ee
CL		 190 oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_AK5385_DFS_MASK);
191 oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_AK5385_DFS_MASK);
d0ce9946
CL		 192 snd_component_add(chip->card, "AK5385");
193}
194
75146fc0 195static void wm8785_registers_init(struct oxygen *chip)
d0ce9946 196{
e58aee95
CL		 197 struct generic_data *data = chip->model_data;
198
878ac3ee 199 wm8785_write(chip, WM8785_R7, 0);
6f0de3ce 200 wm8785_write(chip, WM8785_R0, data->wm8785_regs[0]);
1ff04886 201 wm8785_write(chip, WM8785_R2, data->wm8785_regs[2]);
75146fc0 202}
e58aee95 203
75146fc0
CL		 204static void wm8785_init(struct oxygen *chip)
205{
206 struct generic_data *data = chip->model_data;
207
6f0de3ce
CL		 208 data->wm8785_regs[0] =
209 WM8785_MCR_SLAVE | WM8785_OSR_SINGLE | WM8785_FORMAT_LJUST;
1ff04886 210 data->wm8785_regs[2] = WM8785_HPFR | WM8785_HPFL;
75146fc0 211 wm8785_registers_init(chip);
d0ce9946
CL		 212 snd_component_add(chip->card, "WM8785");
213}
214
215static void generic_init(struct oxygen *chip)
216{
217 ak4396_init(chip);
218 wm8785_init(chip);
219}
220
221static void meridian_init(struct oxygen *chip)
222{
223 ak4396_init(chip);
224 ak5385_init(chip);
225}
226
873591db
CL		 227static void claro_enable_hp(struct oxygen *chip)
228{
229 msleep(300);
230 oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_CLARO_HP);
231 oxygen_set_bits16(chip, OXYGEN_GPIO_DATA, GPIO_CLARO_HP);
232}
233
234static void claro_init(struct oxygen *chip)
235{
236 ak4396_init(chip);
237 wm8785_init(chip);
238 claro_enable_hp(chip);
239}
240
241static void claro_halo_init(struct oxygen *chip)
d91b424d
CL		 242{
243 ak4396_init(chip);
244 ak5385_init(chip);
873591db 245 claro_enable_hp(chip);
d91b424d
CL		 246}
247
2146dcfd 248static void fantasia_init(struct oxygen *chip)
45c1de8e
CL		 249{
250 ak4396_init(chip);
251 snd_component_add(chip->card, "CS5340");
252}
253
2146dcfd 254static void stereo_output_init(struct oxygen *chip)
31f86bac
CL		 255{
256 ak4396_init(chip);
257}
258
d0ce9946
CL		 259static void generic_cleanup(struct oxygen *chip)
260{
261}
262
873591db
CL		 263static void claro_disable_hp(struct oxygen *chip)
264{
265 oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_CLARO_HP);
266}
267
268static void claro_cleanup(struct oxygen *chip)
269{
270 claro_disable_hp(chip);
271}
272
273static void claro_suspend(struct oxygen *chip)
274{
275 claro_disable_hp(chip);
276}
277
4a4bc53b
CL		 278static void generic_resume(struct oxygen *chip)
279{
280 ak4396_registers_init(chip);
281 wm8785_registers_init(chip);
282}
283
c2bc4ff5
CL		 284static void meridian_resume(struct oxygen *chip)
285{
286 ak4396_registers_init(chip);
287}
288
873591db 289static void claro_resume(struct oxygen *chip)
d91b424d
CL		 290{
291 ak4396_registers_init(chip);
873591db 292 claro_enable_hp(chip);
d91b424d
CL		 293}
294
45c1de8e
CL		 295static void stereo_resume(struct oxygen *chip)
296{
297 ak4396_registers_init(chip);
298}
299
d0ce9946
CL		 300static void set_ak4396_params(struct oxygen *chip,
301 struct snd_pcm_hw_params *params)
302{
7ef37cd9 303 struct generic_data *data = chip->model_data;
d0ce9946
CL		 304 unsigned int i;
305 u8 value;
306
6f0de3ce 307 value = data->ak4396_regs[0][AK4396_CONTROL_2] & ~AK4396_DFS_MASK;
d0ce9946
CL		 308 if (params_rate(params) <= 54000)
309 value |= AK4396_DFS_NORMAL;
236c4920 310 else if (params_rate(params) <= 108000)
d0ce9946
CL		 311 value |= AK4396_DFS_DOUBLE;
312 else
313 value |= AK4396_DFS_QUAD;
df91bc23
CL		 314
315 msleep(1); /* wait for the new MCLK to become stable */
316
6f0de3ce 317 if (value != data->ak4396_regs[0][AK4396_CONTROL_2]) {
45c1de8e 318 for (i = 0; i < data->dacs; ++i) {
6f0de3ce
CL		 319 ak4396_write(chip, i, AK4396_CONTROL_1,
320 AK4396_DIF_24_MSB);
321 ak4396_write(chip, i, AK4396_CONTROL_2, value);
322 ak4396_write(chip, i, AK4396_CONTROL_1,
323 AK4396_DIF_24_MSB | AK4396_RSTN);
324 }
325 }
326}
327
328static void update_ak4396_volume(struct oxygen *chip)
329{
45c1de8e 330 struct generic_data *data = chip->model_data;
6f0de3ce
CL		 331 unsigned int i;
332
45c1de8e 333 for (i = 0; i < data->dacs; ++i) {
6f0de3ce
CL		 334 ak4396_write_cached(chip, i, AK4396_LCH_ATT,
335 chip->dac_volume[i * 2]);
336 ak4396_write_cached(chip, i, AK4396_RCH_ATT,
337 chip->dac_volume[i * 2 + 1]);
d0ce9946
CL		 338 }
339}
340
d0ce9946
CL		 341static void update_ak4396_mute(struct oxygen *chip)
342{
7ef37cd9 343 struct generic_data *data = chip->model_data;
d0ce9946
CL		 344 unsigned int i;
345 u8 value;
346
6f0de3ce 347 value = data->ak4396_regs[0][AK4396_CONTROL_2] & ~AK4396_SMUTE;
d0ce9946
CL		 348 if (chip->dac_mute)
349 value |= AK4396_SMUTE;
45c1de8e 350 for (i = 0; i < data->dacs; ++i)
6f0de3ce 351 ak4396_write_cached(chip, i, AK4396_CONTROL_2, value);
d0ce9946
CL		 352}
353
354static void set_wm8785_params(struct oxygen *chip,
355 struct snd_pcm_hw_params *params)
356{
6f0de3ce 357 struct generic_data *data = chip->model_data;
d0ce9946
CL		 358 unsigned int value;
359
878ac3ee 360 value = WM8785_MCR_SLAVE | WM8785_FORMAT_LJUST;
71e22a4b
CL		 361 if (params_rate(params) <= 48000)
362 value |= WM8785_OSR_SINGLE;
363 else if (params_rate(params) <= 96000)
d0ce9946 364 value |= WM8785_OSR_DOUBLE;
d0ce9946 365 else
71e22a4b 366 value |= WM8785_OSR_QUAD;
6f0de3ce
CL		 367 if (value != data->wm8785_regs[0]) {
368 wm8785_write(chip, WM8785_R7, 0);
369 wm8785_write(chip, WM8785_R0, value);
1ff04886 370 wm8785_write(chip, WM8785_R2, data->wm8785_regs[2]);
6f0de3ce 371 }
d0ce9946
CL		 372}
373
374static void set_ak5385_params(struct oxygen *chip,
375 struct snd_pcm_hw_params *params)
376{
377 unsigned int value;
378
379 if (params_rate(params) <= 54000)
878ac3ee 380 value = GPIO_AK5385_DFS_NORMAL;
d0ce9946 381 else if (params_rate(params) <= 108000)
878ac3ee 382 value = GPIO_AK5385_DFS_DOUBLE;
d0ce9946 383 else
878ac3ee
CL		 384 value = GPIO_AK5385_DFS_QUAD;
385 oxygen_write16_masked(chip, OXYGEN_GPIO_DATA,
386 value, GPIO_AK5385_DFS_MASK);
d0ce9946
CL		 387}
388
45c1de8e
CL		 389static void set_no_params(struct oxygen *chip, struct snd_pcm_hw_params *params)
390{
391}
392
4852ad02
CL		 393static int rolloff_info(struct snd_kcontrol *ctl,
394 struct snd_ctl_elem_info *info)
395{
396 static const char *const names[2] = {
397 "Sharp Roll-off", "Slow Roll-off"
398 };
399
400 info->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
401 info->count = 1;
402 info->value.enumerated.items = 2;
403 if (info->value.enumerated.item >= 2)
404 info->value.enumerated.item = 1;
405 strcpy(info->value.enumerated.name, names[info->value.enumerated.item]);
406 return 0;
407}
408
409static int rolloff_get(struct snd_kcontrol *ctl,
410 struct snd_ctl_elem_value *value)
411{
412 struct oxygen *chip = ctl->private_data;
413 struct generic_data *data = chip->model_data;
414
415 value->value.enumerated.item[0] =
416 (data->ak4396_regs[0][AK4396_CONTROL_2] & AK4396_SLOW) != 0;
417 return 0;
418}
419
420static int rolloff_put(struct snd_kcontrol *ctl,
421 struct snd_ctl_elem_value *value)
422{
423 struct oxygen *chip = ctl->private_data;
424 struct generic_data *data = chip->model_data;
425 unsigned int i;
426 int changed;
427 u8 reg;
428
429 mutex_lock(&chip->mutex);
430 reg = data->ak4396_regs[0][AK4396_CONTROL_2];
431 if (value->value.enumerated.item[0])
432 reg |= AK4396_SLOW;
433 else
434 reg &= ~AK4396_SLOW;
435 changed = reg != data->ak4396_regs[0][AK4396_CONTROL_2];
436 if (changed) {
45c1de8e 437 for (i = 0; i < data->dacs; ++i)
4852ad02
CL		 438 ak4396_write(chip, i, AK4396_CONTROL_2, reg);
439 }
440 mutex_unlock(&chip->mutex);
441 return changed;
442}
443
444static const struct snd_kcontrol_new rolloff_control = {
445 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
446 .name = "DAC Filter Playback Enum",
447 .info = rolloff_info,
448 .get = rolloff_get,
449 .put = rolloff_put,
450};
451
1ff04886
CL		 452static int hpf_info(struct snd_kcontrol *ctl, struct snd_ctl_elem_info *info)
453{
454 static const char *const names[2] = {
455 "None", "High-pass Filter"
456 };
457
458 info->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
459 info->count = 1;
460 info->value.enumerated.items = 2;
461 if (info->value.enumerated.item >= 2)
462 info->value.enumerated.item = 1;
463 strcpy(info->value.enumerated.name, names[info->value.enumerated.item]);
464 return 0;
465}
466
467static int hpf_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value)
468{
469 struct oxygen *chip = ctl->private_data;
470 struct generic_data *data = chip->model_data;
471
472 value->value.enumerated.item[0] =
473 (data->wm8785_regs[WM8785_R2] & WM8785_HPFR) != 0;
474 return 0;
475}
476
477static int hpf_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value)
478{
479 struct oxygen *chip = ctl->private_data;
480 struct generic_data *data = chip->model_data;
481 unsigned int reg;
482 int changed;
483
484 mutex_lock(&chip->mutex);
485 reg = data->wm8785_regs[WM8785_R2] & ~(WM8785_HPFR | WM8785_HPFL);
486 if (value->value.enumerated.item[0])
487 reg |= WM8785_HPFR | WM8785_HPFL;
488 changed = reg != data->wm8785_regs[WM8785_R2];
489 if (changed)
490 wm8785_write(chip, WM8785_R2, reg);
491 mutex_unlock(&chip->mutex);
492 return changed;
493}
494
495static const struct snd_kcontrol_new hpf_control = {
496 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
497 .name = "ADC Filter Capture Enum",
498 .info = hpf_info,
499 .get = hpf_get,
500 .put = hpf_put,
501};
502
4852ad02
CL		 503static int generic_mixer_init(struct oxygen *chip)
504{
505 return snd_ctl_add(chip->card, snd_ctl_new1(&rolloff_control, chip));
506}
507
1ff04886
CL		 508static int generic_wm8785_mixer_init(struct oxygen *chip)
509{
510 int err;
511
512 err = generic_mixer_init(chip);
513 if (err < 0)
514 return err;
515 err = snd_ctl_add(chip->card, snd_ctl_new1(&hpf_control, chip));
516 if (err < 0)
517 return err;
518 return 0;
519}
520
d0ce9946
CL		 521static const DECLARE_TLV_DB_LINEAR(ak4396_db_scale, TLV_DB_GAIN_MUTE, 0);
522
523static const struct oxygen_model model_generic = {
524 .shortname = "C-Media CMI8788",
525 .longname = "C-Media Oxygen HD Audio",
526 .chip = "CMI8788",
d0ce9946 527 .init = generic_init,
1ff04886 528 .mixer_init = generic_wm8785_mixer_init,
d0ce9946 529 .cleanup = generic_cleanup,
4a4bc53b 530 .resume = generic_resume,
76ffe1e3 531 .get_i2s_mclk = oxygen_default_i2s_mclk,
d0ce9946
CL		 532 .set_dac_params = set_ak4396_params,
533 .set_adc_params = set_wm8785_params,
534 .update_dac_volume = update_ak4396_volume,
535 .update_dac_mute = update_ak4396_mute,
4972a177 536 .dac_tlv = ak4396_db_scale,
7ef37cd9 537 .model_data_size = sizeof(struct generic_data),
d76596b1
CL		 538 .device_config = PLAYBACK_0_TO_I2S |
539 PLAYBACK_1_TO_SPDIF |
540 PLAYBACK_2_TO_AC97_1 |
541 CAPTURE_0_FROM_I2S_1 |
542 CAPTURE_1_FROM_SPDIF |
b6ca8ab3
CL		 543 CAPTURE_2_FROM_AC97_1 |
544 AC97_CD_INPUT,
976cd627 545 .dac_channels = 8,
193e8138
CL		 546 .dac_volume_min = 0,
547 .dac_volume_max = 255,
87eedd2f
CL		 548 .function_flags = OXYGEN_FUNCTION_SPI |
549 OXYGEN_FUNCTION_ENABLE_SPI_4_5,
05855ba3
CL		 550 .dac_i2s_format = OXYGEN_I2S_FORMAT_LJUST,
551 .adc_i2s_format = OXYGEN_I2S_FORMAT_LJUST,
d0ce9946 552};
d0ce9946 553
30459d7b
CL		 554static int __devinit get_oxygen_model(struct oxygen *chip,
555 const struct pci_device_id *id)
556{
557 chip->model = model_generic;
558 switch (id->driver_data) {
559 case MODEL_MERIDIAN:
560 chip->model.init = meridian_init;
1ff04886 561 chip->model.mixer_init = generic_mixer_init;
30459d7b
CL		 562 chip->model.resume = meridian_resume;
563 chip->model.set_adc_params = set_ak5385_params;
564 chip->model.device_config = PLAYBACK_0_TO_I2S |
565 PLAYBACK_1_TO_SPDIF |
566 CAPTURE_0_FROM_I2S_2 |
567 CAPTURE_1_FROM_SPDIF;
568 break;
873591db
CL		 569 case MODEL_CLARO:
570 chip->model.init = claro_init;
571 chip->model.cleanup = claro_cleanup;
572 chip->model.suspend = claro_suspend;
573 chip->model.resume = claro_resume;
574 break;
575 case MODEL_CLARO_HALO:
576 chip->model.init = claro_halo_init;
1ff04886 577 chip->model.mixer_init = generic_mixer_init;
873591db
CL		 578 chip->model.cleanup = claro_cleanup;
579 chip->model.suspend = claro_suspend;
580 chip->model.resume = claro_resume;
d91b424d 581 chip->model.set_adc_params = set_ak5385_params;
0873a5ae
ES		 582 chip->model.device_config = PLAYBACK_0_TO_I2S |
583 PLAYBACK_1_TO_SPDIF |
584 CAPTURE_0_FROM_I2S_2 |
585 CAPTURE_1_FROM_SPDIF;
d91b424d 586 break;
2146dcfd
CL		 587 case MODEL_FANTASIA:
588 case MODEL_2CH_OUTPUT:
45c1de8e
CL		 589 chip->model.shortname = "C-Media CMI8787";
590 chip->model.chip = "CMI8787";
2146dcfd
CL		 591 if (id->driver_data == MODEL_FANTASIA)
592 chip->model.init = fantasia_init;
31f86bac 593 else
2146dcfd 594 chip->model.init = stereo_output_init;
45c1de8e
CL		 595 chip->model.resume = stereo_resume;
596 chip->model.mixer_init = generic_mixer_init;
597 chip->model.set_adc_params = set_no_params;
598 chip->model.device_config = PLAYBACK_0_TO_I2S |
31f86bac 599 PLAYBACK_1_TO_SPDIF;
2146dcfd 600 if (id->driver_data == MODEL_FANTASIA)
31f86bac 601 chip->model.device_config |= CAPTURE_0_FROM_I2S_1;
45c1de8e
CL		 602 chip->model.dac_channels = 2;
603 break;
30459d7b
CL		 604 }
605 if (id->driver_data == MODEL_MERIDIAN ||
873591db 606 id->driver_data == MODEL_CLARO_HALO) {
30459d7b
CL		 607 chip->model.misc_flags = OXYGEN_MISC_MIDI;
608 chip->model.device_config |= MIDI_OUTPUT | MIDI_INPUT;
609 }
610 return 0;
611}
612
d0ce9946
CL		 613static int __devinit generic_oxygen_probe(struct pci_dev *pci,
614 const struct pci_device_id *pci_id)
615{
616 static int dev;
d0ce9946
CL		 617 int err;
618
619 if (dev >= SNDRV_CARDS)
620 return -ENODEV;
621 if (!enable[dev]) {
622 ++dev;
623 return -ENOENT;
624 }
bb718588 625 err = oxygen_pci_probe(pci, index[dev], id[dev], THIS_MODULE,
30459d7b 626 oxygen_ids, get_oxygen_model);
d0ce9946
CL		 627 if (err >= 0)
628 ++dev;
629 return err;
630}
631
632static struct pci_driver oxygen_driver = {
633 .name = "CMI8788",
634 .id_table = oxygen_ids,
635 .probe = generic_oxygen_probe,
636 .remove = __devexit_p(oxygen_pci_remove),
4a4bc53b
CL		 637#ifdef CONFIG_PM
638 .suspend = oxygen_pci_suspend,
639 .resume = oxygen_pci_resume,
640#endif
d0ce9946
CL		 641};
642
643static int __init alsa_card_oxygen_init(void)
644{
645 return pci_register_driver(&oxygen_driver);
646}
647
648static void __exit alsa_card_oxygen_exit(void)
649{
650 pci_unregister_driver(&oxygen_driver);
651}
652
653module_init(alsa_card_oxygen_init)
654module_exit(alsa_card_oxygen_exit)
Linux 6.x block layer and io_uring tree(s)