Commit | Line | Data |
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d0ce9946 | 1 | /* |
873591db | 2 | * C-Media CMI8788 driver for C-Media's reference design and similar models |
d0ce9946 CL |
3 | * |
4 | * Copyright (c) Clemens Ladisch <clemens@ladisch.de> | |
5 | * | |
6 | * | |
7 | * This driver is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License, version 2. | |
9 | * | |
10 | * This driver is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this driver; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | /* | |
dc0adf48 CL |
21 | * CMI8788: |
22 | * | |
de664936 CL |
23 | * SPI 0 -> 1st AK4396 (front) |
24 | * SPI 1 -> 2nd AK4396 (surround) | |
25 | * SPI 2 -> 3rd AK4396 (center/LFE) | |
26 | * SPI 3 -> WM8785 | |
27 | * SPI 4 -> 4th AK4396 (back) | |
d0ce9946 | 28 | * |
de664936 CL |
29 | * GPIO 0 -> DFS0 of AK5385 |
30 | * GPIO 1 -> DFS1 of AK5385 | |
31 | * GPIO 8 -> enable headphone amplifier on HT-Omega models | |
dc0adf48 CL |
32 | * |
33 | * CM9780: | |
34 | * | |
de664936 CL |
35 | * LINE_OUT -> input of ADC |
36 | * | |
37 | * AUX_IN <- aux | |
38 | * CD_IN <- CD | |
39 | * MIC_IN <- mic | |
40 | * | |
41 | * GPO 0 -> route line-in (0) or AC97 output (1) to ADC input | |
d0ce9946 CL |
42 | */ |
43 | ||
df91bc23 | 44 | #include <linux/delay.h> |
902b05c1 | 45 | #include <linux/mutex.h> |
d0ce9946 | 46 | #include <linux/pci.h> |
902b05c1 | 47 | #include <sound/ac97_codec.h> |
ccc80fb4 | 48 | #include <sound/control.h> |
d0ce9946 | 49 | #include <sound/core.h> |
9719fcaa | 50 | #include <sound/info.h> |
d0ce9946 CL |
51 | #include <sound/initval.h> |
52 | #include <sound/pcm.h> | |
53 | #include <sound/pcm_params.h> | |
54 | #include <sound/tlv.h> | |
55 | #include "oxygen.h" | |
66410bfd | 56 | #include "xonar_dg.h" |
c626026d | 57 | #include "ak4396.h" |
f5b2368b | 58 | #include "wm8785.h" |
d0ce9946 CL |
59 | |
60 | MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>"); | |
61 | MODULE_DESCRIPTION("C-Media CMI8788 driver"); | |
d023dc0a | 62 | MODULE_LICENSE("GPL v2"); |
66410bfd CL |
63 | MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8786}" |
64 | ",{C-Media,CMI8787}" | |
65 | ",{C-Media,CMI8788}}"); | |
d0ce9946 CL |
66 | |
67 | static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; | |
68 | static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; | |
69 | static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; | |
70 | ||
71 | module_param_array(index, int, NULL, 0444); | |
72 | MODULE_PARM_DESC(index, "card index"); | |
73 | module_param_array(id, charp, NULL, 0444); | |
74 | MODULE_PARM_DESC(id, "ID string"); | |
75 | module_param_array(enable, bool, NULL, 0444); | |
76 | MODULE_PARM_DESC(enable, "enable card"); | |
77 | ||
2f1b0ec7 | 78 | enum { |
18f24839 CL |
79 | MODEL_CMEDIA_REF, |
80 | MODEL_MERIDIAN, | |
81 | MODEL_CLARO, | |
82 | MODEL_CLARO_HALO, | |
2146dcfd CL |
83 | MODEL_FANTASIA, |
84 | MODEL_2CH_OUTPUT, | |
66410bfd | 85 | MODEL_XONAR_DG, |
2f1b0ec7 CL |
86 | }; |
87 | ||
cebe41d4 | 88 | static DEFINE_PCI_DEVICE_TABLE(oxygen_ids) = { |
18f24839 | 89 | /* C-Media's reference design */ |
2f1b0ec7 | 90 | { OXYGEN_PCI_SUBID(0x10b0, 0x0216), .driver_data = MODEL_CMEDIA_REF }, |
8c50b759 | 91 | { OXYGEN_PCI_SUBID(0x10b0, 0x0217), .driver_data = MODEL_CMEDIA_REF }, |
2f1b0ec7 CL |
92 | { OXYGEN_PCI_SUBID(0x10b0, 0x0218), .driver_data = MODEL_CMEDIA_REF }, |
93 | { OXYGEN_PCI_SUBID(0x10b0, 0x0219), .driver_data = MODEL_CMEDIA_REF }, | |
94 | { OXYGEN_PCI_SUBID(0x13f6, 0x0001), .driver_data = MODEL_CMEDIA_REF }, | |
95 | { OXYGEN_PCI_SUBID(0x13f6, 0x0010), .driver_data = MODEL_CMEDIA_REF }, | |
96 | { OXYGEN_PCI_SUBID(0x13f6, 0x8788), .driver_data = MODEL_CMEDIA_REF }, | |
97 | { OXYGEN_PCI_SUBID(0x147a, 0xa017), .driver_data = MODEL_CMEDIA_REF }, | |
18f24839 | 98 | { OXYGEN_PCI_SUBID(0x1a58, 0x0910), .driver_data = MODEL_CMEDIA_REF }, |
66410bfd CL |
99 | /* Asus Xonar DG */ |
100 | { OXYGEN_PCI_SUBID(0x1043, 0x8467), .driver_data = MODEL_XONAR_DG }, | |
8c50b759 CL |
101 | /* PCI 2.0 HD Audio */ |
102 | { OXYGEN_PCI_SUBID(0x13f6, 0x8782), .driver_data = MODEL_2CH_OUTPUT }, | |
18f24839 | 103 | /* Kuroutoshikou CMI8787-HG2PCI */ |
2146dcfd | 104 | { OXYGEN_PCI_SUBID(0x13f6, 0xffff), .driver_data = MODEL_2CH_OUTPUT }, |
18f24839 | 105 | /* TempoTec HiFier Fantasia */ |
2146dcfd CL |
106 | { OXYGEN_PCI_SUBID(0x14c3, 0x1710), .driver_data = MODEL_FANTASIA }, |
107 | /* TempoTec HiFier Serenade */ | |
108 | { OXYGEN_PCI_SUBID(0x14c3, 0x1711), .driver_data = MODEL_2CH_OUTPUT }, | |
18f24839 | 109 | /* AuzenTech X-Meridian */ |
2f1b0ec7 | 110 | { OXYGEN_PCI_SUBID(0x415a, 0x5431), .driver_data = MODEL_MERIDIAN }, |
8443d2eb CL |
111 | /* AuzenTech X-Meridian 2G */ |
112 | { OXYGEN_PCI_SUBID(0x5431, 0x017a), .driver_data = MODEL_MERIDIAN }, | |
18f24839 | 113 | /* HT-Omega Claro */ |
873591db | 114 | { OXYGEN_PCI_SUBID(0x7284, 0x9761), .driver_data = MODEL_CLARO }, |
18f24839 | 115 | /* HT-Omega Claro halo */ |
873591db | 116 | { OXYGEN_PCI_SUBID(0x7284, 0x9781), .driver_data = MODEL_CLARO_HALO }, |
d0ce9946 CL |
117 | { } |
118 | }; | |
119 | MODULE_DEVICE_TABLE(pci, oxygen_ids); | |
120 | ||
878ac3ee CL |
121 | |
122 | #define GPIO_AK5385_DFS_MASK 0x0003 | |
123 | #define GPIO_AK5385_DFS_NORMAL 0x0000 | |
124 | #define GPIO_AK5385_DFS_DOUBLE 0x0001 | |
125 | #define GPIO_AK5385_DFS_QUAD 0x0002 | |
126 | ||
873591db CL |
127 | #define GPIO_CLARO_HP 0x0100 |
128 | ||
7ef37cd9 | 129 | struct generic_data { |
45c1de8e | 130 | unsigned int dacs; |
6f0de3ce | 131 | u8 ak4396_regs[4][5]; |
1ff04886 | 132 | u16 wm8785_regs[3]; |
7ef37cd9 CL |
133 | }; |
134 | ||
d0ce9946 CL |
135 | static void ak4396_write(struct oxygen *chip, unsigned int codec, |
136 | u8 reg, u8 value) | |
137 | { | |
138 | /* maps ALSA channel pair number to SPI output */ | |
139 | static const u8 codec_spi_map[4] = { | |
7113e958 | 140 | 0, 1, 2, 4 |
d0ce9946 | 141 | }; |
6f0de3ce CL |
142 | struct generic_data *data = chip->model_data; |
143 | ||
c2353a08 | 144 | oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER | |
d0ce9946 | 145 | OXYGEN_SPI_DATA_LENGTH_2 | |
2ea85986 | 146 | OXYGEN_SPI_CLOCK_160 | |
d0ce9946 | 147 | (codec_spi_map[codec] << OXYGEN_SPI_CODEC_SHIFT) | |
c2353a08 | 148 | OXYGEN_SPI_CEN_LATCH_CLOCK_HI, |
d0ce9946 | 149 | AK4396_WRITE | (reg << 8) | value); |
6f0de3ce CL |
150 | data->ak4396_regs[codec][reg] = value; |
151 | } | |
152 | ||
153 | static void ak4396_write_cached(struct oxygen *chip, unsigned int codec, | |
154 | u8 reg, u8 value) | |
155 | { | |
156 | struct generic_data *data = chip->model_data; | |
157 | ||
158 | if (value != data->ak4396_regs[codec][reg]) | |
159 | ak4396_write(chip, codec, reg, value); | |
d0ce9946 CL |
160 | } |
161 | ||
162 | static void wm8785_write(struct oxygen *chip, u8 reg, unsigned int value) | |
163 | { | |
e58aee95 CL |
164 | struct generic_data *data = chip->model_data; |
165 | ||
c2353a08 | 166 | oxygen_write_spi(chip, OXYGEN_SPI_TRIGGER | |
d0ce9946 | 167 | OXYGEN_SPI_DATA_LENGTH_2 | |
2ea85986 | 168 | OXYGEN_SPI_CLOCK_160 | |
c2353a08 CL |
169 | (3 << OXYGEN_SPI_CODEC_SHIFT) | |
170 | OXYGEN_SPI_CEN_LATCH_CLOCK_LO, | |
d0ce9946 | 171 | (reg << 9) | value); |
6f0de3ce CL |
172 | if (reg < ARRAY_SIZE(data->wm8785_regs)) |
173 | data->wm8785_regs[reg] = value; | |
bbbfb552 CL |
174 | } |
175 | ||
75146fc0 | 176 | static void ak4396_registers_init(struct oxygen *chip) |
d0ce9946 | 177 | { |
7ef37cd9 | 178 | struct generic_data *data = chip->model_data; |
d0ce9946 CL |
179 | unsigned int i; |
180 | ||
45c1de8e | 181 | for (i = 0; i < data->dacs; ++i) { |
6f0de3ce CL |
182 | ak4396_write(chip, i, AK4396_CONTROL_1, |
183 | AK4396_DIF_24_MSB | AK4396_RSTN); | |
184 | ak4396_write(chip, i, AK4396_CONTROL_2, | |
185 | data->ak4396_regs[0][AK4396_CONTROL_2]); | |
186 | ak4396_write(chip, i, AK4396_CONTROL_3, | |
187 | AK4396_PCM); | |
188 | ak4396_write(chip, i, AK4396_LCH_ATT, | |
189 | chip->dac_volume[i * 2]); | |
190 | ak4396_write(chip, i, AK4396_RCH_ATT, | |
191 | chip->dac_volume[i * 2 + 1]); | |
d0ce9946 | 192 | } |
75146fc0 CL |
193 | } |
194 | ||
195 | static void ak4396_init(struct oxygen *chip) | |
196 | { | |
197 | struct generic_data *data = chip->model_data; | |
198 | ||
1f4d7be7 | 199 | data->dacs = chip->model.dac_channels_pcm / 2; |
6f0de3ce CL |
200 | data->ak4396_regs[0][AK4396_CONTROL_2] = |
201 | AK4396_SMUTE | AK4396_DEM_OFF | AK4396_DFS_NORMAL; | |
75146fc0 | 202 | ak4396_registers_init(chip); |
d0ce9946 CL |
203 | snd_component_add(chip->card, "AK4396"); |
204 | } | |
205 | ||
206 | static void ak5385_init(struct oxygen *chip) | |
207 | { | |
878ac3ee CL |
208 | oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_AK5385_DFS_MASK); |
209 | oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_AK5385_DFS_MASK); | |
d0ce9946 CL |
210 | snd_component_add(chip->card, "AK5385"); |
211 | } | |
212 | ||
75146fc0 | 213 | static void wm8785_registers_init(struct oxygen *chip) |
d0ce9946 | 214 | { |
e58aee95 CL |
215 | struct generic_data *data = chip->model_data; |
216 | ||
878ac3ee | 217 | wm8785_write(chip, WM8785_R7, 0); |
6f0de3ce | 218 | wm8785_write(chip, WM8785_R0, data->wm8785_regs[0]); |
1ff04886 | 219 | wm8785_write(chip, WM8785_R2, data->wm8785_regs[2]); |
75146fc0 | 220 | } |
e58aee95 | 221 | |
75146fc0 CL |
222 | static void wm8785_init(struct oxygen *chip) |
223 | { | |
224 | struct generic_data *data = chip->model_data; | |
225 | ||
6f0de3ce CL |
226 | data->wm8785_regs[0] = |
227 | WM8785_MCR_SLAVE | WM8785_OSR_SINGLE | WM8785_FORMAT_LJUST; | |
1ff04886 | 228 | data->wm8785_regs[2] = WM8785_HPFR | WM8785_HPFL; |
75146fc0 | 229 | wm8785_registers_init(chip); |
d0ce9946 CL |
230 | snd_component_add(chip->card, "WM8785"); |
231 | } | |
232 | ||
233 | static void generic_init(struct oxygen *chip) | |
234 | { | |
235 | ak4396_init(chip); | |
236 | wm8785_init(chip); | |
237 | } | |
238 | ||
239 | static void meridian_init(struct oxygen *chip) | |
240 | { | |
241 | ak4396_init(chip); | |
242 | ak5385_init(chip); | |
243 | } | |
244 | ||
873591db CL |
245 | static void claro_enable_hp(struct oxygen *chip) |
246 | { | |
247 | msleep(300); | |
248 | oxygen_set_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_CLARO_HP); | |
249 | oxygen_set_bits16(chip, OXYGEN_GPIO_DATA, GPIO_CLARO_HP); | |
250 | } | |
251 | ||
252 | static void claro_init(struct oxygen *chip) | |
253 | { | |
254 | ak4396_init(chip); | |
255 | wm8785_init(chip); | |
256 | claro_enable_hp(chip); | |
257 | } | |
258 | ||
259 | static void claro_halo_init(struct oxygen *chip) | |
d91b424d CL |
260 | { |
261 | ak4396_init(chip); | |
262 | ak5385_init(chip); | |
873591db | 263 | claro_enable_hp(chip); |
d91b424d CL |
264 | } |
265 | ||
2146dcfd | 266 | static void fantasia_init(struct oxygen *chip) |
45c1de8e CL |
267 | { |
268 | ak4396_init(chip); | |
269 | snd_component_add(chip->card, "CS5340"); | |
270 | } | |
271 | ||
2146dcfd | 272 | static void stereo_output_init(struct oxygen *chip) |
31f86bac CL |
273 | { |
274 | ak4396_init(chip); | |
275 | } | |
276 | ||
d0ce9946 CL |
277 | static void generic_cleanup(struct oxygen *chip) |
278 | { | |
279 | } | |
280 | ||
873591db CL |
281 | static void claro_disable_hp(struct oxygen *chip) |
282 | { | |
283 | oxygen_clear_bits16(chip, OXYGEN_GPIO_DATA, GPIO_CLARO_HP); | |
284 | } | |
285 | ||
286 | static void claro_cleanup(struct oxygen *chip) | |
287 | { | |
288 | claro_disable_hp(chip); | |
289 | } | |
290 | ||
291 | static void claro_suspend(struct oxygen *chip) | |
292 | { | |
293 | claro_disable_hp(chip); | |
294 | } | |
295 | ||
4a4bc53b CL |
296 | static void generic_resume(struct oxygen *chip) |
297 | { | |
298 | ak4396_registers_init(chip); | |
299 | wm8785_registers_init(chip); | |
300 | } | |
301 | ||
c2bc4ff5 CL |
302 | static void meridian_resume(struct oxygen *chip) |
303 | { | |
304 | ak4396_registers_init(chip); | |
305 | } | |
306 | ||
873591db | 307 | static void claro_resume(struct oxygen *chip) |
d91b424d CL |
308 | { |
309 | ak4396_registers_init(chip); | |
873591db | 310 | claro_enable_hp(chip); |
d91b424d CL |
311 | } |
312 | ||
45c1de8e CL |
313 | static void stereo_resume(struct oxygen *chip) |
314 | { | |
315 | ak4396_registers_init(chip); | |
316 | } | |
317 | ||
d0ce9946 CL |
318 | static void set_ak4396_params(struct oxygen *chip, |
319 | struct snd_pcm_hw_params *params) | |
320 | { | |
7ef37cd9 | 321 | struct generic_data *data = chip->model_data; |
d0ce9946 CL |
322 | unsigned int i; |
323 | u8 value; | |
324 | ||
6f0de3ce | 325 | value = data->ak4396_regs[0][AK4396_CONTROL_2] & ~AK4396_DFS_MASK; |
d0ce9946 CL |
326 | if (params_rate(params) <= 54000) |
327 | value |= AK4396_DFS_NORMAL; | |
236c4920 | 328 | else if (params_rate(params) <= 108000) |
d0ce9946 CL |
329 | value |= AK4396_DFS_DOUBLE; |
330 | else | |
331 | value |= AK4396_DFS_QUAD; | |
df91bc23 CL |
332 | |
333 | msleep(1); /* wait for the new MCLK to become stable */ | |
334 | ||
6f0de3ce | 335 | if (value != data->ak4396_regs[0][AK4396_CONTROL_2]) { |
45c1de8e | 336 | for (i = 0; i < data->dacs; ++i) { |
6f0de3ce CL |
337 | ak4396_write(chip, i, AK4396_CONTROL_1, |
338 | AK4396_DIF_24_MSB); | |
339 | ak4396_write(chip, i, AK4396_CONTROL_2, value); | |
340 | ak4396_write(chip, i, AK4396_CONTROL_1, | |
341 | AK4396_DIF_24_MSB | AK4396_RSTN); | |
342 | } | |
343 | } | |
344 | } | |
345 | ||
346 | static void update_ak4396_volume(struct oxygen *chip) | |
347 | { | |
45c1de8e | 348 | struct generic_data *data = chip->model_data; |
6f0de3ce CL |
349 | unsigned int i; |
350 | ||
45c1de8e | 351 | for (i = 0; i < data->dacs; ++i) { |
6f0de3ce CL |
352 | ak4396_write_cached(chip, i, AK4396_LCH_ATT, |
353 | chip->dac_volume[i * 2]); | |
354 | ak4396_write_cached(chip, i, AK4396_RCH_ATT, | |
355 | chip->dac_volume[i * 2 + 1]); | |
d0ce9946 CL |
356 | } |
357 | } | |
358 | ||
d0ce9946 CL |
359 | static void update_ak4396_mute(struct oxygen *chip) |
360 | { | |
7ef37cd9 | 361 | struct generic_data *data = chip->model_data; |
d0ce9946 CL |
362 | unsigned int i; |
363 | u8 value; | |
364 | ||
6f0de3ce | 365 | value = data->ak4396_regs[0][AK4396_CONTROL_2] & ~AK4396_SMUTE; |
d0ce9946 CL |
366 | if (chip->dac_mute) |
367 | value |= AK4396_SMUTE; | |
45c1de8e | 368 | for (i = 0; i < data->dacs; ++i) |
6f0de3ce | 369 | ak4396_write_cached(chip, i, AK4396_CONTROL_2, value); |
d0ce9946 CL |
370 | } |
371 | ||
372 | static void set_wm8785_params(struct oxygen *chip, | |
373 | struct snd_pcm_hw_params *params) | |
374 | { | |
6f0de3ce | 375 | struct generic_data *data = chip->model_data; |
d0ce9946 CL |
376 | unsigned int value; |
377 | ||
878ac3ee | 378 | value = WM8785_MCR_SLAVE | WM8785_FORMAT_LJUST; |
71e22a4b CL |
379 | if (params_rate(params) <= 48000) |
380 | value |= WM8785_OSR_SINGLE; | |
381 | else if (params_rate(params) <= 96000) | |
d0ce9946 | 382 | value |= WM8785_OSR_DOUBLE; |
d0ce9946 | 383 | else |
71e22a4b | 384 | value |= WM8785_OSR_QUAD; |
6f0de3ce CL |
385 | if (value != data->wm8785_regs[0]) { |
386 | wm8785_write(chip, WM8785_R7, 0); | |
387 | wm8785_write(chip, WM8785_R0, value); | |
1ff04886 | 388 | wm8785_write(chip, WM8785_R2, data->wm8785_regs[2]); |
6f0de3ce | 389 | } |
d0ce9946 CL |
390 | } |
391 | ||
392 | static void set_ak5385_params(struct oxygen *chip, | |
393 | struct snd_pcm_hw_params *params) | |
394 | { | |
395 | unsigned int value; | |
396 | ||
397 | if (params_rate(params) <= 54000) | |
878ac3ee | 398 | value = GPIO_AK5385_DFS_NORMAL; |
d0ce9946 | 399 | else if (params_rate(params) <= 108000) |
878ac3ee | 400 | value = GPIO_AK5385_DFS_DOUBLE; |
d0ce9946 | 401 | else |
878ac3ee CL |
402 | value = GPIO_AK5385_DFS_QUAD; |
403 | oxygen_write16_masked(chip, OXYGEN_GPIO_DATA, | |
404 | value, GPIO_AK5385_DFS_MASK); | |
d0ce9946 CL |
405 | } |
406 | ||
45c1de8e CL |
407 | static void set_no_params(struct oxygen *chip, struct snd_pcm_hw_params *params) |
408 | { | |
409 | } | |
410 | ||
4852ad02 CL |
411 | static int rolloff_info(struct snd_kcontrol *ctl, |
412 | struct snd_ctl_elem_info *info) | |
413 | { | |
414 | static const char *const names[2] = { | |
415 | "Sharp Roll-off", "Slow Roll-off" | |
416 | }; | |
417 | ||
418 | info->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
419 | info->count = 1; | |
420 | info->value.enumerated.items = 2; | |
421 | if (info->value.enumerated.item >= 2) | |
422 | info->value.enumerated.item = 1; | |
423 | strcpy(info->value.enumerated.name, names[info->value.enumerated.item]); | |
424 | return 0; | |
425 | } | |
426 | ||
427 | static int rolloff_get(struct snd_kcontrol *ctl, | |
428 | struct snd_ctl_elem_value *value) | |
429 | { | |
430 | struct oxygen *chip = ctl->private_data; | |
431 | struct generic_data *data = chip->model_data; | |
432 | ||
433 | value->value.enumerated.item[0] = | |
434 | (data->ak4396_regs[0][AK4396_CONTROL_2] & AK4396_SLOW) != 0; | |
435 | return 0; | |
436 | } | |
437 | ||
438 | static int rolloff_put(struct snd_kcontrol *ctl, | |
439 | struct snd_ctl_elem_value *value) | |
440 | { | |
441 | struct oxygen *chip = ctl->private_data; | |
442 | struct generic_data *data = chip->model_data; | |
443 | unsigned int i; | |
444 | int changed; | |
445 | u8 reg; | |
446 | ||
447 | mutex_lock(&chip->mutex); | |
448 | reg = data->ak4396_regs[0][AK4396_CONTROL_2]; | |
449 | if (value->value.enumerated.item[0]) | |
450 | reg |= AK4396_SLOW; | |
451 | else | |
452 | reg &= ~AK4396_SLOW; | |
453 | changed = reg != data->ak4396_regs[0][AK4396_CONTROL_2]; | |
454 | if (changed) { | |
45c1de8e | 455 | for (i = 0; i < data->dacs; ++i) |
4852ad02 CL |
456 | ak4396_write(chip, i, AK4396_CONTROL_2, reg); |
457 | } | |
458 | mutex_unlock(&chip->mutex); | |
459 | return changed; | |
460 | } | |
461 | ||
462 | static const struct snd_kcontrol_new rolloff_control = { | |
463 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
464 | .name = "DAC Filter Playback Enum", | |
465 | .info = rolloff_info, | |
466 | .get = rolloff_get, | |
467 | .put = rolloff_put, | |
468 | }; | |
469 | ||
1ff04886 CL |
470 | static int hpf_info(struct snd_kcontrol *ctl, struct snd_ctl_elem_info *info) |
471 | { | |
472 | static const char *const names[2] = { | |
473 | "None", "High-pass Filter" | |
474 | }; | |
475 | ||
476 | info->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; | |
477 | info->count = 1; | |
478 | info->value.enumerated.items = 2; | |
479 | if (info->value.enumerated.item >= 2) | |
480 | info->value.enumerated.item = 1; | |
481 | strcpy(info->value.enumerated.name, names[info->value.enumerated.item]); | |
482 | return 0; | |
483 | } | |
484 | ||
485 | static int hpf_get(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) | |
486 | { | |
487 | struct oxygen *chip = ctl->private_data; | |
488 | struct generic_data *data = chip->model_data; | |
489 | ||
490 | value->value.enumerated.item[0] = | |
491 | (data->wm8785_regs[WM8785_R2] & WM8785_HPFR) != 0; | |
492 | return 0; | |
493 | } | |
494 | ||
495 | static int hpf_put(struct snd_kcontrol *ctl, struct snd_ctl_elem_value *value) | |
496 | { | |
497 | struct oxygen *chip = ctl->private_data; | |
498 | struct generic_data *data = chip->model_data; | |
499 | unsigned int reg; | |
500 | int changed; | |
501 | ||
502 | mutex_lock(&chip->mutex); | |
503 | reg = data->wm8785_regs[WM8785_R2] & ~(WM8785_HPFR | WM8785_HPFL); | |
504 | if (value->value.enumerated.item[0]) | |
505 | reg |= WM8785_HPFR | WM8785_HPFL; | |
506 | changed = reg != data->wm8785_regs[WM8785_R2]; | |
507 | if (changed) | |
508 | wm8785_write(chip, WM8785_R2, reg); | |
509 | mutex_unlock(&chip->mutex); | |
510 | return changed; | |
511 | } | |
512 | ||
513 | static const struct snd_kcontrol_new hpf_control = { | |
514 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
515 | .name = "ADC Filter Capture Enum", | |
516 | .info = hpf_info, | |
517 | .get = hpf_get, | |
518 | .put = hpf_put, | |
519 | }; | |
520 | ||
4852ad02 CL |
521 | static int generic_mixer_init(struct oxygen *chip) |
522 | { | |
523 | return snd_ctl_add(chip->card, snd_ctl_new1(&rolloff_control, chip)); | |
524 | } | |
525 | ||
1ff04886 CL |
526 | static int generic_wm8785_mixer_init(struct oxygen *chip) |
527 | { | |
528 | int err; | |
529 | ||
530 | err = generic_mixer_init(chip); | |
531 | if (err < 0) | |
532 | return err; | |
533 | err = snd_ctl_add(chip->card, snd_ctl_new1(&hpf_control, chip)); | |
534 | if (err < 0) | |
535 | return err; | |
536 | return 0; | |
537 | } | |
538 | ||
9719fcaa CL |
539 | static void dump_ak4396_registers(struct oxygen *chip, |
540 | struct snd_info_buffer *buffer) | |
541 | { | |
542 | struct generic_data *data = chip->model_data; | |
543 | unsigned int dac, i; | |
544 | ||
545 | for (dac = 0; dac < data->dacs; ++dac) { | |
546 | snd_iprintf(buffer, "\nAK4396 %u:", dac + 1); | |
547 | for (i = 0; i < 5; ++i) | |
548 | snd_iprintf(buffer, " %02x", data->ak4396_regs[dac][i]); | |
549 | } | |
550 | snd_iprintf(buffer, "\n"); | |
551 | } | |
552 | ||
553 | static void dump_wm8785_registers(struct oxygen *chip, | |
554 | struct snd_info_buffer *buffer) | |
555 | { | |
556 | struct generic_data *data = chip->model_data; | |
557 | unsigned int i; | |
558 | ||
559 | snd_iprintf(buffer, "\nWM8785:"); | |
560 | for (i = 0; i < 3; ++i) | |
561 | snd_iprintf(buffer, " %03x", data->wm8785_regs[i]); | |
562 | snd_iprintf(buffer, "\n"); | |
563 | } | |
564 | ||
565 | static void dump_oxygen_registers(struct oxygen *chip, | |
566 | struct snd_info_buffer *buffer) | |
567 | { | |
568 | dump_ak4396_registers(chip, buffer); | |
569 | dump_wm8785_registers(chip, buffer); | |
570 | } | |
571 | ||
d0ce9946 CL |
572 | static const DECLARE_TLV_DB_LINEAR(ak4396_db_scale, TLV_DB_GAIN_MUTE, 0); |
573 | ||
574 | static const struct oxygen_model model_generic = { | |
575 | .shortname = "C-Media CMI8788", | |
576 | .longname = "C-Media Oxygen HD Audio", | |
577 | .chip = "CMI8788", | |
d0ce9946 | 578 | .init = generic_init, |
1ff04886 | 579 | .mixer_init = generic_wm8785_mixer_init, |
d0ce9946 | 580 | .cleanup = generic_cleanup, |
4a4bc53b | 581 | .resume = generic_resume, |
d0ce9946 CL |
582 | .set_dac_params = set_ak4396_params, |
583 | .set_adc_params = set_wm8785_params, | |
584 | .update_dac_volume = update_ak4396_volume, | |
585 | .update_dac_mute = update_ak4396_mute, | |
9719fcaa | 586 | .dump_registers = dump_oxygen_registers, |
4972a177 | 587 | .dac_tlv = ak4396_db_scale, |
7ef37cd9 | 588 | .model_data_size = sizeof(struct generic_data), |
d76596b1 CL |
589 | .device_config = PLAYBACK_0_TO_I2S | |
590 | PLAYBACK_1_TO_SPDIF | | |
591 | PLAYBACK_2_TO_AC97_1 | | |
592 | CAPTURE_0_FROM_I2S_1 | | |
593 | CAPTURE_1_FROM_SPDIF | | |
b6ca8ab3 CL |
594 | CAPTURE_2_FROM_AC97_1 | |
595 | AC97_CD_INPUT, | |
1f4d7be7 CL |
596 | .dac_channels_pcm = 8, |
597 | .dac_channels_mixer = 8, | |
193e8138 CL |
598 | .dac_volume_min = 0, |
599 | .dac_volume_max = 255, | |
87eedd2f CL |
600 | .function_flags = OXYGEN_FUNCTION_SPI | |
601 | OXYGEN_FUNCTION_ENABLE_SPI_4_5, | |
ce2c4920 | 602 | .dac_mclks = OXYGEN_MCLKS(256, 128, 128), |
5b8bf2a5 | 603 | .adc_mclks = OXYGEN_MCLKS(256, 256, 128), |
05855ba3 CL |
604 | .dac_i2s_format = OXYGEN_I2S_FORMAT_LJUST, |
605 | .adc_i2s_format = OXYGEN_I2S_FORMAT_LJUST, | |
d0ce9946 | 606 | }; |
d0ce9946 | 607 | |
30459d7b CL |
608 | static int __devinit get_oxygen_model(struct oxygen *chip, |
609 | const struct pci_device_id *id) | |
610 | { | |
611 | chip->model = model_generic; | |
612 | switch (id->driver_data) { | |
613 | case MODEL_MERIDIAN: | |
614 | chip->model.init = meridian_init; | |
1ff04886 | 615 | chip->model.mixer_init = generic_mixer_init; |
30459d7b CL |
616 | chip->model.resume = meridian_resume; |
617 | chip->model.set_adc_params = set_ak5385_params; | |
9719fcaa | 618 | chip->model.dump_registers = dump_ak4396_registers; |
30459d7b CL |
619 | chip->model.device_config = PLAYBACK_0_TO_I2S | |
620 | PLAYBACK_1_TO_SPDIF | | |
621 | CAPTURE_0_FROM_I2S_2 | | |
622 | CAPTURE_1_FROM_SPDIF; | |
623 | break; | |
873591db CL |
624 | case MODEL_CLARO: |
625 | chip->model.init = claro_init; | |
626 | chip->model.cleanup = claro_cleanup; | |
627 | chip->model.suspend = claro_suspend; | |
628 | chip->model.resume = claro_resume; | |
629 | break; | |
630 | case MODEL_CLARO_HALO: | |
631 | chip->model.init = claro_halo_init; | |
1ff04886 | 632 | chip->model.mixer_init = generic_mixer_init; |
873591db CL |
633 | chip->model.cleanup = claro_cleanup; |
634 | chip->model.suspend = claro_suspend; | |
635 | chip->model.resume = claro_resume; | |
d91b424d | 636 | chip->model.set_adc_params = set_ak5385_params; |
9719fcaa | 637 | chip->model.dump_registers = dump_ak4396_registers; |
0873a5ae ES |
638 | chip->model.device_config = PLAYBACK_0_TO_I2S | |
639 | PLAYBACK_1_TO_SPDIF | | |
640 | CAPTURE_0_FROM_I2S_2 | | |
641 | CAPTURE_1_FROM_SPDIF; | |
d91b424d | 642 | break; |
2146dcfd CL |
643 | case MODEL_FANTASIA: |
644 | case MODEL_2CH_OUTPUT: | |
45c1de8e CL |
645 | chip->model.shortname = "C-Media CMI8787"; |
646 | chip->model.chip = "CMI8787"; | |
2146dcfd CL |
647 | if (id->driver_data == MODEL_FANTASIA) |
648 | chip->model.init = fantasia_init; | |
31f86bac | 649 | else |
2146dcfd | 650 | chip->model.init = stereo_output_init; |
45c1de8e CL |
651 | chip->model.resume = stereo_resume; |
652 | chip->model.mixer_init = generic_mixer_init; | |
653 | chip->model.set_adc_params = set_no_params; | |
9719fcaa | 654 | chip->model.dump_registers = dump_ak4396_registers; |
45c1de8e | 655 | chip->model.device_config = PLAYBACK_0_TO_I2S | |
31f86bac | 656 | PLAYBACK_1_TO_SPDIF; |
ce2c4920 | 657 | if (id->driver_data == MODEL_FANTASIA) { |
31f86bac | 658 | chip->model.device_config |= CAPTURE_0_FROM_I2S_1; |
ce2c4920 CL |
659 | chip->model.adc_mclks = OXYGEN_MCLKS(256, 128, 128); |
660 | } | |
1f4d7be7 CL |
661 | chip->model.dac_channels_pcm = 2; |
662 | chip->model.dac_channels_mixer = 2; | |
45c1de8e | 663 | break; |
66410bfd CL |
664 | case MODEL_XONAR_DG: |
665 | chip->model = model_xonar_dg; | |
666 | break; | |
30459d7b CL |
667 | } |
668 | if (id->driver_data == MODEL_MERIDIAN || | |
873591db | 669 | id->driver_data == MODEL_CLARO_HALO) { |
30459d7b CL |
670 | chip->model.misc_flags = OXYGEN_MISC_MIDI; |
671 | chip->model.device_config |= MIDI_OUTPUT | MIDI_INPUT; | |
672 | } | |
673 | return 0; | |
674 | } | |
675 | ||
d0ce9946 CL |
676 | static int __devinit generic_oxygen_probe(struct pci_dev *pci, |
677 | const struct pci_device_id *pci_id) | |
678 | { | |
679 | static int dev; | |
d0ce9946 CL |
680 | int err; |
681 | ||
682 | if (dev >= SNDRV_CARDS) | |
683 | return -ENODEV; | |
684 | if (!enable[dev]) { | |
685 | ++dev; | |
686 | return -ENOENT; | |
687 | } | |
bb718588 | 688 | err = oxygen_pci_probe(pci, index[dev], id[dev], THIS_MODULE, |
30459d7b | 689 | oxygen_ids, get_oxygen_model); |
d0ce9946 CL |
690 | if (err >= 0) |
691 | ++dev; | |
692 | return err; | |
693 | } | |
694 | ||
695 | static struct pci_driver oxygen_driver = { | |
696 | .name = "CMI8788", | |
697 | .id_table = oxygen_ids, | |
698 | .probe = generic_oxygen_probe, | |
699 | .remove = __devexit_p(oxygen_pci_remove), | |
4a4bc53b CL |
700 | #ifdef CONFIG_PM |
701 | .suspend = oxygen_pci_suspend, | |
702 | .resume = oxygen_pci_resume, | |
703 | #endif | |
d0ce9946 CL |
704 | }; |
705 | ||
706 | static int __init alsa_card_oxygen_init(void) | |
707 | { | |
708 | return pci_register_driver(&oxygen_driver); | |
709 | } | |
710 | ||
711 | static void __exit alsa_card_oxygen_exit(void) | |
712 | { | |
713 | pci_unregister_driver(&oxygen_driver); | |
714 | } | |
715 | ||
716 | module_init(alsa_card_oxygen_init) | |
717 | module_exit(alsa_card_oxygen_exit) |