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1a59d1b8 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
1da177e4 LT |
2 | /* |
3 | * Driver for ESS Maestro3/Allegro (ES1988) soundcards. | |
4 | * Copyright (c) 2000 by Zach Brown <zab@zabbo.net> | |
5 | * Takashi Iwai <tiwai@suse.de> | |
6 | * | |
7 | * Most of the hardware init stuffs are based on maestro3 driver for | |
8 | * OSS/Free by Zach Brown. Many thanks to Zach! | |
9 | * | |
1da177e4 LT |
10 | * ChangeLog: |
11 | * Aug. 27, 2001 | |
12 | * - Fixed deadlock on capture | |
13 | * - Added Canyon3D-2 support by Rob Riggs <rob@pangalactic.org> | |
1da177e4 LT |
14 | */ |
15 | ||
16 | #define CARD_NAME "ESS Maestro3/Allegro/Canyon3D-2" | |
17 | #define DRIVER_NAME "Maestro3" | |
18 | ||
6cbbfe1c | 19 | #include <linux/io.h> |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/pci.h> | |
9d2f928d | 24 | #include <linux/dma-mapping.h> |
1da177e4 LT |
25 | #include <linux/slab.h> |
26 | #include <linux/vmalloc.h> | |
65a77217 | 27 | #include <linux/module.h> |
81d7724a | 28 | #include <linux/firmware.h> |
eb581adf | 29 | #include <linux/input.h> |
1da177e4 LT |
30 | #include <sound/core.h> |
31 | #include <sound/info.h> | |
32 | #include <sound/control.h> | |
33 | #include <sound/pcm.h> | |
34 | #include <sound/mpu401.h> | |
35 | #include <sound/ac97_codec.h> | |
36 | #include <sound/initval.h> | |
81d7724a | 37 | #include <asm/byteorder.h> |
1da177e4 LT |
38 | |
39 | MODULE_AUTHOR("Zach Brown <zab@zabbo.net>, Takashi Iwai <tiwai@suse.de>"); | |
40 | MODULE_DESCRIPTION("ESS Maestro3 PCI"); | |
41 | MODULE_LICENSE("GPL"); | |
7e0af29d CL |
42 | MODULE_FIRMWARE("ess/maestro3_assp_kernel.fw"); |
43 | MODULE_FIRMWARE("ess/maestro3_assp_minisrc.fw"); | |
1da177e4 LT |
44 | |
45 | static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ | |
46 | static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ | |
a67ff6a5 RR |
47 | static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* all enabled */ |
48 | static bool external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1}; | |
1da177e4 LT |
49 | static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1}; |
50 | ||
51 | module_param_array(index, int, NULL, 0444); | |
52 | MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard."); | |
53 | module_param_array(id, charp, NULL, 0444); | |
54 | MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard."); | |
55 | module_param_array(enable, bool, NULL, 0444); | |
56 | MODULE_PARM_DESC(enable, "Enable this soundcard."); | |
57 | module_param_array(external_amp, bool, NULL, 0444); | |
58 | MODULE_PARM_DESC(external_amp, "Enable external amp for " CARD_NAME " soundcard."); | |
59 | module_param_array(amp_gpio, int, NULL, 0444); | |
60 | MODULE_PARM_DESC(amp_gpio, "GPIO pin number for external amp. (default = -1)"); | |
61 | ||
62 | #define MAX_PLAYBACKS 2 | |
63 | #define MAX_CAPTURES 1 | |
64 | #define NR_DSPS (MAX_PLAYBACKS + MAX_CAPTURES) | |
65 | ||
66 | ||
67 | /* | |
68 | * maestro3 registers | |
69 | */ | |
70 | ||
71 | /* Allegro PCI configuration registers */ | |
72 | #define PCI_LEGACY_AUDIO_CTRL 0x40 | |
73 | #define SOUND_BLASTER_ENABLE 0x00000001 | |
74 | #define FM_SYNTHESIS_ENABLE 0x00000002 | |
75 | #define GAME_PORT_ENABLE 0x00000004 | |
76 | #define MPU401_IO_ENABLE 0x00000008 | |
77 | #define MPU401_IRQ_ENABLE 0x00000010 | |
78 | #define ALIAS_10BIT_IO 0x00000020 | |
79 | #define SB_DMA_MASK 0x000000C0 | |
80 | #define SB_DMA_0 0x00000040 | |
81 | #define SB_DMA_1 0x00000040 | |
82 | #define SB_DMA_R 0x00000080 | |
83 | #define SB_DMA_3 0x000000C0 | |
84 | #define SB_IRQ_MASK 0x00000700 | |
85 | #define SB_IRQ_5 0x00000000 | |
86 | #define SB_IRQ_7 0x00000100 | |
87 | #define SB_IRQ_9 0x00000200 | |
88 | #define SB_IRQ_10 0x00000300 | |
89 | #define MIDI_IRQ_MASK 0x00003800 | |
90 | #define SERIAL_IRQ_ENABLE 0x00004000 | |
91 | #define DISABLE_LEGACY 0x00008000 | |
92 | ||
93 | #define PCI_ALLEGRO_CONFIG 0x50 | |
94 | #define SB_ADDR_240 0x00000004 | |
95 | #define MPU_ADDR_MASK 0x00000018 | |
96 | #define MPU_ADDR_330 0x00000000 | |
97 | #define MPU_ADDR_300 0x00000008 | |
98 | #define MPU_ADDR_320 0x00000010 | |
99 | #define MPU_ADDR_340 0x00000018 | |
100 | #define USE_PCI_TIMING 0x00000040 | |
101 | #define POSTED_WRITE_ENABLE 0x00000080 | |
102 | #define DMA_POLICY_MASK 0x00000700 | |
103 | #define DMA_DDMA 0x00000000 | |
104 | #define DMA_TDMA 0x00000100 | |
105 | #define DMA_PCPCI 0x00000200 | |
106 | #define DMA_WBDMA16 0x00000400 | |
107 | #define DMA_WBDMA4 0x00000500 | |
108 | #define DMA_WBDMA2 0x00000600 | |
109 | #define DMA_WBDMA1 0x00000700 | |
110 | #define DMA_SAFE_GUARD 0x00000800 | |
111 | #define HI_PERF_GP_ENABLE 0x00001000 | |
112 | #define PIC_SNOOP_MODE_0 0x00002000 | |
113 | #define PIC_SNOOP_MODE_1 0x00004000 | |
114 | #define SOUNDBLASTER_IRQ_MASK 0x00008000 | |
115 | #define RING_IN_ENABLE 0x00010000 | |
116 | #define SPDIF_TEST_MODE 0x00020000 | |
117 | #define CLK_MULT_MODE_SELECT_2 0x00040000 | |
118 | #define EEPROM_WRITE_ENABLE 0x00080000 | |
119 | #define CODEC_DIR_IN 0x00100000 | |
120 | #define HV_BUTTON_FROM_GD 0x00200000 | |
121 | #define REDUCED_DEBOUNCE 0x00400000 | |
122 | #define HV_CTRL_ENABLE 0x00800000 | |
123 | #define SPDIF_ENABLE 0x01000000 | |
124 | #define CLK_DIV_SELECT 0x06000000 | |
125 | #define CLK_DIV_BY_48 0x00000000 | |
126 | #define CLK_DIV_BY_49 0x02000000 | |
127 | #define CLK_DIV_BY_50 0x04000000 | |
128 | #define CLK_DIV_RESERVED 0x06000000 | |
129 | #define PM_CTRL_ENABLE 0x08000000 | |
130 | #define CLK_MULT_MODE_SELECT 0x30000000 | |
131 | #define CLK_MULT_MODE_SHIFT 28 | |
132 | #define CLK_MULT_MODE_0 0x00000000 | |
133 | #define CLK_MULT_MODE_1 0x10000000 | |
134 | #define CLK_MULT_MODE_2 0x20000000 | |
135 | #define CLK_MULT_MODE_3 0x30000000 | |
136 | #define INT_CLK_SELECT 0x40000000 | |
137 | #define INT_CLK_MULT_RESET 0x80000000 | |
138 | ||
139 | /* M3 */ | |
140 | #define INT_CLK_SRC_NOT_PCI 0x00100000 | |
141 | #define INT_CLK_MULT_ENABLE 0x80000000 | |
142 | ||
143 | #define PCI_ACPI_CONTROL 0x54 | |
144 | #define PCI_ACPI_D0 0x00000000 | |
145 | #define PCI_ACPI_D1 0xB4F70000 | |
146 | #define PCI_ACPI_D2 0xB4F7B4F7 | |
147 | ||
148 | #define PCI_USER_CONFIG 0x58 | |
149 | #define EXT_PCI_MASTER_ENABLE 0x00000001 | |
150 | #define SPDIF_OUT_SELECT 0x00000002 | |
151 | #define TEST_PIN_DIR_CTRL 0x00000004 | |
152 | #define AC97_CODEC_TEST 0x00000020 | |
153 | #define TRI_STATE_BUFFER 0x00000080 | |
154 | #define IN_CLK_12MHZ_SELECT 0x00000100 | |
155 | #define MULTI_FUNC_DISABLE 0x00000200 | |
156 | #define EXT_MASTER_PAIR_SEL 0x00000400 | |
157 | #define PCI_MASTER_SUPPORT 0x00000800 | |
158 | #define STOP_CLOCK_ENABLE 0x00001000 | |
159 | #define EAPD_DRIVE_ENABLE 0x00002000 | |
160 | #define REQ_TRI_STATE_ENABLE 0x00004000 | |
161 | #define REQ_LOW_ENABLE 0x00008000 | |
162 | #define MIDI_1_ENABLE 0x00010000 | |
163 | #define MIDI_2_ENABLE 0x00020000 | |
164 | #define SB_AUDIO_SYNC 0x00040000 | |
165 | #define HV_CTRL_TEST 0x00100000 | |
166 | #define SOUNDBLASTER_TEST 0x00400000 | |
167 | ||
168 | #define PCI_USER_CONFIG_C 0x5C | |
169 | ||
170 | #define PCI_DDMA_CTRL 0x60 | |
171 | #define DDMA_ENABLE 0x00000001 | |
172 | ||
173 | ||
174 | /* Allegro registers */ | |
175 | #define HOST_INT_CTRL 0x18 | |
176 | #define SB_INT_ENABLE 0x0001 | |
177 | #define MPU401_INT_ENABLE 0x0002 | |
178 | #define ASSP_INT_ENABLE 0x0010 | |
179 | #define RING_INT_ENABLE 0x0020 | |
180 | #define HV_INT_ENABLE 0x0040 | |
181 | #define CLKRUN_GEN_ENABLE 0x0100 | |
182 | #define HV_CTRL_TO_PME 0x0400 | |
183 | #define SOFTWARE_RESET_ENABLE 0x8000 | |
184 | ||
185 | /* | |
186 | * should be using the above defines, probably. | |
187 | */ | |
188 | #define REGB_ENABLE_RESET 0x01 | |
189 | #define REGB_STOP_CLOCK 0x10 | |
190 | ||
191 | #define HOST_INT_STATUS 0x1A | |
192 | #define SB_INT_PENDING 0x01 | |
193 | #define MPU401_INT_PENDING 0x02 | |
194 | #define ASSP_INT_PENDING 0x10 | |
195 | #define RING_INT_PENDING 0x20 | |
196 | #define HV_INT_PENDING 0x40 | |
197 | ||
198 | #define HARDWARE_VOL_CTRL 0x1B | |
199 | #define SHADOW_MIX_REG_VOICE 0x1C | |
200 | #define HW_VOL_COUNTER_VOICE 0x1D | |
201 | #define SHADOW_MIX_REG_MASTER 0x1E | |
202 | #define HW_VOL_COUNTER_MASTER 0x1F | |
203 | ||
204 | #define CODEC_COMMAND 0x30 | |
205 | #define CODEC_READ_B 0x80 | |
206 | ||
207 | #define CODEC_STATUS 0x30 | |
208 | #define CODEC_BUSY_B 0x01 | |
209 | ||
210 | #define CODEC_DATA 0x32 | |
211 | ||
212 | #define RING_BUS_CTRL_A 0x36 | |
213 | #define RAC_PME_ENABLE 0x0100 | |
214 | #define RAC_SDFS_ENABLE 0x0200 | |
215 | #define LAC_PME_ENABLE 0x0400 | |
216 | #define LAC_SDFS_ENABLE 0x0800 | |
217 | #define SERIAL_AC_LINK_ENABLE 0x1000 | |
218 | #define IO_SRAM_ENABLE 0x2000 | |
219 | #define IIS_INPUT_ENABLE 0x8000 | |
220 | ||
221 | #define RING_BUS_CTRL_B 0x38 | |
222 | #define SECOND_CODEC_ID_MASK 0x0003 | |
223 | #define SPDIF_FUNC_ENABLE 0x0010 | |
224 | #define SECOND_AC_ENABLE 0x0020 | |
225 | #define SB_MODULE_INTF_ENABLE 0x0040 | |
226 | #define SSPE_ENABLE 0x0040 | |
227 | #define M3I_DOCK_ENABLE 0x0080 | |
228 | ||
229 | #define SDO_OUT_DEST_CTRL 0x3A | |
230 | #define COMMAND_ADDR_OUT 0x0003 | |
231 | #define PCM_LR_OUT_LOCAL 0x0000 | |
232 | #define PCM_LR_OUT_REMOTE 0x0004 | |
233 | #define PCM_LR_OUT_MUTE 0x0008 | |
234 | #define PCM_LR_OUT_BOTH 0x000C | |
235 | #define LINE1_DAC_OUT_LOCAL 0x0000 | |
236 | #define LINE1_DAC_OUT_REMOTE 0x0010 | |
237 | #define LINE1_DAC_OUT_MUTE 0x0020 | |
238 | #define LINE1_DAC_OUT_BOTH 0x0030 | |
239 | #define PCM_CLS_OUT_LOCAL 0x0000 | |
240 | #define PCM_CLS_OUT_REMOTE 0x0040 | |
241 | #define PCM_CLS_OUT_MUTE 0x0080 | |
242 | #define PCM_CLS_OUT_BOTH 0x00C0 | |
243 | #define PCM_RLF_OUT_LOCAL 0x0000 | |
244 | #define PCM_RLF_OUT_REMOTE 0x0100 | |
245 | #define PCM_RLF_OUT_MUTE 0x0200 | |
246 | #define PCM_RLF_OUT_BOTH 0x0300 | |
247 | #define LINE2_DAC_OUT_LOCAL 0x0000 | |
248 | #define LINE2_DAC_OUT_REMOTE 0x0400 | |
249 | #define LINE2_DAC_OUT_MUTE 0x0800 | |
250 | #define LINE2_DAC_OUT_BOTH 0x0C00 | |
251 | #define HANDSET_OUT_LOCAL 0x0000 | |
252 | #define HANDSET_OUT_REMOTE 0x1000 | |
253 | #define HANDSET_OUT_MUTE 0x2000 | |
254 | #define HANDSET_OUT_BOTH 0x3000 | |
255 | #define IO_CTRL_OUT_LOCAL 0x0000 | |
256 | #define IO_CTRL_OUT_REMOTE 0x4000 | |
257 | #define IO_CTRL_OUT_MUTE 0x8000 | |
258 | #define IO_CTRL_OUT_BOTH 0xC000 | |
259 | ||
260 | #define SDO_IN_DEST_CTRL 0x3C | |
261 | #define STATUS_ADDR_IN 0x0003 | |
262 | #define PCM_LR_IN_LOCAL 0x0000 | |
263 | #define PCM_LR_IN_REMOTE 0x0004 | |
264 | #define PCM_LR_RESERVED 0x0008 | |
265 | #define PCM_LR_IN_BOTH 0x000C | |
266 | #define LINE1_ADC_IN_LOCAL 0x0000 | |
267 | #define LINE1_ADC_IN_REMOTE 0x0010 | |
268 | #define LINE1_ADC_IN_MUTE 0x0020 | |
269 | #define MIC_ADC_IN_LOCAL 0x0000 | |
270 | #define MIC_ADC_IN_REMOTE 0x0040 | |
271 | #define MIC_ADC_IN_MUTE 0x0080 | |
272 | #define LINE2_DAC_IN_LOCAL 0x0000 | |
273 | #define LINE2_DAC_IN_REMOTE 0x0400 | |
274 | #define LINE2_DAC_IN_MUTE 0x0800 | |
275 | #define HANDSET_IN_LOCAL 0x0000 | |
276 | #define HANDSET_IN_REMOTE 0x1000 | |
277 | #define HANDSET_IN_MUTE 0x2000 | |
278 | #define IO_STATUS_IN_LOCAL 0x0000 | |
279 | #define IO_STATUS_IN_REMOTE 0x4000 | |
280 | ||
281 | #define SPDIF_IN_CTRL 0x3E | |
282 | #define SPDIF_IN_ENABLE 0x0001 | |
283 | ||
284 | #define GPIO_DATA 0x60 | |
285 | #define GPIO_DATA_MASK 0x0FFF | |
286 | #define GPIO_HV_STATUS 0x3000 | |
287 | #define GPIO_PME_STATUS 0x4000 | |
288 | ||
289 | #define GPIO_MASK 0x64 | |
290 | #define GPIO_DIRECTION 0x68 | |
291 | #define GPO_PRIMARY_AC97 0x0001 | |
292 | #define GPI_LINEOUT_SENSE 0x0004 | |
293 | #define GPO_SECONDARY_AC97 0x0008 | |
294 | #define GPI_VOL_DOWN 0x0010 | |
295 | #define GPI_VOL_UP 0x0020 | |
296 | #define GPI_IIS_CLK 0x0040 | |
297 | #define GPI_IIS_LRCLK 0x0080 | |
298 | #define GPI_IIS_DATA 0x0100 | |
299 | #define GPI_DOCKING_STATUS 0x0100 | |
300 | #define GPI_HEADPHONE_SENSE 0x0200 | |
301 | #define GPO_EXT_AMP_SHUTDOWN 0x1000 | |
302 | ||
303 | #define GPO_EXT_AMP_M3 1 /* default m3 amp */ | |
304 | #define GPO_EXT_AMP_ALLEGRO 8 /* default allegro amp */ | |
305 | ||
306 | /* M3 */ | |
307 | #define GPO_M3_EXT_AMP_SHUTDN 0x0002 | |
308 | ||
309 | #define ASSP_INDEX_PORT 0x80 | |
310 | #define ASSP_MEMORY_PORT 0x82 | |
311 | #define ASSP_DATA_PORT 0x84 | |
312 | ||
313 | #define MPU401_DATA_PORT 0x98 | |
314 | #define MPU401_STATUS_PORT 0x99 | |
315 | ||
316 | #define CLK_MULT_DATA_PORT 0x9C | |
317 | ||
318 | #define ASSP_CONTROL_A 0xA2 | |
319 | #define ASSP_0_WS_ENABLE 0x01 | |
320 | #define ASSP_CTRL_A_RESERVED1 0x02 | |
321 | #define ASSP_CTRL_A_RESERVED2 0x04 | |
322 | #define ASSP_CLK_49MHZ_SELECT 0x08 | |
323 | #define FAST_PLU_ENABLE 0x10 | |
324 | #define ASSP_CTRL_A_RESERVED3 0x20 | |
325 | #define DSP_CLK_36MHZ_SELECT 0x40 | |
326 | ||
327 | #define ASSP_CONTROL_B 0xA4 | |
328 | #define RESET_ASSP 0x00 | |
329 | #define RUN_ASSP 0x01 | |
330 | #define ENABLE_ASSP_CLOCK 0x00 | |
331 | #define STOP_ASSP_CLOCK 0x10 | |
332 | #define RESET_TOGGLE 0x40 | |
333 | ||
334 | #define ASSP_CONTROL_C 0xA6 | |
335 | #define ASSP_HOST_INT_ENABLE 0x01 | |
336 | #define FM_ADDR_REMAP_DISABLE 0x02 | |
337 | #define HOST_WRITE_PORT_ENABLE 0x08 | |
338 | ||
339 | #define ASSP_HOST_INT_STATUS 0xAC | |
340 | #define DSP2HOST_REQ_PIORECORD 0x01 | |
341 | #define DSP2HOST_REQ_I2SRATE 0x02 | |
342 | #define DSP2HOST_REQ_TIMER 0x04 | |
343 | ||
1da177e4 LT |
344 | /* |
345 | * ASSP control regs | |
346 | */ | |
347 | #define DSP_PORT_TIMER_COUNT 0x06 | |
348 | ||
349 | #define DSP_PORT_MEMORY_INDEX 0x80 | |
350 | ||
351 | #define DSP_PORT_MEMORY_TYPE 0x82 | |
352 | #define MEMTYPE_INTERNAL_CODE 0x0002 | |
353 | #define MEMTYPE_INTERNAL_DATA 0x0003 | |
354 | #define MEMTYPE_MASK 0x0003 | |
355 | ||
356 | #define DSP_PORT_MEMORY_DATA 0x84 | |
357 | ||
358 | #define DSP_PORT_CONTROL_REG_A 0xA2 | |
359 | #define DSP_PORT_CONTROL_REG_B 0xA4 | |
360 | #define DSP_PORT_CONTROL_REG_C 0xA6 | |
361 | ||
362 | #define REV_A_CODE_MEMORY_BEGIN 0x0000 | |
363 | #define REV_A_CODE_MEMORY_END 0x0FFF | |
364 | #define REV_A_CODE_MEMORY_UNIT_LENGTH 0x0040 | |
365 | #define REV_A_CODE_MEMORY_LENGTH (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1) | |
366 | ||
367 | #define REV_B_CODE_MEMORY_BEGIN 0x0000 | |
368 | #define REV_B_CODE_MEMORY_END 0x0BFF | |
369 | #define REV_B_CODE_MEMORY_UNIT_LENGTH 0x0040 | |
370 | #define REV_B_CODE_MEMORY_LENGTH (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1) | |
371 | ||
372 | #define REV_A_DATA_MEMORY_BEGIN 0x1000 | |
373 | #define REV_A_DATA_MEMORY_END 0x2FFF | |
374 | #define REV_A_DATA_MEMORY_UNIT_LENGTH 0x0080 | |
375 | #define REV_A_DATA_MEMORY_LENGTH (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1) | |
376 | ||
377 | #define REV_B_DATA_MEMORY_BEGIN 0x1000 | |
378 | #define REV_B_DATA_MEMORY_END 0x2BFF | |
379 | #define REV_B_DATA_MEMORY_UNIT_LENGTH 0x0080 | |
380 | #define REV_B_DATA_MEMORY_LENGTH (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1) | |
381 | ||
382 | ||
383 | #define NUM_UNITS_KERNEL_CODE 16 | |
384 | #define NUM_UNITS_KERNEL_DATA 2 | |
385 | ||
386 | #define NUM_UNITS_KERNEL_CODE_WITH_HSP 16 | |
387 | #define NUM_UNITS_KERNEL_DATA_WITH_HSP 5 | |
388 | ||
389 | /* | |
390 | * Kernel data layout | |
391 | */ | |
392 | ||
393 | #define DP_SHIFT_COUNT 7 | |
394 | ||
395 | #define KDATA_BASE_ADDR 0x1000 | |
396 | #define KDATA_BASE_ADDR2 0x1080 | |
397 | ||
398 | #define KDATA_TASK0 (KDATA_BASE_ADDR + 0x0000) | |
399 | #define KDATA_TASK1 (KDATA_BASE_ADDR + 0x0001) | |
400 | #define KDATA_TASK2 (KDATA_BASE_ADDR + 0x0002) | |
401 | #define KDATA_TASK3 (KDATA_BASE_ADDR + 0x0003) | |
402 | #define KDATA_TASK4 (KDATA_BASE_ADDR + 0x0004) | |
403 | #define KDATA_TASK5 (KDATA_BASE_ADDR + 0x0005) | |
404 | #define KDATA_TASK6 (KDATA_BASE_ADDR + 0x0006) | |
405 | #define KDATA_TASK7 (KDATA_BASE_ADDR + 0x0007) | |
406 | #define KDATA_TASK_ENDMARK (KDATA_BASE_ADDR + 0x0008) | |
407 | ||
408 | #define KDATA_CURRENT_TASK (KDATA_BASE_ADDR + 0x0009) | |
409 | #define KDATA_TASK_SWITCH (KDATA_BASE_ADDR + 0x000A) | |
410 | ||
411 | #define KDATA_INSTANCE0_POS3D (KDATA_BASE_ADDR + 0x000B) | |
412 | #define KDATA_INSTANCE1_POS3D (KDATA_BASE_ADDR + 0x000C) | |
413 | #define KDATA_INSTANCE2_POS3D (KDATA_BASE_ADDR + 0x000D) | |
414 | #define KDATA_INSTANCE3_POS3D (KDATA_BASE_ADDR + 0x000E) | |
415 | #define KDATA_INSTANCE4_POS3D (KDATA_BASE_ADDR + 0x000F) | |
416 | #define KDATA_INSTANCE5_POS3D (KDATA_BASE_ADDR + 0x0010) | |
417 | #define KDATA_INSTANCE6_POS3D (KDATA_BASE_ADDR + 0x0011) | |
418 | #define KDATA_INSTANCE7_POS3D (KDATA_BASE_ADDR + 0x0012) | |
419 | #define KDATA_INSTANCE8_POS3D (KDATA_BASE_ADDR + 0x0013) | |
420 | #define KDATA_INSTANCE_POS3D_ENDMARK (KDATA_BASE_ADDR + 0x0014) | |
421 | ||
422 | #define KDATA_INSTANCE0_SPKVIRT (KDATA_BASE_ADDR + 0x0015) | |
423 | #define KDATA_INSTANCE_SPKVIRT_ENDMARK (KDATA_BASE_ADDR + 0x0016) | |
424 | ||
425 | #define KDATA_INSTANCE0_SPDIF (KDATA_BASE_ADDR + 0x0017) | |
426 | #define KDATA_INSTANCE_SPDIF_ENDMARK (KDATA_BASE_ADDR + 0x0018) | |
427 | ||
428 | #define KDATA_INSTANCE0_MODEM (KDATA_BASE_ADDR + 0x0019) | |
429 | #define KDATA_INSTANCE_MODEM_ENDMARK (KDATA_BASE_ADDR + 0x001A) | |
430 | ||
431 | #define KDATA_INSTANCE0_SRC (KDATA_BASE_ADDR + 0x001B) | |
432 | #define KDATA_INSTANCE1_SRC (KDATA_BASE_ADDR + 0x001C) | |
433 | #define KDATA_INSTANCE_SRC_ENDMARK (KDATA_BASE_ADDR + 0x001D) | |
434 | ||
435 | #define KDATA_INSTANCE0_MINISRC (KDATA_BASE_ADDR + 0x001E) | |
436 | #define KDATA_INSTANCE1_MINISRC (KDATA_BASE_ADDR + 0x001F) | |
437 | #define KDATA_INSTANCE2_MINISRC (KDATA_BASE_ADDR + 0x0020) | |
438 | #define KDATA_INSTANCE3_MINISRC (KDATA_BASE_ADDR + 0x0021) | |
439 | #define KDATA_INSTANCE_MINISRC_ENDMARK (KDATA_BASE_ADDR + 0x0022) | |
440 | ||
441 | #define KDATA_INSTANCE0_CPYTHRU (KDATA_BASE_ADDR + 0x0023) | |
442 | #define KDATA_INSTANCE1_CPYTHRU (KDATA_BASE_ADDR + 0x0024) | |
443 | #define KDATA_INSTANCE_CPYTHRU_ENDMARK (KDATA_BASE_ADDR + 0x0025) | |
444 | ||
445 | #define KDATA_CURRENT_DMA (KDATA_BASE_ADDR + 0x0026) | |
446 | #define KDATA_DMA_SWITCH (KDATA_BASE_ADDR + 0x0027) | |
447 | #define KDATA_DMA_ACTIVE (KDATA_BASE_ADDR + 0x0028) | |
448 | ||
449 | #define KDATA_DMA_XFER0 (KDATA_BASE_ADDR + 0x0029) | |
450 | #define KDATA_DMA_XFER1 (KDATA_BASE_ADDR + 0x002A) | |
451 | #define KDATA_DMA_XFER2 (KDATA_BASE_ADDR + 0x002B) | |
452 | #define KDATA_DMA_XFER3 (KDATA_BASE_ADDR + 0x002C) | |
453 | #define KDATA_DMA_XFER4 (KDATA_BASE_ADDR + 0x002D) | |
454 | #define KDATA_DMA_XFER5 (KDATA_BASE_ADDR + 0x002E) | |
455 | #define KDATA_DMA_XFER6 (KDATA_BASE_ADDR + 0x002F) | |
456 | #define KDATA_DMA_XFER7 (KDATA_BASE_ADDR + 0x0030) | |
457 | #define KDATA_DMA_XFER8 (KDATA_BASE_ADDR + 0x0031) | |
458 | #define KDATA_DMA_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0032) | |
459 | ||
460 | #define KDATA_I2S_SAMPLE_COUNT (KDATA_BASE_ADDR + 0x0033) | |
461 | #define KDATA_I2S_INT_METER (KDATA_BASE_ADDR + 0x0034) | |
462 | #define KDATA_I2S_ACTIVE (KDATA_BASE_ADDR + 0x0035) | |
463 | ||
464 | #define KDATA_TIMER_COUNT_RELOAD (KDATA_BASE_ADDR + 0x0036) | |
465 | #define KDATA_TIMER_COUNT_CURRENT (KDATA_BASE_ADDR + 0x0037) | |
466 | ||
467 | #define KDATA_HALT_SYNCH_CLIENT (KDATA_BASE_ADDR + 0x0038) | |
468 | #define KDATA_HALT_SYNCH_DMA (KDATA_BASE_ADDR + 0x0039) | |
469 | #define KDATA_HALT_ACKNOWLEDGE (KDATA_BASE_ADDR + 0x003A) | |
470 | ||
471 | #define KDATA_ADC1_XFER0 (KDATA_BASE_ADDR + 0x003B) | |
472 | #define KDATA_ADC1_XFER_ENDMARK (KDATA_BASE_ADDR + 0x003C) | |
473 | #define KDATA_ADC1_LEFT_VOLUME (KDATA_BASE_ADDR + 0x003D) | |
474 | #define KDATA_ADC1_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x003E) | |
475 | #define KDATA_ADC1_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x003F) | |
476 | #define KDATA_ADC1_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0040) | |
477 | ||
478 | #define KDATA_ADC2_XFER0 (KDATA_BASE_ADDR + 0x0041) | |
479 | #define KDATA_ADC2_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0042) | |
480 | #define KDATA_ADC2_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0043) | |
481 | #define KDATA_ADC2_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x0044) | |
482 | #define KDATA_ADC2_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x0045) | |
483 | #define KDATA_ADC2_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0046) | |
484 | ||
485 | #define KDATA_CD_XFER0 (KDATA_BASE_ADDR + 0x0047) | |
486 | #define KDATA_CD_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0048) | |
487 | #define KDATA_CD_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0049) | |
488 | #define KDATA_CD_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x004A) | |
489 | #define KDATA_CD_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x004B) | |
490 | #define KDATA_CD_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x004C) | |
491 | ||
492 | #define KDATA_MIC_XFER0 (KDATA_BASE_ADDR + 0x004D) | |
493 | #define KDATA_MIC_XFER_ENDMARK (KDATA_BASE_ADDR + 0x004E) | |
494 | #define KDATA_MIC_VOLUME (KDATA_BASE_ADDR + 0x004F) | |
495 | #define KDATA_MIC_SUR_VOL (KDATA_BASE_ADDR + 0x0050) | |
496 | ||
497 | #define KDATA_I2S_XFER0 (KDATA_BASE_ADDR + 0x0051) | |
498 | #define KDATA_I2S_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0052) | |
499 | ||
500 | #define KDATA_CHI_XFER0 (KDATA_BASE_ADDR + 0x0053) | |
501 | #define KDATA_CHI_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0054) | |
502 | ||
503 | #define KDATA_SPDIF_XFER (KDATA_BASE_ADDR + 0x0055) | |
504 | #define KDATA_SPDIF_CURRENT_FRAME (KDATA_BASE_ADDR + 0x0056) | |
505 | #define KDATA_SPDIF_FRAME0 (KDATA_BASE_ADDR + 0x0057) | |
506 | #define KDATA_SPDIF_FRAME1 (KDATA_BASE_ADDR + 0x0058) | |
507 | #define KDATA_SPDIF_FRAME2 (KDATA_BASE_ADDR + 0x0059) | |
508 | ||
509 | #define KDATA_SPDIF_REQUEST (KDATA_BASE_ADDR + 0x005A) | |
510 | #define KDATA_SPDIF_TEMP (KDATA_BASE_ADDR + 0x005B) | |
511 | ||
512 | #define KDATA_SPDIFIN_XFER0 (KDATA_BASE_ADDR + 0x005C) | |
513 | #define KDATA_SPDIFIN_XFER_ENDMARK (KDATA_BASE_ADDR + 0x005D) | |
514 | #define KDATA_SPDIFIN_INT_METER (KDATA_BASE_ADDR + 0x005E) | |
515 | ||
516 | #define KDATA_DSP_RESET_COUNT (KDATA_BASE_ADDR + 0x005F) | |
517 | #define KDATA_DEBUG_OUTPUT (KDATA_BASE_ADDR + 0x0060) | |
518 | ||
519 | #define KDATA_KERNEL_ISR_LIST (KDATA_BASE_ADDR + 0x0061) | |
520 | ||
521 | #define KDATA_KERNEL_ISR_CBSR1 (KDATA_BASE_ADDR + 0x0062) | |
522 | #define KDATA_KERNEL_ISR_CBER1 (KDATA_BASE_ADDR + 0x0063) | |
523 | #define KDATA_KERNEL_ISR_CBCR (KDATA_BASE_ADDR + 0x0064) | |
524 | #define KDATA_KERNEL_ISR_AR0 (KDATA_BASE_ADDR + 0x0065) | |
525 | #define KDATA_KERNEL_ISR_AR1 (KDATA_BASE_ADDR + 0x0066) | |
526 | #define KDATA_KERNEL_ISR_AR2 (KDATA_BASE_ADDR + 0x0067) | |
527 | #define KDATA_KERNEL_ISR_AR3 (KDATA_BASE_ADDR + 0x0068) | |
528 | #define KDATA_KERNEL_ISR_AR4 (KDATA_BASE_ADDR + 0x0069) | |
529 | #define KDATA_KERNEL_ISR_AR5 (KDATA_BASE_ADDR + 0x006A) | |
530 | #define KDATA_KERNEL_ISR_BRCR (KDATA_BASE_ADDR + 0x006B) | |
531 | #define KDATA_KERNEL_ISR_PASR (KDATA_BASE_ADDR + 0x006C) | |
532 | #define KDATA_KERNEL_ISR_PAER (KDATA_BASE_ADDR + 0x006D) | |
533 | ||
534 | #define KDATA_CLIENT_SCRATCH0 (KDATA_BASE_ADDR + 0x006E) | |
535 | #define KDATA_CLIENT_SCRATCH1 (KDATA_BASE_ADDR + 0x006F) | |
536 | #define KDATA_KERNEL_SCRATCH (KDATA_BASE_ADDR + 0x0070) | |
537 | #define KDATA_KERNEL_ISR_SCRATCH (KDATA_BASE_ADDR + 0x0071) | |
538 | ||
539 | #define KDATA_OUEUE_LEFT (KDATA_BASE_ADDR + 0x0072) | |
540 | #define KDATA_QUEUE_RIGHT (KDATA_BASE_ADDR + 0x0073) | |
541 | ||
542 | #define KDATA_ADC1_REQUEST (KDATA_BASE_ADDR + 0x0074) | |
543 | #define KDATA_ADC2_REQUEST (KDATA_BASE_ADDR + 0x0075) | |
544 | #define KDATA_CD_REQUEST (KDATA_BASE_ADDR + 0x0076) | |
545 | #define KDATA_MIC_REQUEST (KDATA_BASE_ADDR + 0x0077) | |
546 | ||
547 | #define KDATA_ADC1_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0078) | |
548 | #define KDATA_ADC2_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0079) | |
549 | #define KDATA_CD_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007A) | |
550 | #define KDATA_MIC_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007B) | |
551 | #define KDATA_MIC_SYNC_COUNTER (KDATA_BASE_ADDR + 0x007C) | |
552 | ||
553 | /* | |
554 | * second 'segment' (?) reserved for mixer | |
555 | * buffers.. | |
556 | */ | |
557 | ||
558 | #define KDATA_MIXER_WORD0 (KDATA_BASE_ADDR2 + 0x0000) | |
559 | #define KDATA_MIXER_WORD1 (KDATA_BASE_ADDR2 + 0x0001) | |
560 | #define KDATA_MIXER_WORD2 (KDATA_BASE_ADDR2 + 0x0002) | |
561 | #define KDATA_MIXER_WORD3 (KDATA_BASE_ADDR2 + 0x0003) | |
562 | #define KDATA_MIXER_WORD4 (KDATA_BASE_ADDR2 + 0x0004) | |
563 | #define KDATA_MIXER_WORD5 (KDATA_BASE_ADDR2 + 0x0005) | |
564 | #define KDATA_MIXER_WORD6 (KDATA_BASE_ADDR2 + 0x0006) | |
565 | #define KDATA_MIXER_WORD7 (KDATA_BASE_ADDR2 + 0x0007) | |
566 | #define KDATA_MIXER_WORD8 (KDATA_BASE_ADDR2 + 0x0008) | |
567 | #define KDATA_MIXER_WORD9 (KDATA_BASE_ADDR2 + 0x0009) | |
568 | #define KDATA_MIXER_WORDA (KDATA_BASE_ADDR2 + 0x000A) | |
569 | #define KDATA_MIXER_WORDB (KDATA_BASE_ADDR2 + 0x000B) | |
570 | #define KDATA_MIXER_WORDC (KDATA_BASE_ADDR2 + 0x000C) | |
571 | #define KDATA_MIXER_WORDD (KDATA_BASE_ADDR2 + 0x000D) | |
572 | #define KDATA_MIXER_WORDE (KDATA_BASE_ADDR2 + 0x000E) | |
573 | #define KDATA_MIXER_WORDF (KDATA_BASE_ADDR2 + 0x000F) | |
574 | ||
575 | #define KDATA_MIXER_XFER0 (KDATA_BASE_ADDR2 + 0x0010) | |
576 | #define KDATA_MIXER_XFER1 (KDATA_BASE_ADDR2 + 0x0011) | |
577 | #define KDATA_MIXER_XFER2 (KDATA_BASE_ADDR2 + 0x0012) | |
578 | #define KDATA_MIXER_XFER3 (KDATA_BASE_ADDR2 + 0x0013) | |
579 | #define KDATA_MIXER_XFER4 (KDATA_BASE_ADDR2 + 0x0014) | |
580 | #define KDATA_MIXER_XFER5 (KDATA_BASE_ADDR2 + 0x0015) | |
581 | #define KDATA_MIXER_XFER6 (KDATA_BASE_ADDR2 + 0x0016) | |
582 | #define KDATA_MIXER_XFER7 (KDATA_BASE_ADDR2 + 0x0017) | |
583 | #define KDATA_MIXER_XFER8 (KDATA_BASE_ADDR2 + 0x0018) | |
584 | #define KDATA_MIXER_XFER9 (KDATA_BASE_ADDR2 + 0x0019) | |
585 | #define KDATA_MIXER_XFER_ENDMARK (KDATA_BASE_ADDR2 + 0x001A) | |
586 | ||
587 | #define KDATA_MIXER_TASK_NUMBER (KDATA_BASE_ADDR2 + 0x001B) | |
588 | #define KDATA_CURRENT_MIXER (KDATA_BASE_ADDR2 + 0x001C) | |
589 | #define KDATA_MIXER_ACTIVE (KDATA_BASE_ADDR2 + 0x001D) | |
590 | #define KDATA_MIXER_BANK_STATUS (KDATA_BASE_ADDR2 + 0x001E) | |
591 | #define KDATA_DAC_LEFT_VOLUME (KDATA_BASE_ADDR2 + 0x001F) | |
592 | #define KDATA_DAC_RIGHT_VOLUME (KDATA_BASE_ADDR2 + 0x0020) | |
593 | ||
594 | #define MAX_INSTANCE_MINISRC (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC) | |
595 | #define MAX_VIRTUAL_DMA_CHANNELS (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0) | |
596 | #define MAX_VIRTUAL_MIXER_CHANNELS (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0) | |
597 | #define MAX_VIRTUAL_ADC1_CHANNELS (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0) | |
598 | ||
599 | /* | |
600 | * client data area offsets | |
601 | */ | |
602 | #define CDATA_INSTANCE_READY 0x00 | |
603 | ||
604 | #define CDATA_HOST_SRC_ADDRL 0x01 | |
605 | #define CDATA_HOST_SRC_ADDRH 0x02 | |
606 | #define CDATA_HOST_SRC_END_PLUS_1L 0x03 | |
607 | #define CDATA_HOST_SRC_END_PLUS_1H 0x04 | |
608 | #define CDATA_HOST_SRC_CURRENTL 0x05 | |
609 | #define CDATA_HOST_SRC_CURRENTH 0x06 | |
610 | ||
611 | #define CDATA_IN_BUF_CONNECT 0x07 | |
612 | #define CDATA_OUT_BUF_CONNECT 0x08 | |
613 | ||
614 | #define CDATA_IN_BUF_BEGIN 0x09 | |
615 | #define CDATA_IN_BUF_END_PLUS_1 0x0A | |
616 | #define CDATA_IN_BUF_HEAD 0x0B | |
617 | #define CDATA_IN_BUF_TAIL 0x0C | |
618 | #define CDATA_OUT_BUF_BEGIN 0x0D | |
619 | #define CDATA_OUT_BUF_END_PLUS_1 0x0E | |
620 | #define CDATA_OUT_BUF_HEAD 0x0F | |
621 | #define CDATA_OUT_BUF_TAIL 0x10 | |
622 | ||
623 | #define CDATA_DMA_CONTROL 0x11 | |
624 | #define CDATA_RESERVED 0x12 | |
625 | ||
626 | #define CDATA_FREQUENCY 0x13 | |
627 | #define CDATA_LEFT_VOLUME 0x14 | |
628 | #define CDATA_RIGHT_VOLUME 0x15 | |
629 | #define CDATA_LEFT_SUR_VOL 0x16 | |
630 | #define CDATA_RIGHT_SUR_VOL 0x17 | |
631 | ||
632 | #define CDATA_HEADER_LEN 0x18 | |
633 | ||
634 | #define SRC3_DIRECTION_OFFSET CDATA_HEADER_LEN | |
635 | #define SRC3_MODE_OFFSET (CDATA_HEADER_LEN + 1) | |
636 | #define SRC3_WORD_LENGTH_OFFSET (CDATA_HEADER_LEN + 2) | |
637 | #define SRC3_PARAMETER_OFFSET (CDATA_HEADER_LEN + 3) | |
638 | #define SRC3_COEFF_ADDR_OFFSET (CDATA_HEADER_LEN + 8) | |
639 | #define SRC3_FILTAP_ADDR_OFFSET (CDATA_HEADER_LEN + 10) | |
640 | #define SRC3_TEMP_INBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 16) | |
641 | #define SRC3_TEMP_OUTBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 17) | |
642 | ||
643 | #define MINISRC_IN_BUFFER_SIZE ( 0x50 * 2 ) | |
644 | #define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2) | |
1da177e4 LT |
645 | #define MINISRC_TMP_BUFFER_SIZE ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 ) |
646 | #define MINISRC_BIQUAD_STAGE 2 | |
647 | #define MINISRC_COEF_LOC 0x175 | |
648 | ||
649 | #define DMACONTROL_BLOCK_MASK 0x000F | |
650 | #define DMAC_BLOCK0_SELECTOR 0x0000 | |
651 | #define DMAC_BLOCK1_SELECTOR 0x0001 | |
652 | #define DMAC_BLOCK2_SELECTOR 0x0002 | |
653 | #define DMAC_BLOCK3_SELECTOR 0x0003 | |
654 | #define DMAC_BLOCK4_SELECTOR 0x0004 | |
655 | #define DMAC_BLOCK5_SELECTOR 0x0005 | |
656 | #define DMAC_BLOCK6_SELECTOR 0x0006 | |
657 | #define DMAC_BLOCK7_SELECTOR 0x0007 | |
658 | #define DMAC_BLOCK8_SELECTOR 0x0008 | |
659 | #define DMAC_BLOCK9_SELECTOR 0x0009 | |
660 | #define DMAC_BLOCKA_SELECTOR 0x000A | |
661 | #define DMAC_BLOCKB_SELECTOR 0x000B | |
662 | #define DMAC_BLOCKC_SELECTOR 0x000C | |
663 | #define DMAC_BLOCKD_SELECTOR 0x000D | |
664 | #define DMAC_BLOCKE_SELECTOR 0x000E | |
665 | #define DMAC_BLOCKF_SELECTOR 0x000F | |
666 | #define DMACONTROL_PAGE_MASK 0x00F0 | |
667 | #define DMAC_PAGE0_SELECTOR 0x0030 | |
668 | #define DMAC_PAGE1_SELECTOR 0x0020 | |
669 | #define DMAC_PAGE2_SELECTOR 0x0010 | |
670 | #define DMAC_PAGE3_SELECTOR 0x0000 | |
671 | #define DMACONTROL_AUTOREPEAT 0x1000 | |
672 | #define DMACONTROL_STOPPED 0x2000 | |
673 | #define DMACONTROL_DIRECTION 0x0100 | |
674 | ||
675 | /* | |
676 | * an arbitrary volume we set the internal | |
677 | * volume settings to so that the ac97 volume | |
678 | * range is a little less insane. 0x7fff is | |
679 | * max. | |
680 | */ | |
681 | #define ARB_VOLUME ( 0x6800 ) | |
682 | ||
683 | /* | |
684 | */ | |
685 | ||
1da177e4 LT |
686 | struct m3_list { |
687 | int curlen; | |
688 | int mem_addr; | |
689 | int max; | |
690 | }; | |
691 | ||
3470c29d | 692 | struct m3_dma { |
1da177e4 LT |
693 | |
694 | int number; | |
3470c29d | 695 | struct snd_pcm_substream *substream; |
1da177e4 LT |
696 | |
697 | struct assp_instance { | |
698 | unsigned short code, data; | |
699 | } inst; | |
700 | ||
701 | int running; | |
702 | int opened; | |
703 | ||
704 | unsigned long buffer_addr; | |
705 | int dma_size; | |
706 | int period_size; | |
707 | unsigned int hwptr; | |
708 | int count; | |
709 | ||
710 | int index[3]; | |
711 | struct m3_list *index_list[3]; | |
712 | ||
713 | int in_lists; | |
714 | ||
715 | struct list_head list; | |
716 | ||
717 | }; | |
718 | ||
719 | struct snd_m3 { | |
720 | ||
3470c29d | 721 | struct snd_card *card; |
1da177e4 LT |
722 | |
723 | unsigned long iobase; | |
724 | ||
725 | int irq; | |
726 | unsigned int allegro_flag : 1; | |
727 | ||
3470c29d | 728 | struct snd_ac97 *ac97; |
1da177e4 | 729 | |
3470c29d | 730 | struct snd_pcm *pcm; |
1da177e4 LT |
731 | |
732 | struct pci_dev *pci; | |
1da177e4 LT |
733 | |
734 | int dacs_active; | |
735 | int timer_users; | |
736 | ||
737 | struct m3_list msrc_list; | |
738 | struct m3_list mixer_list; | |
739 | struct m3_list adc1_list; | |
740 | struct m3_list dma_list; | |
741 | ||
742 | /* for storing reset state..*/ | |
743 | u8 reset_state; | |
744 | ||
745 | int external_amp; | |
1061eeb4 TI |
746 | int amp_gpio; /* gpio pin # for external amp, -1 = default */ |
747 | unsigned int hv_config; /* hardware-volume config bits */ | |
748 | unsigned irda_workaround :1; /* avoid to touch 0x10 on GPIO_DIRECTION | |
749 | (e.g. for IrDA on Dell Inspirons) */ | |
750 | unsigned is_omnibook :1; /* Do HP OmniBook GPIO magic? */ | |
1da177e4 LT |
751 | |
752 | /* midi */ | |
3470c29d | 753 | struct snd_rawmidi *rmidi; |
1da177e4 LT |
754 | |
755 | /* pcm streams */ | |
756 | int num_substreams; | |
3470c29d | 757 | struct m3_dma *substreams; |
1da177e4 LT |
758 | |
759 | spinlock_t reg_lock; | |
760 | ||
eb581adf HG |
761 | #ifdef CONFIG_SND_MAESTRO3_INPUT |
762 | struct input_dev *input_dev; | |
763 | char phys[64]; /* physical device path */ | |
764 | #else | |
3470c29d TI |
765 | struct snd_kcontrol *master_switch; |
766 | struct snd_kcontrol *master_volume; | |
eb581adf | 767 | #endif |
30bdee02 | 768 | struct work_struct hwvol_work; |
eb581adf | 769 | |
715aa675 | 770 | unsigned int in_suspend; |
82f008c2 | 771 | |
1da177e4 | 772 | u16 *suspend_mem; |
81d7724a CL |
773 | |
774 | const struct firmware *assp_kernel_image; | |
775 | const struct firmware *assp_minisrc_image; | |
1da177e4 LT |
776 | }; |
777 | ||
778 | /* | |
779 | * pci ids | |
780 | */ | |
9baa3c34 | 781 | static const struct pci_device_id snd_m3_ids[] = { |
1da177e4 LT |
782 | {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO_1, PCI_ANY_ID, PCI_ANY_ID, |
783 | PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, | |
784 | {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO, PCI_ANY_ID, PCI_ANY_ID, | |
785 | PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, | |
786 | {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2LE, PCI_ANY_ID, PCI_ANY_ID, | |
787 | PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, | |
788 | {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2, PCI_ANY_ID, PCI_ANY_ID, | |
789 | PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, | |
790 | {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3, PCI_ANY_ID, PCI_ANY_ID, | |
791 | PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, | |
792 | {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_1, PCI_ANY_ID, PCI_ANY_ID, | |
793 | PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, | |
794 | {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_HW, PCI_ANY_ID, PCI_ANY_ID, | |
795 | PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, | |
796 | {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_2, PCI_ANY_ID, PCI_ANY_ID, | |
797 | PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, | |
798 | {0,}, | |
799 | }; | |
800 | ||
801 | MODULE_DEVICE_TABLE(pci, snd_m3_ids); | |
802 | ||
88e540a8 | 803 | static const struct snd_pci_quirk m3_amp_quirk_list[] = { |
7efbfd1a | 804 | SND_PCI_QUIRK(0x0E11, 0x0094, "Compaq Evo N600c", 0x0c), |
1061eeb4 TI |
805 | SND_PCI_QUIRK(0x10f7, 0x833e, "Panasonic CF-28", 0x0d), |
806 | SND_PCI_QUIRK(0x10f7, 0x833d, "Panasonic CF-72", 0x0d), | |
807 | SND_PCI_QUIRK(0x1033, 0x80f1, "NEC LM800J/7", 0x03), | |
808 | SND_PCI_QUIRK(0x1509, 0x1740, "LEGEND ZhaoYang 3100CF", 0x03), | |
809 | { } /* END */ | |
810 | }; | |
811 | ||
88e540a8 | 812 | static const struct snd_pci_quirk m3_irda_quirk_list[] = { |
1061eeb4 TI |
813 | SND_PCI_QUIRK(0x1028, 0x00b0, "Dell Inspiron 4000", 1), |
814 | SND_PCI_QUIRK(0x1028, 0x00a4, "Dell Inspiron 8000", 1), | |
815 | SND_PCI_QUIRK(0x1028, 0x00e6, "Dell Inspiron 8100", 1), | |
816 | { } /* END */ | |
1da177e4 LT |
817 | }; |
818 | ||
1061eeb4 | 819 | /* hardware volume quirks */ |
88e540a8 | 820 | static const struct snd_pci_quirk m3_hv_quirk_list[] = { |
82f008c2 | 821 | /* Allegro chips */ |
1061eeb4 TI |
822 | SND_PCI_QUIRK(0x0E11, 0x002E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), |
823 | SND_PCI_QUIRK(0x0E11, 0x0094, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), | |
824 | SND_PCI_QUIRK(0x0E11, 0xB112, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), | |
825 | SND_PCI_QUIRK(0x0E11, 0xB114, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), | |
826 | SND_PCI_QUIRK(0x103C, 0x0012, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), | |
827 | SND_PCI_QUIRK(0x103C, 0x0018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), | |
828 | SND_PCI_QUIRK(0x103C, 0x001C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), | |
829 | SND_PCI_QUIRK(0x103C, 0x001D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), | |
830 | SND_PCI_QUIRK(0x103C, 0x001E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), | |
831 | SND_PCI_QUIRK(0x107B, 0x3350, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), | |
832 | SND_PCI_QUIRK(0x10F7, 0x8338, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), | |
833 | SND_PCI_QUIRK(0x10F7, 0x833C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), | |
834 | SND_PCI_QUIRK(0x10F7, 0x833D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), | |
835 | SND_PCI_QUIRK(0x10F7, 0x833E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), | |
836 | SND_PCI_QUIRK(0x10F7, 0x833F, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), | |
837 | SND_PCI_QUIRK(0x13BD, 0x1018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), | |
838 | SND_PCI_QUIRK(0x13BD, 0x1019, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), | |
839 | SND_PCI_QUIRK(0x13BD, 0x101A, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), | |
840 | SND_PCI_QUIRK(0x14FF, 0x0F03, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), | |
841 | SND_PCI_QUIRK(0x14FF, 0x0F04, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), | |
842 | SND_PCI_QUIRK(0x14FF, 0x0F05, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), | |
843 | SND_PCI_QUIRK(0x156D, 0xB400, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), | |
844 | SND_PCI_QUIRK(0x156D, 0xB795, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), | |
845 | SND_PCI_QUIRK(0x156D, 0xB797, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), | |
846 | SND_PCI_QUIRK(0x156D, 0xC700, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), | |
847 | SND_PCI_QUIRK(0x1033, 0x80F1, NULL, | |
848 | HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), | |
849 | SND_PCI_QUIRK(0x103C, 0x001A, NULL, /* HP OmniBook 6100 */ | |
850 | HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), | |
851 | SND_PCI_QUIRK(0x107B, 0x340A, NULL, | |
852 | HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), | |
853 | SND_PCI_QUIRK(0x107B, 0x3450, NULL, | |
854 | HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), | |
855 | SND_PCI_QUIRK(0x109F, 0x3134, NULL, | |
856 | HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), | |
857 | SND_PCI_QUIRK(0x109F, 0x3161, NULL, | |
858 | HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), | |
859 | SND_PCI_QUIRK(0x144D, 0x3280, NULL, | |
860 | HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), | |
861 | SND_PCI_QUIRK(0x144D, 0x3281, NULL, | |
862 | HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), | |
863 | SND_PCI_QUIRK(0x144D, 0xC002, NULL, | |
864 | HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), | |
865 | SND_PCI_QUIRK(0x144D, 0xC003, NULL, | |
866 | HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), | |
867 | SND_PCI_QUIRK(0x1509, 0x1740, NULL, | |
868 | HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), | |
869 | SND_PCI_QUIRK(0x1610, 0x0010, NULL, | |
870 | HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), | |
871 | SND_PCI_QUIRK(0x1042, 0x1042, NULL, HV_CTRL_ENABLE), | |
872 | SND_PCI_QUIRK(0x107B, 0x9500, NULL, HV_CTRL_ENABLE), | |
873 | SND_PCI_QUIRK(0x14FF, 0x0F06, NULL, HV_CTRL_ENABLE), | |
874 | SND_PCI_QUIRK(0x1558, 0x8586, NULL, HV_CTRL_ENABLE), | |
875 | SND_PCI_QUIRK(0x161F, 0x2011, NULL, HV_CTRL_ENABLE), | |
82f008c2 | 876 | /* Maestro3 chips */ |
1061eeb4 TI |
877 | SND_PCI_QUIRK(0x103C, 0x000E, NULL, HV_CTRL_ENABLE), |
878 | SND_PCI_QUIRK(0x103C, 0x0010, NULL, HV_CTRL_ENABLE), | |
879 | SND_PCI_QUIRK(0x103C, 0x0011, NULL, HV_CTRL_ENABLE), | |
880 | SND_PCI_QUIRK(0x103C, 0x001B, NULL, HV_CTRL_ENABLE), | |
881 | SND_PCI_QUIRK(0x104D, 0x80A6, NULL, HV_CTRL_ENABLE), | |
882 | SND_PCI_QUIRK(0x104D, 0x80AA, NULL, HV_CTRL_ENABLE), | |
883 | SND_PCI_QUIRK(0x107B, 0x5300, NULL, HV_CTRL_ENABLE), | |
884 | SND_PCI_QUIRK(0x110A, 0x1998, NULL, HV_CTRL_ENABLE), | |
885 | SND_PCI_QUIRK(0x13BD, 0x1015, NULL, HV_CTRL_ENABLE), | |
886 | SND_PCI_QUIRK(0x13BD, 0x101C, NULL, HV_CTRL_ENABLE), | |
887 | SND_PCI_QUIRK(0x13BD, 0x1802, NULL, HV_CTRL_ENABLE), | |
888 | SND_PCI_QUIRK(0x1599, 0x0715, NULL, HV_CTRL_ENABLE), | |
889 | SND_PCI_QUIRK(0x5643, 0x5643, NULL, HV_CTRL_ENABLE), | |
890 | SND_PCI_QUIRK(0x144D, 0x3260, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE), | |
891 | SND_PCI_QUIRK(0x144D, 0x3261, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE), | |
892 | SND_PCI_QUIRK(0x144D, 0xC000, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE), | |
893 | SND_PCI_QUIRK(0x144D, 0xC001, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE), | |
894 | { } /* END */ | |
895 | }; | |
896 | ||
897 | /* HP Omnibook quirks */ | |
88e540a8 | 898 | static const struct snd_pci_quirk m3_omnibook_quirk_list[] = { |
1061eeb4 TI |
899 | SND_PCI_QUIRK_ID(0x103c, 0x0010), /* HP OmniBook 6000 */ |
900 | SND_PCI_QUIRK_ID(0x103c, 0x0011), /* HP OmniBook 500 */ | |
901 | { } /* END */ | |
82f008c2 | 902 | }; |
1da177e4 LT |
903 | |
904 | /* | |
905 | * lowlevel functions | |
906 | */ | |
907 | ||
3470c29d | 908 | static inline void snd_m3_outw(struct snd_m3 *chip, u16 value, unsigned long reg) |
1da177e4 LT |
909 | { |
910 | outw(value, chip->iobase + reg); | |
911 | } | |
912 | ||
3470c29d | 913 | static inline u16 snd_m3_inw(struct snd_m3 *chip, unsigned long reg) |
1da177e4 LT |
914 | { |
915 | return inw(chip->iobase + reg); | |
916 | } | |
917 | ||
3470c29d | 918 | static inline void snd_m3_outb(struct snd_m3 *chip, u8 value, unsigned long reg) |
1da177e4 LT |
919 | { |
920 | outb(value, chip->iobase + reg); | |
921 | } | |
922 | ||
3470c29d | 923 | static inline u8 snd_m3_inb(struct snd_m3 *chip, unsigned long reg) |
1da177e4 LT |
924 | { |
925 | return inb(chip->iobase + reg); | |
926 | } | |
927 | ||
928 | /* | |
929 | * access 16bit words to the code or data regions of the dsp's memory. | |
930 | * index addresses 16bit words. | |
931 | */ | |
3470c29d | 932 | static u16 snd_m3_assp_read(struct snd_m3 *chip, u16 region, u16 index) |
1da177e4 LT |
933 | { |
934 | snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE); | |
935 | snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX); | |
936 | return snd_m3_inw(chip, DSP_PORT_MEMORY_DATA); | |
937 | } | |
938 | ||
3470c29d | 939 | static void snd_m3_assp_write(struct snd_m3 *chip, u16 region, u16 index, u16 data) |
1da177e4 LT |
940 | { |
941 | snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE); | |
942 | snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX); | |
943 | snd_m3_outw(chip, data, DSP_PORT_MEMORY_DATA); | |
944 | } | |
945 | ||
3470c29d | 946 | static void snd_m3_assp_halt(struct snd_m3 *chip) |
1da177e4 LT |
947 | { |
948 | chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK; | |
5ba1e7b5 | 949 | msleep(10); |
1da177e4 LT |
950 | snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B); |
951 | } | |
952 | ||
3470c29d | 953 | static void snd_m3_assp_continue(struct snd_m3 *chip) |
1da177e4 LT |
954 | { |
955 | snd_m3_outb(chip, chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B); | |
956 | } | |
957 | ||
958 | ||
959 | /* | |
960 | * This makes me sad. the maestro3 has lists | |
961 | * internally that must be packed.. 0 terminates, | |
962 | * apparently, or maybe all unused entries have | |
963 | * to be 0, the lists have static lengths set | |
964 | * by the binary code images. | |
965 | */ | |
966 | ||
3470c29d | 967 | static int snd_m3_add_list(struct snd_m3 *chip, struct m3_list *list, u16 val) |
1da177e4 LT |
968 | { |
969 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
970 | list->mem_addr + list->curlen, | |
971 | val); | |
972 | return list->curlen++; | |
973 | } | |
974 | ||
3470c29d | 975 | static void snd_m3_remove_list(struct snd_m3 *chip, struct m3_list *list, int index) |
1da177e4 LT |
976 | { |
977 | u16 val; | |
978 | int lastindex = list->curlen - 1; | |
979 | ||
980 | if (index != lastindex) { | |
981 | val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, | |
982 | list->mem_addr + lastindex); | |
983 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
984 | list->mem_addr + index, | |
985 | val); | |
986 | } | |
987 | ||
988 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
989 | list->mem_addr + lastindex, | |
990 | 0); | |
991 | ||
992 | list->curlen--; | |
993 | } | |
994 | ||
3470c29d | 995 | static void snd_m3_inc_timer_users(struct snd_m3 *chip) |
1da177e4 LT |
996 | { |
997 | chip->timer_users++; | |
998 | if (chip->timer_users != 1) | |
999 | return; | |
1000 | ||
1001 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
1002 | KDATA_TIMER_COUNT_RELOAD, | |
1003 | 240); | |
1004 | ||
1005 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
1006 | KDATA_TIMER_COUNT_CURRENT, | |
1007 | 240); | |
1008 | ||
1009 | snd_m3_outw(chip, | |
1010 | snd_m3_inw(chip, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE, | |
1011 | HOST_INT_CTRL); | |
1012 | } | |
1013 | ||
3470c29d | 1014 | static void snd_m3_dec_timer_users(struct snd_m3 *chip) |
1da177e4 LT |
1015 | { |
1016 | chip->timer_users--; | |
1017 | if (chip->timer_users > 0) | |
1018 | return; | |
1019 | ||
1020 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
1021 | KDATA_TIMER_COUNT_RELOAD, | |
1022 | 0); | |
1023 | ||
1024 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
1025 | KDATA_TIMER_COUNT_CURRENT, | |
1026 | 0); | |
1027 | ||
1028 | snd_m3_outw(chip, | |
1029 | snd_m3_inw(chip, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE, | |
1030 | HOST_INT_CTRL); | |
1031 | } | |
1032 | ||
1033 | /* | |
1034 | * start/stop | |
1035 | */ | |
1036 | ||
1037 | /* spinlock held! */ | |
3470c29d TI |
1038 | static int snd_m3_pcm_start(struct snd_m3 *chip, struct m3_dma *s, |
1039 | struct snd_pcm_substream *subs) | |
1da177e4 LT |
1040 | { |
1041 | if (! s || ! subs) | |
1042 | return -EINVAL; | |
1043 | ||
1044 | snd_m3_inc_timer_users(chip); | |
1045 | switch (subs->stream) { | |
1046 | case SNDRV_PCM_STREAM_PLAYBACK: | |
1047 | chip->dacs_active++; | |
1048 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
1049 | s->inst.data + CDATA_INSTANCE_READY, 1); | |
1050 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
1051 | KDATA_MIXER_TASK_NUMBER, | |
1052 | chip->dacs_active); | |
1053 | break; | |
1054 | case SNDRV_PCM_STREAM_CAPTURE: | |
3470c29d | 1055 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
1da177e4 LT |
1056 | KDATA_ADC1_REQUEST, 1); |
1057 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
1058 | s->inst.data + CDATA_INSTANCE_READY, 1); | |
1059 | break; | |
1060 | } | |
1061 | return 0; | |
1062 | } | |
1063 | ||
1064 | /* spinlock held! */ | |
3470c29d TI |
1065 | static int snd_m3_pcm_stop(struct snd_m3 *chip, struct m3_dma *s, |
1066 | struct snd_pcm_substream *subs) | |
1da177e4 LT |
1067 | { |
1068 | if (! s || ! subs) | |
1069 | return -EINVAL; | |
1070 | ||
1071 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
1072 | s->inst.data + CDATA_INSTANCE_READY, 0); | |
1073 | snd_m3_dec_timer_users(chip); | |
1074 | switch (subs->stream) { | |
1075 | case SNDRV_PCM_STREAM_PLAYBACK: | |
1076 | chip->dacs_active--; | |
1077 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
1078 | KDATA_MIXER_TASK_NUMBER, | |
1079 | chip->dacs_active); | |
1080 | break; | |
1081 | case SNDRV_PCM_STREAM_CAPTURE: | |
1082 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
1083 | KDATA_ADC1_REQUEST, 0); | |
1084 | break; | |
1085 | } | |
1086 | return 0; | |
1087 | } | |
1088 | ||
1089 | static int | |
3470c29d | 1090 | snd_m3_pcm_trigger(struct snd_pcm_substream *subs, int cmd) |
1da177e4 | 1091 | { |
3470c29d TI |
1092 | struct snd_m3 *chip = snd_pcm_substream_chip(subs); |
1093 | struct m3_dma *s = subs->runtime->private_data; | |
1da177e4 LT |
1094 | int err = -EINVAL; |
1095 | ||
da3cec35 TI |
1096 | if (snd_BUG_ON(!s)) |
1097 | return -ENXIO; | |
1da177e4 LT |
1098 | |
1099 | spin_lock(&chip->reg_lock); | |
1100 | switch (cmd) { | |
1101 | case SNDRV_PCM_TRIGGER_START: | |
1102 | case SNDRV_PCM_TRIGGER_RESUME: | |
1103 | if (s->running) | |
1104 | err = -EBUSY; | |
1105 | else { | |
1106 | s->running = 1; | |
1107 | err = snd_m3_pcm_start(chip, s, subs); | |
1108 | } | |
1109 | break; | |
1110 | case SNDRV_PCM_TRIGGER_STOP: | |
1111 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
1112 | if (! s->running) | |
1113 | err = 0; /* should return error? */ | |
1114 | else { | |
1115 | s->running = 0; | |
1116 | err = snd_m3_pcm_stop(chip, s, subs); | |
1117 | } | |
1118 | break; | |
1119 | } | |
1120 | spin_unlock(&chip->reg_lock); | |
1121 | return err; | |
1122 | } | |
1123 | ||
1124 | /* | |
1125 | * setup | |
1126 | */ | |
1127 | static void | |
3470c29d | 1128 | snd_m3_pcm_setup1(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs) |
1da177e4 LT |
1129 | { |
1130 | int dsp_in_size, dsp_out_size, dsp_in_buffer, dsp_out_buffer; | |
3470c29d | 1131 | struct snd_pcm_runtime *runtime = subs->runtime; |
1da177e4 LT |
1132 | |
1133 | if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
1134 | dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2); | |
1135 | dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2); | |
1136 | } else { | |
1137 | dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2); | |
1138 | dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2); | |
1139 | } | |
1140 | dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2); | |
1141 | dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1; | |
1142 | ||
1143 | s->dma_size = frames_to_bytes(runtime, runtime->buffer_size); | |
1144 | s->period_size = frames_to_bytes(runtime, runtime->period_size); | |
1145 | s->hwptr = 0; | |
1146 | s->count = 0; | |
1147 | ||
1148 | #define LO(x) ((x) & 0xffff) | |
1149 | #define HI(x) LO((x) >> 16) | |
1150 | ||
1151 | /* host dma buffer pointers */ | |
1152 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
1153 | s->inst.data + CDATA_HOST_SRC_ADDRL, | |
1154 | LO(s->buffer_addr)); | |
1155 | ||
1156 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
1157 | s->inst.data + CDATA_HOST_SRC_ADDRH, | |
1158 | HI(s->buffer_addr)); | |
1159 | ||
1160 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
1161 | s->inst.data + CDATA_HOST_SRC_END_PLUS_1L, | |
1162 | LO(s->buffer_addr + s->dma_size)); | |
1163 | ||
1164 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
1165 | s->inst.data + CDATA_HOST_SRC_END_PLUS_1H, | |
1166 | HI(s->buffer_addr + s->dma_size)); | |
1167 | ||
1168 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
1169 | s->inst.data + CDATA_HOST_SRC_CURRENTL, | |
1170 | LO(s->buffer_addr)); | |
1171 | ||
1172 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
1173 | s->inst.data + CDATA_HOST_SRC_CURRENTH, | |
1174 | HI(s->buffer_addr)); | |
1175 | #undef LO | |
1176 | #undef HI | |
1177 | ||
1178 | /* dsp buffers */ | |
1179 | ||
1180 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
1181 | s->inst.data + CDATA_IN_BUF_BEGIN, | |
1182 | dsp_in_buffer); | |
1183 | ||
1184 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
1185 | s->inst.data + CDATA_IN_BUF_END_PLUS_1, | |
1186 | dsp_in_buffer + (dsp_in_size / 2)); | |
1187 | ||
1188 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
1189 | s->inst.data + CDATA_IN_BUF_HEAD, | |
1190 | dsp_in_buffer); | |
1191 | ||
1192 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
1193 | s->inst.data + CDATA_IN_BUF_TAIL, | |
1194 | dsp_in_buffer); | |
1195 | ||
1196 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
1197 | s->inst.data + CDATA_OUT_BUF_BEGIN, | |
1198 | dsp_out_buffer); | |
1199 | ||
1200 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
1201 | s->inst.data + CDATA_OUT_BUF_END_PLUS_1, | |
1202 | dsp_out_buffer + (dsp_out_size / 2)); | |
1203 | ||
1204 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
1205 | s->inst.data + CDATA_OUT_BUF_HEAD, | |
1206 | dsp_out_buffer); | |
1207 | ||
1208 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
1209 | s->inst.data + CDATA_OUT_BUF_TAIL, | |
1210 | dsp_out_buffer); | |
1211 | } | |
1212 | ||
3470c29d TI |
1213 | static void snd_m3_pcm_setup2(struct snd_m3 *chip, struct m3_dma *s, |
1214 | struct snd_pcm_runtime *runtime) | |
1da177e4 LT |
1215 | { |
1216 | u32 freq; | |
1217 | ||
1218 | /* | |
1219 | * put us in the lists if we're not already there | |
1220 | */ | |
1221 | if (! s->in_lists) { | |
1222 | s->index[0] = snd_m3_add_list(chip, s->index_list[0], | |
1223 | s->inst.data >> DP_SHIFT_COUNT); | |
1224 | s->index[1] = snd_m3_add_list(chip, s->index_list[1], | |
1225 | s->inst.data >> DP_SHIFT_COUNT); | |
1226 | s->index[2] = snd_m3_add_list(chip, s->index_list[2], | |
1227 | s->inst.data >> DP_SHIFT_COUNT); | |
1228 | s->in_lists = 1; | |
1229 | } | |
1230 | ||
1231 | /* write to 'mono' word */ | |
1232 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
1233 | s->inst.data + SRC3_DIRECTION_OFFSET + 1, | |
1234 | runtime->channels == 2 ? 0 : 1); | |
1235 | /* write to '8bit' word */ | |
1236 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
1237 | s->inst.data + SRC3_DIRECTION_OFFSET + 2, | |
1238 | snd_pcm_format_width(runtime->format) == 16 ? 0 : 1); | |
1239 | ||
1240 | /* set up dac/adc rate */ | |
64062869 | 1241 | freq = DIV_ROUND_CLOSEST(runtime->rate << 15, 48000); |
1da177e4 LT |
1242 | if (freq) |
1243 | freq--; | |
1244 | ||
1245 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
1246 | s->inst.data + CDATA_FREQUENCY, | |
1247 | freq); | |
1248 | } | |
1249 | ||
1250 | ||
0b2dcd5d | 1251 | static const struct play_vals { |
1da177e4 LT |
1252 | u16 addr, val; |
1253 | } pv[] = { | |
1254 | {CDATA_LEFT_VOLUME, ARB_VOLUME}, | |
1255 | {CDATA_RIGHT_VOLUME, ARB_VOLUME}, | |
1256 | {SRC3_DIRECTION_OFFSET, 0} , | |
1257 | /* +1, +2 are stereo/16 bit */ | |
1258 | {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */ | |
1259 | {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */ | |
1260 | {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */ | |
1261 | {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */ | |
1262 | {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */ | |
1263 | {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */ | |
1264 | {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */ | |
1265 | {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */ | |
1266 | {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */ | |
1267 | {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */ | |
1268 | {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */ | |
1269 | {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */ | |
1270 | {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */ | |
1271 | {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */ | |
1272 | {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */ | |
1273 | {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */ | |
1274 | {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */ | |
1275 | }; | |
1276 | ||
1277 | ||
1278 | /* the mode passed should be already shifted and masked */ | |
1279 | static void | |
3470c29d TI |
1280 | snd_m3_playback_setup(struct snd_m3 *chip, struct m3_dma *s, |
1281 | struct snd_pcm_substream *subs) | |
1da177e4 LT |
1282 | { |
1283 | unsigned int i; | |
1284 | ||
1285 | /* | |
1286 | * some per client initializers | |
1287 | */ | |
1288 | ||
1289 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
1290 | s->inst.data + SRC3_DIRECTION_OFFSET + 12, | |
1291 | s->inst.data + 40 + 8); | |
1292 | ||
1293 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
1294 | s->inst.data + SRC3_DIRECTION_OFFSET + 19, | |
1295 | s->inst.code + MINISRC_COEF_LOC); | |
1296 | ||
1297 | /* enable or disable low pass filter? */ | |
1298 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
1299 | s->inst.data + SRC3_DIRECTION_OFFSET + 22, | |
1300 | subs->runtime->rate > 45000 ? 0xff : 0); | |
1301 | ||
1302 | /* tell it which way dma is going? */ | |
1303 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
1304 | s->inst.data + CDATA_DMA_CONTROL, | |
1305 | DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR); | |
1306 | ||
1307 | /* | |
1308 | * set an armload of static initializers | |
1309 | */ | |
1310 | for (i = 0; i < ARRAY_SIZE(pv); i++) | |
1311 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
1312 | s->inst.data + pv[i].addr, pv[i].val); | |
1313 | } | |
1314 | ||
1315 | /* | |
1316 | * Native record driver | |
1317 | */ | |
0b2dcd5d | 1318 | static const struct rec_vals { |
1da177e4 LT |
1319 | u16 addr, val; |
1320 | } rv[] = { | |
1321 | {CDATA_LEFT_VOLUME, ARB_VOLUME}, | |
1322 | {CDATA_RIGHT_VOLUME, ARB_VOLUME}, | |
1323 | {SRC3_DIRECTION_OFFSET, 1} , | |
1324 | /* +1, +2 are stereo/16 bit */ | |
1325 | {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */ | |
1326 | {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */ | |
1327 | {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */ | |
1328 | {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */ | |
1329 | {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */ | |
1330 | {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */ | |
1331 | {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */ | |
1332 | {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */ | |
1333 | {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */ | |
1334 | {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */ | |
1335 | {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */ | |
1336 | {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */ | |
1337 | {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */ | |
1338 | {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */ | |
1339 | {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */ | |
1340 | {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */ | |
1341 | {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */ | |
1342 | {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */ | |
1343 | {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */ | |
1344 | }; | |
1345 | ||
1346 | static void | |
3470c29d | 1347 | snd_m3_capture_setup(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs) |
1da177e4 LT |
1348 | { |
1349 | unsigned int i; | |
1350 | ||
1351 | /* | |
1352 | * some per client initializers | |
1353 | */ | |
1354 | ||
1355 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
1356 | s->inst.data + SRC3_DIRECTION_OFFSET + 12, | |
1357 | s->inst.data + 40 + 8); | |
1358 | ||
1359 | /* tell it which way dma is going? */ | |
1360 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
1361 | s->inst.data + CDATA_DMA_CONTROL, | |
1362 | DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT + | |
1363 | DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR); | |
1364 | ||
1365 | /* | |
1366 | * set an armload of static initializers | |
1367 | */ | |
1368 | for (i = 0; i < ARRAY_SIZE(rv); i++) | |
1369 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
1370 | s->inst.data + rv[i].addr, rv[i].val); | |
1371 | } | |
1372 | ||
3470c29d TI |
1373 | static int snd_m3_pcm_hw_params(struct snd_pcm_substream *substream, |
1374 | struct snd_pcm_hw_params *hw_params) | |
1da177e4 | 1375 | { |
3470c29d | 1376 | struct m3_dma *s = substream->runtime->private_data; |
1da177e4 | 1377 | |
1da177e4 LT |
1378 | /* set buffer address */ |
1379 | s->buffer_addr = substream->runtime->dma_addr; | |
1380 | if (s->buffer_addr & 0x3) { | |
747ce5b3 | 1381 | dev_err(substream->pcm->card->dev, "oh my, not aligned\n"); |
1da177e4 LT |
1382 | s->buffer_addr = s->buffer_addr & ~0x3; |
1383 | } | |
1384 | return 0; | |
1385 | } | |
1386 | ||
3470c29d | 1387 | static int snd_m3_pcm_hw_free(struct snd_pcm_substream *substream) |
1da177e4 | 1388 | { |
3470c29d | 1389 | struct m3_dma *s; |
1da177e4 LT |
1390 | |
1391 | if (substream->runtime->private_data == NULL) | |
1392 | return 0; | |
3470c29d | 1393 | s = substream->runtime->private_data; |
1da177e4 LT |
1394 | s->buffer_addr = 0; |
1395 | return 0; | |
1396 | } | |
1397 | ||
1398 | static int | |
3470c29d | 1399 | snd_m3_pcm_prepare(struct snd_pcm_substream *subs) |
1da177e4 | 1400 | { |
3470c29d TI |
1401 | struct snd_m3 *chip = snd_pcm_substream_chip(subs); |
1402 | struct snd_pcm_runtime *runtime = subs->runtime; | |
1403 | struct m3_dma *s = runtime->private_data; | |
1da177e4 | 1404 | |
da3cec35 TI |
1405 | if (snd_BUG_ON(!s)) |
1406 | return -ENXIO; | |
1da177e4 LT |
1407 | |
1408 | if (runtime->format != SNDRV_PCM_FORMAT_U8 && | |
1409 | runtime->format != SNDRV_PCM_FORMAT_S16_LE) | |
1410 | return -EINVAL; | |
1411 | if (runtime->rate > 48000 || | |
1412 | runtime->rate < 8000) | |
1413 | return -EINVAL; | |
1414 | ||
1415 | spin_lock_irq(&chip->reg_lock); | |
1416 | ||
1417 | snd_m3_pcm_setup1(chip, s, subs); | |
1418 | ||
1419 | if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
1420 | snd_m3_playback_setup(chip, s, subs); | |
1421 | else | |
1422 | snd_m3_capture_setup(chip, s, subs); | |
1423 | ||
1424 | snd_m3_pcm_setup2(chip, s, runtime); | |
1425 | ||
1426 | spin_unlock_irq(&chip->reg_lock); | |
1427 | ||
1428 | return 0; | |
1429 | } | |
1430 | ||
1431 | /* | |
1432 | * get current pointer | |
1433 | */ | |
1434 | static unsigned int | |
3470c29d | 1435 | snd_m3_get_pointer(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs) |
1da177e4 LT |
1436 | { |
1437 | u16 hi = 0, lo = 0; | |
1438 | int retry = 10; | |
1439 | u32 addr; | |
1440 | ||
1441 | /* | |
1442 | * try and get a valid answer | |
1443 | */ | |
1444 | while (retry--) { | |
1445 | hi = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, | |
1446 | s->inst.data + CDATA_HOST_SRC_CURRENTH); | |
1447 | ||
1448 | lo = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, | |
1449 | s->inst.data + CDATA_HOST_SRC_CURRENTL); | |
1450 | ||
1451 | if (hi == snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, | |
1452 | s->inst.data + CDATA_HOST_SRC_CURRENTH)) | |
1453 | break; | |
1454 | } | |
1455 | addr = lo | ((u32)hi<<16); | |
1456 | return (unsigned int)(addr - s->buffer_addr); | |
1457 | } | |
1458 | ||
1459 | static snd_pcm_uframes_t | |
3470c29d | 1460 | snd_m3_pcm_pointer(struct snd_pcm_substream *subs) |
1da177e4 | 1461 | { |
3470c29d | 1462 | struct snd_m3 *chip = snd_pcm_substream_chip(subs); |
1da177e4 | 1463 | unsigned int ptr; |
3470c29d | 1464 | struct m3_dma *s = subs->runtime->private_data; |
da3cec35 TI |
1465 | |
1466 | if (snd_BUG_ON(!s)) | |
1467 | return 0; | |
1da177e4 LT |
1468 | |
1469 | spin_lock(&chip->reg_lock); | |
1470 | ptr = snd_m3_get_pointer(chip, s, subs); | |
1471 | spin_unlock(&chip->reg_lock); | |
1472 | return bytes_to_frames(subs->runtime, ptr); | |
1473 | } | |
1474 | ||
1475 | ||
1476 | /* update pointer */ | |
1477 | /* spinlock held! */ | |
3470c29d | 1478 | static void snd_m3_update_ptr(struct snd_m3 *chip, struct m3_dma *s) |
1da177e4 | 1479 | { |
3470c29d | 1480 | struct snd_pcm_substream *subs = s->substream; |
1da177e4 LT |
1481 | unsigned int hwptr; |
1482 | int diff; | |
1483 | ||
1484 | if (! s->running) | |
1485 | return; | |
1486 | ||
0b2dcd5d AM |
1487 | hwptr = snd_m3_get_pointer(chip, s, subs); |
1488 | ||
1489 | /* try to avoid expensive modulo divisions */ | |
1490 | if (hwptr >= s->dma_size) | |
1491 | hwptr %= s->dma_size; | |
1492 | ||
1493 | diff = s->dma_size + hwptr - s->hwptr; | |
1494 | if (diff >= s->dma_size) | |
1495 | diff %= s->dma_size; | |
1496 | ||
1da177e4 LT |
1497 | s->hwptr = hwptr; |
1498 | s->count += diff; | |
0b2dcd5d | 1499 | |
1da177e4 | 1500 | if (s->count >= (signed)s->period_size) { |
0b2dcd5d AM |
1501 | |
1502 | if (s->count < 2 * (signed)s->period_size) | |
1503 | s->count -= (signed)s->period_size; | |
1504 | else | |
1505 | s->count %= s->period_size; | |
1506 | ||
1da177e4 LT |
1507 | spin_unlock(&chip->reg_lock); |
1508 | snd_pcm_period_elapsed(subs); | |
1509 | spin_lock(&chip->reg_lock); | |
1510 | } | |
1511 | } | |
1512 | ||
20133d4c HG |
1513 | /* The m3's hardware volume works by incrementing / decrementing 2 counters |
1514 | (without wrap around) in response to volume button presses and then | |
1515 | generating an interrupt. The pair of counters is stored in bits 1-3 and 5-7 | |
1516 | of a byte wide register. The meaning of bits 0 and 4 is unknown. */ | |
30bdee02 | 1517 | static void snd_m3_update_hw_volume(struct work_struct *work) |
db68d15d | 1518 | { |
30bdee02 | 1519 | struct snd_m3 *chip = container_of(work, struct snd_m3, hwvol_work); |
db68d15d | 1520 | int x, val; |
db68d15d VS |
1521 | |
1522 | /* Figure out which volume control button was pushed, | |
1523 | based on differences from the default register | |
1524 | values. */ | |
1525 | x = inb(chip->iobase + SHADOW_MIX_REG_VOICE) & 0xee; | |
1526 | ||
20133d4c HG |
1527 | /* Reset the volume counters to 4. Tests on the allegro integrated |
1528 | into a Compaq N600C laptop, have revealed that: | |
1529 | 1) Writing any value will result in the 2 counters being reset to | |
1530 | 4 so writing 0x88 is not strictly necessary | |
1531 | 2) Writing to any of the 4 involved registers will reset all 4 | |
1532 | of them (and reading them always returns the same value for all | |
1533 | of them) | |
1534 | It could be that a maestro deviates from this, so leave the code | |
1535 | as is. */ | |
db68d15d VS |
1536 | outb(0x88, chip->iobase + SHADOW_MIX_REG_VOICE); |
1537 | outb(0x88, chip->iobase + HW_VOL_COUNTER_VOICE); | |
1538 | outb(0x88, chip->iobase + SHADOW_MIX_REG_MASTER); | |
1539 | outb(0x88, chip->iobase + HW_VOL_COUNTER_MASTER); | |
1540 | ||
715aa675 HG |
1541 | /* Ignore spurious HV interrupts during suspend / resume, this avoids |
1542 | mistaking them for a mute button press. */ | |
1543 | if (chip->in_suspend) | |
1544 | return; | |
1545 | ||
eb581adf | 1546 | #ifndef CONFIG_SND_MAESTRO3_INPUT |
db68d15d VS |
1547 | if (!chip->master_switch || !chip->master_volume) |
1548 | return; | |
1549 | ||
30bdee02 | 1550 | val = snd_ac97_read(chip->ac97, AC97_MASTER); |
db68d15d VS |
1551 | switch (x) { |
1552 | case 0x88: | |
20133d4c HG |
1553 | /* The counters have not changed, yet we've received a HV |
1554 | interrupt. According to tests run by various people this | |
1555 | happens when pressing the mute button. */ | |
db68d15d | 1556 | val ^= 0x8000; |
db68d15d VS |
1557 | break; |
1558 | case 0xaa: | |
20133d4c | 1559 | /* counters increased by 1 -> volume up */ |
db68d15d VS |
1560 | if ((val & 0x7f) > 0) |
1561 | val--; | |
1562 | if ((val & 0x7f00) > 0) | |
1563 | val -= 0x0100; | |
db68d15d VS |
1564 | break; |
1565 | case 0x66: | |
20133d4c | 1566 | /* counters decreased by 1 -> volume down */ |
db68d15d VS |
1567 | if ((val & 0x7f) < 0x1f) |
1568 | val++; | |
1569 | if ((val & 0x7f00) < 0x1f00) | |
1570 | val += 0x0100; | |
db68d15d VS |
1571 | break; |
1572 | } | |
30bdee02 TI |
1573 | if (snd_ac97_update(chip->ac97, AC97_MASTER, val)) |
1574 | snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, | |
1575 | &chip->master_switch->id); | |
eb581adf HG |
1576 | #else |
1577 | if (!chip->input_dev) | |
1578 | return; | |
1579 | ||
1580 | val = 0; | |
1581 | switch (x) { | |
1582 | case 0x88: | |
1583 | /* The counters have not changed, yet we've received a HV | |
1584 | interrupt. According to tests run by various people this | |
1585 | happens when pressing the mute button. */ | |
1586 | val = KEY_MUTE; | |
1587 | break; | |
1588 | case 0xaa: | |
1589 | /* counters increased by 1 -> volume up */ | |
1590 | val = KEY_VOLUMEUP; | |
1591 | break; | |
1592 | case 0x66: | |
1593 | /* counters decreased by 1 -> volume down */ | |
1594 | val = KEY_VOLUMEDOWN; | |
1595 | break; | |
1596 | } | |
1597 | ||
1598 | if (val) { | |
1599 | input_report_key(chip->input_dev, val, 1); | |
1600 | input_sync(chip->input_dev); | |
1601 | input_report_key(chip->input_dev, val, 0); | |
1602 | input_sync(chip->input_dev); | |
1603 | } | |
1604 | #endif | |
db68d15d VS |
1605 | } |
1606 | ||
7d12e780 | 1607 | static irqreturn_t snd_m3_interrupt(int irq, void *dev_id) |
1da177e4 | 1608 | { |
3470c29d | 1609 | struct snd_m3 *chip = dev_id; |
1da177e4 LT |
1610 | u8 status; |
1611 | int i; | |
1612 | ||
1613 | status = inb(chip->iobase + HOST_INT_STATUS); | |
1614 | ||
1615 | if (status == 0xff) | |
1616 | return IRQ_NONE; | |
db68d15d VS |
1617 | |
1618 | if (status & HV_INT_PENDING) | |
30bdee02 | 1619 | schedule_work(&chip->hwvol_work); |
db68d15d | 1620 | |
1da177e4 LT |
1621 | /* |
1622 | * ack an assp int if its running | |
1623 | * and has an int pending | |
1624 | */ | |
1625 | if (status & ASSP_INT_PENDING) { | |
1626 | u8 ctl = inb(chip->iobase + ASSP_CONTROL_B); | |
1627 | if (!(ctl & STOP_ASSP_CLOCK)) { | |
1628 | ctl = inb(chip->iobase + ASSP_HOST_INT_STATUS); | |
1629 | if (ctl & DSP2HOST_REQ_TIMER) { | |
1630 | outb(DSP2HOST_REQ_TIMER, chip->iobase + ASSP_HOST_INT_STATUS); | |
1631 | /* update adc/dac info if it was a timer int */ | |
1632 | spin_lock(&chip->reg_lock); | |
1633 | for (i = 0; i < chip->num_substreams; i++) { | |
3470c29d | 1634 | struct m3_dma *s = &chip->substreams[i]; |
1da177e4 LT |
1635 | if (s->running) |
1636 | snd_m3_update_ptr(chip, s); | |
1637 | } | |
1638 | spin_unlock(&chip->reg_lock); | |
1639 | } | |
1640 | } | |
1641 | } | |
1642 | ||
1643 | #if 0 /* TODO: not supported yet */ | |
1644 | if ((status & MPU401_INT_PENDING) && chip->rmidi) | |
1645 | snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs); | |
1646 | #endif | |
1647 | ||
1648 | /* ack ints */ | |
88491386 | 1649 | outb(status, chip->iobase + HOST_INT_STATUS); |
1da177e4 LT |
1650 | |
1651 | return IRQ_HANDLED; | |
1652 | } | |
1653 | ||
1654 | ||
1655 | /* | |
1656 | */ | |
1657 | ||
dee49895 | 1658 | static const struct snd_pcm_hardware snd_m3_playback = |
1da177e4 LT |
1659 | { |
1660 | .info = (SNDRV_PCM_INFO_MMAP | | |
1661 | SNDRV_PCM_INFO_INTERLEAVED | | |
1662 | SNDRV_PCM_INFO_MMAP_VALID | | |
1663 | SNDRV_PCM_INFO_BLOCK_TRANSFER | | |
1664 | /*SNDRV_PCM_INFO_PAUSE |*/ | |
1665 | SNDRV_PCM_INFO_RESUME), | |
1666 | .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, | |
1667 | .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, | |
1668 | .rate_min = 8000, | |
1669 | .rate_max = 48000, | |
1670 | .channels_min = 1, | |
1671 | .channels_max = 2, | |
1672 | .buffer_bytes_max = (512*1024), | |
1673 | .period_bytes_min = 64, | |
1674 | .period_bytes_max = (512*1024), | |
1675 | .periods_min = 1, | |
1676 | .periods_max = 1024, | |
1677 | }; | |
1678 | ||
dee49895 | 1679 | static const struct snd_pcm_hardware snd_m3_capture = |
1da177e4 LT |
1680 | { |
1681 | .info = (SNDRV_PCM_INFO_MMAP | | |
1682 | SNDRV_PCM_INFO_INTERLEAVED | | |
1683 | SNDRV_PCM_INFO_MMAP_VALID | | |
1684 | SNDRV_PCM_INFO_BLOCK_TRANSFER | | |
1685 | /*SNDRV_PCM_INFO_PAUSE |*/ | |
1686 | SNDRV_PCM_INFO_RESUME), | |
1687 | .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, | |
1688 | .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, | |
1689 | .rate_min = 8000, | |
1690 | .rate_max = 48000, | |
1691 | .channels_min = 1, | |
1692 | .channels_max = 2, | |
1693 | .buffer_bytes_max = (512*1024), | |
1694 | .period_bytes_min = 64, | |
1695 | .period_bytes_max = (512*1024), | |
1696 | .periods_min = 1, | |
1697 | .periods_max = 1024, | |
1698 | }; | |
1699 | ||
1700 | ||
1701 | /* | |
1702 | */ | |
1703 | ||
1704 | static int | |
3470c29d | 1705 | snd_m3_substream_open(struct snd_m3 *chip, struct snd_pcm_substream *subs) |
1da177e4 LT |
1706 | { |
1707 | int i; | |
3470c29d | 1708 | struct m3_dma *s; |
1da177e4 LT |
1709 | |
1710 | spin_lock_irq(&chip->reg_lock); | |
1711 | for (i = 0; i < chip->num_substreams; i++) { | |
1712 | s = &chip->substreams[i]; | |
1713 | if (! s->opened) | |
1714 | goto __found; | |
1715 | } | |
1716 | spin_unlock_irq(&chip->reg_lock); | |
1717 | return -ENOMEM; | |
1718 | __found: | |
1719 | s->opened = 1; | |
1720 | s->running = 0; | |
1721 | spin_unlock_irq(&chip->reg_lock); | |
1722 | ||
1723 | subs->runtime->private_data = s; | |
1724 | s->substream = subs; | |
1725 | ||
1726 | /* set list owners */ | |
1727 | if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
1728 | s->index_list[0] = &chip->mixer_list; | |
1729 | } else | |
1730 | s->index_list[0] = &chip->adc1_list; | |
1731 | s->index_list[1] = &chip->msrc_list; | |
1732 | s->index_list[2] = &chip->dma_list; | |
1733 | ||
1734 | return 0; | |
1735 | } | |
1736 | ||
1737 | static void | |
3470c29d | 1738 | snd_m3_substream_close(struct snd_m3 *chip, struct snd_pcm_substream *subs) |
1da177e4 | 1739 | { |
3470c29d | 1740 | struct m3_dma *s = subs->runtime->private_data; |
1da177e4 LT |
1741 | |
1742 | if (s == NULL) | |
1743 | return; /* not opened properly */ | |
1744 | ||
1745 | spin_lock_irq(&chip->reg_lock); | |
1746 | if (s->substream && s->running) | |
1747 | snd_m3_pcm_stop(chip, s, s->substream); /* does this happen? */ | |
1748 | if (s->in_lists) { | |
1749 | snd_m3_remove_list(chip, s->index_list[0], s->index[0]); | |
1750 | snd_m3_remove_list(chip, s->index_list[1], s->index[1]); | |
1751 | snd_m3_remove_list(chip, s->index_list[2], s->index[2]); | |
1752 | s->in_lists = 0; | |
1753 | } | |
1754 | s->running = 0; | |
1755 | s->opened = 0; | |
1756 | spin_unlock_irq(&chip->reg_lock); | |
1757 | } | |
1758 | ||
1759 | static int | |
3470c29d | 1760 | snd_m3_playback_open(struct snd_pcm_substream *subs) |
1da177e4 | 1761 | { |
3470c29d TI |
1762 | struct snd_m3 *chip = snd_pcm_substream_chip(subs); |
1763 | struct snd_pcm_runtime *runtime = subs->runtime; | |
1da177e4 LT |
1764 | int err; |
1765 | ||
5cc16ba6 TI |
1766 | err = snd_m3_substream_open(chip, subs); |
1767 | if (err < 0) | |
1da177e4 LT |
1768 | return err; |
1769 | ||
1770 | runtime->hw = snd_m3_playback; | |
1da177e4 LT |
1771 | |
1772 | return 0; | |
1773 | } | |
1774 | ||
1775 | static int | |
3470c29d | 1776 | snd_m3_playback_close(struct snd_pcm_substream *subs) |
1da177e4 | 1777 | { |
3470c29d | 1778 | struct snd_m3 *chip = snd_pcm_substream_chip(subs); |
1da177e4 LT |
1779 | |
1780 | snd_m3_substream_close(chip, subs); | |
1781 | return 0; | |
1782 | } | |
1783 | ||
1784 | static int | |
3470c29d | 1785 | snd_m3_capture_open(struct snd_pcm_substream *subs) |
1da177e4 | 1786 | { |
3470c29d TI |
1787 | struct snd_m3 *chip = snd_pcm_substream_chip(subs); |
1788 | struct snd_pcm_runtime *runtime = subs->runtime; | |
1da177e4 LT |
1789 | int err; |
1790 | ||
5cc16ba6 TI |
1791 | err = snd_m3_substream_open(chip, subs); |
1792 | if (err < 0) | |
1da177e4 LT |
1793 | return err; |
1794 | ||
1795 | runtime->hw = snd_m3_capture; | |
1da177e4 LT |
1796 | |
1797 | return 0; | |
1798 | } | |
1799 | ||
1800 | static int | |
3470c29d | 1801 | snd_m3_capture_close(struct snd_pcm_substream *subs) |
1da177e4 | 1802 | { |
3470c29d | 1803 | struct snd_m3 *chip = snd_pcm_substream_chip(subs); |
1da177e4 LT |
1804 | |
1805 | snd_m3_substream_close(chip, subs); | |
1806 | return 0; | |
1807 | } | |
1808 | ||
1809 | /* | |
1810 | * create pcm instance | |
1811 | */ | |
1812 | ||
6769e988 | 1813 | static const struct snd_pcm_ops snd_m3_playback_ops = { |
1da177e4 LT |
1814 | .open = snd_m3_playback_open, |
1815 | .close = snd_m3_playback_close, | |
1da177e4 LT |
1816 | .hw_params = snd_m3_pcm_hw_params, |
1817 | .hw_free = snd_m3_pcm_hw_free, | |
1818 | .prepare = snd_m3_pcm_prepare, | |
1819 | .trigger = snd_m3_pcm_trigger, | |
1820 | .pointer = snd_m3_pcm_pointer, | |
1821 | }; | |
1822 | ||
6769e988 | 1823 | static const struct snd_pcm_ops snd_m3_capture_ops = { |
1da177e4 LT |
1824 | .open = snd_m3_capture_open, |
1825 | .close = snd_m3_capture_close, | |
1da177e4 LT |
1826 | .hw_params = snd_m3_pcm_hw_params, |
1827 | .hw_free = snd_m3_pcm_hw_free, | |
1828 | .prepare = snd_m3_pcm_prepare, | |
1829 | .trigger = snd_m3_pcm_trigger, | |
1830 | .pointer = snd_m3_pcm_pointer, | |
1831 | }; | |
1832 | ||
e23e7a14 | 1833 | static int |
3470c29d | 1834 | snd_m3_pcm(struct snd_m3 * chip, int device) |
1da177e4 | 1835 | { |
3470c29d | 1836 | struct snd_pcm *pcm; |
1da177e4 LT |
1837 | int err; |
1838 | ||
1839 | err = snd_pcm_new(chip->card, chip->card->driver, device, | |
1840 | MAX_PLAYBACKS, MAX_CAPTURES, &pcm); | |
1841 | if (err < 0) | |
1842 | return err; | |
1843 | ||
1844 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_m3_playback_ops); | |
1845 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_m3_capture_ops); | |
1846 | ||
1847 | pcm->private_data = chip; | |
1848 | pcm->info_flags = 0; | |
1849 | strcpy(pcm->name, chip->card->driver); | |
1850 | chip->pcm = pcm; | |
1851 | ||
e485e538 TI |
1852 | snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, |
1853 | &chip->pci->dev, 64*1024, 64*1024); | |
1da177e4 LT |
1854 | |
1855 | return 0; | |
1856 | } | |
1857 | ||
1858 | ||
1859 | /* | |
1860 | * ac97 interface | |
1861 | */ | |
1862 | ||
1863 | /* | |
1864 | * Wait for the ac97 serial bus to be free. | |
1865 | * return nonzero if the bus is still busy. | |
1866 | */ | |
3470c29d | 1867 | static int snd_m3_ac97_wait(struct snd_m3 *chip) |
1da177e4 LT |
1868 | { |
1869 | int i = 10000; | |
1870 | ||
1871 | do { | |
1872 | if (! (snd_m3_inb(chip, 0x30) & 1)) | |
1873 | return 0; | |
0b2dcd5d | 1874 | cpu_relax(); |
1da177e4 LT |
1875 | } while (i-- > 0); |
1876 | ||
747ce5b3 | 1877 | dev_err(chip->card->dev, "ac97 serial bus busy\n"); |
1da177e4 LT |
1878 | return 1; |
1879 | } | |
1880 | ||
1881 | static unsigned short | |
3470c29d | 1882 | snd_m3_ac97_read(struct snd_ac97 *ac97, unsigned short reg) |
1da177e4 | 1883 | { |
3470c29d | 1884 | struct snd_m3 *chip = ac97->private_data; |
0b2dcd5d | 1885 | unsigned short data = 0xffff; |
1da177e4 LT |
1886 | |
1887 | if (snd_m3_ac97_wait(chip)) | |
0b2dcd5d | 1888 | goto fail; |
1da177e4 LT |
1889 | snd_m3_outb(chip, 0x80 | (reg & 0x7f), CODEC_COMMAND); |
1890 | if (snd_m3_ac97_wait(chip)) | |
30bdee02 | 1891 | goto fail; |
db68d15d | 1892 | data = snd_m3_inw(chip, CODEC_DATA); |
0b2dcd5d | 1893 | fail: |
db68d15d | 1894 | return data; |
1da177e4 LT |
1895 | } |
1896 | ||
1897 | static void | |
3470c29d | 1898 | snd_m3_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val) |
1da177e4 | 1899 | { |
3470c29d | 1900 | struct snd_m3 *chip = ac97->private_data; |
1da177e4 LT |
1901 | |
1902 | if (snd_m3_ac97_wait(chip)) | |
1903 | return; | |
1904 | snd_m3_outw(chip, val, CODEC_DATA); | |
1905 | snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND); | |
2c8d0892 OZ |
1906 | /* |
1907 | * Workaround for buggy ES1988 integrated AC'97 codec. It remains silent | |
1908 | * until the MASTER volume or mute is touched (alsactl restore does not | |
1909 | * work). | |
1910 | */ | |
1911 | if (ac97->id == 0x45838308 && reg == AC97_MASTER) { | |
1912 | snd_m3_ac97_wait(chip); | |
1913 | snd_m3_outw(chip, val, CODEC_DATA); | |
1914 | snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND); | |
1915 | } | |
1da177e4 LT |
1916 | } |
1917 | ||
1918 | ||
030270ba | 1919 | static void snd_m3_remote_codec_config(struct snd_m3 *chip, int isremote) |
1da177e4 | 1920 | { |
030270ba OZ |
1921 | int io = chip->iobase; |
1922 | u16 tmp; | |
1923 | ||
1da177e4 LT |
1924 | isremote = isremote ? 1 : 0; |
1925 | ||
030270ba OZ |
1926 | tmp = inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK; |
1927 | /* enable dock on Dell Latitude C810 */ | |
1928 | if (chip->pci->subsystem_vendor == 0x1028 && | |
1929 | chip->pci->subsystem_device == 0x00e5) | |
1930 | tmp |= M3I_DOCK_ENABLE; | |
1931 | outw(tmp | isremote, io + RING_BUS_CTRL_B); | |
1da177e4 LT |
1932 | outw((inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote, |
1933 | io + SDO_OUT_DEST_CTRL); | |
1934 | outw((inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote, | |
1935 | io + SDO_IN_DEST_CTRL); | |
1936 | } | |
1937 | ||
1938 | /* | |
1939 | * hack, returns non zero on err | |
1940 | */ | |
3470c29d | 1941 | static int snd_m3_try_read_vendor(struct snd_m3 *chip) |
1da177e4 LT |
1942 | { |
1943 | u16 ret; | |
1944 | ||
1945 | if (snd_m3_ac97_wait(chip)) | |
1946 | return 1; | |
1947 | ||
1948 | snd_m3_outb(chip, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30); | |
1949 | ||
1950 | if (snd_m3_ac97_wait(chip)) | |
1951 | return 1; | |
1952 | ||
1953 | ret = snd_m3_inw(chip, 0x32); | |
1954 | ||
1955 | return (ret == 0) || (ret == 0xffff); | |
1956 | } | |
1957 | ||
3470c29d | 1958 | static void snd_m3_ac97_reset(struct snd_m3 *chip) |
1da177e4 LT |
1959 | { |
1960 | u16 dir; | |
1961 | int delay1 = 0, delay2 = 0, i; | |
1962 | int io = chip->iobase; | |
1963 | ||
1964 | if (chip->allegro_flag) { | |
1965 | /* | |
1966 | * the onboard codec on the allegro seems | |
1967 | * to want to wait a very long time before | |
1968 | * coming back to life | |
1969 | */ | |
1970 | delay1 = 50; | |
1971 | delay2 = 800; | |
1972 | } else { | |
1973 | /* maestro3 */ | |
1974 | delay1 = 20; | |
1975 | delay2 = 500; | |
1976 | } | |
1977 | ||
1978 | for (i = 0; i < 5; i++) { | |
1979 | dir = inw(io + GPIO_DIRECTION); | |
1061eeb4 | 1980 | if (!chip->irda_workaround) |
1da177e4 LT |
1981 | dir |= 0x10; /* assuming pci bus master? */ |
1982 | ||
030270ba | 1983 | snd_m3_remote_codec_config(chip, 0); |
1da177e4 LT |
1984 | |
1985 | outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A); | |
1986 | udelay(20); | |
1987 | ||
1988 | outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION); | |
1989 | outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK); | |
1990 | outw(0, io + GPIO_DATA); | |
1991 | outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION); | |
1992 | ||
8433a509 | 1993 | schedule_timeout_uninterruptible(msecs_to_jiffies(delay1)); |
1da177e4 LT |
1994 | |
1995 | outw(GPO_PRIMARY_AC97, io + GPIO_DATA); | |
1996 | udelay(5); | |
1997 | /* ok, bring back the ac-link */ | |
1998 | outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A); | |
1999 | outw(~0, io + GPIO_MASK); | |
2000 | ||
8433a509 | 2001 | schedule_timeout_uninterruptible(msecs_to_jiffies(delay2)); |
1da177e4 LT |
2002 | |
2003 | if (! snd_m3_try_read_vendor(chip)) | |
2004 | break; | |
2005 | ||
2006 | delay1 += 10; | |
2007 | delay2 += 100; | |
2008 | ||
747ce5b3 TI |
2009 | dev_dbg(chip->card->dev, |
2010 | "retrying codec reset with delays of %d and %d ms\n", | |
1da177e4 LT |
2011 | delay1, delay2); |
2012 | } | |
2013 | ||
2014 | #if 0 | |
2015 | /* more gung-ho reset that doesn't | |
2016 | * seem to work anywhere :) | |
2017 | */ | |
2018 | tmp = inw(io + RING_BUS_CTRL_A); | |
2019 | outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A); | |
5ba1e7b5 | 2020 | msleep(20); |
1da177e4 | 2021 | outw(tmp, io + RING_BUS_CTRL_A); |
5ba1e7b5 | 2022 | msleep(50); |
1da177e4 LT |
2023 | #endif |
2024 | } | |
2025 | ||
e23e7a14 | 2026 | static int snd_m3_mixer(struct snd_m3 *chip) |
1da177e4 | 2027 | { |
3470c29d TI |
2028 | struct snd_ac97_bus *pbus; |
2029 | struct snd_ac97_template ac97; | |
1da177e4 | 2030 | int err; |
51055da5 | 2031 | static const struct snd_ac97_bus_ops ops = { |
1da177e4 LT |
2032 | .write = snd_m3_ac97_write, |
2033 | .read = snd_m3_ac97_read, | |
2034 | }; | |
2035 | ||
5cc16ba6 TI |
2036 | err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus); |
2037 | if (err < 0) | |
1da177e4 LT |
2038 | return err; |
2039 | ||
2040 | memset(&ac97, 0, sizeof(ac97)); | |
2041 | ac97.private_data = chip; | |
5cc16ba6 TI |
2042 | err = snd_ac97_mixer(pbus, &ac97, &chip->ac97); |
2043 | if (err < 0) | |
1da177e4 LT |
2044 | return err; |
2045 | ||
2046 | /* seems ac97 PCM needs initialization.. hack hack.. */ | |
2047 | snd_ac97_write(chip->ac97, AC97_PCM, 0x8000 | (15 << 8) | 15); | |
8433a509 | 2048 | schedule_timeout_uninterruptible(msecs_to_jiffies(100)); |
1da177e4 LT |
2049 | snd_ac97_write(chip->ac97, AC97_PCM, 0); |
2050 | ||
eb581adf | 2051 | #ifndef CONFIG_SND_MAESTRO3_INPUT |
233913c0 TI |
2052 | chip->master_switch = snd_ctl_find_id_mixer(chip->card, |
2053 | "Master Playback Switch"); | |
2054 | chip->master_volume = snd_ctl_find_id_mixer(chip->card, | |
2055 | "Master Playback Volume"); | |
eb581adf | 2056 | #endif |
db68d15d | 2057 | |
1da177e4 LT |
2058 | return 0; |
2059 | } | |
2060 | ||
2061 | ||
1da177e4 LT |
2062 | /* |
2063 | * initialize ASSP | |
2064 | */ | |
2065 | ||
2066 | #define MINISRC_LPF_LEN 10 | |
f40b6890 | 2067 | static const u16 minisrc_lpf[MINISRC_LPF_LEN] = { |
1da177e4 LT |
2068 | 0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C, |
2069 | 0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F | |
2070 | }; | |
2071 | ||
f40b6890 | 2072 | static void snd_m3_assp_init(struct snd_m3 *chip) |
1da177e4 LT |
2073 | { |
2074 | unsigned int i; | |
8c0ab942 | 2075 | const __le16 *data; |
1da177e4 LT |
2076 | |
2077 | /* zero kernel data */ | |
2078 | for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++) | |
2079 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
2080 | KDATA_BASE_ADDR + i, 0); | |
2081 | ||
2082 | /* zero mixer data? */ | |
2083 | for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++) | |
2084 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
2085 | KDATA_BASE_ADDR2 + i, 0); | |
2086 | ||
2087 | /* init dma pointer */ | |
2088 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
2089 | KDATA_CURRENT_DMA, | |
2090 | KDATA_DMA_XFER0); | |
2091 | ||
2092 | /* write kernel into code memory.. */ | |
8c0ab942 | 2093 | data = (const __le16 *)chip->assp_kernel_image->data; |
81d7724a | 2094 | for (i = 0 ; i * 2 < chip->assp_kernel_image->size; i++) { |
1da177e4 | 2095 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, |
fa6e1cb6 DW |
2096 | REV_B_CODE_MEMORY_BEGIN + i, |
2097 | le16_to_cpu(data[i])); | |
1da177e4 LT |
2098 | } |
2099 | ||
2100 | /* | |
2101 | * We only have this one client and we know that 0x400 | |
2102 | * is free in our kernel's mem map, so lets just | |
2103 | * drop it there. It seems that the minisrc doesn't | |
2104 | * need vectors, so we won't bother with them.. | |
2105 | */ | |
8c0ab942 | 2106 | data = (const __le16 *)chip->assp_minisrc_image->data; |
81d7724a | 2107 | for (i = 0; i * 2 < chip->assp_minisrc_image->size; i++) { |
1da177e4 | 2108 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, |
fa6e1cb6 | 2109 | 0x400 + i, le16_to_cpu(data[i])); |
1da177e4 LT |
2110 | } |
2111 | ||
2112 | /* | |
2113 | * write the coefficients for the low pass filter? | |
2114 | */ | |
2115 | for (i = 0; i < MINISRC_LPF_LEN ; i++) { | |
2116 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, | |
2117 | 0x400 + MINISRC_COEF_LOC + i, | |
2118 | minisrc_lpf[i]); | |
2119 | } | |
2120 | ||
2121 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, | |
2122 | 0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN, | |
2123 | 0x8000); | |
2124 | ||
2125 | /* | |
2126 | * the minisrc is the only thing on | |
2127 | * our task list.. | |
2128 | */ | |
2129 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
2130 | KDATA_TASK0, | |
2131 | 0x400); | |
2132 | ||
2133 | /* | |
2134 | * init the mixer number.. | |
2135 | */ | |
2136 | ||
2137 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
2138 | KDATA_MIXER_TASK_NUMBER,0); | |
2139 | ||
2140 | /* | |
2141 | * EXTREME KERNEL MASTER VOLUME | |
2142 | */ | |
2143 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
2144 | KDATA_DAC_LEFT_VOLUME, ARB_VOLUME); | |
2145 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
2146 | KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME); | |
2147 | ||
2148 | chip->mixer_list.curlen = 0; | |
2149 | chip->mixer_list.mem_addr = KDATA_MIXER_XFER0; | |
2150 | chip->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS; | |
2151 | chip->adc1_list.curlen = 0; | |
2152 | chip->adc1_list.mem_addr = KDATA_ADC1_XFER0; | |
2153 | chip->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS; | |
2154 | chip->dma_list.curlen = 0; | |
2155 | chip->dma_list.mem_addr = KDATA_DMA_XFER0; | |
2156 | chip->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS; | |
2157 | chip->msrc_list.curlen = 0; | |
2158 | chip->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC; | |
2159 | chip->msrc_list.max = MAX_INSTANCE_MINISRC; | |
2160 | } | |
2161 | ||
2162 | ||
e23e7a14 | 2163 | static int snd_m3_assp_client_init(struct snd_m3 *chip, struct m3_dma *s, int index) |
1da177e4 LT |
2164 | { |
2165 | int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 + | |
2166 | MINISRC_IN_BUFFER_SIZE / 2 + | |
2167 | 1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 ); | |
2168 | int address, i; | |
2169 | ||
2170 | /* | |
2171 | * the revb memory map has 0x1100 through 0x1c00 | |
2172 | * free. | |
2173 | */ | |
2174 | ||
2175 | /* | |
0b2dcd5d | 2176 | * align instance address to 256 bytes so that its |
1da177e4 LT |
2177 | * shifted list address is aligned. |
2178 | * list address = (mem address >> 1) >> 7; | |
2179 | */ | |
7ab39926 | 2180 | data_bytes = ALIGN(data_bytes, 256); |
1da177e4 LT |
2181 | address = 0x1100 + ((data_bytes/2) * index); |
2182 | ||
2183 | if ((address + (data_bytes/2)) >= 0x1c00) { | |
747ce5b3 TI |
2184 | dev_err(chip->card->dev, |
2185 | "no memory for %d bytes at ind %d (addr 0x%x)\n", | |
1da177e4 LT |
2186 | data_bytes, index, address); |
2187 | return -ENOMEM; | |
2188 | } | |
2189 | ||
2190 | s->number = index; | |
2191 | s->inst.code = 0x400; | |
2192 | s->inst.data = address; | |
2193 | ||
2194 | for (i = data_bytes / 2; i > 0; address++, i--) { | |
2195 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
2196 | address, 0); | |
2197 | } | |
2198 | ||
2199 | return 0; | |
2200 | } | |
2201 | ||
2202 | ||
2203 | /* | |
2204 | * this works for the reference board, have to find | |
2205 | * out about others | |
2206 | * | |
2207 | * this needs more magic for 4 speaker, but.. | |
2208 | */ | |
2209 | static void | |
3470c29d | 2210 | snd_m3_amp_enable(struct snd_m3 *chip, int enable) |
1da177e4 LT |
2211 | { |
2212 | int io = chip->iobase; | |
2213 | u16 gpo, polarity; | |
2214 | ||
2215 | if (! chip->external_amp) | |
2216 | return; | |
2217 | ||
2218 | polarity = enable ? 0 : 1; | |
2219 | polarity = polarity << chip->amp_gpio; | |
2220 | gpo = 1 << chip->amp_gpio; | |
2221 | ||
2222 | outw(~gpo, io + GPIO_MASK); | |
2223 | ||
2224 | outw(inw(io + GPIO_DIRECTION) | gpo, | |
2225 | io + GPIO_DIRECTION); | |
2226 | ||
2227 | outw((GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity), | |
2228 | io + GPIO_DATA); | |
2229 | ||
2230 | outw(0xffff, io + GPIO_MASK); | |
2231 | } | |
2232 | ||
8b83afe0 VS |
2233 | static void |
2234 | snd_m3_hv_init(struct snd_m3 *chip) | |
2235 | { | |
2236 | unsigned long io = chip->iobase; | |
2237 | u16 val = GPI_VOL_DOWN | GPI_VOL_UP; | |
2238 | ||
2239 | if (!chip->is_omnibook) | |
2240 | return; | |
2241 | ||
2242 | /* | |
2243 | * Volume buttons on some HP OmniBook laptops | |
2244 | * require some GPIO magic to work correctly. | |
2245 | */ | |
2246 | outw(0xffff, io + GPIO_MASK); | |
2247 | outw(0x0000, io + GPIO_DATA); | |
2248 | ||
2249 | outw(~val, io + GPIO_MASK); | |
2250 | outw(inw(io + GPIO_DIRECTION) & ~val, io + GPIO_DIRECTION); | |
2251 | outw(val, io + GPIO_MASK); | |
2252 | ||
2253 | outw(0xffff, io + GPIO_MASK); | |
2254 | } | |
2255 | ||
1da177e4 | 2256 | static int |
3470c29d | 2257 | snd_m3_chip_init(struct snd_m3 *chip) |
1da177e4 LT |
2258 | { |
2259 | struct pci_dev *pcidev = chip->pci; | |
db68d15d | 2260 | unsigned long io = chip->iobase; |
1da177e4 LT |
2261 | u32 n; |
2262 | u16 w; | |
2263 | u8 t; /* makes as much sense as 'n', no? */ | |
2264 | ||
2265 | pci_read_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, &w); | |
2266 | w &= ~(SOUND_BLASTER_ENABLE|FM_SYNTHESIS_ENABLE| | |
2267 | MPU401_IO_ENABLE|MPU401_IRQ_ENABLE|ALIAS_10BIT_IO| | |
2268 | DISABLE_LEGACY); | |
2269 | pci_write_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, w); | |
2270 | ||
2271 | pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n); | |
82f008c2 | 2272 | n &= ~(HV_CTRL_ENABLE | REDUCED_DEBOUNCE | HV_BUTTON_FROM_GD); |
1061eeb4 | 2273 | n |= chip->hv_config; |
82f008c2 VS |
2274 | /* For some reason we must always use reduced debounce. */ |
2275 | n |= REDUCED_DEBOUNCE; | |
1da177e4 LT |
2276 | n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING; |
2277 | pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n); | |
2278 | ||
2279 | outb(RESET_ASSP, chip->iobase + ASSP_CONTROL_B); | |
2280 | pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n); | |
2281 | n &= ~INT_CLK_SELECT; | |
2282 | if (!chip->allegro_flag) { | |
2283 | n &= ~INT_CLK_MULT_ENABLE; | |
2284 | n |= INT_CLK_SRC_NOT_PCI; | |
2285 | } | |
2286 | n &= ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 ); | |
2287 | pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n); | |
2288 | ||
2289 | if (chip->allegro_flag) { | |
2290 | pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n); | |
2291 | n |= IN_CLK_12MHZ_SELECT; | |
2292 | pci_write_config_dword(pcidev, PCI_USER_CONFIG, n); | |
2293 | } | |
2294 | ||
2295 | t = inb(chip->iobase + ASSP_CONTROL_A); | |
2296 | t &= ~( DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT); | |
2297 | t |= ASSP_CLK_49MHZ_SELECT; | |
2298 | t |= ASSP_0_WS_ENABLE; | |
2299 | outb(t, chip->iobase + ASSP_CONTROL_A); | |
2300 | ||
051b5165 | 2301 | snd_m3_assp_init(chip); /* download DSP code before starting ASSP below */ |
1da177e4 LT |
2302 | outb(RUN_ASSP, chip->iobase + ASSP_CONTROL_B); |
2303 | ||
db68d15d VS |
2304 | outb(0x00, io + HARDWARE_VOL_CTRL); |
2305 | outb(0x88, io + SHADOW_MIX_REG_VOICE); | |
2306 | outb(0x88, io + HW_VOL_COUNTER_VOICE); | |
2307 | outb(0x88, io + SHADOW_MIX_REG_MASTER); | |
2308 | outb(0x88, io + HW_VOL_COUNTER_MASTER); | |
2309 | ||
1da177e4 LT |
2310 | return 0; |
2311 | } | |
2312 | ||
2313 | static void | |
3470c29d | 2314 | snd_m3_enable_ints(struct snd_m3 *chip) |
1da177e4 LT |
2315 | { |
2316 | unsigned long io = chip->iobase; | |
5ba1e7b5 | 2317 | unsigned short val; |
1da177e4 LT |
2318 | |
2319 | /* TODO: MPU401 not supported yet */ | |
5ba1e7b5 | 2320 | val = ASSP_INT_ENABLE /*| MPU401_INT_ENABLE*/; |
1061eeb4 | 2321 | if (chip->hv_config & HV_CTRL_ENABLE) |
5ba1e7b5 | 2322 | val |= HV_INT_ENABLE; |
1bde78bc | 2323 | outb(val, chip->iobase + HOST_INT_STATUS); |
5ba1e7b5 | 2324 | outw(val, io + HOST_INT_CTRL); |
1da177e4 LT |
2325 | outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE, |
2326 | io + ASSP_CONTROL_C); | |
2327 | } | |
2328 | ||
2329 | ||
2330 | /* | |
2331 | */ | |
2332 | ||
5c093925 | 2333 | static void snd_m3_free(struct snd_card *card) |
1da177e4 | 2334 | { |
5c093925 | 2335 | struct snd_m3 *chip = card->private_data; |
3470c29d | 2336 | struct m3_dma *s; |
1da177e4 LT |
2337 | int i; |
2338 | ||
30bdee02 | 2339 | cancel_work_sync(&chip->hwvol_work); |
eb581adf | 2340 | |
1da177e4 LT |
2341 | if (chip->substreams) { |
2342 | spin_lock_irq(&chip->reg_lock); | |
2343 | for (i = 0; i < chip->num_substreams; i++) { | |
2344 | s = &chip->substreams[i]; | |
2345 | /* check surviving pcms; this should not happen though.. */ | |
2346 | if (s->substream && s->running) | |
2347 | snd_m3_pcm_stop(chip, s, s->substream); | |
2348 | } | |
2349 | spin_unlock_irq(&chip->reg_lock); | |
1da177e4 LT |
2350 | } |
2351 | if (chip->iobase) { | |
88491386 | 2352 | outw(0, chip->iobase + HOST_INT_CTRL); /* disable ints */ |
1da177e4 LT |
2353 | } |
2354 | ||
1da177e4 | 2355 | vfree(chip->suspend_mem); |
b7dd2b34 TI |
2356 | release_firmware(chip->assp_kernel_image); |
2357 | release_firmware(chip->assp_minisrc_image); | |
1da177e4 LT |
2358 | } |
2359 | ||
2360 | ||
2361 | /* | |
2362 | * APM support | |
2363 | */ | |
68cb2b55 | 2364 | static int m3_suspend(struct device *dev) |
1da177e4 | 2365 | { |
68cb2b55 | 2366 | struct snd_card *card = dev_get_drvdata(dev); |
0e2364a7 | 2367 | struct snd_m3 *chip = card->private_data; |
e37273d3 | 2368 | int i, dsp_index; |
1da177e4 LT |
2369 | |
2370 | if (chip->suspend_mem == NULL) | |
2371 | return 0; | |
2372 | ||
715aa675 | 2373 | chip->in_suspend = 1; |
30bdee02 | 2374 | cancel_work_sync(&chip->hwvol_work); |
0e2364a7 | 2375 | snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); |
1da177e4 LT |
2376 | snd_ac97_suspend(chip->ac97); |
2377 | ||
5ba1e7b5 | 2378 | msleep(10); /* give the assp a chance to idle.. */ |
1da177e4 LT |
2379 | |
2380 | snd_m3_assp_halt(chip); | |
2381 | ||
2382 | /* save dsp image */ | |
e37273d3 | 2383 | dsp_index = 0; |
1da177e4 | 2384 | for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++) |
e37273d3 | 2385 | chip->suspend_mem[dsp_index++] = |
1da177e4 LT |
2386 | snd_m3_assp_read(chip, MEMTYPE_INTERNAL_CODE, i); |
2387 | for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++) | |
e37273d3 | 2388 | chip->suspend_mem[dsp_index++] = |
1da177e4 | 2389 | snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, i); |
1da177e4 LT |
2390 | return 0; |
2391 | } | |
2392 | ||
68cb2b55 | 2393 | static int m3_resume(struct device *dev) |
1da177e4 | 2394 | { |
68cb2b55 | 2395 | struct snd_card *card = dev_get_drvdata(dev); |
0e2364a7 | 2396 | struct snd_m3 *chip = card->private_data; |
e37273d3 | 2397 | int i, dsp_index; |
1da177e4 LT |
2398 | |
2399 | if (chip->suspend_mem == NULL) | |
2400 | return 0; | |
2401 | ||
1da177e4 LT |
2402 | /* first lets just bring everything back. .*/ |
2403 | snd_m3_outw(chip, 0, 0x54); | |
2404 | snd_m3_outw(chip, 0, 0x56); | |
2405 | ||
2406 | snd_m3_chip_init(chip); | |
2407 | snd_m3_assp_halt(chip); | |
2408 | snd_m3_ac97_reset(chip); | |
2409 | ||
2410 | /* restore dsp image */ | |
e37273d3 | 2411 | dsp_index = 0; |
1da177e4 LT |
2412 | for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++) |
2413 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, i, | |
e37273d3 | 2414 | chip->suspend_mem[dsp_index++]); |
1da177e4 LT |
2415 | for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++) |
2416 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, i, | |
e37273d3 | 2417 | chip->suspend_mem[dsp_index++]); |
1da177e4 LT |
2418 | |
2419 | /* tell the dma engine to restart itself */ | |
2420 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, | |
2421 | KDATA_DMA_ACTIVE, 0); | |
2422 | ||
2423 | /* restore ac97 registers */ | |
2424 | snd_ac97_resume(chip->ac97); | |
2425 | ||
2426 | snd_m3_assp_continue(chip); | |
2427 | snd_m3_enable_ints(chip); | |
2428 | snd_m3_amp_enable(chip, 1); | |
2429 | ||
8b83afe0 VS |
2430 | snd_m3_hv_init(chip); |
2431 | ||
0e2364a7 | 2432 | snd_power_change_state(card, SNDRV_CTL_POWER_D0); |
715aa675 | 2433 | chip->in_suspend = 0; |
1da177e4 LT |
2434 | return 0; |
2435 | } | |
68cb2b55 | 2436 | |
a2280df4 | 2437 | static DEFINE_SIMPLE_DEV_PM_OPS(m3_pm, m3_suspend, m3_resume); |
1da177e4 | 2438 | |
eb581adf | 2439 | #ifdef CONFIG_SND_MAESTRO3_INPUT |
e23e7a14 | 2440 | static int snd_m3_input_register(struct snd_m3 *chip) |
eb581adf HG |
2441 | { |
2442 | struct input_dev *input_dev; | |
2443 | int err; | |
2444 | ||
5c093925 | 2445 | input_dev = devm_input_allocate_device(&chip->pci->dev); |
eb581adf HG |
2446 | if (!input_dev) |
2447 | return -ENOMEM; | |
2448 | ||
2449 | snprintf(chip->phys, sizeof(chip->phys), "pci-%s/input0", | |
2450 | pci_name(chip->pci)); | |
2451 | ||
2452 | input_dev->name = chip->card->driver; | |
2453 | input_dev->phys = chip->phys; | |
2454 | input_dev->id.bustype = BUS_PCI; | |
2455 | input_dev->id.vendor = chip->pci->vendor; | |
2456 | input_dev->id.product = chip->pci->device; | |
2457 | input_dev->dev.parent = &chip->pci->dev; | |
2458 | ||
2459 | __set_bit(EV_KEY, input_dev->evbit); | |
2460 | __set_bit(KEY_MUTE, input_dev->keybit); | |
2461 | __set_bit(KEY_VOLUMEDOWN, input_dev->keybit); | |
2462 | __set_bit(KEY_VOLUMEUP, input_dev->keybit); | |
2463 | ||
2464 | err = input_register_device(input_dev); | |
5c093925 | 2465 | if (err) |
eb581adf | 2466 | return err; |
eb581adf HG |
2467 | |
2468 | chip->input_dev = input_dev; | |
2469 | return 0; | |
2470 | } | |
2471 | #endif /* CONFIG_INPUT */ | |
1da177e4 LT |
2472 | |
2473 | /* | |
2474 | */ | |
2475 | ||
e23e7a14 | 2476 | static int |
3470c29d | 2477 | snd_m3_create(struct snd_card *card, struct pci_dev *pci, |
1da177e4 | 2478 | int enable_amp, |
5c093925 | 2479 | int amp_gpio) |
1da177e4 | 2480 | { |
5c093925 | 2481 | struct snd_m3 *chip = card->private_data; |
1da177e4 | 2482 | int i, err; |
1061eeb4 | 2483 | const struct snd_pci_quirk *quirk; |
1da177e4 | 2484 | |
5c093925 | 2485 | if (pcim_enable_device(pci)) |
1da177e4 LT |
2486 | return -EIO; |
2487 | ||
2488 | /* check, if we can restrict PCI DMA transfers to 28 bits */ | |
669f65ea | 2489 | if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(28))) { |
747ce5b3 TI |
2490 | dev_err(card->dev, |
2491 | "architecture does not support 28bit PCI busmaster DMA\n"); | |
1da177e4 LT |
2492 | return -ENXIO; |
2493 | } | |
2494 | ||
1da177e4 | 2495 | spin_lock_init(&chip->reg_lock); |
5ba1e7b5 | 2496 | |
1da177e4 LT |
2497 | switch (pci->device) { |
2498 | case PCI_DEVICE_ID_ESS_ALLEGRO: | |
2499 | case PCI_DEVICE_ID_ESS_ALLEGRO_1: | |
2500 | case PCI_DEVICE_ID_ESS_CANYON3D_2LE: | |
2501 | case PCI_DEVICE_ID_ESS_CANYON3D_2: | |
2502 | chip->allegro_flag = 1; | |
2503 | break; | |
2504 | } | |
2505 | ||
2506 | chip->card = card; | |
2507 | chip->pci = pci; | |
2508 | chip->irq = -1; | |
30bdee02 | 2509 | INIT_WORK(&chip->hwvol_work, snd_m3_update_hw_volume); |
5c093925 | 2510 | card->private_free = snd_m3_free; |
1da177e4 | 2511 | |
1da177e4 LT |
2512 | chip->external_amp = enable_amp; |
2513 | if (amp_gpio >= 0 && amp_gpio <= 0x0f) | |
2514 | chip->amp_gpio = amp_gpio; | |
1061eeb4 TI |
2515 | else { |
2516 | quirk = snd_pci_quirk_lookup(pci, m3_amp_quirk_list); | |
2517 | if (quirk) { | |
747ce5b3 TI |
2518 | dev_info(card->dev, "set amp-gpio for '%s'\n", |
2519 | snd_pci_quirk_name(quirk)); | |
1061eeb4 TI |
2520 | chip->amp_gpio = quirk->value; |
2521 | } else if (chip->allegro_flag) | |
2522 | chip->amp_gpio = GPO_EXT_AMP_ALLEGRO; | |
2523 | else /* presumably this is for all 'maestro3's.. */ | |
2524 | chip->amp_gpio = GPO_EXT_AMP_M3; | |
2525 | } | |
2526 | ||
2527 | quirk = snd_pci_quirk_lookup(pci, m3_irda_quirk_list); | |
2528 | if (quirk) { | |
747ce5b3 TI |
2529 | dev_info(card->dev, "enabled irda workaround for '%s'\n", |
2530 | snd_pci_quirk_name(quirk)); | |
1061eeb4 TI |
2531 | chip->irda_workaround = 1; |
2532 | } | |
2533 | quirk = snd_pci_quirk_lookup(pci, m3_hv_quirk_list); | |
2534 | if (quirk) | |
2535 | chip->hv_config = quirk->value; | |
2536 | if (snd_pci_quirk_lookup(pci, m3_omnibook_quirk_list)) | |
2537 | chip->is_omnibook = 1; | |
1da177e4 LT |
2538 | |
2539 | chip->num_substreams = NR_DSPS; | |
5c093925 TI |
2540 | chip->substreams = devm_kcalloc(&pci->dev, chip->num_substreams, |
2541 | sizeof(struct m3_dma), GFP_KERNEL); | |
2542 | if (!chip->substreams) | |
1da177e4 | 2543 | return -ENOMEM; |
1da177e4 | 2544 | |
81d7724a CL |
2545 | err = request_firmware(&chip->assp_kernel_image, |
2546 | "ess/maestro3_assp_kernel.fw", &pci->dev); | |
468778a0 | 2547 | if (err < 0) |
5c093925 | 2548 | return err; |
81d7724a CL |
2549 | |
2550 | err = request_firmware(&chip->assp_minisrc_image, | |
2551 | "ess/maestro3_assp_minisrc.fw", &pci->dev); | |
468778a0 | 2552 | if (err < 0) |
5c093925 | 2553 | return err; |
468778a0 ME |
2554 | |
2555 | err = pci_request_regions(pci, card->driver); | |
2556 | if (err < 0) | |
5c093925 | 2557 | return err; |
81d7724a | 2558 | |
1da177e4 LT |
2559 | chip->iobase = pci_resource_start(pci, 0); |
2560 | ||
2561 | /* just to be sure */ | |
2562 | pci_set_master(pci); | |
2563 | ||
2564 | snd_m3_chip_init(chip); | |
2565 | snd_m3_assp_halt(chip); | |
2566 | ||
2567 | snd_m3_ac97_reset(chip); | |
2568 | ||
1da177e4 LT |
2569 | snd_m3_amp_enable(chip, 1); |
2570 | ||
8b83afe0 VS |
2571 | snd_m3_hv_init(chip); |
2572 | ||
5c093925 TI |
2573 | if (devm_request_irq(&pci->dev, pci->irq, snd_m3_interrupt, IRQF_SHARED, |
2574 | KBUILD_MODNAME, chip)) { | |
747ce5b3 | 2575 | dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq); |
5c093925 | 2576 | return -ENOMEM; |
1da177e4 LT |
2577 | } |
2578 | chip->irq = pci->irq; | |
a20b8bfe | 2579 | card->sync_irq = chip->irq; |
1da177e4 | 2580 | |
a2280df4 TI |
2581 | if (IS_ENABLED(CONFIG_PM_SLEEP)) { |
2582 | chip->suspend_mem = | |
2583 | vmalloc(array_size(sizeof(u16), | |
2584 | REV_B_CODE_MEMORY_LENGTH + | |
2585 | REV_B_DATA_MEMORY_LENGTH)); | |
2586 | if (!chip->suspend_mem) | |
2587 | dev_warn(card->dev, "can't allocate apm buffer\n"); | |
2588 | } | |
1da177e4 | 2589 | |
5cc16ba6 TI |
2590 | err = snd_m3_mixer(chip); |
2591 | if (err < 0) | |
1da177e4 LT |
2592 | return err; |
2593 | ||
2594 | for (i = 0; i < chip->num_substreams; i++) { | |
3470c29d | 2595 | struct m3_dma *s = &chip->substreams[i]; |
5cc16ba6 TI |
2596 | err = snd_m3_assp_client_init(chip, s, i); |
2597 | if (err < 0) | |
1da177e4 LT |
2598 | return err; |
2599 | } | |
2600 | ||
5cc16ba6 TI |
2601 | err = snd_m3_pcm(chip, 0); |
2602 | if (err < 0) | |
1da177e4 | 2603 | return err; |
eb581adf HG |
2604 | |
2605 | #ifdef CONFIG_SND_MAESTRO3_INPUT | |
2606 | if (chip->hv_config & HV_CTRL_ENABLE) { | |
2607 | err = snd_m3_input_register(chip); | |
2608 | if (err) | |
747ce5b3 TI |
2609 | dev_warn(card->dev, |
2610 | "Input device registration failed with error %i", | |
2611 | err); | |
eb581adf HG |
2612 | } |
2613 | #endif | |
2614 | ||
1da177e4 LT |
2615 | snd_m3_enable_ints(chip); |
2616 | snd_m3_assp_continue(chip); | |
2617 | ||
1da177e4 LT |
2618 | return 0; |
2619 | } | |
2620 | ||
2621 | /* | |
2622 | */ | |
e23e7a14 | 2623 | static int |
ae86bf5c | 2624 | __snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) |
1da177e4 LT |
2625 | { |
2626 | static int dev; | |
3470c29d TI |
2627 | struct snd_card *card; |
2628 | struct snd_m3 *chip; | |
1da177e4 LT |
2629 | int err; |
2630 | ||
2631 | /* don't pick up modems */ | |
2632 | if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO) | |
2633 | return -ENODEV; | |
2634 | ||
2635 | if (dev >= SNDRV_CARDS) | |
2636 | return -ENODEV; | |
2637 | if (!enable[dev]) { | |
2638 | dev++; | |
2639 | return -ENOENT; | |
2640 | } | |
2641 | ||
5c093925 TI |
2642 | err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, |
2643 | sizeof(*chip), &card); | |
e58de7ba TI |
2644 | if (err < 0) |
2645 | return err; | |
5c093925 | 2646 | chip = card->private_data; |
1da177e4 LT |
2647 | |
2648 | switch (pci->device) { | |
2649 | case PCI_DEVICE_ID_ESS_ALLEGRO: | |
2650 | case PCI_DEVICE_ID_ESS_ALLEGRO_1: | |
2651 | strcpy(card->driver, "Allegro"); | |
2652 | break; | |
2653 | case PCI_DEVICE_ID_ESS_CANYON3D_2LE: | |
2654 | case PCI_DEVICE_ID_ESS_CANYON3D_2: | |
2655 | strcpy(card->driver, "Canyon3D-2"); | |
2656 | break; | |
2657 | default: | |
2658 | strcpy(card->driver, "Maestro3"); | |
2659 | break; | |
2660 | } | |
2661 | ||
5c093925 | 2662 | err = snd_m3_create(card, pci, external_amp[dev], amp_gpio[dev]); |
468778a0 | 2663 | if (err < 0) |
5c093925 | 2664 | return err; |
1da177e4 LT |
2665 | |
2666 | sprintf(card->shortname, "ESS %s PCI", card->driver); | |
2667 | sprintf(card->longname, "%s at 0x%lx, irq %d", | |
2668 | card->shortname, chip->iobase, chip->irq); | |
2669 | ||
468778a0 ME |
2670 | err = snd_card_register(card); |
2671 | if (err < 0) | |
5c093925 | 2672 | return err; |
1da177e4 LT |
2673 | |
2674 | #if 0 /* TODO: not supported yet */ | |
0b2dcd5d | 2675 | /* TODO enable MIDI IRQ and I/O */ |
1da177e4 | 2676 | err = snd_mpu401_uart_new(chip->card, 0, MPU401_HW_MPU401, |
302e4c2f | 2677 | chip->iobase + MPU401_DATA_PORT, |
dba8b469 CL |
2678 | MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK, |
2679 | -1, &chip->rmidi); | |
1da177e4 | 2680 | if (err < 0) |
747ce5b3 | 2681 | dev_warn(card->dev, "no MIDI support.\n"); |
1da177e4 LT |
2682 | #endif |
2683 | ||
2684 | pci_set_drvdata(pci, card); | |
2685 | dev++; | |
2686 | return 0; | |
1da177e4 LT |
2687 | } |
2688 | ||
ae86bf5c TI |
2689 | static int |
2690 | snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) | |
2691 | { | |
2692 | return snd_card_free_on_error(&pci->dev, __snd_m3_probe(pci, pci_id)); | |
2693 | } | |
2694 | ||
e9f66d9b | 2695 | static struct pci_driver m3_driver = { |
3733e424 | 2696 | .name = KBUILD_MODNAME, |
1da177e4 LT |
2697 | .id_table = snd_m3_ids, |
2698 | .probe = snd_m3_probe, | |
68cb2b55 | 2699 | .driver = { |
a2280df4 | 2700 | .pm = &m3_pm, |
68cb2b55 | 2701 | }, |
1da177e4 LT |
2702 | }; |
2703 | ||
e9f66d9b | 2704 | module_pci_driver(m3_driver); |