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[ALSA] Add PCXHR driver
[linux-2.6-block.git] / sound / pci / intel8x0.c
CommitLineData
1da177e4
LT		 1/*
2 * ALSA driver for Intel ICH (i8x0) chipsets
3 *
4 * Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
5 *
6 *
7 * This code also contains alpha support for SiS 735 chipsets provided
8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
9 * for SiS735, so the code is not fully functional.
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25
26 *
27 */
28
29#include <sound/driver.h>
30#include <asm/io.h>
31#include <linux/delay.h>
32#include <linux/interrupt.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/slab.h>
36#include <linux/moduleparam.h>
37#include <sound/core.h>
38#include <sound/pcm.h>
39#include <sound/ac97_codec.h>
40#include <sound/info.h>
41#include <sound/initval.h>
42/* for 440MX workaround */
43#include <asm/pgtable.h>
44#include <asm/cacheflush.h>
45
46MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
47MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
48MODULE_LICENSE("GPL");
49MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
50 "{Intel,82901AB-ICH0},"
51 "{Intel,82801BA-ICH2},"
52 "{Intel,82801CA-ICH3},"
53 "{Intel,82801DB-ICH4},"
54 "{Intel,ICH5},"
55 "{Intel,ICH6},"
56 "{Intel,ICH7},"
57 "{Intel,6300ESB},"
c4c8ea94 58 "{Intel,ESB2},"
1da177e4
LT		 59 "{Intel,MX440},"
60 "{SiS,SI7012},"
61 "{NVidia,nForce Audio},"
62 "{NVidia,nForce2 Audio},"
63 "{AMD,AMD768},"
64 "{AMD,AMD8111},"
65 "{ALI,M5455}}");
66
b7fe4622
CL		 67static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
68static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
69static int ac97_clock = 0;
70static char *ac97_quirk;
71static int buggy_semaphore;
beef08a5 72static int buggy_irq = -1; /* auto-check */
b7fe4622
CL		 73static int xbox;
74
75module_param(index, int, 0444);
1da177e4 76MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
b7fe4622 77module_param(id, charp, 0444);
1da177e4 78MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
b7fe4622 79module_param(ac97_clock, int, 0444);
1da177e4 80MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
b7fe4622 81module_param(ac97_quirk, charp, 0444);
1da177e4 82MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
b7fe4622 83module_param(buggy_semaphore, bool, 0444);
a06147d2 84MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
b7fe4622 85module_param(buggy_irq, bool, 0444);
1da177e4 86MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
b7fe4622 87module_param(xbox, bool, 0444);
1da177e4
LT		 88MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
89
2b3e584b
TI		 90/* just for backward compatibility */
91static int enable;
698444f3 92module_param(enable, bool, 0444);
2b3e584b
TI		 93static int joystick;
94module_param(joystick, int, 0444);
95
1da177e4
LT		 96/*
97 * Direct registers
98 */
1da177e4
LT		 99enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
100
101#define ICHREG(x) ICH_REG_##x
102
103#define DEFINE_REGSET(name,base) \
104enum { \
105 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
106 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
107 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
108 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
109 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
110 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
111 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
112};
113
114/* busmaster blocks */
115DEFINE_REGSET(OFF, 0); /* offset */
116DEFINE_REGSET(PI, 0x00); /* PCM in */
117DEFINE_REGSET(PO, 0x10); /* PCM out */
118DEFINE_REGSET(MC, 0x20); /* Mic in */
119
120/* ICH4 busmaster blocks */
121DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */
122DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */
123DEFINE_REGSET(SP, 0x60); /* SPDIF out */
124
125/* values for each busmaster block */
126
127/* LVI */
128#define ICH_REG_LVI_MASK 0x1f
129
130/* SR */
131#define ICH_FIFOE 0x10 /* FIFO error */
132#define ICH_BCIS 0x08 /* buffer completion interrupt status */
133#define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
134#define ICH_CELV 0x02 /* current equals last valid */
135#define ICH_DCH 0x01 /* DMA controller halted */
136
137/* PIV */
138#define ICH_REG_PIV_MASK 0x1f /* mask */
139
140/* CR */
141#define ICH_IOCE 0x10 /* interrupt on completion enable */
142#define ICH_FEIE 0x08 /* fifo error interrupt enable */
143#define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
144#define ICH_RESETREGS 0x02 /* reset busmaster registers */
145#define ICH_STARTBM 0x01 /* start busmaster operation */
146
147
148/* global block */
149#define ICH_REG_GLOB_CNT 0x2c /* dword - global control */
150#define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */
151#define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */
152#define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */
153#define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */
154#define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */
155#define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */
156#define ICH_PCM_246_MASK 0x00300000 /* 6 channels (not all chips) */
157#define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */
158#define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */
159#define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */
160#define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */
161#define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */
162#define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */
163#define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */
164#define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
165#define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
166#define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
167#define ICH_ACLINK 0x00000008 /* AClink shut off */
168#define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
169#define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
170#define ICH_GIE 0x00000001 /* GPI interrupt enable */
171#define ICH_REG_GLOB_STA 0x30 /* dword - global status */
172#define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
173#define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
174#define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
175#define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
176#define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
177#define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
178#define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
179#define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */
180#define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
181#define ICH_MD3 0x00020000 /* modem power down semaphore */
182#define ICH_AD3 0x00010000 /* audio power down semaphore */
183#define ICH_RCS 0x00008000 /* read completion status */
184#define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
185#define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
186#define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
187#define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
188#define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
189#define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
190#define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
191#define ICH_MCINT 0x00000080 /* MIC capture interrupt */
192#define ICH_POINT 0x00000040 /* playback interrupt */
193#define ICH_PIINT 0x00000020 /* capture interrupt */
194#define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
195#define ICH_MOINT 0x00000004 /* modem playback interrupt */
196#define ICH_MIINT 0x00000002 /* modem capture interrupt */
197#define ICH_GSCI 0x00000001 /* GPI status change interrupt */
198#define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */
199#define ICH_CAS 0x01 /* codec access semaphore */
200#define ICH_REG_SDM 0x80
201#define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */
202#define ICH_DI2L_SHIFT 6
203#define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */
204#define ICH_DI1L_SHIFT 4
205#define ICH_SE 0x00000008 /* steer enable */
206#define ICH_LDI_MASK 0x00000003 /* last codec read data input */
207
208#define ICH_MAX_FRAGS 32 /* max hw frags */
209
210
211/*
212 * registers for Ali5455
213 */
214
215/* ALi 5455 busmaster blocks */
216DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */
217DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */
218DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */
219DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */
220DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */
221DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */
222DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */
223DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */
224DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */
225DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */
226DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */
227
228enum {
229 ICH_REG_ALI_SCR = 0x00, /* System Control Register */
230 ICH_REG_ALI_SSR = 0x04, /* System Status Register */
231 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */
232 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */
233 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
234 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
235 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */
236 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */
237 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */
238 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */
239 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */
240 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */
241 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */
242 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */
243 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */
244 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */
245 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */
246 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */
247 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */
248 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */
249 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */
250};
251
252#define ALI_CAS_SEM_BUSY 0x80000000
253#define ALI_CPR_ADDR_SECONDARY 0x100
254#define ALI_CPR_ADDR_READ 0x80
255#define ALI_CSPSR_CODEC_READY 0x08
256#define ALI_CSPSR_READ_OK 0x02
257#define ALI_CSPSR_WRITE_OK 0x01
258
259/* interrupts for the whole chip by interrupt status register finish */
260
261#define ALI_INT_MICIN2 (1<<26)
262#define ALI_INT_PCMIN2 (1<<25)
263#define ALI_INT_I2SIN (1<<24)
264#define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */
265#define ALI_INT_SPDIFIN (1<<22)
266#define ALI_INT_LFEOUT (1<<21)
267#define ALI_INT_CENTEROUT (1<<20)
268#define ALI_INT_CODECSPDIFOUT (1<<19)
269#define ALI_INT_MICIN (1<<18)
270#define ALI_INT_PCMOUT (1<<17)
271#define ALI_INT_PCMIN (1<<16)
272#define ALI_INT_CPRAIS (1<<7) /* command port available */
273#define ALI_INT_SPRAIS (1<<5) /* status port available */
274#define ALI_INT_GPIO (1<<1)
6b75a9d8
TI		 275#define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\
276 ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
1da177e4
LT		 277
278#define ICH_ALI_SC_RESET (1<<31) /* master reset */
279#define ICH_ALI_SC_AC97_DBL (1<<30)
280#define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
281#define ICH_ALI_SC_IN_BITS (3<<18)
282#define ICH_ALI_SC_OUT_BITS (3<<16)
283#define ICH_ALI_SC_6CH_CFG (3<<14)
284#define ICH_ALI_SC_PCM_4 (1<<8)
285#define ICH_ALI_SC_PCM_6 (2<<8)
286#define ICH_ALI_SC_PCM_246_MASK (3<<8)
287
288#define ICH_ALI_SS_SEC_ID (3<<5)
289#define ICH_ALI_SS_PRI_ID (3<<3)
290
291#define ICH_ALI_IF_AC97SP (1<<21)
292#define ICH_ALI_IF_MC (1<<20)
293#define ICH_ALI_IF_PI (1<<19)
294#define ICH_ALI_IF_MC2 (1<<18)
295#define ICH_ALI_IF_PI2 (1<<17)
296#define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */
297#define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */
298#define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
299#define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */
300#define ICH_ALI_IF_PO_SPDF (1<<3)
301#define ICH_ALI_IF_PO (1<<1)
302
303/*
304 *
305 */
306
6b75a9d8
TI		 307enum {
308 ICHD_PCMIN,
309 ICHD_PCMOUT,
310 ICHD_MIC,
311 ICHD_MIC2,
312 ICHD_PCM2IN,
313 ICHD_SPBAR,
314 ICHD_LAST = ICHD_SPBAR
315};
316enum {
317 NVD_PCMIN,
318 NVD_PCMOUT,
319 NVD_MIC,
320 NVD_SPBAR,
321 NVD_LAST = NVD_SPBAR
322};
323enum {
324 ALID_PCMIN,
325 ALID_PCMOUT,
326 ALID_MIC,
327 ALID_AC97SPDIFOUT,
328 ALID_SPDIFIN,
329 ALID_SPDIFOUT,
330 ALID_LAST = ALID_SPDIFOUT
331};
1da177e4 332
6b75a9d8 333#define get_ichdev(substream) (substream->runtime->private_data)
1da177e4 334
6b75a9d8 335struct ichdev {
1da177e4
LT		 336 unsigned int ichd; /* ich device number */
337 unsigned long reg_offset; /* offset to bmaddr */
338 u32 *bdbar; /* CPU address (32bit) */
339 unsigned int bdbar_addr; /* PCI bus address (32bit) */
6b75a9d8 340 struct snd_pcm_substream *substream;
1da177e4
LT		 341 unsigned int physbuf; /* physical address (32bit) */
342 unsigned int size;
343 unsigned int fragsize;
344 unsigned int fragsize1;
345 unsigned int position;
346 unsigned int pos_shift;
347 int frags;
348 int lvi;
349 int lvi_frag;
350 int civ;
351 int ack;
352 int ack_reload;
353 unsigned int ack_bit;
354 unsigned int roff_sr;
355 unsigned int roff_picb;
356 unsigned int int_sta_mask; /* interrupt status mask */
357 unsigned int ali_slot; /* ALI DMA slot */
358 struct ac97_pcm *pcm;
359 int pcm_open_flag;
360 unsigned int page_attr_changed: 1;
1cfe43d2 361 unsigned int suspended: 1;
6b75a9d8 362};
1da177e4 363
6b75a9d8 364struct intel8x0 {
1da177e4
LT		 365 unsigned int device_type;
366
367 int irq;
368
369 unsigned int mmio;
370 unsigned long addr;
371 void __iomem *remap_addr;
372 unsigned int bm_mmio;
373 unsigned long bmaddr;
374 void __iomem *remap_bmaddr;
375
376 struct pci_dev *pci;
6b75a9d8 377 struct snd_card *card;
1da177e4
LT		 378
379 int pcm_devs;
6b75a9d8
TI		 380 struct snd_pcm *pcm[6];
381 struct ichdev ichd[6];
1da177e4
LT		 382
383 unsigned multi4: 1,
384 multi6: 1,
385 dra: 1,
386 smp20bit: 1;
387 unsigned in_ac97_init: 1,
388 in_sdin_init: 1;
389 unsigned in_measurement: 1; /* during ac97 clock measurement */
390 unsigned fix_nocache: 1; /* workaround for 440MX */
391 unsigned buggy_irq: 1; /* workaround for buggy mobos */
392 unsigned xbox: 1; /* workaround for Xbox AC'97 detection */
a06147d2 393 unsigned buggy_semaphore: 1; /* workaround for buggy codec semaphore */
1da177e4
LT		 394
395 int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
52b72388 396 unsigned int sdm_saved; /* SDM reg value */
1da177e4 397
6b75a9d8
TI		 398 struct snd_ac97_bus *ac97_bus;
399 struct snd_ac97 *ac97[3];
1da177e4
LT		 400 unsigned int ac97_sdin[3];
401
402 spinlock_t reg_lock;
403
404 u32 bdbars_count;
405 struct snd_dma_buffer bdbars;
406 u32 int_sta_reg; /* interrupt status register */
407 u32 int_sta_mask; /* interrupt status mask */
408};
409
410static struct pci_device_id snd_intel8x0_ids[] = {
411 { 0x8086, 0x2415, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
412 { 0x8086, 0x2425, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
413 { 0x8086, 0x2445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
414 { 0x8086, 0x2485, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
415 { 0x8086, 0x24c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH4 */
416 { 0x8086, 0x24d5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH5 */
417 { 0x8086, 0x25a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB */
418 { 0x8086, 0x266e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH6 */
419 { 0x8086, 0x27de, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH7 */
c4c8ea94 420 { 0x8086, 0x2698, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB2 */
1da177e4
LT		 421 { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
422 { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS }, /* SI7012 */
423 { 0x10de, 0x01b1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE */
424 { 0x10de, 0x003a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* MCP04 */
425 { 0x10de, 0x006a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2 */
426 { 0x10de, 0x0059, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK804 */
427 { 0x10de, 0x008a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8 */
428 { 0x10de, 0x00da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE3 */
429 { 0x10de, 0x00ea, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8S */
430 { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
431 { 0x1022, 0x7445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
432 { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI }, /* Ali5455 */
433 { 0, }
434};
435
436MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
437
438/*
439 * Lowlevel I/O - busmaster
440 */
441
6b75a9d8 442static u8 igetbyte(struct intel8x0 *chip, u32 offset)
1da177e4
LT		 443{
444 if (chip->bm_mmio)
445 return readb(chip->remap_bmaddr + offset);
446 else
447 return inb(chip->bmaddr + offset);
448}
449
6b75a9d8 450static u16 igetword(struct intel8x0 *chip, u32 offset)
1da177e4
LT		 451{
452 if (chip->bm_mmio)
453 return readw(chip->remap_bmaddr + offset);
454 else
455 return inw(chip->bmaddr + offset);
456}
457
6b75a9d8 458static u32 igetdword(struct intel8x0 *chip, u32 offset)
1da177e4
LT		 459{
460 if (chip->bm_mmio)
461 return readl(chip->remap_bmaddr + offset);
462 else
463 return inl(chip->bmaddr + offset);
464}
465
6b75a9d8 466static void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
1da177e4
LT		 467{
468 if (chip->bm_mmio)
469 writeb(val, chip->remap_bmaddr + offset);
470 else
471 outb(val, chip->bmaddr + offset);
472}
473
6b75a9d8 474static void iputword(struct intel8x0 *chip, u32 offset, u16 val)
1da177e4
LT		 475{
476 if (chip->bm_mmio)
477 writew(val, chip->remap_bmaddr + offset);
478 else
479 outw(val, chip->bmaddr + offset);
480}
481
6b75a9d8 482static void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
1da177e4
LT		 483{
484 if (chip->bm_mmio)
485 writel(val, chip->remap_bmaddr + offset);
486 else
487 outl(val, chip->bmaddr + offset);
488}
489
490/*
491 * Lowlevel I/O - AC'97 registers
492 */
493
6b75a9d8 494static u16 iagetword(struct intel8x0 *chip, u32 offset)
1da177e4
LT		 495{
496 if (chip->mmio)
497 return readw(chip->remap_addr + offset);
498 else
499 return inw(chip->addr + offset);
500}
501
6b75a9d8 502static void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
1da177e4
LT		 503{
504 if (chip->mmio)
505 writew(val, chip->remap_addr + offset);
506 else
507 outw(val, chip->addr + offset);
508}
509
510/*
511 * Basic I/O
512 */
513
514/*
515 * access to AC97 codec via normal i/o (for ICH and SIS7012)
516 */
517
518/* return the GLOB_STA bit for the corresponding codec */
6b75a9d8 519static unsigned int get_ich_codec_bit(struct intel8x0 *chip, unsigned int codec)
1da177e4
LT		 520{
521 static unsigned int codec_bit[3] = {
522 ICH_PCR, ICH_SCR, ICH_TCR
523 };
524 snd_assert(codec < 3, return ICH_PCR);
525 if (chip->device_type == DEVICE_INTEL_ICH4)
526 codec = chip->ac97_sdin[codec];
527 return codec_bit[codec];
528}
529
6b75a9d8 530static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
1da177e4
LT		 531{
532 int time;
533
534 if (codec > 2)
535 return -EIO;
536 if (chip->in_sdin_init) {
537 /* we don't know the ready bit assignment at the moment */
538 /* so we check any */
539 codec = ICH_PCR | ICH_SCR | ICH_TCR;
540 } else {
541 codec = get_ich_codec_bit(chip, codec);
542 }
543
544 /* codec ready ? */
545 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
546 return -EIO;
547
a06147d2
TI		 548 if (chip->buggy_semaphore)
549 return 0; /* just ignore ... */
550
1da177e4
LT		 551 /* Anyone holding a semaphore for 1 msec should be shot... */
552 time = 100;
553 do {
554 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
555 return 0;
556 udelay(10);
557 } while (time--);
558
559 /* access to some forbidden (non existant) ac97 registers will not
560 * reset the semaphore. So even if you don't get the semaphore, still
561 * continue the access. We don't need the semaphore anyway. */
99b359ba 562 snd_printk(KERN_ERR "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
1da177e4
LT		 563 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
564 iagetword(chip, 0); /* clear semaphore flag */
565 /* I don't care about the semaphore */
566 return -EBUSY;
567}
568
6b75a9d8 569static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
1da177e4
LT		 570 unsigned short reg,
571 unsigned short val)
572{
6b75a9d8 573 struct intel8x0 *chip = ac97->private_data;
1da177e4
LT		 574
575 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
576 if (! chip->in_ac97_init)
99b359ba 577 snd_printk(KERN_ERR "codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
1da177e4
LT		 578 }
579 iaputword(chip, reg + ac97->num * 0x80, val);
580}
581
6b75a9d8 582static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
1da177e4
LT		 583 unsigned short reg)
584{
6b75a9d8 585 struct intel8x0 *chip = ac97->private_data;
1da177e4
LT		 586 unsigned short res;
587 unsigned int tmp;
588
589 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
590 if (! chip->in_ac97_init)
99b359ba 591 snd_printk(KERN_ERR "codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
1da177e4
LT		 592 res = 0xffff;
593 } else {
594 res = iagetword(chip, reg + ac97->num * 0x80);
595 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
596 /* reset RCS and preserve other R/WC bits */
6b75a9d8
TI		 597 iputdword(chip, ICHREG(GLOB_STA), tmp &
598 ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
1da177e4 599 if (! chip->in_ac97_init)
99b359ba 600 snd_printk(KERN_ERR "codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
1da177e4
LT		 601 res = 0xffff;
602 }
603 }
604 return res;
605}
606
6b75a9d8 607static void snd_intel8x0_codec_read_test(struct intel8x0 *chip, unsigned int codec)
1da177e4
LT		 608{
609 unsigned int tmp;
610
611 if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
612 iagetword(chip, codec * 0x80);
613 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
614 /* reset RCS and preserve other R/WC bits */
6b75a9d8
TI		 615 iputdword(chip, ICHREG(GLOB_STA), tmp &
616 ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
1da177e4
LT		 617 }
618 }
619}
620
621/*
622 * access to AC97 for Ali5455
623 */
6b75a9d8 624static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
1da177e4
LT		 625{
626 int count = 0;
627 for (count = 0; count < 0x7f; count++) {
628 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
629 if (val & mask)
630 return 0;
631 }
79ba34b9
TI		 632 if (! chip->in_ac97_init)
633 snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n");
1da177e4
LT		 634 return -EBUSY;
635}
636
6b75a9d8 637static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
1da177e4
LT		 638{
639 int time = 100;
79ba34b9
TI		 640 if (chip->buggy_semaphore)
641 return 0; /* just ignore ... */
1da177e4
LT		 642 while (time-- && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
643 udelay(1);
79ba34b9 644 if (! time && ! chip->in_ac97_init)
1da177e4
LT		 645 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n");
646 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
647}
648
6b75a9d8 649static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
1da177e4 650{
6b75a9d8 651 struct intel8x0 *chip = ac97->private_data;
1da177e4
LT		 652 unsigned short data = 0xffff;
653
654 if (snd_intel8x0_ali_codec_semaphore(chip))
655 goto __err;
656 reg |= ALI_CPR_ADDR_READ;
657 if (ac97->num)
658 reg |= ALI_CPR_ADDR_SECONDARY;
659 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
660 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
661 goto __err;
662 data = igetword(chip, ICHREG(ALI_SPR));
663 __err:
664 return data;
665}
666
6b75a9d8
TI		 667static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
668 unsigned short val)
1da177e4 669{
6b75a9d8 670 struct intel8x0 *chip = ac97->private_data;
1da177e4
LT		 671
672 if (snd_intel8x0_ali_codec_semaphore(chip))
673 return;
674 iputword(chip, ICHREG(ALI_CPR), val);
675 if (ac97->num)
676 reg |= ALI_CPR_ADDR_SECONDARY;
677 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
678 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
679}
680
681
682/*
683 * DMA I/O
684 */
6b75a9d8 685static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev)
1da177e4
LT		 686{
687 int idx;
688 u32 *bdbar = ichdev->bdbar;
689 unsigned long port = ichdev->reg_offset;
690
691 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
692 if (ichdev->size == ichdev->fragsize) {
693 ichdev->ack_reload = ichdev->ack = 2;
694 ichdev->fragsize1 = ichdev->fragsize >> 1;
695 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
696 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
697 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
698 ichdev->fragsize1 >> ichdev->pos_shift);
699 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
700 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
701 ichdev->fragsize1 >> ichdev->pos_shift);
702 }
703 ichdev->frags = 2;
704 } else {
705 ichdev->ack_reload = ichdev->ack = 1;
706 ichdev->fragsize1 = ichdev->fragsize;
707 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
6b75a9d8
TI		 708 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
709 (((idx >> 1) * ichdev->fragsize) %
710 ichdev->size));
1da177e4
LT		 711 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
712 ichdev->fragsize >> ichdev->pos_shift);
6b75a9d8
TI		 713#if 0
714 printk("bdbar[%i] = 0x%x [0x%x]\n",
715 idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
716#endif
1da177e4
LT		 717 }
718 ichdev->frags = ichdev->size / ichdev->fragsize;
719 }
720 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
721 ichdev->civ = 0;
722 iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
723 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
724 ichdev->position = 0;
725#if 0
726 printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
727 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1);
728#endif
729 /* clear interrupts */
730 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
731}
732
733#ifdef __i386__
734/*
735 * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
736 * which aborts PCI busmaster for audio transfer. A workaround is to set
737 * the pages as non-cached. For details, see the errata in
738 * http://www.intel.com/design/chipsets/specupdt/245051.htm
739 */
740static void fill_nocache(void *buf, int size, int nocache)
741{
742 size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
743 change_page_attr(virt_to_page(buf), size, nocache ? PAGE_KERNEL_NOCACHE : PAGE_KERNEL);
744 global_flush_tlb();
745}
746#else
747#define fill_nocache(buf,size,nocache)
748#endif
749
750/*
751 * Interrupt handler
752 */
753
6b75a9d8 754static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
1da177e4
LT		 755{
756 unsigned long port = ichdev->reg_offset;
757 int status, civ, i, step;
758 int ack = 0;
759
760 spin_lock(&chip->reg_lock);
761 status = igetbyte(chip, port + ichdev->roff_sr);
762 civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
763 if (!(status & ICH_BCIS)) {
764 step = 0;
765 } else if (civ == ichdev->civ) {
766 // snd_printd("civ same %d\n", civ);
767 step = 1;
768 ichdev->civ++;
769 ichdev->civ &= ICH_REG_LVI_MASK;
770 } else {
771 step = civ - ichdev->civ;
772 if (step < 0)
773 step += ICH_REG_LVI_MASK + 1;
774 // if (step != 1)
775 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
776 ichdev->civ = civ;
777 }
778
779 ichdev->position += step * ichdev->fragsize1;
780 if (! chip->in_measurement)
781 ichdev->position %= ichdev->size;
782 ichdev->lvi += step;
783 ichdev->lvi &= ICH_REG_LVI_MASK;
784 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
785 for (i = 0; i < step; i++) {
786 ichdev->lvi_frag++;
787 ichdev->lvi_frag %= ichdev->frags;
788 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
6b75a9d8
TI		 789#if 0
790 printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n",
791 ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
792 ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
793 inl(port + 4), inb(port + ICH_REG_OFF_CR));
794#endif
1da177e4
LT		 795 if (--ichdev->ack == 0) {
796 ichdev->ack = ichdev->ack_reload;
797 ack = 1;
798 }
799 }
800 spin_unlock(&chip->reg_lock);
801 if (ack && ichdev->substream) {
802 snd_pcm_period_elapsed(ichdev->substream);
803 }
804 iputbyte(chip, port + ichdev->roff_sr,
805 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
806}
807
808static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id, struct pt_regs *regs)
809{
6b75a9d8
TI		 810 struct intel8x0 *chip = dev_id;
811 struct ichdev *ichdev;
1da177e4
LT		 812 unsigned int status;
813 unsigned int i;
814
815 status = igetdword(chip, chip->int_sta_reg);
816 if (status == 0xffffffff) /* we are not yet resumed */
817 return IRQ_NONE;
818
819 if ((status & chip->int_sta_mask) == 0) {
820 if (status) {
821 /* ack */
822 iputdword(chip, chip->int_sta_reg, status);
823 if (! chip->buggy_irq)
824 status = 0;
825 }
826 return IRQ_RETVAL(status);
827 }
828
829 for (i = 0; i < chip->bdbars_count; i++) {
830 ichdev = &chip->ichd[i];
831 if (status & ichdev->int_sta_mask)
832 snd_intel8x0_update(chip, ichdev);
833 }
834
835 /* ack them */
836 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
837
838 return IRQ_HANDLED;
839}
840
841/*
842 * PCM part
843 */
844
6b75a9d8 845static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4 846{
6b75a9d8
TI		 847 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
848 struct ichdev *ichdev = get_ichdev(substream);
1da177e4
LT		 849 unsigned char val = 0;
850 unsigned long port = ichdev->reg_offset;
851
852 switch (cmd) {
1da177e4 853 case SNDRV_PCM_TRIGGER_RESUME:
1cfe43d2
TI		 854 ichdev->suspended = 0;
855 /* fallthru */
856 case SNDRV_PCM_TRIGGER_START:
1da177e4
LT		 857 val = ICH_IOCE | ICH_STARTBM;
858 break;
1da177e4 859 case SNDRV_PCM_TRIGGER_SUSPEND:
1cfe43d2
TI		 860 ichdev->suspended = 1;
861 /* fallthru */
862 case SNDRV_PCM_TRIGGER_STOP:
1da177e4
LT		 863 val = 0;
864 break;
865 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
866 val = ICH_IOCE;
867 break;
868 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
869 val = ICH_IOCE | ICH_STARTBM;
870 break;
871 default:
872 return -EINVAL;
873 }
874 iputbyte(chip, port + ICH_REG_OFF_CR, val);
875 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
876 /* wait until DMA stopped */
877 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
878 /* reset whole DMA things */
879 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
880 }
881 return 0;
882}
883
6b75a9d8 884static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
1da177e4 885{
6b75a9d8
TI		 886 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
887 struct ichdev *ichdev = get_ichdev(substream);
1da177e4 888 unsigned long port = ichdev->reg_offset;
6b75a9d8
TI		 889 static int fiforeg[] = {
890 ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
891 };
1da177e4
LT		 892 unsigned int val, fifo;
893
894 val = igetdword(chip, ICHREG(ALI_DMACR));
895 switch (cmd) {
1cfe43d2
TI		 896 case SNDRV_PCM_TRIGGER_RESUME:
897 ichdev->suspended = 0;
898 /* fallthru */
1da177e4
LT		 899 case SNDRV_PCM_TRIGGER_START:
900 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1da177e4
LT		 901 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
902 /* clear FIFO for synchronization of channels */
903 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
904 fifo &= ~(0xff << (ichdev->ali_slot % 4));
905 fifo |= 0x83 << (ichdev->ali_slot % 4);
906 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
907 }
908 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
909 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
6b75a9d8
TI		 910 /* start DMA */
911 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot));
1da177e4 912 break;
1cfe43d2
TI		 913 case SNDRV_PCM_TRIGGER_SUSPEND:
914 ichdev->suspended = 1;
915 /* fallthru */
1da177e4
LT		 916 case SNDRV_PCM_TRIGGER_STOP:
917 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
6b75a9d8
TI		 918 /* pause */
919 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16)));
1da177e4
LT		 920 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
921 while (igetbyte(chip, port + ICH_REG_OFF_CR))
922 ;
923 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
924 break;
925 /* reset whole DMA things */
926 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
927 /* clear interrupts */
6b75a9d8
TI		 928 iputbyte(chip, port + ICH_REG_OFF_SR,
929 igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
1da177e4
LT		 930 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
931 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
932 break;
933 default:
934 return -EINVAL;
935 }
936 return 0;
937}
938
6b75a9d8
TI		 939static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
940 struct snd_pcm_hw_params *hw_params)
1da177e4 941{
6b75a9d8
TI		 942 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
943 struct ichdev *ichdev = get_ichdev(substream);
944 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 945 int dbl = params_rate(hw_params) > 48000;
946 int err;
947
948 if (chip->fix_nocache && ichdev->page_attr_changed) {
949 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
950 ichdev->page_attr_changed = 0;
951 }
952 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
953 if (err < 0)
954 return err;
955 if (chip->fix_nocache) {
956 if (runtime->dma_area && ! ichdev->page_attr_changed) {
957 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
958 ichdev->page_attr_changed = 1;
959 }
960 }
961 if (ichdev->pcm_open_flag) {
962 snd_ac97_pcm_close(ichdev->pcm);
963 ichdev->pcm_open_flag = 0;
964 }
965 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
966 params_channels(hw_params),
967 ichdev->pcm->r[dbl].slots);
968 if (err >= 0) {
969 ichdev->pcm_open_flag = 1;
970 /* Force SPDIF setting */
971 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
6b75a9d8
TI		 972 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
973 params_rate(hw_params));
1da177e4
LT		 974 }
975 return err;
976}
977
6b75a9d8 978static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
1da177e4 979{
6b75a9d8
TI		 980 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
981 struct ichdev *ichdev = get_ichdev(substream);
1da177e4
LT		 982
983 if (ichdev->pcm_open_flag) {
984 snd_ac97_pcm_close(ichdev->pcm);
985 ichdev->pcm_open_flag = 0;
986 }
987 if (chip->fix_nocache && ichdev->page_attr_changed) {
988 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
989 ichdev->page_attr_changed = 0;
990 }
991 return snd_pcm_lib_free_pages(substream);
992}
993
6b75a9d8
TI		 994static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
995 struct snd_pcm_runtime *runtime)
1da177e4
LT		 996{
997 unsigned int cnt;
998 int dbl = runtime->rate > 48000;
1cfe43d2
TI		 999
1000 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 1001 switch (chip->device_type) {
1002 case DEVICE_ALI:
1003 cnt = igetdword(chip, ICHREG(ALI_SCR));
1004 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
1005 if (runtime->channels == 4 || dbl)
1006 cnt |= ICH_ALI_SC_PCM_4;
1007 else if (runtime->channels == 6)
1008 cnt |= ICH_ALI_SC_PCM_6;
1009 iputdword(chip, ICHREG(ALI_SCR), cnt);
1010 break;
1011 case DEVICE_SIS:
1012 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1013 cnt &= ~ICH_SIS_PCM_246_MASK;
1014 if (runtime->channels == 4 || dbl)
1015 cnt |= ICH_SIS_PCM_4;
1016 else if (runtime->channels == 6)
1017 cnt |= ICH_SIS_PCM_6;
1018 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1019 break;
1020 default:
1021 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1022 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
1023 if (runtime->channels == 4 || dbl)
1024 cnt |= ICH_PCM_4;
1025 else if (runtime->channels == 6)
1026 cnt |= ICH_PCM_6;
1027 if (chip->device_type == DEVICE_NFORCE) {
1028 /* reset to 2ch once to keep the 6 channel data in alignment,
1029 * to start from Front Left always
1030 */
1031 if (cnt & ICH_PCM_246_MASK) {
1032 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
1033 spin_unlock_irq(&chip->reg_lock);
1034 msleep(50); /* grrr... */
1035 spin_lock_irq(&chip->reg_lock);
1036 }
1037 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
1038 if (runtime->sample_bits > 16)
1039 cnt |= ICH_PCM_20BIT;
1040 }
1041 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1042 break;
1043 }
1cfe43d2 1044 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 1045}
1046
6b75a9d8 1047static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
1da177e4 1048{
6b75a9d8
TI		 1049 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1050 struct snd_pcm_runtime *runtime = substream->runtime;
1051 struct ichdev *ichdev = get_ichdev(substream);
1da177e4
LT		 1052
1053 ichdev->physbuf = runtime->dma_addr;
1054 ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1055 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1da177e4
LT		 1056 if (ichdev->ichd == ICHD_PCMOUT) {
1057 snd_intel8x0_setup_pcm_out(chip, runtime);
1cfe43d2 1058 if (chip->device_type == DEVICE_INTEL_ICH4)
1da177e4 1059 ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1da177e4
LT		 1060 }
1061 snd_intel8x0_setup_periods(chip, ichdev);
1da177e4
LT		 1062 return 0;
1063}
1064
6b75a9d8 1065static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
1da177e4 1066{
6b75a9d8
TI		 1067 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1068 struct ichdev *ichdev = get_ichdev(substream);
1da177e4
LT		 1069 size_t ptr1, ptr;
1070 int civ, timeout = 100;
1071 unsigned int position;
1072
1073 spin_lock(&chip->reg_lock);
1074 do {
1075 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1076 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1077 position = ichdev->position;
1078 if (ptr1 == 0) {
1079 udelay(10);
1080 continue;
1081 }
1082 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
1083 ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1084 break;
1085 } while (timeout--);
1086 ptr1 <<= ichdev->pos_shift;
1087 ptr = ichdev->fragsize1 - ptr1;
1088 ptr += position;
1089 spin_unlock(&chip->reg_lock);
1090 if (ptr >= ichdev->size)
1091 return 0;
1092 return bytes_to_frames(substream->runtime, ptr);
1093}
1094
6b75a9d8 1095static struct snd_pcm_hardware snd_intel8x0_stream =
1da177e4
LT		 1096{
1097 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1098 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1099 SNDRV_PCM_INFO_MMAP_VALID |
1100 SNDRV_PCM_INFO_PAUSE |
1101 SNDRV_PCM_INFO_RESUME),
1102 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1103 .rates = SNDRV_PCM_RATE_48000,
1104 .rate_min = 48000,
1105 .rate_max = 48000,
1106 .channels_min = 2,
1107 .channels_max = 2,
1108 .buffer_bytes_max = 128 * 1024,
1109 .period_bytes_min = 32,
1110 .period_bytes_max = 128 * 1024,
1111 .periods_min = 1,
1112 .periods_max = 1024,
1113 .fifo_size = 0,
1114};
1115
1116static unsigned int channels4[] = {
1117 2, 4,
1118};
1119
6b75a9d8 1120static struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
1da177e4
LT		 1121 .count = ARRAY_SIZE(channels4),
1122 .list = channels4,
1123 .mask = 0,
1124};
1125
1126static unsigned int channels6[] = {
1127 2, 4, 6,
1128};
1129
6b75a9d8 1130static struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
1da177e4
LT		 1131 .count = ARRAY_SIZE(channels6),
1132 .list = channels6,
1133 .mask = 0,
1134};
1135
6b75a9d8 1136static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
1da177e4 1137{
6b75a9d8
TI		 1138 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1139 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1140 int err;
1141
1142 ichdev->substream = substream;
1143 runtime->hw = snd_intel8x0_stream;
1144 runtime->hw.rates = ichdev->pcm->rates;
1145 snd_pcm_limit_hw_rates(runtime);
1146 if (chip->device_type == DEVICE_SIS) {
1147 runtime->hw.buffer_bytes_max = 64*1024;
1148 runtime->hw.period_bytes_max = 64*1024;
1149 }
1150 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1151 return err;
1152 runtime->private_data = ichdev;
1153 return 0;
1154}
1155
6b75a9d8 1156static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
1da177e4 1157{
6b75a9d8
TI		 1158 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1159 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1160 int err;
1161
1162 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1163 if (err < 0)
1164 return err;
1165
1166 if (chip->multi6) {
1167 runtime->hw.channels_max = 6;
6b75a9d8
TI		 1168 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1169 &hw_constraints_channels6);
1da177e4
LT		 1170 } else if (chip->multi4) {
1171 runtime->hw.channels_max = 4;
6b75a9d8
TI		 1172 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1173 &hw_constraints_channels4);
1da177e4
LT		 1174 }
1175 if (chip->dra) {
1176 snd_ac97_pcm_double_rate_rules(runtime);
1177 }
1178 if (chip->smp20bit) {
1179 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1180 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1181 }
1182 return 0;
1183}
1184
6b75a9d8 1185static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
1da177e4 1186{
6b75a9d8 1187 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1188
1189 chip->ichd[ICHD_PCMOUT].substream = NULL;
1190 return 0;
1191}
1192
6b75a9d8 1193static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
1da177e4 1194{
6b75a9d8 1195 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1196
1197 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1198}
1199
6b75a9d8 1200static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
1da177e4 1201{
6b75a9d8 1202 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1203
1204 chip->ichd[ICHD_PCMIN].substream = NULL;
1205 return 0;
1206}
1207
6b75a9d8 1208static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
1da177e4 1209{
6b75a9d8 1210 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1211
1212 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1213}
1214
6b75a9d8 1215static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
1da177e4 1216{
6b75a9d8 1217 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1218
1219 chip->ichd[ICHD_MIC].substream = NULL;
1220 return 0;
1221}
1222
6b75a9d8 1223static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
1da177e4 1224{
6b75a9d8 1225 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1226
1227 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1228}
1229
6b75a9d8 1230static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
1da177e4 1231{
6b75a9d8 1232 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1233
1234 chip->ichd[ICHD_MIC2].substream = NULL;
1235 return 0;
1236}
1237
6b75a9d8 1238static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
1da177e4 1239{
6b75a9d8 1240 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1241
1242 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1243}
1244
6b75a9d8 1245static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
1da177e4 1246{
6b75a9d8 1247 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1248
1249 chip->ichd[ICHD_PCM2IN].substream = NULL;
1250 return 0;
1251}
1252
6b75a9d8 1253static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
1da177e4 1254{
6b75a9d8 1255 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1256 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1257
1258 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1259}
1260
6b75a9d8 1261static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
1da177e4 1262{
6b75a9d8 1263 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1264 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1265
1266 chip->ichd[idx].substream = NULL;
1267 return 0;
1268}
1269
6b75a9d8 1270static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
1da177e4 1271{
6b75a9d8 1272 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1273 unsigned int val;
1274
1275 spin_lock_irq(&chip->reg_lock);
1276 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1277 val |= ICH_ALI_IF_AC97SP;
1278 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1279 /* also needs to set ALI_SC_CODEC_SPDF correctly */
1280 spin_unlock_irq(&chip->reg_lock);
1281
1282 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1283}
1284
6b75a9d8 1285static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
1da177e4 1286{
6b75a9d8 1287 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1288 unsigned int val;
1289
1290 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1291 spin_lock_irq(&chip->reg_lock);
1292 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1293 val &= ~ICH_ALI_IF_AC97SP;
1294 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1295 spin_unlock_irq(&chip->reg_lock);
1296
1297 return 0;
1298}
1299
6b75a9d8 1300static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
1da177e4 1301{
6b75a9d8 1302 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1303
1304 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1305}
1306
6b75a9d8 1307static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
1da177e4 1308{
6b75a9d8 1309 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1310
1311 chip->ichd[ALID_SPDIFIN].substream = NULL;
1312 return 0;
1313}
1314
1315#if 0 // NYI
6b75a9d8 1316static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
1da177e4 1317{
6b75a9d8 1318 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1319
1320 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1321}
1322
6b75a9d8 1323static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
1da177e4 1324{
6b75a9d8 1325 struct intel8x0 *chip = snd_pcm_substream_chip(substream);
1da177e4
LT		 1326
1327 chip->ichd[ALID_SPDIFOUT].substream = NULL;
1328 return 0;
1329}
1330#endif
1331
6b75a9d8 1332static struct snd_pcm_ops snd_intel8x0_playback_ops = {
1da177e4
LT		 1333 .open = snd_intel8x0_playback_open,
1334 .close = snd_intel8x0_playback_close,
1335 .ioctl = snd_pcm_lib_ioctl,
1336 .hw_params = snd_intel8x0_hw_params,
1337 .hw_free = snd_intel8x0_hw_free,
1338 .prepare = snd_intel8x0_pcm_prepare,
1339 .trigger = snd_intel8x0_pcm_trigger,
1340 .pointer = snd_intel8x0_pcm_pointer,
1341};
1342
6b75a9d8 1343static struct snd_pcm_ops snd_intel8x0_capture_ops = {
1da177e4
LT		 1344 .open = snd_intel8x0_capture_open,
1345 .close = snd_intel8x0_capture_close,
1346 .ioctl = snd_pcm_lib_ioctl,
1347 .hw_params = snd_intel8x0_hw_params,
1348 .hw_free = snd_intel8x0_hw_free,
1349 .prepare = snd_intel8x0_pcm_prepare,
1350 .trigger = snd_intel8x0_pcm_trigger,
1351 .pointer = snd_intel8x0_pcm_pointer,
1352};
1353
6b75a9d8 1354static struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
1da177e4
LT		 1355 .open = snd_intel8x0_mic_open,
1356 .close = snd_intel8x0_mic_close,
1357 .ioctl = snd_pcm_lib_ioctl,
1358 .hw_params = snd_intel8x0_hw_params,
1359 .hw_free = snd_intel8x0_hw_free,
1360 .prepare = snd_intel8x0_pcm_prepare,
1361 .trigger = snd_intel8x0_pcm_trigger,
1362 .pointer = snd_intel8x0_pcm_pointer,
1363};
1364
6b75a9d8 1365static struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
1da177e4
LT		 1366 .open = snd_intel8x0_mic2_open,
1367 .close = snd_intel8x0_mic2_close,
1368 .ioctl = snd_pcm_lib_ioctl,
1369 .hw_params = snd_intel8x0_hw_params,
1370 .hw_free = snd_intel8x0_hw_free,
1371 .prepare = snd_intel8x0_pcm_prepare,
1372 .trigger = snd_intel8x0_pcm_trigger,
1373 .pointer = snd_intel8x0_pcm_pointer,
1374};
1375
6b75a9d8 1376static struct snd_pcm_ops snd_intel8x0_capture2_ops = {
1da177e4
LT		 1377 .open = snd_intel8x0_capture2_open,
1378 .close = snd_intel8x0_capture2_close,
1379 .ioctl = snd_pcm_lib_ioctl,
1380 .hw_params = snd_intel8x0_hw_params,
1381 .hw_free = snd_intel8x0_hw_free,
1382 .prepare = snd_intel8x0_pcm_prepare,
1383 .trigger = snd_intel8x0_pcm_trigger,
1384 .pointer = snd_intel8x0_pcm_pointer,
1385};
1386
6b75a9d8 1387static struct snd_pcm_ops snd_intel8x0_spdif_ops = {
1da177e4
LT		 1388 .open = snd_intel8x0_spdif_open,
1389 .close = snd_intel8x0_spdif_close,
1390 .ioctl = snd_pcm_lib_ioctl,
1391 .hw_params = snd_intel8x0_hw_params,
1392 .hw_free = snd_intel8x0_hw_free,
1393 .prepare = snd_intel8x0_pcm_prepare,
1394 .trigger = snd_intel8x0_pcm_trigger,
1395 .pointer = snd_intel8x0_pcm_pointer,
1396};
1397
6b75a9d8 1398static struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
1da177e4
LT		 1399 .open = snd_intel8x0_playback_open,
1400 .close = snd_intel8x0_playback_close,
1401 .ioctl = snd_pcm_lib_ioctl,
1402 .hw_params = snd_intel8x0_hw_params,
1403 .hw_free = snd_intel8x0_hw_free,
1404 .prepare = snd_intel8x0_pcm_prepare,
1405 .trigger = snd_intel8x0_ali_trigger,
1406 .pointer = snd_intel8x0_pcm_pointer,
1407};
1408
6b75a9d8 1409static struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
1da177e4
LT		 1410 .open = snd_intel8x0_capture_open,
1411 .close = snd_intel8x0_capture_close,
1412 .ioctl = snd_pcm_lib_ioctl,
1413 .hw_params = snd_intel8x0_hw_params,
1414 .hw_free = snd_intel8x0_hw_free,
1415 .prepare = snd_intel8x0_pcm_prepare,
1416 .trigger = snd_intel8x0_ali_trigger,
1417 .pointer = snd_intel8x0_pcm_pointer,
1418};
1419
6b75a9d8 1420static struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
1da177e4
LT		 1421 .open = snd_intel8x0_mic_open,
1422 .close = snd_intel8x0_mic_close,
1423 .ioctl = snd_pcm_lib_ioctl,
1424 .hw_params = snd_intel8x0_hw_params,
1425 .hw_free = snd_intel8x0_hw_free,
1426 .prepare = snd_intel8x0_pcm_prepare,
1427 .trigger = snd_intel8x0_ali_trigger,
1428 .pointer = snd_intel8x0_pcm_pointer,
1429};
1430
6b75a9d8 1431static struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
1da177e4
LT		 1432 .open = snd_intel8x0_ali_ac97spdifout_open,
1433 .close = snd_intel8x0_ali_ac97spdifout_close,
1434 .ioctl = snd_pcm_lib_ioctl,
1435 .hw_params = snd_intel8x0_hw_params,
1436 .hw_free = snd_intel8x0_hw_free,
1437 .prepare = snd_intel8x0_pcm_prepare,
1438 .trigger = snd_intel8x0_ali_trigger,
1439 .pointer = snd_intel8x0_pcm_pointer,
1440};
1441
6b75a9d8 1442static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
1da177e4
LT		 1443 .open = snd_intel8x0_ali_spdifin_open,
1444 .close = snd_intel8x0_ali_spdifin_close,
1445 .ioctl = snd_pcm_lib_ioctl,
1446 .hw_params = snd_intel8x0_hw_params,
1447 .hw_free = snd_intel8x0_hw_free,
1448 .prepare = snd_intel8x0_pcm_prepare,
1449 .trigger = snd_intel8x0_pcm_trigger,
1450 .pointer = snd_intel8x0_pcm_pointer,
1451};
1452
1453#if 0 // NYI
6b75a9d8 1454static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
1da177e4
LT		 1455 .open = snd_intel8x0_ali_spdifout_open,
1456 .close = snd_intel8x0_ali_spdifout_close,
1457 .ioctl = snd_pcm_lib_ioctl,
1458 .hw_params = snd_intel8x0_hw_params,
1459 .hw_free = snd_intel8x0_hw_free,
1460 .prepare = snd_intel8x0_pcm_prepare,
1461 .trigger = snd_intel8x0_pcm_trigger,
1462 .pointer = snd_intel8x0_pcm_pointer,
1463};
1464#endif // NYI
1465
1466struct ich_pcm_table {
1467 char *suffix;
6b75a9d8
TI		 1468 struct snd_pcm_ops *playback_ops;
1469 struct snd_pcm_ops *capture_ops;
1da177e4
LT		 1470 size_t prealloc_size;
1471 size_t prealloc_max_size;
1472 int ac97_idx;
1473};
1474
6b75a9d8
TI		 1475static int __devinit snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
1476 struct ich_pcm_table *rec)
1da177e4 1477{
6b75a9d8 1478 struct snd_pcm *pcm;
1da177e4
LT		 1479 int err;
1480 char name[32];
1481
1482 if (rec->suffix)
1483 sprintf(name, "Intel ICH - %s", rec->suffix);
1484 else
1485 strcpy(name, "Intel ICH");
1486 err = snd_pcm_new(chip->card, name, device,
1487 rec->playback_ops ? 1 : 0,
1488 rec->capture_ops ? 1 : 0, &pcm);
1489 if (err < 0)
1490 return err;
1491
1492 if (rec->playback_ops)
1493 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1494 if (rec->capture_ops)
1495 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1496
1497 pcm->private_data = chip;
1498 pcm->info_flags = 0;
1499 if (rec->suffix)
1500 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1501 else
1502 strcpy(pcm->name, chip->card->shortname);
1503 chip->pcm[device] = pcm;
1504
6b75a9d8
TI		 1505 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1506 snd_dma_pci_data(chip->pci),
1da177e4
LT		 1507 rec->prealloc_size, rec->prealloc_max_size);
1508
1509 return 0;
1510}
1511
1512static struct ich_pcm_table intel_pcms[] __devinitdata = {
1513 {
1514 .playback_ops = &snd_intel8x0_playback_ops,
1515 .capture_ops = &snd_intel8x0_capture_ops,
1516 .prealloc_size = 64 * 1024,
1517 .prealloc_max_size = 128 * 1024,
1518 },
1519 {
1520 .suffix = "MIC ADC",
1521 .capture_ops = &snd_intel8x0_capture_mic_ops,
1522 .prealloc_size = 0,
1523 .prealloc_max_size = 128 * 1024,
1524 .ac97_idx = ICHD_MIC,
1525 },
1526 {
1527 .suffix = "MIC2 ADC",
1528 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1529 .prealloc_size = 0,
1530 .prealloc_max_size = 128 * 1024,
1531 .ac97_idx = ICHD_MIC2,
1532 },
1533 {
1534 .suffix = "ADC2",
1535 .capture_ops = &snd_intel8x0_capture2_ops,
1536 .prealloc_size = 0,
1537 .prealloc_max_size = 128 * 1024,
1538 .ac97_idx = ICHD_PCM2IN,
1539 },
1540 {
1541 .suffix = "IEC958",
1542 .playback_ops = &snd_intel8x0_spdif_ops,
1543 .prealloc_size = 64 * 1024,
1544 .prealloc_max_size = 128 * 1024,
1545 .ac97_idx = ICHD_SPBAR,
1546 },
1547};
1548
1549static struct ich_pcm_table nforce_pcms[] __devinitdata = {
1550 {
1551 .playback_ops = &snd_intel8x0_playback_ops,
1552 .capture_ops = &snd_intel8x0_capture_ops,
1553 .prealloc_size = 64 * 1024,
1554 .prealloc_max_size = 128 * 1024,
1555 },
1556 {
1557 .suffix = "MIC ADC",
1558 .capture_ops = &snd_intel8x0_capture_mic_ops,
1559 .prealloc_size = 0,
1560 .prealloc_max_size = 128 * 1024,
1561 .ac97_idx = NVD_MIC,
1562 },
1563 {
1564 .suffix = "IEC958",
1565 .playback_ops = &snd_intel8x0_spdif_ops,
1566 .prealloc_size = 64 * 1024,
1567 .prealloc_max_size = 128 * 1024,
1568 .ac97_idx = NVD_SPBAR,
1569 },
1570};
1571
1572static struct ich_pcm_table ali_pcms[] __devinitdata = {
1573 {
1574 .playback_ops = &snd_intel8x0_ali_playback_ops,
1575 .capture_ops = &snd_intel8x0_ali_capture_ops,
1576 .prealloc_size = 64 * 1024,
1577 .prealloc_max_size = 128 * 1024,
1578 },
1579 {
1580 .suffix = "MIC ADC",
1581 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1582 .prealloc_size = 0,
1583 .prealloc_max_size = 128 * 1024,
1584 .ac97_idx = ALID_MIC,
1585 },
1586 {
1587 .suffix = "IEC958",
1588 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1589 .capture_ops = &snd_intel8x0_ali_spdifin_ops,
1590 .prealloc_size = 64 * 1024,
1591 .prealloc_max_size = 128 * 1024,
1592 .ac97_idx = ALID_AC97SPDIFOUT,
1593 },
1594#if 0 // NYI
1595 {
1596 .suffix = "HW IEC958",
1597 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1598 .prealloc_size = 64 * 1024,
1599 .prealloc_max_size = 128 * 1024,
1600 },
1601#endif
1602};
1603
6b75a9d8 1604static int __devinit snd_intel8x0_pcm(struct intel8x0 *chip)
1da177e4
LT		 1605{
1606 int i, tblsize, device, err;
1607 struct ich_pcm_table *tbl, *rec;
1608
1609 switch (chip->device_type) {
1610 case DEVICE_INTEL_ICH4:
1611 tbl = intel_pcms;
1612 tblsize = ARRAY_SIZE(intel_pcms);
1613 break;
1614 case DEVICE_NFORCE:
1615 tbl = nforce_pcms;
1616 tblsize = ARRAY_SIZE(nforce_pcms);
1617 break;
1618 case DEVICE_ALI:
1619 tbl = ali_pcms;
1620 tblsize = ARRAY_SIZE(ali_pcms);
1621 break;
1622 default:
1623 tbl = intel_pcms;
1624 tblsize = 2;
1625 break;
1626 }
1627
1628 device = 0;
1629 for (i = 0; i < tblsize; i++) {
1630 rec = tbl + i;
1631 if (i > 0 && rec->ac97_idx) {
1632 /* activate PCM only when associated AC'97 codec */
1633 if (! chip->ichd[rec->ac97_idx].pcm)
1634 continue;
1635 }
1636 err = snd_intel8x0_pcm1(chip, device, rec);
1637 if (err < 0)
1638 return err;
1639 device++;
1640 }
1641
1642 chip->pcm_devs = device;
1643 return 0;
1644}
1645
1646
1647/*
1648 * Mixer part
1649 */
1650
6b75a9d8 1651static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1da177e4 1652{
6b75a9d8 1653 struct intel8x0 *chip = bus->private_data;
1da177e4
LT		 1654 chip->ac97_bus = NULL;
1655}
1656
6b75a9d8 1657static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
1da177e4 1658{
6b75a9d8 1659 struct intel8x0 *chip = ac97->private_data;
1da177e4
LT		 1660 chip->ac97[ac97->num] = NULL;
1661}
1662
1663static struct ac97_pcm ac97_pcm_defs[] __devinitdata = {
1664 /* front PCM */
1665 {
1666 .exclusive = 1,
1667 .r = { {
1668 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1669 (1 << AC97_SLOT_PCM_RIGHT) |
1670 (1 << AC97_SLOT_PCM_CENTER) |
1671 (1 << AC97_SLOT_PCM_SLEFT) |
1672 (1 << AC97_SLOT_PCM_SRIGHT) |
1673 (1 << AC97_SLOT_LFE)
1674 },
1675 {
1676 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1677 (1 << AC97_SLOT_PCM_RIGHT) |
1678 (1 << AC97_SLOT_PCM_LEFT_0) |
1679 (1 << AC97_SLOT_PCM_RIGHT_0)
1680 }
1681 }
1682 },
1683 /* PCM IN #1 */
1684 {
1685 .stream = 1,
1686 .exclusive = 1,
1687 .r = { {
1688 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1689 (1 << AC97_SLOT_PCM_RIGHT)
1690 }
1691 }
1692 },
1693 /* MIC IN #1 */
1694 {
1695 .stream = 1,
1696 .exclusive = 1,
1697 .r = { {
1698 .slots = (1 << AC97_SLOT_MIC)
1699 }
1700 }
1701 },
1702 /* S/PDIF PCM */
1703 {
1704 .exclusive = 1,
1705 .spdif = 1,
1706 .r = { {
1707 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1708 (1 << AC97_SLOT_SPDIF_RIGHT2)
1709 }
1710 }
1711 },
1712 /* PCM IN #2 */
1713 {
1714 .stream = 1,
1715 .exclusive = 1,
1716 .r = { {
1717 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1718 (1 << AC97_SLOT_PCM_RIGHT)
1719 }
1720 }
1721 },
1722 /* MIC IN #2 */
1723 {
1724 .stream = 1,
1725 .exclusive = 1,
1726 .r = { {
1727 .slots = (1 << AC97_SLOT_MIC)
1728 }
1729 }
1730 },
1731};
1732
1733static struct ac97_quirk ac97_quirks[] __devinitdata = {
1734 {
6fd8b87f
JCD		 1735 .subvendor = 0x0e11,
1736 .subdevice = 0x008a,
1da177e4
LT		 1737 .name = "Compaq Evo W4000", /* AD1885 */
1738 .type = AC97_TUNE_HP_ONLY
1739 },
1740 {
6fd8b87f
JCD		 1741 .subvendor = 0x0e11,
1742 .subdevice = 0x00b8,
1da177e4
LT		 1743 .name = "Compaq Evo D510C",
1744 .type = AC97_TUNE_HP_ONLY
1745 },
1746 {
6fd8b87f
JCD		 1747 .subvendor = 0x0e11,
1748 .subdevice = 0x0860,
1da177e4
LT		 1749 .name = "HP/Compaq nx7010",
1750 .type = AC97_TUNE_MUTE_LED
1751 },
1752 {
6fd8b87f
JCD		 1753 .subvendor = 0x1014,
1754 .subdevice = 0x1f00,
1da177e4
LT		 1755 .name = "MS-9128",
1756 .type = AC97_TUNE_ALC_JACK
1757 },
5d529390
TI		 1758 {
1759 .subvendor = 0x1014,
1760 .subdevice = 0x0267,
1761 .name = "IBM NetVista A30p", /* AD1981B */
1762 .type = AC97_TUNE_HP_ONLY
1763 },
72c8986c
DS		 1764 {
1765 .subvendor = 0x1025,
1766 .subdevice = 0x0083,
1767 .name = "Acer Aspire 3003LCi",
1768 .type = AC97_TUNE_HP_ONLY
1769 },
1da177e4 1770 {
6fd8b87f
JCD		 1771 .subvendor = 0x1028,
1772 .subdevice = 0x00d8,
1da177e4
LT		 1773 .name = "Dell Precision 530", /* AD1885 */
1774 .type = AC97_TUNE_HP_ONLY
1775 },
1776 {
6fd8b87f
JCD		 1777 .subvendor = 0x1028,
1778 .subdevice = 0x010d,
1da177e4
LT		 1779 .name = "Dell", /* which model? AD1885 */
1780 .type = AC97_TUNE_HP_ONLY
1781 },
1782 {
6fd8b87f
JCD		 1783 .subvendor = 0x1028,
1784 .subdevice = 0x0126,
1da177e4
LT		 1785 .name = "Dell Optiplex GX260", /* AD1981A */
1786 .type = AC97_TUNE_HP_ONLY
1787 },
1788 {
6fd8b87f
JCD		 1789 .subvendor = 0x1028,
1790 .subdevice = 0x012c,
1da177e4
LT		 1791 .name = "Dell Precision 650", /* AD1981A */
1792 .type = AC97_TUNE_HP_ONLY
1793 },
1794 {
6fd8b87f
JCD		 1795 .subvendor = 0x1028,
1796 .subdevice = 0x012d,
1da177e4
LT		 1797 .name = "Dell Precision 450", /* AD1981B*/
1798 .type = AC97_TUNE_HP_ONLY
1799 },
1800 {
6fd8b87f
JCD		 1801 .subvendor = 0x1028,
1802 .subdevice = 0x0147,
1da177e4
LT		 1803 .name = "Dell", /* which model? AD1981B*/
1804 .type = AC97_TUNE_HP_ONLY
1805 },
1806 {
6fd8b87f
JCD		 1807 .subvendor = 0x1028,
1808 .subdevice = 0x0163,
1da177e4
LT		 1809 .name = "Dell Unknown", /* STAC9750/51 */
1810 .type = AC97_TUNE_HP_ONLY
1811 },
6d6f9156
KL		 1812 {
1813 .subvendor = 0x1028,
1814 .subdevice = 0x0191,
1815 .name = "Dell Inspiron 8600",
1816 .type = AC97_TUNE_HP_ONLY
1817 },
1da177e4 1818 {
6fd8b87f
JCD		 1819 .subvendor = 0x103c,
1820 .subdevice = 0x006d,
1da177e4
LT		 1821 .name = "HP zv5000",
1822 .type = AC97_TUNE_MUTE_LED /*AD1981B*/
1823 },
1824 { /* FIXME: which codec? */
6fd8b87f
JCD		 1825 .subvendor = 0x103c,
1826 .subdevice = 0x00c3,
1da177e4
LT		 1827 .name = "HP xw6000",
1828 .type = AC97_TUNE_HP_ONLY
1829 },
1830 {
6fd8b87f
JCD		 1831 .subvendor = 0x103c,
1832 .subdevice = 0x088c,
1da177e4
LT		 1833 .name = "HP nc8000",
1834 .type = AC97_TUNE_MUTE_LED
1835 },
1836 {
6fd8b87f
JCD		 1837 .subvendor = 0x103c,
1838 .subdevice = 0x0890,
1da177e4
LT		 1839 .name = "HP nc6000",
1840 .type = AC97_TUNE_MUTE_LED
1841 },
e0c93cf3
DH		 1842 {
1843 .subvendor = 0x103c,
1844 .subdevice = 0x0934,
1845 .name = "HP nx8220",
1846 .type = AC97_TUNE_MUTE_LED
1847 },
66d10647
SV		 1848 {
1849 .subvendor = 0x103c,
1850 .subdevice = 0x099c,
1851 .name = "HP nx6110", /* AD1981B */
1852 .type = AC97_TUNE_HP_ONLY
1853 },
1da177e4 1854 {
6fd8b87f
JCD		 1855 .subvendor = 0x103c,
1856 .subdevice = 0x129d,
1da177e4
LT		 1857 .name = "HP xw8000",
1858 .type = AC97_TUNE_HP_ONLY
1859 },
1860 {
6fd8b87f
JCD		 1861 .subvendor = 0x103c,
1862 .subdevice = 0x12f1,
1da177e4
LT		 1863 .name = "HP xw8200", /* AD1981B*/
1864 .type = AC97_TUNE_HP_ONLY
1865 },
1866 {
6fd8b87f
JCD		 1867 .subvendor = 0x103c,
1868 .subdevice = 0x12f2,
1da177e4
LT		 1869 .name = "HP xw6200",
1870 .type = AC97_TUNE_HP_ONLY
1871 },
1872 {
6fd8b87f
JCD		 1873 .subvendor = 0x103c,
1874 .subdevice = 0x3008,
1da177e4
LT		 1875 .name = "HP xw4200", /* AD1981B*/
1876 .type = AC97_TUNE_HP_ONLY
1877 },
1878 {
6fd8b87f
JCD		 1879 .subvendor = 0x104d,
1880 .subdevice = 0x8197,
1da177e4
LT		 1881 .name = "Sony S1XP",
1882 .type = AC97_TUNE_INV_EAPD
1883 },
1884 {
6fd8b87f
JCD		 1885 .subvendor = 0x1043,
1886 .subdevice = 0x80f3,
1da177e4
LT		 1887 .name = "ASUS ICH5/AD1985",
1888 .type = AC97_TUNE_AD_SHARING
1889 },
1890 {
6fd8b87f
JCD		 1891 .subvendor = 0x10cf,
1892 .subdevice = 0x11c3,
1da177e4
LT		 1893 .name = "Fujitsu-Siemens E4010",
1894 .type = AC97_TUNE_HP_ONLY
1895 },
98c7f212
TI		 1896 {
1897 .subvendor = 0x10cf,
1898 .subdevice = 0x1225,
1899 .name = "Fujitsu-Siemens T3010",
1900 .type = AC97_TUNE_HP_ONLY
1901 },
1da177e4 1902 {
6fd8b87f
JCD		 1903 .subvendor = 0x10cf,
1904 .subdevice = 0x1253,
1da177e4
LT		 1905 .name = "Fujitsu S6210", /* STAC9750/51 */
1906 .type = AC97_TUNE_HP_ONLY
1907 },
9970dce5
TI		 1908 {
1909 .subvendor = 0x10cf,
1910 .subdevice = 0x12ec,
1911 .name = "Fujitsu-Siemens 4010",
1912 .type = AC97_TUNE_HP_ONLY
1913 },
2eb061f4
JK		 1914 {
1915 .subvendor = 0x10cf,
1916 .subdevice = 0x12f2,
1917 .name = "Fujitsu-Siemens Celsius H320",
1918 .type = AC97_TUNE_SWAP_HP
1919 },
1da177e4 1920 {
6fd8b87f
JCD		 1921 .subvendor = 0x10f1,
1922 .subdevice = 0x2665,
1da177e4
LT		 1923 .name = "Fujitsu-Siemens Celsius", /* AD1981? */
1924 .type = AC97_TUNE_HP_ONLY
1925 },
1926 {
6fd8b87f
JCD		 1927 .subvendor = 0x10f1,
1928 .subdevice = 0x2885,
1da177e4
LT		 1929 .name = "AMD64 Mobo", /* ALC650 */
1930 .type = AC97_TUNE_HP_ONLY
1931 },
1932 {
6fd8b87f
JCD		 1933 .subvendor = 0x110a,
1934 .subdevice = 0x0056,
1da177e4
LT		 1935 .name = "Fujitsu-Siemens Scenic", /* AD1981? */
1936 .type = AC97_TUNE_HP_ONLY
1937 },
1938 {
6fd8b87f
JCD		 1939 .subvendor = 0x11d4,
1940 .subdevice = 0x5375,
1da177e4
LT		 1941 .name = "ADI AD1985 (discrete)",
1942 .type = AC97_TUNE_HP_ONLY
1943 },
1944 {
6fd8b87f
JCD		 1945 .subvendor = 0x1462,
1946 .subdevice = 0x5470,
1da177e4
LT		 1947 .name = "MSI P4 ATX 645 Ultra",
1948 .type = AC97_TUNE_HP_ONLY
1949 },
1950 {
6fd8b87f
JCD		 1951 .subvendor = 0x1734,
1952 .subdevice = 0x0088,
1da177e4
LT		 1953 .name = "Fujitsu-Siemens D1522", /* AD1981 */
1954 .type = AC97_TUNE_HP_ONLY
1955 },
1956 {
6fd8b87f
JCD		 1957 .subvendor = 0x8086,
1958 .subdevice = 0x2000,
1da177e4
LT		 1959 .mask = 0xfff0,
1960 .name = "Intel ICH5/AD1985",
1961 .type = AC97_TUNE_AD_SHARING
1962 },
1963 {
6fd8b87f
JCD		 1964 .subvendor = 0x8086,
1965 .subdevice = 0x4000,
1da177e4
LT		 1966 .mask = 0xfff0,
1967 .name = "Intel ICH5/AD1985",
1968 .type = AC97_TUNE_AD_SHARING
1969 },
1970 {
6fd8b87f
JCD		 1971 .subvendor = 0x8086,
1972 .subdevice = 0x4856,
1da177e4
LT		 1973 .name = "Intel D845WN (82801BA)",
1974 .type = AC97_TUNE_SWAP_HP
1975 },
1976 {
6fd8b87f
JCD		 1977 .subvendor = 0x8086,
1978 .subdevice = 0x4d44,
1da177e4
LT		 1979 .name = "Intel D850EMV2", /* AD1885 */
1980 .type = AC97_TUNE_HP_ONLY
1981 },
1982 {
6fd8b87f
JCD		 1983 .subvendor = 0x8086,
1984 .subdevice = 0x4d56,
1da177e4
LT		 1985 .name = "Intel ICH/AD1885",
1986 .type = AC97_TUNE_HP_ONLY
1987 },
1988 {
6fd8b87f
JCD		 1989 .subvendor = 0x8086,
1990 .subdevice = 0x6000,
1da177e4
LT		 1991 .mask = 0xfff0,
1992 .name = "Intel ICH5/AD1985",
1993 .type = AC97_TUNE_AD_SHARING
1994 },
1995 {
6fd8b87f
JCD		 1996 .subvendor = 0x8086,
1997 .subdevice = 0xe000,
1da177e4
LT		 1998 .mask = 0xfff0,
1999 .name = "Intel ICH5/AD1985",
2000 .type = AC97_TUNE_AD_SHARING
2001 },
2002#if 0 /* FIXME: this seems wrong on most boards */
2003 {
6fd8b87f
JCD		 2004 .subvendor = 0x8086,
2005 .subdevice = 0xa000,
1da177e4
LT		 2006 .mask = 0xfff0,
2007 .name = "Intel ICH5/AD1985",
2008 .type = AC97_TUNE_HP_ONLY
2009 },
2010#endif
2011 { } /* terminator */
2012};
2013
6b75a9d8
TI		 2014static int __devinit snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
2015 const char *quirk_override)
1da177e4 2016{
6b75a9d8
TI		 2017 struct snd_ac97_bus *pbus;
2018 struct snd_ac97_template ac97;
1da177e4
LT		 2019 int err;
2020 unsigned int i, codecs;
2021 unsigned int glob_sta = 0;
6b75a9d8
TI		 2022 struct snd_ac97_bus_ops *ops;
2023 static struct snd_ac97_bus_ops standard_bus_ops = {
1da177e4
LT		 2024 .write = snd_intel8x0_codec_write,
2025 .read = snd_intel8x0_codec_read,
2026 };
6b75a9d8 2027 static struct snd_ac97_bus_ops ali_bus_ops = {
1da177e4
LT		 2028 .write = snd_intel8x0_ali_codec_write,
2029 .read = snd_intel8x0_ali_codec_read,
2030 };
2031
2032 chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
2033 switch (chip->device_type) {
2034 case DEVICE_NFORCE:
2035 chip->spdif_idx = NVD_SPBAR;
2036 break;
2037 case DEVICE_ALI:
2038 chip->spdif_idx = ALID_AC97SPDIFOUT;
2039 break;
2040 case DEVICE_INTEL_ICH4:
2041 chip->spdif_idx = ICHD_SPBAR;
2042 break;
2043 };
2044
2045 chip->in_ac97_init = 1;
2046
2047 memset(&ac97, 0, sizeof(ac97));
2048 ac97.private_data = chip;
2049 ac97.private_free = snd_intel8x0_mixer_free_ac97;
2050 ac97.scaps = AC97_SCAP_SKIP_MODEM;
2051 if (chip->xbox)
2052 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
2053 if (chip->device_type != DEVICE_ALI) {
2054 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
2055 ops = &standard_bus_ops;
2056 if (chip->device_type == DEVICE_INTEL_ICH4) {
2057 codecs = 0;
2058 if (glob_sta & ICH_PCR)
2059 codecs++;
2060 if (glob_sta & ICH_SCR)
2061 codecs++;
2062 if (glob_sta & ICH_TCR)
2063 codecs++;
2064 chip->in_sdin_init = 1;
2065 for (i = 0; i < codecs; i++) {
2066 snd_intel8x0_codec_read_test(chip, i);
2067 chip->ac97_sdin[i] = igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2068 }
2069 chip->in_sdin_init = 0;
2070 } else {
2071 codecs = glob_sta & ICH_SCR ? 2 : 1;
2072 }
2073 } else {
2074 ops = &ali_bus_ops;
2075 codecs = 1;
2076 /* detect the secondary codec */
2077 for (i = 0; i < 100; i++) {
2078 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2079 if (reg & 0x40) {
2080 codecs = 2;
2081 break;
2082 }
2083 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2084 udelay(1);
2085 }
2086 }
2087 if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2088 goto __err;
2089 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
1da177e4
LT		 2090 if (ac97_clock >= 8000 && ac97_clock <= 48000)
2091 pbus->clock = ac97_clock;
2092 /* FIXME: my test board doesn't work well with VRA... */
2093 if (chip->device_type == DEVICE_ALI)
2094 pbus->no_vra = 1;
2095 else
2096 pbus->dra = 1;
2097 chip->ac97_bus = pbus;
2098
2099 ac97.pci = chip->pci;
2100 for (i = 0; i < codecs; i++) {
2101 ac97.num = i;
2102 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2103 if (err != -EACCES)
2104 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);
2105 if (i == 0)
2106 goto __err;
2107 continue;
2108 }
2109 }
2110 /* tune up the primary codec */
2111 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2112 /* enable separate SDINs for ICH4 */
2113 if (chip->device_type == DEVICE_INTEL_ICH4)
2114 pbus->isdin = 1;
2115 /* find the available PCM streams */
2116 i = ARRAY_SIZE(ac97_pcm_defs);
2117 if (chip->device_type != DEVICE_INTEL_ICH4)
2118 i -= 2; /* do not allocate PCM2IN and MIC2 */
2119 if (chip->spdif_idx < 0)
2120 i--; /* do not allocate S/PDIF */
2121 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2122 if (err < 0)
2123 goto __err;
2124 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2125 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2126 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2127 if (chip->spdif_idx >= 0)
2128 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2129 if (chip->device_type == DEVICE_INTEL_ICH4) {
2130 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2131 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2132 }
2133 /* enable separate SDINs for ICH4 */
2134 if (chip->device_type == DEVICE_INTEL_ICH4) {
2135 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2136 u8 tmp = igetbyte(chip, ICHREG(SDM));
2137 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2138 if (pcm) {
2139 tmp |= ICH_SE; /* steer enable for multiple SDINs */
2140 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2141 for (i = 1; i < 4; i++) {
2142 if (pcm->r[0].codec[i]) {
2143 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2144 break;
2145 }
2146 }
2147 } else {
2148 tmp &= ~ICH_SE; /* steer disable */
2149 }
2150 iputbyte(chip, ICHREG(SDM), tmp);
2151 }
2152 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2153 chip->multi4 = 1;
2154 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE))
2155 chip->multi6 = 1;
2156 }
2157 if (pbus->pcms[0].r[1].rslots[0]) {
2158 chip->dra = 1;
2159 }
2160 if (chip->device_type == DEVICE_INTEL_ICH4) {
2161 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2162 chip->smp20bit = 1;
2163 }
2164 if (chip->device_type == DEVICE_NFORCE) {
2165 /* 48kHz only */
2166 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2167 }
2168 if (chip->device_type == DEVICE_INTEL_ICH4) {
2169 /* use slot 10/11 for SPDIF */
2170 u32 val;
2171 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2172 val |= ICH_PCM_SPDIF_1011;
2173 iputdword(chip, ICHREG(GLOB_CNT), val);
2174 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2175 }
2176 chip->in_ac97_init = 0;
2177 return 0;
2178
2179 __err:
2180 /* clear the cold-reset bit for the next chance */
2181 if (chip->device_type != DEVICE_ALI)
6b75a9d8
TI		 2182 iputdword(chip, ICHREG(GLOB_CNT),
2183 igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
1da177e4
LT		 2184 return err;
2185}
2186
2187
2188/*
2189 *
2190 */
2191
6b75a9d8 2192static void do_ali_reset(struct intel8x0 *chip)
1da177e4
LT		 2193{
2194 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2195 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2196 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2197 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2198 iputdword(chip, ICHREG(ALI_INTERFACECR),
d78bec21 2199 ICH_ALI_IF_PI|ICH_ALI_IF_PO);
1da177e4
LT		 2200 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2201 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2202}
2203
6b75a9d8 2204static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
1da177e4
LT		 2205{
2206 unsigned long end_time;
2207 unsigned int cnt, status, nstatus;
2208
2209 /* put logic to right state */
2210 /* first clear status bits */
2211 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2212 if (chip->device_type == DEVICE_NFORCE)
2213 status |= ICH_NVSPINT;
2214 cnt = igetdword(chip, ICHREG(GLOB_STA));
2215 iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2216
2217 /* ACLink on, 2 channels */
2218 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2219 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2220 /* finish cold or do warm reset */
2221 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2222 iputdword(chip, ICHREG(GLOB_CNT), cnt);
2223 end_time = (jiffies + (HZ / 4)) + 1;
2224 do {
2225 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2226 goto __ok;
954bea35 2227 schedule_timeout_uninterruptible(1);
1da177e4 2228 } while (time_after_eq(end_time, jiffies));
6b75a9d8
TI		 2229 snd_printk(KERN_ERR "AC'97 warm reset still in progress? [0x%x]\n",
2230 igetdword(chip, ICHREG(GLOB_CNT)));
1da177e4
LT		 2231 return -EIO;
2232
2233 __ok:
2234 if (probing) {
2235 /* wait for any codec ready status.
2236 * Once it becomes ready it should remain ready
2237 * as long as we do not disable the ac97 link.
2238 */
2239 end_time = jiffies + HZ;
2240 do {
6b75a9d8
TI		 2241 status = igetdword(chip, ICHREG(GLOB_STA)) &
2242 (ICH_PCR | ICH_SCR | ICH_TCR);
1da177e4
LT		 2243 if (status)
2244 break;
954bea35 2245 schedule_timeout_uninterruptible(1);
1da177e4
LT		 2246 } while (time_after_eq(end_time, jiffies));
2247 if (! status) {
2248 /* no codec is found */
6b75a9d8
TI		 2249 snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n",
2250 igetdword(chip, ICHREG(GLOB_STA)));
1da177e4
LT		 2251 return -EIO;
2252 }
2253
2254 if (chip->device_type == DEVICE_INTEL_ICH4)
2255 /* ICH4 can have three codecs */
2256 nstatus = ICH_PCR | ICH_SCR | ICH_TCR;
2257 else
2258 /* others up to two codecs */
2259 nstatus = ICH_PCR | ICH_SCR;
2260
2261 /* wait for other codecs ready status. */
2262 end_time = jiffies + HZ / 4;
2263 while (status != nstatus && time_after_eq(end_time, jiffies)) {
954bea35 2264 schedule_timeout_uninterruptible(1);
1da177e4
LT		 2265 status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus;
2266 }
2267
2268 } else {
2269 /* resume phase */
2270 int i;
2271 status = 0;
2272 for (i = 0; i < 3; i++)
2273 if (chip->ac97[i])
2274 status |= get_ich_codec_bit(chip, i);
2275 /* wait until all the probed codecs are ready */
2276 end_time = jiffies + HZ;
2277 do {
6b75a9d8
TI		 2278 nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
2279 (ICH_PCR | ICH_SCR | ICH_TCR);
1da177e4
LT		 2280 if (status == nstatus)
2281 break;
954bea35 2282 schedule_timeout_uninterruptible(1);
1da177e4
LT		 2283 } while (time_after_eq(end_time, jiffies));
2284 }
2285
2286 if (chip->device_type == DEVICE_SIS) {
2287 /* unmute the output on SIS7012 */
2288 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2289 }
2290 if (chip->device_type == DEVICE_NFORCE) {
2291 /* enable SPDIF interrupt */
2292 unsigned int val;
2293 pci_read_config_dword(chip->pci, 0x4c, &val);
2294 val |= 0x1000000;
2295 pci_write_config_dword(chip->pci, 0x4c, val);
2296 }
2297 return 0;
2298}
2299
6b75a9d8 2300static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
1da177e4
LT		 2301{
2302 u32 reg;
2303 int i = 0;
2304
2305 reg = igetdword(chip, ICHREG(ALI_SCR));
2306 if ((reg & 2) == 0) /* Cold required */
2307 reg |= 2;
2308 else
2309 reg |= 1; /* Warm */
2310 reg &= ~0x80000000; /* ACLink on */
2311 iputdword(chip, ICHREG(ALI_SCR), reg);
2312
2313 for (i = 0; i < HZ / 2; i++) {
2314 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2315 goto __ok;
954bea35 2316 schedule_timeout_uninterruptible(1);
1da177e4
LT		 2317 }
2318 snd_printk(KERN_ERR "AC'97 reset failed.\n");
2319 if (probing)
2320 return -EIO;
2321
2322 __ok:
2323 for (i = 0; i < HZ / 2; i++) {
2324 reg = igetdword(chip, ICHREG(ALI_RTSR));
2325 if (reg & 0x80) /* primary codec */
2326 break;
2327 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
954bea35 2328 schedule_timeout_uninterruptible(1);
1da177e4
LT		 2329 }
2330
2331 do_ali_reset(chip);
2332 return 0;
2333}
2334
6b75a9d8 2335static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
1da177e4
LT		 2336{
2337 unsigned int i;
2338 int err;
2339
2340 if (chip->device_type != DEVICE_ALI) {
2341 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2342 return err;
2343 iagetword(chip, 0); /* clear semaphore flag */
2344 } else {
2345 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2346 return err;
2347 }
2348
2349 /* disable interrupts */
2350 for (i = 0; i < chip->bdbars_count; i++)
2351 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2352 /* reset channels */
2353 for (i = 0; i < chip->bdbars_count; i++)
2354 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2355 /* initialize Buffer Descriptor Lists */
2356 for (i = 0; i < chip->bdbars_count; i++)
6b75a9d8
TI		 2357 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
2358 chip->ichd[i].bdbar_addr);
1da177e4
LT		 2359 return 0;
2360}
2361
6b75a9d8 2362static int snd_intel8x0_free(struct intel8x0 *chip)
1da177e4
LT		 2363{
2364 unsigned int i;
2365
2366 if (chip->irq < 0)
2367 goto __hw_end;
2368 /* disable interrupts */
2369 for (i = 0; i < chip->bdbars_count; i++)
2370 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2371 /* reset channels */
2372 for (i = 0; i < chip->bdbars_count; i++)
2373 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2374 if (chip->device_type == DEVICE_NFORCE) {
2375 /* stop the spdif interrupt */
2376 unsigned int val;
2377 pci_read_config_dword(chip->pci, 0x4c, &val);
2378 val &= ~0x1000000;
2379 pci_write_config_dword(chip->pci, 0x4c, val);
2380 }
2381 /* --- */
2382 synchronize_irq(chip->irq);
2383 __hw_end:
2384 if (chip->irq >= 0)
6b75a9d8 2385 free_irq(chip->irq, chip);
1da177e4
LT		 2386 if (chip->bdbars.area) {
2387 if (chip->fix_nocache)
2388 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
2389 snd_dma_free_pages(&chip->bdbars);
2390 }
2391 if (chip->remap_addr)
2392 iounmap(chip->remap_addr);
2393 if (chip->remap_bmaddr)
2394 iounmap(chip->remap_bmaddr);
2395 pci_release_regions(chip->pci);
2396 pci_disable_device(chip->pci);
2397 kfree(chip);
2398 return 0;
2399}
2400
2401#ifdef CONFIG_PM
2402/*
2403 * power management
2404 */
5809c6c4 2405static int intel8x0_suspend(struct pci_dev *pci, pm_message_t state)
1da177e4 2406{
5809c6c4
TI		 2407 struct snd_card *card = pci_get_drvdata(pci);
2408 struct intel8x0 *chip = card->private_data;
1da177e4
LT		 2409 int i;
2410
5809c6c4 2411 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1da177e4
LT		 2412 for (i = 0; i < chip->pcm_devs; i++)
2413 snd_pcm_suspend_all(chip->pcm[i]);
2414 /* clear nocache */
2415 if (chip->fix_nocache) {
2416 for (i = 0; i < chip->bdbars_count; i++) {
6b75a9d8 2417 struct ichdev *ichdev = &chip->ichd[i];
1da177e4 2418 if (ichdev->substream && ichdev->page_attr_changed) {
6b75a9d8 2419 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
1da177e4
LT		 2420 if (runtime->dma_area)
2421 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0);
2422 }
2423 }
2424 }
2425 for (i = 0; i < 3; i++)
5809c6c4 2426 snd_ac97_suspend(chip->ac97[i]);
52b72388
TI		 2427 if (chip->device_type == DEVICE_INTEL_ICH4)
2428 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
adbedd34 2429
90158b83 2430 if (chip->irq >= 0)
6b75a9d8 2431 free_irq(chip->irq, chip);
5809c6c4
TI		 2432 pci_disable_device(pci);
2433 pci_save_state(pci);
1da177e4
LT		 2434 return 0;
2435}
2436
5809c6c4 2437static int intel8x0_resume(struct pci_dev *pci)
1da177e4 2438{
5809c6c4
TI		 2439 struct snd_card *card = pci_get_drvdata(pci);
2440 struct intel8x0 *chip = card->private_data;
1da177e4
LT		 2441 int i;
2442
5809c6c4
TI		 2443 pci_restore_state(pci);
2444 pci_enable_device(pci);
2445 pci_set_master(pci);
2446 request_irq(pci->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ,
6b75a9d8 2447 card->shortname, chip);
5809c6c4 2448 chip->irq = pci->irq;
90158b83
RW		 2449 synchronize_irq(chip->irq);
2450 snd_intel8x0_chip_init(chip, 1);
1da177e4 2451
52b72388
TI		 2452 /* re-initialize mixer stuff */
2453 if (chip->device_type == DEVICE_INTEL_ICH4) {
2454 /* enable separate SDINs for ICH4 */
2455 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2456 /* use slot 10/11 for SPDIF */
2457 iputdword(chip, ICHREG(GLOB_CNT),
2458 (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2459 ICH_PCM_SPDIF_1011);
2460 }
2461
1da177e4
LT		 2462 /* refill nocache */
2463 if (chip->fix_nocache)
2464 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2465
2466 for (i = 0; i < 3; i++)
5809c6c4 2467 snd_ac97_resume(chip->ac97[i]);
1da177e4
LT		 2468
2469 /* refill nocache */
2470 if (chip->fix_nocache) {
2471 for (i = 0; i < chip->bdbars_count; i++) {
6b75a9d8 2472 struct ichdev *ichdev = &chip->ichd[i];
1da177e4 2473 if (ichdev->substream && ichdev->page_attr_changed) {
6b75a9d8 2474 struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
1da177e4
LT		 2475 if (runtime->dma_area)
2476 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
2477 }
2478 }
2479 }
2480
1cfe43d2
TI		 2481 /* resume status */
2482 for (i = 0; i < chip->bdbars_count; i++) {
6b75a9d8 2483 struct ichdev *ichdev = &chip->ichd[i];
1cfe43d2
TI		 2484 unsigned long port = ichdev->reg_offset;
2485 if (! ichdev->substream || ! ichdev->suspended)
2486 continue;
2487 if (ichdev->ichd == ICHD_PCMOUT)
2488 snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2489 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2490 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2491 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2492 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2493 }
2494
5809c6c4 2495 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1da177e4
LT		 2496 return 0;
2497}
2498#endif /* CONFIG_PM */
2499
2500#define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */
2501
6b75a9d8 2502static void __devinit intel8x0_measure_ac97_clock(struct intel8x0 *chip)
1da177e4 2503{
6b75a9d8
TI		 2504 struct snd_pcm_substream *subs;
2505 struct ichdev *ichdev;
1da177e4
LT		 2506 unsigned long port;
2507 unsigned long pos, t;
2508 struct timeval start_time, stop_time;
2509
2510 if (chip->ac97_bus->clock != 48000)
2511 return; /* specified in module option */
2512
2513 subs = chip->pcm[0]->streams[0].substream;
2514 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
99b359ba 2515 snd_printk(KERN_WARNING "no playback buffer allocated - aborting measure ac97 clock\n");
1da177e4
LT		 2516 return;
2517 }
2518 ichdev = &chip->ichd[ICHD_PCMOUT];
2519 ichdev->physbuf = subs->dma_buffer.addr;
2520 ichdev->size = chip->ichd[ICHD_PCMOUT].fragsize = INTEL8X0_TESTBUF_SIZE;
2521 ichdev->substream = NULL; /* don't process interrupts */
2522
2523 /* set rate */
2524 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2525 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock);
2526 return;
2527 }
2528 snd_intel8x0_setup_periods(chip, ichdev);
2529 port = ichdev->reg_offset;
2530 spin_lock_irq(&chip->reg_lock);
2531 chip->in_measurement = 1;
2532 /* trigger */
2533 if (chip->device_type != DEVICE_ALI)
2534 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2535 else {
2536 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2537 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2538 }
2539 do_gettimeofday(&start_time);
2540 spin_unlock_irq(&chip->reg_lock);
ef21ca24 2541 msleep(50);
1da177e4
LT		 2542 spin_lock_irq(&chip->reg_lock);
2543 /* check the position */
2544 pos = ichdev->fragsize1;
2545 pos -= igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << ichdev->pos_shift;
2546 pos += ichdev->position;
2547 chip->in_measurement = 0;
2548 do_gettimeofday(&stop_time);
2549 /* stop */
2550 if (chip->device_type == DEVICE_ALI) {
d78bec21 2551 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
1da177e4
LT		 2552 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2553 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2554 ;
2555 } else {
2556 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2557 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2558 ;
2559 }
2560 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2561 spin_unlock_irq(&chip->reg_lock);
2562
2563 t = stop_time.tv_sec - start_time.tv_sec;
2564 t *= 1000000;
2565 t += stop_time.tv_usec - start_time.tv_usec;
2566 printk(KERN_INFO "%s: measured %lu usecs\n", __FUNCTION__, t);
2567 if (t == 0) {
2568 snd_printk(KERN_ERR "?? calculation error..\n");
2569 return;
2570 }
2571 pos = (pos / 4) * 1000;
2572 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2573 if (pos < 40000 || pos >= 60000)
2574 /* abnormal value. hw problem? */
2575 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos);
2576 else if (pos < 47500 || pos > 48500)
2577 /* not 48000Hz, tuning the clock.. */
2578 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2579 printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
2580}
2581
adf1b3d2 2582#ifdef CONFIG_PROC_FS
6b75a9d8
TI		 2583static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
2584 struct snd_info_buffer *buffer)
1da177e4 2585{
6b75a9d8 2586 struct intel8x0 *chip = entry->private_data;
1da177e4
LT		 2587 unsigned int tmp;
2588
2589 snd_iprintf(buffer, "Intel8x0\n\n");
2590 if (chip->device_type == DEVICE_ALI)
2591 return;
2592 tmp = igetdword(chip, ICHREG(GLOB_STA));
2593 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2594 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
2595 if (chip->device_type == DEVICE_INTEL_ICH4)
2596 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2597 snd_iprintf(buffer, "AC'97 codecs ready :%s%s%s%s\n",
2598 tmp & ICH_PCR ? " primary" : "",
2599 tmp & ICH_SCR ? " secondary" : "",
2600 tmp & ICH_TCR ? " tertiary" : "",
2601 (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : "");
2602 if (chip->device_type == DEVICE_INTEL_ICH4)
2603 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n",
2604 chip->ac97_sdin[0],
2605 chip->ac97_sdin[1],
2606 chip->ac97_sdin[2]);
2607}
2608
6b75a9d8 2609static void __devinit snd_intel8x0_proc_init(struct intel8x0 * chip)
1da177e4 2610{
6b75a9d8 2611 struct snd_info_entry *entry;
1da177e4
LT		 2612
2613 if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
2614 snd_info_set_text_ops(entry, chip, 1024, snd_intel8x0_proc_read);
2615}
adf1b3d2
TI		 2616#else
2617#define snd_intel8x0_proc_init(x)
2618#endif
1da177e4 2619
6b75a9d8 2620static int snd_intel8x0_dev_free(struct snd_device *device)
1da177e4 2621{
6b75a9d8 2622 struct intel8x0 *chip = device->device_data;
1da177e4
LT		 2623 return snd_intel8x0_free(chip);
2624}
2625
2626struct ich_reg_info {
2627 unsigned int int_sta_mask;
2628 unsigned int offset;
2629};
2630
6b75a9d8 2631static int __devinit snd_intel8x0_create(struct snd_card *card,
1da177e4
LT		 2632 struct pci_dev *pci,
2633 unsigned long device_type,
6b75a9d8 2634 struct intel8x0 ** r_intel8x0)
1da177e4 2635{
6b75a9d8 2636 struct intel8x0 *chip;
1da177e4
LT		 2637 int err;
2638 unsigned int i;
2639 unsigned int int_sta_masks;
6b75a9d8
TI		 2640 struct ichdev *ichdev;
2641 static struct snd_device_ops ops = {
1da177e4
LT		 2642 .dev_free = snd_intel8x0_dev_free,
2643 };
2644
2645 static unsigned int bdbars[] = {
2646 3, /* DEVICE_INTEL */
2647 6, /* DEVICE_INTEL_ICH4 */
2648 3, /* DEVICE_SIS */
2649 6, /* DEVICE_ALI */
2650 4, /* DEVICE_NFORCE */
2651 };
2652 static struct ich_reg_info intel_regs[6] = {
2653 { ICH_PIINT, 0 },
2654 { ICH_POINT, 0x10 },
2655 { ICH_MCINT, 0x20 },
2656 { ICH_M2INT, 0x40 },
2657 { ICH_P2INT, 0x50 },
2658 { ICH_SPINT, 0x60 },
2659 };
2660 static struct ich_reg_info nforce_regs[4] = {
2661 { ICH_PIINT, 0 },
2662 { ICH_POINT, 0x10 },
2663 { ICH_MCINT, 0x20 },
2664 { ICH_NVSPINT, 0x70 },
2665 };
2666 static struct ich_reg_info ali_regs[6] = {
2667 { ALI_INT_PCMIN, 0x40 },
2668 { ALI_INT_PCMOUT, 0x50 },
2669 { ALI_INT_MICIN, 0x60 },
2670 { ALI_INT_CODECSPDIFOUT, 0x70 },
2671 { ALI_INT_SPDIFIN, 0xa0 },
2672 { ALI_INT_SPDIFOUT, 0xb0 },
2673 };
2674 struct ich_reg_info *tbl;
2675
2676 *r_intel8x0 = NULL;
2677
2678 if ((err = pci_enable_device(pci)) < 0)
2679 return err;
2680
e560d8d8 2681 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1da177e4
LT		 2682 if (chip == NULL) {
2683 pci_disable_device(pci);
2684 return -ENOMEM;
2685 }
2686 spin_lock_init(&chip->reg_lock);
2687 chip->device_type = device_type;
2688 chip->card = card;
2689 chip->pci = pci;
2690 chip->irq = -1;
c829b052
TI		 2691
2692 /* module parameters */
2693 chip->buggy_irq = buggy_irq;
2694 chip->buggy_semaphore = buggy_semaphore;
2695 if (xbox)
2696 chip->xbox = 1;
1da177e4
LT		 2697
2698 if (pci->vendor == PCI_VENDOR_ID_INTEL &&
2699 pci->device == PCI_DEVICE_ID_INTEL_440MX)
2700 chip->fix_nocache = 1; /* enable workaround */
2701
1da177e4
LT		 2702 if ((err = pci_request_regions(pci, card->shortname)) < 0) {
2703 kfree(chip);
2704 pci_disable_device(pci);
2705 return err;
2706 }
2707
2708 if (device_type == DEVICE_ALI) {
2709 /* ALI5455 has no ac97 region */
2710 chip->bmaddr = pci_resource_start(pci, 0);
2711 goto port_inited;
2712 }
2713
2714 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) { /* ICH4 and Nforce */
2715 chip->mmio = 1;
2716 chip->addr = pci_resource_start(pci, 2);
2717 chip->remap_addr = ioremap_nocache(chip->addr,
2718 pci_resource_len(pci, 2));
2719 if (chip->remap_addr == NULL) {
99b359ba 2720 snd_printk(KERN_ERR "AC'97 space ioremap problem\n");
1da177e4
LT		 2721 snd_intel8x0_free(chip);
2722 return -EIO;
2723 }
2724 } else {
2725 chip->addr = pci_resource_start(pci, 0);
2726 }
2727 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) { /* ICH4 */
2728 chip->bm_mmio = 1;
2729 chip->bmaddr = pci_resource_start(pci, 3);
2730 chip->remap_bmaddr = ioremap_nocache(chip->bmaddr,
2731 pci_resource_len(pci, 3));
2732 if (chip->remap_bmaddr == NULL) {
99b359ba 2733 snd_printk(KERN_ERR "Controller space ioremap problem\n");
1da177e4
LT		 2734 snd_intel8x0_free(chip);
2735 return -EIO;
2736 }
2737 } else {
2738 chip->bmaddr = pci_resource_start(pci, 1);
2739 }
2740
2741 port_inited:
1da177e4
LT		 2742 chip->bdbars_count = bdbars[device_type];
2743
2744 /* initialize offsets */
2745 switch (device_type) {
2746 case DEVICE_NFORCE:
2747 tbl = nforce_regs;
2748 break;
2749 case DEVICE_ALI:
2750 tbl = ali_regs;
2751 break;
2752 default:
2753 tbl = intel_regs;
2754 break;
2755 }
2756 for (i = 0; i < chip->bdbars_count; i++) {
2757 ichdev = &chip->ichd[i];
2758 ichdev->ichd = i;
2759 ichdev->reg_offset = tbl[i].offset;
2760 ichdev->int_sta_mask = tbl[i].int_sta_mask;
2761 if (device_type == DEVICE_SIS) {
2762 /* SiS 7012 swaps the registers */
2763 ichdev->roff_sr = ICH_REG_OFF_PICB;
2764 ichdev->roff_picb = ICH_REG_OFF_SR;
2765 } else {
2766 ichdev->roff_sr = ICH_REG_OFF_SR;
2767 ichdev->roff_picb = ICH_REG_OFF_PICB;
2768 }
2769 if (device_type == DEVICE_ALI)
2770 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
2771 /* SIS7012 handles the pcm data in bytes, others are in samples */
2772 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
2773 }
2774
2775 /* allocate buffer descriptor lists */
2776 /* the start of each lists must be aligned to 8 bytes */
2777 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
2778 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
2779 &chip->bdbars) < 0) {
2780 snd_intel8x0_free(chip);
2781 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n");
2782 return -ENOMEM;
2783 }
2784 /* tables must be aligned to 8 bytes here, but the kernel pages
2785 are much bigger, so we don't care (on i386) */
2786 /* workaround for 440MX */
2787 if (chip->fix_nocache)
2788 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2789 int_sta_masks = 0;
2790 for (i = 0; i < chip->bdbars_count; i++) {
2791 ichdev = &chip->ichd[i];
beef08a5
TI		 2792 ichdev->bdbar = ((u32 *)chip->bdbars.area) +
2793 (i * ICH_MAX_FRAGS * 2);
2794 ichdev->bdbar_addr = chip->bdbars.addr +
2795 (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
1da177e4
LT		 2796 int_sta_masks |= ichdev->int_sta_mask;
2797 }
beef08a5
TI		 2798 chip->int_sta_reg = device_type == DEVICE_ALI ?
2799 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
1da177e4
LT		 2800 chip->int_sta_mask = int_sta_masks;
2801
beef08a5
TI		 2802 /* request irq after initializaing int_sta_mask, etc */
2803 if (request_irq(pci->irq, snd_intel8x0_interrupt,
6b75a9d8 2804 SA_INTERRUPT|SA_SHIRQ, card->shortname, chip)) {
beef08a5
TI		 2805 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2806 snd_intel8x0_free(chip);
2807 return -EBUSY;
2808 }
2809 chip->irq = pci->irq;
2810 pci_set_master(pci);
2811 synchronize_irq(chip->irq);
2812
1da177e4
LT		 2813 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
2814 snd_intel8x0_free(chip);
2815 return err;
2816 }
2817
1da177e4
LT		 2818 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2819 snd_intel8x0_free(chip);
2820 return err;
2821 }
2822
2823 snd_card_set_dev(card, &pci->dev);
2824
2825 *r_intel8x0 = chip;
2826 return 0;
2827}
2828
2829static struct shortname_table {
2830 unsigned int id;
2831 const char *s;
2832} shortnames[] __devinitdata = {
8cdfd251
TI		 2833 { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
2834 { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
2835 { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
1da177e4 2836 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
8cdfd251
TI		 2837 { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
2838 { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
2839 { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
1da177e4
LT		 2840 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
2841 { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
2842 { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
3437c5df 2843 { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
1da177e4 2844 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
8cdfd251 2845 { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
1da177e4
LT		 2846 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
2847 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
2848 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
2849 { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
2850 { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
2851 { 0x003a, "NVidia MCP04" },
2852 { 0x746d, "AMD AMD8111" },
2853 { 0x7445, "AMD AMD768" },
2854 { 0x5455, "ALi M5455" },
2855 { 0, NULL },
2856};
2857
2858static int __devinit snd_intel8x0_probe(struct pci_dev *pci,
2859 const struct pci_device_id *pci_id)
2860{
6b75a9d8
TI		 2861 struct snd_card *card;
2862 struct intel8x0 *chip;
1da177e4
LT		 2863 int err;
2864 struct shortname_table *name;
2865
b7fe4622 2866 card = snd_card_new(index, id, THIS_MODULE, 0);
1da177e4
LT		 2867 if (card == NULL)
2868 return -ENOMEM;
2869
2870 switch (pci_id->driver_data) {
2871 case DEVICE_NFORCE:
2872 strcpy(card->driver, "NFORCE");
2873 break;
2874 case DEVICE_INTEL_ICH4:
2875 strcpy(card->driver, "ICH4");
2876 break;
2877 default:
2878 strcpy(card->driver, "ICH");
2879 break;
2880 }
2881
2882 strcpy(card->shortname, "Intel ICH");
2883 for (name = shortnames; name->id; name++) {
2884 if (pci->device == name->id) {
2885 strcpy(card->shortname, name->s);
2886 break;
2887 }
2888 }
2889
beef08a5
TI		 2890 if (buggy_irq < 0) {
2891 /* some Nforce[2] and ICH boards have problems with IRQ handling.
2892 * Needs to return IRQ_HANDLED for unknown irqs.
2893 */
2894 if (pci_id->driver_data == DEVICE_NFORCE)
2895 buggy_irq = 1;
2896 else
2897 buggy_irq = 0;
2898 }
2899
a06147d2 2900 if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data,
c829b052 2901 &chip)) < 0) {
1da177e4
LT		 2902 snd_card_free(card);
2903 return err;
2904 }
5809c6c4 2905 card->private_data = chip;
1da177e4 2906
b7fe4622 2907 if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) {
1da177e4
LT		 2908 snd_card_free(card);
2909 return err;
2910 }
2911 if ((err = snd_intel8x0_pcm(chip)) < 0) {
2912 snd_card_free(card);
2913 return err;
2914 }
2915
2916 snd_intel8x0_proc_init(chip);
2917
2918 snprintf(card->longname, sizeof(card->longname),
2919 "%s with %s at %#lx, irq %i", card->shortname,
2920 snd_ac97_get_short_name(chip->ac97[0]), chip->addr, chip->irq);
2921
b7fe4622 2922 if (! ac97_clock)
1da177e4
LT		 2923 intel8x0_measure_ac97_clock(chip);
2924
2925 if ((err = snd_card_register(card)) < 0) {
2926 snd_card_free(card);
2927 return err;
2928 }
2929 pci_set_drvdata(pci, card);
1da177e4
LT		 2930 return 0;
2931}
2932
2933static void __devexit snd_intel8x0_remove(struct pci_dev *pci)
2934{
2935 snd_card_free(pci_get_drvdata(pci));
2936 pci_set_drvdata(pci, NULL);
2937}
2938
2939static struct pci_driver driver = {
2940 .name = "Intel ICH",
2941 .id_table = snd_intel8x0_ids,
2942 .probe = snd_intel8x0_probe,
2943 .remove = __devexit_p(snd_intel8x0_remove),
5809c6c4
TI		 2944#ifdef CONFIG_PM
2945 .suspend = intel8x0_suspend,
2946 .resume = intel8x0_resume,
2947#endif
1da177e4
LT		 2948};
2949
2950
2951static int __init alsa_card_intel8x0_init(void)
2952{
01d25d46 2953 return pci_register_driver(&driver);
1da177e4
LT		 2954}
2955
2956static void __exit alsa_card_intel8x0_exit(void)
2957{
2958 pci_unregister_driver(&driver);
2959}
2960
2961module_init(alsa_card_intel8x0_init)
2962module_exit(alsa_card_intel8x0_exit)
Linux 6.x block layer and io_uring tree(s)