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[ALSA] Fix DocBook warnings
[linux-2.6-block.git] / sound / pci / intel8x0.c
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1da177e4
LT		 1/*
2 * ALSA driver for Intel ICH (i8x0) chipsets
3 *
4 * Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
5 *
6 *
7 * This code also contains alpha support for SiS 735 chipsets provided
8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
9 * for SiS735, so the code is not fully functional.
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25
26 *
27 */
28
29#include <sound/driver.h>
30#include <asm/io.h>
31#include <linux/delay.h>
32#include <linux/interrupt.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/slab.h>
36#include <linux/moduleparam.h>
37#include <sound/core.h>
38#include <sound/pcm.h>
39#include <sound/ac97_codec.h>
40#include <sound/info.h>
41#include <sound/initval.h>
42/* for 440MX workaround */
43#include <asm/pgtable.h>
44#include <asm/cacheflush.h>
45
46MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
47MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
48MODULE_LICENSE("GPL");
49MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
50 "{Intel,82901AB-ICH0},"
51 "{Intel,82801BA-ICH2},"
52 "{Intel,82801CA-ICH3},"
53 "{Intel,82801DB-ICH4},"
54 "{Intel,ICH5},"
55 "{Intel,ICH6},"
56 "{Intel,ICH7},"
57 "{Intel,6300ESB},"
c4c8ea94 58 "{Intel,ESB2},"
1da177e4
LT		 59 "{Intel,MX440},"
60 "{SiS,SI7012},"
61 "{NVidia,nForce Audio},"
62 "{NVidia,nForce2 Audio},"
63 "{AMD,AMD768},"
64 "{AMD,AMD8111},"
65 "{ALI,M5455}}");
66
67static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
68static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
69static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
70static int ac97_clock[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 0};
71static char *ac97_quirk[SNDRV_CARDS];
72static int buggy_irq[SNDRV_CARDS];
73static int xbox[SNDRV_CARDS];
74
75#ifdef SUPPORT_MIDI
76static int mpu_port[SNDRV_CARDS]; /* disabled */
77#endif
78
79module_param_array(index, int, NULL, 0444);
80MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
81module_param_array(id, charp, NULL, 0444);
82MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
83module_param_array(enable, bool, NULL, 0444);
84MODULE_PARM_DESC(enable, "Enable Intel i8x0 soundcard.");
85module_param_array(ac97_clock, int, NULL, 0444);
86MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
87module_param_array(ac97_quirk, charp, NULL, 0444);
88MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
89module_param_array(buggy_irq, bool, NULL, 0444);
90MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
91module_param_array(xbox, bool, NULL, 0444);
92MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
93
94/*
95 * Direct registers
96 */
97
98#ifndef PCI_DEVICE_ID_INTEL_82801
99#define PCI_DEVICE_ID_INTEL_82801 0x2415
100#endif
101#ifndef PCI_DEVICE_ID_INTEL_82901
102#define PCI_DEVICE_ID_INTEL_82901 0x2425
103#endif
104#ifndef PCI_DEVICE_ID_INTEL_82801BA
105#define PCI_DEVICE_ID_INTEL_82801BA 0x2445
106#endif
107#ifndef PCI_DEVICE_ID_INTEL_440MX
108#define PCI_DEVICE_ID_INTEL_440MX 0x7195
109#endif
110#ifndef PCI_DEVICE_ID_INTEL_ICH3
111#define PCI_DEVICE_ID_INTEL_ICH3 0x2485
112#endif
113#ifndef PCI_DEVICE_ID_INTEL_ICH4
114#define PCI_DEVICE_ID_INTEL_ICH4 0x24c5
115#endif
116#ifndef PCI_DEVICE_ID_INTEL_ICH5
117#define PCI_DEVICE_ID_INTEL_ICH5 0x24d5
118#endif
119#ifndef PCI_DEVICE_ID_INTEL_ESB_5
120#define PCI_DEVICE_ID_INTEL_ESB_5 0x25a6
121#endif
122#ifndef PCI_DEVICE_ID_INTEL_ICH6_18
123#define PCI_DEVICE_ID_INTEL_ICH6_18 0x266e
124#endif
125#ifndef PCI_DEVICE_ID_INTEL_ICH7_20
126#define PCI_DEVICE_ID_INTEL_ICH7_20 0x27de
127#endif
3437c5df
JG		 128#ifndef PCI_DEVICE_ID_INTEL_ESB2_14
129#define PCI_DEVICE_ID_INTEL_ESB2_14 0x2698
c4c8ea94 130#endif
1da177e4
LT		 131#ifndef PCI_DEVICE_ID_SI_7012
132#define PCI_DEVICE_ID_SI_7012 0x7012
133#endif
134#ifndef PCI_DEVICE_ID_NVIDIA_MCP_AUDIO
135#define PCI_DEVICE_ID_NVIDIA_MCP_AUDIO 0x01b1
136#endif
137#ifndef PCI_DEVICE_ID_NVIDIA_CK804_AUDIO
138#define PCI_DEVICE_ID_NVIDIA_CK804_AUDIO 0x0059
139#endif
140#ifndef PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO
141#define PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO 0x006a
142#endif
143#ifndef PCI_DEVICE_ID_NVIDIA_CK8_AUDIO
144#define PCI_DEVICE_ID_NVIDIA_CK8_AUDIO 0x008a
145#endif
146#ifndef PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO
147#define PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO 0x00da
148#endif
149#ifndef PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO
150#define PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO 0x00ea
151#endif
152
153enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
154
155#define ICHREG(x) ICH_REG_##x
156
157#define DEFINE_REGSET(name,base) \
158enum { \
159 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
160 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
161 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
162 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
163 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
164 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
165 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
166};
167
168/* busmaster blocks */
169DEFINE_REGSET(OFF, 0); /* offset */
170DEFINE_REGSET(PI, 0x00); /* PCM in */
171DEFINE_REGSET(PO, 0x10); /* PCM out */
172DEFINE_REGSET(MC, 0x20); /* Mic in */
173
174/* ICH4 busmaster blocks */
175DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */
176DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */
177DEFINE_REGSET(SP, 0x60); /* SPDIF out */
178
179/* values for each busmaster block */
180
181/* LVI */
182#define ICH_REG_LVI_MASK 0x1f
183
184/* SR */
185#define ICH_FIFOE 0x10 /* FIFO error */
186#define ICH_BCIS 0x08 /* buffer completion interrupt status */
187#define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
188#define ICH_CELV 0x02 /* current equals last valid */
189#define ICH_DCH 0x01 /* DMA controller halted */
190
191/* PIV */
192#define ICH_REG_PIV_MASK 0x1f /* mask */
193
194/* CR */
195#define ICH_IOCE 0x10 /* interrupt on completion enable */
196#define ICH_FEIE 0x08 /* fifo error interrupt enable */
197#define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
198#define ICH_RESETREGS 0x02 /* reset busmaster registers */
199#define ICH_STARTBM 0x01 /* start busmaster operation */
200
201
202/* global block */
203#define ICH_REG_GLOB_CNT 0x2c /* dword - global control */
204#define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */
205#define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */
206#define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */
207#define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */
208#define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */
209#define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */
210#define ICH_PCM_246_MASK 0x00300000 /* 6 channels (not all chips) */
211#define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */
212#define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */
213#define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */
214#define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */
215#define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */
216#define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */
217#define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */
218#define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
219#define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
220#define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
221#define ICH_ACLINK 0x00000008 /* AClink shut off */
222#define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
223#define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
224#define ICH_GIE 0x00000001 /* GPI interrupt enable */
225#define ICH_REG_GLOB_STA 0x30 /* dword - global status */
226#define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
227#define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
228#define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
229#define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
230#define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
231#define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
232#define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
233#define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */
234#define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
235#define ICH_MD3 0x00020000 /* modem power down semaphore */
236#define ICH_AD3 0x00010000 /* audio power down semaphore */
237#define ICH_RCS 0x00008000 /* read completion status */
238#define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
239#define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
240#define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
241#define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
242#define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
243#define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
244#define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
245#define ICH_MCINT 0x00000080 /* MIC capture interrupt */
246#define ICH_POINT 0x00000040 /* playback interrupt */
247#define ICH_PIINT 0x00000020 /* capture interrupt */
248#define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
249#define ICH_MOINT 0x00000004 /* modem playback interrupt */
250#define ICH_MIINT 0x00000002 /* modem capture interrupt */
251#define ICH_GSCI 0x00000001 /* GPI status change interrupt */
252#define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */
253#define ICH_CAS 0x01 /* codec access semaphore */
254#define ICH_REG_SDM 0x80
255#define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */
256#define ICH_DI2L_SHIFT 6
257#define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */
258#define ICH_DI1L_SHIFT 4
259#define ICH_SE 0x00000008 /* steer enable */
260#define ICH_LDI_MASK 0x00000003 /* last codec read data input */
261
262#define ICH_MAX_FRAGS 32 /* max hw frags */
263
264
265/*
266 * registers for Ali5455
267 */
268
269/* ALi 5455 busmaster blocks */
270DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */
271DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */
272DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */
273DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */
274DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */
275DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */
276DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */
277DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */
278DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */
279DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */
280DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */
281
282enum {
283 ICH_REG_ALI_SCR = 0x00, /* System Control Register */
284 ICH_REG_ALI_SSR = 0x04, /* System Status Register */
285 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */
286 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */
287 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
288 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
289 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */
290 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */
291 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */
292 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */
293 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */
294 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */
295 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */
296 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */
297 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */
298 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */
299 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */
300 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */
301 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */
302 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */
303 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */
304};
305
306#define ALI_CAS_SEM_BUSY 0x80000000
307#define ALI_CPR_ADDR_SECONDARY 0x100
308#define ALI_CPR_ADDR_READ 0x80
309#define ALI_CSPSR_CODEC_READY 0x08
310#define ALI_CSPSR_READ_OK 0x02
311#define ALI_CSPSR_WRITE_OK 0x01
312
313/* interrupts for the whole chip by interrupt status register finish */
314
315#define ALI_INT_MICIN2 (1<<26)
316#define ALI_INT_PCMIN2 (1<<25)
317#define ALI_INT_I2SIN (1<<24)
318#define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */
319#define ALI_INT_SPDIFIN (1<<22)
320#define ALI_INT_LFEOUT (1<<21)
321#define ALI_INT_CENTEROUT (1<<20)
322#define ALI_INT_CODECSPDIFOUT (1<<19)
323#define ALI_INT_MICIN (1<<18)
324#define ALI_INT_PCMOUT (1<<17)
325#define ALI_INT_PCMIN (1<<16)
326#define ALI_INT_CPRAIS (1<<7) /* command port available */
327#define ALI_INT_SPRAIS (1<<5) /* status port available */
328#define ALI_INT_GPIO (1<<1)
329#define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
330
331#define ICH_ALI_SC_RESET (1<<31) /* master reset */
332#define ICH_ALI_SC_AC97_DBL (1<<30)
333#define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
334#define ICH_ALI_SC_IN_BITS (3<<18)
335#define ICH_ALI_SC_OUT_BITS (3<<16)
336#define ICH_ALI_SC_6CH_CFG (3<<14)
337#define ICH_ALI_SC_PCM_4 (1<<8)
338#define ICH_ALI_SC_PCM_6 (2<<8)
339#define ICH_ALI_SC_PCM_246_MASK (3<<8)
340
341#define ICH_ALI_SS_SEC_ID (3<<5)
342#define ICH_ALI_SS_PRI_ID (3<<3)
343
344#define ICH_ALI_IF_AC97SP (1<<21)
345#define ICH_ALI_IF_MC (1<<20)
346#define ICH_ALI_IF_PI (1<<19)
347#define ICH_ALI_IF_MC2 (1<<18)
348#define ICH_ALI_IF_PI2 (1<<17)
349#define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */
350#define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */
351#define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
352#define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */
353#define ICH_ALI_IF_PO_SPDF (1<<3)
354#define ICH_ALI_IF_PO (1<<1)
355
356/*
357 *
358 */
359
360enum { ICHD_PCMIN, ICHD_PCMOUT, ICHD_MIC, ICHD_MIC2, ICHD_PCM2IN, ICHD_SPBAR, ICHD_LAST = ICHD_SPBAR };
361enum { NVD_PCMIN, NVD_PCMOUT, NVD_MIC, NVD_SPBAR, NVD_LAST = NVD_SPBAR };
362enum { ALID_PCMIN, ALID_PCMOUT, ALID_MIC, ALID_AC97SPDIFOUT, ALID_SPDIFIN, ALID_SPDIFOUT, ALID_LAST = ALID_SPDIFOUT };
363
364#define get_ichdev(substream) (ichdev_t *)(substream->runtime->private_data)
365
366typedef struct {
367 unsigned int ichd; /* ich device number */
368 unsigned long reg_offset; /* offset to bmaddr */
369 u32 *bdbar; /* CPU address (32bit) */
370 unsigned int bdbar_addr; /* PCI bus address (32bit) */
371 snd_pcm_substream_t *substream;
372 unsigned int physbuf; /* physical address (32bit) */
373 unsigned int size;
374 unsigned int fragsize;
375 unsigned int fragsize1;
376 unsigned int position;
377 unsigned int pos_shift;
378 int frags;
379 int lvi;
380 int lvi_frag;
381 int civ;
382 int ack;
383 int ack_reload;
384 unsigned int ack_bit;
385 unsigned int roff_sr;
386 unsigned int roff_picb;
387 unsigned int int_sta_mask; /* interrupt status mask */
388 unsigned int ali_slot; /* ALI DMA slot */
389 struct ac97_pcm *pcm;
390 int pcm_open_flag;
391 unsigned int page_attr_changed: 1;
1cfe43d2 392 unsigned int suspended: 1;
1da177e4
LT		 393} ichdev_t;
394
395typedef struct _snd_intel8x0 intel8x0_t;
396
397struct _snd_intel8x0 {
398 unsigned int device_type;
399
400 int irq;
401
402 unsigned int mmio;
403 unsigned long addr;
404 void __iomem *remap_addr;
405 unsigned int bm_mmio;
406 unsigned long bmaddr;
407 void __iomem *remap_bmaddr;
408
409 struct pci_dev *pci;
410 snd_card_t *card;
411
412 int pcm_devs;
413 snd_pcm_t *pcm[6];
414 ichdev_t ichd[6];
415
416 unsigned multi4: 1,
417 multi6: 1,
418 dra: 1,
419 smp20bit: 1;
420 unsigned in_ac97_init: 1,
421 in_sdin_init: 1;
422 unsigned in_measurement: 1; /* during ac97 clock measurement */
423 unsigned fix_nocache: 1; /* workaround for 440MX */
424 unsigned buggy_irq: 1; /* workaround for buggy mobos */
425 unsigned xbox: 1; /* workaround for Xbox AC'97 detection */
426
427 int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
52b72388 428 unsigned int sdm_saved; /* SDM reg value */
1da177e4
LT		 429
430 ac97_bus_t *ac97_bus;
431 ac97_t *ac97[3];
432 unsigned int ac97_sdin[3];
433
434 spinlock_t reg_lock;
435
436 u32 bdbars_count;
437 struct snd_dma_buffer bdbars;
438 u32 int_sta_reg; /* interrupt status register */
439 u32 int_sta_mask; /* interrupt status mask */
440};
441
442static struct pci_device_id snd_intel8x0_ids[] = {
443 { 0x8086, 0x2415, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
444 { 0x8086, 0x2425, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
445 { 0x8086, 0x2445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
446 { 0x8086, 0x2485, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
447 { 0x8086, 0x24c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH4 */
448 { 0x8086, 0x24d5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH5 */
449 { 0x8086, 0x25a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB */
450 { 0x8086, 0x266e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH6 */
451 { 0x8086, 0x27de, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH7 */
c4c8ea94 452 { 0x8086, 0x2698, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB2 */
1da177e4
LT		 453 { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
454 { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS }, /* SI7012 */
455 { 0x10de, 0x01b1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE */
456 { 0x10de, 0x003a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* MCP04 */
457 { 0x10de, 0x006a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2 */
458 { 0x10de, 0x0059, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK804 */
459 { 0x10de, 0x008a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8 */
460 { 0x10de, 0x00da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE3 */
461 { 0x10de, 0x00ea, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8S */
462 { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
463 { 0x1022, 0x7445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
464 { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI }, /* Ali5455 */
465 { 0, }
466};
467
468MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
469
470/*
471 * Lowlevel I/O - busmaster
472 */
473
474static u8 igetbyte(intel8x0_t *chip, u32 offset)
475{
476 if (chip->bm_mmio)
477 return readb(chip->remap_bmaddr + offset);
478 else
479 return inb(chip->bmaddr + offset);
480}
481
482static u16 igetword(intel8x0_t *chip, u32 offset)
483{
484 if (chip->bm_mmio)
485 return readw(chip->remap_bmaddr + offset);
486 else
487 return inw(chip->bmaddr + offset);
488}
489
490static u32 igetdword(intel8x0_t *chip, u32 offset)
491{
492 if (chip->bm_mmio)
493 return readl(chip->remap_bmaddr + offset);
494 else
495 return inl(chip->bmaddr + offset);
496}
497
498static void iputbyte(intel8x0_t *chip, u32 offset, u8 val)
499{
500 if (chip->bm_mmio)
501 writeb(val, chip->remap_bmaddr + offset);
502 else
503 outb(val, chip->bmaddr + offset);
504}
505
506static void iputword(intel8x0_t *chip, u32 offset, u16 val)
507{
508 if (chip->bm_mmio)
509 writew(val, chip->remap_bmaddr + offset);
510 else
511 outw(val, chip->bmaddr + offset);
512}
513
514static void iputdword(intel8x0_t *chip, u32 offset, u32 val)
515{
516 if (chip->bm_mmio)
517 writel(val, chip->remap_bmaddr + offset);
518 else
519 outl(val, chip->bmaddr + offset);
520}
521
522/*
523 * Lowlevel I/O - AC'97 registers
524 */
525
526static u16 iagetword(intel8x0_t *chip, u32 offset)
527{
528 if (chip->mmio)
529 return readw(chip->remap_addr + offset);
530 else
531 return inw(chip->addr + offset);
532}
533
534static void iaputword(intel8x0_t *chip, u32 offset, u16 val)
535{
536 if (chip->mmio)
537 writew(val, chip->remap_addr + offset);
538 else
539 outw(val, chip->addr + offset);
540}
541
542/*
543 * Basic I/O
544 */
545
546/*
547 * access to AC97 codec via normal i/o (for ICH and SIS7012)
548 */
549
550/* return the GLOB_STA bit for the corresponding codec */
551static unsigned int get_ich_codec_bit(intel8x0_t *chip, unsigned int codec)
552{
553 static unsigned int codec_bit[3] = {
554 ICH_PCR, ICH_SCR, ICH_TCR
555 };
556 snd_assert(codec < 3, return ICH_PCR);
557 if (chip->device_type == DEVICE_INTEL_ICH4)
558 codec = chip->ac97_sdin[codec];
559 return codec_bit[codec];
560}
561
562static int snd_intel8x0_codec_semaphore(intel8x0_t *chip, unsigned int codec)
563{
564 int time;
565
566 if (codec > 2)
567 return -EIO;
568 if (chip->in_sdin_init) {
569 /* we don't know the ready bit assignment at the moment */
570 /* so we check any */
571 codec = ICH_PCR | ICH_SCR | ICH_TCR;
572 } else {
573 codec = get_ich_codec_bit(chip, codec);
574 }
575
576 /* codec ready ? */
577 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
578 return -EIO;
579
580 /* Anyone holding a semaphore for 1 msec should be shot... */
581 time = 100;
582 do {
583 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
584 return 0;
585 udelay(10);
586 } while (time--);
587
588 /* access to some forbidden (non existant) ac97 registers will not
589 * reset the semaphore. So even if you don't get the semaphore, still
590 * continue the access. We don't need the semaphore anyway. */
591 snd_printk("codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
592 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
593 iagetword(chip, 0); /* clear semaphore flag */
594 /* I don't care about the semaphore */
595 return -EBUSY;
596}
597
598static void snd_intel8x0_codec_write(ac97_t *ac97,
599 unsigned short reg,
600 unsigned short val)
601{
602 intel8x0_t *chip = ac97->private_data;
603
604 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
605 if (! chip->in_ac97_init)
606 snd_printk("codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
607 }
608 iaputword(chip, reg + ac97->num * 0x80, val);
609}
610
611static unsigned short snd_intel8x0_codec_read(ac97_t *ac97,
612 unsigned short reg)
613{
614 intel8x0_t *chip = ac97->private_data;
615 unsigned short res;
616 unsigned int tmp;
617
618 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
619 if (! chip->in_ac97_init)
620 snd_printk("codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
621 res = 0xffff;
622 } else {
623 res = iagetword(chip, reg + ac97->num * 0x80);
624 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
625 /* reset RCS and preserve other R/WC bits */
626 iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
627 if (! chip->in_ac97_init)
628 snd_printk("codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
629 res = 0xffff;
630 }
631 }
632 return res;
633}
634
635static void snd_intel8x0_codec_read_test(intel8x0_t *chip, unsigned int codec)
636{
637 unsigned int tmp;
638
639 if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
640 iagetword(chip, codec * 0x80);
641 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
642 /* reset RCS and preserve other R/WC bits */
643 iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
644 }
645 }
646}
647
648/*
649 * access to AC97 for Ali5455
650 */
651static int snd_intel8x0_ali_codec_ready(intel8x0_t *chip, int mask)
652{
653 int count = 0;
654 for (count = 0; count < 0x7f; count++) {
655 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
656 if (val & mask)
657 return 0;
658 }
659 snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n");
660 return -EBUSY;
661}
662
663static int snd_intel8x0_ali_codec_semaphore(intel8x0_t *chip)
664{
665 int time = 100;
666 while (time-- && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
667 udelay(1);
668 if (! time)
669 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n");
670 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
671}
672
673static unsigned short snd_intel8x0_ali_codec_read(ac97_t *ac97, unsigned short reg)
674{
675 intel8x0_t *chip = ac97->private_data;
676 unsigned short data = 0xffff;
677
678 if (snd_intel8x0_ali_codec_semaphore(chip))
679 goto __err;
680 reg |= ALI_CPR_ADDR_READ;
681 if (ac97->num)
682 reg |= ALI_CPR_ADDR_SECONDARY;
683 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
684 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
685 goto __err;
686 data = igetword(chip, ICHREG(ALI_SPR));
687 __err:
688 return data;
689}
690
691static void snd_intel8x0_ali_codec_write(ac97_t *ac97, unsigned short reg, unsigned short val)
692{
693 intel8x0_t *chip = ac97->private_data;
694
695 if (snd_intel8x0_ali_codec_semaphore(chip))
696 return;
697 iputword(chip, ICHREG(ALI_CPR), val);
698 if (ac97->num)
699 reg |= ALI_CPR_ADDR_SECONDARY;
700 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
701 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
702}
703
704
705/*
706 * DMA I/O
707 */
708static void snd_intel8x0_setup_periods(intel8x0_t *chip, ichdev_t *ichdev)
709{
710 int idx;
711 u32 *bdbar = ichdev->bdbar;
712 unsigned long port = ichdev->reg_offset;
713
714 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
715 if (ichdev->size == ichdev->fragsize) {
716 ichdev->ack_reload = ichdev->ack = 2;
717 ichdev->fragsize1 = ichdev->fragsize >> 1;
718 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
719 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
720 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
721 ichdev->fragsize1 >> ichdev->pos_shift);
722 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
723 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
724 ichdev->fragsize1 >> ichdev->pos_shift);
725 }
726 ichdev->frags = 2;
727 } else {
728 ichdev->ack_reload = ichdev->ack = 1;
729 ichdev->fragsize1 = ichdev->fragsize;
730 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
731 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size));
732 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
733 ichdev->fragsize >> ichdev->pos_shift);
734 // printk("bdbar[%i] = 0x%x [0x%x]\n", idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
735 }
736 ichdev->frags = ichdev->size / ichdev->fragsize;
737 }
738 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
739 ichdev->civ = 0;
740 iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
741 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
742 ichdev->position = 0;
743#if 0
744 printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
745 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1);
746#endif
747 /* clear interrupts */
748 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
749}
750
751#ifdef __i386__
752/*
753 * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
754 * which aborts PCI busmaster for audio transfer. A workaround is to set
755 * the pages as non-cached. For details, see the errata in
756 * http://www.intel.com/design/chipsets/specupdt/245051.htm
757 */
758static void fill_nocache(void *buf, int size, int nocache)
759{
760 size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
761 change_page_attr(virt_to_page(buf), size, nocache ? PAGE_KERNEL_NOCACHE : PAGE_KERNEL);
762 global_flush_tlb();
763}
764#else
765#define fill_nocache(buf,size,nocache)
766#endif
767
768/*
769 * Interrupt handler
770 */
771
772static inline void snd_intel8x0_update(intel8x0_t *chip, ichdev_t *ichdev)
773{
774 unsigned long port = ichdev->reg_offset;
775 int status, civ, i, step;
776 int ack = 0;
777
778 spin_lock(&chip->reg_lock);
779 status = igetbyte(chip, port + ichdev->roff_sr);
780 civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
781 if (!(status & ICH_BCIS)) {
782 step = 0;
783 } else if (civ == ichdev->civ) {
784 // snd_printd("civ same %d\n", civ);
785 step = 1;
786 ichdev->civ++;
787 ichdev->civ &= ICH_REG_LVI_MASK;
788 } else {
789 step = civ - ichdev->civ;
790 if (step < 0)
791 step += ICH_REG_LVI_MASK + 1;
792 // if (step != 1)
793 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
794 ichdev->civ = civ;
795 }
796
797 ichdev->position += step * ichdev->fragsize1;
798 if (! chip->in_measurement)
799 ichdev->position %= ichdev->size;
800 ichdev->lvi += step;
801 ichdev->lvi &= ICH_REG_LVI_MASK;
802 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
803 for (i = 0; i < step; i++) {
804 ichdev->lvi_frag++;
805 ichdev->lvi_frag %= ichdev->frags;
806 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
807 // printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), inl(port + 4), inb(port + ICH_REG_OFF_CR));
808 if (--ichdev->ack == 0) {
809 ichdev->ack = ichdev->ack_reload;
810 ack = 1;
811 }
812 }
813 spin_unlock(&chip->reg_lock);
814 if (ack && ichdev->substream) {
815 snd_pcm_period_elapsed(ichdev->substream);
816 }
817 iputbyte(chip, port + ichdev->roff_sr,
818 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
819}
820
821static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id, struct pt_regs *regs)
822{
823 intel8x0_t *chip = dev_id;
824 ichdev_t *ichdev;
825 unsigned int status;
826 unsigned int i;
827
828 status = igetdword(chip, chip->int_sta_reg);
829 if (status == 0xffffffff) /* we are not yet resumed */
830 return IRQ_NONE;
831
832 if ((status & chip->int_sta_mask) == 0) {
833 if (status) {
834 /* ack */
835 iputdword(chip, chip->int_sta_reg, status);
836 if (! chip->buggy_irq)
837 status = 0;
838 }
839 return IRQ_RETVAL(status);
840 }
841
842 for (i = 0; i < chip->bdbars_count; i++) {
843 ichdev = &chip->ichd[i];
844 if (status & ichdev->int_sta_mask)
845 snd_intel8x0_update(chip, ichdev);
846 }
847
848 /* ack them */
849 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
850
851 return IRQ_HANDLED;
852}
853
854/*
855 * PCM part
856 */
857
858static int snd_intel8x0_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
859{
860 intel8x0_t *chip = snd_pcm_substream_chip(substream);
861 ichdev_t *ichdev = get_ichdev(substream);
862 unsigned char val = 0;
863 unsigned long port = ichdev->reg_offset;
864
865 switch (cmd) {
1da177e4 866 case SNDRV_PCM_TRIGGER_RESUME:
1cfe43d2
TI		 867 ichdev->suspended = 0;
868 /* fallthru */
869 case SNDRV_PCM_TRIGGER_START:
1da177e4
LT		 870 val = ICH_IOCE | ICH_STARTBM;
871 break;
1da177e4 872 case SNDRV_PCM_TRIGGER_SUSPEND:
1cfe43d2
TI		 873 ichdev->suspended = 1;
874 /* fallthru */
875 case SNDRV_PCM_TRIGGER_STOP:
1da177e4
LT		 876 val = 0;
877 break;
878 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
879 val = ICH_IOCE;
880 break;
881 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
882 val = ICH_IOCE | ICH_STARTBM;
883 break;
884 default:
885 return -EINVAL;
886 }
887 iputbyte(chip, port + ICH_REG_OFF_CR, val);
888 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
889 /* wait until DMA stopped */
890 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
891 /* reset whole DMA things */
892 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
893 }
894 return 0;
895}
896
897static int snd_intel8x0_ali_trigger(snd_pcm_substream_t *substream, int cmd)
898{
899 intel8x0_t *chip = snd_pcm_substream_chip(substream);
900 ichdev_t *ichdev = get_ichdev(substream);
901 unsigned long port = ichdev->reg_offset;
902 static int fiforeg[] = { ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3) };
903 unsigned int val, fifo;
904
905 val = igetdword(chip, ICHREG(ALI_DMACR));
906 switch (cmd) {
1cfe43d2
TI		 907 case SNDRV_PCM_TRIGGER_RESUME:
908 ichdev->suspended = 0;
909 /* fallthru */
1da177e4
LT		 910 case SNDRV_PCM_TRIGGER_START:
911 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1da177e4
LT		 912 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
913 /* clear FIFO for synchronization of channels */
914 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
915 fifo &= ~(0xff << (ichdev->ali_slot % 4));
916 fifo |= 0x83 << (ichdev->ali_slot % 4);
917 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
918 }
919 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
920 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
921 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot)); /* start DMA */
922 break;
1cfe43d2
TI		 923 case SNDRV_PCM_TRIGGER_SUSPEND:
924 ichdev->suspended = 1;
925 /* fallthru */
1da177e4
LT		 926 case SNDRV_PCM_TRIGGER_STOP:
927 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1da177e4
LT		 928 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16))); /* pause */
929 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
930 while (igetbyte(chip, port + ICH_REG_OFF_CR))
931 ;
932 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
933 break;
934 /* reset whole DMA things */
935 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
936 /* clear interrupts */
937 iputbyte(chip, port + ICH_REG_OFF_SR, igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
938 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
939 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
940 break;
941 default:
942 return -EINVAL;
943 }
944 return 0;
945}
946
947static int snd_intel8x0_hw_params(snd_pcm_substream_t * substream,
948 snd_pcm_hw_params_t * hw_params)
949{
950 intel8x0_t *chip = snd_pcm_substream_chip(substream);
951 ichdev_t *ichdev = get_ichdev(substream);
952 snd_pcm_runtime_t *runtime = substream->runtime;
953 int dbl = params_rate(hw_params) > 48000;
954 int err;
955
956 if (chip->fix_nocache && ichdev->page_attr_changed) {
957 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
958 ichdev->page_attr_changed = 0;
959 }
960 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
961 if (err < 0)
962 return err;
963 if (chip->fix_nocache) {
964 if (runtime->dma_area && ! ichdev->page_attr_changed) {
965 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
966 ichdev->page_attr_changed = 1;
967 }
968 }
969 if (ichdev->pcm_open_flag) {
970 snd_ac97_pcm_close(ichdev->pcm);
971 ichdev->pcm_open_flag = 0;
972 }
973 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
974 params_channels(hw_params),
975 ichdev->pcm->r[dbl].slots);
976 if (err >= 0) {
977 ichdev->pcm_open_flag = 1;
978 /* Force SPDIF setting */
979 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
980 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF, params_rate(hw_params));
981 }
982 return err;
983}
984
985static int snd_intel8x0_hw_free(snd_pcm_substream_t * substream)
986{
987 intel8x0_t *chip = snd_pcm_substream_chip(substream);
988 ichdev_t *ichdev = get_ichdev(substream);
989
990 if (ichdev->pcm_open_flag) {
991 snd_ac97_pcm_close(ichdev->pcm);
992 ichdev->pcm_open_flag = 0;
993 }
994 if (chip->fix_nocache && ichdev->page_attr_changed) {
995 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
996 ichdev->page_attr_changed = 0;
997 }
998 return snd_pcm_lib_free_pages(substream);
999}
1000
1001static void snd_intel8x0_setup_pcm_out(intel8x0_t *chip,
1002 snd_pcm_runtime_t *runtime)
1003{
1004 unsigned int cnt;
1005 int dbl = runtime->rate > 48000;
1cfe43d2
TI		 1006
1007 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 1008 switch (chip->device_type) {
1009 case DEVICE_ALI:
1010 cnt = igetdword(chip, ICHREG(ALI_SCR));
1011 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
1012 if (runtime->channels == 4 || dbl)
1013 cnt |= ICH_ALI_SC_PCM_4;
1014 else if (runtime->channels == 6)
1015 cnt |= ICH_ALI_SC_PCM_6;
1016 iputdword(chip, ICHREG(ALI_SCR), cnt);
1017 break;
1018 case DEVICE_SIS:
1019 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1020 cnt &= ~ICH_SIS_PCM_246_MASK;
1021 if (runtime->channels == 4 || dbl)
1022 cnt |= ICH_SIS_PCM_4;
1023 else if (runtime->channels == 6)
1024 cnt |= ICH_SIS_PCM_6;
1025 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1026 break;
1027 default:
1028 cnt = igetdword(chip, ICHREG(GLOB_CNT));
1029 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
1030 if (runtime->channels == 4 || dbl)
1031 cnt |= ICH_PCM_4;
1032 else if (runtime->channels == 6)
1033 cnt |= ICH_PCM_6;
1034 if (chip->device_type == DEVICE_NFORCE) {
1035 /* reset to 2ch once to keep the 6 channel data in alignment,
1036 * to start from Front Left always
1037 */
1038 if (cnt & ICH_PCM_246_MASK) {
1039 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
1040 spin_unlock_irq(&chip->reg_lock);
1041 msleep(50); /* grrr... */
1042 spin_lock_irq(&chip->reg_lock);
1043 }
1044 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
1045 if (runtime->sample_bits > 16)
1046 cnt |= ICH_PCM_20BIT;
1047 }
1048 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1049 break;
1050 }
1cfe43d2 1051 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 1052}
1053
1054static int snd_intel8x0_pcm_prepare(snd_pcm_substream_t * substream)
1055{
1056 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1057 snd_pcm_runtime_t *runtime = substream->runtime;
1058 ichdev_t *ichdev = get_ichdev(substream);
1059
1060 ichdev->physbuf = runtime->dma_addr;
1061 ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1062 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1da177e4
LT		 1063 if (ichdev->ichd == ICHD_PCMOUT) {
1064 snd_intel8x0_setup_pcm_out(chip, runtime);
1cfe43d2 1065 if (chip->device_type == DEVICE_INTEL_ICH4)
1da177e4 1066 ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1da177e4
LT		 1067 }
1068 snd_intel8x0_setup_periods(chip, ichdev);
1da177e4
LT		 1069 return 0;
1070}
1071
1072static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(snd_pcm_substream_t * substream)
1073{
1074 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1075 ichdev_t *ichdev = get_ichdev(substream);
1076 size_t ptr1, ptr;
1077 int civ, timeout = 100;
1078 unsigned int position;
1079
1080 spin_lock(&chip->reg_lock);
1081 do {
1082 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1083 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1084 position = ichdev->position;
1085 if (ptr1 == 0) {
1086 udelay(10);
1087 continue;
1088 }
1089 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
1090 ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1091 break;
1092 } while (timeout--);
1093 ptr1 <<= ichdev->pos_shift;
1094 ptr = ichdev->fragsize1 - ptr1;
1095 ptr += position;
1096 spin_unlock(&chip->reg_lock);
1097 if (ptr >= ichdev->size)
1098 return 0;
1099 return bytes_to_frames(substream->runtime, ptr);
1100}
1101
1102static snd_pcm_hardware_t snd_intel8x0_stream =
1103{
1104 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1105 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1106 SNDRV_PCM_INFO_MMAP_VALID |
1107 SNDRV_PCM_INFO_PAUSE |
1108 SNDRV_PCM_INFO_RESUME),
1109 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1110 .rates = SNDRV_PCM_RATE_48000,
1111 .rate_min = 48000,
1112 .rate_max = 48000,
1113 .channels_min = 2,
1114 .channels_max = 2,
1115 .buffer_bytes_max = 128 * 1024,
1116 .period_bytes_min = 32,
1117 .period_bytes_max = 128 * 1024,
1118 .periods_min = 1,
1119 .periods_max = 1024,
1120 .fifo_size = 0,
1121};
1122
1123static unsigned int channels4[] = {
1124 2, 4,
1125};
1126
1127static snd_pcm_hw_constraint_list_t hw_constraints_channels4 = {
1128 .count = ARRAY_SIZE(channels4),
1129 .list = channels4,
1130 .mask = 0,
1131};
1132
1133static unsigned int channels6[] = {
1134 2, 4, 6,
1135};
1136
1137static snd_pcm_hw_constraint_list_t hw_constraints_channels6 = {
1138 .count = ARRAY_SIZE(channels6),
1139 .list = channels6,
1140 .mask = 0,
1141};
1142
1143static int snd_intel8x0_pcm_open(snd_pcm_substream_t * substream, ichdev_t *ichdev)
1144{
1145 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1146 snd_pcm_runtime_t *runtime = substream->runtime;
1147 int err;
1148
1149 ichdev->substream = substream;
1150 runtime->hw = snd_intel8x0_stream;
1151 runtime->hw.rates = ichdev->pcm->rates;
1152 snd_pcm_limit_hw_rates(runtime);
1153 if (chip->device_type == DEVICE_SIS) {
1154 runtime->hw.buffer_bytes_max = 64*1024;
1155 runtime->hw.period_bytes_max = 64*1024;
1156 }
1157 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1158 return err;
1159 runtime->private_data = ichdev;
1160 return 0;
1161}
1162
1163static int snd_intel8x0_playback_open(snd_pcm_substream_t * substream)
1164{
1165 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1166 snd_pcm_runtime_t *runtime = substream->runtime;
1167 int err;
1168
1169 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1170 if (err < 0)
1171 return err;
1172
1173 if (chip->multi6) {
1174 runtime->hw.channels_max = 6;
1175 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels6);
1176 } else if (chip->multi4) {
1177 runtime->hw.channels_max = 4;
1178 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels4);
1179 }
1180 if (chip->dra) {
1181 snd_ac97_pcm_double_rate_rules(runtime);
1182 }
1183 if (chip->smp20bit) {
1184 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1185 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1186 }
1187 return 0;
1188}
1189
1190static int snd_intel8x0_playback_close(snd_pcm_substream_t * substream)
1191{
1192 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1193
1194 chip->ichd[ICHD_PCMOUT].substream = NULL;
1195 return 0;
1196}
1197
1198static int snd_intel8x0_capture_open(snd_pcm_substream_t * substream)
1199{
1200 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1201
1202 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1203}
1204
1205static int snd_intel8x0_capture_close(snd_pcm_substream_t * substream)
1206{
1207 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1208
1209 chip->ichd[ICHD_PCMIN].substream = NULL;
1210 return 0;
1211}
1212
1213static int snd_intel8x0_mic_open(snd_pcm_substream_t * substream)
1214{
1215 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1216
1217 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1218}
1219
1220static int snd_intel8x0_mic_close(snd_pcm_substream_t * substream)
1221{
1222 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1223
1224 chip->ichd[ICHD_MIC].substream = NULL;
1225 return 0;
1226}
1227
1228static int snd_intel8x0_mic2_open(snd_pcm_substream_t * substream)
1229{
1230 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1231
1232 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1233}
1234
1235static int snd_intel8x0_mic2_close(snd_pcm_substream_t * substream)
1236{
1237 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1238
1239 chip->ichd[ICHD_MIC2].substream = NULL;
1240 return 0;
1241}
1242
1243static int snd_intel8x0_capture2_open(snd_pcm_substream_t * substream)
1244{
1245 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1246
1247 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1248}
1249
1250static int snd_intel8x0_capture2_close(snd_pcm_substream_t * substream)
1251{
1252 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1253
1254 chip->ichd[ICHD_PCM2IN].substream = NULL;
1255 return 0;
1256}
1257
1258static int snd_intel8x0_spdif_open(snd_pcm_substream_t * substream)
1259{
1260 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1261 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1262
1263 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1264}
1265
1266static int snd_intel8x0_spdif_close(snd_pcm_substream_t * substream)
1267{
1268 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1269 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1270
1271 chip->ichd[idx].substream = NULL;
1272 return 0;
1273}
1274
1275static int snd_intel8x0_ali_ac97spdifout_open(snd_pcm_substream_t * substream)
1276{
1277 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1278 unsigned int val;
1279
1280 spin_lock_irq(&chip->reg_lock);
1281 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1282 val |= ICH_ALI_IF_AC97SP;
1283 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1284 /* also needs to set ALI_SC_CODEC_SPDF correctly */
1285 spin_unlock_irq(&chip->reg_lock);
1286
1287 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1288}
1289
1290static int snd_intel8x0_ali_ac97spdifout_close(snd_pcm_substream_t * substream)
1291{
1292 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1293 unsigned int val;
1294
1295 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1296 spin_lock_irq(&chip->reg_lock);
1297 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1298 val &= ~ICH_ALI_IF_AC97SP;
1299 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1300 spin_unlock_irq(&chip->reg_lock);
1301
1302 return 0;
1303}
1304
1305static int snd_intel8x0_ali_spdifin_open(snd_pcm_substream_t * substream)
1306{
1307 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1308
1309 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1310}
1311
1312static int snd_intel8x0_ali_spdifin_close(snd_pcm_substream_t * substream)
1313{
1314 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1315
1316 chip->ichd[ALID_SPDIFIN].substream = NULL;
1317 return 0;
1318}
1319
1320#if 0 // NYI
1321static int snd_intel8x0_ali_spdifout_open(snd_pcm_substream_t * substream)
1322{
1323 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1324
1325 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1326}
1327
1328static int snd_intel8x0_ali_spdifout_close(snd_pcm_substream_t * substream)
1329{
1330 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1331
1332 chip->ichd[ALID_SPDIFOUT].substream = NULL;
1333 return 0;
1334}
1335#endif
1336
1337static snd_pcm_ops_t snd_intel8x0_playback_ops = {
1338 .open = snd_intel8x0_playback_open,
1339 .close = snd_intel8x0_playback_close,
1340 .ioctl = snd_pcm_lib_ioctl,
1341 .hw_params = snd_intel8x0_hw_params,
1342 .hw_free = snd_intel8x0_hw_free,
1343 .prepare = snd_intel8x0_pcm_prepare,
1344 .trigger = snd_intel8x0_pcm_trigger,
1345 .pointer = snd_intel8x0_pcm_pointer,
1346};
1347
1348static snd_pcm_ops_t snd_intel8x0_capture_ops = {
1349 .open = snd_intel8x0_capture_open,
1350 .close = snd_intel8x0_capture_close,
1351 .ioctl = snd_pcm_lib_ioctl,
1352 .hw_params = snd_intel8x0_hw_params,
1353 .hw_free = snd_intel8x0_hw_free,
1354 .prepare = snd_intel8x0_pcm_prepare,
1355 .trigger = snd_intel8x0_pcm_trigger,
1356 .pointer = snd_intel8x0_pcm_pointer,
1357};
1358
1359static snd_pcm_ops_t snd_intel8x0_capture_mic_ops = {
1360 .open = snd_intel8x0_mic_open,
1361 .close = snd_intel8x0_mic_close,
1362 .ioctl = snd_pcm_lib_ioctl,
1363 .hw_params = snd_intel8x0_hw_params,
1364 .hw_free = snd_intel8x0_hw_free,
1365 .prepare = snd_intel8x0_pcm_prepare,
1366 .trigger = snd_intel8x0_pcm_trigger,
1367 .pointer = snd_intel8x0_pcm_pointer,
1368};
1369
1370static snd_pcm_ops_t snd_intel8x0_capture_mic2_ops = {
1371 .open = snd_intel8x0_mic2_open,
1372 .close = snd_intel8x0_mic2_close,
1373 .ioctl = snd_pcm_lib_ioctl,
1374 .hw_params = snd_intel8x0_hw_params,
1375 .hw_free = snd_intel8x0_hw_free,
1376 .prepare = snd_intel8x0_pcm_prepare,
1377 .trigger = snd_intel8x0_pcm_trigger,
1378 .pointer = snd_intel8x0_pcm_pointer,
1379};
1380
1381static snd_pcm_ops_t snd_intel8x0_capture2_ops = {
1382 .open = snd_intel8x0_capture2_open,
1383 .close = snd_intel8x0_capture2_close,
1384 .ioctl = snd_pcm_lib_ioctl,
1385 .hw_params = snd_intel8x0_hw_params,
1386 .hw_free = snd_intel8x0_hw_free,
1387 .prepare = snd_intel8x0_pcm_prepare,
1388 .trigger = snd_intel8x0_pcm_trigger,
1389 .pointer = snd_intel8x0_pcm_pointer,
1390};
1391
1392static snd_pcm_ops_t snd_intel8x0_spdif_ops = {
1393 .open = snd_intel8x0_spdif_open,
1394 .close = snd_intel8x0_spdif_close,
1395 .ioctl = snd_pcm_lib_ioctl,
1396 .hw_params = snd_intel8x0_hw_params,
1397 .hw_free = snd_intel8x0_hw_free,
1398 .prepare = snd_intel8x0_pcm_prepare,
1399 .trigger = snd_intel8x0_pcm_trigger,
1400 .pointer = snd_intel8x0_pcm_pointer,
1401};
1402
1403static snd_pcm_ops_t snd_intel8x0_ali_playback_ops = {
1404 .open = snd_intel8x0_playback_open,
1405 .close = snd_intel8x0_playback_close,
1406 .ioctl = snd_pcm_lib_ioctl,
1407 .hw_params = snd_intel8x0_hw_params,
1408 .hw_free = snd_intel8x0_hw_free,
1409 .prepare = snd_intel8x0_pcm_prepare,
1410 .trigger = snd_intel8x0_ali_trigger,
1411 .pointer = snd_intel8x0_pcm_pointer,
1412};
1413
1414static snd_pcm_ops_t snd_intel8x0_ali_capture_ops = {
1415 .open = snd_intel8x0_capture_open,
1416 .close = snd_intel8x0_capture_close,
1417 .ioctl = snd_pcm_lib_ioctl,
1418 .hw_params = snd_intel8x0_hw_params,
1419 .hw_free = snd_intel8x0_hw_free,
1420 .prepare = snd_intel8x0_pcm_prepare,
1421 .trigger = snd_intel8x0_ali_trigger,
1422 .pointer = snd_intel8x0_pcm_pointer,
1423};
1424
1425static snd_pcm_ops_t snd_intel8x0_ali_capture_mic_ops = {
1426 .open = snd_intel8x0_mic_open,
1427 .close = snd_intel8x0_mic_close,
1428 .ioctl = snd_pcm_lib_ioctl,
1429 .hw_params = snd_intel8x0_hw_params,
1430 .hw_free = snd_intel8x0_hw_free,
1431 .prepare = snd_intel8x0_pcm_prepare,
1432 .trigger = snd_intel8x0_ali_trigger,
1433 .pointer = snd_intel8x0_pcm_pointer,
1434};
1435
1436static snd_pcm_ops_t snd_intel8x0_ali_ac97spdifout_ops = {
1437 .open = snd_intel8x0_ali_ac97spdifout_open,
1438 .close = snd_intel8x0_ali_ac97spdifout_close,
1439 .ioctl = snd_pcm_lib_ioctl,
1440 .hw_params = snd_intel8x0_hw_params,
1441 .hw_free = snd_intel8x0_hw_free,
1442 .prepare = snd_intel8x0_pcm_prepare,
1443 .trigger = snd_intel8x0_ali_trigger,
1444 .pointer = snd_intel8x0_pcm_pointer,
1445};
1446
1447static snd_pcm_ops_t snd_intel8x0_ali_spdifin_ops = {
1448 .open = snd_intel8x0_ali_spdifin_open,
1449 .close = snd_intel8x0_ali_spdifin_close,
1450 .ioctl = snd_pcm_lib_ioctl,
1451 .hw_params = snd_intel8x0_hw_params,
1452 .hw_free = snd_intel8x0_hw_free,
1453 .prepare = snd_intel8x0_pcm_prepare,
1454 .trigger = snd_intel8x0_pcm_trigger,
1455 .pointer = snd_intel8x0_pcm_pointer,
1456};
1457
1458#if 0 // NYI
1459static snd_pcm_ops_t snd_intel8x0_ali_spdifout_ops = {
1460 .open = snd_intel8x0_ali_spdifout_open,
1461 .close = snd_intel8x0_ali_spdifout_close,
1462 .ioctl = snd_pcm_lib_ioctl,
1463 .hw_params = snd_intel8x0_hw_params,
1464 .hw_free = snd_intel8x0_hw_free,
1465 .prepare = snd_intel8x0_pcm_prepare,
1466 .trigger = snd_intel8x0_pcm_trigger,
1467 .pointer = snd_intel8x0_pcm_pointer,
1468};
1469#endif // NYI
1470
1471struct ich_pcm_table {
1472 char *suffix;
1473 snd_pcm_ops_t *playback_ops;
1474 snd_pcm_ops_t *capture_ops;
1475 size_t prealloc_size;
1476 size_t prealloc_max_size;
1477 int ac97_idx;
1478};
1479
1480static int __devinit snd_intel8x0_pcm1(intel8x0_t *chip, int device, struct ich_pcm_table *rec)
1481{
1482 snd_pcm_t *pcm;
1483 int err;
1484 char name[32];
1485
1486 if (rec->suffix)
1487 sprintf(name, "Intel ICH - %s", rec->suffix);
1488 else
1489 strcpy(name, "Intel ICH");
1490 err = snd_pcm_new(chip->card, name, device,
1491 rec->playback_ops ? 1 : 0,
1492 rec->capture_ops ? 1 : 0, &pcm);
1493 if (err < 0)
1494 return err;
1495
1496 if (rec->playback_ops)
1497 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1498 if (rec->capture_ops)
1499 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1500
1501 pcm->private_data = chip;
1502 pcm->info_flags = 0;
1503 if (rec->suffix)
1504 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1505 else
1506 strcpy(pcm->name, chip->card->shortname);
1507 chip->pcm[device] = pcm;
1508
1509 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1510 rec->prealloc_size, rec->prealloc_max_size);
1511
1512 return 0;
1513}
1514
1515static struct ich_pcm_table intel_pcms[] __devinitdata = {
1516 {
1517 .playback_ops = &snd_intel8x0_playback_ops,
1518 .capture_ops = &snd_intel8x0_capture_ops,
1519 .prealloc_size = 64 * 1024,
1520 .prealloc_max_size = 128 * 1024,
1521 },
1522 {
1523 .suffix = "MIC ADC",
1524 .capture_ops = &snd_intel8x0_capture_mic_ops,
1525 .prealloc_size = 0,
1526 .prealloc_max_size = 128 * 1024,
1527 .ac97_idx = ICHD_MIC,
1528 },
1529 {
1530 .suffix = "MIC2 ADC",
1531 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1532 .prealloc_size = 0,
1533 .prealloc_max_size = 128 * 1024,
1534 .ac97_idx = ICHD_MIC2,
1535 },
1536 {
1537 .suffix = "ADC2",
1538 .capture_ops = &snd_intel8x0_capture2_ops,
1539 .prealloc_size = 0,
1540 .prealloc_max_size = 128 * 1024,
1541 .ac97_idx = ICHD_PCM2IN,
1542 },
1543 {
1544 .suffix = "IEC958",
1545 .playback_ops = &snd_intel8x0_spdif_ops,
1546 .prealloc_size = 64 * 1024,
1547 .prealloc_max_size = 128 * 1024,
1548 .ac97_idx = ICHD_SPBAR,
1549 },
1550};
1551
1552static struct ich_pcm_table nforce_pcms[] __devinitdata = {
1553 {
1554 .playback_ops = &snd_intel8x0_playback_ops,
1555 .capture_ops = &snd_intel8x0_capture_ops,
1556 .prealloc_size = 64 * 1024,
1557 .prealloc_max_size = 128 * 1024,
1558 },
1559 {
1560 .suffix = "MIC ADC",
1561 .capture_ops = &snd_intel8x0_capture_mic_ops,
1562 .prealloc_size = 0,
1563 .prealloc_max_size = 128 * 1024,
1564 .ac97_idx = NVD_MIC,
1565 },
1566 {
1567 .suffix = "IEC958",
1568 .playback_ops = &snd_intel8x0_spdif_ops,
1569 .prealloc_size = 64 * 1024,
1570 .prealloc_max_size = 128 * 1024,
1571 .ac97_idx = NVD_SPBAR,
1572 },
1573};
1574
1575static struct ich_pcm_table ali_pcms[] __devinitdata = {
1576 {
1577 .playback_ops = &snd_intel8x0_ali_playback_ops,
1578 .capture_ops = &snd_intel8x0_ali_capture_ops,
1579 .prealloc_size = 64 * 1024,
1580 .prealloc_max_size = 128 * 1024,
1581 },
1582 {
1583 .suffix = "MIC ADC",
1584 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1585 .prealloc_size = 0,
1586 .prealloc_max_size = 128 * 1024,
1587 .ac97_idx = ALID_MIC,
1588 },
1589 {
1590 .suffix = "IEC958",
1591 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1592 .capture_ops = &snd_intel8x0_ali_spdifin_ops,
1593 .prealloc_size = 64 * 1024,
1594 .prealloc_max_size = 128 * 1024,
1595 .ac97_idx = ALID_AC97SPDIFOUT,
1596 },
1597#if 0 // NYI
1598 {
1599 .suffix = "HW IEC958",
1600 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1601 .prealloc_size = 64 * 1024,
1602 .prealloc_max_size = 128 * 1024,
1603 },
1604#endif
1605};
1606
1607static int __devinit snd_intel8x0_pcm(intel8x0_t *chip)
1608{
1609 int i, tblsize, device, err;
1610 struct ich_pcm_table *tbl, *rec;
1611
1612 switch (chip->device_type) {
1613 case DEVICE_INTEL_ICH4:
1614 tbl = intel_pcms;
1615 tblsize = ARRAY_SIZE(intel_pcms);
1616 break;
1617 case DEVICE_NFORCE:
1618 tbl = nforce_pcms;
1619 tblsize = ARRAY_SIZE(nforce_pcms);
1620 break;
1621 case DEVICE_ALI:
1622 tbl = ali_pcms;
1623 tblsize = ARRAY_SIZE(ali_pcms);
1624 break;
1625 default:
1626 tbl = intel_pcms;
1627 tblsize = 2;
1628 break;
1629 }
1630
1631 device = 0;
1632 for (i = 0; i < tblsize; i++) {
1633 rec = tbl + i;
1634 if (i > 0 && rec->ac97_idx) {
1635 /* activate PCM only when associated AC'97 codec */
1636 if (! chip->ichd[rec->ac97_idx].pcm)
1637 continue;
1638 }
1639 err = snd_intel8x0_pcm1(chip, device, rec);
1640 if (err < 0)
1641 return err;
1642 device++;
1643 }
1644
1645 chip->pcm_devs = device;
1646 return 0;
1647}
1648
1649
1650/*
1651 * Mixer part
1652 */
1653
1654static void snd_intel8x0_mixer_free_ac97_bus(ac97_bus_t *bus)
1655{
1656 intel8x0_t *chip = bus->private_data;
1657 chip->ac97_bus = NULL;
1658}
1659
1660static void snd_intel8x0_mixer_free_ac97(ac97_t *ac97)
1661{
1662 intel8x0_t *chip = ac97->private_data;
1663 chip->ac97[ac97->num] = NULL;
1664}
1665
1666static struct ac97_pcm ac97_pcm_defs[] __devinitdata = {
1667 /* front PCM */
1668 {
1669 .exclusive = 1,
1670 .r = { {
1671 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1672 (1 << AC97_SLOT_PCM_RIGHT) |
1673 (1 << AC97_SLOT_PCM_CENTER) |
1674 (1 << AC97_SLOT_PCM_SLEFT) |
1675 (1 << AC97_SLOT_PCM_SRIGHT) |
1676 (1 << AC97_SLOT_LFE)
1677 },
1678 {
1679 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1680 (1 << AC97_SLOT_PCM_RIGHT) |
1681 (1 << AC97_SLOT_PCM_LEFT_0) |
1682 (1 << AC97_SLOT_PCM_RIGHT_0)
1683 }
1684 }
1685 },
1686 /* PCM IN #1 */
1687 {
1688 .stream = 1,
1689 .exclusive = 1,
1690 .r = { {
1691 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1692 (1 << AC97_SLOT_PCM_RIGHT)
1693 }
1694 }
1695 },
1696 /* MIC IN #1 */
1697 {
1698 .stream = 1,
1699 .exclusive = 1,
1700 .r = { {
1701 .slots = (1 << AC97_SLOT_MIC)
1702 }
1703 }
1704 },
1705 /* S/PDIF PCM */
1706 {
1707 .exclusive = 1,
1708 .spdif = 1,
1709 .r = { {
1710 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1711 (1 << AC97_SLOT_SPDIF_RIGHT2)
1712 }
1713 }
1714 },
1715 /* PCM IN #2 */
1716 {
1717 .stream = 1,
1718 .exclusive = 1,
1719 .r = { {
1720 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1721 (1 << AC97_SLOT_PCM_RIGHT)
1722 }
1723 }
1724 },
1725 /* MIC IN #2 */
1726 {
1727 .stream = 1,
1728 .exclusive = 1,
1729 .r = { {
1730 .slots = (1 << AC97_SLOT_MIC)
1731 }
1732 }
1733 },
1734};
1735
1736static struct ac97_quirk ac97_quirks[] __devinitdata = {
1737 {
6fd8b87f
JCD		 1738 .subvendor = 0x0e11,
1739 .subdevice = 0x008a,
1da177e4
LT		 1740 .name = "Compaq Evo W4000", /* AD1885 */
1741 .type = AC97_TUNE_HP_ONLY
1742 },
1743 {
6fd8b87f
JCD		 1744 .subvendor = 0x0e11,
1745 .subdevice = 0x00b8,
1da177e4
LT		 1746 .name = "Compaq Evo D510C",
1747 .type = AC97_TUNE_HP_ONLY
1748 },
1749 {
6fd8b87f
JCD		 1750 .subvendor = 0x0e11,
1751 .subdevice = 0x0860,
1da177e4
LT		 1752 .name = "HP/Compaq nx7010",
1753 .type = AC97_TUNE_MUTE_LED
1754 },
1755 {
6fd8b87f
JCD		 1756 .subvendor = 0x1014,
1757 .subdevice = 0x1f00,
1da177e4
LT		 1758 .name = "MS-9128",
1759 .type = AC97_TUNE_ALC_JACK
1760 },
5d529390
TI		 1761 {
1762 .subvendor = 0x1014,
1763 .subdevice = 0x0267,
1764 .name = "IBM NetVista A30p", /* AD1981B */
1765 .type = AC97_TUNE_HP_ONLY
1766 },
1da177e4 1767 {
6fd8b87f
JCD		 1768 .subvendor = 0x1028,
1769 .subdevice = 0x00d8,
1da177e4
LT		 1770 .name = "Dell Precision 530", /* AD1885 */
1771 .type = AC97_TUNE_HP_ONLY
1772 },
1773 {
6fd8b87f
JCD		 1774 .subvendor = 0x1028,
1775 .subdevice = 0x010d,
1da177e4
LT		 1776 .name = "Dell", /* which model? AD1885 */
1777 .type = AC97_TUNE_HP_ONLY
1778 },
1779 {
6fd8b87f
JCD		 1780 .subvendor = 0x1028,
1781 .subdevice = 0x0126,
1da177e4
LT		 1782 .name = "Dell Optiplex GX260", /* AD1981A */
1783 .type = AC97_TUNE_HP_ONLY
1784 },
1785 {
6fd8b87f
JCD		 1786 .subvendor = 0x1028,
1787 .subdevice = 0x012c,
1da177e4
LT		 1788 .name = "Dell Precision 650", /* AD1981A */
1789 .type = AC97_TUNE_HP_ONLY
1790 },
1791 {
6fd8b87f
JCD		 1792 .subvendor = 0x1028,
1793 .subdevice = 0x012d,
1da177e4
LT		 1794 .name = "Dell Precision 450", /* AD1981B*/
1795 .type = AC97_TUNE_HP_ONLY
1796 },
1797 {
6fd8b87f
JCD		 1798 .subvendor = 0x1028,
1799 .subdevice = 0x0147,
1da177e4
LT		 1800 .name = "Dell", /* which model? AD1981B*/
1801 .type = AC97_TUNE_HP_ONLY
1802 },
1803 {
6fd8b87f
JCD		 1804 .subvendor = 0x1028,
1805 .subdevice = 0x0163,
1da177e4
LT		 1806 .name = "Dell Unknown", /* STAC9750/51 */
1807 .type = AC97_TUNE_HP_ONLY
1808 },
1809 {
6fd8b87f
JCD		 1810 .subvendor = 0x103c,
1811 .subdevice = 0x006d,
1da177e4
LT		 1812 .name = "HP zv5000",
1813 .type = AC97_TUNE_MUTE_LED /*AD1981B*/
1814 },
1815 { /* FIXME: which codec? */
6fd8b87f
JCD		 1816 .subvendor = 0x103c,
1817 .subdevice = 0x00c3,
1da177e4
LT		 1818 .name = "HP xw6000",
1819 .type = AC97_TUNE_HP_ONLY
1820 },
1821 {
6fd8b87f
JCD		 1822 .subvendor = 0x103c,
1823 .subdevice = 0x088c,
1da177e4
LT		 1824 .name = "HP nc8000",
1825 .type = AC97_TUNE_MUTE_LED
1826 },
1827 {
6fd8b87f
JCD		 1828 .subvendor = 0x103c,
1829 .subdevice = 0x0890,
1da177e4
LT		 1830 .name = "HP nc6000",
1831 .type = AC97_TUNE_MUTE_LED
1832 },
e0c93cf3
DH		 1833 {
1834 .subvendor = 0x103c,
1835 .subdevice = 0x0934,
1836 .name = "HP nx8220",
1837 .type = AC97_TUNE_MUTE_LED
1838 },
66d10647
SV		 1839 {
1840 .subvendor = 0x103c,
1841 .subdevice = 0x099c,
1842 .name = "HP nx6110", /* AD1981B */
1843 .type = AC97_TUNE_HP_ONLY
1844 },
1da177e4 1845 {
6fd8b87f
JCD		 1846 .subvendor = 0x103c,
1847 .subdevice = 0x129d,
1da177e4
LT		 1848 .name = "HP xw8000",
1849 .type = AC97_TUNE_HP_ONLY
1850 },
1851 {
6fd8b87f
JCD		 1852 .subvendor = 0x103c,
1853 .subdevice = 0x12f1,
1da177e4
LT		 1854 .name = "HP xw8200", /* AD1981B*/
1855 .type = AC97_TUNE_HP_ONLY
1856 },
1857 {
6fd8b87f
JCD		 1858 .subvendor = 0x103c,
1859 .subdevice = 0x12f2,
1da177e4
LT		 1860 .name = "HP xw6200",
1861 .type = AC97_TUNE_HP_ONLY
1862 },
1863 {
6fd8b87f
JCD		 1864 .subvendor = 0x103c,
1865 .subdevice = 0x3008,
1da177e4
LT		 1866 .name = "HP xw4200", /* AD1981B*/
1867 .type = AC97_TUNE_HP_ONLY
1868 },
1869 {
6fd8b87f
JCD		 1870 .subvendor = 0x104d,
1871 .subdevice = 0x8197,
1da177e4
LT		 1872 .name = "Sony S1XP",
1873 .type = AC97_TUNE_INV_EAPD
1874 },
1875 {
6fd8b87f
JCD		 1876 .subvendor = 0x1043,
1877 .subdevice = 0x80f3,
1da177e4
LT		 1878 .name = "ASUS ICH5/AD1985",
1879 .type = AC97_TUNE_AD_SHARING
1880 },
1881 {
6fd8b87f
JCD		 1882 .subvendor = 0x10cf,
1883 .subdevice = 0x11c3,
1da177e4
LT		 1884 .name = "Fujitsu-Siemens E4010",
1885 .type = AC97_TUNE_HP_ONLY
1886 },
98c7f212
TI		 1887 {
1888 .subvendor = 0x10cf,
1889 .subdevice = 0x1225,
1890 .name = "Fujitsu-Siemens T3010",
1891 .type = AC97_TUNE_HP_ONLY
1892 },
1da177e4 1893 {
6fd8b87f
JCD		 1894 .subvendor = 0x10cf,
1895 .subdevice = 0x1253,
1da177e4
LT		 1896 .name = "Fujitsu S6210", /* STAC9750/51 */
1897 .type = AC97_TUNE_HP_ONLY
1898 },
9970dce5
TI		 1899 {
1900 .subvendor = 0x10cf,
1901 .subdevice = 0x12ec,
1902 .name = "Fujitsu-Siemens 4010",
1903 .type = AC97_TUNE_HP_ONLY
1904 },
1da177e4 1905 {
6fd8b87f
JCD		 1906 .subvendor = 0x10f1,
1907 .subdevice = 0x2665,
1da177e4
LT		 1908 .name = "Fujitsu-Siemens Celsius", /* AD1981? */
1909 .type = AC97_TUNE_HP_ONLY
1910 },
1911 {
6fd8b87f
JCD		 1912 .subvendor = 0x10f1,
1913 .subdevice = 0x2885,
1da177e4
LT		 1914 .name = "AMD64 Mobo", /* ALC650 */
1915 .type = AC97_TUNE_HP_ONLY
1916 },
1917 {
6fd8b87f
JCD		 1918 .subvendor = 0x110a,
1919 .subdevice = 0x0056,
1da177e4
LT		 1920 .name = "Fujitsu-Siemens Scenic", /* AD1981? */
1921 .type = AC97_TUNE_HP_ONLY
1922 },
1923 {
6fd8b87f
JCD		 1924 .subvendor = 0x11d4,
1925 .subdevice = 0x5375,
1da177e4
LT		 1926 .name = "ADI AD1985 (discrete)",
1927 .type = AC97_TUNE_HP_ONLY
1928 },
1929 {
6fd8b87f
JCD		 1930 .subvendor = 0x1462,
1931 .subdevice = 0x5470,
1da177e4
LT		 1932 .name = "MSI P4 ATX 645 Ultra",
1933 .type = AC97_TUNE_HP_ONLY
1934 },
1935 {
6fd8b87f
JCD		 1936 .subvendor = 0x1734,
1937 .subdevice = 0x0088,
1da177e4
LT		 1938 .name = "Fujitsu-Siemens D1522", /* AD1981 */
1939 .type = AC97_TUNE_HP_ONLY
1940 },
1941 {
6fd8b87f
JCD		 1942 .subvendor = 0x8086,
1943 .subdevice = 0x2000,
1da177e4
LT		 1944 .mask = 0xfff0,
1945 .name = "Intel ICH5/AD1985",
1946 .type = AC97_TUNE_AD_SHARING
1947 },
1948 {
6fd8b87f
JCD		 1949 .subvendor = 0x8086,
1950 .subdevice = 0x4000,
1da177e4
LT		 1951 .mask = 0xfff0,
1952 .name = "Intel ICH5/AD1985",
1953 .type = AC97_TUNE_AD_SHARING
1954 },
1955 {
6fd8b87f
JCD		 1956 .subvendor = 0x8086,
1957 .subdevice = 0x4856,
1da177e4
LT		 1958 .name = "Intel D845WN (82801BA)",
1959 .type = AC97_TUNE_SWAP_HP
1960 },
1961 {
6fd8b87f
JCD		 1962 .subvendor = 0x8086,
1963 .subdevice = 0x4d44,
1da177e4
LT		 1964 .name = "Intel D850EMV2", /* AD1885 */
1965 .type = AC97_TUNE_HP_ONLY
1966 },
1967 {
6fd8b87f
JCD		 1968 .subvendor = 0x8086,
1969 .subdevice = 0x4d56,
1da177e4
LT		 1970 .name = "Intel ICH/AD1885",
1971 .type = AC97_TUNE_HP_ONLY
1972 },
1973 {
6fd8b87f
JCD		 1974 .subvendor = 0x8086,
1975 .subdevice = 0x6000,
1da177e4
LT		 1976 .mask = 0xfff0,
1977 .name = "Intel ICH5/AD1985",
1978 .type = AC97_TUNE_AD_SHARING
1979 },
1980 {
6fd8b87f
JCD		 1981 .subvendor = 0x8086,
1982 .subdevice = 0xe000,
1da177e4
LT		 1983 .mask = 0xfff0,
1984 .name = "Intel ICH5/AD1985",
1985 .type = AC97_TUNE_AD_SHARING
1986 },
1987#if 0 /* FIXME: this seems wrong on most boards */
1988 {
6fd8b87f
JCD		 1989 .subvendor = 0x8086,
1990 .subdevice = 0xa000,
1da177e4
LT		 1991 .mask = 0xfff0,
1992 .name = "Intel ICH5/AD1985",
1993 .type = AC97_TUNE_HP_ONLY
1994 },
1995#endif
1996 { } /* terminator */
1997};
1998
1999static int __devinit snd_intel8x0_mixer(intel8x0_t *chip, int ac97_clock, const char *quirk_override)
2000{
2001 ac97_bus_t *pbus;
2002 ac97_template_t ac97;
2003 int err;
2004 unsigned int i, codecs;
2005 unsigned int glob_sta = 0;
2006 ac97_bus_ops_t *ops;
2007 static ac97_bus_ops_t standard_bus_ops = {
2008 .write = snd_intel8x0_codec_write,
2009 .read = snd_intel8x0_codec_read,
2010 };
2011 static ac97_bus_ops_t ali_bus_ops = {
2012 .write = snd_intel8x0_ali_codec_write,
2013 .read = snd_intel8x0_ali_codec_read,
2014 };
2015
2016 chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
2017 switch (chip->device_type) {
2018 case DEVICE_NFORCE:
2019 chip->spdif_idx = NVD_SPBAR;
2020 break;
2021 case DEVICE_ALI:
2022 chip->spdif_idx = ALID_AC97SPDIFOUT;
2023 break;
2024 case DEVICE_INTEL_ICH4:
2025 chip->spdif_idx = ICHD_SPBAR;
2026 break;
2027 };
2028
2029 chip->in_ac97_init = 1;
2030
2031 memset(&ac97, 0, sizeof(ac97));
2032 ac97.private_data = chip;
2033 ac97.private_free = snd_intel8x0_mixer_free_ac97;
2034 ac97.scaps = AC97_SCAP_SKIP_MODEM;
2035 if (chip->xbox)
2036 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
2037 if (chip->device_type != DEVICE_ALI) {
2038 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
2039 ops = &standard_bus_ops;
2040 if (chip->device_type == DEVICE_INTEL_ICH4) {
2041 codecs = 0;
2042 if (glob_sta & ICH_PCR)
2043 codecs++;
2044 if (glob_sta & ICH_SCR)
2045 codecs++;
2046 if (glob_sta & ICH_TCR)
2047 codecs++;
2048 chip->in_sdin_init = 1;
2049 for (i = 0; i < codecs; i++) {
2050 snd_intel8x0_codec_read_test(chip, i);
2051 chip->ac97_sdin[i] = igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2052 }
2053 chip->in_sdin_init = 0;
2054 } else {
2055 codecs = glob_sta & ICH_SCR ? 2 : 1;
2056 }
2057 } else {
2058 ops = &ali_bus_ops;
2059 codecs = 1;
2060 /* detect the secondary codec */
2061 for (i = 0; i < 100; i++) {
2062 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2063 if (reg & 0x40) {
2064 codecs = 2;
2065 break;
2066 }
2067 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2068 udelay(1);
2069 }
2070 }
2071 if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2072 goto __err;
2073 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
2074 pbus->shared_type = AC97_SHARED_TYPE_ICH; /* shared with modem driver */
2075 if (ac97_clock >= 8000 && ac97_clock <= 48000)
2076 pbus->clock = ac97_clock;
2077 /* FIXME: my test board doesn't work well with VRA... */
2078 if (chip->device_type == DEVICE_ALI)
2079 pbus->no_vra = 1;
2080 else
2081 pbus->dra = 1;
2082 chip->ac97_bus = pbus;
2083
2084 ac97.pci = chip->pci;
2085 for (i = 0; i < codecs; i++) {
2086 ac97.num = i;
2087 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2088 if (err != -EACCES)
2089 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);
2090 if (i == 0)
2091 goto __err;
2092 continue;
2093 }
2094 }
2095 /* tune up the primary codec */
2096 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2097 /* enable separate SDINs for ICH4 */
2098 if (chip->device_type == DEVICE_INTEL_ICH4)
2099 pbus->isdin = 1;
2100 /* find the available PCM streams */
2101 i = ARRAY_SIZE(ac97_pcm_defs);
2102 if (chip->device_type != DEVICE_INTEL_ICH4)
2103 i -= 2; /* do not allocate PCM2IN and MIC2 */
2104 if (chip->spdif_idx < 0)
2105 i--; /* do not allocate S/PDIF */
2106 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2107 if (err < 0)
2108 goto __err;
2109 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2110 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2111 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2112 if (chip->spdif_idx >= 0)
2113 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2114 if (chip->device_type == DEVICE_INTEL_ICH4) {
2115 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2116 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2117 }
2118 /* enable separate SDINs for ICH4 */
2119 if (chip->device_type == DEVICE_INTEL_ICH4) {
2120 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2121 u8 tmp = igetbyte(chip, ICHREG(SDM));
2122 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2123 if (pcm) {
2124 tmp |= ICH_SE; /* steer enable for multiple SDINs */
2125 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2126 for (i = 1; i < 4; i++) {
2127 if (pcm->r[0].codec[i]) {
2128 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2129 break;
2130 }
2131 }
2132 } else {
2133 tmp &= ~ICH_SE; /* steer disable */
2134 }
2135 iputbyte(chip, ICHREG(SDM), tmp);
2136 }
2137 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2138 chip->multi4 = 1;
2139 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE))
2140 chip->multi6 = 1;
2141 }
2142 if (pbus->pcms[0].r[1].rslots[0]) {
2143 chip->dra = 1;
2144 }
2145 if (chip->device_type == DEVICE_INTEL_ICH4) {
2146 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2147 chip->smp20bit = 1;
2148 }
2149 if (chip->device_type == DEVICE_NFORCE) {
2150 /* 48kHz only */
2151 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2152 }
2153 if (chip->device_type == DEVICE_INTEL_ICH4) {
2154 /* use slot 10/11 for SPDIF */
2155 u32 val;
2156 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2157 val |= ICH_PCM_SPDIF_1011;
2158 iputdword(chip, ICHREG(GLOB_CNT), val);
2159 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2160 }
2161 chip->in_ac97_init = 0;
2162 return 0;
2163
2164 __err:
2165 /* clear the cold-reset bit for the next chance */
2166 if (chip->device_type != DEVICE_ALI)
2167 iputdword(chip, ICHREG(GLOB_CNT), igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2168 return err;
2169}
2170
2171
2172/*
2173 *
2174 */
2175
2176static void do_ali_reset(intel8x0_t *chip)
2177{
2178 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2179 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2180 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2181 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2182 iputdword(chip, ICHREG(ALI_INTERFACECR),
2183 ICH_ALI_IF_MC|ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2184 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2185 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2186}
2187
2188#define do_delay(chip) do {\
2189 set_current_state(TASK_UNINTERRUPTIBLE);\
2190 schedule_timeout(1);\
2191} while (0)
2192
2193static int snd_intel8x0_ich_chip_init(intel8x0_t *chip, int probing)
2194{
2195 unsigned long end_time;
2196 unsigned int cnt, status, nstatus;
2197
2198 /* put logic to right state */
2199 /* first clear status bits */
2200 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2201 if (chip->device_type == DEVICE_NFORCE)
2202 status |= ICH_NVSPINT;
2203 cnt = igetdword(chip, ICHREG(GLOB_STA));
2204 iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2205
2206 /* ACLink on, 2 channels */
2207 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2208 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2209 /* finish cold or do warm reset */
2210 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2211 iputdword(chip, ICHREG(GLOB_CNT), cnt);
2212 end_time = (jiffies + (HZ / 4)) + 1;
2213 do {
2214 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2215 goto __ok;
2216 do_delay(chip);
2217 } while (time_after_eq(end_time, jiffies));
2218 snd_printk("AC'97 warm reset still in progress? [0x%x]\n", igetdword(chip, ICHREG(GLOB_CNT)));
2219 return -EIO;
2220
2221 __ok:
2222 if (probing) {
2223 /* wait for any codec ready status.
2224 * Once it becomes ready it should remain ready
2225 * as long as we do not disable the ac97 link.
2226 */
2227 end_time = jiffies + HZ;
2228 do {
2229 status = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
2230 if (status)
2231 break;
2232 do_delay(chip);
2233 } while (time_after_eq(end_time, jiffies));
2234 if (! status) {
2235 /* no codec is found */
2236 snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n", igetdword(chip, ICHREG(GLOB_STA)));
2237 return -EIO;
2238 }
2239
2240 if (chip->device_type == DEVICE_INTEL_ICH4)
2241 /* ICH4 can have three codecs */
2242 nstatus = ICH_PCR | ICH_SCR | ICH_TCR;
2243 else
2244 /* others up to two codecs */
2245 nstatus = ICH_PCR | ICH_SCR;
2246
2247 /* wait for other codecs ready status. */
2248 end_time = jiffies + HZ / 4;
2249 while (status != nstatus && time_after_eq(end_time, jiffies)) {
2250 do_delay(chip);
2251 status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus;
2252 }
2253
2254 } else {
2255 /* resume phase */
2256 int i;
2257 status = 0;
2258 for (i = 0; i < 3; i++)
2259 if (chip->ac97[i])
2260 status |= get_ich_codec_bit(chip, i);
2261 /* wait until all the probed codecs are ready */
2262 end_time = jiffies + HZ;
2263 do {
2264 nstatus = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
2265 if (status == nstatus)
2266 break;
2267 do_delay(chip);
2268 } while (time_after_eq(end_time, jiffies));
2269 }
2270
2271 if (chip->device_type == DEVICE_SIS) {
2272 /* unmute the output on SIS7012 */
2273 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2274 }
2275 if (chip->device_type == DEVICE_NFORCE) {
2276 /* enable SPDIF interrupt */
2277 unsigned int val;
2278 pci_read_config_dword(chip->pci, 0x4c, &val);
2279 val |= 0x1000000;
2280 pci_write_config_dword(chip->pci, 0x4c, val);
2281 }
2282 return 0;
2283}
2284
2285static int snd_intel8x0_ali_chip_init(intel8x0_t *chip, int probing)
2286{
2287 u32 reg;
2288 int i = 0;
2289
2290 reg = igetdword(chip, ICHREG(ALI_SCR));
2291 if ((reg & 2) == 0) /* Cold required */
2292 reg |= 2;
2293 else
2294 reg |= 1; /* Warm */
2295 reg &= ~0x80000000; /* ACLink on */
2296 iputdword(chip, ICHREG(ALI_SCR), reg);
2297
2298 for (i = 0; i < HZ / 2; i++) {
2299 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2300 goto __ok;
2301 do_delay(chip);
2302 }
2303 snd_printk(KERN_ERR "AC'97 reset failed.\n");
2304 if (probing)
2305 return -EIO;
2306
2307 __ok:
2308 for (i = 0; i < HZ / 2; i++) {
2309 reg = igetdword(chip, ICHREG(ALI_RTSR));
2310 if (reg & 0x80) /* primary codec */
2311 break;
2312 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2313 do_delay(chip);
2314 }
2315
2316 do_ali_reset(chip);
2317 return 0;
2318}
2319
2320static int snd_intel8x0_chip_init(intel8x0_t *chip, int probing)
2321{
2322 unsigned int i;
2323 int err;
2324
2325 if (chip->device_type != DEVICE_ALI) {
2326 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2327 return err;
2328 iagetword(chip, 0); /* clear semaphore flag */
2329 } else {
2330 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2331 return err;
2332 }
2333
2334 /* disable interrupts */
2335 for (i = 0; i < chip->bdbars_count; i++)
2336 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2337 /* reset channels */
2338 for (i = 0; i < chip->bdbars_count; i++)
2339 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2340 /* initialize Buffer Descriptor Lists */
2341 for (i = 0; i < chip->bdbars_count; i++)
2342 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr);
2343 return 0;
2344}
2345
2346static int snd_intel8x0_free(intel8x0_t *chip)
2347{
2348 unsigned int i;
2349
2350 if (chip->irq < 0)
2351 goto __hw_end;
2352 /* disable interrupts */
2353 for (i = 0; i < chip->bdbars_count; i++)
2354 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2355 /* reset channels */
2356 for (i = 0; i < chip->bdbars_count; i++)
2357 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2358 if (chip->device_type == DEVICE_NFORCE) {
2359 /* stop the spdif interrupt */
2360 unsigned int val;
2361 pci_read_config_dword(chip->pci, 0x4c, &val);
2362 val &= ~0x1000000;
2363 pci_write_config_dword(chip->pci, 0x4c, val);
2364 }
2365 /* --- */
2366 synchronize_irq(chip->irq);
2367 __hw_end:
2368 if (chip->irq >= 0)
2369 free_irq(chip->irq, (void *)chip);
2370 if (chip->bdbars.area) {
2371 if (chip->fix_nocache)
2372 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
2373 snd_dma_free_pages(&chip->bdbars);
2374 }
2375 if (chip->remap_addr)
2376 iounmap(chip->remap_addr);
2377 if (chip->remap_bmaddr)
2378 iounmap(chip->remap_bmaddr);
2379 pci_release_regions(chip->pci);
2380 pci_disable_device(chip->pci);
2381 kfree(chip);
2382 return 0;
2383}
2384
2385#ifdef CONFIG_PM
2386/*
2387 * power management
2388 */
2389static int intel8x0_suspend(snd_card_t *card, pm_message_t state)
2390{
2391 intel8x0_t *chip = card->pm_private_data;
2392 int i;
2393
2394 for (i = 0; i < chip->pcm_devs; i++)
2395 snd_pcm_suspend_all(chip->pcm[i]);
2396 /* clear nocache */
2397 if (chip->fix_nocache) {
2398 for (i = 0; i < chip->bdbars_count; i++) {
2399 ichdev_t *ichdev = &chip->ichd[i];
2400 if (ichdev->substream && ichdev->page_attr_changed) {
2401 snd_pcm_runtime_t *runtime = ichdev->substream->runtime;
2402 if (runtime->dma_area)
2403 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0);
2404 }
2405 }
2406 }
2407 for (i = 0; i < 3; i++)
2408 if (chip->ac97[i])
2409 snd_ac97_suspend(chip->ac97[i]);
52b72388
TI		 2410 if (chip->device_type == DEVICE_INTEL_ICH4)
2411 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
adbedd34 2412
90158b83
RW		 2413 if (chip->irq >= 0)
2414 free_irq(chip->irq, (void *)chip);
1da177e4
LT		 2415 pci_disable_device(chip->pci);
2416 return 0;
2417}
2418
2419static int intel8x0_resume(snd_card_t *card)
2420{
2421 intel8x0_t *chip = card->pm_private_data;
2422 int i;
2423
2424 pci_enable_device(chip->pci);
2425 pci_set_master(chip->pci);
90158b83
RW		 2426 request_irq(chip->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip);
2427 synchronize_irq(chip->irq);
2428 snd_intel8x0_chip_init(chip, 1);
1da177e4 2429
52b72388
TI		 2430 /* re-initialize mixer stuff */
2431 if (chip->device_type == DEVICE_INTEL_ICH4) {
2432 /* enable separate SDINs for ICH4 */
2433 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2434 /* use slot 10/11 for SPDIF */
2435 iputdword(chip, ICHREG(GLOB_CNT),
2436 (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2437 ICH_PCM_SPDIF_1011);
2438 }
2439
1da177e4
LT		 2440 /* refill nocache */
2441 if (chip->fix_nocache)
2442 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2443
2444 for (i = 0; i < 3; i++)
2445 if (chip->ac97[i])
2446 snd_ac97_resume(chip->ac97[i]);
2447
2448 /* refill nocache */
2449 if (chip->fix_nocache) {
2450 for (i = 0; i < chip->bdbars_count; i++) {
2451 ichdev_t *ichdev = &chip->ichd[i];
2452 if (ichdev->substream && ichdev->page_attr_changed) {
2453 snd_pcm_runtime_t *runtime = ichdev->substream->runtime;
2454 if (runtime->dma_area)
2455 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
2456 }
2457 }
2458 }
2459
1cfe43d2
TI		 2460 /* resume status */
2461 for (i = 0; i < chip->bdbars_count; i++) {
2462 ichdev_t *ichdev = &chip->ichd[i];
2463 unsigned long port = ichdev->reg_offset;
2464 if (! ichdev->substream || ! ichdev->suspended)
2465 continue;
2466 if (ichdev->ichd == ICHD_PCMOUT)
2467 snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2468 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2469 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2470 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2471 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2472 }
2473
1da177e4
LT		 2474 return 0;
2475}
2476#endif /* CONFIG_PM */
2477
2478#define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */
2479
2480static void __devinit intel8x0_measure_ac97_clock(intel8x0_t *chip)
2481{
2482 snd_pcm_substream_t *subs;
2483 ichdev_t *ichdev;
2484 unsigned long port;
2485 unsigned long pos, t;
2486 struct timeval start_time, stop_time;
2487
2488 if (chip->ac97_bus->clock != 48000)
2489 return; /* specified in module option */
2490
2491 subs = chip->pcm[0]->streams[0].substream;
2492 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2493 snd_printk("no playback buffer allocated - aborting measure ac97 clock\n");
2494 return;
2495 }
2496 ichdev = &chip->ichd[ICHD_PCMOUT];
2497 ichdev->physbuf = subs->dma_buffer.addr;
2498 ichdev->size = chip->ichd[ICHD_PCMOUT].fragsize = INTEL8X0_TESTBUF_SIZE;
2499 ichdev->substream = NULL; /* don't process interrupts */
2500
2501 /* set rate */
2502 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2503 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock);
2504 return;
2505 }
2506 snd_intel8x0_setup_periods(chip, ichdev);
2507 port = ichdev->reg_offset;
2508 spin_lock_irq(&chip->reg_lock);
2509 chip->in_measurement = 1;
2510 /* trigger */
2511 if (chip->device_type != DEVICE_ALI)
2512 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2513 else {
2514 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2515 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2516 }
2517 do_gettimeofday(&start_time);
2518 spin_unlock_irq(&chip->reg_lock);
ef21ca24 2519 msleep(50);
1da177e4
LT		 2520 spin_lock_irq(&chip->reg_lock);
2521 /* check the position */
2522 pos = ichdev->fragsize1;
2523 pos -= igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << ichdev->pos_shift;
2524 pos += ichdev->position;
2525 chip->in_measurement = 0;
2526 do_gettimeofday(&stop_time);
2527 /* stop */
2528 if (chip->device_type == DEVICE_ALI) {
2529 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 8));
2530 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2531 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2532 ;
2533 } else {
2534 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2535 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2536 ;
2537 }
2538 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2539 spin_unlock_irq(&chip->reg_lock);
2540
2541 t = stop_time.tv_sec - start_time.tv_sec;
2542 t *= 1000000;
2543 t += stop_time.tv_usec - start_time.tv_usec;
2544 printk(KERN_INFO "%s: measured %lu usecs\n", __FUNCTION__, t);
2545 if (t == 0) {
2546 snd_printk(KERN_ERR "?? calculation error..\n");
2547 return;
2548 }
2549 pos = (pos / 4) * 1000;
2550 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2551 if (pos < 40000 || pos >= 60000)
2552 /* abnormal value. hw problem? */
2553 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos);
2554 else if (pos < 47500 || pos > 48500)
2555 /* not 48000Hz, tuning the clock.. */
2556 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2557 printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
2558}
2559
2560static void snd_intel8x0_proc_read(snd_info_entry_t * entry,
2561 snd_info_buffer_t * buffer)
2562{
2563 intel8x0_t *chip = entry->private_data;
2564 unsigned int tmp;
2565
2566 snd_iprintf(buffer, "Intel8x0\n\n");
2567 if (chip->device_type == DEVICE_ALI)
2568 return;
2569 tmp = igetdword(chip, ICHREG(GLOB_STA));
2570 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2571 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
2572 if (chip->device_type == DEVICE_INTEL_ICH4)
2573 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2574 snd_iprintf(buffer, "AC'97 codecs ready :%s%s%s%s\n",
2575 tmp & ICH_PCR ? " primary" : "",
2576 tmp & ICH_SCR ? " secondary" : "",
2577 tmp & ICH_TCR ? " tertiary" : "",
2578 (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : "");
2579 if (chip->device_type == DEVICE_INTEL_ICH4)
2580 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n",
2581 chip->ac97_sdin[0],
2582 chip->ac97_sdin[1],
2583 chip->ac97_sdin[2]);
2584}
2585
2586static void __devinit snd_intel8x0_proc_init(intel8x0_t * chip)
2587{
2588 snd_info_entry_t *entry;
2589
2590 if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
2591 snd_info_set_text_ops(entry, chip, 1024, snd_intel8x0_proc_read);
2592}
2593
2594static int snd_intel8x0_dev_free(snd_device_t *device)
2595{
2596 intel8x0_t *chip = device->device_data;
2597 return snd_intel8x0_free(chip);
2598}
2599
2600struct ich_reg_info {
2601 unsigned int int_sta_mask;
2602 unsigned int offset;
2603};
2604
2605static int __devinit snd_intel8x0_create(snd_card_t * card,
2606 struct pci_dev *pci,
2607 unsigned long device_type,
2608 intel8x0_t ** r_intel8x0)
2609{
2610 intel8x0_t *chip;
2611 int err;
2612 unsigned int i;
2613 unsigned int int_sta_masks;
2614 ichdev_t *ichdev;
2615 static snd_device_ops_t ops = {
2616 .dev_free = snd_intel8x0_dev_free,
2617 };
2618
2619 static unsigned int bdbars[] = {
2620 3, /* DEVICE_INTEL */
2621 6, /* DEVICE_INTEL_ICH4 */
2622 3, /* DEVICE_SIS */
2623 6, /* DEVICE_ALI */
2624 4, /* DEVICE_NFORCE */
2625 };
2626 static struct ich_reg_info intel_regs[6] = {
2627 { ICH_PIINT, 0 },
2628 { ICH_POINT, 0x10 },
2629 { ICH_MCINT, 0x20 },
2630 { ICH_M2INT, 0x40 },
2631 { ICH_P2INT, 0x50 },
2632 { ICH_SPINT, 0x60 },
2633 };
2634 static struct ich_reg_info nforce_regs[4] = {
2635 { ICH_PIINT, 0 },
2636 { ICH_POINT, 0x10 },
2637 { ICH_MCINT, 0x20 },
2638 { ICH_NVSPINT, 0x70 },
2639 };
2640 static struct ich_reg_info ali_regs[6] = {
2641 { ALI_INT_PCMIN, 0x40 },
2642 { ALI_INT_PCMOUT, 0x50 },
2643 { ALI_INT_MICIN, 0x60 },
2644 { ALI_INT_CODECSPDIFOUT, 0x70 },
2645 { ALI_INT_SPDIFIN, 0xa0 },
2646 { ALI_INT_SPDIFOUT, 0xb0 },
2647 };
2648 struct ich_reg_info *tbl;
2649
2650 *r_intel8x0 = NULL;
2651
2652 if ((err = pci_enable_device(pci)) < 0)
2653 return err;
2654
2655 chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
2656 if (chip == NULL) {
2657 pci_disable_device(pci);
2658 return -ENOMEM;
2659 }
2660 spin_lock_init(&chip->reg_lock);
2661 chip->device_type = device_type;
2662 chip->card = card;
2663 chip->pci = pci;
2664 chip->irq = -1;
2665
2666 if (pci->vendor == PCI_VENDOR_ID_INTEL &&
2667 pci->device == PCI_DEVICE_ID_INTEL_440MX)
2668 chip->fix_nocache = 1; /* enable workaround */
2669
2670 /* some Nforce[2] and ICH boards have problems with IRQ handling.
2671 * Needs to return IRQ_HANDLED for unknown irqs.
2672 */
2673 if (device_type == DEVICE_NFORCE)
2674 chip->buggy_irq = 1;
2675
2676 if ((err = pci_request_regions(pci, card->shortname)) < 0) {
2677 kfree(chip);
2678 pci_disable_device(pci);
2679 return err;
2680 }
2681
2682 if (device_type == DEVICE_ALI) {
2683 /* ALI5455 has no ac97 region */
2684 chip->bmaddr = pci_resource_start(pci, 0);
2685 goto port_inited;
2686 }
2687
2688 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) { /* ICH4 and Nforce */
2689 chip->mmio = 1;
2690 chip->addr = pci_resource_start(pci, 2);
2691 chip->remap_addr = ioremap_nocache(chip->addr,
2692 pci_resource_len(pci, 2));
2693 if (chip->remap_addr == NULL) {
2694 snd_printk("AC'97 space ioremap problem\n");
2695 snd_intel8x0_free(chip);
2696 return -EIO;
2697 }
2698 } else {
2699 chip->addr = pci_resource_start(pci, 0);
2700 }
2701 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) { /* ICH4 */
2702 chip->bm_mmio = 1;
2703 chip->bmaddr = pci_resource_start(pci, 3);
2704 chip->remap_bmaddr = ioremap_nocache(chip->bmaddr,
2705 pci_resource_len(pci, 3));
2706 if (chip->remap_bmaddr == NULL) {
2707 snd_printk("Controller space ioremap problem\n");
2708 snd_intel8x0_free(chip);
2709 return -EIO;
2710 }
2711 } else {
2712 chip->bmaddr = pci_resource_start(pci, 1);
2713 }
2714
2715 port_inited:
2716 if (request_irq(pci->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip)) {
2717 snd_printk("unable to grab IRQ %d\n", pci->irq);
2718 snd_intel8x0_free(chip);
2719 return -EBUSY;
2720 }
2721 chip->irq = pci->irq;
2722 pci_set_master(pci);
2723 synchronize_irq(chip->irq);
2724
2725 chip->bdbars_count = bdbars[device_type];
2726
2727 /* initialize offsets */
2728 switch (device_type) {
2729 case DEVICE_NFORCE:
2730 tbl = nforce_regs;
2731 break;
2732 case DEVICE_ALI:
2733 tbl = ali_regs;
2734 break;
2735 default:
2736 tbl = intel_regs;
2737 break;
2738 }
2739 for (i = 0; i < chip->bdbars_count; i++) {
2740 ichdev = &chip->ichd[i];
2741 ichdev->ichd = i;
2742 ichdev->reg_offset = tbl[i].offset;
2743 ichdev->int_sta_mask = tbl[i].int_sta_mask;
2744 if (device_type == DEVICE_SIS) {
2745 /* SiS 7012 swaps the registers */
2746 ichdev->roff_sr = ICH_REG_OFF_PICB;
2747 ichdev->roff_picb = ICH_REG_OFF_SR;
2748 } else {
2749 ichdev->roff_sr = ICH_REG_OFF_SR;
2750 ichdev->roff_picb = ICH_REG_OFF_PICB;
2751 }
2752 if (device_type == DEVICE_ALI)
2753 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
2754 /* SIS7012 handles the pcm data in bytes, others are in samples */
2755 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
2756 }
2757
2758 /* allocate buffer descriptor lists */
2759 /* the start of each lists must be aligned to 8 bytes */
2760 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
2761 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
2762 &chip->bdbars) < 0) {
2763 snd_intel8x0_free(chip);
2764 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n");
2765 return -ENOMEM;
2766 }
2767 /* tables must be aligned to 8 bytes here, but the kernel pages
2768 are much bigger, so we don't care (on i386) */
2769 /* workaround for 440MX */
2770 if (chip->fix_nocache)
2771 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2772 int_sta_masks = 0;
2773 for (i = 0; i < chip->bdbars_count; i++) {
2774 ichdev = &chip->ichd[i];
2775 ichdev->bdbar = ((u32 *)chip->bdbars.area) + (i * ICH_MAX_FRAGS * 2);
2776 ichdev->bdbar_addr = chip->bdbars.addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
2777 int_sta_masks |= ichdev->int_sta_mask;
2778 }
2779 chip->int_sta_reg = device_type == DEVICE_ALI ? ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
2780 chip->int_sta_mask = int_sta_masks;
2781
2782 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
2783 snd_intel8x0_free(chip);
2784 return err;
2785 }
2786
2787 snd_card_set_pm_callback(card, intel8x0_suspend, intel8x0_resume, chip);
2788
2789 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2790 snd_intel8x0_free(chip);
2791 return err;
2792 }
2793
2794 snd_card_set_dev(card, &pci->dev);
2795
2796 *r_intel8x0 = chip;
2797 return 0;
2798}
2799
2800static struct shortname_table {
2801 unsigned int id;
2802 const char *s;
2803} shortnames[] __devinitdata = {
2804 { PCI_DEVICE_ID_INTEL_82801, "Intel 82801AA-ICH" },
2805 { PCI_DEVICE_ID_INTEL_82901, "Intel 82901AB-ICH0" },
2806 { PCI_DEVICE_ID_INTEL_82801BA, "Intel 82801BA-ICH2" },
2807 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
2808 { PCI_DEVICE_ID_INTEL_ICH3, "Intel 82801CA-ICH3" },
2809 { PCI_DEVICE_ID_INTEL_ICH4, "Intel 82801DB-ICH4" },
2810 { PCI_DEVICE_ID_INTEL_ICH5, "Intel ICH5" },
2811 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
2812 { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
2813 { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
3437c5df 2814 { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
1da177e4
LT		 2815 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
2816 { PCI_DEVICE_ID_NVIDIA_MCP_AUDIO, "NVidia nForce" },
2817 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
2818 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
2819 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
2820 { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
2821 { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
2822 { 0x003a, "NVidia MCP04" },
2823 { 0x746d, "AMD AMD8111" },
2824 { 0x7445, "AMD AMD768" },
2825 { 0x5455, "ALi M5455" },
2826 { 0, NULL },
2827};
2828
2829static int __devinit snd_intel8x0_probe(struct pci_dev *pci,
2830 const struct pci_device_id *pci_id)
2831{
2832 static int dev;
2833 snd_card_t *card;
2834 intel8x0_t *chip;
2835 int err;
2836 struct shortname_table *name;
2837
2838 if (dev >= SNDRV_CARDS)
2839 return -ENODEV;
2840 if (!enable[dev]) {
2841 dev++;
2842 return -ENOENT;
2843 }
2844
2845 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2846 if (card == NULL)
2847 return -ENOMEM;
2848
2849 switch (pci_id->driver_data) {
2850 case DEVICE_NFORCE:
2851 strcpy(card->driver, "NFORCE");
2852 break;
2853 case DEVICE_INTEL_ICH4:
2854 strcpy(card->driver, "ICH4");
2855 break;
2856 default:
2857 strcpy(card->driver, "ICH");
2858 break;
2859 }
2860
2861 strcpy(card->shortname, "Intel ICH");
2862 for (name = shortnames; name->id; name++) {
2863 if (pci->device == name->id) {
2864 strcpy(card->shortname, name->s);
2865 break;
2866 }
2867 }
2868
2869 if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data, &chip)) < 0) {
2870 snd_card_free(card);
2871 return err;
2872 }
2873 if (buggy_irq[dev])
2874 chip->buggy_irq = 1;
2875 if (xbox[dev])
2876 chip->xbox = 1;
2877
2878 if ((err = snd_intel8x0_mixer(chip, ac97_clock[dev], ac97_quirk[dev])) < 0) {
2879 snd_card_free(card);
2880 return err;
2881 }
2882 if ((err = snd_intel8x0_pcm(chip)) < 0) {
2883 snd_card_free(card);
2884 return err;
2885 }
2886
2887 snd_intel8x0_proc_init(chip);
2888
2889 snprintf(card->longname, sizeof(card->longname),
2890 "%s with %s at %#lx, irq %i", card->shortname,
2891 snd_ac97_get_short_name(chip->ac97[0]), chip->addr, chip->irq);
2892
2893 if (! ac97_clock[dev])
2894 intel8x0_measure_ac97_clock(chip);
2895
2896 if ((err = snd_card_register(card)) < 0) {
2897 snd_card_free(card);
2898 return err;
2899 }
2900 pci_set_drvdata(pci, card);
2901 dev++;
2902 return 0;
2903}
2904
2905static void __devexit snd_intel8x0_remove(struct pci_dev *pci)
2906{
2907 snd_card_free(pci_get_drvdata(pci));
2908 pci_set_drvdata(pci, NULL);
2909}
2910
2911static struct pci_driver driver = {
2912 .name = "Intel ICH",
2913 .id_table = snd_intel8x0_ids,
2914 .probe = snd_intel8x0_probe,
2915 .remove = __devexit_p(snd_intel8x0_remove),
2916 SND_PCI_PM_CALLBACKS
2917};
2918
2919
2920static int __init alsa_card_intel8x0_init(void)
2921{
01d25d46 2922 return pci_register_driver(&driver);
1da177e4
LT		 2923}
2924
2925static void __exit alsa_card_intel8x0_exit(void)
2926{
2927 pci_unregister_driver(&driver);
2928}
2929
2930module_init(alsa_card_intel8x0_init)
2931module_exit(alsa_card_intel8x0_exit)
Linux 6.x block layer and io_uring tree(s)