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[ALSA] sound: align device drivers menus
[linux-2.6-block.git] / sound / pci / intel8x0.c
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1da177e4
LT		 1/*
2 * ALSA driver for Intel ICH (i8x0) chipsets
3 *
4 * Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
5 *
6 *
7 * This code also contains alpha support for SiS 735 chipsets provided
8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
9 * for SiS735, so the code is not fully functional.
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25
26 *
27 */
28
29#include <sound/driver.h>
30#include <asm/io.h>
31#include <linux/delay.h>
32#include <linux/interrupt.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/slab.h>
36#include <linux/moduleparam.h>
37#include <sound/core.h>
38#include <sound/pcm.h>
39#include <sound/ac97_codec.h>
40#include <sound/info.h>
41#include <sound/initval.h>
42/* for 440MX workaround */
43#include <asm/pgtable.h>
44#include <asm/cacheflush.h>
45
46MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
47MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
48MODULE_LICENSE("GPL");
49MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
50 "{Intel,82901AB-ICH0},"
51 "{Intel,82801BA-ICH2},"
52 "{Intel,82801CA-ICH3},"
53 "{Intel,82801DB-ICH4},"
54 "{Intel,ICH5},"
55 "{Intel,ICH6},"
56 "{Intel,ICH7},"
57 "{Intel,6300ESB},"
c4c8ea94 58 "{Intel,ESB2},"
1da177e4
LT		 59 "{Intel,MX440},"
60 "{SiS,SI7012},"
61 "{NVidia,nForce Audio},"
62 "{NVidia,nForce2 Audio},"
63 "{AMD,AMD768},"
64 "{AMD,AMD8111},"
65 "{ALI,M5455}}");
66
67static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
68static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
69static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
70static int ac97_clock[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 0};
71static char *ac97_quirk[SNDRV_CARDS];
a06147d2 72static int buggy_semaphore[SNDRV_CARDS];
1da177e4
LT		 73static int buggy_irq[SNDRV_CARDS];
74static int xbox[SNDRV_CARDS];
75
76#ifdef SUPPORT_MIDI
77static int mpu_port[SNDRV_CARDS]; /* disabled */
78#endif
79
80module_param_array(index, int, NULL, 0444);
81MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
82module_param_array(id, charp, NULL, 0444);
83MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
84module_param_array(enable, bool, NULL, 0444);
85MODULE_PARM_DESC(enable, "Enable Intel i8x0 soundcard.");
86module_param_array(ac97_clock, int, NULL, 0444);
87MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
88module_param_array(ac97_quirk, charp, NULL, 0444);
89MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
a06147d2
TI		 90module_param_array(buggy_semaphore, bool, NULL, 0444);
91MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
1da177e4
LT		 92module_param_array(buggy_irq, bool, NULL, 0444);
93MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
94module_param_array(xbox, bool, NULL, 0444);
95MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
96
97/*
98 * Direct registers
99 */
1da177e4
LT		 100enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
101
102#define ICHREG(x) ICH_REG_##x
103
104#define DEFINE_REGSET(name,base) \
105enum { \
106 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
107 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
108 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
109 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
110 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
111 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
112 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
113};
114
115/* busmaster blocks */
116DEFINE_REGSET(OFF, 0); /* offset */
117DEFINE_REGSET(PI, 0x00); /* PCM in */
118DEFINE_REGSET(PO, 0x10); /* PCM out */
119DEFINE_REGSET(MC, 0x20); /* Mic in */
120
121/* ICH4 busmaster blocks */
122DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */
123DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */
124DEFINE_REGSET(SP, 0x60); /* SPDIF out */
125
126/* values for each busmaster block */
127
128/* LVI */
129#define ICH_REG_LVI_MASK 0x1f
130
131/* SR */
132#define ICH_FIFOE 0x10 /* FIFO error */
133#define ICH_BCIS 0x08 /* buffer completion interrupt status */
134#define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
135#define ICH_CELV 0x02 /* current equals last valid */
136#define ICH_DCH 0x01 /* DMA controller halted */
137
138/* PIV */
139#define ICH_REG_PIV_MASK 0x1f /* mask */
140
141/* CR */
142#define ICH_IOCE 0x10 /* interrupt on completion enable */
143#define ICH_FEIE 0x08 /* fifo error interrupt enable */
144#define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
145#define ICH_RESETREGS 0x02 /* reset busmaster registers */
146#define ICH_STARTBM 0x01 /* start busmaster operation */
147
148
149/* global block */
150#define ICH_REG_GLOB_CNT 0x2c /* dword - global control */
151#define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */
152#define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */
153#define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */
154#define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */
155#define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */
156#define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */
157#define ICH_PCM_246_MASK 0x00300000 /* 6 channels (not all chips) */
158#define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */
159#define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */
160#define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */
161#define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */
162#define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */
163#define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */
164#define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */
165#define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
166#define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
167#define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
168#define ICH_ACLINK 0x00000008 /* AClink shut off */
169#define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
170#define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
171#define ICH_GIE 0x00000001 /* GPI interrupt enable */
172#define ICH_REG_GLOB_STA 0x30 /* dword - global status */
173#define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
174#define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
175#define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
176#define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
177#define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
178#define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
179#define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
180#define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */
181#define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
182#define ICH_MD3 0x00020000 /* modem power down semaphore */
183#define ICH_AD3 0x00010000 /* audio power down semaphore */
184#define ICH_RCS 0x00008000 /* read completion status */
185#define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
186#define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
187#define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
188#define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
189#define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
190#define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
191#define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
192#define ICH_MCINT 0x00000080 /* MIC capture interrupt */
193#define ICH_POINT 0x00000040 /* playback interrupt */
194#define ICH_PIINT 0x00000020 /* capture interrupt */
195#define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
196#define ICH_MOINT 0x00000004 /* modem playback interrupt */
197#define ICH_MIINT 0x00000002 /* modem capture interrupt */
198#define ICH_GSCI 0x00000001 /* GPI status change interrupt */
199#define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */
200#define ICH_CAS 0x01 /* codec access semaphore */
201#define ICH_REG_SDM 0x80
202#define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */
203#define ICH_DI2L_SHIFT 6
204#define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */
205#define ICH_DI1L_SHIFT 4
206#define ICH_SE 0x00000008 /* steer enable */
207#define ICH_LDI_MASK 0x00000003 /* last codec read data input */
208
209#define ICH_MAX_FRAGS 32 /* max hw frags */
210
211
212/*
213 * registers for Ali5455
214 */
215
216/* ALi 5455 busmaster blocks */
217DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */
218DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */
219DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */
220DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */
221DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */
222DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */
223DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */
224DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */
225DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */
226DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */
227DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */
228
229enum {
230 ICH_REG_ALI_SCR = 0x00, /* System Control Register */
231 ICH_REG_ALI_SSR = 0x04, /* System Status Register */
232 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */
233 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */
234 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
235 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
236 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */
237 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */
238 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */
239 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */
240 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */
241 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */
242 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */
243 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */
244 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */
245 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */
246 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */
247 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */
248 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */
249 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */
250 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */
251};
252
253#define ALI_CAS_SEM_BUSY 0x80000000
254#define ALI_CPR_ADDR_SECONDARY 0x100
255#define ALI_CPR_ADDR_READ 0x80
256#define ALI_CSPSR_CODEC_READY 0x08
257#define ALI_CSPSR_READ_OK 0x02
258#define ALI_CSPSR_WRITE_OK 0x01
259
260/* interrupts for the whole chip by interrupt status register finish */
261
262#define ALI_INT_MICIN2 (1<<26)
263#define ALI_INT_PCMIN2 (1<<25)
264#define ALI_INT_I2SIN (1<<24)
265#define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */
266#define ALI_INT_SPDIFIN (1<<22)
267#define ALI_INT_LFEOUT (1<<21)
268#define ALI_INT_CENTEROUT (1<<20)
269#define ALI_INT_CODECSPDIFOUT (1<<19)
270#define ALI_INT_MICIN (1<<18)
271#define ALI_INT_PCMOUT (1<<17)
272#define ALI_INT_PCMIN (1<<16)
273#define ALI_INT_CPRAIS (1<<7) /* command port available */
274#define ALI_INT_SPRAIS (1<<5) /* status port available */
275#define ALI_INT_GPIO (1<<1)
276#define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
277
278#define ICH_ALI_SC_RESET (1<<31) /* master reset */
279#define ICH_ALI_SC_AC97_DBL (1<<30)
280#define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
281#define ICH_ALI_SC_IN_BITS (3<<18)
282#define ICH_ALI_SC_OUT_BITS (3<<16)
283#define ICH_ALI_SC_6CH_CFG (3<<14)
284#define ICH_ALI_SC_PCM_4 (1<<8)
285#define ICH_ALI_SC_PCM_6 (2<<8)
286#define ICH_ALI_SC_PCM_246_MASK (3<<8)
287
288#define ICH_ALI_SS_SEC_ID (3<<5)
289#define ICH_ALI_SS_PRI_ID (3<<3)
290
291#define ICH_ALI_IF_AC97SP (1<<21)
292#define ICH_ALI_IF_MC (1<<20)
293#define ICH_ALI_IF_PI (1<<19)
294#define ICH_ALI_IF_MC2 (1<<18)
295#define ICH_ALI_IF_PI2 (1<<17)
296#define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */
297#define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */
298#define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
299#define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */
300#define ICH_ALI_IF_PO_SPDF (1<<3)
301#define ICH_ALI_IF_PO (1<<1)
302
303/*
304 *
305 */
306
307enum { ICHD_PCMIN, ICHD_PCMOUT, ICHD_MIC, ICHD_MIC2, ICHD_PCM2IN, ICHD_SPBAR, ICHD_LAST = ICHD_SPBAR };
308enum { NVD_PCMIN, NVD_PCMOUT, NVD_MIC, NVD_SPBAR, NVD_LAST = NVD_SPBAR };
309enum { ALID_PCMIN, ALID_PCMOUT, ALID_MIC, ALID_AC97SPDIFOUT, ALID_SPDIFIN, ALID_SPDIFOUT, ALID_LAST = ALID_SPDIFOUT };
310
311#define get_ichdev(substream) (ichdev_t *)(substream->runtime->private_data)
312
313typedef struct {
314 unsigned int ichd; /* ich device number */
315 unsigned long reg_offset; /* offset to bmaddr */
316 u32 *bdbar; /* CPU address (32bit) */
317 unsigned int bdbar_addr; /* PCI bus address (32bit) */
318 snd_pcm_substream_t *substream;
319 unsigned int physbuf; /* physical address (32bit) */
320 unsigned int size;
321 unsigned int fragsize;
322 unsigned int fragsize1;
323 unsigned int position;
324 unsigned int pos_shift;
325 int frags;
326 int lvi;
327 int lvi_frag;
328 int civ;
329 int ack;
330 int ack_reload;
331 unsigned int ack_bit;
332 unsigned int roff_sr;
333 unsigned int roff_picb;
334 unsigned int int_sta_mask; /* interrupt status mask */
335 unsigned int ali_slot; /* ALI DMA slot */
336 struct ac97_pcm *pcm;
337 int pcm_open_flag;
338 unsigned int page_attr_changed: 1;
1cfe43d2 339 unsigned int suspended: 1;
1da177e4
LT		 340} ichdev_t;
341
342typedef struct _snd_intel8x0 intel8x0_t;
343
344struct _snd_intel8x0 {
345 unsigned int device_type;
346
347 int irq;
348
349 unsigned int mmio;
350 unsigned long addr;
351 void __iomem *remap_addr;
352 unsigned int bm_mmio;
353 unsigned long bmaddr;
354 void __iomem *remap_bmaddr;
355
356 struct pci_dev *pci;
357 snd_card_t *card;
358
359 int pcm_devs;
360 snd_pcm_t *pcm[6];
361 ichdev_t ichd[6];
362
363 unsigned multi4: 1,
364 multi6: 1,
365 dra: 1,
366 smp20bit: 1;
367 unsigned in_ac97_init: 1,
368 in_sdin_init: 1;
369 unsigned in_measurement: 1; /* during ac97 clock measurement */
370 unsigned fix_nocache: 1; /* workaround for 440MX */
371 unsigned buggy_irq: 1; /* workaround for buggy mobos */
372 unsigned xbox: 1; /* workaround for Xbox AC'97 detection */
a06147d2 373 unsigned buggy_semaphore: 1; /* workaround for buggy codec semaphore */
1da177e4
LT		 374
375 int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
52b72388 376 unsigned int sdm_saved; /* SDM reg value */
1da177e4
LT		 377
378 ac97_bus_t *ac97_bus;
379 ac97_t *ac97[3];
380 unsigned int ac97_sdin[3];
381
382 spinlock_t reg_lock;
383
384 u32 bdbars_count;
385 struct snd_dma_buffer bdbars;
386 u32 int_sta_reg; /* interrupt status register */
387 u32 int_sta_mask; /* interrupt status mask */
388};
389
390static struct pci_device_id snd_intel8x0_ids[] = {
391 { 0x8086, 0x2415, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
392 { 0x8086, 0x2425, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
393 { 0x8086, 0x2445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
394 { 0x8086, 0x2485, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
395 { 0x8086, 0x24c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH4 */
396 { 0x8086, 0x24d5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH5 */
397 { 0x8086, 0x25a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB */
398 { 0x8086, 0x266e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH6 */
399 { 0x8086, 0x27de, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH7 */
c4c8ea94 400 { 0x8086, 0x2698, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB2 */
1da177e4
LT		 401 { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
402 { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS }, /* SI7012 */
403 { 0x10de, 0x01b1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE */
404 { 0x10de, 0x003a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* MCP04 */
405 { 0x10de, 0x006a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2 */
406 { 0x10de, 0x0059, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK804 */
407 { 0x10de, 0x008a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8 */
408 { 0x10de, 0x00da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE3 */
409 { 0x10de, 0x00ea, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8S */
410 { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
411 { 0x1022, 0x7445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
412 { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI }, /* Ali5455 */
413 { 0, }
414};
415
416MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
417
418/*
419 * Lowlevel I/O - busmaster
420 */
421
422static u8 igetbyte(intel8x0_t *chip, u32 offset)
423{
424 if (chip->bm_mmio)
425 return readb(chip->remap_bmaddr + offset);
426 else
427 return inb(chip->bmaddr + offset);
428}
429
430static u16 igetword(intel8x0_t *chip, u32 offset)
431{
432 if (chip->bm_mmio)
433 return readw(chip->remap_bmaddr + offset);
434 else
435 return inw(chip->bmaddr + offset);
436}
437
438static u32 igetdword(intel8x0_t *chip, u32 offset)
439{
440 if (chip->bm_mmio)
441 return readl(chip->remap_bmaddr + offset);
442 else
443 return inl(chip->bmaddr + offset);
444}
445
446static void iputbyte(intel8x0_t *chip, u32 offset, u8 val)
447{
448 if (chip->bm_mmio)
449 writeb(val, chip->remap_bmaddr + offset);
450 else
451 outb(val, chip->bmaddr + offset);
452}
453
454static void iputword(intel8x0_t *chip, u32 offset, u16 val)
455{
456 if (chip->bm_mmio)
457 writew(val, chip->remap_bmaddr + offset);
458 else
459 outw(val, chip->bmaddr + offset);
460}
461
462static void iputdword(intel8x0_t *chip, u32 offset, u32 val)
463{
464 if (chip->bm_mmio)
465 writel(val, chip->remap_bmaddr + offset);
466 else
467 outl(val, chip->bmaddr + offset);
468}
469
470/*
471 * Lowlevel I/O - AC'97 registers
472 */
473
474static u16 iagetword(intel8x0_t *chip, u32 offset)
475{
476 if (chip->mmio)
477 return readw(chip->remap_addr + offset);
478 else
479 return inw(chip->addr + offset);
480}
481
482static void iaputword(intel8x0_t *chip, u32 offset, u16 val)
483{
484 if (chip->mmio)
485 writew(val, chip->remap_addr + offset);
486 else
487 outw(val, chip->addr + offset);
488}
489
490/*
491 * Basic I/O
492 */
493
494/*
495 * access to AC97 codec via normal i/o (for ICH and SIS7012)
496 */
497
498/* return the GLOB_STA bit for the corresponding codec */
499static unsigned int get_ich_codec_bit(intel8x0_t *chip, unsigned int codec)
500{
501 static unsigned int codec_bit[3] = {
502 ICH_PCR, ICH_SCR, ICH_TCR
503 };
504 snd_assert(codec < 3, return ICH_PCR);
505 if (chip->device_type == DEVICE_INTEL_ICH4)
506 codec = chip->ac97_sdin[codec];
507 return codec_bit[codec];
508}
509
510static int snd_intel8x0_codec_semaphore(intel8x0_t *chip, unsigned int codec)
511{
512 int time;
513
514 if (codec > 2)
515 return -EIO;
516 if (chip->in_sdin_init) {
517 /* we don't know the ready bit assignment at the moment */
518 /* so we check any */
519 codec = ICH_PCR | ICH_SCR | ICH_TCR;
520 } else {
521 codec = get_ich_codec_bit(chip, codec);
522 }
523
524 /* codec ready ? */
525 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
526 return -EIO;
527
a06147d2
TI		 528 if (chip->buggy_semaphore)
529 return 0; /* just ignore ... */
530
1da177e4
LT		 531 /* Anyone holding a semaphore for 1 msec should be shot... */
532 time = 100;
533 do {
534 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
535 return 0;
536 udelay(10);
537 } while (time--);
538
539 /* access to some forbidden (non existant) ac97 registers will not
540 * reset the semaphore. So even if you don't get the semaphore, still
541 * continue the access. We don't need the semaphore anyway. */
542 snd_printk("codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
543 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
544 iagetword(chip, 0); /* clear semaphore flag */
545 /* I don't care about the semaphore */
546 return -EBUSY;
547}
548
549static void snd_intel8x0_codec_write(ac97_t *ac97,
550 unsigned short reg,
551 unsigned short val)
552{
553 intel8x0_t *chip = ac97->private_data;
554
555 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
556 if (! chip->in_ac97_init)
557 snd_printk("codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
558 }
559 iaputword(chip, reg + ac97->num * 0x80, val);
560}
561
562static unsigned short snd_intel8x0_codec_read(ac97_t *ac97,
563 unsigned short reg)
564{
565 intel8x0_t *chip = ac97->private_data;
566 unsigned short res;
567 unsigned int tmp;
568
569 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
570 if (! chip->in_ac97_init)
571 snd_printk("codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
572 res = 0xffff;
573 } else {
574 res = iagetword(chip, reg + ac97->num * 0x80);
575 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
576 /* reset RCS and preserve other R/WC bits */
577 iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
578 if (! chip->in_ac97_init)
579 snd_printk("codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
580 res = 0xffff;
581 }
582 }
583 return res;
584}
585
586static void snd_intel8x0_codec_read_test(intel8x0_t *chip, unsigned int codec)
587{
588 unsigned int tmp;
589
590 if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
591 iagetword(chip, codec * 0x80);
592 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
593 /* reset RCS and preserve other R/WC bits */
594 iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
595 }
596 }
597}
598
599/*
600 * access to AC97 for Ali5455
601 */
602static int snd_intel8x0_ali_codec_ready(intel8x0_t *chip, int mask)
603{
604 int count = 0;
605 for (count = 0; count < 0x7f; count++) {
606 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
607 if (val & mask)
608 return 0;
609 }
610 snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n");
611 return -EBUSY;
612}
613
614static int snd_intel8x0_ali_codec_semaphore(intel8x0_t *chip)
615{
616 int time = 100;
617 while (time-- && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
618 udelay(1);
619 if (! time)
620 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n");
621 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
622}
623
624static unsigned short snd_intel8x0_ali_codec_read(ac97_t *ac97, unsigned short reg)
625{
626 intel8x0_t *chip = ac97->private_data;
627 unsigned short data = 0xffff;
628
629 if (snd_intel8x0_ali_codec_semaphore(chip))
630 goto __err;
631 reg |= ALI_CPR_ADDR_READ;
632 if (ac97->num)
633 reg |= ALI_CPR_ADDR_SECONDARY;
634 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
635 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
636 goto __err;
637 data = igetword(chip, ICHREG(ALI_SPR));
638 __err:
639 return data;
640}
641
642static void snd_intel8x0_ali_codec_write(ac97_t *ac97, unsigned short reg, unsigned short val)
643{
644 intel8x0_t *chip = ac97->private_data;
645
646 if (snd_intel8x0_ali_codec_semaphore(chip))
647 return;
648 iputword(chip, ICHREG(ALI_CPR), val);
649 if (ac97->num)
650 reg |= ALI_CPR_ADDR_SECONDARY;
651 iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
652 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
653}
654
655
656/*
657 * DMA I/O
658 */
659static void snd_intel8x0_setup_periods(intel8x0_t *chip, ichdev_t *ichdev)
660{
661 int idx;
662 u32 *bdbar = ichdev->bdbar;
663 unsigned long port = ichdev->reg_offset;
664
665 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
666 if (ichdev->size == ichdev->fragsize) {
667 ichdev->ack_reload = ichdev->ack = 2;
668 ichdev->fragsize1 = ichdev->fragsize >> 1;
669 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
670 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
671 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
672 ichdev->fragsize1 >> ichdev->pos_shift);
673 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
674 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
675 ichdev->fragsize1 >> ichdev->pos_shift);
676 }
677 ichdev->frags = 2;
678 } else {
679 ichdev->ack_reload = ichdev->ack = 1;
680 ichdev->fragsize1 = ichdev->fragsize;
681 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
682 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size));
683 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
684 ichdev->fragsize >> ichdev->pos_shift);
685 // printk("bdbar[%i] = 0x%x [0x%x]\n", idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
686 }
687 ichdev->frags = ichdev->size / ichdev->fragsize;
688 }
689 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
690 ichdev->civ = 0;
691 iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
692 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
693 ichdev->position = 0;
694#if 0
695 printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
696 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1);
697#endif
698 /* clear interrupts */
699 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
700}
701
702#ifdef __i386__
703/*
704 * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
705 * which aborts PCI busmaster for audio transfer. A workaround is to set
706 * the pages as non-cached. For details, see the errata in
707 * http://www.intel.com/design/chipsets/specupdt/245051.htm
708 */
709static void fill_nocache(void *buf, int size, int nocache)
710{
711 size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
712 change_page_attr(virt_to_page(buf), size, nocache ? PAGE_KERNEL_NOCACHE : PAGE_KERNEL);
713 global_flush_tlb();
714}
715#else
716#define fill_nocache(buf,size,nocache)
717#endif
718
719/*
720 * Interrupt handler
721 */
722
723static inline void snd_intel8x0_update(intel8x0_t *chip, ichdev_t *ichdev)
724{
725 unsigned long port = ichdev->reg_offset;
726 int status, civ, i, step;
727 int ack = 0;
728
729 spin_lock(&chip->reg_lock);
730 status = igetbyte(chip, port + ichdev->roff_sr);
731 civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
732 if (!(status & ICH_BCIS)) {
733 step = 0;
734 } else if (civ == ichdev->civ) {
735 // snd_printd("civ same %d\n", civ);
736 step = 1;
737 ichdev->civ++;
738 ichdev->civ &= ICH_REG_LVI_MASK;
739 } else {
740 step = civ - ichdev->civ;
741 if (step < 0)
742 step += ICH_REG_LVI_MASK + 1;
743 // if (step != 1)
744 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
745 ichdev->civ = civ;
746 }
747
748 ichdev->position += step * ichdev->fragsize1;
749 if (! chip->in_measurement)
750 ichdev->position %= ichdev->size;
751 ichdev->lvi += step;
752 ichdev->lvi &= ICH_REG_LVI_MASK;
753 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
754 for (i = 0; i < step; i++) {
755 ichdev->lvi_frag++;
756 ichdev->lvi_frag %= ichdev->frags;
757 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
758 // printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), inl(port + 4), inb(port + ICH_REG_OFF_CR));
759 if (--ichdev->ack == 0) {
760 ichdev->ack = ichdev->ack_reload;
761 ack = 1;
762 }
763 }
764 spin_unlock(&chip->reg_lock);
765 if (ack && ichdev->substream) {
766 snd_pcm_period_elapsed(ichdev->substream);
767 }
768 iputbyte(chip, port + ichdev->roff_sr,
769 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
770}
771
772static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id, struct pt_regs *regs)
773{
774 intel8x0_t *chip = dev_id;
775 ichdev_t *ichdev;
776 unsigned int status;
777 unsigned int i;
778
779 status = igetdword(chip, chip->int_sta_reg);
780 if (status == 0xffffffff) /* we are not yet resumed */
781 return IRQ_NONE;
782
783 if ((status & chip->int_sta_mask) == 0) {
784 if (status) {
785 /* ack */
786 iputdword(chip, chip->int_sta_reg, status);
787 if (! chip->buggy_irq)
788 status = 0;
789 }
790 return IRQ_RETVAL(status);
791 }
792
793 for (i = 0; i < chip->bdbars_count; i++) {
794 ichdev = &chip->ichd[i];
795 if (status & ichdev->int_sta_mask)
796 snd_intel8x0_update(chip, ichdev);
797 }
798
799 /* ack them */
800 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
801
802 return IRQ_HANDLED;
803}
804
805/*
806 * PCM part
807 */
808
809static int snd_intel8x0_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
810{
811 intel8x0_t *chip = snd_pcm_substream_chip(substream);
812 ichdev_t *ichdev = get_ichdev(substream);
813 unsigned char val = 0;
814 unsigned long port = ichdev->reg_offset;
815
816 switch (cmd) {
1da177e4 817 case SNDRV_PCM_TRIGGER_RESUME:
1cfe43d2
TI		 818 ichdev->suspended = 0;
819 /* fallthru */
820 case SNDRV_PCM_TRIGGER_START:
1da177e4
LT		 821 val = ICH_IOCE | ICH_STARTBM;
822 break;
1da177e4 823 case SNDRV_PCM_TRIGGER_SUSPEND:
1cfe43d2
TI		 824 ichdev->suspended = 1;
825 /* fallthru */
826 case SNDRV_PCM_TRIGGER_STOP:
1da177e4
LT		 827 val = 0;
828 break;
829 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
830 val = ICH_IOCE;
831 break;
832 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
833 val = ICH_IOCE | ICH_STARTBM;
834 break;
835 default:
836 return -EINVAL;
837 }
838 iputbyte(chip, port + ICH_REG_OFF_CR, val);
839 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
840 /* wait until DMA stopped */
841 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
842 /* reset whole DMA things */
843 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
844 }
845 return 0;
846}
847
848static int snd_intel8x0_ali_trigger(snd_pcm_substream_t *substream, int cmd)
849{
850 intel8x0_t *chip = snd_pcm_substream_chip(substream);
851 ichdev_t *ichdev = get_ichdev(substream);
852 unsigned long port = ichdev->reg_offset;
853 static int fiforeg[] = { ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3) };
854 unsigned int val, fifo;
855
856 val = igetdword(chip, ICHREG(ALI_DMACR));
857 switch (cmd) {
1cfe43d2
TI		 858 case SNDRV_PCM_TRIGGER_RESUME:
859 ichdev->suspended = 0;
860 /* fallthru */
1da177e4
LT		 861 case SNDRV_PCM_TRIGGER_START:
862 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1da177e4
LT		 863 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
864 /* clear FIFO for synchronization of channels */
865 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
866 fifo &= ~(0xff << (ichdev->ali_slot % 4));
867 fifo |= 0x83 << (ichdev->ali_slot % 4);
868 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
869 }
870 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
871 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
872 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot)); /* start DMA */
873 break;
1cfe43d2
TI		 874 case SNDRV_PCM_TRIGGER_SUSPEND:
875 ichdev->suspended = 1;
876 /* fallthru */
1da177e4
LT		 877 case SNDRV_PCM_TRIGGER_STOP:
878 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1da177e4
LT		 879 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16))); /* pause */
880 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
881 while (igetbyte(chip, port + ICH_REG_OFF_CR))
882 ;
883 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
884 break;
885 /* reset whole DMA things */
886 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
887 /* clear interrupts */
888 iputbyte(chip, port + ICH_REG_OFF_SR, igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
889 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
890 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
891 break;
892 default:
893 return -EINVAL;
894 }
895 return 0;
896}
897
898static int snd_intel8x0_hw_params(snd_pcm_substream_t * substream,
899 snd_pcm_hw_params_t * hw_params)
900{
901 intel8x0_t *chip = snd_pcm_substream_chip(substream);
902 ichdev_t *ichdev = get_ichdev(substream);
903 snd_pcm_runtime_t *runtime = substream->runtime;
904 int dbl = params_rate(hw_params) > 48000;
905 int err;
906
907 if (chip->fix_nocache && ichdev->page_attr_changed) {
908 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
909 ichdev->page_attr_changed = 0;
910 }
911 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
912 if (err < 0)
913 return err;
914 if (chip->fix_nocache) {
915 if (runtime->dma_area && ! ichdev->page_attr_changed) {
916 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
917 ichdev->page_attr_changed = 1;
918 }
919 }
920 if (ichdev->pcm_open_flag) {
921 snd_ac97_pcm_close(ichdev->pcm);
922 ichdev->pcm_open_flag = 0;
923 }
924 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
925 params_channels(hw_params),
926 ichdev->pcm->r[dbl].slots);
927 if (err >= 0) {
928 ichdev->pcm_open_flag = 1;
929 /* Force SPDIF setting */
930 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
931 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF, params_rate(hw_params));
932 }
933 return err;
934}
935
936static int snd_intel8x0_hw_free(snd_pcm_substream_t * substream)
937{
938 intel8x0_t *chip = snd_pcm_substream_chip(substream);
939 ichdev_t *ichdev = get_ichdev(substream);
940
941 if (ichdev->pcm_open_flag) {
942 snd_ac97_pcm_close(ichdev->pcm);
943 ichdev->pcm_open_flag = 0;
944 }
945 if (chip->fix_nocache && ichdev->page_attr_changed) {
946 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
947 ichdev->page_attr_changed = 0;
948 }
949 return snd_pcm_lib_free_pages(substream);
950}
951
952static void snd_intel8x0_setup_pcm_out(intel8x0_t *chip,
953 snd_pcm_runtime_t *runtime)
954{
955 unsigned int cnt;
956 int dbl = runtime->rate > 48000;
1cfe43d2
TI		 957
958 spin_lock_irq(&chip->reg_lock);
1da177e4
LT		 959 switch (chip->device_type) {
960 case DEVICE_ALI:
961 cnt = igetdword(chip, ICHREG(ALI_SCR));
962 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
963 if (runtime->channels == 4 || dbl)
964 cnt |= ICH_ALI_SC_PCM_4;
965 else if (runtime->channels == 6)
966 cnt |= ICH_ALI_SC_PCM_6;
967 iputdword(chip, ICHREG(ALI_SCR), cnt);
968 break;
969 case DEVICE_SIS:
970 cnt = igetdword(chip, ICHREG(GLOB_CNT));
971 cnt &= ~ICH_SIS_PCM_246_MASK;
972 if (runtime->channels == 4 || dbl)
973 cnt |= ICH_SIS_PCM_4;
974 else if (runtime->channels == 6)
975 cnt |= ICH_SIS_PCM_6;
976 iputdword(chip, ICHREG(GLOB_CNT), cnt);
977 break;
978 default:
979 cnt = igetdword(chip, ICHREG(GLOB_CNT));
980 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
981 if (runtime->channels == 4 || dbl)
982 cnt |= ICH_PCM_4;
983 else if (runtime->channels == 6)
984 cnt |= ICH_PCM_6;
985 if (chip->device_type == DEVICE_NFORCE) {
986 /* reset to 2ch once to keep the 6 channel data in alignment,
987 * to start from Front Left always
988 */
989 if (cnt & ICH_PCM_246_MASK) {
990 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
991 spin_unlock_irq(&chip->reg_lock);
992 msleep(50); /* grrr... */
993 spin_lock_irq(&chip->reg_lock);
994 }
995 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
996 if (runtime->sample_bits > 16)
997 cnt |= ICH_PCM_20BIT;
998 }
999 iputdword(chip, ICHREG(GLOB_CNT), cnt);
1000 break;
1001 }
1cfe43d2 1002 spin_unlock_irq(&chip->reg_lock);
1da177e4
LT		 1003}
1004
1005static int snd_intel8x0_pcm_prepare(snd_pcm_substream_t * substream)
1006{
1007 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1008 snd_pcm_runtime_t *runtime = substream->runtime;
1009 ichdev_t *ichdev = get_ichdev(substream);
1010
1011 ichdev->physbuf = runtime->dma_addr;
1012 ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1013 ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1da177e4
LT		 1014 if (ichdev->ichd == ICHD_PCMOUT) {
1015 snd_intel8x0_setup_pcm_out(chip, runtime);
1cfe43d2 1016 if (chip->device_type == DEVICE_INTEL_ICH4)
1da177e4 1017 ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1da177e4
LT		 1018 }
1019 snd_intel8x0_setup_periods(chip, ichdev);
1da177e4
LT		 1020 return 0;
1021}
1022
1023static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(snd_pcm_substream_t * substream)
1024{
1025 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1026 ichdev_t *ichdev = get_ichdev(substream);
1027 size_t ptr1, ptr;
1028 int civ, timeout = 100;
1029 unsigned int position;
1030
1031 spin_lock(&chip->reg_lock);
1032 do {
1033 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1034 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1035 position = ichdev->position;
1036 if (ptr1 == 0) {
1037 udelay(10);
1038 continue;
1039 }
1040 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
1041 ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1042 break;
1043 } while (timeout--);
1044 ptr1 <<= ichdev->pos_shift;
1045 ptr = ichdev->fragsize1 - ptr1;
1046 ptr += position;
1047 spin_unlock(&chip->reg_lock);
1048 if (ptr >= ichdev->size)
1049 return 0;
1050 return bytes_to_frames(substream->runtime, ptr);
1051}
1052
1053static snd_pcm_hardware_t snd_intel8x0_stream =
1054{
1055 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1056 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1057 SNDRV_PCM_INFO_MMAP_VALID |
1058 SNDRV_PCM_INFO_PAUSE |
1059 SNDRV_PCM_INFO_RESUME),
1060 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1061 .rates = SNDRV_PCM_RATE_48000,
1062 .rate_min = 48000,
1063 .rate_max = 48000,
1064 .channels_min = 2,
1065 .channels_max = 2,
1066 .buffer_bytes_max = 128 * 1024,
1067 .period_bytes_min = 32,
1068 .period_bytes_max = 128 * 1024,
1069 .periods_min = 1,
1070 .periods_max = 1024,
1071 .fifo_size = 0,
1072};
1073
1074static unsigned int channels4[] = {
1075 2, 4,
1076};
1077
1078static snd_pcm_hw_constraint_list_t hw_constraints_channels4 = {
1079 .count = ARRAY_SIZE(channels4),
1080 .list = channels4,
1081 .mask = 0,
1082};
1083
1084static unsigned int channels6[] = {
1085 2, 4, 6,
1086};
1087
1088static snd_pcm_hw_constraint_list_t hw_constraints_channels6 = {
1089 .count = ARRAY_SIZE(channels6),
1090 .list = channels6,
1091 .mask = 0,
1092};
1093
1094static int snd_intel8x0_pcm_open(snd_pcm_substream_t * substream, ichdev_t *ichdev)
1095{
1096 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1097 snd_pcm_runtime_t *runtime = substream->runtime;
1098 int err;
1099
1100 ichdev->substream = substream;
1101 runtime->hw = snd_intel8x0_stream;
1102 runtime->hw.rates = ichdev->pcm->rates;
1103 snd_pcm_limit_hw_rates(runtime);
1104 if (chip->device_type == DEVICE_SIS) {
1105 runtime->hw.buffer_bytes_max = 64*1024;
1106 runtime->hw.period_bytes_max = 64*1024;
1107 }
1108 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1109 return err;
1110 runtime->private_data = ichdev;
1111 return 0;
1112}
1113
1114static int snd_intel8x0_playback_open(snd_pcm_substream_t * substream)
1115{
1116 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1117 snd_pcm_runtime_t *runtime = substream->runtime;
1118 int err;
1119
1120 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1121 if (err < 0)
1122 return err;
1123
1124 if (chip->multi6) {
1125 runtime->hw.channels_max = 6;
1126 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels6);
1127 } else if (chip->multi4) {
1128 runtime->hw.channels_max = 4;
1129 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels4);
1130 }
1131 if (chip->dra) {
1132 snd_ac97_pcm_double_rate_rules(runtime);
1133 }
1134 if (chip->smp20bit) {
1135 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1136 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1137 }
1138 return 0;
1139}
1140
1141static int snd_intel8x0_playback_close(snd_pcm_substream_t * substream)
1142{
1143 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1144
1145 chip->ichd[ICHD_PCMOUT].substream = NULL;
1146 return 0;
1147}
1148
1149static int snd_intel8x0_capture_open(snd_pcm_substream_t * substream)
1150{
1151 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1152
1153 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1154}
1155
1156static int snd_intel8x0_capture_close(snd_pcm_substream_t * substream)
1157{
1158 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1159
1160 chip->ichd[ICHD_PCMIN].substream = NULL;
1161 return 0;
1162}
1163
1164static int snd_intel8x0_mic_open(snd_pcm_substream_t * substream)
1165{
1166 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1167
1168 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1169}
1170
1171static int snd_intel8x0_mic_close(snd_pcm_substream_t * substream)
1172{
1173 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1174
1175 chip->ichd[ICHD_MIC].substream = NULL;
1176 return 0;
1177}
1178
1179static int snd_intel8x0_mic2_open(snd_pcm_substream_t * substream)
1180{
1181 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1182
1183 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1184}
1185
1186static int snd_intel8x0_mic2_close(snd_pcm_substream_t * substream)
1187{
1188 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1189
1190 chip->ichd[ICHD_MIC2].substream = NULL;
1191 return 0;
1192}
1193
1194static int snd_intel8x0_capture2_open(snd_pcm_substream_t * substream)
1195{
1196 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1197
1198 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1199}
1200
1201static int snd_intel8x0_capture2_close(snd_pcm_substream_t * substream)
1202{
1203 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1204
1205 chip->ichd[ICHD_PCM2IN].substream = NULL;
1206 return 0;
1207}
1208
1209static int snd_intel8x0_spdif_open(snd_pcm_substream_t * substream)
1210{
1211 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1212 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1213
1214 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1215}
1216
1217static int snd_intel8x0_spdif_close(snd_pcm_substream_t * substream)
1218{
1219 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1220 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1221
1222 chip->ichd[idx].substream = NULL;
1223 return 0;
1224}
1225
1226static int snd_intel8x0_ali_ac97spdifout_open(snd_pcm_substream_t * substream)
1227{
1228 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1229 unsigned int val;
1230
1231 spin_lock_irq(&chip->reg_lock);
1232 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1233 val |= ICH_ALI_IF_AC97SP;
1234 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1235 /* also needs to set ALI_SC_CODEC_SPDF correctly */
1236 spin_unlock_irq(&chip->reg_lock);
1237
1238 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1239}
1240
1241static int snd_intel8x0_ali_ac97spdifout_close(snd_pcm_substream_t * substream)
1242{
1243 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1244 unsigned int val;
1245
1246 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1247 spin_lock_irq(&chip->reg_lock);
1248 val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1249 val &= ~ICH_ALI_IF_AC97SP;
1250 iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1251 spin_unlock_irq(&chip->reg_lock);
1252
1253 return 0;
1254}
1255
1256static int snd_intel8x0_ali_spdifin_open(snd_pcm_substream_t * substream)
1257{
1258 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1259
1260 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1261}
1262
1263static int snd_intel8x0_ali_spdifin_close(snd_pcm_substream_t * substream)
1264{
1265 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1266
1267 chip->ichd[ALID_SPDIFIN].substream = NULL;
1268 return 0;
1269}
1270
1271#if 0 // NYI
1272static int snd_intel8x0_ali_spdifout_open(snd_pcm_substream_t * substream)
1273{
1274 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1275
1276 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1277}
1278
1279static int snd_intel8x0_ali_spdifout_close(snd_pcm_substream_t * substream)
1280{
1281 intel8x0_t *chip = snd_pcm_substream_chip(substream);
1282
1283 chip->ichd[ALID_SPDIFOUT].substream = NULL;
1284 return 0;
1285}
1286#endif
1287
1288static snd_pcm_ops_t snd_intel8x0_playback_ops = {
1289 .open = snd_intel8x0_playback_open,
1290 .close = snd_intel8x0_playback_close,
1291 .ioctl = snd_pcm_lib_ioctl,
1292 .hw_params = snd_intel8x0_hw_params,
1293 .hw_free = snd_intel8x0_hw_free,
1294 .prepare = snd_intel8x0_pcm_prepare,
1295 .trigger = snd_intel8x0_pcm_trigger,
1296 .pointer = snd_intel8x0_pcm_pointer,
1297};
1298
1299static snd_pcm_ops_t snd_intel8x0_capture_ops = {
1300 .open = snd_intel8x0_capture_open,
1301 .close = snd_intel8x0_capture_close,
1302 .ioctl = snd_pcm_lib_ioctl,
1303 .hw_params = snd_intel8x0_hw_params,
1304 .hw_free = snd_intel8x0_hw_free,
1305 .prepare = snd_intel8x0_pcm_prepare,
1306 .trigger = snd_intel8x0_pcm_trigger,
1307 .pointer = snd_intel8x0_pcm_pointer,
1308};
1309
1310static snd_pcm_ops_t snd_intel8x0_capture_mic_ops = {
1311 .open = snd_intel8x0_mic_open,
1312 .close = snd_intel8x0_mic_close,
1313 .ioctl = snd_pcm_lib_ioctl,
1314 .hw_params = snd_intel8x0_hw_params,
1315 .hw_free = snd_intel8x0_hw_free,
1316 .prepare = snd_intel8x0_pcm_prepare,
1317 .trigger = snd_intel8x0_pcm_trigger,
1318 .pointer = snd_intel8x0_pcm_pointer,
1319};
1320
1321static snd_pcm_ops_t snd_intel8x0_capture_mic2_ops = {
1322 .open = snd_intel8x0_mic2_open,
1323 .close = snd_intel8x0_mic2_close,
1324 .ioctl = snd_pcm_lib_ioctl,
1325 .hw_params = snd_intel8x0_hw_params,
1326 .hw_free = snd_intel8x0_hw_free,
1327 .prepare = snd_intel8x0_pcm_prepare,
1328 .trigger = snd_intel8x0_pcm_trigger,
1329 .pointer = snd_intel8x0_pcm_pointer,
1330};
1331
1332static snd_pcm_ops_t snd_intel8x0_capture2_ops = {
1333 .open = snd_intel8x0_capture2_open,
1334 .close = snd_intel8x0_capture2_close,
1335 .ioctl = snd_pcm_lib_ioctl,
1336 .hw_params = snd_intel8x0_hw_params,
1337 .hw_free = snd_intel8x0_hw_free,
1338 .prepare = snd_intel8x0_pcm_prepare,
1339 .trigger = snd_intel8x0_pcm_trigger,
1340 .pointer = snd_intel8x0_pcm_pointer,
1341};
1342
1343static snd_pcm_ops_t snd_intel8x0_spdif_ops = {
1344 .open = snd_intel8x0_spdif_open,
1345 .close = snd_intel8x0_spdif_close,
1346 .ioctl = snd_pcm_lib_ioctl,
1347 .hw_params = snd_intel8x0_hw_params,
1348 .hw_free = snd_intel8x0_hw_free,
1349 .prepare = snd_intel8x0_pcm_prepare,
1350 .trigger = snd_intel8x0_pcm_trigger,
1351 .pointer = snd_intel8x0_pcm_pointer,
1352};
1353
1354static snd_pcm_ops_t snd_intel8x0_ali_playback_ops = {
1355 .open = snd_intel8x0_playback_open,
1356 .close = snd_intel8x0_playback_close,
1357 .ioctl = snd_pcm_lib_ioctl,
1358 .hw_params = snd_intel8x0_hw_params,
1359 .hw_free = snd_intel8x0_hw_free,
1360 .prepare = snd_intel8x0_pcm_prepare,
1361 .trigger = snd_intel8x0_ali_trigger,
1362 .pointer = snd_intel8x0_pcm_pointer,
1363};
1364
1365static snd_pcm_ops_t snd_intel8x0_ali_capture_ops = {
1366 .open = snd_intel8x0_capture_open,
1367 .close = snd_intel8x0_capture_close,
1368 .ioctl = snd_pcm_lib_ioctl,
1369 .hw_params = snd_intel8x0_hw_params,
1370 .hw_free = snd_intel8x0_hw_free,
1371 .prepare = snd_intel8x0_pcm_prepare,
1372 .trigger = snd_intel8x0_ali_trigger,
1373 .pointer = snd_intel8x0_pcm_pointer,
1374};
1375
1376static snd_pcm_ops_t snd_intel8x0_ali_capture_mic_ops = {
1377 .open = snd_intel8x0_mic_open,
1378 .close = snd_intel8x0_mic_close,
1379 .ioctl = snd_pcm_lib_ioctl,
1380 .hw_params = snd_intel8x0_hw_params,
1381 .hw_free = snd_intel8x0_hw_free,
1382 .prepare = snd_intel8x0_pcm_prepare,
1383 .trigger = snd_intel8x0_ali_trigger,
1384 .pointer = snd_intel8x0_pcm_pointer,
1385};
1386
1387static snd_pcm_ops_t snd_intel8x0_ali_ac97spdifout_ops = {
1388 .open = snd_intel8x0_ali_ac97spdifout_open,
1389 .close = snd_intel8x0_ali_ac97spdifout_close,
1390 .ioctl = snd_pcm_lib_ioctl,
1391 .hw_params = snd_intel8x0_hw_params,
1392 .hw_free = snd_intel8x0_hw_free,
1393 .prepare = snd_intel8x0_pcm_prepare,
1394 .trigger = snd_intel8x0_ali_trigger,
1395 .pointer = snd_intel8x0_pcm_pointer,
1396};
1397
1398static snd_pcm_ops_t snd_intel8x0_ali_spdifin_ops = {
1399 .open = snd_intel8x0_ali_spdifin_open,
1400 .close = snd_intel8x0_ali_spdifin_close,
1401 .ioctl = snd_pcm_lib_ioctl,
1402 .hw_params = snd_intel8x0_hw_params,
1403 .hw_free = snd_intel8x0_hw_free,
1404 .prepare = snd_intel8x0_pcm_prepare,
1405 .trigger = snd_intel8x0_pcm_trigger,
1406 .pointer = snd_intel8x0_pcm_pointer,
1407};
1408
1409#if 0 // NYI
1410static snd_pcm_ops_t snd_intel8x0_ali_spdifout_ops = {
1411 .open = snd_intel8x0_ali_spdifout_open,
1412 .close = snd_intel8x0_ali_spdifout_close,
1413 .ioctl = snd_pcm_lib_ioctl,
1414 .hw_params = snd_intel8x0_hw_params,
1415 .hw_free = snd_intel8x0_hw_free,
1416 .prepare = snd_intel8x0_pcm_prepare,
1417 .trigger = snd_intel8x0_pcm_trigger,
1418 .pointer = snd_intel8x0_pcm_pointer,
1419};
1420#endif // NYI
1421
1422struct ich_pcm_table {
1423 char *suffix;
1424 snd_pcm_ops_t *playback_ops;
1425 snd_pcm_ops_t *capture_ops;
1426 size_t prealloc_size;
1427 size_t prealloc_max_size;
1428 int ac97_idx;
1429};
1430
1431static int __devinit snd_intel8x0_pcm1(intel8x0_t *chip, int device, struct ich_pcm_table *rec)
1432{
1433 snd_pcm_t *pcm;
1434 int err;
1435 char name[32];
1436
1437 if (rec->suffix)
1438 sprintf(name, "Intel ICH - %s", rec->suffix);
1439 else
1440 strcpy(name, "Intel ICH");
1441 err = snd_pcm_new(chip->card, name, device,
1442 rec->playback_ops ? 1 : 0,
1443 rec->capture_ops ? 1 : 0, &pcm);
1444 if (err < 0)
1445 return err;
1446
1447 if (rec->playback_ops)
1448 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1449 if (rec->capture_ops)
1450 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1451
1452 pcm->private_data = chip;
1453 pcm->info_flags = 0;
1454 if (rec->suffix)
1455 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1456 else
1457 strcpy(pcm->name, chip->card->shortname);
1458 chip->pcm[device] = pcm;
1459
1460 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1461 rec->prealloc_size, rec->prealloc_max_size);
1462
1463 return 0;
1464}
1465
1466static struct ich_pcm_table intel_pcms[] __devinitdata = {
1467 {
1468 .playback_ops = &snd_intel8x0_playback_ops,
1469 .capture_ops = &snd_intel8x0_capture_ops,
1470 .prealloc_size = 64 * 1024,
1471 .prealloc_max_size = 128 * 1024,
1472 },
1473 {
1474 .suffix = "MIC ADC",
1475 .capture_ops = &snd_intel8x0_capture_mic_ops,
1476 .prealloc_size = 0,
1477 .prealloc_max_size = 128 * 1024,
1478 .ac97_idx = ICHD_MIC,
1479 },
1480 {
1481 .suffix = "MIC2 ADC",
1482 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1483 .prealloc_size = 0,
1484 .prealloc_max_size = 128 * 1024,
1485 .ac97_idx = ICHD_MIC2,
1486 },
1487 {
1488 .suffix = "ADC2",
1489 .capture_ops = &snd_intel8x0_capture2_ops,
1490 .prealloc_size = 0,
1491 .prealloc_max_size = 128 * 1024,
1492 .ac97_idx = ICHD_PCM2IN,
1493 },
1494 {
1495 .suffix = "IEC958",
1496 .playback_ops = &snd_intel8x0_spdif_ops,
1497 .prealloc_size = 64 * 1024,
1498 .prealloc_max_size = 128 * 1024,
1499 .ac97_idx = ICHD_SPBAR,
1500 },
1501};
1502
1503static struct ich_pcm_table nforce_pcms[] __devinitdata = {
1504 {
1505 .playback_ops = &snd_intel8x0_playback_ops,
1506 .capture_ops = &snd_intel8x0_capture_ops,
1507 .prealloc_size = 64 * 1024,
1508 .prealloc_max_size = 128 * 1024,
1509 },
1510 {
1511 .suffix = "MIC ADC",
1512 .capture_ops = &snd_intel8x0_capture_mic_ops,
1513 .prealloc_size = 0,
1514 .prealloc_max_size = 128 * 1024,
1515 .ac97_idx = NVD_MIC,
1516 },
1517 {
1518 .suffix = "IEC958",
1519 .playback_ops = &snd_intel8x0_spdif_ops,
1520 .prealloc_size = 64 * 1024,
1521 .prealloc_max_size = 128 * 1024,
1522 .ac97_idx = NVD_SPBAR,
1523 },
1524};
1525
1526static struct ich_pcm_table ali_pcms[] __devinitdata = {
1527 {
1528 .playback_ops = &snd_intel8x0_ali_playback_ops,
1529 .capture_ops = &snd_intel8x0_ali_capture_ops,
1530 .prealloc_size = 64 * 1024,
1531 .prealloc_max_size = 128 * 1024,
1532 },
1533 {
1534 .suffix = "MIC ADC",
1535 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1536 .prealloc_size = 0,
1537 .prealloc_max_size = 128 * 1024,
1538 .ac97_idx = ALID_MIC,
1539 },
1540 {
1541 .suffix = "IEC958",
1542 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1543 .capture_ops = &snd_intel8x0_ali_spdifin_ops,
1544 .prealloc_size = 64 * 1024,
1545 .prealloc_max_size = 128 * 1024,
1546 .ac97_idx = ALID_AC97SPDIFOUT,
1547 },
1548#if 0 // NYI
1549 {
1550 .suffix = "HW IEC958",
1551 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1552 .prealloc_size = 64 * 1024,
1553 .prealloc_max_size = 128 * 1024,
1554 },
1555#endif
1556};
1557
1558static int __devinit snd_intel8x0_pcm(intel8x0_t *chip)
1559{
1560 int i, tblsize, device, err;
1561 struct ich_pcm_table *tbl, *rec;
1562
1563 switch (chip->device_type) {
1564 case DEVICE_INTEL_ICH4:
1565 tbl = intel_pcms;
1566 tblsize = ARRAY_SIZE(intel_pcms);
1567 break;
1568 case DEVICE_NFORCE:
1569 tbl = nforce_pcms;
1570 tblsize = ARRAY_SIZE(nforce_pcms);
1571 break;
1572 case DEVICE_ALI:
1573 tbl = ali_pcms;
1574 tblsize = ARRAY_SIZE(ali_pcms);
1575 break;
1576 default:
1577 tbl = intel_pcms;
1578 tblsize = 2;
1579 break;
1580 }
1581
1582 device = 0;
1583 for (i = 0; i < tblsize; i++) {
1584 rec = tbl + i;
1585 if (i > 0 && rec->ac97_idx) {
1586 /* activate PCM only when associated AC'97 codec */
1587 if (! chip->ichd[rec->ac97_idx].pcm)
1588 continue;
1589 }
1590 err = snd_intel8x0_pcm1(chip, device, rec);
1591 if (err < 0)
1592 return err;
1593 device++;
1594 }
1595
1596 chip->pcm_devs = device;
1597 return 0;
1598}
1599
1600
1601/*
1602 * Mixer part
1603 */
1604
1605static void snd_intel8x0_mixer_free_ac97_bus(ac97_bus_t *bus)
1606{
1607 intel8x0_t *chip = bus->private_data;
1608 chip->ac97_bus = NULL;
1609}
1610
1611static void snd_intel8x0_mixer_free_ac97(ac97_t *ac97)
1612{
1613 intel8x0_t *chip = ac97->private_data;
1614 chip->ac97[ac97->num] = NULL;
1615}
1616
1617static struct ac97_pcm ac97_pcm_defs[] __devinitdata = {
1618 /* front PCM */
1619 {
1620 .exclusive = 1,
1621 .r = { {
1622 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1623 (1 << AC97_SLOT_PCM_RIGHT) |
1624 (1 << AC97_SLOT_PCM_CENTER) |
1625 (1 << AC97_SLOT_PCM_SLEFT) |
1626 (1 << AC97_SLOT_PCM_SRIGHT) |
1627 (1 << AC97_SLOT_LFE)
1628 },
1629 {
1630 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1631 (1 << AC97_SLOT_PCM_RIGHT) |
1632 (1 << AC97_SLOT_PCM_LEFT_0) |
1633 (1 << AC97_SLOT_PCM_RIGHT_0)
1634 }
1635 }
1636 },
1637 /* PCM IN #1 */
1638 {
1639 .stream = 1,
1640 .exclusive = 1,
1641 .r = { {
1642 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1643 (1 << AC97_SLOT_PCM_RIGHT)
1644 }
1645 }
1646 },
1647 /* MIC IN #1 */
1648 {
1649 .stream = 1,
1650 .exclusive = 1,
1651 .r = { {
1652 .slots = (1 << AC97_SLOT_MIC)
1653 }
1654 }
1655 },
1656 /* S/PDIF PCM */
1657 {
1658 .exclusive = 1,
1659 .spdif = 1,
1660 .r = { {
1661 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1662 (1 << AC97_SLOT_SPDIF_RIGHT2)
1663 }
1664 }
1665 },
1666 /* PCM IN #2 */
1667 {
1668 .stream = 1,
1669 .exclusive = 1,
1670 .r = { {
1671 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1672 (1 << AC97_SLOT_PCM_RIGHT)
1673 }
1674 }
1675 },
1676 /* MIC IN #2 */
1677 {
1678 .stream = 1,
1679 .exclusive = 1,
1680 .r = { {
1681 .slots = (1 << AC97_SLOT_MIC)
1682 }
1683 }
1684 },
1685};
1686
1687static struct ac97_quirk ac97_quirks[] __devinitdata = {
1688 {
6fd8b87f
JCD		 1689 .subvendor = 0x0e11,
1690 .subdevice = 0x008a,
1da177e4
LT		 1691 .name = "Compaq Evo W4000", /* AD1885 */
1692 .type = AC97_TUNE_HP_ONLY
1693 },
1694 {
6fd8b87f
JCD		 1695 .subvendor = 0x0e11,
1696 .subdevice = 0x00b8,
1da177e4
LT		 1697 .name = "Compaq Evo D510C",
1698 .type = AC97_TUNE_HP_ONLY
1699 },
1700 {
6fd8b87f
JCD		 1701 .subvendor = 0x0e11,
1702 .subdevice = 0x0860,
1da177e4
LT		 1703 .name = "HP/Compaq nx7010",
1704 .type = AC97_TUNE_MUTE_LED
1705 },
1706 {
6fd8b87f
JCD		 1707 .subvendor = 0x1014,
1708 .subdevice = 0x1f00,
1da177e4
LT		 1709 .name = "MS-9128",
1710 .type = AC97_TUNE_ALC_JACK
1711 },
5d529390
TI		 1712 {
1713 .subvendor = 0x1014,
1714 .subdevice = 0x0267,
1715 .name = "IBM NetVista A30p", /* AD1981B */
1716 .type = AC97_TUNE_HP_ONLY
1717 },
1da177e4 1718 {
6fd8b87f
JCD		 1719 .subvendor = 0x1028,
1720 .subdevice = 0x00d8,
1da177e4
LT		 1721 .name = "Dell Precision 530", /* AD1885 */
1722 .type = AC97_TUNE_HP_ONLY
1723 },
1724 {
6fd8b87f
JCD		 1725 .subvendor = 0x1028,
1726 .subdevice = 0x010d,
1da177e4
LT		 1727 .name = "Dell", /* which model? AD1885 */
1728 .type = AC97_TUNE_HP_ONLY
1729 },
1730 {
6fd8b87f
JCD		 1731 .subvendor = 0x1028,
1732 .subdevice = 0x0126,
1da177e4
LT		 1733 .name = "Dell Optiplex GX260", /* AD1981A */
1734 .type = AC97_TUNE_HP_ONLY
1735 },
1736 {
6fd8b87f
JCD		 1737 .subvendor = 0x1028,
1738 .subdevice = 0x012c,
1da177e4
LT		 1739 .name = "Dell Precision 650", /* AD1981A */
1740 .type = AC97_TUNE_HP_ONLY
1741 },
1742 {
6fd8b87f
JCD		 1743 .subvendor = 0x1028,
1744 .subdevice = 0x012d,
1da177e4
LT		 1745 .name = "Dell Precision 450", /* AD1981B*/
1746 .type = AC97_TUNE_HP_ONLY
1747 },
1748 {
6fd8b87f
JCD		 1749 .subvendor = 0x1028,
1750 .subdevice = 0x0147,
1da177e4
LT		 1751 .name = "Dell", /* which model? AD1981B*/
1752 .type = AC97_TUNE_HP_ONLY
1753 },
1754 {
6fd8b87f
JCD		 1755 .subvendor = 0x1028,
1756 .subdevice = 0x0163,
1da177e4
LT		 1757 .name = "Dell Unknown", /* STAC9750/51 */
1758 .type = AC97_TUNE_HP_ONLY
1759 },
1760 {
6fd8b87f
JCD		 1761 .subvendor = 0x103c,
1762 .subdevice = 0x006d,
1da177e4
LT		 1763 .name = "HP zv5000",
1764 .type = AC97_TUNE_MUTE_LED /*AD1981B*/
1765 },
1766 { /* FIXME: which codec? */
6fd8b87f
JCD		 1767 .subvendor = 0x103c,
1768 .subdevice = 0x00c3,
1da177e4
LT		 1769 .name = "HP xw6000",
1770 .type = AC97_TUNE_HP_ONLY
1771 },
1772 {
6fd8b87f
JCD		 1773 .subvendor = 0x103c,
1774 .subdevice = 0x088c,
1da177e4
LT		 1775 .name = "HP nc8000",
1776 .type = AC97_TUNE_MUTE_LED
1777 },
1778 {
6fd8b87f
JCD		 1779 .subvendor = 0x103c,
1780 .subdevice = 0x0890,
1da177e4
LT		 1781 .name = "HP nc6000",
1782 .type = AC97_TUNE_MUTE_LED
1783 },
e0c93cf3
DH		 1784 {
1785 .subvendor = 0x103c,
1786 .subdevice = 0x0934,
1787 .name = "HP nx8220",
1788 .type = AC97_TUNE_MUTE_LED
1789 },
66d10647
SV		 1790 {
1791 .subvendor = 0x103c,
1792 .subdevice = 0x099c,
1793 .name = "HP nx6110", /* AD1981B */
1794 .type = AC97_TUNE_HP_ONLY
1795 },
1da177e4 1796 {
6fd8b87f
JCD		 1797 .subvendor = 0x103c,
1798 .subdevice = 0x129d,
1da177e4
LT		 1799 .name = "HP xw8000",
1800 .type = AC97_TUNE_HP_ONLY
1801 },
1802 {
6fd8b87f
JCD		 1803 .subvendor = 0x103c,
1804 .subdevice = 0x12f1,
1da177e4
LT		 1805 .name = "HP xw8200", /* AD1981B*/
1806 .type = AC97_TUNE_HP_ONLY
1807 },
1808 {
6fd8b87f
JCD		 1809 .subvendor = 0x103c,
1810 .subdevice = 0x12f2,
1da177e4
LT		 1811 .name = "HP xw6200",
1812 .type = AC97_TUNE_HP_ONLY
1813 },
1814 {
6fd8b87f
JCD		 1815 .subvendor = 0x103c,
1816 .subdevice = 0x3008,
1da177e4
LT		 1817 .name = "HP xw4200", /* AD1981B*/
1818 .type = AC97_TUNE_HP_ONLY
1819 },
1820 {
6fd8b87f
JCD		 1821 .subvendor = 0x104d,
1822 .subdevice = 0x8197,
1da177e4
LT		 1823 .name = "Sony S1XP",
1824 .type = AC97_TUNE_INV_EAPD
1825 },
1826 {
6fd8b87f
JCD		 1827 .subvendor = 0x1043,
1828 .subdevice = 0x80f3,
1da177e4
LT		 1829 .name = "ASUS ICH5/AD1985",
1830 .type = AC97_TUNE_AD_SHARING
1831 },
1832 {
6fd8b87f
JCD		 1833 .subvendor = 0x10cf,
1834 .subdevice = 0x11c3,
1da177e4
LT		 1835 .name = "Fujitsu-Siemens E4010",
1836 .type = AC97_TUNE_HP_ONLY
1837 },
98c7f212
TI		 1838 {
1839 .subvendor = 0x10cf,
1840 .subdevice = 0x1225,
1841 .name = "Fujitsu-Siemens T3010",
1842 .type = AC97_TUNE_HP_ONLY
1843 },
1da177e4 1844 {
6fd8b87f
JCD		 1845 .subvendor = 0x10cf,
1846 .subdevice = 0x1253,
1da177e4
LT		 1847 .name = "Fujitsu S6210", /* STAC9750/51 */
1848 .type = AC97_TUNE_HP_ONLY
1849 },
9970dce5
TI		 1850 {
1851 .subvendor = 0x10cf,
1852 .subdevice = 0x12ec,
1853 .name = "Fujitsu-Siemens 4010",
1854 .type = AC97_TUNE_HP_ONLY
1855 },
1da177e4 1856 {
6fd8b87f
JCD		 1857 .subvendor = 0x10f1,
1858 .subdevice = 0x2665,
1da177e4
LT		 1859 .name = "Fujitsu-Siemens Celsius", /* AD1981? */
1860 .type = AC97_TUNE_HP_ONLY
1861 },
1862 {
6fd8b87f
JCD		 1863 .subvendor = 0x10f1,
1864 .subdevice = 0x2885,
1da177e4
LT		 1865 .name = "AMD64 Mobo", /* ALC650 */
1866 .type = AC97_TUNE_HP_ONLY
1867 },
1868 {
6fd8b87f
JCD		 1869 .subvendor = 0x110a,
1870 .subdevice = 0x0056,
1da177e4
LT		 1871 .name = "Fujitsu-Siemens Scenic", /* AD1981? */
1872 .type = AC97_TUNE_HP_ONLY
1873 },
1874 {
6fd8b87f
JCD		 1875 .subvendor = 0x11d4,
1876 .subdevice = 0x5375,
1da177e4
LT		 1877 .name = "ADI AD1985 (discrete)",
1878 .type = AC97_TUNE_HP_ONLY
1879 },
1880 {
6fd8b87f
JCD		 1881 .subvendor = 0x1462,
1882 .subdevice = 0x5470,
1da177e4
LT		 1883 .name = "MSI P4 ATX 645 Ultra",
1884 .type = AC97_TUNE_HP_ONLY
1885 },
1886 {
6fd8b87f
JCD		 1887 .subvendor = 0x1734,
1888 .subdevice = 0x0088,
1da177e4
LT		 1889 .name = "Fujitsu-Siemens D1522", /* AD1981 */
1890 .type = AC97_TUNE_HP_ONLY
1891 },
1892 {
6fd8b87f
JCD		 1893 .subvendor = 0x8086,
1894 .subdevice = 0x2000,
1da177e4
LT		 1895 .mask = 0xfff0,
1896 .name = "Intel ICH5/AD1985",
1897 .type = AC97_TUNE_AD_SHARING
1898 },
1899 {
6fd8b87f
JCD		 1900 .subvendor = 0x8086,
1901 .subdevice = 0x4000,
1da177e4
LT		 1902 .mask = 0xfff0,
1903 .name = "Intel ICH5/AD1985",
1904 .type = AC97_TUNE_AD_SHARING
1905 },
1906 {
6fd8b87f
JCD		 1907 .subvendor = 0x8086,
1908 .subdevice = 0x4856,
1da177e4
LT		 1909 .name = "Intel D845WN (82801BA)",
1910 .type = AC97_TUNE_SWAP_HP
1911 },
1912 {
6fd8b87f
JCD		 1913 .subvendor = 0x8086,
1914 .subdevice = 0x4d44,
1da177e4
LT		 1915 .name = "Intel D850EMV2", /* AD1885 */
1916 .type = AC97_TUNE_HP_ONLY
1917 },
1918 {
6fd8b87f
JCD		 1919 .subvendor = 0x8086,
1920 .subdevice = 0x4d56,
1da177e4
LT		 1921 .name = "Intel ICH/AD1885",
1922 .type = AC97_TUNE_HP_ONLY
1923 },
1924 {
6fd8b87f
JCD		 1925 .subvendor = 0x8086,
1926 .subdevice = 0x6000,
1da177e4
LT		 1927 .mask = 0xfff0,
1928 .name = "Intel ICH5/AD1985",
1929 .type = AC97_TUNE_AD_SHARING
1930 },
1931 {
6fd8b87f
JCD		 1932 .subvendor = 0x8086,
1933 .subdevice = 0xe000,
1da177e4
LT		 1934 .mask = 0xfff0,
1935 .name = "Intel ICH5/AD1985",
1936 .type = AC97_TUNE_AD_SHARING
1937 },
1938#if 0 /* FIXME: this seems wrong on most boards */
1939 {
6fd8b87f
JCD		 1940 .subvendor = 0x8086,
1941 .subdevice = 0xa000,
1da177e4
LT		 1942 .mask = 0xfff0,
1943 .name = "Intel ICH5/AD1985",
1944 .type = AC97_TUNE_HP_ONLY
1945 },
1946#endif
1947 { } /* terminator */
1948};
1949
1950static int __devinit snd_intel8x0_mixer(intel8x0_t *chip, int ac97_clock, const char *quirk_override)
1951{
1952 ac97_bus_t *pbus;
1953 ac97_template_t ac97;
1954 int err;
1955 unsigned int i, codecs;
1956 unsigned int glob_sta = 0;
1957 ac97_bus_ops_t *ops;
1958 static ac97_bus_ops_t standard_bus_ops = {
1959 .write = snd_intel8x0_codec_write,
1960 .read = snd_intel8x0_codec_read,
1961 };
1962 static ac97_bus_ops_t ali_bus_ops = {
1963 .write = snd_intel8x0_ali_codec_write,
1964 .read = snd_intel8x0_ali_codec_read,
1965 };
1966
1967 chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
1968 switch (chip->device_type) {
1969 case DEVICE_NFORCE:
1970 chip->spdif_idx = NVD_SPBAR;
1971 break;
1972 case DEVICE_ALI:
1973 chip->spdif_idx = ALID_AC97SPDIFOUT;
1974 break;
1975 case DEVICE_INTEL_ICH4:
1976 chip->spdif_idx = ICHD_SPBAR;
1977 break;
1978 };
1979
1980 chip->in_ac97_init = 1;
1981
1982 memset(&ac97, 0, sizeof(ac97));
1983 ac97.private_data = chip;
1984 ac97.private_free = snd_intel8x0_mixer_free_ac97;
1985 ac97.scaps = AC97_SCAP_SKIP_MODEM;
1986 if (chip->xbox)
1987 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
1988 if (chip->device_type != DEVICE_ALI) {
1989 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
1990 ops = &standard_bus_ops;
1991 if (chip->device_type == DEVICE_INTEL_ICH4) {
1992 codecs = 0;
1993 if (glob_sta & ICH_PCR)
1994 codecs++;
1995 if (glob_sta & ICH_SCR)
1996 codecs++;
1997 if (glob_sta & ICH_TCR)
1998 codecs++;
1999 chip->in_sdin_init = 1;
2000 for (i = 0; i < codecs; i++) {
2001 snd_intel8x0_codec_read_test(chip, i);
2002 chip->ac97_sdin[i] = igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2003 }
2004 chip->in_sdin_init = 0;
2005 } else {
2006 codecs = glob_sta & ICH_SCR ? 2 : 1;
2007 }
2008 } else {
2009 ops = &ali_bus_ops;
2010 codecs = 1;
2011 /* detect the secondary codec */
2012 for (i = 0; i < 100; i++) {
2013 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2014 if (reg & 0x40) {
2015 codecs = 2;
2016 break;
2017 }
2018 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2019 udelay(1);
2020 }
2021 }
2022 if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2023 goto __err;
2024 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
1da177e4
LT		 2025 if (ac97_clock >= 8000 && ac97_clock <= 48000)
2026 pbus->clock = ac97_clock;
2027 /* FIXME: my test board doesn't work well with VRA... */
2028 if (chip->device_type == DEVICE_ALI)
2029 pbus->no_vra = 1;
2030 else
2031 pbus->dra = 1;
2032 chip->ac97_bus = pbus;
2033
2034 ac97.pci = chip->pci;
2035 for (i = 0; i < codecs; i++) {
2036 ac97.num = i;
2037 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2038 if (err != -EACCES)
2039 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);
2040 if (i == 0)
2041 goto __err;
2042 continue;
2043 }
2044 }
2045 /* tune up the primary codec */
2046 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2047 /* enable separate SDINs for ICH4 */
2048 if (chip->device_type == DEVICE_INTEL_ICH4)
2049 pbus->isdin = 1;
2050 /* find the available PCM streams */
2051 i = ARRAY_SIZE(ac97_pcm_defs);
2052 if (chip->device_type != DEVICE_INTEL_ICH4)
2053 i -= 2; /* do not allocate PCM2IN and MIC2 */
2054 if (chip->spdif_idx < 0)
2055 i--; /* do not allocate S/PDIF */
2056 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2057 if (err < 0)
2058 goto __err;
2059 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2060 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2061 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2062 if (chip->spdif_idx >= 0)
2063 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2064 if (chip->device_type == DEVICE_INTEL_ICH4) {
2065 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2066 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2067 }
2068 /* enable separate SDINs for ICH4 */
2069 if (chip->device_type == DEVICE_INTEL_ICH4) {
2070 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2071 u8 tmp = igetbyte(chip, ICHREG(SDM));
2072 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2073 if (pcm) {
2074 tmp |= ICH_SE; /* steer enable for multiple SDINs */
2075 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2076 for (i = 1; i < 4; i++) {
2077 if (pcm->r[0].codec[i]) {
2078 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2079 break;
2080 }
2081 }
2082 } else {
2083 tmp &= ~ICH_SE; /* steer disable */
2084 }
2085 iputbyte(chip, ICHREG(SDM), tmp);
2086 }
2087 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2088 chip->multi4 = 1;
2089 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE))
2090 chip->multi6 = 1;
2091 }
2092 if (pbus->pcms[0].r[1].rslots[0]) {
2093 chip->dra = 1;
2094 }
2095 if (chip->device_type == DEVICE_INTEL_ICH4) {
2096 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2097 chip->smp20bit = 1;
2098 }
2099 if (chip->device_type == DEVICE_NFORCE) {
2100 /* 48kHz only */
2101 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2102 }
2103 if (chip->device_type == DEVICE_INTEL_ICH4) {
2104 /* use slot 10/11 for SPDIF */
2105 u32 val;
2106 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2107 val |= ICH_PCM_SPDIF_1011;
2108 iputdword(chip, ICHREG(GLOB_CNT), val);
2109 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2110 }
2111 chip->in_ac97_init = 0;
2112 return 0;
2113
2114 __err:
2115 /* clear the cold-reset bit for the next chance */
2116 if (chip->device_type != DEVICE_ALI)
2117 iputdword(chip, ICHREG(GLOB_CNT), igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2118 return err;
2119}
2120
2121
2122/*
2123 *
2124 */
2125
2126static void do_ali_reset(intel8x0_t *chip)
2127{
2128 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2129 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2130 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2131 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2132 iputdword(chip, ICHREG(ALI_INTERFACECR),
2133 ICH_ALI_IF_MC|ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2134 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2135 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2136}
2137
2138#define do_delay(chip) do {\
2139 set_current_state(TASK_UNINTERRUPTIBLE);\
2140 schedule_timeout(1);\
2141} while (0)
2142
2143static int snd_intel8x0_ich_chip_init(intel8x0_t *chip, int probing)
2144{
2145 unsigned long end_time;
2146 unsigned int cnt, status, nstatus;
2147
2148 /* put logic to right state */
2149 /* first clear status bits */
2150 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2151 if (chip->device_type == DEVICE_NFORCE)
2152 status |= ICH_NVSPINT;
2153 cnt = igetdword(chip, ICHREG(GLOB_STA));
2154 iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2155
2156 /* ACLink on, 2 channels */
2157 cnt = igetdword(chip, ICHREG(GLOB_CNT));
2158 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2159 /* finish cold or do warm reset */
2160 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2161 iputdword(chip, ICHREG(GLOB_CNT), cnt);
2162 end_time = (jiffies + (HZ / 4)) + 1;
2163 do {
2164 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2165 goto __ok;
2166 do_delay(chip);
2167 } while (time_after_eq(end_time, jiffies));
2168 snd_printk("AC'97 warm reset still in progress? [0x%x]\n", igetdword(chip, ICHREG(GLOB_CNT)));
2169 return -EIO;
2170
2171 __ok:
2172 if (probing) {
2173 /* wait for any codec ready status.
2174 * Once it becomes ready it should remain ready
2175 * as long as we do not disable the ac97 link.
2176 */
2177 end_time = jiffies + HZ;
2178 do {
2179 status = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
2180 if (status)
2181 break;
2182 do_delay(chip);
2183 } while (time_after_eq(end_time, jiffies));
2184 if (! status) {
2185 /* no codec is found */
2186 snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n", igetdword(chip, ICHREG(GLOB_STA)));
2187 return -EIO;
2188 }
2189
2190 if (chip->device_type == DEVICE_INTEL_ICH4)
2191 /* ICH4 can have three codecs */
2192 nstatus = ICH_PCR | ICH_SCR | ICH_TCR;
2193 else
2194 /* others up to two codecs */
2195 nstatus = ICH_PCR | ICH_SCR;
2196
2197 /* wait for other codecs ready status. */
2198 end_time = jiffies + HZ / 4;
2199 while (status != nstatus && time_after_eq(end_time, jiffies)) {
2200 do_delay(chip);
2201 status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus;
2202 }
2203
2204 } else {
2205 /* resume phase */
2206 int i;
2207 status = 0;
2208 for (i = 0; i < 3; i++)
2209 if (chip->ac97[i])
2210 status |= get_ich_codec_bit(chip, i);
2211 /* wait until all the probed codecs are ready */
2212 end_time = jiffies + HZ;
2213 do {
2214 nstatus = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
2215 if (status == nstatus)
2216 break;
2217 do_delay(chip);
2218 } while (time_after_eq(end_time, jiffies));
2219 }
2220
2221 if (chip->device_type == DEVICE_SIS) {
2222 /* unmute the output on SIS7012 */
2223 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2224 }
2225 if (chip->device_type == DEVICE_NFORCE) {
2226 /* enable SPDIF interrupt */
2227 unsigned int val;
2228 pci_read_config_dword(chip->pci, 0x4c, &val);
2229 val |= 0x1000000;
2230 pci_write_config_dword(chip->pci, 0x4c, val);
2231 }
2232 return 0;
2233}
2234
2235static int snd_intel8x0_ali_chip_init(intel8x0_t *chip, int probing)
2236{
2237 u32 reg;
2238 int i = 0;
2239
2240 reg = igetdword(chip, ICHREG(ALI_SCR));
2241 if ((reg & 2) == 0) /* Cold required */
2242 reg |= 2;
2243 else
2244 reg |= 1; /* Warm */
2245 reg &= ~0x80000000; /* ACLink on */
2246 iputdword(chip, ICHREG(ALI_SCR), reg);
2247
2248 for (i = 0; i < HZ / 2; i++) {
2249 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2250 goto __ok;
2251 do_delay(chip);
2252 }
2253 snd_printk(KERN_ERR "AC'97 reset failed.\n");
2254 if (probing)
2255 return -EIO;
2256
2257 __ok:
2258 for (i = 0; i < HZ / 2; i++) {
2259 reg = igetdword(chip, ICHREG(ALI_RTSR));
2260 if (reg & 0x80) /* primary codec */
2261 break;
2262 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2263 do_delay(chip);
2264 }
2265
2266 do_ali_reset(chip);
2267 return 0;
2268}
2269
2270static int snd_intel8x0_chip_init(intel8x0_t *chip, int probing)
2271{
2272 unsigned int i;
2273 int err;
2274
2275 if (chip->device_type != DEVICE_ALI) {
2276 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2277 return err;
2278 iagetword(chip, 0); /* clear semaphore flag */
2279 } else {
2280 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2281 return err;
2282 }
2283
2284 /* disable interrupts */
2285 for (i = 0; i < chip->bdbars_count; i++)
2286 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2287 /* reset channels */
2288 for (i = 0; i < chip->bdbars_count; i++)
2289 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2290 /* initialize Buffer Descriptor Lists */
2291 for (i = 0; i < chip->bdbars_count; i++)
2292 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr);
2293 return 0;
2294}
2295
2296static int snd_intel8x0_free(intel8x0_t *chip)
2297{
2298 unsigned int i;
2299
2300 if (chip->irq < 0)
2301 goto __hw_end;
2302 /* disable interrupts */
2303 for (i = 0; i < chip->bdbars_count; i++)
2304 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2305 /* reset channels */
2306 for (i = 0; i < chip->bdbars_count; i++)
2307 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2308 if (chip->device_type == DEVICE_NFORCE) {
2309 /* stop the spdif interrupt */
2310 unsigned int val;
2311 pci_read_config_dword(chip->pci, 0x4c, &val);
2312 val &= ~0x1000000;
2313 pci_write_config_dword(chip->pci, 0x4c, val);
2314 }
2315 /* --- */
2316 synchronize_irq(chip->irq);
2317 __hw_end:
2318 if (chip->irq >= 0)
2319 free_irq(chip->irq, (void *)chip);
2320 if (chip->bdbars.area) {
2321 if (chip->fix_nocache)
2322 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
2323 snd_dma_free_pages(&chip->bdbars);
2324 }
2325 if (chip->remap_addr)
2326 iounmap(chip->remap_addr);
2327 if (chip->remap_bmaddr)
2328 iounmap(chip->remap_bmaddr);
2329 pci_release_regions(chip->pci);
2330 pci_disable_device(chip->pci);
2331 kfree(chip);
2332 return 0;
2333}
2334
2335#ifdef CONFIG_PM
2336/*
2337 * power management
2338 */
2339static int intel8x0_suspend(snd_card_t *card, pm_message_t state)
2340{
2341 intel8x0_t *chip = card->pm_private_data;
2342 int i;
2343
2344 for (i = 0; i < chip->pcm_devs; i++)
2345 snd_pcm_suspend_all(chip->pcm[i]);
2346 /* clear nocache */
2347 if (chip->fix_nocache) {
2348 for (i = 0; i < chip->bdbars_count; i++) {
2349 ichdev_t *ichdev = &chip->ichd[i];
2350 if (ichdev->substream && ichdev->page_attr_changed) {
2351 snd_pcm_runtime_t *runtime = ichdev->substream->runtime;
2352 if (runtime->dma_area)
2353 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0);
2354 }
2355 }
2356 }
2357 for (i = 0; i < 3; i++)
2358 if (chip->ac97[i])
2359 snd_ac97_suspend(chip->ac97[i]);
52b72388
TI		 2360 if (chip->device_type == DEVICE_INTEL_ICH4)
2361 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
adbedd34 2362
90158b83
RW		 2363 if (chip->irq >= 0)
2364 free_irq(chip->irq, (void *)chip);
1da177e4
LT		 2365 pci_disable_device(chip->pci);
2366 return 0;
2367}
2368
2369static int intel8x0_resume(snd_card_t *card)
2370{
2371 intel8x0_t *chip = card->pm_private_data;
2372 int i;
2373
2374 pci_enable_device(chip->pci);
2375 pci_set_master(chip->pci);
90158b83
RW		 2376 request_irq(chip->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip);
2377 synchronize_irq(chip->irq);
2378 snd_intel8x0_chip_init(chip, 1);
1da177e4 2379
52b72388
TI		 2380 /* re-initialize mixer stuff */
2381 if (chip->device_type == DEVICE_INTEL_ICH4) {
2382 /* enable separate SDINs for ICH4 */
2383 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2384 /* use slot 10/11 for SPDIF */
2385 iputdword(chip, ICHREG(GLOB_CNT),
2386 (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2387 ICH_PCM_SPDIF_1011);
2388 }
2389
1da177e4
LT		 2390 /* refill nocache */
2391 if (chip->fix_nocache)
2392 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2393
2394 for (i = 0; i < 3; i++)
2395 if (chip->ac97[i])
2396 snd_ac97_resume(chip->ac97[i]);
2397
2398 /* refill nocache */
2399 if (chip->fix_nocache) {
2400 for (i = 0; i < chip->bdbars_count; i++) {
2401 ichdev_t *ichdev = &chip->ichd[i];
2402 if (ichdev->substream && ichdev->page_attr_changed) {
2403 snd_pcm_runtime_t *runtime = ichdev->substream->runtime;
2404 if (runtime->dma_area)
2405 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
2406 }
2407 }
2408 }
2409
1cfe43d2
TI		 2410 /* resume status */
2411 for (i = 0; i < chip->bdbars_count; i++) {
2412 ichdev_t *ichdev = &chip->ichd[i];
2413 unsigned long port = ichdev->reg_offset;
2414 if (! ichdev->substream || ! ichdev->suspended)
2415 continue;
2416 if (ichdev->ichd == ICHD_PCMOUT)
2417 snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2418 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2419 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2420 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2421 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2422 }
2423
1da177e4
LT		 2424 return 0;
2425}
2426#endif /* CONFIG_PM */
2427
2428#define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */
2429
2430static void __devinit intel8x0_measure_ac97_clock(intel8x0_t *chip)
2431{
2432 snd_pcm_substream_t *subs;
2433 ichdev_t *ichdev;
2434 unsigned long port;
2435 unsigned long pos, t;
2436 struct timeval start_time, stop_time;
2437
2438 if (chip->ac97_bus->clock != 48000)
2439 return; /* specified in module option */
2440
2441 subs = chip->pcm[0]->streams[0].substream;
2442 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2443 snd_printk("no playback buffer allocated - aborting measure ac97 clock\n");
2444 return;
2445 }
2446 ichdev = &chip->ichd[ICHD_PCMOUT];
2447 ichdev->physbuf = subs->dma_buffer.addr;
2448 ichdev->size = chip->ichd[ICHD_PCMOUT].fragsize = INTEL8X0_TESTBUF_SIZE;
2449 ichdev->substream = NULL; /* don't process interrupts */
2450
2451 /* set rate */
2452 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2453 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock);
2454 return;
2455 }
2456 snd_intel8x0_setup_periods(chip, ichdev);
2457 port = ichdev->reg_offset;
2458 spin_lock_irq(&chip->reg_lock);
2459 chip->in_measurement = 1;
2460 /* trigger */
2461 if (chip->device_type != DEVICE_ALI)
2462 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2463 else {
2464 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2465 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2466 }
2467 do_gettimeofday(&start_time);
2468 spin_unlock_irq(&chip->reg_lock);
ef21ca24 2469 msleep(50);
1da177e4
LT		 2470 spin_lock_irq(&chip->reg_lock);
2471 /* check the position */
2472 pos = ichdev->fragsize1;
2473 pos -= igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << ichdev->pos_shift;
2474 pos += ichdev->position;
2475 chip->in_measurement = 0;
2476 do_gettimeofday(&stop_time);
2477 /* stop */
2478 if (chip->device_type == DEVICE_ALI) {
2479 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 8));
2480 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2481 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2482 ;
2483 } else {
2484 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2485 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2486 ;
2487 }
2488 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2489 spin_unlock_irq(&chip->reg_lock);
2490
2491 t = stop_time.tv_sec - start_time.tv_sec;
2492 t *= 1000000;
2493 t += stop_time.tv_usec - start_time.tv_usec;
2494 printk(KERN_INFO "%s: measured %lu usecs\n", __FUNCTION__, t);
2495 if (t == 0) {
2496 snd_printk(KERN_ERR "?? calculation error..\n");
2497 return;
2498 }
2499 pos = (pos / 4) * 1000;
2500 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2501 if (pos < 40000 || pos >= 60000)
2502 /* abnormal value. hw problem? */
2503 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos);
2504 else if (pos < 47500 || pos > 48500)
2505 /* not 48000Hz, tuning the clock.. */
2506 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2507 printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
2508}
2509
2510static void snd_intel8x0_proc_read(snd_info_entry_t * entry,
2511 snd_info_buffer_t * buffer)
2512{
2513 intel8x0_t *chip = entry->private_data;
2514 unsigned int tmp;
2515
2516 snd_iprintf(buffer, "Intel8x0\n\n");
2517 if (chip->device_type == DEVICE_ALI)
2518 return;
2519 tmp = igetdword(chip, ICHREG(GLOB_STA));
2520 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2521 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
2522 if (chip->device_type == DEVICE_INTEL_ICH4)
2523 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2524 snd_iprintf(buffer, "AC'97 codecs ready :%s%s%s%s\n",
2525 tmp & ICH_PCR ? " primary" : "",
2526 tmp & ICH_SCR ? " secondary" : "",
2527 tmp & ICH_TCR ? " tertiary" : "",
2528 (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : "");
2529 if (chip->device_type == DEVICE_INTEL_ICH4)
2530 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n",
2531 chip->ac97_sdin[0],
2532 chip->ac97_sdin[1],
2533 chip->ac97_sdin[2]);
2534}
2535
2536static void __devinit snd_intel8x0_proc_init(intel8x0_t * chip)
2537{
2538 snd_info_entry_t *entry;
2539
2540 if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
2541 snd_info_set_text_ops(entry, chip, 1024, snd_intel8x0_proc_read);
2542}
2543
2544static int snd_intel8x0_dev_free(snd_device_t *device)
2545{
2546 intel8x0_t *chip = device->device_data;
2547 return snd_intel8x0_free(chip);
2548}
2549
2550struct ich_reg_info {
2551 unsigned int int_sta_mask;
2552 unsigned int offset;
2553};
2554
2555static int __devinit snd_intel8x0_create(snd_card_t * card,
2556 struct pci_dev *pci,
2557 unsigned long device_type,
a06147d2 2558 int buggy_sem,
1da177e4
LT		 2559 intel8x0_t ** r_intel8x0)
2560{
2561 intel8x0_t *chip;
2562 int err;
2563 unsigned int i;
2564 unsigned int int_sta_masks;
2565 ichdev_t *ichdev;
2566 static snd_device_ops_t ops = {
2567 .dev_free = snd_intel8x0_dev_free,
2568 };
2569
2570 static unsigned int bdbars[] = {
2571 3, /* DEVICE_INTEL */
2572 6, /* DEVICE_INTEL_ICH4 */
2573 3, /* DEVICE_SIS */
2574 6, /* DEVICE_ALI */
2575 4, /* DEVICE_NFORCE */
2576 };
2577 static struct ich_reg_info intel_regs[6] = {
2578 { ICH_PIINT, 0 },
2579 { ICH_POINT, 0x10 },
2580 { ICH_MCINT, 0x20 },
2581 { ICH_M2INT, 0x40 },
2582 { ICH_P2INT, 0x50 },
2583 { ICH_SPINT, 0x60 },
2584 };
2585 static struct ich_reg_info nforce_regs[4] = {
2586 { ICH_PIINT, 0 },
2587 { ICH_POINT, 0x10 },
2588 { ICH_MCINT, 0x20 },
2589 { ICH_NVSPINT, 0x70 },
2590 };
2591 static struct ich_reg_info ali_regs[6] = {
2592 { ALI_INT_PCMIN, 0x40 },
2593 { ALI_INT_PCMOUT, 0x50 },
2594 { ALI_INT_MICIN, 0x60 },
2595 { ALI_INT_CODECSPDIFOUT, 0x70 },
2596 { ALI_INT_SPDIFIN, 0xa0 },
2597 { ALI_INT_SPDIFOUT, 0xb0 },
2598 };
2599 struct ich_reg_info *tbl;
2600
2601 *r_intel8x0 = NULL;
2602
2603 if ((err = pci_enable_device(pci)) < 0)
2604 return err;
2605
e560d8d8 2606 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1da177e4
LT		 2607 if (chip == NULL) {
2608 pci_disable_device(pci);
2609 return -ENOMEM;
2610 }
2611 spin_lock_init(&chip->reg_lock);
2612 chip->device_type = device_type;
2613 chip->card = card;
2614 chip->pci = pci;
2615 chip->irq = -1;
a06147d2 2616 chip->buggy_semaphore = buggy_sem;
1da177e4
LT		 2617
2618 if (pci->vendor == PCI_VENDOR_ID_INTEL &&
2619 pci->device == PCI_DEVICE_ID_INTEL_440MX)
2620 chip->fix_nocache = 1; /* enable workaround */
2621
2622 /* some Nforce[2] and ICH boards have problems with IRQ handling.
2623 * Needs to return IRQ_HANDLED for unknown irqs.
2624 */
2625 if (device_type == DEVICE_NFORCE)
2626 chip->buggy_irq = 1;
2627
2628 if ((err = pci_request_regions(pci, card->shortname)) < 0) {
2629 kfree(chip);
2630 pci_disable_device(pci);
2631 return err;
2632 }
2633
2634 if (device_type == DEVICE_ALI) {
2635 /* ALI5455 has no ac97 region */
2636 chip->bmaddr = pci_resource_start(pci, 0);
2637 goto port_inited;
2638 }
2639
2640 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) { /* ICH4 and Nforce */
2641 chip->mmio = 1;
2642 chip->addr = pci_resource_start(pci, 2);
2643 chip->remap_addr = ioremap_nocache(chip->addr,
2644 pci_resource_len(pci, 2));
2645 if (chip->remap_addr == NULL) {
2646 snd_printk("AC'97 space ioremap problem\n");
2647 snd_intel8x0_free(chip);
2648 return -EIO;
2649 }
2650 } else {
2651 chip->addr = pci_resource_start(pci, 0);
2652 }
2653 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) { /* ICH4 */
2654 chip->bm_mmio = 1;
2655 chip->bmaddr = pci_resource_start(pci, 3);
2656 chip->remap_bmaddr = ioremap_nocache(chip->bmaddr,
2657 pci_resource_len(pci, 3));
2658 if (chip->remap_bmaddr == NULL) {
2659 snd_printk("Controller space ioremap problem\n");
2660 snd_intel8x0_free(chip);
2661 return -EIO;
2662 }
2663 } else {
2664 chip->bmaddr = pci_resource_start(pci, 1);
2665 }
2666
2667 port_inited:
2668 if (request_irq(pci->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip)) {
2669 snd_printk("unable to grab IRQ %d\n", pci->irq);
2670 snd_intel8x0_free(chip);
2671 return -EBUSY;
2672 }
2673 chip->irq = pci->irq;
2674 pci_set_master(pci);
2675 synchronize_irq(chip->irq);
2676
2677 chip->bdbars_count = bdbars[device_type];
2678
2679 /* initialize offsets */
2680 switch (device_type) {
2681 case DEVICE_NFORCE:
2682 tbl = nforce_regs;
2683 break;
2684 case DEVICE_ALI:
2685 tbl = ali_regs;
2686 break;
2687 default:
2688 tbl = intel_regs;
2689 break;
2690 }
2691 for (i = 0; i < chip->bdbars_count; i++) {
2692 ichdev = &chip->ichd[i];
2693 ichdev->ichd = i;
2694 ichdev->reg_offset = tbl[i].offset;
2695 ichdev->int_sta_mask = tbl[i].int_sta_mask;
2696 if (device_type == DEVICE_SIS) {
2697 /* SiS 7012 swaps the registers */
2698 ichdev->roff_sr = ICH_REG_OFF_PICB;
2699 ichdev->roff_picb = ICH_REG_OFF_SR;
2700 } else {
2701 ichdev->roff_sr = ICH_REG_OFF_SR;
2702 ichdev->roff_picb = ICH_REG_OFF_PICB;
2703 }
2704 if (device_type == DEVICE_ALI)
2705 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
2706 /* SIS7012 handles the pcm data in bytes, others are in samples */
2707 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
2708 }
2709
2710 /* allocate buffer descriptor lists */
2711 /* the start of each lists must be aligned to 8 bytes */
2712 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
2713 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
2714 &chip->bdbars) < 0) {
2715 snd_intel8x0_free(chip);
2716 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n");
2717 return -ENOMEM;
2718 }
2719 /* tables must be aligned to 8 bytes here, but the kernel pages
2720 are much bigger, so we don't care (on i386) */
2721 /* workaround for 440MX */
2722 if (chip->fix_nocache)
2723 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2724 int_sta_masks = 0;
2725 for (i = 0; i < chip->bdbars_count; i++) {
2726 ichdev = &chip->ichd[i];
2727 ichdev->bdbar = ((u32 *)chip->bdbars.area) + (i * ICH_MAX_FRAGS * 2);
2728 ichdev->bdbar_addr = chip->bdbars.addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
2729 int_sta_masks |= ichdev->int_sta_mask;
2730 }
2731 chip->int_sta_reg = device_type == DEVICE_ALI ? ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
2732 chip->int_sta_mask = int_sta_masks;
2733
2734 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
2735 snd_intel8x0_free(chip);
2736 return err;
2737 }
2738
2739 snd_card_set_pm_callback(card, intel8x0_suspend, intel8x0_resume, chip);
2740
2741 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2742 snd_intel8x0_free(chip);
2743 return err;
2744 }
2745
2746 snd_card_set_dev(card, &pci->dev);
2747
2748 *r_intel8x0 = chip;
2749 return 0;
2750}
2751
2752static struct shortname_table {
2753 unsigned int id;
2754 const char *s;
2755} shortnames[] __devinitdata = {
8cdfd251
TI		 2756 { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
2757 { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
2758 { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
1da177e4 2759 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
8cdfd251
TI		 2760 { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
2761 { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
2762 { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
1da177e4
LT		 2763 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
2764 { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
2765 { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
3437c5df 2766 { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
1da177e4 2767 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
8cdfd251 2768 { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
1da177e4
LT		 2769 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
2770 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
2771 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
2772 { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
2773 { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
2774 { 0x003a, "NVidia MCP04" },
2775 { 0x746d, "AMD AMD8111" },
2776 { 0x7445, "AMD AMD768" },
2777 { 0x5455, "ALi M5455" },
2778 { 0, NULL },
2779};
2780
2781static int __devinit snd_intel8x0_probe(struct pci_dev *pci,
2782 const struct pci_device_id *pci_id)
2783{
2784 static int dev;
2785 snd_card_t *card;
2786 intel8x0_t *chip;
2787 int err;
2788 struct shortname_table *name;
2789
2790 if (dev >= SNDRV_CARDS)
2791 return -ENODEV;
2792 if (!enable[dev]) {
2793 dev++;
2794 return -ENOENT;
2795 }
2796
2797 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2798 if (card == NULL)
2799 return -ENOMEM;
2800
2801 switch (pci_id->driver_data) {
2802 case DEVICE_NFORCE:
2803 strcpy(card->driver, "NFORCE");
2804 break;
2805 case DEVICE_INTEL_ICH4:
2806 strcpy(card->driver, "ICH4");
2807 break;
2808 default:
2809 strcpy(card->driver, "ICH");
2810 break;
2811 }
2812
2813 strcpy(card->shortname, "Intel ICH");
2814 for (name = shortnames; name->id; name++) {
2815 if (pci->device == name->id) {
2816 strcpy(card->shortname, name->s);
2817 break;
2818 }
2819 }
2820
a06147d2
TI		 2821 if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data,
2822 buggy_semaphore[dev], &chip)) < 0) {
1da177e4
LT		 2823 snd_card_free(card);
2824 return err;
2825 }
2826 if (buggy_irq[dev])
2827 chip->buggy_irq = 1;
2828 if (xbox[dev])
2829 chip->xbox = 1;
2830
2831 if ((err = snd_intel8x0_mixer(chip, ac97_clock[dev], ac97_quirk[dev])) < 0) {
2832 snd_card_free(card);
2833 return err;
2834 }
2835 if ((err = snd_intel8x0_pcm(chip)) < 0) {
2836 snd_card_free(card);
2837 return err;
2838 }
2839
2840 snd_intel8x0_proc_init(chip);
2841
2842 snprintf(card->longname, sizeof(card->longname),
2843 "%s with %s at %#lx, irq %i", card->shortname,
2844 snd_ac97_get_short_name(chip->ac97[0]), chip->addr, chip->irq);
2845
2846 if (! ac97_clock[dev])
2847 intel8x0_measure_ac97_clock(chip);
2848
2849 if ((err = snd_card_register(card)) < 0) {
2850 snd_card_free(card);
2851 return err;
2852 }
2853 pci_set_drvdata(pci, card);
2854 dev++;
2855 return 0;
2856}
2857
2858static void __devexit snd_intel8x0_remove(struct pci_dev *pci)
2859{
2860 snd_card_free(pci_get_drvdata(pci));
2861 pci_set_drvdata(pci, NULL);
2862}
2863
2864static struct pci_driver driver = {
2865 .name = "Intel ICH",
3bcd4649 2866 .owner = THIS_MODULE,
1da177e4
LT		 2867 .id_table = snd_intel8x0_ids,
2868 .probe = snd_intel8x0_probe,
2869 .remove = __devexit_p(snd_intel8x0_remove),
2870 SND_PCI_PM_CALLBACKS
2871};
2872
2873
2874static int __init alsa_card_intel8x0_init(void)
2875{
01d25d46 2876 return pci_register_driver(&driver);
1da177e4
LT		 2877}
2878
2879static void __exit alsa_card_intel8x0_exit(void)
2880{
2881 pci_unregister_driver(&driver);
2882}
2883
2884module_init(alsa_card_intel8x0_init)
2885module_exit(alsa_card_intel8x0_exit)
Linux 6.x block layer and io_uring tree(s)