[linux-2.6-block.git] / sound / pci / ice1712 / wm8776.h

#ifndef __SOUND_WM8776_H
#define __SOUND_WM8776_H

/*
 *   ALSA driver for ICEnsemble VT17xx
 *
 *   Lowlevel functions for WM8776 codec
 *
 *	Copyright (c) 2012 Ondrej Zary <linux@rainbow-software.org>
 *
 *   This program is free software; you can redistribute it and/or modify
 *   it under the terms of the GNU General Public License as published by
 *   the Free Software Foundation; either version 2 of the License, or
 *   (at your option) any later version.
 *
 *   This program is distributed in the hope that it will be useful,
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *   GNU General Public License for more details.
 *
 *   You should have received a copy of the GNU General Public License
 *   along with this program; if not, write to the Free Software
 *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 *
 */

#define WM8776_REG_HPLVOL	0x00
#define WM8776_REG_HPRVOL	0x01
#define WM8776_REG_HPMASTER	0x02
#define WM8776_HPVOL_MASK		0x17f		/* incl. update bit */
#define WM8776_VOL_HPZCEN		(1 << 7)	/* zero cross detect */
#define WM8776_VOL_UPDATE		(1 << 8)	/* update volume */
#define WM8776_REG_DACLVOL	0x03
#define WM8776_REG_DACRVOL	0x04
#define WM8776_REG_DACMASTER	0x05
#define WM8776_DACVOL_MASK		0x1ff		/* incl. update bit */
#define WM8776_REG_PHASESWAP	0x06
#define WM8776_PHASE_INVERTL		(1 << 0)
#define WM8776_PHASE_INVERTR		(1 << 1)
#define WM8776_REG_DACCTRL1	0x07
#define WM8776_DAC_DZCEN		(1 << 0)
#define WM8776_DAC_ATC			(1 << 1)
#define WM8776_DAC_IZD			(1 << 2)
#define WM8776_DAC_TOD			(1 << 3)
#define WM8776_DAC_PL_MASK		0xf0
#define WM8776_DAC_PL_LL		(1 << 4)	/* L chan: L signal */
#define WM8776_DAC_PL_LR		(2 << 4)	/* L chan: R signal */
#define WM8776_DAC_PL_LB		(3 << 4)	/* L chan: both */
#define WM8776_DAC_PL_RL		(1 << 6)	/* R chan: L signal */
#define WM8776_DAC_PL_RR		(2 << 6)	/* R chan: R signal */
#define WM8776_DAC_PL_RB		(3 << 6)	/* R chan: both */
#define WM8776_REG_DACMUTE	0x08
#define WM8776_DACMUTE			(1 << 0)
#define WM8776_REG_DACCTRL2	0x09
#define WM8776_DAC2_DEEMPH		(1 << 0)
#define WM8776_DAC2_ZFLAG_DISABLE	(0 << 1)
#define WM8776_DAC2_ZFLAG_OWN		(1 << 1)
#define WM8776_DAC2_ZFLAG_BOTH		(2 << 1)
#define WM8776_DAC2_ZFLAG_EITHER	(3 << 1)
#define WM8776_REG_DACIFCTRL	0x0a
#define WM8776_FMT_RIGHTJ		(0 << 0)
#define WM8776_FMT_LEFTJ		(1 << 0)
#define WM8776_FMT_I2S			(2 << 0)
#define WM8776_FMT_DSP			(3 << 0)
#define WM8776_FMT_DSP_LATE		(1 << 2)	/* in DSP mode */
#define WM8776_FMT_LRC_INVERTED		(1 << 2)	/* in other modes */
#define WM8776_FMT_BCLK_INVERTED	(1 << 3)
#define WM8776_FMT_16BIT		(0 << 4)
#define WM8776_FMT_20BIT		(1 << 4)
#define WM8776_FMT_24BIT		(2 << 4)
#define WM8776_FMT_32BIT		(3 << 4)
#define WM8776_REG_ADCIFCTRL	0x0b
#define WM8776_FMT_ADCMCLK_INVERTED	(1 << 6)
#define WM8776_FMT_ADCHPD		(1 << 8)
#define WM8776_REG_MSTRCTRL	0x0c
#define WM8776_IF_ADC256FS		(2 << 0)
#define WM8776_IF_ADC384FS		(3 << 0)
#define WM8776_IF_ADC512FS		(4 << 0)
#define WM8776_IF_ADC768FS		(5 << 0)
#define WM8776_IF_OVERSAMP64		(1 << 3)
#define WM8776_IF_DAC128FS		(0 << 4)
#define WM8776_IF_DAC192FS		(1 << 4)
#define WM8776_IF_DAC256FS		(2 << 4)
#define WM8776_IF_DAC384FS		(3 << 4)
#define WM8776_IF_DAC512FS		(4 << 4)
#define WM8776_IF_DAC768FS		(5 << 4)
#define WM8776_IF_DAC_MASTER		(1 << 7)
#define WM8776_IF_ADC_MASTER		(1 << 8)
#define WM8776_REG_PWRDOWN	0x0d
#define WM8776_PWR_PDWN			(1 << 0)
#define WM8776_PWR_ADCPD		(1 << 1)
#define WM8776_PWR_DACPD		(1 << 2)
#define WM8776_PWR_HPPD			(1 << 3)
#define WM8776_PWR_AINPD		(1 << 6)
#define WM8776_REG_ADCLVOL	0x0e
#define WM8776_REG_ADCRVOL	0x0f
#define WM8776_ADC_GAIN_MASK		0xff
#define WM8776_ADC_ZCEN			(1 << 8)
#define WM8776_REG_ALCCTRL1	0x10
#define WM8776_ALC1_LCT_MASK		0x0f	/* 0=-16dB, 1=-15dB..15=-1dB */
#define WM8776_ALC1_MAXGAIN_MASK	0x70	/* 0,1=0dB, 2=+4dB...7=+24dB */
#define WM8776_ALC1_LCSEL_MASK		0x180
#define WM8776_ALC1_LCSEL_LIMITER	(0 << 7)
#define WM8776_ALC1_LCSEL_ALCR		(1 << 7)
#define WM8776_ALC1_LCSEL_ALCL		(2 << 7)
#define WM8776_ALC1_LCSEL_ALCSTEREO	(3 << 7)
#define WM8776_REG_ALCCTRL2	0x11
#define WM8776_ALC2_HOLD_MASK		0x0f	/*0=0ms, 1=2.67ms, 2=5.33ms.. */
#define WM8776_ALC2_ZCEN		(1 << 7)
#define WM8776_ALC2_LCEN		(1 << 8)
#define WM8776_REG_ALCCTRL3	0x12
#define WM8776_ALC3_ATK_MASK		0x0f
#define WM8776_ALC3_DCY_MASK		0xf0
#define WM8776_ALC3_FDECAY		(1 << 8)
#define WM8776_REG_NOISEGATE	0x13
#define WM8776_NGAT_ENABLE		(1 << 0)
#define WM8776_NGAT_THR_MASK		0x1c	/*0=-78dB, 1=-72dB...7=-36dB */
#define WM8776_REG_LIMITER	0x14
#define WM8776_LIM_MAXATTEN_MASK	0x0f
#define WM8776_LIM_TRANWIN_MASK		0x70	/*0=0us, 1=62.5us, 2=125us.. */
#define WM8776_REG_ADCMUX	0x15
#define WM8776_ADC_MUX_AIN1		(1 << 0)
#define WM8776_ADC_MUX_AIN2		(1 << 1)
#define WM8776_ADC_MUX_AIN3		(1 << 2)
#define WM8776_ADC_MUX_AIN4		(1 << 3)
#define WM8776_ADC_MUX_AIN5		(1 << 4)
#define WM8776_ADC_MUTER		(1 << 6)
#define WM8776_ADC_MUTEL		(1 << 7)
#define WM8776_ADC_LRBOTH		(1 << 8)
#define WM8776_REG_OUTMUX	0x16
#define WM8776_OUTMUX_DAC		(1 << 0)
#define WM8776_OUTMUX_AUX		(1 << 1)
#define WM8776_OUTMUX_BYPASS		(1 << 2)
#define WM8776_REG_RESET	0x17

#define WM8776_REG_COUNT	0x17	/* don't cache the RESET register */

struct snd_wm8776;

struct snd_wm8776_ops {
	void (*write)(struct snd_wm8776 *wm, u8 addr, u8 data);
};

enum snd_wm8776_ctl_id {
	WM8776_CTL_DAC_VOL,
	WM8776_CTL_DAC_SW,
	WM8776_CTL_DAC_ZC_SW,
	WM8776_CTL_HP_VOL,
	WM8776_CTL_HP_SW,
	WM8776_CTL_HP_ZC_SW,
	WM8776_CTL_AUX_SW,
	WM8776_CTL_BYPASS_SW,
	WM8776_CTL_DAC_IZD_SW,
	WM8776_CTL_PHASE_SW,
	WM8776_CTL_DEEMPH_SW,
	WM8776_CTL_ADC_VOL,
	WM8776_CTL_ADC_SW,
	WM8776_CTL_INPUT1_SW,
	WM8776_CTL_INPUT2_SW,
	WM8776_CTL_INPUT3_SW,
	WM8776_CTL_INPUT4_SW,
	WM8776_CTL_INPUT5_SW,
	WM8776_CTL_AGC_SEL,
	WM8776_CTL_LIM_THR,
	WM8776_CTL_LIM_ATK,
	WM8776_CTL_LIM_DCY,
	WM8776_CTL_LIM_TRANWIN,
	WM8776_CTL_LIM_MAXATTN,
	WM8776_CTL_ALC_TGT,
	WM8776_CTL_ALC_ATK,
	WM8776_CTL_ALC_DCY,
	WM8776_CTL_ALC_MAXGAIN,
	WM8776_CTL_ALC_MAXATTN,
	WM8776_CTL_ALC_HLD,
	WM8776_CTL_NGT_SW,
	WM8776_CTL_NGT_THR,

	WM8776_CTL_COUNT,
};

#define WM8776_ENUM_MAX		16

#define WM8776_FLAG_STEREO	(1 << 0)
#define WM8776_FLAG_VOL_UPDATE	(1 << 1)
#define WM8776_FLAG_INVERT	(1 << 2)
#define WM8776_FLAG_LIM		(1 << 3)
#define WM8776_FLAG_ALC		(1 << 4)

struct snd_wm8776_ctl {
	const char *name;
	snd_ctl_elem_type_t type;
	const char *const enum_names[WM8776_ENUM_MAX];
	const unsigned int *tlv;
	u16 reg1, reg2, mask1, mask2, min, max, flags;
	void (*set)(struct snd_wm8776 *wm, u16 ch1, u16 ch2);
	void (*get)(struct snd_wm8776 *wm, u16 *ch1, u16 *ch2);
};

enum snd_wm8776_agc_mode {
	WM8776_AGC_OFF,
	WM8776_AGC_LIM,
	WM8776_AGC_ALC_R,
	WM8776_AGC_ALC_L,
	WM8776_AGC_ALC_STEREO
};

struct snd_wm8776 {
	struct snd_card *card;
	struct snd_wm8776_ctl ctl[WM8776_CTL_COUNT];
	enum snd_wm8776_agc_mode agc_mode;
	struct snd_wm8776_ops ops;
	u16 regs[WM8776_REG_COUNT];	/* 9-bit registers */
};


void snd_wm8776_init(struct snd_wm8776 *wm);
void snd_wm8776_resume(struct snd_wm8776 *wm);
void snd_wm8776_set_dac_if(struct snd_wm8776 *wm, u16 dac);
void snd_wm8776_set_adc_if(struct snd_wm8776 *wm, u16 adc);
void snd_wm8776_set_master_mode(struct snd_wm8776 *wm, u16 mode);
void snd_wm8776_set_power(struct snd_wm8776 *wm, u16 power);
void snd_wm8776_volume_restore(struct snd_wm8776 *wm);
int snd_wm8776_build_controls(struct snd_wm8776 *wm);

#endif /* __SOUND_WM8776_H */
Commit	Line	Data
bfe51427 OZ	1	#ifndef __SOUND_WM8776_H
	2	#define __SOUND_WM8776_H
	3
	4	/*
	5	* ALSA driver for ICEnsemble VT17xx
	6	*
	7	* Lowlevel functions for WM8776 codec
	8	*
	9	* Copyright (c) 2012 Ondrej Zary <linux@rainbow-software.org>
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2 of the License, or
	14	* (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	24	*
	25	*/
	26
	27	#define WM8776_REG_HPLVOL 0x00
	28	#define WM8776_REG_HPRVOL 0x01
	29	#define WM8776_REG_HPMASTER 0x02
	30	#define WM8776_HPVOL_MASK 0x17f /* incl. update bit */
	31	#define WM8776_VOL_HPZCEN (1 << 7) /* zero cross detect */
	32	#define WM8776_VOL_UPDATE (1 << 8) /* update volume */
	33	#define WM8776_REG_DACLVOL 0x03
	34	#define WM8776_REG_DACRVOL 0x04
	35	#define WM8776_REG_DACMASTER 0x05
	36	#define WM8776_DACVOL_MASK 0x1ff /* incl. update bit */
	37	#define WM8776_REG_PHASESWAP 0x06
	38	#define WM8776_PHASE_INVERTL (1 << 0)
	39	#define WM8776_PHASE_INVERTR (1 << 1)
	40	#define WM8776_REG_DACCTRL1 0x07
	41	#define WM8776_DAC_DZCEN (1 << 0)
	42	#define WM8776_DAC_ATC (1 << 1)
	43	#define WM8776_DAC_IZD (1 << 2)
	44	#define WM8776_DAC_TOD (1 << 3)
	45	#define WM8776_DAC_PL_MASK 0xf0
	46	#define WM8776_DAC_PL_LL (1 << 4) /* L chan: L signal */
	47	#define WM8776_DAC_PL_LR (2 << 4) /* L chan: R signal */
	48	#define WM8776_DAC_PL_LB (3 << 4) /* L chan: both */
	49	#define WM8776_DAC_PL_RL (1 << 6) /* R chan: L signal */
	50	#define WM8776_DAC_PL_RR (2 << 6) /* R chan: R signal */
	51	#define WM8776_DAC_PL_RB (3 << 6) /* R chan: both */
	52	#define WM8776_REG_DACMUTE 0x08
	53	#define WM8776_DACMUTE (1 << 0)
	54	#define WM8776_REG_DACCTRL2 0x09
	55	#define WM8776_DAC2_DEEMPH (1 << 0)
	56	#define WM8776_DAC2_ZFLAG_DISABLE (0 << 1)
	57	#define WM8776_DAC2_ZFLAG_OWN (1 << 1)
	58	#define WM8776_DAC2_ZFLAG_BOTH (2 << 1)
	59	#define WM8776_DAC2_ZFLAG_EITHER (3 << 1)
	60	#define WM8776_REG_DACIFCTRL 0x0a
	61	#define WM8776_FMT_RIGHTJ (0 << 0)
	62	#define WM8776_FMT_LEFTJ (1 << 0)
	63	#define WM8776_FMT_I2S (2 << 0)
	64	#define WM8776_FMT_DSP (3 << 0)
65	#define WM8776_FMT_DSP_LATE (1 << 2) /* in DSP mode */
66	#define WM8776_FMT_LRC_INVERTED (1 << 2) /* in other modes */
67	#define WM8776_FMT_BCLK_INVERTED (1 << 3)
68	#define WM8776_FMT_16BIT (0 << 4)
69	#define WM8776_FMT_20BIT (1 << 4)
70	#define WM8776_FMT_24BIT (2 << 4)
71	#define WM8776_FMT_32BIT (3 << 4)
72	#define WM8776_REG_ADCIFCTRL 0x0b
73	#define WM8776_FMT_ADCMCLK_INVERTED (1 << 6)
74	#define WM8776_FMT_ADCHPD (1 << 8)
75	#define WM8776_REG_MSTRCTRL 0x0c
76	#define WM8776_IF_ADC256FS (2 << 0)
77	#define WM8776_IF_ADC384FS (3 << 0)
78	#define WM8776_IF_ADC512FS (4 << 0)
79	#define WM8776_IF_ADC768FS (5 << 0)
80	#define WM8776_IF_OVERSAMP64 (1 << 3)
81	#define WM8776_IF_DAC128FS (0 << 4)
82	#define WM8776_IF_DAC192FS (1 << 4)
83	#define WM8776_IF_DAC256FS (2 << 4)
84	#define WM8776_IF_DAC384FS (3 << 4)
85	#define WM8776_IF_DAC512FS (4 << 4)
86	#define WM8776_IF_DAC768FS (5 << 4)
87	#define WM8776_IF_DAC_MASTER (1 << 7)
88	#define WM8776_IF_ADC_MASTER (1 << 8)
89	#define WM8776_REG_PWRDOWN 0x0d
90	#define WM8776_PWR_PDWN (1 << 0)
91	#define WM8776_PWR_ADCPD (1 << 1)
92	#define WM8776_PWR_DACPD (1 << 2)
93	#define WM8776_PWR_HPPD (1 << 3)
94	#define WM8776_PWR_AINPD (1 << 6)
95	#define WM8776_REG_ADCLVOL 0x0e
96	#define WM8776_REG_ADCRVOL 0x0f
97	#define WM8776_ADC_GAIN_MASK 0xff
98	#define WM8776_ADC_ZCEN (1 << 8)
99	#define WM8776_REG_ALCCTRL1 0x10
100	#define WM8776_ALC1_LCT_MASK 0x0f /* 0=-16dB, 1=-15dB..15=-1dB */
101	#define WM8776_ALC1_MAXGAIN_MASK 0x70 /* 0,1=0dB, 2=+4dB...7=+24dB */
102	#define WM8776_ALC1_LCSEL_MASK 0x180
103	#define WM8776_ALC1_LCSEL_LIMITER (0 << 7)
104	#define WM8776_ALC1_LCSEL_ALCR (1 << 7)
105	#define WM8776_ALC1_LCSEL_ALCL (2 << 7)
106	#define WM8776_ALC1_LCSEL_ALCSTEREO (3 << 7)
107	#define WM8776_REG_ALCCTRL2 0x11
108	#define WM8776_ALC2_HOLD_MASK 0x0f /0=0ms, 1=2.67ms, 2=5.33ms.. /
109	#define WM8776_ALC2_ZCEN (1 << 7)
110	#define WM8776_ALC2_LCEN (1 << 8)
111	#define WM8776_REG_ALCCTRL3 0x12
112	#define WM8776_ALC3_ATK_MASK 0x0f
113	#define WM8776_ALC3_DCY_MASK 0xf0
114	#define WM8776_ALC3_FDECAY (1 << 8)
115	#define WM8776_REG_NOISEGATE 0x13
116	#define WM8776_NGAT_ENABLE (1 << 0)
117	#define WM8776_NGAT_THR_MASK 0x1c /0=-78dB, 1=-72dB...7=-36dB /
118	#define WM8776_REG_LIMITER 0x14
119	#define WM8776_LIM_MAXATTEN_MASK 0x0f
120	#define WM8776_LIM_TRANWIN_MASK 0x70 /0=0us, 1=62.5us, 2=125us.. /
121	#define WM8776_REG_ADCMUX 0x15
122	#define WM8776_ADC_MUX_AIN1 (1 << 0)
123	#define WM8776_ADC_MUX_AIN2 (1 << 1)
124	#define WM8776_ADC_MUX_AIN3 (1 << 2)
125	#define WM8776_ADC_MUX_AIN4 (1 << 3)
126	#define WM8776_ADC_MUX_AIN5 (1 << 4)
127	#define WM8776_ADC_MUTER (1 << 6)
128	#define WM8776_ADC_MUTEL (1 << 7)
129	#define WM8776_ADC_LRBOTH (1 << 8)
130	#define WM8776_REG_OUTMUX 0x16
131	#define WM8776_OUTMUX_DAC (1 << 0)
132	#define WM8776_OUTMUX_AUX (1 << 1)
133	#define WM8776_OUTMUX_BYPASS (1 << 2)
134	#define WM8776_REG_RESET 0x17
135
136	#define WM8776_REG_COUNT 0x17 /* don't cache the RESET register */
137
138	struct snd_wm8776;
139
140	struct snd_wm8776_ops {
141	void (write)(struct snd_wm8776 wm, u8 addr, u8 data);
142	};
143
144	enum snd_wm8776_ctl_id {
145	WM8776_CTL_DAC_VOL,
146	WM8776_CTL_DAC_SW,
147	WM8776_CTL_DAC_ZC_SW,
148	WM8776_CTL_HP_VOL,
149	WM8776_CTL_HP_SW,
150	WM8776_CTL_HP_ZC_SW,
151	WM8776_CTL_AUX_SW,
152	WM8776_CTL_BYPASS_SW,
153	WM8776_CTL_DAC_IZD_SW,
154	WM8776_CTL_PHASE_SW,
155	WM8776_CTL_DEEMPH_SW,
156	WM8776_CTL_ADC_VOL,
157	WM8776_CTL_ADC_SW,
158	WM8776_CTL_INPUT1_SW,
159	WM8776_CTL_INPUT2_SW,
160	WM8776_CTL_INPUT3_SW,
161	WM8776_CTL_INPUT4_SW,
162	WM8776_CTL_INPUT5_SW,
163	WM8776_CTL_AGC_SEL,
164	WM8776_CTL_LIM_THR,
165	WM8776_CTL_LIM_ATK,
166	WM8776_CTL_LIM_DCY,
167	WM8776_CTL_LIM_TRANWIN,
168	WM8776_CTL_LIM_MAXATTN,
169	WM8776_CTL_ALC_TGT,
170	WM8776_CTL_ALC_ATK,
171	WM8776_CTL_ALC_DCY,
172	WM8776_CTL_ALC_MAXGAIN,
173	WM8776_CTL_ALC_MAXATTN,
174	WM8776_CTL_ALC_HLD,
175	WM8776_CTL_NGT_SW,
176	WM8776_CTL_NGT_THR,
177
178	WM8776_CTL_COUNT,
179	};
180
181	#define WM8776_ENUM_MAX 16
182
183	#define WM8776_FLAG_STEREO (1 << 0)
184	#define WM8776_FLAG_VOL_UPDATE (1 << 1)
185	#define WM8776_FLAG_INVERT (1 << 2)
186	#define WM8776_FLAG_LIM (1 << 3)
187	#define WM8776_FLAG_ALC (1 << 4)
188
189	struct snd_wm8776_ctl {
a2af050f	190	const char *name;
bfe51427 OZ	191	snd_ctl_elem_type_t type;
	192	const char *const enum_names[WM8776_ENUM_MAX];
	193	const unsigned int *tlv;
	194	u16 reg1, reg2, mask1, mask2, min, max, flags;
	195	void (set)(struct snd_wm8776 wm, u16 ch1, u16 ch2);
	196	void (get)(struct snd_wm8776 wm, u16 ch1, u16 ch2);
	197	};
	198
	199	enum snd_wm8776_agc_mode {
	200	WM8776_AGC_OFF,
	201	WM8776_AGC_LIM,
	202	WM8776_AGC_ALC_R,
	203	WM8776_AGC_ALC_L,
	204	WM8776_AGC_ALC_STEREO
	205	};
	206
	207	struct snd_wm8776 {
	208	struct snd_card *card;
	209	struct snd_wm8776_ctl ctl[WM8776_CTL_COUNT];
	210	enum snd_wm8776_agc_mode agc_mode;
	211	struct snd_wm8776_ops ops;
	212	u16 regs[WM8776_REG_COUNT]; /* 9-bit registers */
	213	};
	214
	215
	216
	217	void snd_wm8776_init(struct snd_wm8776 *wm);
	218	void snd_wm8776_resume(struct snd_wm8776 *wm);
	219	void snd_wm8776_set_dac_if(struct snd_wm8776 *wm, u16 dac);
	220	void snd_wm8776_set_adc_if(struct snd_wm8776 *wm, u16 adc);
	221	void snd_wm8776_set_master_mode(struct snd_wm8776 *wm, u16 mode);
	222	void snd_wm8776_set_power(struct snd_wm8776 *wm, u16 power);
	223	void snd_wm8776_volume_restore(struct snd_wm8776 *wm);
	224	int snd_wm8776_build_controls(struct snd_wm8776 *wm);
	225
	226	#endif /* __SOUND_WM8776_H */