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ALSA: pci: Avoid non-standard macro usage
[linux-2.6-block.git] / sound / pci / ice1712 / ice1712.c
CommitLineData
1a59d1b8 1// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4
LT		 2/*
3 * ALSA driver for ICEnsemble ICE1712 (Envy24)
4 *
c1017a4c 5 * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
3d8cb466 6 */
1da177e4
LT		 7
8/*
9 NOTES:
10 - spdif nonaudio consumer mode does not work (at least with my
11 Sony STR-DB830)
12*/
13
14/*
15 * Changes:
16 *
17 * 2002.09.09 Takashi Iwai <tiwai@suse.de>
18 * split the code to several files. each low-level routine
19 * is stored in the local file and called from registration
20 * function from card_info struct.
21 *
22 * 2002.11.26 James Stafford <jstafford@ampltd.com>
23 * Added support for VT1724 (Envy24HT)
3d8cb466 24 * I have left out support for 176.4 and 192 KHz for the moment.
1da177e4
LT		 25 * I also haven't done anything with the internal S/PDIF transmitter or the MPU-401
26 *
27 * 2003.02.20 Taksahi Iwai <tiwai@suse.de>
28 * Split vt1724 part to an independent driver.
29 * The GPIO is accessed through the callback functions now.
30 *
31 * 2004.03.31 Doug McLain <nostar@comcast.net>
32 * Added support for Event Electronics EZ8 card to hoontech.c.
33 */
34
35
1da177e4
LT		 36#include <linux/delay.h>
37#include <linux/interrupt.h>
38#include <linux/init.h>
39#include <linux/pci.h>
9d2f928d 40#include <linux/dma-mapping.h>
1da177e4 41#include <linux/slab.h>
65a77217 42#include <linux/module.h>
62932df8 43#include <linux/mutex.h>
910638ae 44
1da177e4
LT		 45#include <sound/core.h>
46#include <sound/cs8427.h>
47#include <sound/info.h>
1da177e4 48#include <sound/initval.h>
680ef792 49#include <sound/tlv.h>
1da177e4
LT		 50
51#include <sound/asoundef.h>
52
53#include "ice1712.h"
54
55/* lowlevel routines */
56#include "delta.h"
57#include "ews.h"
58#include "hoontech.h"
59
c1017a4c 60MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
1da177e4
LT		 61MODULE_DESCRIPTION("ICEnsemble ICE1712 (Envy24)");
62MODULE_LICENSE("GPL");
63MODULE_SUPPORTED_DEVICE("{"
64 HOONTECH_DEVICE_DESC
65 DELTA_DEVICE_DESC
66 EWS_DEVICE_DESC
67 "{ICEnsemble,Generic ICE1712},"
68 "{ICEnsemble,Generic Envy24}}");
69
70static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
71static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
a67ff6a5 72static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
1da177e4 73static char *model[SNDRV_CARDS];
a67ff6a5 74static bool omni[SNDRV_CARDS]; /* Delta44 & 66 Omni I/O support */
7c9d440e 75static int cs8427_timeout[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 500}; /* CS8427 S/PDIF transceiver reset timeout value in msec */
01a00e5e 76static int dxr_enable[SNDRV_CARDS]; /* DXR enable for DMX6FIRE */
1da177e4
LT		 77
78module_param_array(index, int, NULL, 0444);
79MODULE_PARM_DESC(index, "Index value for ICE1712 soundcard.");
80module_param_array(id, charp, NULL, 0444);
81MODULE_PARM_DESC(id, "ID string for ICE1712 soundcard.");
82module_param_array(enable, bool, NULL, 0444);
83MODULE_PARM_DESC(enable, "Enable ICE1712 soundcard.");
84module_param_array(omni, bool, NULL, 0444);
85MODULE_PARM_DESC(omni, "Enable Midiman M-Audio Delta Omni I/O support.");
86module_param_array(cs8427_timeout, int, NULL, 0444);
87MODULE_PARM_DESC(cs8427_timeout, "Define reset timeout for cs8427 chip in msec resolution.");
88module_param_array(model, charp, NULL, 0444);
89MODULE_PARM_DESC(model, "Use the given board model.");
531af462 90module_param_array(dxr_enable, int, NULL, 0444);
01a00e5e 91MODULE_PARM_DESC(dxr_enable, "Enable DXR support for Terratec DMX6FIRE.");
1da177e4 92
1da177e4 93
9baa3c34 94static const struct pci_device_id snd_ice1712_ids[] = {
28d27aae 95 { PCI_VDEVICE(ICE, PCI_DEVICE_ID_ICE_1712), 0 }, /* ICE1712 */
1da177e4
LT		 96 { 0, }
97};
98
99MODULE_DEVICE_TABLE(pci, snd_ice1712_ids);
100
6ca308d4
TI		 101static int snd_ice1712_build_pro_mixer(struct snd_ice1712 *ice);
102static int snd_ice1712_build_controls(struct snd_ice1712 *ice);
1da177e4
LT		 103
104static int PRO_RATE_LOCKED;
105static int PRO_RATE_RESET = 1;
106static unsigned int PRO_RATE_DEFAULT = 44100;
107
108/*
109 * Basic I/O
110 */
3d8cb466 111
1da177e4 112/* check whether the clock mode is spdif-in */
6ca308d4 113static inline int is_spdif_master(struct snd_ice1712 *ice)
1da177e4
LT		 114{
115 return (inb(ICEMT(ice, RATE)) & ICE1712_SPDIF_MASTER) ? 1 : 0;
116}
117
6ca308d4 118static inline int is_pro_rate_locked(struct snd_ice1712 *ice)
1da177e4
LT		 119{
120 return is_spdif_master(ice) || PRO_RATE_LOCKED;
121}
122
3d8cb466 123static inline void snd_ice1712_ds_write(struct snd_ice1712 *ice, u8 channel, u8 addr, u32 data)
1da177e4
LT		 124{
125 outb((channel << 4) | addr, ICEDS(ice, INDEX));
126 outl(data, ICEDS(ice, DATA));
127}
128
3d8cb466 129static inline u32 snd_ice1712_ds_read(struct snd_ice1712 *ice, u8 channel, u8 addr)
1da177e4
LT		 130{
131 outb((channel << 4) | addr, ICEDS(ice, INDEX));
132 return inl(ICEDS(ice, DATA));
133}
134
6ca308d4 135static void snd_ice1712_ac97_write(struct snd_ac97 *ac97,
1da177e4
LT		 136 unsigned short reg,
137 unsigned short val)
138{
6ca308d4 139 struct snd_ice1712 *ice = ac97->private_data;
1da177e4
LT		 140 int tm;
141 unsigned char old_cmd = 0;
142
143 for (tm = 0; tm < 0x10000; tm++) {
144 old_cmd = inb(ICEREG(ice, AC97_CMD));
145 if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
146 continue;
147 if (!(old_cmd & ICE1712_AC97_READY))
148 continue;
149 break;
150 }
151 outb(reg, ICEREG(ice, AC97_INDEX));
152 outw(val, ICEREG(ice, AC97_DATA));
153 old_cmd &= ~(ICE1712_AC97_PBK_VSR | ICE1712_AC97_CAP_VSR);
154 outb(old_cmd | ICE1712_AC97_WRITE, ICEREG(ice, AC97_CMD));
155 for (tm = 0; tm < 0x10000; tm++)
156 if ((inb(ICEREG(ice, AC97_CMD)) & ICE1712_AC97_WRITE) == 0)
157 break;
158}
159
6ca308d4 160static unsigned short snd_ice1712_ac97_read(struct snd_ac97 *ac97,
1da177e4
LT		 161 unsigned short reg)
162{
6ca308d4 163 struct snd_ice1712 *ice = ac97->private_data;
1da177e4
LT		 164 int tm;
165 unsigned char old_cmd = 0;
166
167 for (tm = 0; tm < 0x10000; tm++) {
168 old_cmd = inb(ICEREG(ice, AC97_CMD));
169 if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
170 continue;
171 if (!(old_cmd & ICE1712_AC97_READY))
172 continue;
173 break;
174 }
175 outb(reg, ICEREG(ice, AC97_INDEX));
176 outb(old_cmd | ICE1712_AC97_READ, ICEREG(ice, AC97_CMD));
177 for (tm = 0; tm < 0x10000; tm++)
178 if ((inb(ICEREG(ice, AC97_CMD)) & ICE1712_AC97_READ) == 0)
179 break;
180 if (tm >= 0x10000) /* timeout */
181 return ~0;
182 return inw(ICEREG(ice, AC97_DATA));
183}
184
185/*
186 * pro ac97 section
187 */
188
6ca308d4 189static void snd_ice1712_pro_ac97_write(struct snd_ac97 *ac97,
1da177e4
LT		 190 unsigned short reg,
191 unsigned short val)
192{
6ca308d4 193 struct snd_ice1712 *ice = ac97->private_data;
1da177e4
LT		 194 int tm;
195 unsigned char old_cmd = 0;
196
197 for (tm = 0; tm < 0x10000; tm++) {
198 old_cmd = inb(ICEMT(ice, AC97_CMD));
199 if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
200 continue;
201 if (!(old_cmd & ICE1712_AC97_READY))
202 continue;
203 break;
204 }
205 outb(reg, ICEMT(ice, AC97_INDEX));
206 outw(val, ICEMT(ice, AC97_DATA));
207 old_cmd &= ~(ICE1712_AC97_PBK_VSR | ICE1712_AC97_CAP_VSR);
208 outb(old_cmd | ICE1712_AC97_WRITE, ICEMT(ice, AC97_CMD));
209 for (tm = 0; tm < 0x10000; tm++)
210 if ((inb(ICEMT(ice, AC97_CMD)) & ICE1712_AC97_WRITE) == 0)
211 break;
212}
213
214
6ca308d4 215static unsigned short snd_ice1712_pro_ac97_read(struct snd_ac97 *ac97,
1da177e4
LT		 216 unsigned short reg)
217{
6ca308d4 218 struct snd_ice1712 *ice = ac97->private_data;
1da177e4
LT		 219 int tm;
220 unsigned char old_cmd = 0;
221
222 for (tm = 0; tm < 0x10000; tm++) {
223 old_cmd = inb(ICEMT(ice, AC97_CMD));
224 if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
225 continue;
226 if (!(old_cmd & ICE1712_AC97_READY))
227 continue;
228 break;
229 }
230 outb(reg, ICEMT(ice, AC97_INDEX));
231 outb(old_cmd | ICE1712_AC97_READ, ICEMT(ice, AC97_CMD));
232 for (tm = 0; tm < 0x10000; tm++)
233 if ((inb(ICEMT(ice, AC97_CMD)) & ICE1712_AC97_READ) == 0)
234 break;
235 if (tm >= 0x10000) /* timeout */
236 return ~0;
237 return inw(ICEMT(ice, AC97_DATA));
238}
239
240/*
241 * consumer ac97 digital mix
242 */
a5ce8890 243#define snd_ice1712_digmix_route_ac97_info snd_ctl_boolean_mono_info
1da177e4 244
6ca308d4 245static int snd_ice1712_digmix_route_ac97_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 246{
6ca308d4 247 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
3d8cb466 248
1da177e4
LT		 249 ucontrol->value.integer.value[0] = inb(ICEMT(ice, MONITOR_ROUTECTRL)) & ICE1712_ROUTE_AC97 ? 1 : 0;
250 return 0;
251}
252
6ca308d4 253static int snd_ice1712_digmix_route_ac97_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 254{
6ca308d4 255 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4 256 unsigned char val, nval;
3d8cb466 257
1da177e4
LT		 258 spin_lock_irq(&ice->reg_lock);
259 val = inb(ICEMT(ice, MONITOR_ROUTECTRL));
260 nval = val & ~ICE1712_ROUTE_AC97;
3d8cb466
AB		 261 if (ucontrol->value.integer.value[0])
262 nval |= ICE1712_ROUTE_AC97;
1da177e4
LT		 263 outb(nval, ICEMT(ice, MONITOR_ROUTECTRL));
264 spin_unlock_irq(&ice->reg_lock);
265 return val != nval;
266}
267
f3b827e0 268static const struct snd_kcontrol_new snd_ice1712_mixer_digmix_route_ac97 = {
1da177e4
LT		 269 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
270 .name = "Digital Mixer To AC97",
271 .info = snd_ice1712_digmix_route_ac97_info,
272 .get = snd_ice1712_digmix_route_ac97_get,
273 .put = snd_ice1712_digmix_route_ac97_put,
274};
275
276
277/*
278 * gpio operations
279 */
6ca308d4 280static void snd_ice1712_set_gpio_dir(struct snd_ice1712 *ice, unsigned int data)
1da177e4
LT		 281{
282 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION, data);
283 inb(ICEREG(ice, DATA)); /* dummy read for pci-posting */
284}
285
49470306
PH		 286static unsigned int snd_ice1712_get_gpio_dir(struct snd_ice1712 *ice)
287{
288 return snd_ice1712_read(ice, ICE1712_IREG_GPIO_DIRECTION);
289}
290
291static unsigned int snd_ice1712_get_gpio_mask(struct snd_ice1712 *ice)
292{
293 return snd_ice1712_read(ice, ICE1712_IREG_GPIO_WRITE_MASK);
294}
295
6ca308d4 296static void snd_ice1712_set_gpio_mask(struct snd_ice1712 *ice, unsigned int data)
1da177e4
LT		 297{
298 snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK, data);
299 inb(ICEREG(ice, DATA)); /* dummy read for pci-posting */
300}
301
6ca308d4 302static unsigned int snd_ice1712_get_gpio_data(struct snd_ice1712 *ice)
1da177e4
LT		 303{
304 return snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA);
305}
306
6ca308d4 307static void snd_ice1712_set_gpio_data(struct snd_ice1712 *ice, unsigned int val)
1da177e4
LT		 308{
309 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, val);
310 inb(ICEREG(ice, DATA)); /* dummy read for pci-posting */
311}
312
1da177e4
LT		 313/*
314 *
315 * CS8427 interface
316 *
317 */
318
319/*
320 * change the input clock selection
321 * spdif_clock = 1 - IEC958 input, 0 - Envy24
322 */
6ca308d4 323static int snd_ice1712_cs8427_set_input_clock(struct snd_ice1712 *ice, int spdif_clock)
1da177e4
LT		 324{
325 unsigned char reg[2] = { 0x80 | 4, 0 }; /* CS8427 auto increment | register number 4 + data */
326 unsigned char val, nval;
327 int res = 0;
3d8cb466 328
1da177e4
LT		 329 snd_i2c_lock(ice->i2c);
330 if (snd_i2c_sendbytes(ice->cs8427, reg, 1) != 1) {
331 snd_i2c_unlock(ice->i2c);
332 return -EIO;
333 }
334 if (snd_i2c_readbytes(ice->cs8427, &val, 1) != 1) {
335 snd_i2c_unlock(ice->i2c);
336 return -EIO;
337 }
338 nval = val & 0xf0;
339 if (spdif_clock)
340 nval |= 0x01;
341 else
342 nval |= 0x04;
343 if (val != nval) {
344 reg[1] = nval;
345 if (snd_i2c_sendbytes(ice->cs8427, reg, 2) != 2) {
346 res = -EIO;
347 } else {
348 res++;
349 }
350 }
351 snd_i2c_unlock(ice->i2c);
352 return res;
353}
354
355/*
356 * spdif callbacks
357 */
6ca308d4 358static void open_cs8427(struct snd_ice1712 *ice, struct snd_pcm_substream *substream)
1da177e4
LT		 359{
360 snd_cs8427_iec958_active(ice->cs8427, 1);
361}
362
6ca308d4 363static void close_cs8427(struct snd_ice1712 *ice, struct snd_pcm_substream *substream)
1da177e4
LT		 364{
365 snd_cs8427_iec958_active(ice->cs8427, 0);
366}
367
6ca308d4 368static void setup_cs8427(struct snd_ice1712 *ice, int rate)
1da177e4
LT		 369{
370 snd_cs8427_iec958_pcm(ice->cs8427, rate);
371}
372
373/*
374 * create and initialize callbacks for cs8427 interface
375 */
e23e7a14 376int snd_ice1712_init_cs8427(struct snd_ice1712 *ice, int addr)
1da177e4
LT		 377{
378 int err;
379
3d8cb466
AB		 380 err = snd_cs8427_create(ice->i2c, addr,
381 (ice->cs8427_timeout * HZ) / 1000, &ice->cs8427);
382 if (err < 0) {
6dfb5aff 383 dev_err(ice->card->dev, "CS8427 initialization failed\n");
1da177e4
LT		 384 return err;
385 }
386 ice->spdif.ops.open = open_cs8427;
387 ice->spdif.ops.close = close_cs8427;
388 ice->spdif.ops.setup_rate = setup_cs8427;
389 return 0;
390}
391
e957ebf1
JK		 392static void snd_ice1712_set_input_clock_source(struct snd_ice1712 *ice, int spdif_is_master)
393{
3d8cb466
AB		 394 /* change CS8427 clock source too */
395 if (ice->cs8427)
396 snd_ice1712_cs8427_set_input_clock(ice, spdif_is_master);
e957ebf1
JK		 397 /* notify ak4524 chip as well */
398 if (spdif_is_master) {
399 unsigned int i;
400 for (i = 0; i < ice->akm_codecs; i++) {
401 if (ice->akm[i].ops.set_rate_val)
402 ice->akm[i].ops.set_rate_val(&ice->akm[i], 0);
403 }
404 }
405}
1da177e4
LT		 406
407/*
408 * Interrupt handler
409 */
410
7d12e780 411static irqreturn_t snd_ice1712_interrupt(int irq, void *dev_id)
1da177e4 412{
6ca308d4 413 struct snd_ice1712 *ice = dev_id;
1da177e4
LT		 414 unsigned char status;
415 int handled = 0;
416
417 while (1) {
418 status = inb(ICEREG(ice, IRQSTAT));
419 if (status == 0)
420 break;
421 handled = 1;
422 if (status & ICE1712_IRQ_MPU1) {
423 if (ice->rmidi[0])
7d12e780 424 snd_mpu401_uart_interrupt(irq, ice->rmidi[0]->private_data);
1da177e4
LT		 425 outb(ICE1712_IRQ_MPU1, ICEREG(ice, IRQSTAT));
426 status &= ~ICE1712_IRQ_MPU1;
427 }
428 if (status & ICE1712_IRQ_TIMER)
429 outb(ICE1712_IRQ_TIMER, ICEREG(ice, IRQSTAT));
430 if (status & ICE1712_IRQ_MPU2) {
431 if (ice->rmidi[1])
7d12e780 432 snd_mpu401_uart_interrupt(irq, ice->rmidi[1]->private_data);
1da177e4
LT		 433 outb(ICE1712_IRQ_MPU2, ICEREG(ice, IRQSTAT));
434 status &= ~ICE1712_IRQ_MPU2;
435 }
436 if (status & ICE1712_IRQ_PROPCM) {
437 unsigned char mtstat = inb(ICEMT(ice, IRQ));
438 if (mtstat & ICE1712_MULTI_PBKSTATUS) {
439 if (ice->playback_pro_substream)
440 snd_pcm_period_elapsed(ice->playback_pro_substream);
441 outb(ICE1712_MULTI_PBKSTATUS, ICEMT(ice, IRQ));
442 }
443 if (mtstat & ICE1712_MULTI_CAPSTATUS) {
444 if (ice->capture_pro_substream)
445 snd_pcm_period_elapsed(ice->capture_pro_substream);
446 outb(ICE1712_MULTI_CAPSTATUS, ICEMT(ice, IRQ));
447 }
448 }
449 if (status & ICE1712_IRQ_FM)
450 outb(ICE1712_IRQ_FM, ICEREG(ice, IRQSTAT));
451 if (status & ICE1712_IRQ_PBKDS) {
452 u32 idx;
453 u16 pbkstatus;
6ca308d4 454 struct snd_pcm_substream *substream;
1da177e4 455 pbkstatus = inw(ICEDS(ice, INTSTAT));
6dfb5aff 456 /* dev_dbg(ice->card->dev, "pbkstatus = 0x%x\n", pbkstatus); */
1da177e4
LT		 457 for (idx = 0; idx < 6; idx++) {
458 if ((pbkstatus & (3 << (idx * 2))) == 0)
459 continue;
3d8cb466
AB		 460 substream = ice->playback_con_substream_ds[idx];
461 if (substream != NULL)
1da177e4
LT		 462 snd_pcm_period_elapsed(substream);
463 outw(3 << (idx * 2), ICEDS(ice, INTSTAT));
464 }
465 outb(ICE1712_IRQ_PBKDS, ICEREG(ice, IRQSTAT));
466 }
467 if (status & ICE1712_IRQ_CONCAP) {
468 if (ice->capture_con_substream)
469 snd_pcm_period_elapsed(ice->capture_con_substream);
470 outb(ICE1712_IRQ_CONCAP, ICEREG(ice, IRQSTAT));
471 }
472 if (status & ICE1712_IRQ_CONPBK) {
473 if (ice->playback_con_substream)
474 snd_pcm_period_elapsed(ice->playback_con_substream);
475 outb(ICE1712_IRQ_CONPBK, ICEREG(ice, IRQSTAT));
476 }
477 }
478 return IRQ_RETVAL(handled);
479}
480
481
482/*
483 * PCM part - misc
484 */
485
6ca308d4
TI		 486static int snd_ice1712_hw_params(struct snd_pcm_substream *substream,
487 struct snd_pcm_hw_params *hw_params)
1da177e4
LT		 488{
489 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
490}
491
6ca308d4 492static int snd_ice1712_hw_free(struct snd_pcm_substream *substream)
1da177e4
LT		 493{
494 return snd_pcm_lib_free_pages(substream);
495}
496
497/*
498 * PCM part - consumer I/O
499 */
500
6ca308d4 501static int snd_ice1712_playback_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 502 int cmd)
503{
6ca308d4 504 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 505 int result = 0;
506 u32 tmp;
3d8cb466 507
1da177e4
LT		 508 spin_lock(&ice->reg_lock);
509 tmp = snd_ice1712_read(ice, ICE1712_IREG_PBK_CTRL);
510 if (cmd == SNDRV_PCM_TRIGGER_START) {
511 tmp |= 1;
512 } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
513 tmp &= ~1;
514 } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) {
515 tmp |= 2;
516 } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE) {
517 tmp &= ~2;
518 } else {
519 result = -EINVAL;
520 }
521 snd_ice1712_write(ice, ICE1712_IREG_PBK_CTRL, tmp);
522 spin_unlock(&ice->reg_lock);
523 return result;
524}
525
6ca308d4 526static int snd_ice1712_playback_ds_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 527 int cmd)
528{
6ca308d4 529 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 530 int result = 0;
531 u32 tmp;
3d8cb466 532
1da177e4
LT		 533 spin_lock(&ice->reg_lock);
534 tmp = snd_ice1712_ds_read(ice, substream->number * 2, ICE1712_DSC_CONTROL);
535 if (cmd == SNDRV_PCM_TRIGGER_START) {
536 tmp |= 1;
537 } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
538 tmp &= ~1;
539 } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) {
540 tmp |= 2;
541 } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE) {
542 tmp &= ~2;
543 } else {
544 result = -EINVAL;
545 }
546 snd_ice1712_ds_write(ice, substream->number * 2, ICE1712_DSC_CONTROL, tmp);
547 spin_unlock(&ice->reg_lock);
548 return result;
549}
550
6ca308d4 551static int snd_ice1712_capture_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 552 int cmd)
553{
6ca308d4 554 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 555 int result = 0;
556 u8 tmp;
3d8cb466 557
1da177e4
LT		 558 spin_lock(&ice->reg_lock);
559 tmp = snd_ice1712_read(ice, ICE1712_IREG_CAP_CTRL);
560 if (cmd == SNDRV_PCM_TRIGGER_START) {
561 tmp |= 1;
562 } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
563 tmp &= ~1;
564 } else {
565 result = -EINVAL;
566 }
567 snd_ice1712_write(ice, ICE1712_IREG_CAP_CTRL, tmp);
568 spin_unlock(&ice->reg_lock);
569 return result;
570}
571
6ca308d4 572static int snd_ice1712_playback_prepare(struct snd_pcm_substream *substream)
1da177e4 573{
6ca308d4
TI		 574 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
575 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 576 u32 period_size, buf_size, rate, tmp;
577
578 period_size = (snd_pcm_lib_period_bytes(substream) >> 2) - 1;
579 buf_size = snd_pcm_lib_buffer_bytes(substream) - 1;
580 tmp = 0x0000;
581 if (snd_pcm_format_width(runtime->format) == 16)
582 tmp |= 0x10;
583 if (runtime->channels == 2)
584 tmp |= 0x08;
585 rate = (runtime->rate * 8192) / 375;
586 if (rate > 0x000fffff)
587 rate = 0x000fffff;
588 spin_lock_irq(&ice->reg_lock);
589 outb(0, ice->ddma_port + 15);
590 outb(ICE1712_DMA_MODE_WRITE | ICE1712_DMA_AUTOINIT, ice->ddma_port + 0x0b);
591 outl(runtime->dma_addr, ice->ddma_port + 0);
592 outw(buf_size, ice->ddma_port + 4);
593 snd_ice1712_write(ice, ICE1712_IREG_PBK_RATE_LO, rate & 0xff);
594 snd_ice1712_write(ice, ICE1712_IREG_PBK_RATE_MID, (rate >> 8) & 0xff);
595 snd_ice1712_write(ice, ICE1712_IREG_PBK_RATE_HI, (rate >> 16) & 0xff);
596 snd_ice1712_write(ice, ICE1712_IREG_PBK_CTRL, tmp);
597 snd_ice1712_write(ice, ICE1712_IREG_PBK_COUNT_LO, period_size & 0xff);
598 snd_ice1712_write(ice, ICE1712_IREG_PBK_COUNT_HI, period_size >> 8);
599 snd_ice1712_write(ice, ICE1712_IREG_PBK_LEFT, 0);
600 snd_ice1712_write(ice, ICE1712_IREG_PBK_RIGHT, 0);
601 spin_unlock_irq(&ice->reg_lock);
602 return 0;
603}
604
6ca308d4 605static int snd_ice1712_playback_ds_prepare(struct snd_pcm_substream *substream)
1da177e4 606{
6ca308d4
TI		 607 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
608 struct snd_pcm_runtime *runtime = substream->runtime;
b393df01 609 u32 period_size, rate, tmp, chn;
1da177e4
LT		 610
611 period_size = snd_pcm_lib_period_bytes(substream) - 1;
1da177e4
LT		 612 tmp = 0x0064;
613 if (snd_pcm_format_width(runtime->format) == 16)
614 tmp &= ~0x04;
615 if (runtime->channels == 2)
616 tmp |= 0x08;
617 rate = (runtime->rate * 8192) / 375;
618 if (rate > 0x000fffff)
619 rate = 0x000fffff;
620 ice->playback_con_active_buf[substream->number] = 0;
621 ice->playback_con_virt_addr[substream->number] = runtime->dma_addr;
622 chn = substream->number * 2;
623 spin_lock_irq(&ice->reg_lock);
624 snd_ice1712_ds_write(ice, chn, ICE1712_DSC_ADDR0, runtime->dma_addr);
625 snd_ice1712_ds_write(ice, chn, ICE1712_DSC_COUNT0, period_size);
626 snd_ice1712_ds_write(ice, chn, ICE1712_DSC_ADDR1, runtime->dma_addr + (runtime->periods > 1 ? period_size + 1 : 0));
627 snd_ice1712_ds_write(ice, chn, ICE1712_DSC_COUNT1, period_size);
628 snd_ice1712_ds_write(ice, chn, ICE1712_DSC_RATE, rate);
629 snd_ice1712_ds_write(ice, chn, ICE1712_DSC_VOLUME, 0);
630 snd_ice1712_ds_write(ice, chn, ICE1712_DSC_CONTROL, tmp);
631 if (runtime->channels == 2) {
632 snd_ice1712_ds_write(ice, chn + 1, ICE1712_DSC_RATE, rate);
633 snd_ice1712_ds_write(ice, chn + 1, ICE1712_DSC_VOLUME, 0);
634 }
635 spin_unlock_irq(&ice->reg_lock);
636 return 0;
637}
638
6ca308d4 639static int snd_ice1712_capture_prepare(struct snd_pcm_substream *substream)
1da177e4 640{
6ca308d4
TI		 641 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
642 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 643 u32 period_size, buf_size;
644 u8 tmp;
645
646 period_size = (snd_pcm_lib_period_bytes(substream) >> 2) - 1;
647 buf_size = snd_pcm_lib_buffer_bytes(substream) - 1;
648 tmp = 0x06;
649 if (snd_pcm_format_width(runtime->format) == 16)
650 tmp &= ~0x04;
651 if (runtime->channels == 2)
652 tmp &= ~0x02;
653 spin_lock_irq(&ice->reg_lock);
654 outl(ice->capture_con_virt_addr = runtime->dma_addr, ICEREG(ice, CONCAP_ADDR));
655 outw(buf_size, ICEREG(ice, CONCAP_COUNT));
656 snd_ice1712_write(ice, ICE1712_IREG_CAP_COUNT_HI, period_size >> 8);
657 snd_ice1712_write(ice, ICE1712_IREG_CAP_COUNT_LO, period_size & 0xff);
658 snd_ice1712_write(ice, ICE1712_IREG_CAP_CTRL, tmp);
659 spin_unlock_irq(&ice->reg_lock);
660 snd_ac97_set_rate(ice->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate);
661 return 0;
662}
663
6ca308d4 664static snd_pcm_uframes_t snd_ice1712_playback_pointer(struct snd_pcm_substream *substream)
1da177e4 665{
6ca308d4
TI		 666 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
667 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 668 size_t ptr;
669
670 if (!(snd_ice1712_read(ice, ICE1712_IREG_PBK_CTRL) & 1))
671 return 0;
672 ptr = runtime->buffer_size - inw(ice->ddma_port + 4);
4f8e9400 673 ptr = bytes_to_frames(substream->runtime, ptr);
1da177e4
LT		 674 if (ptr == runtime->buffer_size)
675 ptr = 0;
4f8e9400 676 return ptr;
1da177e4
LT		 677}
678
6ca308d4 679static snd_pcm_uframes_t snd_ice1712_playback_ds_pointer(struct snd_pcm_substream *substream)
1da177e4 680{
6ca308d4 681 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 682 u8 addr;
683 size_t ptr;
684
685 if (!(snd_ice1712_ds_read(ice, substream->number * 2, ICE1712_DSC_CONTROL) & 1))
686 return 0;
687 if (ice->playback_con_active_buf[substream->number])
688 addr = ICE1712_DSC_ADDR1;
689 else
690 addr = ICE1712_DSC_ADDR0;
691 ptr = snd_ice1712_ds_read(ice, substream->number * 2, addr) -
692 ice->playback_con_virt_addr[substream->number];
4f8e9400 693 ptr = bytes_to_frames(substream->runtime, ptr);
1da177e4
LT		 694 if (ptr == substream->runtime->buffer_size)
695 ptr = 0;
4f8e9400 696 return ptr;
1da177e4
LT		 697}
698
6ca308d4 699static snd_pcm_uframes_t snd_ice1712_capture_pointer(struct snd_pcm_substream *substream)
1da177e4 700{
6ca308d4 701 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 702 size_t ptr;
703
704 if (!(snd_ice1712_read(ice, ICE1712_IREG_CAP_CTRL) & 1))
705 return 0;
706 ptr = inl(ICEREG(ice, CONCAP_ADDR)) - ice->capture_con_virt_addr;
4f8e9400 707 ptr = bytes_to_frames(substream->runtime, ptr);
1da177e4
LT		 708 if (ptr == substream->runtime->buffer_size)
709 ptr = 0;
4f8e9400 710 return ptr;
1da177e4
LT		 711}
712
3d8cb466 713static const struct snd_pcm_hardware snd_ice1712_playback = {
1da177e4
LT		 714 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
715 SNDRV_PCM_INFO_BLOCK_TRANSFER |
716 SNDRV_PCM_INFO_MMAP_VALID |
717 SNDRV_PCM_INFO_PAUSE),
718 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
719 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
720 .rate_min = 4000,
721 .rate_max = 48000,
722 .channels_min = 1,
723 .channels_max = 2,
724 .buffer_bytes_max = (64*1024),
725 .period_bytes_min = 64,
726 .period_bytes_max = (64*1024),
727 .periods_min = 1,
728 .periods_max = 1024,
729 .fifo_size = 0,
730};
731
3d8cb466 732static const struct snd_pcm_hardware snd_ice1712_playback_ds = {
1da177e4
LT		 733 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
734 SNDRV_PCM_INFO_BLOCK_TRANSFER |
735 SNDRV_PCM_INFO_MMAP_VALID |
736 SNDRV_PCM_INFO_PAUSE),
737 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
738 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
739 .rate_min = 4000,
740 .rate_max = 48000,
741 .channels_min = 1,
742 .channels_max = 2,
743 .buffer_bytes_max = (128*1024),
744 .period_bytes_min = 64,
745 .period_bytes_max = (128*1024),
746 .periods_min = 2,
747 .periods_max = 2,
748 .fifo_size = 0,
749};
750
3d8cb466 751static const struct snd_pcm_hardware snd_ice1712_capture = {
1da177e4
LT		 752 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
753 SNDRV_PCM_INFO_BLOCK_TRANSFER |
754 SNDRV_PCM_INFO_MMAP_VALID),
755 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
756 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
757 .rate_min = 4000,
758 .rate_max = 48000,
759 .channels_min = 1,
760 .channels_max = 2,
761 .buffer_bytes_max = (64*1024),
762 .period_bytes_min = 64,
763 .period_bytes_max = (64*1024),
764 .periods_min = 1,
765 .periods_max = 1024,
766 .fifo_size = 0,
767};
768
6ca308d4 769static int snd_ice1712_playback_open(struct snd_pcm_substream *substream)
1da177e4 770{
6ca308d4
TI		 771 struct snd_pcm_runtime *runtime = substream->runtime;
772 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 773
774 ice->playback_con_substream = substream;
775 runtime->hw = snd_ice1712_playback;
776 return 0;
777}
778
6ca308d4 779static int snd_ice1712_playback_ds_open(struct snd_pcm_substream *substream)
1da177e4 780{
6ca308d4
TI		 781 struct snd_pcm_runtime *runtime = substream->runtime;
782 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 783 u32 tmp;
784
785 ice->playback_con_substream_ds[substream->number] = substream;
786 runtime->hw = snd_ice1712_playback_ds;
3d8cb466 787 spin_lock_irq(&ice->reg_lock);
1da177e4
LT		 788 tmp = inw(ICEDS(ice, INTMASK)) & ~(1 << (substream->number * 2));
789 outw(tmp, ICEDS(ice, INTMASK));
790 spin_unlock_irq(&ice->reg_lock);
791 return 0;
792}
793
6ca308d4 794static int snd_ice1712_capture_open(struct snd_pcm_substream *substream)
1da177e4 795{
6ca308d4
TI		 796 struct snd_pcm_runtime *runtime = substream->runtime;
797 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 798
799 ice->capture_con_substream = substream;
800 runtime->hw = snd_ice1712_capture;
801 runtime->hw.rates = ice->ac97->rates[AC97_RATES_ADC];
802 if (!(runtime->hw.rates & SNDRV_PCM_RATE_8000))
803 runtime->hw.rate_min = 48000;
804 return 0;
805}
806
6ca308d4 807static int snd_ice1712_playback_close(struct snd_pcm_substream *substream)
1da177e4 808{
6ca308d4 809 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 810
811 ice->playback_con_substream = NULL;
812 return 0;
813}
814
6ca308d4 815static int snd_ice1712_playback_ds_close(struct snd_pcm_substream *substream)
1da177e4 816{
6ca308d4 817 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 818 u32 tmp;
819
3d8cb466 820 spin_lock_irq(&ice->reg_lock);
1da177e4
LT		 821 tmp = inw(ICEDS(ice, INTMASK)) | (3 << (substream->number * 2));
822 outw(tmp, ICEDS(ice, INTMASK));
823 spin_unlock_irq(&ice->reg_lock);
824 ice->playback_con_substream_ds[substream->number] = NULL;
825 return 0;
826}
827
6ca308d4 828static int snd_ice1712_capture_close(struct snd_pcm_substream *substream)
1da177e4 829{
6ca308d4 830 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 831
832 ice->capture_con_substream = NULL;
833 return 0;
834}
835
6769e988 836static const struct snd_pcm_ops snd_ice1712_playback_ops = {
1da177e4
LT		 837 .open = snd_ice1712_playback_open,
838 .close = snd_ice1712_playback_close,
839 .ioctl = snd_pcm_lib_ioctl,
840 .hw_params = snd_ice1712_hw_params,
841 .hw_free = snd_ice1712_hw_free,
842 .prepare = snd_ice1712_playback_prepare,
843 .trigger = snd_ice1712_playback_trigger,
844 .pointer = snd_ice1712_playback_pointer,
845};
846
6769e988 847static const struct snd_pcm_ops snd_ice1712_playback_ds_ops = {
1da177e4
LT		 848 .open = snd_ice1712_playback_ds_open,
849 .close = snd_ice1712_playback_ds_close,
850 .ioctl = snd_pcm_lib_ioctl,
851 .hw_params = snd_ice1712_hw_params,
852 .hw_free = snd_ice1712_hw_free,
853 .prepare = snd_ice1712_playback_ds_prepare,
854 .trigger = snd_ice1712_playback_ds_trigger,
855 .pointer = snd_ice1712_playback_ds_pointer,
856};
857
6769e988 858static const struct snd_pcm_ops snd_ice1712_capture_ops = {
1da177e4
LT		 859 .open = snd_ice1712_capture_open,
860 .close = snd_ice1712_capture_close,
861 .ioctl = snd_pcm_lib_ioctl,
862 .hw_params = snd_ice1712_hw_params,
863 .hw_free = snd_ice1712_hw_free,
864 .prepare = snd_ice1712_capture_prepare,
865 .trigger = snd_ice1712_capture_trigger,
866 .pointer = snd_ice1712_capture_pointer,
867};
868
08a4c10b 869static int snd_ice1712_pcm(struct snd_ice1712 *ice, int device)
1da177e4 870{
6ca308d4 871 struct snd_pcm *pcm;
1da177e4
LT		 872 int err;
873
1da177e4
LT		 874 err = snd_pcm_new(ice->card, "ICE1712 consumer", device, 1, 1, &pcm);
875 if (err < 0)
876 return err;
877
878 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ice1712_playback_ops);
879 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ice1712_capture_ops);
880
881 pcm->private_data = ice;
1da177e4
LT		 882 pcm->info_flags = 0;
883 strcpy(pcm->name, "ICE1712 consumer");
884 ice->pcm = pcm;
885
886 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
6974f8ad
TI		 887 &ice->pci->dev,
888 64*1024, 64*1024);
1da177e4 889
6dfb5aff
TI		 890 dev_warn(ice->card->dev,
891 "Consumer PCM code does not work well at the moment --jk\n");
1da177e4
LT		 892
893 return 0;
894}
895
08a4c10b 896static int snd_ice1712_pcm_ds(struct snd_ice1712 *ice, int device)
1da177e4 897{
6ca308d4 898 struct snd_pcm *pcm;
1da177e4
LT		 899 int err;
900
1da177e4
LT		 901 err = snd_pcm_new(ice->card, "ICE1712 consumer (DS)", device, 6, 0, &pcm);
902 if (err < 0)
903 return err;
904
905 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ice1712_playback_ds_ops);
906
907 pcm->private_data = ice;
1da177e4
LT		 908 pcm->info_flags = 0;
909 strcpy(pcm->name, "ICE1712 consumer (DS)");
910 ice->pcm_ds = pcm;
911
912 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
6974f8ad
TI		 913 &ice->pci->dev,
914 64*1024, 128*1024);
1da177e4 915
1da177e4
LT		 916 return 0;
917}
918
919/*
920 * PCM code - professional part (multitrack)
921 */
922
5cf30ddf 923static const unsigned int rates[] = { 8000, 9600, 11025, 12000, 16000, 22050, 24000,
1da177e4
LT		 924 32000, 44100, 48000, 64000, 88200, 96000 };
925
5cf30ddf 926static const struct snd_pcm_hw_constraint_list hw_constraints_rates = {
1da177e4
LT		 927 .count = ARRAY_SIZE(rates),
928 .list = rates,
929 .mask = 0,
930};
931
6ca308d4 932static int snd_ice1712_pro_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 933 int cmd)
934{
6ca308d4 935 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 936 switch (cmd) {
937 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
938 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
939 {
940 unsigned int what;
941 unsigned int old;
942 if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
943 return -EINVAL;
944 what = ICE1712_PLAYBACK_PAUSE;
945 snd_pcm_trigger_done(substream, substream);
946 spin_lock(&ice->reg_lock);
947 old = inl(ICEMT(ice, PLAYBACK_CONTROL));
948 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
949 old |= what;
950 else
951 old &= ~what;
952 outl(old, ICEMT(ice, PLAYBACK_CONTROL));
953 spin_unlock(&ice->reg_lock);
954 break;
955 }
956 case SNDRV_PCM_TRIGGER_START:
957 case SNDRV_PCM_TRIGGER_STOP:
958 {
959 unsigned int what = 0;
960 unsigned int old;
6ca308d4 961 struct snd_pcm_substream *s;
1da177e4 962
ef991b95 963 snd_pcm_group_for_each_entry(s, substream) {
1da177e4
LT		 964 if (s == ice->playback_pro_substream) {
965 what |= ICE1712_PLAYBACK_START;
966 snd_pcm_trigger_done(s, substream);
967 } else if (s == ice->capture_pro_substream) {
968 what |= ICE1712_CAPTURE_START_SHADOW;
969 snd_pcm_trigger_done(s, substream);
970 }
971 }
972 spin_lock(&ice->reg_lock);
973 old = inl(ICEMT(ice, PLAYBACK_CONTROL));
974 if (cmd == SNDRV_PCM_TRIGGER_START)
975 old |= what;
976 else
977 old &= ~what;
978 outl(old, ICEMT(ice, PLAYBACK_CONTROL));
979 spin_unlock(&ice->reg_lock);
980 break;
981 }
982 default:
983 return -EINVAL;
984 }
985 return 0;
986}
987
988/*
989 */
6ca308d4 990static void snd_ice1712_set_pro_rate(struct snd_ice1712 *ice, unsigned int rate, int force)
1da177e4
LT		 991{
992 unsigned long flags;
993 unsigned char val, old;
994 unsigned int i;
995
996 switch (rate) {
997 case 8000: val = 6; break;
998 case 9600: val = 3; break;
999 case 11025: val = 10; break;
1000 case 12000: val = 2; break;
1001 case 16000: val = 5; break;
1002 case 22050: val = 9; break;
1003 case 24000: val = 1; break;
1004 case 32000: val = 4; break;
1005 case 44100: val = 8; break;
1006 case 48000: val = 0; break;
1007 case 64000: val = 15; break;
1008 case 88200: val = 11; break;
1009 case 96000: val = 7; break;
1010 default:
1011 snd_BUG();
1012 val = 0;
1013 rate = 48000;
1014 break;
1015 }
1016
1017 spin_lock_irqsave(&ice->reg_lock, flags);
1018 if (inb(ICEMT(ice, PLAYBACK_CONTROL)) & (ICE1712_CAPTURE_START_SHADOW|
1019 ICE1712_PLAYBACK_PAUSE|
1020 ICE1712_PLAYBACK_START)) {
3d8cb466 1021__out:
1da177e4
LT		 1022 spin_unlock_irqrestore(&ice->reg_lock, flags);
1023 return;
1024 }
1025 if (!force && is_pro_rate_locked(ice))
1026 goto __out;
1027
3d8cb466 1028 old = inb(ICEMT(ice, RATE));
1da177e4
LT		 1029 if (!force && old == val)
1030 goto __out;
6ea0cae7
OZ		 1031
1032 ice->cur_rate = rate;
1da177e4
LT		 1033 outb(val, ICEMT(ice, RATE));
1034 spin_unlock_irqrestore(&ice->reg_lock, flags);
1035
1036 if (ice->gpio.set_pro_rate)
1037 ice->gpio.set_pro_rate(ice, rate);
1038 for (i = 0; i < ice->akm_codecs; i++) {
1039 if (ice->akm[i].ops.set_rate_val)
1040 ice->akm[i].ops.set_rate_val(&ice->akm[i], rate);
1041 }
1042 if (ice->spdif.ops.setup_rate)
1043 ice->spdif.ops.setup_rate(ice, rate);
1044}
1045
6ca308d4 1046static int snd_ice1712_playback_pro_prepare(struct snd_pcm_substream *substream)
1da177e4 1047{
6ca308d4 1048 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 1049
1050 ice->playback_pro_size = snd_pcm_lib_buffer_bytes(substream);
1051 spin_lock_irq(&ice->reg_lock);
1052 outl(substream->runtime->dma_addr, ICEMT(ice, PLAYBACK_ADDR));
1053 outw((ice->playback_pro_size >> 2) - 1, ICEMT(ice, PLAYBACK_SIZE));
1054 outw((snd_pcm_lib_period_bytes(substream) >> 2) - 1, ICEMT(ice, PLAYBACK_COUNT));
1055 spin_unlock_irq(&ice->reg_lock);
1056
1057 return 0;
1058}
1059
6ca308d4
TI		 1060static int snd_ice1712_playback_pro_hw_params(struct snd_pcm_substream *substream,
1061 struct snd_pcm_hw_params *hw_params)
1da177e4 1062{
6ca308d4 1063 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 1064
1065 snd_ice1712_set_pro_rate(ice, params_rate(hw_params), 0);
1066 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
1067}
1068
6ca308d4 1069static int snd_ice1712_capture_pro_prepare(struct snd_pcm_substream *substream)
1da177e4 1070{
6ca308d4 1071 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 1072
1073 ice->capture_pro_size = snd_pcm_lib_buffer_bytes(substream);
1074 spin_lock_irq(&ice->reg_lock);
1075 outl(substream->runtime->dma_addr, ICEMT(ice, CAPTURE_ADDR));
1076 outw((ice->capture_pro_size >> 2) - 1, ICEMT(ice, CAPTURE_SIZE));
1077 outw((snd_pcm_lib_period_bytes(substream) >> 2) - 1, ICEMT(ice, CAPTURE_COUNT));
1078 spin_unlock_irq(&ice->reg_lock);
1079 return 0;
1080}
1081
6ca308d4
TI		 1082static int snd_ice1712_capture_pro_hw_params(struct snd_pcm_substream *substream,
1083 struct snd_pcm_hw_params *hw_params)
1da177e4 1084{
6ca308d4 1085 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 1086
1087 snd_ice1712_set_pro_rate(ice, params_rate(hw_params), 0);
1088 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
1089}
1090
6ca308d4 1091static snd_pcm_uframes_t snd_ice1712_playback_pro_pointer(struct snd_pcm_substream *substream)
1da177e4 1092{
6ca308d4 1093 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 1094 size_t ptr;
1095
1096 if (!(inl(ICEMT(ice, PLAYBACK_CONTROL)) & ICE1712_PLAYBACK_START))
1097 return 0;
1098 ptr = ice->playback_pro_size - (inw(ICEMT(ice, PLAYBACK_SIZE)) << 2);
4f8e9400 1099 ptr = bytes_to_frames(substream->runtime, ptr);
1da177e4
LT		 1100 if (ptr == substream->runtime->buffer_size)
1101 ptr = 0;
4f8e9400 1102 return ptr;
1da177e4
LT		 1103}
1104
6ca308d4 1105static snd_pcm_uframes_t snd_ice1712_capture_pro_pointer(struct snd_pcm_substream *substream)
1da177e4 1106{
6ca308d4 1107 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 1108 size_t ptr;
1109
1110 if (!(inl(ICEMT(ice, PLAYBACK_CONTROL)) & ICE1712_CAPTURE_START_SHADOW))
1111 return 0;
1112 ptr = ice->capture_pro_size - (inw(ICEMT(ice, CAPTURE_SIZE)) << 2);
4f8e9400 1113 ptr = bytes_to_frames(substream->runtime, ptr);
1da177e4
LT		 1114 if (ptr == substream->runtime->buffer_size)
1115 ptr = 0;
4f8e9400 1116 return ptr;
1da177e4
LT		 1117}
1118
3d8cb466 1119static const struct snd_pcm_hardware snd_ice1712_playback_pro = {
1da177e4
LT		 1120 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1121 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1122 SNDRV_PCM_INFO_MMAP_VALID |
1123 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
1124 .formats = SNDRV_PCM_FMTBIT_S32_LE,
1125 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_96000,
1126 .rate_min = 4000,
1127 .rate_max = 96000,
1128 .channels_min = 10,
1129 .channels_max = 10,
1130 .buffer_bytes_max = (256*1024),
1131 .period_bytes_min = 10 * 4 * 2,
1132 .period_bytes_max = 131040,
1133 .periods_min = 1,
1134 .periods_max = 1024,
1135 .fifo_size = 0,
1136};
1137
3d8cb466 1138static const struct snd_pcm_hardware snd_ice1712_capture_pro = {
1da177e4
LT		 1139 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1140 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1141 SNDRV_PCM_INFO_MMAP_VALID |
1142 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
1143 .formats = SNDRV_PCM_FMTBIT_S32_LE,
1144 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_96000,
1145 .rate_min = 4000,
1146 .rate_max = 96000,
1147 .channels_min = 12,
1148 .channels_max = 12,
1149 .buffer_bytes_max = (256*1024),
1150 .period_bytes_min = 12 * 4 * 2,
1151 .period_bytes_max = 131040,
1152 .periods_min = 1,
1153 .periods_max = 1024,
1154 .fifo_size = 0,
1155};
1156
6ca308d4 1157static int snd_ice1712_playback_pro_open(struct snd_pcm_substream *substream)
1da177e4 1158{
6ca308d4
TI		 1159 struct snd_pcm_runtime *runtime = substream->runtime;
1160 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 1161
1162 ice->playback_pro_substream = substream;
1163 runtime->hw = snd_ice1712_playback_pro;
1164 snd_pcm_set_sync(substream);
1165 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1166 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
350a5147
SA		 1167 if (is_pro_rate_locked(ice)) {
1168 runtime->hw.rate_min = PRO_RATE_DEFAULT;
1169 runtime->hw.rate_max = PRO_RATE_DEFAULT;
1170 }
1da177e4
LT		 1171
1172 if (ice->spdif.ops.open)
1173 ice->spdif.ops.open(ice, substream);
1174
1175 return 0;
1176}
1177
6ca308d4 1178static int snd_ice1712_capture_pro_open(struct snd_pcm_substream *substream)
1da177e4 1179{
6ca308d4
TI		 1180 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1181 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1182
1183 ice->capture_pro_substream = substream;
1184 runtime->hw = snd_ice1712_capture_pro;
1185 snd_pcm_set_sync(substream);
1186 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1187 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
350a5147
SA		 1188 if (is_pro_rate_locked(ice)) {
1189 runtime->hw.rate_min = PRO_RATE_DEFAULT;
1190 runtime->hw.rate_max = PRO_RATE_DEFAULT;
1191 }
1192
1da177e4
LT		 1193 return 0;
1194}
1195
6ca308d4 1196static int snd_ice1712_playback_pro_close(struct snd_pcm_substream *substream)
1da177e4 1197{
6ca308d4 1198 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 1199
1200 if (PRO_RATE_RESET)
1201 snd_ice1712_set_pro_rate(ice, PRO_RATE_DEFAULT, 0);
1202 ice->playback_pro_substream = NULL;
1203 if (ice->spdif.ops.close)
1204 ice->spdif.ops.close(ice, substream);
1205
1206 return 0;
1207}
1208
6ca308d4 1209static int snd_ice1712_capture_pro_close(struct snd_pcm_substream *substream)
1da177e4 1210{
6ca308d4 1211 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
1da177e4
LT		 1212
1213 if (PRO_RATE_RESET)
1214 snd_ice1712_set_pro_rate(ice, PRO_RATE_DEFAULT, 0);
1215 ice->capture_pro_substream = NULL;
1216 return 0;
1217}
1218
6769e988 1219static const struct snd_pcm_ops snd_ice1712_playback_pro_ops = {
1da177e4
LT		 1220 .open = snd_ice1712_playback_pro_open,
1221 .close = snd_ice1712_playback_pro_close,
1222 .ioctl = snd_pcm_lib_ioctl,
1223 .hw_params = snd_ice1712_playback_pro_hw_params,
1224 .hw_free = snd_ice1712_hw_free,
1225 .prepare = snd_ice1712_playback_pro_prepare,
1226 .trigger = snd_ice1712_pro_trigger,
1227 .pointer = snd_ice1712_playback_pro_pointer,
1228};
1229
6769e988 1230static const struct snd_pcm_ops snd_ice1712_capture_pro_ops = {
1da177e4
LT		 1231 .open = snd_ice1712_capture_pro_open,
1232 .close = snd_ice1712_capture_pro_close,
1233 .ioctl = snd_pcm_lib_ioctl,
1234 .hw_params = snd_ice1712_capture_pro_hw_params,
1235 .hw_free = snd_ice1712_hw_free,
1236 .prepare = snd_ice1712_capture_pro_prepare,
1237 .trigger = snd_ice1712_pro_trigger,
1238 .pointer = snd_ice1712_capture_pro_pointer,
1239};
1240
08a4c10b 1241static int snd_ice1712_pcm_profi(struct snd_ice1712 *ice, int device)
1da177e4 1242{
6ca308d4 1243 struct snd_pcm *pcm;
1da177e4
LT		 1244 int err;
1245
1da177e4
LT		 1246 err = snd_pcm_new(ice->card, "ICE1712 multi", device, 1, 1, &pcm);
1247 if (err < 0)
1248 return err;
1249
1250 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ice1712_playback_pro_ops);
1251 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ice1712_capture_pro_ops);
1252
1253 pcm->private_data = ice;
1da177e4
LT		 1254 pcm->info_flags = 0;
1255 strcpy(pcm->name, "ICE1712 multi");
1256
1257 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
6974f8ad
TI		 1258 &ice->pci->dev,
1259 256*1024, 256*1024);
1da177e4
LT		 1260
1261 ice->pcm_pro = pcm;
3d8cb466 1262
1da177e4
LT		 1263 if (ice->cs8427) {
1264 /* assign channels to iec958 */
1265 err = snd_cs8427_iec958_build(ice->cs8427,
1266 pcm->streams[0].substream,
1267 pcm->streams[1].substream);
1268 if (err < 0)
1269 return err;
1270 }
1271
387417b5 1272 return snd_ice1712_build_pro_mixer(ice);
1da177e4
LT		 1273}
1274
1275/*
1276 * Mixer section
1277 */
1278
6ca308d4 1279static void snd_ice1712_update_volume(struct snd_ice1712 *ice, int index)
1da177e4
LT		 1280{
1281 unsigned int vol = ice->pro_volumes[index];
1282 unsigned short val = 0;
1283
1284 val |= (vol & 0x8000) == 0 ? (96 - (vol & 0x7f)) : 0x7f;
1285 val |= ((vol & 0x80000000) == 0 ? (96 - ((vol >> 16) & 0x7f)) : 0x7f) << 8;
1286 outb(index, ICEMT(ice, MONITOR_INDEX));
1287 outw(val, ICEMT(ice, MONITOR_VOLUME));
1288}
1289
a5ce8890 1290#define snd_ice1712_pro_mixer_switch_info snd_ctl_boolean_stereo_info
1da177e4 1291
6ca308d4 1292static int snd_ice1712_pro_mixer_switch_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1293{
6ca308d4 1294 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
c3daa92d
HH		 1295 int priv_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) +
1296 kcontrol->private_value;
3d8cb466 1297
1da177e4 1298 spin_lock_irq(&ice->reg_lock);
c3daa92d
HH		 1299 ucontrol->value.integer.value[0] =
1300 !((ice->pro_volumes[priv_idx] >> 15) & 1);
1301 ucontrol->value.integer.value[1] =
1302 !((ice->pro_volumes[priv_idx] >> 31) & 1);
1da177e4
LT		 1303 spin_unlock_irq(&ice->reg_lock);
1304 return 0;
1305}
1306
6ca308d4 1307static int snd_ice1712_pro_mixer_switch_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1308{
6ca308d4 1309 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
c3daa92d
HH		 1310 int priv_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) +
1311 kcontrol->private_value;
1da177e4
LT		 1312 unsigned int nval, change;
1313
1314 nval = (ucontrol->value.integer.value[0] ? 0 : 0x00008000) |
1315 (ucontrol->value.integer.value[1] ? 0 : 0x80000000);
1316 spin_lock_irq(&ice->reg_lock);
c3daa92d
HH		 1317 nval |= ice->pro_volumes[priv_idx] & ~0x80008000;
1318 change = nval != ice->pro_volumes[priv_idx];
1319 ice->pro_volumes[priv_idx] = nval;
1320 snd_ice1712_update_volume(ice, priv_idx);
1da177e4
LT		 1321 spin_unlock_irq(&ice->reg_lock);
1322 return change;
1323}
1324
6ca308d4 1325static int snd_ice1712_pro_mixer_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1326{
1327 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1328 uinfo->count = 2;
1329 uinfo->value.integer.min = 0;
1330 uinfo->value.integer.max = 96;
1331 return 0;
1332}
1333
6ca308d4 1334static int snd_ice1712_pro_mixer_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1335{
6ca308d4 1336 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
c3daa92d
HH		 1337 int priv_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) +
1338 kcontrol->private_value;
3d8cb466 1339
1da177e4 1340 spin_lock_irq(&ice->reg_lock);
c3daa92d
HH		 1341 ucontrol->value.integer.value[0] =
1342 (ice->pro_volumes[priv_idx] >> 0) & 127;
1343 ucontrol->value.integer.value[1] =
1344 (ice->pro_volumes[priv_idx] >> 16) & 127;
1da177e4
LT		 1345 spin_unlock_irq(&ice->reg_lock);
1346 return 0;
1347}
1348
6ca308d4 1349static int snd_ice1712_pro_mixer_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1350{
6ca308d4 1351 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
c3daa92d
HH		 1352 int priv_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) +
1353 kcontrol->private_value;
1da177e4
LT		 1354 unsigned int nval, change;
1355
1356 nval = (ucontrol->value.integer.value[0] & 127) |
1357 ((ucontrol->value.integer.value[1] & 127) << 16);
1358 spin_lock_irq(&ice->reg_lock);
c3daa92d
HH		 1359 nval |= ice->pro_volumes[priv_idx] & ~0x007f007f;
1360 change = nval != ice->pro_volumes[priv_idx];
1361 ice->pro_volumes[priv_idx] = nval;
1362 snd_ice1712_update_volume(ice, priv_idx);
1da177e4
LT		 1363 spin_unlock_irq(&ice->reg_lock);
1364 return change;
1365}
1366
0cb29ea0 1367static const DECLARE_TLV_DB_SCALE(db_scale_playback, -14400, 150, 0);
1da177e4 1368
e23e7a14 1369static struct snd_kcontrol_new snd_ice1712_multi_playback_ctrls[] = {
1da177e4
LT		 1370 {
1371 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1372 .name = "Multi Playback Switch",
1373 .info = snd_ice1712_pro_mixer_switch_info,
1374 .get = snd_ice1712_pro_mixer_switch_get,
1375 .put = snd_ice1712_pro_mixer_switch_put,
1376 .private_value = 0,
1377 .count = 10,
1378 },
1379 {
1380 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
680ef792
TI		 1381 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
1382 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
1da177e4
LT		 1383 .name = "Multi Playback Volume",
1384 .info = snd_ice1712_pro_mixer_volume_info,
1385 .get = snd_ice1712_pro_mixer_volume_get,
1386 .put = snd_ice1712_pro_mixer_volume_put,
1387 .private_value = 0,
1388 .count = 10,
680ef792 1389 .tlv = { .p = db_scale_playback }
1da177e4
LT		 1390 },
1391};
1392
6ba1ad38 1393static const struct snd_kcontrol_new snd_ice1712_multi_capture_analog_switch = {
1da177e4
LT		 1394 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1395 .name = "H/W Multi Capture Switch",
1396 .info = snd_ice1712_pro_mixer_switch_info,
1397 .get = snd_ice1712_pro_mixer_switch_get,
1398 .put = snd_ice1712_pro_mixer_switch_put,
1399 .private_value = 10,
1400};
1401
f3b827e0 1402static const struct snd_kcontrol_new snd_ice1712_multi_capture_spdif_switch = {
1da177e4 1403 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3d8cb466 1404 .name = SNDRV_CTL_NAME_IEC958("Multi ", CAPTURE, SWITCH),
1da177e4
LT		 1405 .info = snd_ice1712_pro_mixer_switch_info,
1406 .get = snd_ice1712_pro_mixer_switch_get,
1407 .put = snd_ice1712_pro_mixer_switch_put,
1408 .private_value = 18,
1409 .count = 2,
1410};
1411
6ba1ad38 1412static const struct snd_kcontrol_new snd_ice1712_multi_capture_analog_volume = {
1da177e4 1413 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
680ef792
TI		 1414 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
1415 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
1da177e4
LT		 1416 .name = "H/W Multi Capture Volume",
1417 .info = snd_ice1712_pro_mixer_volume_info,
1418 .get = snd_ice1712_pro_mixer_volume_get,
1419 .put = snd_ice1712_pro_mixer_volume_put,
1420 .private_value = 10,
680ef792 1421 .tlv = { .p = db_scale_playback }
1da177e4
LT		 1422};
1423
f3b827e0 1424static const struct snd_kcontrol_new snd_ice1712_multi_capture_spdif_volume = {
1da177e4 1425 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3d8cb466 1426 .name = SNDRV_CTL_NAME_IEC958("Multi ", CAPTURE, VOLUME),
1da177e4
LT		 1427 .info = snd_ice1712_pro_mixer_volume_info,
1428 .get = snd_ice1712_pro_mixer_volume_get,
1429 .put = snd_ice1712_pro_mixer_volume_put,
1430 .private_value = 18,
1431 .count = 2,
1432};
1433
e23e7a14 1434static int snd_ice1712_build_pro_mixer(struct snd_ice1712 *ice)
1da177e4 1435{
6ca308d4 1436 struct snd_card *card = ice->card;
1da177e4
LT		 1437 unsigned int idx;
1438 int err;
1439
1440 /* multi-channel mixer */
1441 for (idx = 0; idx < ARRAY_SIZE(snd_ice1712_multi_playback_ctrls); idx++) {
1442 err = snd_ctl_add(card, snd_ctl_new1(&snd_ice1712_multi_playback_ctrls[idx], ice));
1443 if (err < 0)
1444 return err;
1445 }
3d8cb466 1446
1da177e4 1447 if (ice->num_total_adcs > 0) {
6ca308d4 1448 struct snd_kcontrol_new tmp = snd_ice1712_multi_capture_analog_switch;
1da177e4
LT		 1449 tmp.count = ice->num_total_adcs;
1450 err = snd_ctl_add(card, snd_ctl_new1(&tmp, ice));
1451 if (err < 0)
1452 return err;
1453 }
1454
1455 err = snd_ctl_add(card, snd_ctl_new1(&snd_ice1712_multi_capture_spdif_switch, ice));
1456 if (err < 0)
1457 return err;
1458
1459 if (ice->num_total_adcs > 0) {
6ca308d4 1460 struct snd_kcontrol_new tmp = snd_ice1712_multi_capture_analog_volume;
1da177e4
LT		 1461 tmp.count = ice->num_total_adcs;
1462 err = snd_ctl_add(card, snd_ctl_new1(&tmp, ice));
1463 if (err < 0)
1464 return err;
1465 }
1466
1467 err = snd_ctl_add(card, snd_ctl_new1(&snd_ice1712_multi_capture_spdif_volume, ice));
1468 if (err < 0)
1469 return err;
1470
1471 /* initialize volumes */
1472 for (idx = 0; idx < 10; idx++) {
1473 ice->pro_volumes[idx] = 0x80008000; /* mute */
1474 snd_ice1712_update_volume(ice, idx);
1475 }
1476 for (idx = 10; idx < 10 + ice->num_total_adcs; idx++) {
1477 ice->pro_volumes[idx] = 0x80008000; /* mute */
1478 snd_ice1712_update_volume(ice, idx);
1479 }
1480 for (idx = 18; idx < 20; idx++) {
1481 ice->pro_volumes[idx] = 0x80008000; /* mute */
1482 snd_ice1712_update_volume(ice, idx);
1483 }
1484 return 0;
1485}
1486
6ca308d4 1487static void snd_ice1712_mixer_free_ac97(struct snd_ac97 *ac97)
1da177e4 1488{
6ca308d4 1489 struct snd_ice1712 *ice = ac97->private_data;
1da177e4
LT		 1490 ice->ac97 = NULL;
1491}
1492
e23e7a14 1493static int snd_ice1712_ac97_mixer(struct snd_ice1712 *ice)
1da177e4
LT		 1494{
1495 int err, bus_num = 0;
6ca308d4
TI		 1496 struct snd_ac97_template ac97;
1497 struct snd_ac97_bus *pbus;
1498 static struct snd_ac97_bus_ops con_ops = {
1da177e4
LT		 1499 .write = snd_ice1712_ac97_write,
1500 .read = snd_ice1712_ac97_read,
1501 };
6ca308d4 1502 static struct snd_ac97_bus_ops pro_ops = {
1da177e4
LT		 1503 .write = snd_ice1712_pro_ac97_write,
1504 .read = snd_ice1712_pro_ac97_read,
1505 };
1506
1507 if (ice_has_con_ac97(ice)) {
3d8cb466
AB		 1508 err = snd_ac97_bus(ice->card, bus_num++, &con_ops, NULL, &pbus);
1509 if (err < 0)
1da177e4
LT		 1510 return err;
1511 memset(&ac97, 0, sizeof(ac97));
1512 ac97.private_data = ice;
1513 ac97.private_free = snd_ice1712_mixer_free_ac97;
3d8cb466
AB		 1514 err = snd_ac97_mixer(pbus, &ac97, &ice->ac97);
1515 if (err < 0)
6dfb5aff
TI		 1516 dev_warn(ice->card->dev,
1517 "cannot initialize ac97 for consumer, skipped\n");
1da177e4 1518 else {
387417b5
SM		 1519 return snd_ctl_add(ice->card,
1520 snd_ctl_new1(&snd_ice1712_mixer_digmix_route_ac97,
1521 ice));
1da177e4
LT		 1522 }
1523 }
1524
3d8cb466
AB		 1525 if (!(ice->eeprom.data[ICE_EEP1_ACLINK] & ICE1712_CFG_PRO_I2S)) {
1526 err = snd_ac97_bus(ice->card, bus_num, &pro_ops, NULL, &pbus);
1527 if (err < 0)
1da177e4
LT		 1528 return err;
1529 memset(&ac97, 0, sizeof(ac97));
1530 ac97.private_data = ice;
1531 ac97.private_free = snd_ice1712_mixer_free_ac97;
3d8cb466
AB		 1532 err = snd_ac97_mixer(pbus, &ac97, &ice->ac97);
1533 if (err < 0)
6dfb5aff
TI		 1534 dev_warn(ice->card->dev,
1535 "cannot initialize pro ac97, skipped\n");
1da177e4
LT		 1536 else
1537 return 0;
1538 }
1539 /* I2S mixer only */
1540 strcat(ice->card->mixername, "ICE1712 - multitrack");
1541 return 0;
1542}
1543
1544/*
1545 *
1546 */
1547
6ca308d4 1548static inline unsigned int eeprom_double(struct snd_ice1712 *ice, int idx)
1da177e4
LT		 1549{
1550 return (unsigned int)ice->eeprom.data[idx] | ((unsigned int)ice->eeprom.data[idx + 1] << 8);
1551}
1552
3d8cb466 1553static void snd_ice1712_proc_read(struct snd_info_entry *entry,
6ca308d4 1554 struct snd_info_buffer *buffer)
1da177e4 1555{
6ca308d4 1556 struct snd_ice1712 *ice = entry->private_data;
1da177e4
LT		 1557 unsigned int idx;
1558
1559 snd_iprintf(buffer, "%s\n\n", ice->card->longname);
1560 snd_iprintf(buffer, "EEPROM:\n");
1561
1562 snd_iprintf(buffer, " Subvendor : 0x%x\n", ice->eeprom.subvendor);
1563 snd_iprintf(buffer, " Size : %i bytes\n", ice->eeprom.size);
1564 snd_iprintf(buffer, " Version : %i\n", ice->eeprom.version);
1565 snd_iprintf(buffer, " Codec : 0x%x\n", ice->eeprom.data[ICE_EEP1_CODEC]);
1566 snd_iprintf(buffer, " ACLink : 0x%x\n", ice->eeprom.data[ICE_EEP1_ACLINK]);
1567 snd_iprintf(buffer, " I2S ID : 0x%x\n", ice->eeprom.data[ICE_EEP1_I2SID]);
1568 snd_iprintf(buffer, " S/PDIF : 0x%x\n", ice->eeprom.data[ICE_EEP1_SPDIF]);
1569 snd_iprintf(buffer, " GPIO mask : 0x%x\n", ice->eeprom.gpiomask);
1570 snd_iprintf(buffer, " GPIO state : 0x%x\n", ice->eeprom.gpiostate);
1571 snd_iprintf(buffer, " GPIO direction : 0x%x\n", ice->eeprom.gpiodir);
1572 snd_iprintf(buffer, " AC'97 main : 0x%x\n", eeprom_double(ice, ICE_EEP1_AC97_MAIN_LO));
1573 snd_iprintf(buffer, " AC'97 pcm : 0x%x\n", eeprom_double(ice, ICE_EEP1_AC97_PCM_LO));
1574 snd_iprintf(buffer, " AC'97 record : 0x%x\n", eeprom_double(ice, ICE_EEP1_AC97_REC_LO));
1575 snd_iprintf(buffer, " AC'97 record src : 0x%x\n", ice->eeprom.data[ICE_EEP1_AC97_RECSRC]);
1576 for (idx = 0; idx < 4; idx++)
1577 snd_iprintf(buffer, " DAC ID #%i : 0x%x\n", idx, ice->eeprom.data[ICE_EEP1_DAC_ID + idx]);
1578 for (idx = 0; idx < 4; idx++)
1579 snd_iprintf(buffer, " ADC ID #%i : 0x%x\n", idx, ice->eeprom.data[ICE_EEP1_ADC_ID + idx]);
1580 for (idx = 0x1c; idx < ice->eeprom.size; idx++)
1581 snd_iprintf(buffer, " Extra #%02i : 0x%x\n", idx, ice->eeprom.data[idx]);
1582
1583 snd_iprintf(buffer, "\nRegisters:\n");
1584 snd_iprintf(buffer, " PSDOUT03 : 0x%04x\n", (unsigned)inw(ICEMT(ice, ROUTE_PSDOUT03)));
1585 snd_iprintf(buffer, " CAPTURE : 0x%08x\n", inl(ICEMT(ice, ROUTE_CAPTURE)));
1586 snd_iprintf(buffer, " SPDOUT : 0x%04x\n", (unsigned)inw(ICEMT(ice, ROUTE_SPDOUT)));
1587 snd_iprintf(buffer, " RATE : 0x%02x\n", (unsigned)inb(ICEMT(ice, RATE)));
f7004f39 1588 snd_iprintf(buffer, " GPIO_DATA : 0x%02x\n", (unsigned)snd_ice1712_get_gpio_data(ice));
3d8cb466 1589 snd_iprintf(buffer, " GPIO_WRITE_MASK : 0x%02x\n", (unsigned)snd_ice1712_read(ice, ICE1712_IREG_GPIO_WRITE_MASK));
f7004f39 1590 snd_iprintf(buffer, " GPIO_DIRECTION : 0x%02x\n", (unsigned)snd_ice1712_read(ice, ICE1712_IREG_GPIO_DIRECTION));
1da177e4
LT		 1591}
1592
e23e7a14 1593static void snd_ice1712_proc_init(struct snd_ice1712 *ice)
1da177e4 1594{
47f2769b 1595 snd_card_ro_proc_new(ice->card, "ice1712", ice, snd_ice1712_proc_read);
1da177e4
LT		 1596}
1597
1598/*
1599 *
1600 */
1601
6ca308d4
TI		 1602static int snd_ice1712_eeprom_info(struct snd_kcontrol *kcontrol,
1603 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1604{
1605 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
6ca308d4 1606 uinfo->count = sizeof(struct snd_ice1712_eeprom);
1da177e4
LT		 1607 return 0;
1608}
1609
6ca308d4
TI		 1610static int snd_ice1712_eeprom_get(struct snd_kcontrol *kcontrol,
1611 struct snd_ctl_elem_value *ucontrol)
1da177e4 1612{
6ca308d4 1613 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
3d8cb466 1614
1da177e4
LT		 1615 memcpy(ucontrol->value.bytes.data, &ice->eeprom, sizeof(ice->eeprom));
1616 return 0;
1617}
1618
f3b827e0 1619static const struct snd_kcontrol_new snd_ice1712_eeprom = {
1da177e4
LT		 1620 .iface = SNDRV_CTL_ELEM_IFACE_CARD,
1621 .name = "ICE1712 EEPROM",
1622 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1623 .info = snd_ice1712_eeprom_info,
1624 .get = snd_ice1712_eeprom_get
1625};
1626
1627/*
1628 */
6ca308d4
TI		 1629static int snd_ice1712_spdif_info(struct snd_kcontrol *kcontrol,
1630 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1631{
1632 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1633 uinfo->count = 1;
1634 return 0;
1635}
1636
6ca308d4
TI		 1637static int snd_ice1712_spdif_default_get(struct snd_kcontrol *kcontrol,
1638 struct snd_ctl_elem_value *ucontrol)
1da177e4 1639{
6ca308d4 1640 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4 1641 if (ice->spdif.ops.default_get)
3d8cb466 1642 ice->spdif.ops.default_get(ice, ucontrol);
1da177e4
LT		 1643 return 0;
1644}
1645
6ca308d4
TI		 1646static int snd_ice1712_spdif_default_put(struct snd_kcontrol *kcontrol,
1647 struct snd_ctl_elem_value *ucontrol)
1da177e4 1648{
6ca308d4 1649 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1650 if (ice->spdif.ops.default_put)
1651 return ice->spdif.ops.default_put(ice, ucontrol);
1652 return 0;
1653}
1654
f3b827e0 1655static const struct snd_kcontrol_new snd_ice1712_spdif_default =
1da177e4
LT		 1656{
1657 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
3d8cb466 1658 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1da177e4
LT		 1659 .info = snd_ice1712_spdif_info,
1660 .get = snd_ice1712_spdif_default_get,
1661 .put = snd_ice1712_spdif_default_put
1662};
1663
6ca308d4
TI		 1664static int snd_ice1712_spdif_maskc_get(struct snd_kcontrol *kcontrol,
1665 struct snd_ctl_elem_value *ucontrol)
1da177e4 1666{
6ca308d4 1667 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1668 if (ice->spdif.ops.default_get) {
1669 ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
1670 IEC958_AES0_PROFESSIONAL |
1671 IEC958_AES0_CON_NOT_COPYRIGHT |
1672 IEC958_AES0_CON_EMPHASIS;
1673 ucontrol->value.iec958.status[1] = IEC958_AES1_CON_ORIGINAL |
1674 IEC958_AES1_CON_CATEGORY;
1675 ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS;
1676 } else {
1677 ucontrol->value.iec958.status[0] = 0xff;
1678 ucontrol->value.iec958.status[1] = 0xff;
1679 ucontrol->value.iec958.status[2] = 0xff;
1680 ucontrol->value.iec958.status[3] = 0xff;
1681 ucontrol->value.iec958.status[4] = 0xff;
1682 }
1683 return 0;
1684}
1685
6ca308d4
TI		 1686static int snd_ice1712_spdif_maskp_get(struct snd_kcontrol *kcontrol,
1687 struct snd_ctl_elem_value *ucontrol)
1da177e4 1688{
6ca308d4 1689 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1690 if (ice->spdif.ops.default_get) {
1691 ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
1692 IEC958_AES0_PROFESSIONAL |
1693 IEC958_AES0_PRO_FS |
1694 IEC958_AES0_PRO_EMPHASIS;
1695 ucontrol->value.iec958.status[1] = IEC958_AES1_PRO_MODE;
1696 } else {
1697 ucontrol->value.iec958.status[0] = 0xff;
1698 ucontrol->value.iec958.status[1] = 0xff;
1699 ucontrol->value.iec958.status[2] = 0xff;
1700 ucontrol->value.iec958.status[3] = 0xff;
1701 ucontrol->value.iec958.status[4] = 0xff;
1702 }
1703 return 0;
1704}
1705
f3b827e0 1706static const struct snd_kcontrol_new snd_ice1712_spdif_maskc =
1da177e4
LT		 1707{
1708 .access = SNDRV_CTL_ELEM_ACCESS_READ,
67ed4161 1709 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
3d8cb466 1710 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
1da177e4
LT		 1711 .info = snd_ice1712_spdif_info,
1712 .get = snd_ice1712_spdif_maskc_get,
1713};
1714
f3b827e0 1715static const struct snd_kcontrol_new snd_ice1712_spdif_maskp =
1da177e4
LT		 1716{
1717 .access = SNDRV_CTL_ELEM_ACCESS_READ,
67ed4161 1718 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
3d8cb466 1719 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK),
1da177e4
LT		 1720 .info = snd_ice1712_spdif_info,
1721 .get = snd_ice1712_spdif_maskp_get,
1722};
1723
6ca308d4
TI		 1724static int snd_ice1712_spdif_stream_get(struct snd_kcontrol *kcontrol,
1725 struct snd_ctl_elem_value *ucontrol)
1da177e4 1726{
6ca308d4 1727 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1728 if (ice->spdif.ops.stream_get)
1729 ice->spdif.ops.stream_get(ice, ucontrol);
1730 return 0;
1731}
1732
6ca308d4
TI		 1733static int snd_ice1712_spdif_stream_put(struct snd_kcontrol *kcontrol,
1734 struct snd_ctl_elem_value *ucontrol)
1da177e4 1735{
6ca308d4 1736 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1737 if (ice->spdif.ops.stream_put)
1738 return ice->spdif.ops.stream_put(ice, ucontrol);
1739 return 0;
1740}
1741
f3b827e0 1742static const struct snd_kcontrol_new snd_ice1712_spdif_stream =
1da177e4 1743{
6ca308d4
TI		 1744 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
1745 SNDRV_CTL_ELEM_ACCESS_INACTIVE),
1da177e4 1746 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
3d8cb466 1747 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM),
1da177e4
LT		 1748 .info = snd_ice1712_spdif_info,
1749 .get = snd_ice1712_spdif_stream_get,
1750 .put = snd_ice1712_spdif_stream_put
1751};
1752
6ca308d4
TI		 1753int snd_ice1712_gpio_get(struct snd_kcontrol *kcontrol,
1754 struct snd_ctl_elem_value *ucontrol)
1da177e4 1755{
6ca308d4 1756 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1757 unsigned char mask = kcontrol->private_value & 0xff;
1758 int invert = (kcontrol->private_value & (1<<24)) ? 1 : 0;
3d8cb466 1759
1da177e4 1760 snd_ice1712_save_gpio_status(ice);
6ca308d4
TI		 1761 ucontrol->value.integer.value[0] =
1762 (snd_ice1712_gpio_read(ice) & mask ? 1 : 0) ^ invert;
1da177e4
LT		 1763 snd_ice1712_restore_gpio_status(ice);
1764 return 0;
1765}
1766
6ca308d4
TI		 1767int snd_ice1712_gpio_put(struct snd_kcontrol *kcontrol,
1768 struct snd_ctl_elem_value *ucontrol)
1da177e4 1769{
6ca308d4 1770 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1771 unsigned char mask = kcontrol->private_value & 0xff;
1772 int invert = (kcontrol->private_value & (1<<24)) ? mask : 0;
1773 unsigned int val, nval;
1774
1775 if (kcontrol->private_value & (1 << 31))
1776 return -EPERM;
1777 nval = (ucontrol->value.integer.value[0] ? mask : 0) ^ invert;
1778 snd_ice1712_save_gpio_status(ice);
1779 val = snd_ice1712_gpio_read(ice);
1780 nval |= val & ~mask;
1781 if (val != nval)
1782 snd_ice1712_gpio_write(ice, nval);
1783 snd_ice1712_restore_gpio_status(ice);
1784 return val != nval;
1785}
1786
1787/*
1788 * rate
1789 */
6ca308d4
TI		 1790static int snd_ice1712_pro_internal_clock_info(struct snd_kcontrol *kcontrol,
1791 struct snd_ctl_elem_info *uinfo)
1da177e4 1792{
32b47da0 1793 static const char * const texts[] = {
1da177e4
LT		 1794 "8000", /* 0: 6 */
1795 "9600", /* 1: 3 */
1796 "11025", /* 2: 10 */
1797 "12000", /* 3: 2 */
1798 "16000", /* 4: 5 */
1799 "22050", /* 5: 9 */
1800 "24000", /* 6: 1 */
1801 "32000", /* 7: 4 */
1802 "44100", /* 8: 8 */
1803 "48000", /* 9: 0 */
1804 "64000", /* 10: 15 */
1805 "88200", /* 11: 11 */
1806 "96000", /* 12: 7 */
1807 "IEC958 Input", /* 13: -- */
1808 };
c4fa251f 1809 return snd_ctl_enum_info(uinfo, 1, 14, texts);
1da177e4
LT		 1810}
1811
6ca308d4
TI		 1812static int snd_ice1712_pro_internal_clock_get(struct snd_kcontrol *kcontrol,
1813 struct snd_ctl_elem_value *ucontrol)
1da177e4 1814{
6ca308d4 1815 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
32b47da0 1816 static const unsigned char xlate[16] = {
1da177e4
LT		 1817 9, 6, 3, 1, 7, 4, 0, 12, 8, 5, 2, 11, 255, 255, 255, 10
1818 };
1819 unsigned char val;
3d8cb466 1820
1da177e4
LT		 1821 spin_lock_irq(&ice->reg_lock);
1822 if (is_spdif_master(ice)) {
1823 ucontrol->value.enumerated.item[0] = 13;
1824 } else {
1825 val = xlate[inb(ICEMT(ice, RATE)) & 15];
1826 if (val == 255) {
1827 snd_BUG();
1828 val = 0;
1829 }
1830 ucontrol->value.enumerated.item[0] = val;
1831 }
1832 spin_unlock_irq(&ice->reg_lock);
1833 return 0;
1834}
1835
6ca308d4
TI		 1836static int snd_ice1712_pro_internal_clock_put(struct snd_kcontrol *kcontrol,
1837 struct snd_ctl_elem_value *ucontrol)
1da177e4 1838{
6ca308d4 1839 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
32b47da0 1840 static const unsigned int xrate[13] = {
fe25befd 1841 8000, 9600, 11025, 12000, 16000, 22050, 24000,
1da177e4
LT		 1842 32000, 44100, 48000, 64000, 88200, 96000
1843 };
1844 unsigned char oval;
1845 int change = 0;
1846
1847 spin_lock_irq(&ice->reg_lock);
1848 oval = inb(ICEMT(ice, RATE));
1849 if (ucontrol->value.enumerated.item[0] == 13) {
1850 outb(oval | ICE1712_SPDIF_MASTER, ICEMT(ice, RATE));
1851 } else {
1852 PRO_RATE_DEFAULT = xrate[ucontrol->value.integer.value[0] % 13];
1853 spin_unlock_irq(&ice->reg_lock);
1854 snd_ice1712_set_pro_rate(ice, PRO_RATE_DEFAULT, 1);
1855 spin_lock_irq(&ice->reg_lock);
1856 }
1857 change = inb(ICEMT(ice, RATE)) != oval;
1858 spin_unlock_irq(&ice->reg_lock);
1859
6ca308d4 1860 if ((oval & ICE1712_SPDIF_MASTER) !=
e957ebf1 1861 (inb(ICEMT(ice, RATE)) & ICE1712_SPDIF_MASTER))
3d8cb466 1862 snd_ice1712_set_input_clock_source(ice, is_spdif_master(ice));
1da177e4
LT		 1863
1864 return change;
1865}
1866
f3b827e0 1867static const struct snd_kcontrol_new snd_ice1712_pro_internal_clock = {
1da177e4
LT		 1868 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1869 .name = "Multi Track Internal Clock",
1870 .info = snd_ice1712_pro_internal_clock_info,
1871 .get = snd_ice1712_pro_internal_clock_get,
1872 .put = snd_ice1712_pro_internal_clock_put
1873};
1874
6ca308d4
TI		 1875static int snd_ice1712_pro_internal_clock_default_info(struct snd_kcontrol *kcontrol,
1876 struct snd_ctl_elem_info *uinfo)
1da177e4 1877{
32b47da0 1878 static const char * const texts[] = {
1da177e4
LT		 1879 "8000", /* 0: 6 */
1880 "9600", /* 1: 3 */
1881 "11025", /* 2: 10 */
1882 "12000", /* 3: 2 */
1883 "16000", /* 4: 5 */
1884 "22050", /* 5: 9 */
1885 "24000", /* 6: 1 */
1886 "32000", /* 7: 4 */
1887 "44100", /* 8: 8 */
1888 "48000", /* 9: 0 */
1889 "64000", /* 10: 15 */
1890 "88200", /* 11: 11 */
1891 "96000", /* 12: 7 */
3d8cb466 1892 /* "IEC958 Input", 13: -- */
1da177e4 1893 };
c4fa251f 1894 return snd_ctl_enum_info(uinfo, 1, 13, texts);
1da177e4
LT		 1895}
1896
6ca308d4
TI		 1897static int snd_ice1712_pro_internal_clock_default_get(struct snd_kcontrol *kcontrol,
1898 struct snd_ctl_elem_value *ucontrol)
1da177e4
LT		 1899{
1900 int val;
32b47da0 1901 static const unsigned int xrate[13] = {
fe25befd 1902 8000, 9600, 11025, 12000, 16000, 22050, 24000,
1da177e4
LT		 1903 32000, 44100, 48000, 64000, 88200, 96000
1904 };
1905
1906 for (val = 0; val < 13; val++) {
1907 if (xrate[val] == PRO_RATE_DEFAULT)
1908 break;
1909 }
1910
1911 ucontrol->value.enumerated.item[0] = val;
1912 return 0;
1913}
1914
6ca308d4
TI		 1915static int snd_ice1712_pro_internal_clock_default_put(struct snd_kcontrol *kcontrol,
1916 struct snd_ctl_elem_value *ucontrol)
1da177e4 1917{
32b47da0 1918 static const unsigned int xrate[13] = {
fe25befd 1919 8000, 9600, 11025, 12000, 16000, 22050, 24000,
1da177e4
LT		 1920 32000, 44100, 48000, 64000, 88200, 96000
1921 };
1922 unsigned char oval;
1923 int change = 0;
1924
1925 oval = PRO_RATE_DEFAULT;
1926 PRO_RATE_DEFAULT = xrate[ucontrol->value.integer.value[0] % 13];
1927 change = PRO_RATE_DEFAULT != oval;
1928
1929 return change;
1930}
1931
f3b827e0 1932static const struct snd_kcontrol_new snd_ice1712_pro_internal_clock_default = {
1da177e4
LT		 1933 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1934 .name = "Multi Track Internal Clock Default",
1935 .info = snd_ice1712_pro_internal_clock_default_info,
1936 .get = snd_ice1712_pro_internal_clock_default_get,
1937 .put = snd_ice1712_pro_internal_clock_default_put
1938};
1939
a5ce8890 1940#define snd_ice1712_pro_rate_locking_info snd_ctl_boolean_mono_info
1da177e4 1941
6ca308d4
TI		 1942static int snd_ice1712_pro_rate_locking_get(struct snd_kcontrol *kcontrol,
1943 struct snd_ctl_elem_value *ucontrol)
1da177e4
LT		 1944{
1945 ucontrol->value.integer.value[0] = PRO_RATE_LOCKED;
1946 return 0;
1947}
1948
6ca308d4
TI		 1949static int snd_ice1712_pro_rate_locking_put(struct snd_kcontrol *kcontrol,
1950 struct snd_ctl_elem_value *ucontrol)
1da177e4 1951{
6ca308d4 1952 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1953 int change = 0, nval;
1954
1955 nval = ucontrol->value.integer.value[0] ? 1 : 0;
1956 spin_lock_irq(&ice->reg_lock);
1957 change = PRO_RATE_LOCKED != nval;
1958 PRO_RATE_LOCKED = nval;
1959 spin_unlock_irq(&ice->reg_lock);
1960 return change;
1961}
1962
f3b827e0 1963static const struct snd_kcontrol_new snd_ice1712_pro_rate_locking = {
1da177e4
LT		 1964 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1965 .name = "Multi Track Rate Locking",
1966 .info = snd_ice1712_pro_rate_locking_info,
1967 .get = snd_ice1712_pro_rate_locking_get,
1968 .put = snd_ice1712_pro_rate_locking_put
1969};
1970
a5ce8890 1971#define snd_ice1712_pro_rate_reset_info snd_ctl_boolean_mono_info
1da177e4 1972
6ca308d4
TI		 1973static int snd_ice1712_pro_rate_reset_get(struct snd_kcontrol *kcontrol,
1974 struct snd_ctl_elem_value *ucontrol)
1da177e4
LT		 1975{
1976 ucontrol->value.integer.value[0] = PRO_RATE_RESET;
1977 return 0;
1978}
1979
6ca308d4
TI		 1980static int snd_ice1712_pro_rate_reset_put(struct snd_kcontrol *kcontrol,
1981 struct snd_ctl_elem_value *ucontrol)
1da177e4 1982{
6ca308d4 1983 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1984 int change = 0, nval;
1985
1986 nval = ucontrol->value.integer.value[0] ? 1 : 0;
1987 spin_lock_irq(&ice->reg_lock);
1988 change = PRO_RATE_RESET != nval;
1989 PRO_RATE_RESET = nval;
1990 spin_unlock_irq(&ice->reg_lock);
1991 return change;
1992}
1993
f3b827e0 1994static const struct snd_kcontrol_new snd_ice1712_pro_rate_reset = {
1da177e4
LT		 1995 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1996 .name = "Multi Track Rate Reset",
1997 .info = snd_ice1712_pro_rate_reset_info,
1998 .get = snd_ice1712_pro_rate_reset_get,
1999 .put = snd_ice1712_pro_rate_reset_put
2000};
2001
2002/*
2003 * routing
2004 */
6ca308d4
TI		 2005static int snd_ice1712_pro_route_info(struct snd_kcontrol *kcontrol,
2006 struct snd_ctl_elem_info *uinfo)
1da177e4 2007{
32b47da0 2008 static const char * const texts[] = {
1da177e4
LT		 2009 "PCM Out", /* 0 */
2010 "H/W In 0", "H/W In 1", "H/W In 2", "H/W In 3", /* 1-4 */
2011 "H/W In 4", "H/W In 5", "H/W In 6", "H/W In 7", /* 5-8 */
2012 "IEC958 In L", "IEC958 In R", /* 9-10 */
2013 "Digital Mixer", /* 11 - optional */
2014 };
c4fa251f
TI		 2015 int num_items = snd_ctl_get_ioffidx(kcontrol, &uinfo->id) < 2 ? 12 : 11;
2016 return snd_ctl_enum_info(uinfo, 1, num_items, texts);
1da177e4
LT		 2017}
2018
6ca308d4
TI		 2019static int snd_ice1712_pro_route_analog_get(struct snd_kcontrol *kcontrol,
2020 struct snd_ctl_elem_value *ucontrol)
1da177e4 2021{
6ca308d4 2022 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2023 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2024 unsigned int val, cval;
2025
2026 spin_lock_irq(&ice->reg_lock);
2027 val = inw(ICEMT(ice, ROUTE_PSDOUT03));
2028 cval = inl(ICEMT(ice, ROUTE_CAPTURE));
2029 spin_unlock_irq(&ice->reg_lock);
2030
2031 val >>= ((idx % 2) * 8) + ((idx / 2) * 2);
2032 val &= 3;
2033 cval >>= ((idx / 2) * 8) + ((idx % 2) * 4);
2034 if (val == 1 && idx < 2)
2035 ucontrol->value.enumerated.item[0] = 11;
2036 else if (val == 2)
2037 ucontrol->value.enumerated.item[0] = (cval & 7) + 1;
2038 else if (val == 3)
2039 ucontrol->value.enumerated.item[0] = ((cval >> 3) & 1) + 9;
2040 else
2041 ucontrol->value.enumerated.item[0] = 0;
2042 return 0;
2043}
2044
6ca308d4
TI		 2045static int snd_ice1712_pro_route_analog_put(struct snd_kcontrol *kcontrol,
2046 struct snd_ctl_elem_value *ucontrol)
1da177e4 2047{
6ca308d4 2048 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2049 int change, shift;
2050 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2051 unsigned int val, old_val, nval;
3d8cb466 2052
1da177e4
LT		 2053 /* update PSDOUT */
2054 if (ucontrol->value.enumerated.item[0] >= 11)
2055 nval = idx < 2 ? 1 : 0; /* dig mixer (or pcm) */
2056 else if (ucontrol->value.enumerated.item[0] >= 9)
2057 nval = 3; /* spdif in */
2058 else if (ucontrol->value.enumerated.item[0] >= 1)
2059 nval = 2; /* analog in */
2060 else
2061 nval = 0; /* pcm */
2062 shift = ((idx % 2) * 8) + ((idx / 2) * 2);
2063 spin_lock_irq(&ice->reg_lock);
2064 val = old_val = inw(ICEMT(ice, ROUTE_PSDOUT03));
2065 val &= ~(0x03 << shift);
2066 val |= nval << shift;
2067 change = val != old_val;
2068 if (change)
2069 outw(val, ICEMT(ice, ROUTE_PSDOUT03));
2070 spin_unlock_irq(&ice->reg_lock);
2071 if (nval < 2) /* dig mixer of pcm */
2072 return change;
2073
2074 /* update CAPTURE */
2075 spin_lock_irq(&ice->reg_lock);
2076 val = old_val = inl(ICEMT(ice, ROUTE_CAPTURE));
2077 shift = ((idx / 2) * 8) + ((idx % 2) * 4);
2078 if (nval == 2) { /* analog in */
2079 nval = ucontrol->value.enumerated.item[0] - 1;
2080 val &= ~(0x07 << shift);
2081 val |= nval << shift;
2082 } else { /* spdif in */
2083 nval = (ucontrol->value.enumerated.item[0] - 9) << 3;
2084 val &= ~(0x08 << shift);
2085 val |= nval << shift;
2086 }
2087 if (val != old_val) {
2088 change = 1;
2089 outl(val, ICEMT(ice, ROUTE_CAPTURE));
2090 }
2091 spin_unlock_irq(&ice->reg_lock);
2092 return change;
2093}
2094
6ca308d4
TI		 2095static int snd_ice1712_pro_route_spdif_get(struct snd_kcontrol *kcontrol,
2096 struct snd_ctl_elem_value *ucontrol)
1da177e4 2097{
6ca308d4 2098 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2099 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2100 unsigned int val, cval;
2101 val = inw(ICEMT(ice, ROUTE_SPDOUT));
2102 cval = (val >> (idx * 4 + 8)) & 0x0f;
2103 val = (val >> (idx * 2)) & 0x03;
2104 if (val == 1)
2105 ucontrol->value.enumerated.item[0] = 11;
2106 else if (val == 2)
2107 ucontrol->value.enumerated.item[0] = (cval & 7) + 1;
2108 else if (val == 3)
2109 ucontrol->value.enumerated.item[0] = ((cval >> 3) & 1) + 9;
2110 else
2111 ucontrol->value.enumerated.item[0] = 0;
2112 return 0;
2113}
2114
6ca308d4
TI		 2115static int snd_ice1712_pro_route_spdif_put(struct snd_kcontrol *kcontrol,
2116 struct snd_ctl_elem_value *ucontrol)
1da177e4 2117{
6ca308d4 2118 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2119 int change, shift;
2120 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2121 unsigned int val, old_val, nval;
3d8cb466 2122
1da177e4
LT		 2123 /* update SPDOUT */
2124 spin_lock_irq(&ice->reg_lock);
2125 val = old_val = inw(ICEMT(ice, ROUTE_SPDOUT));
2126 if (ucontrol->value.enumerated.item[0] >= 11)
2127 nval = 1;
2128 else if (ucontrol->value.enumerated.item[0] >= 9)
2129 nval = 3;
2130 else if (ucontrol->value.enumerated.item[0] >= 1)
2131 nval = 2;
2132 else
2133 nval = 0;
2134 shift = idx * 2;
2135 val &= ~(0x03 << shift);
2136 val |= nval << shift;
2137 shift = idx * 4 + 8;
2138 if (nval == 2) {
2139 nval = ucontrol->value.enumerated.item[0] - 1;
2140 val &= ~(0x07 << shift);
2141 val |= nval << shift;
2142 } else if (nval == 3) {
2143 nval = (ucontrol->value.enumerated.item[0] - 9) << 3;
2144 val &= ~(0x08 << shift);
2145 val |= nval << shift;
2146 }
2147 change = val != old_val;
2148 if (change)
2149 outw(val, ICEMT(ice, ROUTE_SPDOUT));
2150 spin_unlock_irq(&ice->reg_lock);
2151 return change;
2152}
2153
6ba1ad38 2154static const struct snd_kcontrol_new snd_ice1712_mixer_pro_analog_route = {
1da177e4
LT		 2155 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2156 .name = "H/W Playback Route",
2157 .info = snd_ice1712_pro_route_info,
2158 .get = snd_ice1712_pro_route_analog_get,
2159 .put = snd_ice1712_pro_route_analog_put,
2160};
2161
f3b827e0 2162static const struct snd_kcontrol_new snd_ice1712_mixer_pro_spdif_route = {
1da177e4 2163 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3d8cb466 2164 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, NONE) "Route",
1da177e4
LT		 2165 .info = snd_ice1712_pro_route_info,
2166 .get = snd_ice1712_pro_route_spdif_get,
2167 .put = snd_ice1712_pro_route_spdif_put,
2168 .count = 2,
2169};
2170
2171
6ca308d4
TI		 2172static int snd_ice1712_pro_volume_rate_info(struct snd_kcontrol *kcontrol,
2173 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 2174{
2175 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2176 uinfo->count = 1;
2177 uinfo->value.integer.min = 0;
2178 uinfo->value.integer.max = 255;
2179 return 0;
2180}
2181
6ca308d4
TI		 2182static int snd_ice1712_pro_volume_rate_get(struct snd_kcontrol *kcontrol,
2183 struct snd_ctl_elem_value *ucontrol)
1da177e4 2184{
6ca308d4 2185 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
3d8cb466 2186
1da177e4
LT		 2187 ucontrol->value.integer.value[0] = inb(ICEMT(ice, MONITOR_RATE));
2188 return 0;
2189}
2190
6ca308d4
TI		 2191static int snd_ice1712_pro_volume_rate_put(struct snd_kcontrol *kcontrol,
2192 struct snd_ctl_elem_value *ucontrol)
1da177e4 2193{
6ca308d4 2194 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2195 int change;
2196
2197 spin_lock_irq(&ice->reg_lock);
2198 change = inb(ICEMT(ice, MONITOR_RATE)) != ucontrol->value.integer.value[0];
2199 outb(ucontrol->value.integer.value[0], ICEMT(ice, MONITOR_RATE));
2200 spin_unlock_irq(&ice->reg_lock);
2201 return change;
2202}
2203
f3b827e0 2204static const struct snd_kcontrol_new snd_ice1712_mixer_pro_volume_rate = {
1da177e4
LT		 2205 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2206 .name = "Multi Track Volume Rate",
2207 .info = snd_ice1712_pro_volume_rate_info,
2208 .get = snd_ice1712_pro_volume_rate_get,
2209 .put = snd_ice1712_pro_volume_rate_put
2210};
2211
6ca308d4
TI		 2212static int snd_ice1712_pro_peak_info(struct snd_kcontrol *kcontrol,
2213 struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 2214{
2215 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2216 uinfo->count = 22;
2217 uinfo->value.integer.min = 0;
2218 uinfo->value.integer.max = 255;
2219 return 0;
2220}
2221
6ca308d4
TI		 2222static int snd_ice1712_pro_peak_get(struct snd_kcontrol *kcontrol,
2223 struct snd_ctl_elem_value *ucontrol)
1da177e4 2224{
6ca308d4 2225 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
1da177e4 2226 int idx;
3d8cb466 2227
1da177e4
LT		 2228 spin_lock_irq(&ice->reg_lock);
2229 for (idx = 0; idx < 22; idx++) {
2230 outb(idx, ICEMT(ice, MONITOR_PEAKINDEX));
2231 ucontrol->value.integer.value[idx] = inb(ICEMT(ice, MONITOR_PEAKDATA));
2232 }
2233 spin_unlock_irq(&ice->reg_lock);
2234 return 0;
2235}
2236
f3b827e0 2237static const struct snd_kcontrol_new snd_ice1712_mixer_pro_peak = {
2bdf6633 2238 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1da177e4
LT		 2239 .name = "Multi Track Peak",
2240 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
2241 .info = snd_ice1712_pro_peak_info,
2242 .get = snd_ice1712_pro_peak_get
2243};
2244
2245/*
2246 *
2247 */
2248
2249/*
2250 * list of available boards
2251 */
e23e7a14 2252static struct snd_ice1712_card_info *card_tables[] = {
1da177e4
LT		 2253 snd_ice1712_hoontech_cards,
2254 snd_ice1712_delta_cards,
2255 snd_ice1712_ews_cards,
2256 NULL,
2257};
2258
e23e7a14
BP		 2259static unsigned char snd_ice1712_read_i2c(struct snd_ice1712 *ice,
2260 unsigned char dev,
2261 unsigned char addr)
1da177e4
LT		 2262{
2263 long t = 0x10000;
2264
2265 outb(addr, ICEREG(ice, I2C_BYTE_ADDR));
2266 outb(dev & ~ICE1712_I2C_WRITE, ICEREG(ice, I2C_DEV_ADDR));
2267 while (t-- > 0 && (inb(ICEREG(ice, I2C_CTRL)) & ICE1712_I2C_BUSY)) ;
2268 return inb(ICEREG(ice, I2C_DATA));
2269}
2270
e23e7a14
BP		 2271static int snd_ice1712_read_eeprom(struct snd_ice1712 *ice,
2272 const char *modelname)
1da177e4 2273{
9718a29d 2274 int dev = ICE_I2C_EEPROM_ADDR; /* I2C EEPROM device address */
1da177e4 2275 unsigned int i, size;
bf748ed7 2276 struct snd_ice1712_card_info * const *tbl, *c;
1da177e4 2277
3d8cb466 2278 if (!modelname || !*modelname) {
1da177e4
LT		 2279 ice->eeprom.subvendor = 0;
2280 if ((inb(ICEREG(ice, I2C_CTRL)) & ICE1712_I2C_EEPROM) != 0)
2281 ice->eeprom.subvendor = (snd_ice1712_read_i2c(ice, dev, 0x00) << 0) |
3d8cb466
AB		 2282 (snd_ice1712_read_i2c(ice, dev, 0x01) << 8) |
2283 (snd_ice1712_read_i2c(ice, dev, 0x02) << 16) |
1da177e4 2284 (snd_ice1712_read_i2c(ice, dev, 0x03) << 24);
6ca308d4
TI		 2285 if (ice->eeprom.subvendor == 0 ||
2286 ice->eeprom.subvendor == (unsigned int)-1) {
1da177e4
LT		 2287 /* invalid subvendor from EEPROM, try the PCI subststem ID instead */
2288 u16 vendor, device;
2289 pci_read_config_word(ice->pci, PCI_SUBSYSTEM_VENDOR_ID, &vendor);
2290 pci_read_config_word(ice->pci, PCI_SUBSYSTEM_ID, &device);
2291 ice->eeprom.subvendor = ((unsigned int)swab16(vendor) << 16) | swab16(device);
2292 if (ice->eeprom.subvendor == 0 || ice->eeprom.subvendor == (unsigned int)-1) {
6dfb5aff
TI		 2293 dev_err(ice->card->dev,
2294 "No valid ID is found\n");
1da177e4
LT		 2295 return -ENXIO;
2296 }
2297 }
2298 }
2299 for (tbl = card_tables; *tbl; tbl++) {
2300 for (c = *tbl; c->subvendor; c++) {
3d8cb466 2301 if (modelname && c->model && !strcmp(modelname, c->model)) {
6dfb5aff
TI		 2302 dev_info(ice->card->dev,
2303 "Using board model %s\n", c->name);
1da177e4
LT		 2304 ice->eeprom.subvendor = c->subvendor;
2305 } else if (c->subvendor != ice->eeprom.subvendor)
2306 continue;
3d8cb466 2307 if (!c->eeprom_size || !c->eeprom_data)
1da177e4
LT		 2308 goto found;
2309 /* if the EEPROM is given by the driver, use it */
6dfb5aff 2310 dev_dbg(ice->card->dev, "using the defined eeprom..\n");
1da177e4
LT		 2311 ice->eeprom.version = 1;
2312 ice->eeprom.size = c->eeprom_size + 6;
2313 memcpy(ice->eeprom.data, c->eeprom_data, c->eeprom_size);
2314 goto read_skipped;
2315 }
2316 }
6dfb5aff 2317 dev_warn(ice->card->dev, "No matching model found for ID 0x%x\n",
6ca308d4 2318 ice->eeprom.subvendor);
1da177e4
LT		 2319
2320 found:
2321 ice->eeprom.size = snd_ice1712_read_i2c(ice, dev, 0x04);
2322 if (ice->eeprom.size < 6)
2323 ice->eeprom.size = 32; /* FIXME: any cards without the correct size? */
2324 else if (ice->eeprom.size > 32) {
6dfb5aff
TI		 2325 dev_err(ice->card->dev,
2326 "invalid EEPROM (size = %i)\n", ice->eeprom.size);
1da177e4
LT		 2327 return -EIO;
2328 }
2329 ice->eeprom.version = snd_ice1712_read_i2c(ice, dev, 0x05);
2330 if (ice->eeprom.version != 1) {
6dfb5aff 2331 dev_err(ice->card->dev, "invalid EEPROM version %i\n",
6ca308d4 2332 ice->eeprom.version);
1da177e4
LT		 2333 /* return -EIO; */
2334 }
2335 size = ice->eeprom.size - 6;
2336 for (i = 0; i < size; i++)
2337 ice->eeprom.data[i] = snd_ice1712_read_i2c(ice, dev, i + 6);
2338
2339 read_skipped:
2340 ice->eeprom.gpiomask = ice->eeprom.data[ICE_EEP1_GPIO_MASK];
2341 ice->eeprom.gpiostate = ice->eeprom.data[ICE_EEP1_GPIO_STATE];
2342 ice->eeprom.gpiodir = ice->eeprom.data[ICE_EEP1_GPIO_DIR];
2343
2344 return 0;
2345}
2346
2347
2348
e23e7a14 2349static int snd_ice1712_chip_init(struct snd_ice1712 *ice)
1da177e4
LT		 2350{
2351 outb(ICE1712_RESET | ICE1712_NATIVE, ICEREG(ice, CONTROL));
2352 udelay(200);
2353 outb(ICE1712_NATIVE, ICEREG(ice, CONTROL));
2354 udelay(200);
721b8a29
AH		 2355 if (ice->eeprom.subvendor == ICE1712_SUBDEVICE_DMX6FIRE &&
2356 !ice->dxr_enable)
2357 /* Set eeprom value to limit active ADCs and DACs to 6;
2358 * Also disable AC97 as no hardware in standard 6fire card/box
2359 * Note: DXR extensions are not currently supported
2360 */
2361 ice->eeprom.data[ICE_EEP1_CODEC] = 0x3a;
2362 pci_write_config_byte(ice->pci, 0x60, ice->eeprom.data[ICE_EEP1_CODEC]);
1da177e4
LT		 2363 pci_write_config_byte(ice->pci, 0x61, ice->eeprom.data[ICE_EEP1_ACLINK]);
2364 pci_write_config_byte(ice->pci, 0x62, ice->eeprom.data[ICE_EEP1_I2SID]);
2365 pci_write_config_byte(ice->pci, 0x63, ice->eeprom.data[ICE_EEP1_SPDIF]);
2366 if (ice->eeprom.subvendor != ICE1712_SUBDEVICE_STDSP24) {
2367 ice->gpio.write_mask = ice->eeprom.gpiomask;
2368 ice->gpio.direction = ice->eeprom.gpiodir;
6ca308d4
TI		 2369 snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK,
2370 ice->eeprom.gpiomask);
2371 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION,
2372 ice->eeprom.gpiodir);
2373 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA,
2374 ice->eeprom.gpiostate);
1da177e4
LT		 2375 } else {
2376 ice->gpio.write_mask = 0xc0;
2377 ice->gpio.direction = 0xff;
2378 snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK, 0xc0);
2379 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION, 0xff);
6ca308d4
TI		 2380 snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA,
2381 ICE1712_STDSP24_CLOCK_BIT);
1da177e4
LT		 2382 }
2383 snd_ice1712_write(ice, ICE1712_IREG_PRO_POWERDOWN, 0);
2384 if (!(ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_NO_CON_AC97)) {
2385 outb(ICE1712_AC97_WARM, ICEREG(ice, AC97_CMD));
2386 udelay(100);
2387 outb(0, ICEREG(ice, AC97_CMD));
2388 udelay(200);
2389 snd_ice1712_write(ice, ICE1712_IREG_CONSUMER_POWERDOWN, 0);
2390 }
2391 snd_ice1712_set_pro_rate(ice, 48000, 1);
ca051e8a
OZ		 2392 /* unmask used interrupts */
2393 outb(((ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_2xMPU401) == 0 ?
2394 ICE1712_IRQ_MPU2 : 0) |
2395 ((ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_NO_CON_AC97) ?
2396 ICE1712_IRQ_PBKDS | ICE1712_IRQ_CONCAP | ICE1712_IRQ_CONPBK : 0),
2397 ICEREG(ice, IRQMASK));
2398 outb(0x00, ICEMT(ice, IRQ));
1da177e4
LT		 2399
2400 return 0;
2401}
2402
e23e7a14 2403int snd_ice1712_spdif_build_controls(struct snd_ice1712 *ice)
1da177e4
LT		 2404{
2405 int err;
6ca308d4 2406 struct snd_kcontrol *kctl;
1da177e4 2407
da3cec35
TI		 2408 if (snd_BUG_ON(!ice->pcm_pro))
2409 return -EIO;
1da177e4
LT		 2410 err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_default, ice));
2411 if (err < 0)
2412 return err;
2413 kctl->id.device = ice->pcm_pro->device;
2414 err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_maskc, ice));
2415 if (err < 0)
2416 return err;
2417 kctl->id.device = ice->pcm_pro->device;
2418 err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_maskp, ice));
2419 if (err < 0)
2420 return err;
2421 kctl->id.device = ice->pcm_pro->device;
2422 err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_stream, ice));
2423 if (err < 0)
2424 return err;
2425 kctl->id.device = ice->pcm_pro->device;
2426 ice->spdif.stream_ctl = kctl;
2427 return 0;
2428}
2429
2430
e23e7a14 2431static int snd_ice1712_build_controls(struct snd_ice1712 *ice)
1da177e4
LT		 2432{
2433 int err;
2434
2435 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_eeprom, ice));
2436 if (err < 0)
2437 return err;
2438 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_internal_clock, ice));
2439 if (err < 0)
2440 return err;
2441 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_internal_clock_default, ice));
2442 if (err < 0)
2443 return err;
2444
2445 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_rate_locking, ice));
2446 if (err < 0)
2447 return err;
2448 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_rate_reset, ice));
2449 if (err < 0)
2450 return err;
2451
2452 if (ice->num_total_dacs > 0) {
6ca308d4 2453 struct snd_kcontrol_new tmp = snd_ice1712_mixer_pro_analog_route;
1da177e4
LT		 2454 tmp.count = ice->num_total_dacs;
2455 err = snd_ctl_add(ice->card, snd_ctl_new1(&tmp, ice));
2456 if (err < 0)
2457 return err;
2458 }
2459
2460 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_pro_spdif_route, ice));
2461 if (err < 0)
2462 return err;
2463
2464 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_pro_volume_rate, ice));
2465 if (err < 0)
2466 return err;
387417b5
SM		 2467 return snd_ctl_add(ice->card,
2468 snd_ctl_new1(&snd_ice1712_mixer_pro_peak, ice));
1da177e4
LT		 2469}
2470
6ca308d4 2471static int snd_ice1712_free(struct snd_ice1712 *ice)
1da177e4 2472{
3d8cb466 2473 if (!ice->port)
1da177e4
LT		 2474 goto __hw_end;
2475 /* mask all interrupts */
890b13a3 2476 outb(ICE1712_MULTI_CAPTURE | ICE1712_MULTI_PLAYBACK, ICEMT(ice, IRQ));
1da177e4
LT		 2477 outb(0xff, ICEREG(ice, IRQMASK));
2478 /* --- */
3d8cb466 2479__hw_end:
f000fd80 2480 if (ice->irq >= 0)
6ca308d4 2481 free_irq(ice->irq, ice);
f000fd80 2482
1da177e4
LT		 2483 if (ice->port)
2484 pci_release_regions(ice->pci);
2485 snd_ice1712_akm4xxx_free(ice);
2486 pci_disable_device(ice->pci);
7cda8ba9 2487 kfree(ice->spec);
1da177e4
LT		 2488 kfree(ice);
2489 return 0;
2490}
2491
6ca308d4 2492static int snd_ice1712_dev_free(struct snd_device *device)
1da177e4 2493{
6ca308d4 2494 struct snd_ice1712 *ice = device->device_data;
1da177e4
LT		 2495 return snd_ice1712_free(ice);
2496}
2497
e23e7a14
BP		 2498static int snd_ice1712_create(struct snd_card *card,
2499 struct pci_dev *pci,
2500 const char *modelname,
2501 int omni,
2502 int cs8427_timeout,
2503 int dxr_enable,
2504 struct snd_ice1712 **r_ice1712)
1da177e4 2505{
6ca308d4 2506 struct snd_ice1712 *ice;
1da177e4 2507 int err;
6ca308d4 2508 static struct snd_device_ops ops = {
1da177e4
LT		 2509 .dev_free = snd_ice1712_dev_free,
2510 };
2511
2512 *r_ice1712 = NULL;
2513
3d8cb466
AB		 2514 /* enable PCI device */
2515 err = pci_enable_device(pci);
2516 if (err < 0)
1da177e4
LT		 2517 return err;
2518 /* check, if we can restrict PCI DMA transfers to 28 bits */
412b979c
QL		 2519 if (dma_set_mask(&pci->dev, DMA_BIT_MASK(28)) < 0 ||
2520 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(28)) < 0) {
6dfb5aff
TI		 2521 dev_err(card->dev,
2522 "architecture does not support 28bit PCI busmaster DMA\n");
1da177e4
LT		 2523 pci_disable_device(pci);
2524 return -ENXIO;
2525 }
2526
e560d8d8 2527 ice = kzalloc(sizeof(*ice), GFP_KERNEL);
1da177e4
LT		 2528 if (ice == NULL) {
2529 pci_disable_device(pci);
2530 return -ENOMEM;
2531 }
2532 ice->omni = omni ? 1 : 0;
2533 if (cs8427_timeout < 1)
2534 cs8427_timeout = 1;
2535 else if (cs8427_timeout > 1000)
2536 cs8427_timeout = 1000;
2537 ice->cs8427_timeout = cs8427_timeout;
531af462 2538 ice->dxr_enable = dxr_enable;
1da177e4 2539 spin_lock_init(&ice->reg_lock);
62932df8
IM		 2540 mutex_init(&ice->gpio_mutex);
2541 mutex_init(&ice->i2c_mutex);
2542 mutex_init(&ice->open_mutex);
1da177e4 2543 ice->gpio.set_mask = snd_ice1712_set_gpio_mask;
49470306 2544 ice->gpio.get_mask = snd_ice1712_get_gpio_mask;
1da177e4 2545 ice->gpio.set_dir = snd_ice1712_set_gpio_dir;
49470306 2546 ice->gpio.get_dir = snd_ice1712_get_gpio_dir;
1da177e4
LT		 2547 ice->gpio.set_data = snd_ice1712_set_gpio_data;
2548 ice->gpio.get_data = snd_ice1712_get_gpio_data;
2549
2550 ice->spdif.cs8403_bits =
2551 ice->spdif.cs8403_stream_bits = (0x01 | /* consumer format */
2552 0x10 | /* no emphasis */
2553 0x20); /* PCM encoder/decoder */
2554 ice->card = card;
2555 ice->pci = pci;
2556 ice->irq = -1;
2557 pci_set_master(pci);
ca051e8a 2558 /* disable legacy emulation */
1da177e4
LT		 2559 pci_write_config_word(ice->pci, 0x40, 0x807f);
2560 pci_write_config_word(ice->pci, 0x42, 0x0006);
2561 snd_ice1712_proc_init(ice);
2562 synchronize_irq(pci->irq);
2563
69a4cfdd
SC		 2564 card->private_data = ice;
2565
3d8cb466
AB		 2566 err = pci_request_regions(pci, "ICE1712");
2567 if (err < 0) {
1da177e4
LT		 2568 kfree(ice);
2569 pci_disable_device(pci);
2570 return err;
2571 }
2572 ice->port = pci_resource_start(pci, 0);
2573 ice->ddma_port = pci_resource_start(pci, 1);
2574 ice->dmapath_port = pci_resource_start(pci, 2);
2575 ice->profi_port = pci_resource_start(pci, 3);
2576
437a5a46 2577 if (request_irq(pci->irq, snd_ice1712_interrupt, IRQF_SHARED,
934c2b6d 2578 KBUILD_MODNAME, ice)) {
6dfb5aff 2579 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
1da177e4
LT		 2580 snd_ice1712_free(ice);
2581 return -EIO;
2582 }
3d8cb466 2583
1da177e4
LT		 2584 ice->irq = pci->irq;
2585
2586 if (snd_ice1712_read_eeprom(ice, modelname) < 0) {
2587 snd_ice1712_free(ice);
2588 return -EIO;
2589 }
2590 if (snd_ice1712_chip_init(ice) < 0) {
2591 snd_ice1712_free(ice);
2592 return -EIO;
2593 }
2594
3d8cb466
AB		 2595 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ice, &ops);
2596 if (err < 0) {
1da177e4 2597 snd_ice1712_free(ice);
3d8cb466 2598 return err;
1da177e4
LT		 2599 }
2600
1da177e4
LT		 2601 *r_ice1712 = ice;
2602 return 0;
2603}
2604
2605
2606/*
2607 *
2608 * Registration
2609 *
2610 */
2611
e23e7a14 2612static struct snd_ice1712_card_info no_matched;
1da177e4 2613
e23e7a14
BP		 2614static int snd_ice1712_probe(struct pci_dev *pci,
2615 const struct pci_device_id *pci_id)
1da177e4
LT		 2616{
2617 static int dev;
6ca308d4
TI		 2618 struct snd_card *card;
2619 struct snd_ice1712 *ice;
1da177e4 2620 int pcm_dev = 0, err;
bf748ed7 2621 struct snd_ice1712_card_info * const *tbl, *c;
1da177e4
LT		 2622
2623 if (dev >= SNDRV_CARDS)
2624 return -ENODEV;
2625 if (!enable[dev]) {
2626 dev++;
2627 return -ENOENT;
2628 }
2629
60c5772b
TI		 2630 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2631 0, &card);
e58de7ba
TI		 2632 if (err < 0)
2633 return err;
1da177e4
LT		 2634
2635 strcpy(card->driver, "ICE1712");
2636 strcpy(card->shortname, "ICEnsemble ICE1712");
3d8cb466
AB		 2637
2638 err = snd_ice1712_create(card, pci, model[dev], omni[dev],
2639 cs8427_timeout[dev], dxr_enable[dev], &ice);
2640 if (err < 0) {
1da177e4
LT		 2641 snd_card_free(card);
2642 return err;
2643 }
2644
2645 for (tbl = card_tables; *tbl; tbl++) {
2646 for (c = *tbl; c->subvendor; c++) {
2647 if (c->subvendor == ice->eeprom.subvendor) {
267bccaf 2648 ice->card_info = c;
1da177e4
LT		 2649 strcpy(card->shortname, c->name);
2650 if (c->driver) /* specific driver? */
2651 strcpy(card->driver, c->driver);
2652 if (c->chip_init) {
3d8cb466
AB		 2653 err = c->chip_init(ice);
2654 if (err < 0) {
1da177e4
LT		 2655 snd_card_free(card);
2656 return err;
2657 }
2658 }
2659 goto __found;
2660 }
2661 }
2662 }
2663 c = &no_matched;
2664 __found:
2665
08a4c10b 2666 err = snd_ice1712_pcm_profi(ice, pcm_dev++);
3d8cb466 2667 if (err < 0) {
1da177e4
LT		 2668 snd_card_free(card);
2669 return err;
2670 }
3d8cb466 2671
8cd2b264 2672 if (ice_has_con_ac97(ice)) {
08a4c10b 2673 err = snd_ice1712_pcm(ice, pcm_dev++);
3d8cb466 2674 if (err < 0) {
1da177e4
LT		 2675 snd_card_free(card);
2676 return err;
2677 }
8cd2b264 2678 }
1da177e4 2679
3d8cb466
AB		 2680 err = snd_ice1712_ac97_mixer(ice);
2681 if (err < 0) {
1da177e4
LT		 2682 snd_card_free(card);
2683 return err;
2684 }
2685
3d8cb466
AB		 2686 err = snd_ice1712_build_controls(ice);
2687 if (err < 0) {
1da177e4
LT		 2688 snd_card_free(card);
2689 return err;
2690 }
2691
2692 if (c->build_controls) {
3d8cb466
AB		 2693 err = c->build_controls(ice);
2694 if (err < 0) {
1da177e4
LT		 2695 snd_card_free(card);
2696 return err;
2697 }
2698 }
2699
8cd2b264 2700 if (ice_has_con_ac97(ice)) {
08a4c10b 2701 err = snd_ice1712_pcm_ds(ice, pcm_dev++);
3d8cb466 2702 if (err < 0) {
1da177e4
LT		 2703 snd_card_free(card);
2704 return err;
2705 }
8cd2b264 2706 }
1da177e4 2707
3d8cb466
AB		 2708 if (!c->no_mpu401) {
2709 err = snd_mpu401_uart_new(card, 0, MPU401_HW_ICE1712,
2710 ICEREG(ice, MPU1_CTRL),
dba8b469
CL		 2711 c->mpu401_1_info_flags |
2712 MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK,
2713 -1, &ice->rmidi[0]);
3d8cb466 2714 if (err < 0) {
1da177e4
LT		 2715 snd_card_free(card);
2716 return err;
2717 }
3bef229e 2718 if (c->mpu401_1_name)
25985edc 2719 /* Preferred name available in card_info */
3bef229e
AH		 2720 snprintf(ice->rmidi[0]->name,
2721 sizeof(ice->rmidi[0]->name),
2722 "%s %d", c->mpu401_1_name, card->number);
2723
2724 if (ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_2xMPU401) {
2725 /* 2nd port used */
3d8cb466
AB		 2726 err = snd_mpu401_uart_new(card, 1, MPU401_HW_ICE1712,
2727 ICEREG(ice, MPU2_CTRL),
dba8b469
CL		 2728 c->mpu401_2_info_flags |
2729 MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK,
2730 -1, &ice->rmidi[1]);
3d8cb466
AB		 2731
2732 if (err < 0) {
1da177e4
LT		 2733 snd_card_free(card);
2734 return err;
2735 }
3bef229e 2736 if (c->mpu401_2_name)
25985edc 2737 /* Preferred name available in card_info */
3bef229e
AH		 2738 snprintf(ice->rmidi[1]->name,
2739 sizeof(ice->rmidi[1]->name),
2740 "%s %d", c->mpu401_2_name,
2741 card->number);
2742 }
1da177e4
LT		 2743 }
2744
e957ebf1
JK		 2745 snd_ice1712_set_input_clock_source(ice, 0);
2746
1da177e4
LT		 2747 sprintf(card->longname, "%s at 0x%lx, irq %i",
2748 card->shortname, ice->port, ice->irq);
2749
3d8cb466
AB		 2750 err = snd_card_register(card);
2751 if (err < 0) {
1da177e4
LT		 2752 snd_card_free(card);
2753 return err;
2754 }
2755 pci_set_drvdata(pci, card);
2756 dev++;
2757 return 0;
2758}
2759
e23e7a14 2760static void snd_ice1712_remove(struct pci_dev *pci)
1da177e4 2761{
267bccaf
OZ		 2762 struct snd_card *card = pci_get_drvdata(pci);
2763 struct snd_ice1712 *ice = card->private_data;
2764
2765 if (ice->card_info && ice->card_info->chip_exit)
2766 ice->card_info->chip_exit(ice);
2767 snd_card_free(card);
1da177e4
LT		 2768}
2769
ca051e8a
OZ		 2770#ifdef CONFIG_PM_SLEEP
2771static int snd_ice1712_suspend(struct device *dev)
2772{
ca051e8a
OZ		 2773 struct snd_card *card = dev_get_drvdata(dev);
2774 struct snd_ice1712 *ice = card->private_data;
2775
2776 if (!ice->pm_suspend_enabled)
2777 return 0;
2778
2779 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2780
ca051e8a
OZ		 2781 snd_ac97_suspend(ice->ac97);
2782
6ea0cae7
OZ		 2783 spin_lock_irq(&ice->reg_lock);
2784 ice->pm_saved_is_spdif_master = is_spdif_master(ice);
2785 ice->pm_saved_spdif_ctrl = inw(ICEMT(ice, ROUTE_SPDOUT));
2786 ice->pm_saved_route = inw(ICEMT(ice, ROUTE_PSDOUT03));
2787 spin_unlock_irq(&ice->reg_lock);
2788
ca051e8a
OZ		 2789 if (ice->pm_suspend)
2790 ice->pm_suspend(ice);
ca051e8a
OZ		 2791 return 0;
2792}
2793
2794static int snd_ice1712_resume(struct device *dev)
2795{
ca051e8a
OZ		 2796 struct snd_card *card = dev_get_drvdata(dev);
2797 struct snd_ice1712 *ice = card->private_data;
6ea0cae7 2798 int rate;
ca051e8a
OZ		 2799
2800 if (!ice->pm_suspend_enabled)
2801 return 0;
2802
6ea0cae7
OZ		 2803 if (ice->cur_rate)
2804 rate = ice->cur_rate;
2805 else
2806 rate = PRO_RATE_DEFAULT;
2807
ca051e8a
OZ		 2808 if (snd_ice1712_chip_init(ice) < 0) {
2809 snd_card_disconnect(card);
2810 return -EIO;
2811 }
2812
6ea0cae7
OZ		 2813 ice->cur_rate = rate;
2814
ca051e8a
OZ		 2815 if (ice->pm_resume)
2816 ice->pm_resume(ice);
2817
6ea0cae7
OZ		 2818 if (ice->pm_saved_is_spdif_master) {
2819 /* switching to external clock via SPDIF */
2820 spin_lock_irq(&ice->reg_lock);
2821 outb(inb(ICEMT(ice, RATE)) | ICE1712_SPDIF_MASTER,
2822 ICEMT(ice, RATE));
2823 spin_unlock_irq(&ice->reg_lock);
2824 snd_ice1712_set_input_clock_source(ice, 1);
2825 } else {
2826 /* internal on-card clock */
2827 snd_ice1712_set_pro_rate(ice, rate, 1);
2828 snd_ice1712_set_input_clock_source(ice, 0);
2829 }
2830
2831 outw(ice->pm_saved_spdif_ctrl, ICEMT(ice, ROUTE_SPDOUT));
2832 outw(ice->pm_saved_route, ICEMT(ice, ROUTE_PSDOUT03));
2833
ae1b2265 2834 snd_ac97_resume(ice->ac97);
ca051e8a
OZ		 2835
2836 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2837 return 0;
2838}
2839
2840static SIMPLE_DEV_PM_OPS(snd_ice1712_pm, snd_ice1712_suspend, snd_ice1712_resume);
2841#define SND_VT1712_PM_OPS &snd_ice1712_pm
2842#else
2843#define SND_VT1712_PM_OPS NULL
2844#endif /* CONFIG_PM_SLEEP */
2845
e9f66d9b 2846static struct pci_driver ice1712_driver = {
3733e424 2847 .name = KBUILD_MODNAME,
1da177e4
LT		 2848 .id_table = snd_ice1712_ids,
2849 .probe = snd_ice1712_probe,
e23e7a14 2850 .remove = snd_ice1712_remove,
ca051e8a
OZ		 2851 .driver = {
2852 .pm = SND_VT1712_PM_OPS,
2853 },
1da177e4
LT		 2854};
2855
e9f66d9b 2856module_pci_driver(ice1712_driver);
Linux 6.x block layer and io_uring tree(s)