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ALSA: hda: hdmi - fix port numbering for ICL and TGL platforms
[linux-2.6-block.git] / sound / pci / hda / patch_hdmi.c
CommitLineData
1a59d1b8 1// SPDX-License-Identifier: GPL-2.0-or-later
079d88cc
WF		 2/*
3 *
4 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
5 *
6 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
84eb01be
TI		 7 * Copyright (c) 2006 ATI Technologies Inc.
8 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
9 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
5a613584 10 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
079d88cc
WF		 11 *
12 * Authors:
13 * Wu Fengguang <wfg@linux.intel.com>
14 *
15 * Maintained by:
16 * Wu Fengguang <wfg@linux.intel.com>
079d88cc
WF		 17 */
18
84eb01be
TI		 19#include <linux/init.h>
20#include <linux/delay.h>
ade49db3 21#include <linux/pci.h>
84eb01be 22#include <linux/slab.h>
65a77217 23#include <linux/module.h>
aaa23f86 24#include <linux/pm_runtime.h>
84eb01be 25#include <sound/core.h>
07acecc1 26#include <sound/jack.h>
433968da 27#include <sound/asoundef.h>
d45e6889 28#include <sound/tlv.h>
25adc137
DH		 29#include <sound/hdaudio.h>
30#include <sound/hda_i915.h>
67b90cb8 31#include <sound/hda_chmap.h>
be57bfff 32#include <sound/hda_codec.h>
84eb01be 33#include "hda_local.h"
1835a0f9 34#include "hda_jack.h"
84eb01be 35
0ebaa24c
TI		 36static bool static_hdmi_pcm;
37module_param(static_hdmi_pcm, bool, 0644);
38MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
39
384a48d7
SW		 40struct hdmi_spec_per_cvt {
41 hda_nid_t cvt_nid;
42 int assigned;
43 unsigned int channels_min;
44 unsigned int channels_max;
45 u32 rates;
46 u64 formats;
47 unsigned int maxbps;
48};
079d88cc 49
4eea3091
TI		 50/* max. connections to a widget */
51#define HDA_MAX_CONNECTIONS 32
52
384a48d7
SW		 53struct hdmi_spec_per_pin {
54 hda_nid_t pin_nid;
9152085d 55 int dev_id;
a76056f2
LY		 56 /* pin idx, different device entries on the same pin use the same idx */
57 int pin_nid_idx;
384a48d7
SW		 58 int num_mux_nids;
59 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
2df6742f 60 int mux_idx;
1df5a06a 61 hda_nid_t cvt_nid;
744626da
WF		 62
63 struct hda_codec *codec;
384a48d7 64 struct hdmi_eld sink_eld;
a4e9a38b 65 struct mutex lock;
744626da 66 struct delayed_work work;
2bea241a 67 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
a76056f2 68 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
c6e8453e 69 int repoll_count;
b054087d
TI		 70 bool setup; /* the stream has been set up by prepare callback */
71 int channels; /* current number of channels */
1a6003b5 72 bool non_pcm;
d45e6889
TI		 73 bool chmap_set; /* channel-map override by ALSA API? */
74 unsigned char chmap[8]; /* ALSA API channel-map */
cd6a6503 75#ifdef CONFIG_SND_PROC_FS
a4e9a38b
TI		 76 struct snd_info_entry *proc_entry;
77#endif
384a48d7 78};
079d88cc 79
307229d2
AH		 80/* operations used by generic code that can be overridden by patches */
81struct hdmi_ops {
82 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
83 unsigned char *buf, int *eld_size);
84
307229d2
AH		 85 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
86 int ca, int active_channels, int conn_type);
87
88 /* enable/disable HBR (HD passthrough) */
89 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
90
91 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
92 hda_nid_t pin_nid, u32 stream_tag, int format);
93
4846a67e
TI		 94 void (*pin_cvt_fixup)(struct hda_codec *codec,
95 struct hdmi_spec_per_pin *per_pin,
96 hda_nid_t cvt_nid);
307229d2
AH		 97};
98
2bea241a
LY		 99struct hdmi_pcm {
100 struct hda_pcm *pcm;
101 struct snd_jack *jack;
fb087eaa 102 struct snd_kcontrol *eld_ctl;
2bea241a
LY		 103};
104
384a48d7 105struct hdmi_spec {
ade49db3 106 struct hda_codec *codec;
384a48d7 107 int num_cvts;
bce0d2a8
TI		 108 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
109 hda_nid_t cvt_nids[4]; /* only for haswell fix */
079d88cc 110
9152085d
LY		 111 /*
112 * num_pins is the number of virtual pins
113 * for example, there are 3 pins, and each pin
114 * has 4 device entries, then the num_pins is 12
115 */
384a48d7 116 int num_pins;
9152085d
LY		 117 /*
118 * num_nids is the number of real pins
119 * In the above example, num_nids is 3
120 */
121 int num_nids;
122 /*
123 * dev_num is the number of device entries
124 * on each pin.
125 * In the above example, dev_num is 4
126 */
127 int dev_num;
bce0d2a8 128 struct snd_array pins; /* struct hdmi_spec_per_pin */
2bea241a 129 struct hdmi_pcm pcm_rec[16];
42b29870 130 struct mutex pcm_lock;
302d5a80 131 struct mutex bind_lock; /* for audio component binding */
a76056f2
LY		 132 /* pcm_bitmap means which pcms have been assigned to pins*/
133 unsigned long pcm_bitmap;
2bf3c85a 134 int pcm_used; /* counter of pcm_rec[] */
ac98379a
LY		 135 /* bitmap shows whether the pcm is opened in user space
136 * bit 0 means the first playback PCM (PCM3);
137 * bit 1 means the second playback PCM, and so on.
138 */
139 unsigned long pcm_in_use;
079d88cc 140
4bd038f9 141 struct hdmi_eld temp_eld;
307229d2 142 struct hdmi_ops ops;
75fae117
SW		 143
144 bool dyn_pin_out;
6590faab 145 bool dyn_pcm_assign;
cb45722b 146 bool intel_hsw_fixup; /* apply Intel platform-specific fixups */
079d88cc 147 /*
5a613584 148 * Non-generic VIA/NVIDIA specific
079d88cc
WF		 149 */
150 struct hda_multi_out multiout;
d0b1252d 151 struct hda_pcm_stream pcm_playback;
25adc137 152
ade49db3
TI		 153 bool use_jack_detect; /* jack detection enabled */
154 bool use_acomp_notifier; /* use eld_notify callback for hotplug */
155 bool acomp_registered; /* audio component registered in this driver */
ae891abe 156 struct drm_audio_component_audio_ops drm_audio_ops;
ade49db3 157 int (*port2pin)(struct hda_codec *, int); /* reverse port/pin mapping */
67b90cb8
SP		 158
159 struct hdac_chmap chmap;
a87a4d23 160 hda_nid_t vendor_nid;
b0d8bc50
JK		 161 const int *port_map;
162 int port_num;
079d88cc
WF		 163};
164
a57942bf 165#ifdef CONFIG_SND_HDA_COMPONENT
691be973
TI		 166static inline bool codec_has_acomp(struct hda_codec *codec)
167{
168 struct hdmi_spec *spec = codec->spec;
169 return spec->use_acomp_notifier;
170}
f4e3040b
TI		 171#else
172#define codec_has_acomp(codec) false
173#endif
079d88cc
WF		 174
175struct hdmi_audio_infoframe {
176 u8 type; /* 0x84 */
177 u8 ver; /* 0x01 */
178 u8 len; /* 0x0a */
179
53d7d69d
WF		 180 u8 checksum;
181
079d88cc
WF		 182 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
183 u8 SS01_SF24;
184 u8 CXT04;
185 u8 CA;
186 u8 LFEPBL01_LSV36_DM_INH7;
53d7d69d
WF		 187};
188
189struct dp_audio_infoframe {
190 u8 type; /* 0x84 */
191 u8 len; /* 0x1b */
192 u8 ver; /* 0x11 << 2 */
193
194 u8 CC02_CT47; /* match with HDMI infoframe from this on */
195 u8 SS01_SF24;
196 u8 CXT04;
197 u8 CA;
198 u8 LFEPBL01_LSV36_DM_INH7;
079d88cc
WF		 199};
200
2b203dbb
TI		 201union audio_infoframe {
202 struct hdmi_audio_infoframe hdmi;
203 struct dp_audio_infoframe dp;
204 u8 bytes[0];
205};
206
079d88cc
WF		 207/*
208 * HDMI routines
209 */
210
bce0d2a8
TI		 211#define get_pin(spec, idx) \
212 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
213#define get_cvt(spec, idx) \
214 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
2bea241a
LY		 215/* obtain hdmi_pcm object assigned to idx */
216#define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx])
217/* obtain hda_pcm object assigned to idx */
218#define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm)
bce0d2a8 219
9152085d
LY		 220static int pin_id_to_pin_index(struct hda_codec *codec,
221 hda_nid_t pin_nid, int dev_id)
079d88cc 222{
4e76a883 223 struct hdmi_spec *spec = codec->spec;
384a48d7 224 int pin_idx;
9152085d 225 struct hdmi_spec_per_pin *per_pin;
079d88cc 226
9152085d
LY		 227 /*
228 * (dev_id == -1) means it is NON-MST pin
229 * return the first virtual pin on this port
230 */
231 if (dev_id == -1)
232 dev_id = 0;
233
234 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
235 per_pin = get_pin(spec, pin_idx);
236 if ((per_pin->pin_nid == pin_nid) &&
237 (per_pin->dev_id == dev_id))
384a48d7 238 return pin_idx;
9152085d 239 }
079d88cc 240
4e76a883 241 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
384a48d7
SW		 242 return -EINVAL;
243}
244
2bf3c85a
LY		 245static int hinfo_to_pcm_index(struct hda_codec *codec,
246 struct hda_pcm_stream *hinfo)
247{
248 struct hdmi_spec *spec = codec->spec;
249 int pcm_idx;
250
251 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
252 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
253 return pcm_idx;
254
255 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
256 return -EINVAL;
257}
258
4e76a883 259static int hinfo_to_pin_index(struct hda_codec *codec,
384a48d7
SW		 260 struct hda_pcm_stream *hinfo)
261{
4e76a883 262 struct hdmi_spec *spec = codec->spec;
6590faab 263 struct hdmi_spec_per_pin *per_pin;
384a48d7
SW		 264 int pin_idx;
265
6590faab
LY		 266 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
267 per_pin = get_pin(spec, pin_idx);
2bea241a
LY		 268 if (per_pin->pcm &&
269 per_pin->pcm->pcm->stream == hinfo)
384a48d7 270 return pin_idx;
6590faab 271 }
384a48d7 272
6590faab 273 codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo);
384a48d7
SW		 274 return -EINVAL;
275}
276
022f344b
LY		 277static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
278 int pcm_idx)
279{
280 int i;
281 struct hdmi_spec_per_pin *per_pin;
282
283 for (i = 0; i < spec->num_pins; i++) {
284 per_pin = get_pin(spec, i);
285 if (per_pin->pcm_idx == pcm_idx)
286 return per_pin;
287 }
288 return NULL;
289}
290
4e76a883 291static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
384a48d7 292{
4e76a883 293 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 294 int cvt_idx;
295
296 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
bce0d2a8 297 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
384a48d7
SW		 298 return cvt_idx;
299
4e76a883 300 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
079d88cc
WF		 301 return -EINVAL;
302}
303
14bc52b8
PLB		 304static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
305 struct snd_ctl_elem_info *uinfo)
306{
307 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9 308 struct hdmi_spec *spec = codec->spec;
a4e9a38b 309 struct hdmi_spec_per_pin *per_pin;
68e03de9 310 struct hdmi_eld *eld;
fb087eaa 311 int pcm_idx;
14bc52b8 312
14bc52b8
PLB		 313 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
314
fb087eaa
LY		 315 pcm_idx = kcontrol->private_value;
316 mutex_lock(&spec->pcm_lock);
317 per_pin = pcm_idx_to_pin(spec, pcm_idx);
318 if (!per_pin) {
319 /* no pin is bound to the pcm */
320 uinfo->count = 0;
f69548ff 321 goto unlock;
fb087eaa 322 }
a4e9a38b 323 eld = &per_pin->sink_eld;
68e03de9 324 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
14bc52b8 325
f69548ff
TI		 326 unlock:
327 mutex_unlock(&spec->pcm_lock);
14bc52b8
PLB		 328 return 0;
329}
330
331static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
332 struct snd_ctl_elem_value *ucontrol)
333{
334 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9 335 struct hdmi_spec *spec = codec->spec;
a4e9a38b 336 struct hdmi_spec_per_pin *per_pin;
68e03de9 337 struct hdmi_eld *eld;
fb087eaa 338 int pcm_idx;
f69548ff 339 int err = 0;
14bc52b8 340
fb087eaa
LY		 341 pcm_idx = kcontrol->private_value;
342 mutex_lock(&spec->pcm_lock);
343 per_pin = pcm_idx_to_pin(spec, pcm_idx);
344 if (!per_pin) {
345 /* no pin is bound to the pcm */
346 memset(ucontrol->value.bytes.data, 0,
347 ARRAY_SIZE(ucontrol->value.bytes.data));
f69548ff 348 goto unlock;
fb087eaa 349 }
68e03de9 350
f69548ff 351 eld = &per_pin->sink_eld;
360a8245
DH		 352 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
353 eld->eld_size > ELD_MAX_SIZE) {
68e03de9 354 snd_BUG();
f69548ff
TI		 355 err = -EINVAL;
356 goto unlock;
68e03de9
DH		 357 }
358
359 memset(ucontrol->value.bytes.data, 0,
360 ARRAY_SIZE(ucontrol->value.bytes.data));
361 if (eld->eld_valid)
362 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
363 eld->eld_size);
14bc52b8 364
f69548ff
TI		 365 unlock:
366 mutex_unlock(&spec->pcm_lock);
367 return err;
14bc52b8
PLB		 368}
369
f3b827e0 370static const struct snd_kcontrol_new eld_bytes_ctl = {
14bc52b8
PLB		 371 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
372 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
373 .name = "ELD",
374 .info = hdmi_eld_ctl_info,
375 .get = hdmi_eld_ctl_get,
376};
377
fb087eaa 378static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
14bc52b8
PLB		 379 int device)
380{
381 struct snd_kcontrol *kctl;
382 struct hdmi_spec *spec = codec->spec;
383 int err;
384
385 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
386 if (!kctl)
387 return -ENOMEM;
fb087eaa 388 kctl->private_value = pcm_idx;
14bc52b8
PLB		 389 kctl->id.device = device;
390
fb087eaa
LY		 391 /* no pin nid is associated with the kctl now
392 * tbd: associate pin nid to eld ctl later
393 */
394 err = snd_hda_ctl_add(codec, 0, kctl);
14bc52b8
PLB		 395 if (err < 0)
396 return err;
397
fb087eaa 398 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
14bc52b8
PLB		 399 return 0;
400}
401
079d88cc
WF		 402#ifdef BE_PARANOID
403static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
404 int *packet_index, int *byte_index)
405{
406 int val;
407
408 val = snd_hda_codec_read(codec, pin_nid, 0,
409 AC_VERB_GET_HDMI_DIP_INDEX, 0);
410
411 *packet_index = val >> 5;
412 *byte_index = val & 0x1f;
413}
414#endif
415
416static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
417 int packet_index, int byte_index)
418{
419 int val;
420
421 val = (packet_index << 5) | (byte_index & 0x1f);
422
423 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
424}
425
426static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
427 unsigned char val)
428{
429 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
430}
431
384a48d7 432static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc 433{
75fae117
SW		 434 struct hdmi_spec *spec = codec->spec;
435 int pin_out;
436
079d88cc
WF		 437 /* Unmute */
438 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
439 snd_hda_codec_write(codec, pin_nid, 0,
440 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
75fae117
SW		 441
442 if (spec->dyn_pin_out)
443 /* Disable pin out until stream is active */
444 pin_out = 0;
445 else
446 /* Enable pin out: some machines with GM965 gets broken output
447 * when the pin is disabled or changed while using with HDMI
448 */
449 pin_out = PIN_OUT;
450
079d88cc 451 snd_hda_codec_write(codec, pin_nid, 0,
75fae117 452 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
079d88cc
WF		 453}
454
a4e9a38b
TI		 455/*
456 * ELD proc files
457 */
458
cd6a6503 459#ifdef CONFIG_SND_PROC_FS
a4e9a38b
TI		 460static void print_eld_info(struct snd_info_entry *entry,
461 struct snd_info_buffer *buffer)
462{
463 struct hdmi_spec_per_pin *per_pin = entry->private_data;
464
465 mutex_lock(&per_pin->lock);
466 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
467 mutex_unlock(&per_pin->lock);
468}
469
470static void write_eld_info(struct snd_info_entry *entry,
471 struct snd_info_buffer *buffer)
472{
473 struct hdmi_spec_per_pin *per_pin = entry->private_data;
474
475 mutex_lock(&per_pin->lock);
476 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
477 mutex_unlock(&per_pin->lock);
478}
479
480static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
481{
482 char name[32];
483 struct hda_codec *codec = per_pin->codec;
484 struct snd_info_entry *entry;
485 int err;
486
487 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
6efdd851 488 err = snd_card_proc_new(codec->card, name, &entry);
a4e9a38b
TI		 489 if (err < 0)
490 return err;
491
492 snd_info_set_text_ops(entry, per_pin, print_eld_info);
493 entry->c.text.write = write_eld_info;
6a73cf46 494 entry->mode |= 0200;
a4e9a38b
TI		 495 per_pin->proc_entry = entry;
496
497 return 0;
498}
499
500static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
501{
1947a114 502 if (!per_pin->codec->bus->shutdown) {
c560a679 503 snd_info_free_entry(per_pin->proc_entry);
a4e9a38b
TI		 504 per_pin->proc_entry = NULL;
505 }
506}
507#else
b55447a7
TI		 508static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
509 int index)
a4e9a38b
TI		 510{
511 return 0;
512}
b55447a7 513static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
a4e9a38b
TI		 514{
515}
516#endif
079d88cc 517
079d88cc
WF		 518/*
519 * Audio InfoFrame routines
520 */
521
522/*
523 * Enable Audio InfoFrame Transmission
524 */
525static void hdmi_start_infoframe_trans(struct hda_codec *codec,
526 hda_nid_t pin_nid)
527{
528 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
529 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
530 AC_DIPXMIT_BEST);
531}
532
533/*
534 * Disable Audio InfoFrame Transmission
535 */
536static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
537 hda_nid_t pin_nid)
538{
539 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
540 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
541 AC_DIPXMIT_DISABLE);
542}
543
544static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
545{
546#ifdef CONFIG_SND_DEBUG_VERBOSE
547 int i;
548 int size;
549
550 size = snd_hdmi_get_eld_size(codec, pin_nid);
4e76a883 551 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
079d88cc
WF		 552
553 for (i = 0; i < 8; i++) {
554 size = snd_hda_codec_read(codec, pin_nid, 0,
555 AC_VERB_GET_HDMI_DIP_SIZE, i);
4e76a883 556 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
079d88cc
WF		 557 }
558#endif
559}
560
561static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
562{
563#ifdef BE_PARANOID
564 int i, j;
565 int size;
566 int pi, bi;
567 for (i = 0; i < 8; i++) {
568 size = snd_hda_codec_read(codec, pin_nid, 0,
569 AC_VERB_GET_HDMI_DIP_SIZE, i);
570 if (size == 0)
571 continue;
572
573 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
574 for (j = 1; j < 1000; j++) {
575 hdmi_write_dip_byte(codec, pin_nid, 0x0);
576 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
577 if (pi != i)
4e76a883 578 codec_dbg(codec, "dip index %d: %d != %d\n",
079d88cc
WF		 579 bi, pi, i);
580 if (bi == 0) /* byte index wrapped around */
581 break;
582 }
4e76a883 583 codec_dbg(codec,
079d88cc
WF		 584 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
585 i, size, j);
586 }
587#endif
588}
589
53d7d69d 590static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
079d88cc 591{
53d7d69d 592 u8 *bytes = (u8 *)hdmi_ai;
079d88cc
WF		 593 u8 sum = 0;
594 int i;
595
53d7d69d 596 hdmi_ai->checksum = 0;
079d88cc 597
53d7d69d 598 for (i = 0; i < sizeof(*hdmi_ai); i++)
079d88cc
WF		 599 sum += bytes[i];
600
53d7d69d 601 hdmi_ai->checksum = -sum;
079d88cc
WF		 602}
603
604static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
605 hda_nid_t pin_nid,
53d7d69d 606 u8 *dip, int size)
079d88cc 607{
079d88cc
WF		 608 int i;
609
610 hdmi_debug_dip_size(codec, pin_nid);
611 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
612
079d88cc 613 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d
WF		 614 for (i = 0; i < size; i++)
615 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
079d88cc
WF		 616}
617
618static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
53d7d69d 619 u8 *dip, int size)
079d88cc 620{
079d88cc
WF		 621 u8 val;
622 int i;
623
624 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
625 != AC_DIPXMIT_BEST)
626 return false;
627
628 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d 629 for (i = 0; i < size; i++) {
079d88cc
WF		 630 val = snd_hda_codec_read(codec, pin_nid, 0,
631 AC_VERB_GET_HDMI_DIP_DATA, 0);
53d7d69d 632 if (val != dip[i])
079d88cc
WF		 633 return false;
634 }
635
636 return true;
637}
638
307229d2
AH		 639static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
640 hda_nid_t pin_nid,
641 int ca, int active_channels,
642 int conn_type)
643{
644 union audio_infoframe ai;
645
caaf5ef9 646 memset(&ai, 0, sizeof(ai));
307229d2
AH		 647 if (conn_type == 0) { /* HDMI */
648 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
649
650 hdmi_ai->type = 0x84;
651 hdmi_ai->ver = 0x01;
652 hdmi_ai->len = 0x0a;
653 hdmi_ai->CC02_CT47 = active_channels - 1;
654 hdmi_ai->CA = ca;
655 hdmi_checksum_audio_infoframe(hdmi_ai);
656 } else if (conn_type == 1) { /* DisplayPort */
657 struct dp_audio_infoframe *dp_ai = &ai.dp;
658
659 dp_ai->type = 0x84;
660 dp_ai->len = 0x1b;
661 dp_ai->ver = 0x11 << 2;
662 dp_ai->CC02_CT47 = active_channels - 1;
663 dp_ai->CA = ca;
664 } else {
4e76a883 665 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
307229d2
AH		 666 pin_nid);
667 return;
668 }
669
670 /*
671 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
672 * sizeof(*dp_ai) to avoid partial match/update problems when
673 * the user switches between HDMI/DP monitors.
674 */
675 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
676 sizeof(ai))) {
4e76a883
TI		 677 codec_dbg(codec,
678 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
307229d2
AH		 679 pin_nid,
680 active_channels, ca);
681 hdmi_stop_infoframe_trans(codec, pin_nid);
682 hdmi_fill_audio_infoframe(codec, pin_nid,
683 ai.bytes, sizeof(ai));
684 hdmi_start_infoframe_trans(codec, pin_nid);
685 }
686}
687
b054087d
TI		 688static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
689 struct hdmi_spec_per_pin *per_pin,
690 bool non_pcm)
079d88cc 691{
307229d2 692 struct hdmi_spec *spec = codec->spec;
739ffee9 693 struct hdac_chmap *chmap = &spec->chmap;
384a48d7 694 hda_nid_t pin_nid = per_pin->pin_nid;
b054087d 695 int channels = per_pin->channels;
1df5a06a 696 int active_channels;
384a48d7 697 struct hdmi_eld *eld;
828cb4ed 698 int ca;
079d88cc 699
b054087d
TI		 700 if (!channels)
701 return;
702
44bb6d0c
TI		 703 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */
704 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
58f7d28d
ML		 705 snd_hda_codec_write(codec, pin_nid, 0,
706 AC_VERB_SET_AMP_GAIN_MUTE,
707 AMP_OUT_UNMUTE);
708
bce0d2a8 709 eld = &per_pin->sink_eld;
079d88cc 710
bb63f726 711 ca = snd_hdac_channel_allocation(&codec->core,
828cb4ed
SP		 712 eld->info.spk_alloc, channels,
713 per_pin->chmap_set, non_pcm, per_pin->chmap);
384a48d7 714
bb63f726 715 active_channels = snd_hdac_get_active_channels(ca);
1df5a06a 716
739ffee9
SP		 717 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid,
718 active_channels);
1df5a06a 719
39edac70
AH		 720 /*
721 * always configure channel mapping, it may have been changed by the
722 * user in the meantime
723 */
bb63f726 724 snd_hdac_setup_channel_mapping(&spec->chmap,
828cb4ed
SP		 725 pin_nid, non_pcm, ca, channels,
726 per_pin->chmap, per_pin->chmap_set);
39edac70 727
307229d2
AH		 728 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
729 eld->info.conn_type);
433968da 730
1a6003b5 731 per_pin->non_pcm = non_pcm;
079d88cc
WF		 732}
733
079d88cc
WF		 734/*
735 * Unsolicited events
736 */
737
efe47108 738static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
38faddb1 739
9152085d
LY		 740static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid,
741 int dev_id)
079d88cc
WF		 742{
743 struct hdmi_spec *spec = codec->spec;
9152085d 744 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id);
1a4f69d5 745
20ce9029
DH		 746 if (pin_idx < 0)
747 return;
aaa23f86 748 mutex_lock(&spec->pcm_lock);
20ce9029
DH		 749 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
750 snd_hda_jack_report_sync(codec);
aaa23f86 751 mutex_unlock(&spec->pcm_lock);
20ce9029
DH		 752}
753
1a4f69d5
TI		 754static void jack_callback(struct hda_codec *codec,
755 struct hda_jack_callback *jack)
756{
ade49db3
TI		 757 /* stop polling when notification is enabled */
758 if (codec_has_acomp(codec))
759 return;
760
9152085d
LY		 761 /* hda_jack don't support DP MST */
762 check_presence_and_report(codec, jack->nid, 0);
1a4f69d5
TI		 763}
764
20ce9029
DH		 765static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
766{
3a93897e 767 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
3a93897e 768 struct hda_jack_tbl *jack;
2e59e5ab 769 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
3a93897e 770
9152085d
LY		 771 /*
772 * assume DP MST uses dyn_pcm_assign and acomp and
773 * never comes here
774 * if DP MST supports unsol event, below code need
775 * consider dev_entry
776 */
3a93897e
TI		 777 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
778 if (!jack)
779 return;
3a93897e 780 jack->jack_dirty = 1;
079d88cc 781
4e76a883 782 codec_dbg(codec,
2e59e5ab 783 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
20ce9029 784 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
fae3d88a 785 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
079d88cc 786
9152085d
LY		 787 /* hda_jack don't support DP MST */
788 check_presence_and_report(codec, jack->nid, 0);
079d88cc
WF		 789}
790
791static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
792{
793 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
794 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
795 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
796 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
797
4e76a883 798 codec_info(codec,
e9ea8e8f 799 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
384a48d7 800 codec->addr,
079d88cc
WF		 801 tag,
802 subtag,
803 cp_state,
804 cp_ready);
805
806 /* TODO */
807 if (cp_state)
808 ;
809 if (cp_ready)
810 ;
811}
812
813
814static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
815{
079d88cc
WF		 816 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
817 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
818
ade49db3
TI		 819 if (codec_has_acomp(codec))
820 return;
821
3a93897e 822 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
4e76a883 823 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
079d88cc
WF		 824 return;
825 }
826
827 if (subtag == 0)
828 hdmi_intrinsic_event(codec, res);
829 else
830 hdmi_non_intrinsic_event(codec, res);
831}
832
58f7d28d 833static void haswell_verify_D0(struct hda_codec *codec,
53b434f0 834 hda_nid_t cvt_nid, hda_nid_t nid)
83f26ad2 835{
58f7d28d 836 int pwr;
83f26ad2 837
53b434f0
WX		 838 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
839 * thus pins could only choose converter 0 for use. Make sure the
840 * converters are in correct power state */
fd678cac 841 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
53b434f0
WX		 842 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
843
fd678cac 844 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
83f26ad2
DH		 845 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
846 AC_PWRST_D0);
847 msleep(40);
848 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
849 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
4e76a883 850 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
83f26ad2 851 }
83f26ad2
DH		 852}
853
079d88cc
WF		 854/*
855 * Callbacks
856 */
857
92f10b3f
TI		 858/* HBR should be Non-PCM, 8 channels */
859#define is_hbr_format(format) \
860 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
861
307229d2
AH		 862static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
863 bool hbr)
079d88cc 864{
307229d2 865 int pinctl, new_pinctl;
83f26ad2 866
384a48d7
SW		 867 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
868 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
ea87d1c4
AH		 869 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
870
13122e6e
AH		 871 if (pinctl < 0)
872 return hbr ? -EINVAL : 0;
873
ea87d1c4 874 new_pinctl = pinctl & ~AC_PINCTL_EPT;
307229d2 875 if (hbr)
ea87d1c4
AH		 876 new_pinctl |= AC_PINCTL_EPT_HBR;
877 else
878 new_pinctl |= AC_PINCTL_EPT_NATIVE;
879
4e76a883
TI		 880 codec_dbg(codec,
881 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
384a48d7 882 pin_nid,
ea87d1c4
AH		 883 pinctl == new_pinctl ? "" : "new-",
884 new_pinctl);
885
886 if (pinctl != new_pinctl)
384a48d7 887 snd_hda_codec_write(codec, pin_nid, 0,
ea87d1c4
AH		 888 AC_VERB_SET_PIN_WIDGET_CONTROL,
889 new_pinctl);
307229d2
AH		 890 } else if (hbr)
891 return -EINVAL;
ea87d1c4 892
307229d2
AH		 893 return 0;
894}
895
896static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
897 hda_nid_t pin_nid, u32 stream_tag, int format)
898{
899 struct hdmi_spec *spec = codec->spec;
5a5d718f 900 unsigned int param;
307229d2
AH		 901 int err;
902
307229d2
AH		 903 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
904
905 if (err) {
4e76a883 906 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
307229d2 907 return err;
ea87d1c4 908 }
079d88cc 909
cb45722b 910 if (spec->intel_hsw_fixup) {
5a5d718f
SP		 911
912 /*
913 * on recent platforms IEC Coding Type is required for HBR
914 * support, read current Digital Converter settings and set
915 * ICT bitfield if needed.
916 */
917 param = snd_hda_codec_read(codec, cvt_nid, 0,
918 AC_VERB_GET_DIGI_CONVERT_1, 0);
919
920 param = (param >> 16) & ~(AC_DIG3_ICT);
921
922 /* on recent platforms ICT mode is required for HBR support */
923 if (is_hbr_format(format))
924 param |= 0x1;
925
926 snd_hda_codec_write(codec, cvt_nid, 0,
927 AC_VERB_SET_DIGI_CONVERT_3, param);
928 }
929
384a48d7 930 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
ea87d1c4 931 return 0;
079d88cc
WF		 932}
933
42b29870
LY		 934/* Try to find an available converter
935 * If pin_idx is less then zero, just try to find an available converter.
936 * Otherwise, try to find an available converter and get the cvt mux index
937 * of the pin.
938 */
7ef166b8 939static int hdmi_choose_cvt(struct hda_codec *codec,
4846a67e 940 int pin_idx, int *cvt_id)
bbbe3390
TI		 941{
942 struct hdmi_spec *spec = codec->spec;
384a48d7 943 struct hdmi_spec_per_pin *per_pin;
384a48d7 944 struct hdmi_spec_per_cvt *per_cvt = NULL;
7ef166b8 945 int cvt_idx, mux_idx = 0;
bbbe3390 946
42b29870
LY		 947 /* pin_idx < 0 means no pin will be bound to the converter */
948 if (pin_idx < 0)
949 per_pin = NULL;
950 else
951 per_pin = get_pin(spec, pin_idx);
384a48d7
SW		 952
953 /* Dynamically assign converter to stream */
954 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
bce0d2a8 955 per_cvt = get_cvt(spec, cvt_idx);
bbbe3390 956
384a48d7
SW		 957 /* Must not already be assigned */
958 if (per_cvt->assigned)
959 continue;
42b29870
LY		 960 if (per_pin == NULL)
961 break;
384a48d7
SW		 962 /* Must be in pin's mux's list of converters */
963 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
964 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
965 break;
966 /* Not in mux list */
967 if (mux_idx == per_pin->num_mux_nids)
968 continue;
969 break;
970 }
7ef166b8 971
384a48d7
SW		 972 /* No free converters */
973 if (cvt_idx == spec->num_cvts)
42b29870 974 return -EBUSY;
384a48d7 975
42b29870
LY		 976 if (per_pin != NULL)
977 per_pin->mux_idx = mux_idx;
2df6742f 978
7ef166b8
WX		 979 if (cvt_id)
980 *cvt_id = cvt_idx;
7ef166b8
WX		 981
982 return 0;
983}
984
2df6742f
ML		 985/* Assure the pin select the right convetor */
986static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
987 struct hdmi_spec_per_pin *per_pin)
988{
989 hda_nid_t pin_nid = per_pin->pin_nid;
990 int mux_idx, curr;
991
992 mux_idx = per_pin->mux_idx;
993 curr = snd_hda_codec_read(codec, pin_nid, 0,
994 AC_VERB_GET_CONNECT_SEL, 0);
995 if (curr != mux_idx)
996 snd_hda_codec_write_cache(codec, pin_nid, 0,
997 AC_VERB_SET_CONNECT_SEL,
998 mux_idx);
999}
1000
42b29870
LY		 1001/* get the mux index for the converter of the pins
1002 * converter's mux index is the same for all pins on Intel platform
1003 */
1004static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
1005 hda_nid_t cvt_nid)
1006{
1007 int i;
1008
1009 for (i = 0; i < spec->num_cvts; i++)
1010 if (spec->cvt_nids[i] == cvt_nid)
1011 return i;
1012 return -EINVAL;
1013}
1014
300016b9
ML		 1015/* Intel HDMI workaround to fix audio routing issue:
1016 * For some Intel display codecs, pins share the same connection list.
1017 * So a conveter can be selected by multiple pins and playback on any of these
1018 * pins will generate sound on the external display, because audio flows from
1019 * the same converter to the display pipeline. Also muting one pin may make
1020 * other pins have no sound output.
1021 * So this function assures that an assigned converter for a pin is not selected
1022 * by any other pins.
1023 */
1024static void intel_not_share_assigned_cvt(struct hda_codec *codec,
9152085d
LY		 1025 hda_nid_t pin_nid,
1026 int dev_id, int mux_idx)
7ef166b8
WX		 1027{
1028 struct hdmi_spec *spec = codec->spec;
7639a06c 1029 hda_nid_t nid;
f82d7d16
ML		 1030 int cvt_idx, curr;
1031 struct hdmi_spec_per_cvt *per_cvt;
9152085d
LY		 1032 struct hdmi_spec_per_pin *per_pin;
1033 int pin_idx;
1034
1035 /* configure the pins connections */
1036 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1037 int dev_id_saved;
1038 int dev_num;
7ef166b8 1039
9152085d
LY		 1040 per_pin = get_pin(spec, pin_idx);
1041 /*
1042 * pin not connected to monitor
1043 * no need to operate on it
1044 */
1045 if (!per_pin->pcm)
1046 continue;
f82d7d16 1047
9152085d
LY		 1048 if ((per_pin->pin_nid == pin_nid) &&
1049 (per_pin->dev_id == dev_id))
f82d7d16 1050 continue;
7ef166b8 1051
9152085d
LY		 1052 /*
1053 * if per_pin->dev_id >= dev_num,
1054 * snd_hda_get_dev_select() will fail,
1055 * and the following operation is unpredictable.
1056 * So skip this situation.
1057 */
1058 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1;
1059 if (per_pin->dev_id >= dev_num)
7ef166b8
WX		 1060 continue;
1061
9152085d
LY		 1062 nid = per_pin->pin_nid;
1063
1064 /*
1065 * Calling this function should not impact
1066 * on the device entry selection
1067 * So let's save the dev id for each pin,
1068 * and restore it when return
1069 */
1070 dev_id_saved = snd_hda_get_dev_select(codec, nid);
1071 snd_hda_set_dev_select(codec, nid, per_pin->dev_id);
f82d7d16 1072 curr = snd_hda_codec_read(codec, nid, 0,
7ef166b8 1073 AC_VERB_GET_CONNECT_SEL, 0);
9152085d
LY		 1074 if (curr != mux_idx) {
1075 snd_hda_set_dev_select(codec, nid, dev_id_saved);
f82d7d16 1076 continue;
9152085d
LY		 1077 }
1078
7ef166b8 1079
f82d7d16
ML		 1080 /* choose an unassigned converter. The conveters in the
1081 * connection list are in the same order as in the codec.
1082 */
1083 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1084 per_cvt = get_cvt(spec, cvt_idx);
1085 if (!per_cvt->assigned) {
4e76a883
TI		 1086 codec_dbg(codec,
1087 "choose cvt %d for pin nid %d\n",
f82d7d16
ML		 1088 cvt_idx, nid);
1089 snd_hda_codec_write_cache(codec, nid, 0,
7ef166b8 1090 AC_VERB_SET_CONNECT_SEL,
f82d7d16
ML		 1091 cvt_idx);
1092 break;
1093 }
7ef166b8 1094 }
9152085d 1095 snd_hda_set_dev_select(codec, nid, dev_id_saved);
7ef166b8
WX		 1096 }
1097}
1098
42b29870
LY		 1099/* A wrapper of intel_not_share_asigned_cvt() */
1100static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
9152085d 1101 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid)
42b29870
LY		 1102{
1103 int mux_idx;
1104 struct hdmi_spec *spec = codec->spec;
1105
42b29870
LY		 1106 /* On Intel platform, the mapping of converter nid to
1107 * mux index of the pins are always the same.
1108 * The pin nid may be 0, this means all pins will not
1109 * share the converter.
1110 */
1111 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1112 if (mux_idx >= 0)
9152085d 1113 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx);
42b29870
LY		 1114}
1115
4846a67e
TI		 1116/* skeleton caller of pin_cvt_fixup ops */
1117static void pin_cvt_fixup(struct hda_codec *codec,
1118 struct hdmi_spec_per_pin *per_pin,
1119 hda_nid_t cvt_nid)
1120{
1121 struct hdmi_spec *spec = codec->spec;
1122
1123 if (spec->ops.pin_cvt_fixup)
1124 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid);
1125}
1126
42b29870
LY		 1127/* called in hdmi_pcm_open when no pin is assigned to the PCM
1128 * in dyn_pcm_assign mode.
1129 */
1130static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1131 struct hda_codec *codec,
1132 struct snd_pcm_substream *substream)
1133{
1134 struct hdmi_spec *spec = codec->spec;
1135 struct snd_pcm_runtime *runtime = substream->runtime;
ac98379a 1136 int cvt_idx, pcm_idx;
42b29870
LY		 1137 struct hdmi_spec_per_cvt *per_cvt = NULL;
1138 int err;
1139
ac98379a
LY		 1140 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1141 if (pcm_idx < 0)
1142 return -EINVAL;
1143
4846a67e 1144 err = hdmi_choose_cvt(codec, -1, &cvt_idx);
42b29870
LY		 1145 if (err)
1146 return err;
1147
1148 per_cvt = get_cvt(spec, cvt_idx);
1149 per_cvt->assigned = 1;
1150 hinfo->nid = per_cvt->cvt_nid;
1151
4846a67e 1152 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid);
42b29870 1153
ac98379a 1154 set_bit(pcm_idx, &spec->pcm_in_use);
42b29870
LY		 1155 /* todo: setup spdif ctls assign */
1156
1157 /* Initially set the converter's capabilities */
1158 hinfo->channels_min = per_cvt->channels_min;
1159 hinfo->channels_max = per_cvt->channels_max;
1160 hinfo->rates = per_cvt->rates;
1161 hinfo->formats = per_cvt->formats;
1162 hinfo->maxbps = per_cvt->maxbps;
1163
1164 /* Store the updated parameters */
1165 runtime->hw.channels_min = hinfo->channels_min;
1166 runtime->hw.channels_max = hinfo->channels_max;
1167 runtime->hw.formats = hinfo->formats;
1168 runtime->hw.rates = hinfo->rates;
1169
1170 snd_pcm_hw_constraint_step(substream->runtime, 0,
1171 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1172 return 0;
1173}
1174
7ef166b8
WX		 1175/*
1176 * HDA PCM callbacks
1177 */
1178static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1179 struct hda_codec *codec,
1180 struct snd_pcm_substream *substream)
1181{
1182 struct hdmi_spec *spec = codec->spec;
1183 struct snd_pcm_runtime *runtime = substream->runtime;
4846a67e 1184 int pin_idx, cvt_idx, pcm_idx;
7ef166b8
WX		 1185 struct hdmi_spec_per_pin *per_pin;
1186 struct hdmi_eld *eld;
1187 struct hdmi_spec_per_cvt *per_cvt = NULL;
1188 int err;
1189
1190 /* Validate hinfo */
2bf3c85a
LY		 1191 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1192 if (pcm_idx < 0)
7ef166b8 1193 return -EINVAL;
2bf3c85a 1194
42b29870 1195 mutex_lock(&spec->pcm_lock);
4e76a883 1196 pin_idx = hinfo_to_pin_index(codec, hinfo);
42b29870
LY		 1197 if (!spec->dyn_pcm_assign) {
1198 if (snd_BUG_ON(pin_idx < 0)) {
f69548ff
TI		 1199 err = -EINVAL;
1200 goto unlock;
42b29870
LY		 1201 }
1202 } else {
1203 /* no pin is assigned to the PCM
1204 * PA need pcm open successfully when probe
1205 */
1206 if (pin_idx < 0) {
1207 err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
f69548ff 1208 goto unlock;
42b29870
LY		 1209 }
1210 }
7ef166b8 1211
4846a67e 1212 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx);
f69548ff
TI		 1213 if (err < 0)
1214 goto unlock;
7ef166b8
WX		 1215
1216 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1217 /* Claim converter */
1218 per_cvt->assigned = 1;
42b29870 1219
ac98379a 1220 set_bit(pcm_idx, &spec->pcm_in_use);
42b29870 1221 per_pin = get_pin(spec, pin_idx);
1df5a06a 1222 per_pin->cvt_nid = per_cvt->cvt_nid;
384a48d7
SW		 1223 hinfo->nid = per_cvt->cvt_nid;
1224
9152085d 1225 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
bddee96b 1226 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
384a48d7 1227 AC_VERB_SET_CONNECT_SEL,
4846a67e 1228 per_pin->mux_idx);
7ef166b8
WX		 1229
1230 /* configure unused pins to choose other converters */
4846a67e 1231 pin_cvt_fixup(codec, per_pin, 0);
7ef166b8 1232
2bf3c85a 1233 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
bbbe3390 1234
2def8172 1235 /* Initially set the converter's capabilities */
384a48d7
SW		 1236 hinfo->channels_min = per_cvt->channels_min;
1237 hinfo->channels_max = per_cvt->channels_max;
1238 hinfo->rates = per_cvt->rates;
1239 hinfo->formats = per_cvt->formats;
1240 hinfo->maxbps = per_cvt->maxbps;
2def8172 1241
42b29870 1242 eld = &per_pin->sink_eld;
384a48d7 1243 /* Restrict capabilities by ELD if this isn't disabled */
c3d52105 1244 if (!static_hdmi_pcm && eld->eld_valid) {
1613d6b4 1245 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
bbbe3390 1246 if (hinfo->channels_min > hinfo->channels_max ||
2ad779b7
TI		 1247 !hinfo->rates || !hinfo->formats) {
1248 per_cvt->assigned = 0;
1249 hinfo->nid = 0;
2bf3c85a 1250 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
f69548ff
TI		 1251 err = -ENODEV;
1252 goto unlock;
2ad779b7 1253 }
bbbe3390 1254 }
2def8172
SW		 1255
1256 /* Store the updated parameters */
639cef0e
TI		 1257 runtime->hw.channels_min = hinfo->channels_min;
1258 runtime->hw.channels_max = hinfo->channels_max;
1259 runtime->hw.formats = hinfo->formats;
1260 runtime->hw.rates = hinfo->rates;
4fe2ca14
TI		 1261
1262 snd_pcm_hw_constraint_step(substream->runtime, 0,
1263 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
f69548ff
TI		 1264 unlock:
1265 mutex_unlock(&spec->pcm_lock);
1266 return err;
bbbe3390
TI		 1267}
1268
079d88cc
WF		 1269/*
1270 * HDA/HDMI auto parsing
1271 */
384a48d7 1272static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
079d88cc
WF		 1273{
1274 struct hdmi_spec *spec = codec->spec;
bce0d2a8 1275 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1276 hda_nid_t pin_nid = per_pin->pin_nid;
079d88cc
WF		 1277
1278 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
4e76a883
TI		 1279 codec_warn(codec,
1280 "HDMI: pin %d wcaps %#x does not support connection list\n",
079d88cc
WF		 1281 pin_nid, get_wcaps(codec, pin_nid));
1282 return -EINVAL;
1283 }
1284
9152085d 1285 /* all the device entries on the same pin have the same conn list */
384a48d7
SW		 1286 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1287 per_pin->mux_nids,
1288 HDA_MAX_CONNECTIONS);
079d88cc
WF		 1289
1290 return 0;
1291}
1292
a76056f2
LY		 1293static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
1294 struct hdmi_spec_per_pin *per_pin)
1295{
1296 int i;
1297
1298 /* try the prefer PCM */
1299 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap))
1300 return per_pin->pin_nid_idx;
1301
1302 /* have a second try; check the "reserved area" over num_pins */
9152085d 1303 for (i = spec->num_nids; i < spec->pcm_used; i++) {
a76056f2
LY		 1304 if (!test_bit(i, &spec->pcm_bitmap))
1305 return i;
1306 }
1307
1308 /* the last try; check the empty slots in pins */
9152085d 1309 for (i = 0; i < spec->num_nids; i++) {
a76056f2
LY		 1310 if (!test_bit(i, &spec->pcm_bitmap))
1311 return i;
1312 }
1313 return -EBUSY;
1314}
1315
1316static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
1317 struct hdmi_spec_per_pin *per_pin)
1318{
1319 int idx;
1320
1321 /* pcm already be attached to the pin */
1322 if (per_pin->pcm)
1323 return;
1324 idx = hdmi_find_pcm_slot(spec, per_pin);
d10a80de 1325 if (idx == -EBUSY)
a76056f2
LY		 1326 return;
1327 per_pin->pcm_idx = idx;
2bea241a 1328 per_pin->pcm = get_hdmi_pcm(spec, idx);
a76056f2
LY		 1329 set_bit(idx, &spec->pcm_bitmap);
1330}
1331
1332static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
1333 struct hdmi_spec_per_pin *per_pin)
1334{
1335 int idx;
1336
1337 /* pcm already be detached from the pin */
1338 if (!per_pin->pcm)
1339 return;
1340 idx = per_pin->pcm_idx;
1341 per_pin->pcm_idx = -1;
1342 per_pin->pcm = NULL;
1343 if (idx >= 0 && idx < spec->pcm_used)
1344 clear_bit(idx, &spec->pcm_bitmap);
1345}
1346
ac98379a
LY		 1347static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
1348 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
1349{
1350 int mux_idx;
1351
1352 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1353 if (per_pin->mux_nids[mux_idx] == cvt_nid)
1354 break;
1355 return mux_idx;
1356}
1357
1358static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
1359
1360static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
1361 struct hdmi_spec_per_pin *per_pin)
1362{
1363 struct hda_codec *codec = per_pin->codec;
1364 struct hda_pcm *pcm;
1365 struct hda_pcm_stream *hinfo;
1366 struct snd_pcm_substream *substream;
1367 int mux_idx;
1368 bool non_pcm;
1369
1370 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
2bea241a 1371 pcm = get_pcm_rec(spec, per_pin->pcm_idx);
ac98379a
LY		 1372 else
1373 return;
8a7d6003
TI		 1374 if (!pcm->pcm)
1375 return;
ac98379a
LY		 1376 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
1377 return;
1378
1379 /* hdmi audio only uses playback and one substream */
1380 hinfo = pcm->stream;
1381 substream = pcm->pcm->streams[0].substream;
1382
1383 per_pin->cvt_nid = hinfo->nid;
1384
1385 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
9152085d
LY		 1386 if (mux_idx < per_pin->num_mux_nids) {
1387 snd_hda_set_dev_select(codec, per_pin->pin_nid,
1388 per_pin->dev_id);
ac98379a
LY		 1389 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1390 AC_VERB_SET_CONNECT_SEL,
1391 mux_idx);
9152085d 1392 }
ac98379a
LY		 1393 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
1394
1395 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
1396 if (substream->runtime)
1397 per_pin->channels = substream->runtime->channels;
1398 per_pin->setup = true;
1399 per_pin->mux_idx = mux_idx;
1400
1401 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1402}
1403
1404static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
1405 struct hdmi_spec_per_pin *per_pin)
1406{
1407 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1408 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
1409
1410 per_pin->chmap_set = false;
1411 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1412
1413 per_pin->setup = false;
1414 per_pin->channels = 0;
1415}
1416
e90247f9
TI		 1417/* update per_pin ELD from the given new ELD;
1418 * setup info frame and notification accordingly
1419 */
551626ec 1420static bool update_eld(struct hda_codec *codec,
e90247f9
TI		 1421 struct hdmi_spec_per_pin *per_pin,
1422 struct hdmi_eld *eld)
1423{
1424 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
a76056f2 1425 struct hdmi_spec *spec = codec->spec;
e90247f9
TI		 1426 bool old_eld_valid = pin_eld->eld_valid;
1427 bool eld_changed;
f953e72c 1428 int pcm_idx;
e90247f9 1429
fb087eaa
LY		 1430 /* for monitor disconnection, save pcm_idx firstly */
1431 pcm_idx = per_pin->pcm_idx;
a76056f2 1432 if (spec->dyn_pcm_assign) {
ac98379a 1433 if (eld->eld_valid) {
a76056f2 1434 hdmi_attach_hda_pcm(spec, per_pin);
ac98379a
LY		 1435 hdmi_pcm_setup_pin(spec, per_pin);
1436 } else {
1437 hdmi_pcm_reset_pin(spec, per_pin);
a76056f2 1438 hdmi_detach_hda_pcm(spec, per_pin);
ac98379a 1439 }
a76056f2 1440 }
fb087eaa
LY		 1441 /* if pcm_idx == -1, it means this is in monitor connection event
1442 * we can get the correct pcm_idx now.
1443 */
1444 if (pcm_idx == -1)
1445 pcm_idx = per_pin->pcm_idx;
a76056f2 1446
e90247f9
TI		 1447 if (eld->eld_valid)
1448 snd_hdmi_show_eld(codec, &eld->info);
1449
1450 eld_changed = (pin_eld->eld_valid != eld->eld_valid);
551626ec
TI		 1451 eld_changed |= (pin_eld->monitor_present != eld->monitor_present);
1452 if (!eld_changed && eld->eld_valid && pin_eld->eld_valid)
e90247f9
TI		 1453 if (pin_eld->eld_size != eld->eld_size ||
1454 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1455 eld->eld_size) != 0)
1456 eld_changed = true;
1457
551626ec
TI		 1458 if (eld_changed) {
1459 pin_eld->monitor_present = eld->monitor_present;
1460 pin_eld->eld_valid = eld->eld_valid;
1461 pin_eld->eld_size = eld->eld_size;
1462 if (eld->eld_valid)
1463 memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1464 eld->eld_size);
1465 pin_eld->info = eld->info;
1466 }
e90247f9
TI		 1467
1468 /*
1469 * Re-setup pin and infoframe. This is needed e.g. when
1470 * - sink is first plugged-in
1471 * - transcoder can change during stream playback on Haswell
1472 * and this can make HW reset converter selection on a pin.
1473 */
1474 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
4846a67e 1475 pin_cvt_fixup(codec, per_pin, 0);
e90247f9
TI		 1476 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1477 }
1478
fb087eaa 1479 if (eld_changed && pcm_idx >= 0)
e90247f9
TI		 1480 snd_ctl_notify(codec->card,
1481 SNDRV_CTL_EVENT_MASK_VALUE |
1482 SNDRV_CTL_EVENT_MASK_INFO,
fb087eaa 1483 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
551626ec 1484 return eld_changed;
e90247f9
TI		 1485}
1486
788d441a
TI		 1487/* update ELD and jack state via HD-audio verbs */
1488static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1489 int repoll)
079d88cc 1490{
464837a7 1491 struct hda_jack_tbl *jack;
744626da 1492 struct hda_codec *codec = per_pin->codec;
4bd038f9
DH		 1493 struct hdmi_spec *spec = codec->spec;
1494 struct hdmi_eld *eld = &spec->temp_eld;
744626da 1495 hda_nid_t pin_nid = per_pin->pin_nid;
5d44f927
SW		 1496 /*
1497 * Always execute a GetPinSense verb here, even when called from
1498 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1499 * response's PD bit is not the real PD value, but indicates that
1500 * the real PD value changed. An older version of the HD-audio
1501 * specification worked this way. Hence, we just ignore the data in
1502 * the unsolicited response to avoid custom WARs.
1503 */
da4a7a39 1504 int present;
efe47108 1505 bool ret;
9a5e5234 1506 bool do_repoll = false;
079d88cc 1507
da4a7a39
DH		 1508 present = snd_hda_pin_sense(codec, pin_nid);
1509
a4e9a38b 1510 mutex_lock(&per_pin->lock);
c44da62b
TI		 1511 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1512 if (eld->monitor_present)
4bd038f9
DH		 1513 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1514 else
1515 eld->eld_valid = false;
079d88cc 1516
4e76a883 1517 codec_dbg(codec,
384a48d7 1518 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
c44da62b 1519 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
5d44f927 1520
4bd038f9 1521 if (eld->eld_valid) {
307229d2 1522 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1613d6b4 1523 &eld->eld_size) < 0)
4bd038f9 1524 eld->eld_valid = false;
1613d6b4 1525 else {
79514d47 1526 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1613d6b4 1527 eld->eld_size) < 0)
4bd038f9 1528 eld->eld_valid = false;
1613d6b4 1529 }
9a5e5234
TI		 1530 if (!eld->eld_valid && repoll)
1531 do_repoll = true;
744626da 1532 }
4bd038f9 1533
9a5e5234 1534 if (do_repoll)
e90247f9
TI		 1535 schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300));
1536 else
1537 update_eld(codec, per_pin, eld);
92c69e79 1538
c44da62b 1539 ret = !repoll || !eld->monitor_present || eld->eld_valid;
464837a7
DH		 1540
1541 jack = snd_hda_jack_tbl_get(codec, pin_nid);
7f641e26 1542 if (jack) {
464837a7 1543 jack->block_report = !ret;
7f641e26
HW		 1544 jack->pin_sense = (eld->monitor_present && eld->eld_valid) ?
1545 AC_PINSENSE_PRESENCE : 0;
1546 }
a4e9a38b 1547 mutex_unlock(&per_pin->lock);
efe47108 1548 return ret;
079d88cc
WF		 1549}
1550
3184270e
LY		 1551static struct snd_jack *pin_idx_to_jack(struct hda_codec *codec,
1552 struct hdmi_spec_per_pin *per_pin)
1553{
1554 struct hdmi_spec *spec = codec->spec;
1555 struct snd_jack *jack = NULL;
1556 struct hda_jack_tbl *jack_tbl;
1557
1558 /* if !dyn_pcm_assign, get jack from hda_jack_tbl
1559 * in !dyn_pcm_assign case, spec->pcm_rec[].jack is not
1560 * NULL even after snd_hda_jack_tbl_clear() is called to
1561 * free snd_jack. This may cause access invalid memory
1562 * when calling snd_jack_report
1563 */
1564 if (per_pin->pcm_idx >= 0 && spec->dyn_pcm_assign)
1565 jack = spec->pcm_rec[per_pin->pcm_idx].jack;
1566 else if (!spec->dyn_pcm_assign) {
9152085d
LY		 1567 /*
1568 * jack tbl doesn't support DP MST
1569 * DP MST will use dyn_pcm_assign,
1570 * so DP MST will never come here
1571 */
3184270e
LY		 1572 jack_tbl = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1573 if (jack_tbl)
1574 jack = jack_tbl->jack;
1575 }
1576 return jack;
1577}
1578
788d441a
TI		 1579/* update ELD and jack state via audio component */
1580static void sync_eld_via_acomp(struct hda_codec *codec,
1581 struct hdmi_spec_per_pin *per_pin)
1582{
788d441a
TI		 1583 struct hdmi_spec *spec = codec->spec;
1584 struct hdmi_eld *eld = &spec->temp_eld;
25e4abb3 1585 struct snd_jack *jack = NULL;
551626ec 1586 bool changed;
788d441a
TI		 1587 int size;
1588
e2dc7d7d 1589 mutex_lock(&per_pin->lock);
c64c1437 1590 eld->monitor_present = false;
9152085d
LY		 1591 size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid,
1592 per_pin->dev_id, &eld->monitor_present,
1593 eld->eld_buffer, ELD_MAX_SIZE);
e2dc7d7d
TI		 1594 if (size > 0) {
1595 size = min(size, ELD_MAX_SIZE);
1596 if (snd_hdmi_parse_eld(codec, &eld->info,
1597 eld->eld_buffer, size) < 0)
1598 size = -EINVAL;
1599 }
788d441a 1600
e2dc7d7d
TI		 1601 if (size > 0) {
1602 eld->eld_valid = true;
1603 eld->eld_size = size;
1604 } else {
1605 eld->eld_valid = false;
1606 eld->eld_size = 0;
788d441a 1607 }
e2dc7d7d 1608
25e4abb3
LY		 1609 /* pcm_idx >=0 before update_eld() means it is in monitor
1610 * disconnected event. Jack must be fetched before update_eld()
1611 */
3184270e 1612 jack = pin_idx_to_jack(codec, per_pin);
551626ec 1613 changed = update_eld(codec, per_pin, eld);
3184270e
LY		 1614 if (jack == NULL)
1615 jack = pin_idx_to_jack(codec, per_pin);
551626ec
TI		 1616 if (changed && jack)
1617 snd_jack_report(jack,
1618 (eld->monitor_present && eld->eld_valid) ?
855b5e01 1619 SND_JACK_AVOUT : 0);
e2dc7d7d 1620 mutex_unlock(&per_pin->lock);
788d441a
TI		 1621}
1622
1623static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1624{
1625 struct hda_codec *codec = per_pin->codec;
a76056f2 1626 int ret;
788d441a 1627
222bde03 1628 /* no temporary power up/down needed for component notifier */
aaa23f86
CW		 1629 if (!codec_has_acomp(codec)) {
1630 ret = snd_hda_power_up_pm(codec);
1631 if (ret < 0 && pm_runtime_suspended(hda_codec_dev(codec))) {
1632 snd_hda_power_down_pm(codec);
1633 return false;
1634 }
ade49db3
TI		 1635 ret = hdmi_present_sense_via_verbs(per_pin, repoll);
1636 snd_hda_power_down_pm(codec);
1637 } else {
788d441a 1638 sync_eld_via_acomp(codec, per_pin);
a76056f2 1639 ret = false; /* don't call snd_hda_jack_report_sync() */
788d441a 1640 }
a76056f2
LY		 1641
1642 return ret;
788d441a
TI		 1643}
1644
744626da
WF		 1645static void hdmi_repoll_eld(struct work_struct *work)
1646{
1647 struct hdmi_spec_per_pin *per_pin =
1648 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
aaa23f86
CW		 1649 struct hda_codec *codec = per_pin->codec;
1650 struct hdmi_spec *spec = codec->spec;
8c2e6728
HW		 1651 struct hda_jack_tbl *jack;
1652
1653 jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1654 if (jack)
1655 jack->jack_dirty = 1;
744626da 1656
c6e8453e
WF		 1657 if (per_pin->repoll_count++ > 6)
1658 per_pin->repoll_count = 0;
1659
aaa23f86 1660 mutex_lock(&spec->pcm_lock);
efe47108
TI		 1661 if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1662 snd_hda_jack_report_sync(per_pin->codec);
aaa23f86 1663 mutex_unlock(&spec->pcm_lock);
744626da
WF		 1664}
1665
c88d4e84
TI		 1666static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1667 hda_nid_t nid);
1668
079d88cc
WF		 1669static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1670{
1671 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1672 unsigned int caps, config;
1673 int pin_idx;
1674 struct hdmi_spec_per_pin *per_pin;
07acecc1 1675 int err;
9152085d 1676 int dev_num, i;
079d88cc 1677
efc2f8de 1678 caps = snd_hda_query_pin_caps(codec, pin_nid);
384a48d7
SW		 1679 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1680 return 0;
1681
9152085d
LY		 1682 /*
1683 * For DP MST audio, Configuration Default is the same for
1684 * all device entries on the same pin
1685 */
efc2f8de 1686 config = snd_hda_codec_get_pincfg(codec, pin_nid);
384a48d7
SW		 1687 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1688 return 0;
1689
9152085d
LY		 1690 /*
1691 * To simplify the implementation, malloc all
1692 * the virtual pins in the initialization statically
1693 */
cb45722b 1694 if (spec->intel_hsw_fixup) {
9152085d
LY		 1695 /*
1696 * On Intel platforms, device entries number is
1697 * changed dynamically. If there is a DP MST
1698 * hub connected, the device entries number is 3.
1699 * Otherwise, it is 1.
1700 * Here we manually set dev_num to 3, so that
1701 * we can initialize all the device entries when
1702 * bootup statically.
1703 */
1704 dev_num = 3;
1705 spec->dev_num = 3;
1706 } else if (spec->dyn_pcm_assign && codec->dp_mst) {
1707 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1;
1708 /*
1709 * spec->dev_num is the maxinum number of device entries
1710 * among all the pins
1711 */
1712 spec->dev_num = (spec->dev_num > dev_num) ?
1713 spec->dev_num : dev_num;
1714 } else {
1715 /*
1716 * If the platform doesn't support DP MST,
1717 * manually set dev_num to 1. This means
1718 * the pin has only one device entry.
1719 */
1720 dev_num = 1;
1721 spec->dev_num = 1;
2bea241a 1722 }
079d88cc 1723
9152085d
LY		 1724 for (i = 0; i < dev_num; i++) {
1725 pin_idx = spec->num_pins;
1726 per_pin = snd_array_new(&spec->pins);
079d88cc 1727
9152085d
LY		 1728 if (!per_pin)
1729 return -ENOMEM;
1730
1731 if (spec->dyn_pcm_assign) {
1732 per_pin->pcm = NULL;
1733 per_pin->pcm_idx = -1;
1734 } else {
1735 per_pin->pcm = get_hdmi_pcm(spec, pin_idx);
1736 per_pin->pcm_idx = pin_idx;
1737 }
1738 per_pin->pin_nid = pin_nid;
1739 per_pin->pin_nid_idx = spec->num_nids;
1740 per_pin->dev_id = i;
1741 per_pin->non_pcm = false;
1742 snd_hda_set_dev_select(codec, pin_nid, i);
cb45722b 1743 if (spec->intel_hsw_fixup)
9152085d
LY		 1744 intel_haswell_fixup_connect_list(codec, pin_nid);
1745 err = hdmi_read_pin_conn(codec, pin_idx);
1746 if (err < 0)
1747 return err;
1748 spec->num_pins++;
1749 }
1750 spec->num_nids++;
079d88cc 1751
384a48d7 1752 return 0;
079d88cc
WF		 1753}
1754
384a48d7 1755static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc
WF		 1756{
1757 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1758 struct hdmi_spec_per_cvt *per_cvt;
1759 unsigned int chans;
1760 int err;
079d88cc 1761
384a48d7
SW		 1762 chans = get_wcaps(codec, cvt_nid);
1763 chans = get_wcaps_channels(chans);
1764
bce0d2a8
TI		 1765 per_cvt = snd_array_new(&spec->cvts);
1766 if (!per_cvt)
1767 return -ENOMEM;
384a48d7
SW		 1768
1769 per_cvt->cvt_nid = cvt_nid;
1770 per_cvt->channels_min = 2;
d45e6889 1771 if (chans <= 16) {
384a48d7 1772 per_cvt->channels_max = chans;
67b90cb8
SP		 1773 if (chans > spec->chmap.channels_max)
1774 spec->chmap.channels_max = chans;
d45e6889 1775 }
384a48d7
SW		 1776
1777 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1778 &per_cvt->rates,
1779 &per_cvt->formats,
1780 &per_cvt->maxbps);
1781 if (err < 0)
1782 return err;
1783
bce0d2a8
TI		 1784 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1785 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1786 spec->num_cvts++;
079d88cc
WF		 1787
1788 return 0;
1789}
1790
1791static int hdmi_parse_codec(struct hda_codec *codec)
1792{
1793 hda_nid_t nid;
1794 int i, nodes;
1795
7639a06c 1796 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
079d88cc 1797 if (!nid || nodes < 0) {
4e76a883 1798 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
079d88cc
WF		 1799 return -EINVAL;
1800 }
1801
1802 for (i = 0; i < nodes; i++, nid++) {
1803 unsigned int caps;
1804 unsigned int type;
1805
efc2f8de 1806 caps = get_wcaps(codec, nid);
079d88cc
WF		 1807 type = get_wcaps_type(caps);
1808
1809 if (!(caps & AC_WCAP_DIGITAL))
1810 continue;
1811
1812 switch (type) {
1813 case AC_WID_AUD_OUT:
384a48d7 1814 hdmi_add_cvt(codec, nid);
079d88cc
WF		 1815 break;
1816 case AC_WID_PIN:
3eaead57 1817 hdmi_add_pin(codec, nid);
079d88cc
WF		 1818 break;
1819 }
1820 }
1821
079d88cc
WF		 1822 return 0;
1823}
1824
84eb01be
TI		 1825/*
1826 */
1a6003b5
TI		 1827static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1828{
1829 struct hda_spdif_out *spdif;
1830 bool non_pcm;
1831
1832 mutex_lock(&codec->spdif_mutex);
1833 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
960a581e
LY		 1834 /* Add sanity check to pass klockwork check.
1835 * This should never happen.
1836 */
1837 if (WARN_ON(spdif == NULL))
1838 return true;
1a6003b5
TI		 1839 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1840 mutex_unlock(&codec->spdif_mutex);
1841 return non_pcm;
1842}
1843
84eb01be
TI		 1844/*
1845 * HDMI callbacks
1846 */
1847
1848static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1849 struct hda_codec *codec,
1850 unsigned int stream_tag,
1851 unsigned int format,
1852 struct snd_pcm_substream *substream)
1853{
384a48d7
SW		 1854 hda_nid_t cvt_nid = hinfo->nid;
1855 struct hdmi_spec *spec = codec->spec;
42b29870
LY		 1856 int pin_idx;
1857 struct hdmi_spec_per_pin *per_pin;
1858 hda_nid_t pin_nid;
ddd621fb 1859 struct snd_pcm_runtime *runtime = substream->runtime;
1a6003b5 1860 bool non_pcm;
053b0559 1861 int pinctl, stripe;
f69548ff 1862 int err = 0;
1a6003b5 1863
42b29870
LY		 1864 mutex_lock(&spec->pcm_lock);
1865 pin_idx = hinfo_to_pin_index(codec, hinfo);
1866 if (spec->dyn_pcm_assign && pin_idx < 0) {
1867 /* when dyn_pcm_assign and pcm is not bound to a pin
1868 * skip pin setup and return 0 to make audio playback
1869 * be ongoing
1870 */
4846a67e 1871 pin_cvt_fixup(codec, NULL, cvt_nid);
42b29870
LY		 1872 snd_hda_codec_setup_stream(codec, cvt_nid,
1873 stream_tag, 0, format);
f69548ff 1874 goto unlock;
42b29870 1875 }
1a6003b5 1876
42b29870 1877 if (snd_BUG_ON(pin_idx < 0)) {
f69548ff
TI		 1878 err = -EINVAL;
1879 goto unlock;
42b29870
LY		 1880 }
1881 per_pin = get_pin(spec, pin_idx);
1882 pin_nid = per_pin->pin_nid;
4846a67e
TI		 1883
1884 /* Verify pin:cvt selections to avoid silent audio after S3.
1885 * After S3, the audio driver restores pin:cvt selections
1886 * but this can happen before gfx is ready and such selection
1887 * is overlooked by HW. Thus multiple pins can share a same
1888 * default convertor and mute control will affect each other,
1889 * which can cause a resumed audio playback become silent
1890 * after S3.
1891 */
1892 pin_cvt_fixup(codec, per_pin, 0);
2df6742f 1893
ddd621fb
LY		 1894 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
1895 /* Todo: add DP1.2 MST audio support later */
93a9ff15 1896 if (codec_has_acomp(codec))
9152085d 1897 snd_hdac_sync_audio_rate(&codec->core, pin_nid, per_pin->dev_id,
f9318941 1898 runtime->rate);
ddd621fb 1899
1a6003b5 1900 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
a4e9a38b 1901 mutex_lock(&per_pin->lock);
b054087d
TI		 1902 per_pin->channels = substream->runtime->channels;
1903 per_pin->setup = true;
384a48d7 1904
053b0559
SP		 1905 if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) {
1906 stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core,
1907 substream);
1908 snd_hda_codec_write(codec, cvt_nid, 0,
1909 AC_VERB_SET_STRIPE_CONTROL,
1910 stripe);
1911 }
1912
b054087d 1913 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
a4e9a38b 1914 mutex_unlock(&per_pin->lock);
75fae117
SW		 1915 if (spec->dyn_pin_out) {
1916 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1917 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1918 snd_hda_codec_write(codec, pin_nid, 0,
1919 AC_VERB_SET_PIN_WIDGET_CONTROL,
1920 pinctl | PIN_OUT);
1921 }
1922
9152085d 1923 /* snd_hda_set_dev_select() has been called before */
42b29870
LY		 1924 err = spec->ops.setup_stream(codec, cvt_nid, pin_nid,
1925 stream_tag, format);
f69548ff 1926 unlock:
42b29870
LY		 1927 mutex_unlock(&spec->pcm_lock);
1928 return err;
84eb01be
TI		 1929}
1930
8dfaa573
TI		 1931static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1932 struct hda_codec *codec,
1933 struct snd_pcm_substream *substream)
1934{
1935 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1936 return 0;
1937}
1938
f2ad24fa
TI		 1939static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1940 struct hda_codec *codec,
1941 struct snd_pcm_substream *substream)
384a48d7
SW		 1942{
1943 struct hdmi_spec *spec = codec->spec;
2bf3c85a 1944 int cvt_idx, pin_idx, pcm_idx;
384a48d7
SW		 1945 struct hdmi_spec_per_cvt *per_cvt;
1946 struct hdmi_spec_per_pin *per_pin;
75fae117 1947 int pinctl;
f69548ff 1948 int err = 0;
384a48d7 1949
384a48d7 1950 if (hinfo->nid) {
2bf3c85a
LY		 1951 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1952 if (snd_BUG_ON(pcm_idx < 0))
1953 return -EINVAL;
4e76a883 1954 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
384a48d7
SW		 1955 if (snd_BUG_ON(cvt_idx < 0))
1956 return -EINVAL;
bce0d2a8 1957 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1958
1959 snd_BUG_ON(!per_cvt->assigned);
1960 per_cvt->assigned = 0;
1961 hinfo->nid = 0;
1962
42b29870 1963 mutex_lock(&spec->pcm_lock);
b09887f8 1964 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
ac98379a 1965 clear_bit(pcm_idx, &spec->pcm_in_use);
4e76a883 1966 pin_idx = hinfo_to_pin_index(codec, hinfo);
f69548ff
TI		 1967 if (spec->dyn_pcm_assign && pin_idx < 0)
1968 goto unlock;
42b29870
LY		 1969
1970 if (snd_BUG_ON(pin_idx < 0)) {
f69548ff
TI		 1971 err = -EINVAL;
1972 goto unlock;
42b29870 1973 }
bce0d2a8 1974 per_pin = get_pin(spec, pin_idx);
384a48d7 1975
75fae117
SW		 1976 if (spec->dyn_pin_out) {
1977 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1978 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1979 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1980 AC_VERB_SET_PIN_WIDGET_CONTROL,
1981 pinctl & ~PIN_OUT);
1982 }
1983
a4e9a38b 1984 mutex_lock(&per_pin->lock);
d45e6889
TI		 1985 per_pin->chmap_set = false;
1986 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
b054087d
TI		 1987
1988 per_pin->setup = false;
1989 per_pin->channels = 0;
a4e9a38b 1990 mutex_unlock(&per_pin->lock);
f69548ff 1991 unlock:
42b29870 1992 mutex_unlock(&spec->pcm_lock);
384a48d7 1993 }
d45e6889 1994
f69548ff 1995 return err;
384a48d7
SW		 1996}
1997
1998static const struct hda_pcm_ops generic_ops = {
1999 .open = hdmi_pcm_open,
f2ad24fa 2000 .close = hdmi_pcm_close,
384a48d7 2001 .prepare = generic_hdmi_playback_pcm_prepare,
8dfaa573 2002 .cleanup = generic_hdmi_playback_pcm_cleanup,
84eb01be
TI		 2003};
2004
44fde3b8
SP		 2005static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx)
2006{
2007 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2008 struct hdmi_spec *spec = codec->spec;
2009 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2010
2011 if (!per_pin)
2012 return 0;
2013
2014 return per_pin->sink_eld.info.spk_alloc;
2015}
2016
9b3dc8aa
SP		 2017static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx,
2018 unsigned char *chmap)
2019{
2020 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2021 struct hdmi_spec *spec = codec->spec;
2022 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2023
2024 /* chmap is already set to 0 in caller */
2025 if (!per_pin)
2026 return;
2027
2028 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap));
2029}
2030
2031static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx,
2032 unsigned char *chmap, int prepared)
2033{
2034 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2035 struct hdmi_spec *spec = codec->spec;
2036 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2037
ed0739b5
LY		 2038 if (!per_pin)
2039 return;
9b3dc8aa
SP		 2040 mutex_lock(&per_pin->lock);
2041 per_pin->chmap_set = true;
2042 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap));
2043 if (prepared)
2044 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2045 mutex_unlock(&per_pin->lock);
2046}
2047
2048static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx)
2049{
2050 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2051 struct hdmi_spec *spec = codec->spec;
2052 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2053
2054 return per_pin ? true:false;
2055}
2056
84eb01be
TI		 2057static int generic_hdmi_build_pcms(struct hda_codec *codec)
2058{
2059 struct hdmi_spec *spec = codec->spec;
2a2edfbb 2060 int idx, pcm_num;
84eb01be 2061
9152085d
LY		 2062 /*
2063 * for non-mst mode, pcm number is the same as before
2a2edfbb
KV		 2064 * for DP MST mode without extra PCM, pcm number is same
2065 * for DP MST mode with extra PCMs, pcm number is
2066 * (nid number + dev_num - 1)
2067 * dev_num is the device entry number in a pin
9152085d 2068 */
2a2edfbb
KV		 2069
2070 if (codec->mst_no_extra_pcms)
2071 pcm_num = spec->num_nids;
2072 else
2073 pcm_num = spec->num_nids + spec->dev_num - 1;
2074
2075 codec_dbg(codec, "hdmi: pcm_num set to %d\n", pcm_num);
2076
2077 for (idx = 0; idx < pcm_num; idx++) {
384a48d7 2078 struct hda_pcm *info;
84eb01be 2079 struct hda_pcm_stream *pstr;
bce0d2a8 2080
9152085d 2081 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx);
bce0d2a8
TI		 2082 if (!info)
2083 return -ENOMEM;
2bea241a 2084
9152085d 2085 spec->pcm_rec[idx].pcm = info;
2bf3c85a 2086 spec->pcm_used++;
84eb01be 2087 info->pcm_type = HDA_PCM_TYPE_HDMI;
d45e6889 2088 info->own_chmap = true;
384a48d7 2089
84eb01be 2090 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
384a48d7
SW		 2091 pstr->substreams = 1;
2092 pstr->ops = generic_ops;
9152085d
LY		 2093 /* pcm number is less than 16 */
2094 if (spec->pcm_used >= 16)
2095 break;
384a48d7 2096 /* other pstr fields are set in open */
84eb01be
TI		 2097 }
2098
2099 return 0;
2100}
2101
25e4abb3 2102static void free_hdmi_jack_priv(struct snd_jack *jack)
788d441a 2103{
25e4abb3 2104 struct hdmi_pcm *pcm = jack->private_data;
788d441a 2105
25e4abb3 2106 pcm->jack = NULL;
788d441a
TI		 2107}
2108
25e4abb3
LY		 2109static int add_hdmi_jack_kctl(struct hda_codec *codec,
2110 struct hdmi_spec *spec,
2111 int pcm_idx,
788d441a
TI		 2112 const char *name)
2113{
2114 struct snd_jack *jack;
2115 int err;
2116
2117 err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack,
2118 true, false);
2119 if (err < 0)
2120 return err;
25e4abb3
LY		 2121
2122 spec->pcm_rec[pcm_idx].jack = jack;
2123 jack->private_data = &spec->pcm_rec[pcm_idx];
2124 jack->private_free = free_hdmi_jack_priv;
788d441a
TI		 2125 return 0;
2126}
2127
25e4abb3 2128static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
0b6c49b5 2129{
31ef2257 2130 char hdmi_str[32] = "HDMI/DP";
0b6c49b5 2131 struct hdmi_spec *spec = codec->spec;
25e4abb3
LY		 2132 struct hdmi_spec_per_pin *per_pin;
2133 struct hda_jack_tbl *jack;
2134 int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
909cadc6 2135 bool phantom_jack;
25e4abb3 2136 int ret;
0b6c49b5 2137
31ef2257
TI		 2138 if (pcmdev > 0)
2139 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
25e4abb3
LY		 2140
2141 if (spec->dyn_pcm_assign)
2142 return add_hdmi_jack_kctl(codec, spec, pcm_idx, hdmi_str);
2143
2144 /* for !dyn_pcm_assign, we still use hda_jack for compatibility */
2145 /* if !dyn_pcm_assign, it must be non-MST mode.
2146 * This means pcms and pins are statically mapped.
2147 * And pcm_idx is pin_idx.
2148 */
2149 per_pin = get_pin(spec, pcm_idx);
909cadc6
TI		 2150 phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid);
2151 if (phantom_jack)
30efd8de
DH		 2152 strncat(hdmi_str, " Phantom",
2153 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
25e4abb3 2154 ret = snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str,
911761c2 2155 phantom_jack, 0, NULL);
25e4abb3
LY		 2156 if (ret < 0)
2157 return ret;
2158 jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
2159 if (jack == NULL)
2160 return 0;
2161 /* assign jack->jack to pcm_rec[].jack to
2162 * align with dyn_pcm_assign mode
2163 */
2164 spec->pcm_rec[pcm_idx].jack = jack->jack;
2165 return 0;
0b6c49b5
DH		 2166}
2167
84eb01be
TI		 2168static int generic_hdmi_build_controls(struct hda_codec *codec)
2169{
2170 struct hdmi_spec *spec = codec->spec;
1f7f51a6 2171 int dev, err;
25e4abb3 2172 int pin_idx, pcm_idx;
84eb01be 2173
25e4abb3 2174 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
8a7d6003
TI		 2175 if (!get_pcm_rec(spec, pcm_idx)->pcm) {
2176 /* no PCM: mark this for skipping permanently */
2177 set_bit(pcm_idx, &spec->pcm_bitmap);
2178 continue;
2179 }
2180
25e4abb3 2181 err = generic_hdmi_build_jack(codec, pcm_idx);
0b6c49b5
DH		 2182 if (err < 0)
2183 return err;
2184
b09887f8
LY		 2185 /* create the spdif for each pcm
2186 * pin will be bound when monitor is connected
2187 */
2188 if (spec->dyn_pcm_assign)
2189 err = snd_hda_create_dig_out_ctls(codec,
2190 0, spec->cvt_nids[0],
2191 HDA_PCM_TYPE_HDMI);
2192 else {
2193 struct hdmi_spec_per_pin *per_pin =
2194 get_pin(spec, pcm_idx);
2195 err = snd_hda_create_dig_out_ctls(codec,
dcda5806
TI		 2196 per_pin->pin_nid,
2197 per_pin->mux_nids[0],
2198 HDA_PCM_TYPE_HDMI);
b09887f8 2199 }
84eb01be
TI		 2200 if (err < 0)
2201 return err;
b09887f8 2202 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
14bc52b8 2203
1f7f51a6
WY		 2204 dev = get_pcm_rec(spec, pcm_idx)->device;
2205 if (dev != SNDRV_PCM_INVALID_DEVICE) {
2206 /* add control for ELD Bytes */
2207 err = hdmi_create_eld_ctl(codec, pcm_idx, dev);
2208 if (err < 0)
2209 return err;
2210 }
fb087eaa
LY		 2211 }
2212
2213 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2214 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
31ef2257 2215
82b1d73f 2216 hdmi_present_sense(per_pin, 0);
84eb01be
TI		 2217 }
2218
d45e6889 2219 /* add channel maps */
022f344b 2220 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
bbbc7e85 2221 struct hda_pcm *pcm;
2ca320e2 2222
022f344b 2223 pcm = get_pcm_rec(spec, pcm_idx);
bbbc7e85 2224 if (!pcm || !pcm->pcm)
2ca320e2 2225 break;
2f6e8a85 2226 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap);
d45e6889
TI		 2227 if (err < 0)
2228 return err;
d45e6889
TI		 2229 }
2230
84eb01be
TI		 2231 return 0;
2232}
2233
8b8d654b 2234static int generic_hdmi_init_per_pins(struct hda_codec *codec)
84eb01be
TI		 2235{
2236 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 2237 int pin_idx;
2238
2239 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2240 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
84eb01be 2241
744626da 2242 per_pin->codec = codec;
a4e9a38b 2243 mutex_init(&per_pin->lock);
744626da 2244 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
a4e9a38b 2245 eld_proc_new(per_pin, pin_idx);
84eb01be 2246 }
8b8d654b
TI		 2247 return 0;
2248}
2249
2250static int generic_hdmi_init(struct hda_codec *codec)
2251{
2252 struct hdmi_spec *spec = codec->spec;
2253 int pin_idx;
2254
302d5a80 2255 mutex_lock(&spec->bind_lock);
ade49db3 2256 spec->use_jack_detect = !codec->jackpoll_interval;
8b8d654b 2257 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2258 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
8b8d654b 2259 hda_nid_t pin_nid = per_pin->pin_nid;
9152085d 2260 int dev_id = per_pin->dev_id;
8b8d654b 2261
9152085d 2262 snd_hda_set_dev_select(codec, pin_nid, dev_id);
8b8d654b 2263 hdmi_init_pin(codec, pin_nid);
ade49db3
TI		 2264 if (codec_has_acomp(codec))
2265 continue;
2266 if (spec->use_jack_detect)
2267 snd_hda_jack_detect_enable(codec, pin_nid);
2268 else
788d441a 2269 snd_hda_jack_detect_enable_callback(codec, pin_nid,
ade49db3 2270 jack_callback);
8b8d654b 2271 }
302d5a80 2272 mutex_unlock(&spec->bind_lock);
84eb01be
TI		 2273 return 0;
2274}
2275
bce0d2a8
TI		 2276static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2277{
2278 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2279 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
bce0d2a8
TI		 2280}
2281
2282static void hdmi_array_free(struct hdmi_spec *spec)
2283{
2284 snd_array_free(&spec->pins);
2285 snd_array_free(&spec->cvts);
bce0d2a8
TI		 2286}
2287
a686632f
TI		 2288static void generic_spec_free(struct hda_codec *codec)
2289{
2290 struct hdmi_spec *spec = codec->spec;
2291
2292 if (spec) {
2293 hdmi_array_free(spec);
2294 kfree(spec);
2295 codec->spec = NULL;
2296 }
2297 codec->dp_mst = false;
2298}
2299
84eb01be
TI		 2300static void generic_hdmi_free(struct hda_codec *codec)
2301{
2302 struct hdmi_spec *spec = codec->spec;
25e4abb3 2303 int pin_idx, pcm_idx;
384a48d7 2304
ade49db3
TI		 2305 if (spec->acomp_registered) {
2306 snd_hdac_acomp_exit(&codec->bus->core);
2307 } else if (codec_has_acomp(codec)) {
a57942bf 2308 snd_hdac_acomp_register_notifier(&codec->bus->core, NULL);
4914da2f
TI		 2309 codec->relaxed_resume = 0;
2310 }
25adc137 2311
384a48d7 2312 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2313 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2f35c630 2314 cancel_delayed_work_sync(&per_pin->work);
a4e9a38b 2315 eld_proc_free(per_pin);
25e4abb3
LY		 2316 }
2317
2318 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2319 if (spec->pcm_rec[pcm_idx].jack == NULL)
2320 continue;
2321 if (spec->dyn_pcm_assign)
2322 snd_device_free(codec->card,
2323 spec->pcm_rec[pcm_idx].jack);
2324 else
2325 spec->pcm_rec[pcm_idx].jack = NULL;
384a48d7 2326 }
84eb01be 2327
a686632f 2328 generic_spec_free(codec);
84eb01be
TI		 2329}
2330
28cb72e5
WX		 2331#ifdef CONFIG_PM
2332static int generic_hdmi_resume(struct hda_codec *codec)
2333{
2334 struct hdmi_spec *spec = codec->spec;
2335 int pin_idx;
2336
a2833683 2337 codec->patch_ops.init(codec);
eeecd9d1 2338 regcache_sync(codec->core.regmap);
28cb72e5
WX		 2339
2340 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2341 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2342 hdmi_present_sense(per_pin, 1);
2343 }
2344 return 0;
2345}
2346#endif
2347
fb79e1e0 2348static const struct hda_codec_ops generic_hdmi_patch_ops = {
84eb01be
TI		 2349 .init = generic_hdmi_init,
2350 .free = generic_hdmi_free,
2351 .build_pcms = generic_hdmi_build_pcms,
2352 .build_controls = generic_hdmi_build_controls,
2353 .unsol_event = hdmi_unsol_event,
28cb72e5
WX		 2354#ifdef CONFIG_PM
2355 .resume = generic_hdmi_resume,
2356#endif
84eb01be
TI		 2357};
2358
307229d2
AH		 2359static const struct hdmi_ops generic_standard_hdmi_ops = {
2360 .pin_get_eld = snd_hdmi_get_eld,
307229d2
AH		 2361 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2362 .pin_hbr_setup = hdmi_pin_hbr_setup,
2363 .setup_stream = hdmi_setup_stream,
67b90cb8
SP		 2364};
2365
a686632f
TI		 2366/* allocate codec->spec and assign/initialize generic parser ops */
2367static int alloc_generic_hdmi(struct hda_codec *codec)
2368{
2369 struct hdmi_spec *spec;
2370
2371 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2372 if (!spec)
2373 return -ENOMEM;
2374
ade49db3 2375 spec->codec = codec;
a686632f 2376 spec->ops = generic_standard_hdmi_ops;
9152085d 2377 spec->dev_num = 1; /* initialize to 1 */
a686632f 2378 mutex_init(&spec->pcm_lock);
302d5a80 2379 mutex_init(&spec->bind_lock);
a686632f
TI		 2380 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap);
2381
2382 spec->chmap.ops.get_chmap = hdmi_get_chmap;
2383 spec->chmap.ops.set_chmap = hdmi_set_chmap;
2384 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached;
44fde3b8 2385 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc,
a686632f
TI		 2386
2387 codec->spec = spec;
2388 hdmi_array_init(spec, 4);
2389
2390 codec->patch_ops = generic_hdmi_patch_ops;
2391
2392 return 0;
2393}
2394
2395/* generic HDMI parser */
2396static int patch_generic_hdmi(struct hda_codec *codec)
2397{
2398 int err;
2399
2400 err = alloc_generic_hdmi(codec);
2401 if (err < 0)
2402 return err;
2403
2404 err = hdmi_parse_codec(codec);
2405 if (err < 0) {
2406 generic_spec_free(codec);
2407 return err;
2408 }
2409
2410 generic_hdmi_init_per_pins(codec);
2411 return 0;
2412}
2413
ade49db3
TI		 2414/*
2415 * generic audio component binding
2416 */
2417
2418/* turn on / off the unsol event jack detection dynamically */
2419static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid,
2420 bool use_acomp)
2421{
2422 struct hda_jack_tbl *tbl;
2423
2424 tbl = snd_hda_jack_tbl_get(codec, nid);
2425 if (tbl) {
2426 /* clear unsol even if component notifier is used, or re-enable
2427 * if notifier is cleared
2428 */
2429 unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag);
2430 snd_hda_codec_write_cache(codec, nid, 0,
2431 AC_VERB_SET_UNSOLICITED_ENABLE, val);
2432 } else {
2433 /* if no jack entry was defined beforehand, create a new one
2434 * at need (i.e. only when notifier is cleared)
2435 */
2436 if (!use_acomp)
2437 snd_hda_jack_detect_enable(codec, nid);
2438 }
2439}
2440
2441/* set up / clear component notifier dynamically */
2442static void generic_acomp_notifier_set(struct drm_audio_component *acomp,
2443 bool use_acomp)
2444{
2445 struct hdmi_spec *spec;
2446 int i;
2447
2448 spec = container_of(acomp->audio_ops, struct hdmi_spec, drm_audio_ops);
302d5a80 2449 mutex_lock(&spec->bind_lock);
ade49db3
TI		 2450 spec->use_acomp_notifier = use_acomp;
2451 spec->codec->relaxed_resume = use_acomp;
2452 /* reprogram each jack detection logic depending on the notifier */
2453 if (spec->use_jack_detect) {
2454 for (i = 0; i < spec->num_pins; i++)
2455 reprogram_jack_detect(spec->codec,
2456 get_pin(spec, i)->pin_nid,
2457 use_acomp);
2458 }
302d5a80 2459 mutex_unlock(&spec->bind_lock);
ade49db3
TI		 2460}
2461
2462/* enable / disable the notifier via master bind / unbind */
2463static int generic_acomp_master_bind(struct device *dev,
2464 struct drm_audio_component *acomp)
2465{
2466 generic_acomp_notifier_set(acomp, true);
2467 return 0;
2468}
2469
2470static void generic_acomp_master_unbind(struct device *dev,
2471 struct drm_audio_component *acomp)
2472{
2473 generic_acomp_notifier_set(acomp, false);
2474}
2475
2476/* check whether both HD-audio and DRM PCI devices belong to the same bus */
2477static int match_bound_vga(struct device *dev, int subtype, void *data)
2478{
2479 struct hdac_bus *bus = data;
2480 struct pci_dev *pci, *master;
2481
2482 if (!dev_is_pci(dev) || !dev_is_pci(bus->dev))
2483 return 0;
2484 master = to_pci_dev(bus->dev);
2485 pci = to_pci_dev(dev);
2486 return master->bus == pci->bus;
2487}
2488
2489/* audio component notifier for AMD/Nvidia HDMI codecs */
2490static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id)
2491{
2492 struct hda_codec *codec = audio_ptr;
2493 struct hdmi_spec *spec = codec->spec;
2494 hda_nid_t pin_nid = spec->port2pin(codec, port);
2495
2496 if (!pin_nid)
2497 return;
2498 if (get_wcaps_type(get_wcaps(codec, pin_nid)) != AC_WID_PIN)
2499 return;
2500 /* skip notification during system suspend (but not in runtime PM);
2501 * the state will be updated at resume
2502 */
2503 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2504 return;
2505 /* ditto during suspend/resume process itself */
2506 if (snd_hdac_is_in_pm(&codec->core))
2507 return;
2508
2509 check_presence_and_report(codec, pin_nid, dev_id);
2510}
2511
2512/* set up the private drm_audio_ops from the template */
2513static void setup_drm_audio_ops(struct hda_codec *codec,
2514 const struct drm_audio_component_audio_ops *ops)
2515{
2516 struct hdmi_spec *spec = codec->spec;
2517
2518 spec->drm_audio_ops.audio_ptr = codec;
2519 /* intel_audio_codec_enable() or intel_audio_codec_disable()
2520 * will call pin_eld_notify with using audio_ptr pointer
2521 * We need make sure audio_ptr is really setup
2522 */
2523 wmb();
2524 spec->drm_audio_ops.pin2port = ops->pin2port;
2525 spec->drm_audio_ops.pin_eld_notify = ops->pin_eld_notify;
2526 spec->drm_audio_ops.master_bind = ops->master_bind;
2527 spec->drm_audio_ops.master_unbind = ops->master_unbind;
2528}
2529
2530/* initialize the generic HDMI audio component */
2531static void generic_acomp_init(struct hda_codec *codec,
2532 const struct drm_audio_component_audio_ops *ops,
2533 int (*port2pin)(struct hda_codec *, int))
2534{
2535 struct hdmi_spec *spec = codec->spec;
2536
2537 spec->port2pin = port2pin;
2538 setup_drm_audio_ops(codec, ops);
2539 if (!snd_hdac_acomp_init(&codec->bus->core, &spec->drm_audio_ops,
dd23e1d5 2540 match_bound_vga, 0)) {
ade49db3 2541 spec->acomp_registered = true;
dd23e1d5
TI		 2542 codec->bus->keep_power = 0;
2543 }
ade49db3
TI		 2544}
2545
a686632f
TI		 2546/*
2547 * Intel codec parsers and helpers
2548 */
2549
c88d4e84
TI		 2550static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2551 hda_nid_t nid)
2552{
2553 struct hdmi_spec *spec = codec->spec;
2554 hda_nid_t conns[4];
2555 int nconns;
6ffe168f 2556
c88d4e84
TI		 2557 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2558 if (nconns == spec->num_cvts &&
2559 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
6ffe168f
ML		 2560 return;
2561
c88d4e84 2562 /* override pins connection list */
4e76a883 2563 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
c88d4e84 2564 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
6ffe168f
ML		 2565}
2566
b0d8bc50
JK		 2567#define INTEL_GET_VENDOR_VERB 0xf81
2568#define INTEL_SET_VENDOR_VERB 0x781
2569#define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2570#define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
1611a9c9
ML		 2571
2572static void intel_haswell_enable_all_pins(struct hda_codec *codec,
17df3f55 2573 bool update_tree)
1611a9c9
ML		 2574{
2575 unsigned int vendor_param;
a87a4d23 2576 struct hdmi_spec *spec = codec->spec;
1611a9c9 2577
a87a4d23 2578 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
1611a9c9
ML		 2579 INTEL_GET_VENDOR_VERB, 0);
2580 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2581 return;
2582
2583 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
a87a4d23 2584 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
1611a9c9
ML		 2585 INTEL_SET_VENDOR_VERB, vendor_param);
2586 if (vendor_param == -1)
2587 return;
2588
17df3f55
TI		 2589 if (update_tree)
2590 snd_hda_codec_update_widgets(codec);
1611a9c9
ML		 2591}
2592
c88d4e84
TI		 2593static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2594{
2595 unsigned int vendor_param;
a87a4d23 2596 struct hdmi_spec *spec = codec->spec;
c88d4e84 2597
a87a4d23 2598 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
c88d4e84
TI		 2599 INTEL_GET_VENDOR_VERB, 0);
2600 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2601 return;
2602
2603 /* enable DP1.2 mode */
2604 vendor_param |= INTEL_EN_DP12;
a551d914 2605 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
a87a4d23 2606 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0,
c88d4e84
TI		 2607 INTEL_SET_VENDOR_VERB, vendor_param);
2608}
2609
17df3f55
TI		 2610/* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2611 * Otherwise you may get severe h/w communication errors.
2612 */
2613static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2614 unsigned int power_state)
2615{
2616 if (power_state == AC_PWRST_D0) {
2617 intel_haswell_enable_all_pins(codec, false);
2618 intel_haswell_fixup_enable_dp12(codec);
2619 }
c88d4e84 2620
17df3f55
TI		 2621 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2622 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2623}
6ffe168f 2624
a57942bf
TI		 2625/* There is a fixed mapping between audio pin node and display port.
2626 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL:
2627 * Pin Widget 5 - PORT B (port = 1 in i915 driver)
2628 * Pin Widget 6 - PORT C (port = 2 in i915 driver)
2629 * Pin Widget 7 - PORT D (port = 3 in i915 driver)
2630 *
2631 * on VLV, ILK:
2632 * Pin Widget 4 - PORT B (port = 1 in i915 driver)
2633 * Pin Widget 5 - PORT C (port = 2 in i915 driver)
2634 * Pin Widget 6 - PORT D (port = 3 in i915 driver)
2635 */
2636static int intel_base_nid(struct hda_codec *codec)
2637{
2638 switch (codec->core.vendor_id) {
2639 case 0x80860054: /* ILK */
2640 case 0x80862804: /* ILK */
2641 case 0x80862882: /* VLV */
2642 return 4;
2643 default:
2644 return 5;
2645 }
2646}
2647
2648static int intel_pin2port(void *audio_ptr, int pin_nid)
2649{
b0d8bc50
JK		 2650 struct hda_codec *codec = audio_ptr;
2651 struct hdmi_spec *spec = codec->spec;
2652 int base_nid, i;
a57942bf 2653
b0d8bc50
JK		 2654 if (!spec->port_num) {
2655 base_nid = intel_base_nid(codec);
2656 if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3))
2657 return -1;
2658 return pin_nid - base_nid + 1; /* intel port is 1-based */
2659 }
2660
2661 /*
2662 * looking for the pin number in the mapping table and return
2663 * the index which indicate the port number
2664 */
2665 for (i = 0; i < spec->port_num; i++) {
2666 if (pin_nid == spec->port_map[i])
d577cf76 2667 return i;
b0d8bc50
JK		 2668 }
2669
2670 /* return -1 if pin number exceeds our expectation */
2671 codec_info(codec, "Can't find the HDMI/DP port for pin %d\n", pin_nid);
2672 return -1;
a57942bf
TI		 2673}
2674
3140aafb
TI		 2675static int intel_port2pin(struct hda_codec *codec, int port)
2676{
2677 struct hdmi_spec *spec = codec->spec;
2678
2679 if (!spec->port_num) {
2680 /* we assume only from port-B to port-D */
2681 if (port < 1 || port > 3)
2682 return 0;
2683 /* intel port is 1-based */
2684 return port + intel_base_nid(codec) - 1;
2685 }
2686
d577cf76 2687 if (port < 0 || port >= spec->port_num)
3140aafb 2688 return 0;
d577cf76 2689 return spec->port_map[port];
3140aafb
TI		 2690}
2691
f9318941 2692static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe)
25adc137
DH		 2693{
2694 struct hda_codec *codec = audio_ptr;
7ff652ff 2695 int pin_nid;
9152085d 2696 int dev_id = pipe;
25adc137 2697
3140aafb
TI		 2698 pin_nid = intel_port2pin(codec, port);
2699 if (!pin_nid)
4f8e4f35 2700 return;
8ae743e8
TI		 2701 /* skip notification during system suspend (but not in runtime PM);
2702 * the state will be updated at resume
2703 */
2704 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2705 return;
eb399d3c 2706 /* ditto during suspend/resume process itself */
feb20fae 2707 if (snd_hdac_is_in_pm(&codec->core))
eb399d3c 2708 return;
8ae743e8 2709
bb03ed21 2710 snd_hdac_i915_set_bclk(&codec->bus->core);
9152085d 2711 check_presence_and_report(codec, pin_nid, dev_id);
25adc137
DH		 2712}
2713
ade49db3
TI		 2714static const struct drm_audio_component_audio_ops intel_audio_ops = {
2715 .pin2port = intel_pin2port,
2716 .pin_eld_notify = intel_pin_eld_notify,
2717};
2718
a686632f
TI		 2719/* register i915 component pin_eld_notify callback */
2720static void register_i915_notifier(struct hda_codec *codec)
84eb01be 2721{
a686632f 2722 struct hdmi_spec *spec = codec->spec;
84eb01be 2723
a686632f 2724 spec->use_acomp_notifier = true;
ade49db3
TI		 2725 spec->port2pin = intel_port2pin;
2726 setup_drm_audio_ops(codec, &intel_audio_ops);
a57942bf 2727 snd_hdac_acomp_register_notifier(&codec->bus->core,
82887c0b 2728 &spec->drm_audio_ops);
4914da2f
TI		 2729 /* no need for forcible resume for jack check thanks to notifier */
2730 codec->relaxed_resume = 1;
a686632f 2731}
84eb01be 2732
2c1c9b86
TI		 2733/* setup_stream ops override for HSW+ */
2734static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
2735 hda_nid_t pin_nid, u32 stream_tag, int format)
2736{
2737 haswell_verify_D0(codec, cvt_nid, pin_nid);
2738 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
2739}
739ffee9 2740
4846a67e
TI		 2741/* pin_cvt_fixup ops override for HSW+ and VLV+ */
2742static void i915_pin_cvt_fixup(struct hda_codec *codec,
2743 struct hdmi_spec_per_pin *per_pin,
2744 hda_nid_t cvt_nid)
2745{
2746 if (per_pin) {
9152085d
LY		 2747 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2748 per_pin->dev_id);
4846a67e
TI		 2749 intel_verify_pin_cvt_connect(codec, per_pin);
2750 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
9152085d 2751 per_pin->dev_id, per_pin->mux_idx);
4846a67e 2752 } else {
9152085d 2753 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid);
4846a67e
TI		 2754 }
2755}
739ffee9 2756
43f6c8d9
TI		 2757/* precondition and allocation for Intel codecs */
2758static int alloc_intel_hdmi(struct hda_codec *codec)
a686632f 2759{
f2dbe87c
TI		 2760 int err;
2761
43f6c8d9 2762 /* requires i915 binding */
a686632f
TI		 2763 if (!codec->bus->core.audio_component) {
2764 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
fdd49c51
TI		 2765 /* set probe_id here to prevent generic fallback binding */
2766 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE;
a686632f 2767 return -ENODEV;
691be973 2768 }
55913110 2769
f2dbe87c
TI		 2770 err = alloc_generic_hdmi(codec);
2771 if (err < 0)
2772 return err;
2773 /* no need to handle unsol events */
2774 codec->patch_ops.unsol_event = NULL;
2775 return 0;
43f6c8d9
TI		 2776}
2777
2778/* parse and post-process for Intel codecs */
2779static int parse_intel_hdmi(struct hda_codec *codec)
2780{
2781 int err;
2782
2783 err = hdmi_parse_codec(codec);
2784 if (err < 0) {
2785 generic_spec_free(codec);
2786 return err;
2787 }
2788
2789 generic_hdmi_init_per_pins(codec);
2790 register_i915_notifier(codec);
2791 return 0;
2792}
2793
2794/* Intel Haswell and onwards; audio component with eld notifier */
b0d8bc50
JK		 2795static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid,
2796 const int *port_map, int port_num)
43f6c8d9
TI		 2797{
2798 struct hdmi_spec *spec;
2799 int err;
2800
2801 err = alloc_intel_hdmi(codec);
a686632f
TI		 2802 if (err < 0)
2803 return err;
2804 spec = codec->spec;
9152085d
LY		 2805 codec->dp_mst = true;
2806 spec->dyn_pcm_assign = true;
a87a4d23 2807 spec->vendor_nid = vendor_nid;
b0d8bc50
JK		 2808 spec->port_map = port_map;
2809 spec->port_num = port_num;
cb45722b 2810 spec->intel_hsw_fixup = true;
6ffe168f 2811
a686632f
TI		 2812 intel_haswell_enable_all_pins(codec, true);
2813 intel_haswell_fixup_enable_dp12(codec);
2814
46594d33 2815 codec->display_power_control = 1;
2bd1f73f 2816
a686632f 2817 codec->patch_ops.set_power_state = haswell_set_power_state;
a686632f
TI		 2818 codec->depop_delay = 0;
2819 codec->auto_runtime_pm = 1;
2820
2c1c9b86 2821 spec->ops.setup_stream = i915_hsw_setup_stream;
4846a67e 2822 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2c1c9b86 2823
43f6c8d9 2824 return parse_intel_hdmi(codec);
a686632f
TI		 2825}
2826
a87a4d23
ACDO		 2827static int patch_i915_hsw_hdmi(struct hda_codec *codec)
2828{
b0d8bc50 2829 return intel_hsw_common_init(codec, 0x08, NULL, 0);
a87a4d23
ACDO		 2830}
2831
2832static int patch_i915_glk_hdmi(struct hda_codec *codec)
2833{
b0d8bc50
JK		 2834 return intel_hsw_common_init(codec, 0x0b, NULL, 0);
2835}
2836
2837static int patch_i915_icl_hdmi(struct hda_codec *codec)
2838{
2839 /*
2840 * pin to port mapping table where the value indicate the pin number and
d577cf76 2841 * the index indicate the port number.
b0d8bc50 2842 */
d577cf76 2843 static const int map[] = {0x0, 0x4, 0x6, 0x8, 0xa, 0xb};
b0d8bc50
JK		 2844
2845 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map));
a87a4d23
ACDO		 2846}
2847
9a11ba73
KV		 2848static int patch_i915_tgl_hdmi(struct hda_codec *codec)
2849{
2850 /*
2851 * pin to port mapping table where the value indicate the pin number and
d577cf76 2852 * the index indicate the port number.
9a11ba73
KV		 2853 */
2854 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf};
2855
2856 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map));
2857}
2858
2859
7ff652ff 2860/* Intel Baytrail and Braswell; with eld notifier */
a686632f
TI		 2861static int patch_i915_byt_hdmi(struct hda_codec *codec)
2862{
2863 struct hdmi_spec *spec;
2864 int err;
2865
43f6c8d9 2866 err = alloc_intel_hdmi(codec);
a686632f
TI		 2867 if (err < 0)
2868 return err;
2869 spec = codec->spec;
2377c3c3 2870
a686632f
TI		 2871 /* For Valleyview/Cherryview, only the display codec is in the display
2872 * power well and can use link_power ops to request/release the power.
2873 */
029d92c2 2874 codec->display_power_control = 1;
84eb01be 2875
a686632f
TI		 2876 codec->depop_delay = 0;
2877 codec->auto_runtime_pm = 1;
84eb01be 2878
4846a67e
TI		 2879 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2880
43f6c8d9 2881 return parse_intel_hdmi(codec);
84eb01be
TI		 2882}
2883
7ff652ff 2884/* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */
e85015a3
TI		 2885static int patch_i915_cpt_hdmi(struct hda_codec *codec)
2886{
e85015a3
TI		 2887 int err;
2888
43f6c8d9 2889 err = alloc_intel_hdmi(codec);
e85015a3
TI		 2890 if (err < 0)
2891 return err;
43f6c8d9 2892 return parse_intel_hdmi(codec);
84eb01be
TI		 2893}
2894
3aaf8980
SW		 2895/*
2896 * Shared non-generic implementations
2897 */
2898
2899static int simple_playback_build_pcms(struct hda_codec *codec)
2900{
2901 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2902 struct hda_pcm *info;
8ceb332d
TI		 2903 unsigned int chans;
2904 struct hda_pcm_stream *pstr;
bce0d2a8 2905 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2906
bce0d2a8
TI		 2907 per_cvt = get_cvt(spec, 0);
2908 chans = get_wcaps(codec, per_cvt->cvt_nid);
8ceb332d 2909 chans = get_wcaps_channels(chans);
3aaf8980 2910
bbbc7e85 2911 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
bce0d2a8
TI		 2912 if (!info)
2913 return -ENOMEM;
2bea241a 2914 spec->pcm_rec[0].pcm = info;
8ceb332d
TI		 2915 info->pcm_type = HDA_PCM_TYPE_HDMI;
2916 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2917 *pstr = spec->pcm_playback;
bce0d2a8 2918 pstr->nid = per_cvt->cvt_nid;
8ceb332d
TI		 2919 if (pstr->channels_max <= 2 && chans && chans <= 16)
2920 pstr->channels_max = chans;
3aaf8980
SW		 2921
2922 return 0;
2923}
2924
4b6ace9e
TI		 2925/* unsolicited event for jack sensing */
2926static void simple_hdmi_unsol_event(struct hda_codec *codec,
2927 unsigned int res)
2928{
9dd8cf12 2929 snd_hda_jack_set_dirty_all(codec);
4b6ace9e
TI		 2930 snd_hda_jack_report_sync(codec);
2931}
2932
2933/* generic_hdmi_build_jack can be used for simple_hdmi, too,
2934 * as long as spec->pins[] is set correctly
2935 */
2936#define simple_hdmi_build_jack generic_hdmi_build_jack
2937
3aaf8980
SW		 2938static int simple_playback_build_controls(struct hda_codec *codec)
2939{
2940 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2941 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2942 int err;
3aaf8980 2943
bce0d2a8 2944 per_cvt = get_cvt(spec, 0);
c9a6338a
AH		 2945 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2946 per_cvt->cvt_nid,
2947 HDA_PCM_TYPE_HDMI);
8ceb332d
TI		 2948 if (err < 0)
2949 return err;
2950 return simple_hdmi_build_jack(codec, 0);
3aaf8980
SW		 2951}
2952
4f0110ce
TI		 2953static int simple_playback_init(struct hda_codec *codec)
2954{
2955 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 2956 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2957 hda_nid_t pin = per_pin->pin_nid;
8ceb332d
TI		 2958
2959 snd_hda_codec_write(codec, pin, 0,
2960 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2961 /* some codecs require to unmute the pin */
2962 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2963 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2964 AMP_OUT_UNMUTE);
62f949bf 2965 snd_hda_jack_detect_enable(codec, pin);
4f0110ce
TI		 2966 return 0;
2967}
2968
3aaf8980
SW		 2969static void simple_playback_free(struct hda_codec *codec)
2970{
2971 struct hdmi_spec *spec = codec->spec;
2972
bce0d2a8 2973 hdmi_array_free(spec);
3aaf8980
SW		 2974 kfree(spec);
2975}
2976
84eb01be
TI		 2977/*
2978 * Nvidia specific implementations
2979 */
2980
2981#define Nv_VERB_SET_Channel_Allocation 0xF79
2982#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2983#define Nv_VERB_SET_Audio_Protection_On 0xF98
2984#define Nv_VERB_SET_Audio_Protection_Off 0xF99
2985
2986#define nvhdmi_master_con_nid_7x 0x04
2987#define nvhdmi_master_pin_nid_7x 0x05
2988
fb79e1e0 2989static const hda_nid_t nvhdmi_con_nids_7x[4] = {
84eb01be
TI		 2990 /*front, rear, clfe, rear_surr */
2991 0x6, 0x8, 0xa, 0xc,
2992};
2993
ceaa86ba
TI		 2994static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2995 /* set audio protect on */
2996 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2997 /* enable digital output on pin widget */
2998 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2999 {} /* terminator */
3000};
3001
3002static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
84eb01be
TI		 3003 /* set audio protect on */
3004 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
3005 /* enable digital output on pin widget */
3006 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3007 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3008 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3009 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3010 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3011 {} /* terminator */
3012};
3013
3014#ifdef LIMITED_RATE_FMT_SUPPORT
3015/* support only the safe format and rate */
3016#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
3017#define SUPPORTED_MAXBPS 16
3018#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
3019#else
3020/* support all rates and formats */
3021#define SUPPORTED_RATES \
3022 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
3023 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
3024 SNDRV_PCM_RATE_192000)
3025#define SUPPORTED_MAXBPS 24
3026#define SUPPORTED_FORMATS \
3027 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
3028#endif
3029
ceaa86ba
TI		 3030static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
3031{
3032 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
3033 return 0;
3034}
3035
3036static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
84eb01be 3037{
ceaa86ba 3038 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
84eb01be
TI		 3039 return 0;
3040}
3041
50c697ad 3042static const unsigned int channels_2_6_8[] = {
393004b2
ND		 3043 2, 6, 8
3044};
3045
50c697ad 3046static const unsigned int channels_2_8[] = {
393004b2
ND		 3047 2, 8
3048};
3049
50c697ad 3050static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
393004b2
ND		 3051 .count = ARRAY_SIZE(channels_2_6_8),
3052 .list = channels_2_6_8,
3053 .mask = 0,
3054};
3055
50c697ad 3056static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
393004b2
ND		 3057 .count = ARRAY_SIZE(channels_2_8),
3058 .list = channels_2_8,
3059 .mask = 0,
3060};
3061
84eb01be
TI		 3062static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
3063 struct hda_codec *codec,
3064 struct snd_pcm_substream *substream)
3065{
3066 struct hdmi_spec *spec = codec->spec;
50c697ad 3067 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
393004b2 3068
b9a94a9c 3069 switch (codec->preset->vendor_id) {
393004b2
ND		 3070 case 0x10de0002:
3071 case 0x10de0003:
3072 case 0x10de0005:
3073 case 0x10de0006:
3074 hw_constraints_channels = &hw_constraints_2_8_channels;
3075 break;
3076 case 0x10de0007:
3077 hw_constraints_channels = &hw_constraints_2_6_8_channels;
3078 break;
3079 default:
3080 break;
3081 }
3082
3083 if (hw_constraints_channels != NULL) {
3084 snd_pcm_hw_constraint_list(substream->runtime, 0,
3085 SNDRV_PCM_HW_PARAM_CHANNELS,
3086 hw_constraints_channels);
ad09fc9d
TI		 3087 } else {
3088 snd_pcm_hw_constraint_step(substream->runtime, 0,
3089 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
393004b2
ND		 3090 }
3091
84eb01be
TI		 3092 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3093}
3094
3095static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
3096 struct hda_codec *codec,
3097 struct snd_pcm_substream *substream)
3098{
3099 struct hdmi_spec *spec = codec->spec;
3100 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3101}
3102
3103static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3104 struct hda_codec *codec,
3105 unsigned int stream_tag,
3106 unsigned int format,
3107 struct snd_pcm_substream *substream)
3108{
3109 struct hdmi_spec *spec = codec->spec;
3110 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3111 stream_tag, format, substream);
3112}
3113
d0b1252d
TI		 3114static const struct hda_pcm_stream simple_pcm_playback = {
3115 .substreams = 1,
3116 .channels_min = 2,
3117 .channels_max = 2,
3118 .ops = {
3119 .open = simple_playback_pcm_open,
3120 .close = simple_playback_pcm_close,
3121 .prepare = simple_playback_pcm_prepare
3122 },
3123};
3124
3125static const struct hda_codec_ops simple_hdmi_patch_ops = {
3126 .build_controls = simple_playback_build_controls,
3127 .build_pcms = simple_playback_build_pcms,
3128 .init = simple_playback_init,
3129 .free = simple_playback_free,
250e41ac 3130 .unsol_event = simple_hdmi_unsol_event,
d0b1252d
TI		 3131};
3132
3133static int patch_simple_hdmi(struct hda_codec *codec,
3134 hda_nid_t cvt_nid, hda_nid_t pin_nid)
3135{
3136 struct hdmi_spec *spec;
bce0d2a8
TI		 3137 struct hdmi_spec_per_cvt *per_cvt;
3138 struct hdmi_spec_per_pin *per_pin;
d0b1252d
TI		 3139
3140 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
3141 if (!spec)
3142 return -ENOMEM;
3143
ade49db3 3144 spec->codec = codec;
d0b1252d 3145 codec->spec = spec;
bce0d2a8 3146 hdmi_array_init(spec, 1);
d0b1252d
TI		 3147
3148 spec->multiout.num_dacs = 0; /* no analog */
3149 spec->multiout.max_channels = 2;
3150 spec->multiout.dig_out_nid = cvt_nid;
3151 spec->num_cvts = 1;
3152 spec->num_pins = 1;
bce0d2a8
TI		 3153 per_pin = snd_array_new(&spec->pins);
3154 per_cvt = snd_array_new(&spec->cvts);
3155 if (!per_pin || !per_cvt) {
3156 simple_playback_free(codec);
3157 return -ENOMEM;
3158 }
3159 per_cvt->cvt_nid = cvt_nid;
3160 per_pin->pin_nid = pin_nid;
d0b1252d
TI		 3161 spec->pcm_playback = simple_pcm_playback;
3162
3163 codec->patch_ops = simple_hdmi_patch_ops;
3164
3165 return 0;
3166}
3167
1f348522
AP		 3168static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
3169 int channels)
3170{
3171 unsigned int chanmask;
3172 int chan = channels ? (channels - 1) : 1;
3173
3174 switch (channels) {
3175 default:
3176 case 0:
3177 case 2:
3178 chanmask = 0x00;
3179 break;
3180 case 4:
3181 chanmask = 0x08;
3182 break;
3183 case 6:
3184 chanmask = 0x0b;
3185 break;
3186 case 8:
3187 chanmask = 0x13;
3188 break;
3189 }
3190
3191 /* Set the audio infoframe channel allocation and checksum fields. The
3192 * channel count is computed implicitly by the hardware. */
3193 snd_hda_codec_write(codec, 0x1, 0,
3194 Nv_VERB_SET_Channel_Allocation, chanmask);
3195
3196 snd_hda_codec_write(codec, 0x1, 0,
3197 Nv_VERB_SET_Info_Frame_Checksum,
3198 (0x71 - chan - chanmask));
3199}
3200
84eb01be
TI		 3201static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
3202 struct hda_codec *codec,
3203 struct snd_pcm_substream *substream)
3204{
3205 struct hdmi_spec *spec = codec->spec;
3206 int i;
3207
3208 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
3209 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
3210 for (i = 0; i < 4; i++) {
3211 /* set the stream id */
3212 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3213 AC_VERB_SET_CHANNEL_STREAMID, 0);
3214 /* set the stream format */
3215 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3216 AC_VERB_SET_STREAM_FORMAT, 0);
3217 }
3218
1f348522
AP		 3219 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
3220 * streams are disabled. */
3221 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3222
84eb01be
TI		 3223 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3224}
3225
3226static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
3227 struct hda_codec *codec,
3228 unsigned int stream_tag,
3229 unsigned int format,
3230 struct snd_pcm_substream *substream)
3231{
3232 int chs;
112daa7a 3233 unsigned int dataDCC2, channel_id;
84eb01be 3234 int i;
7c935976 3235 struct hdmi_spec *spec = codec->spec;
e3245cdd 3236 struct hda_spdif_out *spdif;
bce0d2a8 3237 struct hdmi_spec_per_cvt *per_cvt;
84eb01be
TI		 3238
3239 mutex_lock(&codec->spdif_mutex);
bce0d2a8
TI		 3240 per_cvt = get_cvt(spec, 0);
3241 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
84eb01be
TI		 3242
3243 chs = substream->runtime->channels;
84eb01be 3244
84eb01be
TI		 3245 dataDCC2 = 0x2;
3246
84eb01be 3247 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
7c935976 3248 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 3249 snd_hda_codec_write(codec,
3250 nvhdmi_master_con_nid_7x,
3251 0,
3252 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 3253 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 3254
3255 /* set the stream id */
3256 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3257 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
3258
3259 /* set the stream format */
3260 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3261 AC_VERB_SET_STREAM_FORMAT, format);
3262
3263 /* turn on again (if needed) */
3264 /* enable and set the channel status audio/data flag */
7c935976 3265 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 3266 snd_hda_codec_write(codec,
3267 nvhdmi_master_con_nid_7x,
3268 0,
3269 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 3270 spdif->ctls & 0xff);
84eb01be
TI		 3271 snd_hda_codec_write(codec,
3272 nvhdmi_master_con_nid_7x,
3273 0,
3274 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3275 }
3276
3277 for (i = 0; i < 4; i++) {
3278 if (chs == 2)
3279 channel_id = 0;
3280 else
3281 channel_id = i * 2;
3282
3283 /* turn off SPDIF once;
3284 *otherwise the IEC958 bits won't be updated
3285 */
3286 if (codec->spdif_status_reset &&
7c935976 3287 (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 3288 snd_hda_codec_write(codec,
3289 nvhdmi_con_nids_7x[i],
3290 0,
3291 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 3292 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 3293 /* set the stream id */
3294 snd_hda_codec_write(codec,
3295 nvhdmi_con_nids_7x[i],
3296 0,
3297 AC_VERB_SET_CHANNEL_STREAMID,
3298 (stream_tag << 4) | channel_id);
3299 /* set the stream format */
3300 snd_hda_codec_write(codec,
3301 nvhdmi_con_nids_7x[i],
3302 0,
3303 AC_VERB_SET_STREAM_FORMAT,
3304 format);
3305 /* turn on again (if needed) */
3306 /* enable and set the channel status audio/data flag */
3307 if (codec->spdif_status_reset &&
7c935976 3308 (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 3309 snd_hda_codec_write(codec,
3310 nvhdmi_con_nids_7x[i],
3311 0,
3312 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 3313 spdif->ctls & 0xff);
84eb01be
TI		 3314 snd_hda_codec_write(codec,
3315 nvhdmi_con_nids_7x[i],
3316 0,
3317 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3318 }
3319 }
3320
1f348522 3321 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
84eb01be
TI		 3322
3323 mutex_unlock(&codec->spdif_mutex);
3324 return 0;
3325}
3326
fb79e1e0 3327static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
84eb01be
TI		 3328 .substreams = 1,
3329 .channels_min = 2,
3330 .channels_max = 8,
3331 .nid = nvhdmi_master_con_nid_7x,
3332 .rates = SUPPORTED_RATES,
3333 .maxbps = SUPPORTED_MAXBPS,
3334 .formats = SUPPORTED_FORMATS,
3335 .ops = {
3336 .open = simple_playback_pcm_open,
3337 .close = nvhdmi_8ch_7x_pcm_close,
3338 .prepare = nvhdmi_8ch_7x_pcm_prepare
3339 },
3340};
3341
84eb01be
TI		 3342static int patch_nvhdmi_2ch(struct hda_codec *codec)
3343{
3344 struct hdmi_spec *spec;
d0b1252d
TI		 3345 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
3346 nvhdmi_master_pin_nid_7x);
3347 if (err < 0)
3348 return err;
84eb01be 3349
ceaa86ba 3350 codec->patch_ops.init = nvhdmi_7x_init_2ch;
d0b1252d
TI		 3351 /* override the PCM rates, etc, as the codec doesn't give full list */
3352 spec = codec->spec;
3353 spec->pcm_playback.rates = SUPPORTED_RATES;
3354 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
3355 spec->pcm_playback.formats = SUPPORTED_FORMATS;
84eb01be
TI		 3356 return 0;
3357}
3358
53775b0d
TI		 3359static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
3360{
3361 struct hdmi_spec *spec = codec->spec;
3362 int err = simple_playback_build_pcms(codec);
bce0d2a8
TI		 3363 if (!err) {
3364 struct hda_pcm *info = get_pcm_rec(spec, 0);
3365 info->own_chmap = true;
3366 }
53775b0d
TI		 3367 return err;
3368}
3369
3370static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
3371{
3372 struct hdmi_spec *spec = codec->spec;
bce0d2a8 3373 struct hda_pcm *info;
53775b0d
TI		 3374 struct snd_pcm_chmap *chmap;
3375 int err;
3376
3377 err = simple_playback_build_controls(codec);
3378 if (err < 0)
3379 return err;
3380
3381 /* add channel maps */
bce0d2a8
TI		 3382 info = get_pcm_rec(spec, 0);
3383 err = snd_pcm_add_chmap_ctls(info->pcm,
53775b0d
TI		 3384 SNDRV_PCM_STREAM_PLAYBACK,
3385 snd_pcm_alt_chmaps, 8, 0, &chmap);
3386 if (err < 0)
3387 return err;
b9a94a9c 3388 switch (codec->preset->vendor_id) {
53775b0d
TI		 3389 case 0x10de0002:
3390 case 0x10de0003:
3391 case 0x10de0005:
3392 case 0x10de0006:
3393 chmap->channel_mask = (1U << 2) | (1U << 8);
3394 break;
3395 case 0x10de0007:
3396 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
3397 }
3398 return 0;
3399}
3400
84eb01be
TI		 3401static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
3402{
3403 struct hdmi_spec *spec;
3404 int err = patch_nvhdmi_2ch(codec);
84eb01be
TI		 3405 if (err < 0)
3406 return err;
3407 spec = codec->spec;
3408 spec->multiout.max_channels = 8;
d0b1252d 3409 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
ceaa86ba 3410 codec->patch_ops.init = nvhdmi_7x_init_8ch;
53775b0d
TI		 3411 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
3412 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
1f348522
AP		 3413
3414 /* Initialize the audio infoframe channel mask and checksum to something
3415 * valid */
3416 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3417
84eb01be
TI		 3418 return 0;
3419}
3420
611885bc
AH		 3421/*
3422 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
3423 * - 0x10de0015
3424 * - 0x10de0040
3425 */
67b90cb8 3426static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
f302240d 3427 struct hdac_cea_channel_speaker_allocation *cap, int channels)
611885bc
AH		 3428{
3429 if (cap->ca_index == 0x00 && channels == 2)
3430 return SNDRV_CTL_TLVT_CHMAP_FIXED;
3431
028cb68e
SP		 3432 /* If the speaker allocation matches the channel count, it is OK. */
3433 if (cap->channels != channels)
3434 return -1;
3435
3436 /* all channels are remappable freely */
3437 return SNDRV_CTL_TLVT_CHMAP_VAR;
611885bc
AH		 3438}
3439
828cb4ed
SP		 3440static int nvhdmi_chmap_validate(struct hdac_chmap *chmap,
3441 int ca, int chs, unsigned char *map)
611885bc
AH		 3442{
3443 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
3444 return -EINVAL;
3445
3446 return 0;
3447}
3448
ade49db3
TI		 3449/* map from pin NID to port; port is 0-based */
3450/* for Nvidia: assume widget NID starting from 4, with step 1 (4, 5, 6, ...) */
3451static int nvhdmi_pin2port(void *audio_ptr, int pin_nid)
3452{
3453 return pin_nid - 4;
3454}
3455
3456/* reverse-map from port to pin NID: see above */
3457static int nvhdmi_port2pin(struct hda_codec *codec, int port)
3458{
3459 return port + 4;
3460}
3461
3462static const struct drm_audio_component_audio_ops nvhdmi_audio_ops = {
3463 .pin2port = nvhdmi_pin2port,
3464 .pin_eld_notify = generic_acomp_pin_eld_notify,
3465 .master_bind = generic_acomp_master_bind,
3466 .master_unbind = generic_acomp_master_unbind,
3467};
3468
611885bc
AH		 3469static int patch_nvhdmi(struct hda_codec *codec)
3470{
3471 struct hdmi_spec *spec;
3472 int err;
3473
3474 err = patch_generic_hdmi(codec);
3475 if (err)
3476 return err;
3477
3478 spec = codec->spec;
75fae117 3479 spec->dyn_pin_out = true;
611885bc 3480
67b90cb8 3481 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
611885bc 3482 nvhdmi_chmap_cea_alloc_validate_get_type;
67b90cb8 3483 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
611885bc 3484
94989e31
LW		 3485 codec->link_down_at_suspend = 1;
3486
ade49db3
TI		 3487 generic_acomp_init(codec, &nvhdmi_audio_ops, nvhdmi_port2pin);
3488
611885bc
AH		 3489 return 0;
3490}
3491
26e9a960
TR		 3492/*
3493 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
3494 * accessed using vendor-defined verbs. These registers can be used for
3495 * interoperability between the HDA and HDMI drivers.
3496 */
3497
3498/* Audio Function Group node */
3499#define NVIDIA_AFG_NID 0x01
3500
3501/*
3502 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
3503 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3504 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3505 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3506 * additional bit (at position 30) to signal the validity of the format.
3507 *
3508 * | 31 | 30 | 29 16 | 15 0 |
3509 * +---------+-------+--------+--------+
3510 * | TRIGGER | VALID | UNUSED | FORMAT |
3511 * +-----------------------------------|
3512 *
3513 * Note that for the trigger bit to take effect it needs to change value
3514 * (i.e. it needs to be toggled).
3515 */
3516#define NVIDIA_GET_SCRATCH0 0xfa6
3517#define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
3518#define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
3519#define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
3520#define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
3521#define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3522#define NVIDIA_SCRATCH_VALID (1 << 6)
3523
3524#define NVIDIA_GET_SCRATCH1 0xfab
3525#define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
3526#define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
3527#define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
3528#define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
3529
3530/*
3531 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3532 * the format is invalidated so that the HDMI codec can be disabled.
3533 */
3534static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
3535{
3536 unsigned int value;
3537
3538 /* bits [31:30] contain the trigger and valid bits */
3539 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3540 NVIDIA_GET_SCRATCH0, 0);
3541 value = (value >> 24) & 0xff;
3542
3543 /* bits [15:0] are used to store the HDA format */
3544 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3545 NVIDIA_SET_SCRATCH0_BYTE0,
3546 (format >> 0) & 0xff);
3547 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3548 NVIDIA_SET_SCRATCH0_BYTE1,
3549 (format >> 8) & 0xff);
3550
3551 /* bits [16:24] are unused */
3552 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3553 NVIDIA_SET_SCRATCH0_BYTE2, 0);
3554
3555 /*
3556 * Bit 30 signals that the data is valid and hence that HDMI audio can
3557 * be enabled.
3558 */
3559 if (format == 0)
3560 value &= ~NVIDIA_SCRATCH_VALID;
3561 else
3562 value |= NVIDIA_SCRATCH_VALID;
3563
3564 /*
3565 * Whenever the trigger bit is toggled, an interrupt is raised in the
3566 * HDMI codec. The HDMI driver will use that as trigger to update its
3567 * configuration.
3568 */
3569 value ^= NVIDIA_SCRATCH_TRIGGER;
3570
3571 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3572 NVIDIA_SET_SCRATCH0_BYTE3, value);
3573}
3574
3575static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3576 struct hda_codec *codec,
3577 unsigned int stream_tag,
3578 unsigned int format,
3579 struct snd_pcm_substream *substream)
3580{
3581 int err;
3582
3583 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3584 format, substream);
3585 if (err < 0)
3586 return err;
3587
3588 /* notify the HDMI codec of the format change */
3589 tegra_hdmi_set_format(codec, format);
3590
3591 return 0;
3592}
3593
3594static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3595 struct hda_codec *codec,
3596 struct snd_pcm_substream *substream)
3597{
3598 /* invalidate the format in the HDMI codec */
3599 tegra_hdmi_set_format(codec, 0);
3600
3601 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3602}
3603
3604static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3605{
3606 struct hdmi_spec *spec = codec->spec;
3607 unsigned int i;
3608
3609 for (i = 0; i < spec->num_pins; i++) {
3610 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3611
3612 if (pcm->pcm_type == type)
3613 return pcm;
3614 }
3615
3616 return NULL;
3617}
3618
3619static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3620{
3621 struct hda_pcm_stream *stream;
3622 struct hda_pcm *pcm;
3623 int err;
3624
3625 err = generic_hdmi_build_pcms(codec);
3626 if (err < 0)
3627 return err;
3628
3629 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3630 if (!pcm)
3631 return -ENODEV;
3632
3633 /*
3634 * Override ->prepare() and ->cleanup() operations to notify the HDMI
3635 * codec about format changes.
3636 */
3637 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3638 stream->ops.prepare = tegra_hdmi_pcm_prepare;
3639 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3640
3641 return 0;
3642}
3643
3644static int patch_tegra_hdmi(struct hda_codec *codec)
3645{
3646 int err;
3647
3648 err = patch_generic_hdmi(codec);
3649 if (err)
3650 return err;
3651
3652 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3653
3654 return 0;
3655}
3656
84eb01be 3657/*
5a613584 3658 * ATI/AMD-specific implementations
84eb01be
TI		 3659 */
3660
5a613584 3661#define is_amdhdmi_rev3_or_later(codec) \
7639a06c
TI		 3662 ((codec)->core.vendor_id == 0x1002aa01 && \
3663 ((codec)->core.revision_id & 0xff00) >= 0x0300)
5a613584
AH		 3664#define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3665
3666/* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3667#define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3668#define ATI_VERB_SET_DOWNMIX_INFO 0x772
3669#define ATI_VERB_SET_MULTICHANNEL_01 0x777
3670#define ATI_VERB_SET_MULTICHANNEL_23 0x778
3671#define ATI_VERB_SET_MULTICHANNEL_45 0x779
3672#define ATI_VERB_SET_MULTICHANNEL_67 0x77a
461cf6b3 3673#define ATI_VERB_SET_HBR_CONTROL 0x77c
5a613584
AH		 3674#define ATI_VERB_SET_MULTICHANNEL_1 0x785
3675#define ATI_VERB_SET_MULTICHANNEL_3 0x786
3676#define ATI_VERB_SET_MULTICHANNEL_5 0x787
3677#define ATI_VERB_SET_MULTICHANNEL_7 0x788
3678#define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
3679#define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3680#define ATI_VERB_GET_DOWNMIX_INFO 0xf72
3681#define ATI_VERB_GET_MULTICHANNEL_01 0xf77
3682#define ATI_VERB_GET_MULTICHANNEL_23 0xf78
3683#define ATI_VERB_GET_MULTICHANNEL_45 0xf79
3684#define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
461cf6b3 3685#define ATI_VERB_GET_HBR_CONTROL 0xf7c
5a613584
AH		 3686#define ATI_VERB_GET_MULTICHANNEL_1 0xf85
3687#define ATI_VERB_GET_MULTICHANNEL_3 0xf86
3688#define ATI_VERB_GET_MULTICHANNEL_5 0xf87
3689#define ATI_VERB_GET_MULTICHANNEL_7 0xf88
3690#define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
3691
84d69e79
AH		 3692/* AMD specific HDA cvt verbs */
3693#define ATI_VERB_SET_RAMP_RATE 0x770
3694#define ATI_VERB_GET_RAMP_RATE 0xf70
3695
5a613584
AH		 3696#define ATI_OUT_ENABLE 0x1
3697
3698#define ATI_MULTICHANNEL_MODE_PAIRED 0
3699#define ATI_MULTICHANNEL_MODE_SINGLE 1
3700
461cf6b3
AH		 3701#define ATI_HBR_CAPABLE 0x01
3702#define ATI_HBR_ENABLE 0x10
3703
89250f84
AH		 3704static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3705 unsigned char *buf, int *eld_size)
3706{
3707 /* call hda_eld.c ATI/AMD-specific function */
3708 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3709 is_amdhdmi_rev3_or_later(codec));
3710}
3711
5a613584
AH		 3712static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
3713 int active_channels, int conn_type)
3714{
3715 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3716}
3717
3718static int atihdmi_paired_swap_fc_lfe(int pos)
3719{
3720 /*
3721 * ATI/AMD have automatic FC/LFE swap built-in
3722 * when in pairwise mapping mode.
3723 */
3724
3725 switch (pos) {
3726 /* see channel_allocations[].speakers[] */
3727 case 2: return 3;
3728 case 3: return 2;
3729 default: break;
3730 }
3731
3732 return pos;
3733}
3734
828cb4ed
SP		 3735static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap,
3736 int ca, int chs, unsigned char *map)
5a613584 3737{
f302240d 3738 struct hdac_cea_channel_speaker_allocation *cap;
5a613584
AH		 3739 int i, j;
3740
3741 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3742
bb63f726 3743 cap = snd_hdac_get_ch_alloc_from_ca(ca);
5a613584 3744 for (i = 0; i < chs; ++i) {
bb63f726 3745 int mask = snd_hdac_chmap_to_spk_mask(map[i]);
5a613584
AH		 3746 bool ok = false;
3747 bool companion_ok = false;
3748
3749 if (!mask)
3750 continue;
3751
3752 for (j = 0 + i % 2; j < 8; j += 2) {
3753 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3754 if (cap->speakers[chan_idx] == mask) {
3755 /* channel is in a supported position */
3756 ok = true;
3757
3758 if (i % 2 == 0 && i + 1 < chs) {
3759 /* even channel, check the odd companion */
3760 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
bb63f726 3761 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]);
5a613584
AH		 3762 int comp_mask_act = cap->speakers[comp_chan_idx];
3763
3764 if (comp_mask_req == comp_mask_act)
3765 companion_ok = true;
3766 else
3767 return -EINVAL;
3768 }
3769 break;
3770 }
3771 }
3772
3773 if (!ok)
3774 return -EINVAL;
3775
3776 if (companion_ok)
3777 i++; /* companion channel already checked */
3778 }
3779
3780 return 0;
3781}
3782
739ffee9
SP		 3783static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac,
3784 hda_nid_t pin_nid, int hdmi_slot, int stream_channel)
5a613584 3785{
739ffee9 3786 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
5a613584
AH		 3787 int verb;
3788 int ati_channel_setup = 0;
3789
3790 if (hdmi_slot > 7)
3791 return -EINVAL;
3792
3793 if (!has_amd_full_remap_support(codec)) {
3794 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3795
3796 /* In case this is an odd slot but without stream channel, do not
3797 * disable the slot since the corresponding even slot could have a
3798 * channel. In case neither have a channel, the slot pair will be
3799 * disabled when this function is called for the even slot. */
3800 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3801 return 0;
3802
3803 hdmi_slot -= hdmi_slot % 2;
3804
3805 if (stream_channel != 0xf)
3806 stream_channel -= stream_channel % 2;
3807 }
3808
3809 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3810
3811 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3812
3813 if (stream_channel != 0xf)
3814 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3815
3816 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3817}
3818
739ffee9
SP		 3819static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac,
3820 hda_nid_t pin_nid, int asp_slot)
5a613584 3821{
739ffee9 3822 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
5a613584
AH		 3823 bool was_odd = false;
3824 int ati_asp_slot = asp_slot;
3825 int verb;
3826 int ati_channel_setup;
3827
3828 if (asp_slot > 7)
3829 return -EINVAL;
3830
3831 if (!has_amd_full_remap_support(codec)) {
3832 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3833 if (ati_asp_slot % 2 != 0) {
3834 ati_asp_slot -= 1;
3835 was_odd = true;
3836 }
3837 }
3838
3839 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3840
3841 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3842
3843 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3844 return 0xf;
3845
3846 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3847}
84eb01be 3848
67b90cb8
SP		 3849static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
3850 struct hdac_chmap *chmap,
f302240d 3851 struct hdac_cea_channel_speaker_allocation *cap,
67b90cb8 3852 int channels)
5a613584
AH		 3853{
3854 int c;
3855
3856 /*
3857 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3858 * we need to take that into account (a single channel may take 2
3859 * channel slots if we need to carry a silent channel next to it).
3860 * On Rev3+ AMD codecs this function is not used.
3861 */
3862 int chanpairs = 0;
3863
3864 /* We only produce even-numbered channel count TLVs */
3865 if ((channels % 2) != 0)
3866 return -1;
3867
3868 for (c = 0; c < 7; c += 2) {
3869 if (cap->speakers[c] || cap->speakers[c+1])
3870 chanpairs++;
3871 }
3872
3873 if (chanpairs * 2 != channels)
3874 return -1;
3875
3876 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3877}
3878
828cb4ed 3879static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap,
f302240d
SP		 3880 struct hdac_cea_channel_speaker_allocation *cap,
3881 unsigned int *chmap, int channels)
5a613584
AH		 3882{
3883 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3884 int count = 0;
3885 int c;
3886
3887 for (c = 7; c >= 0; c--) {
3888 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3889 int spk = cap->speakers[chan];
3890 if (!spk) {
3891 /* add N/A channel if the companion channel is occupied */
3892 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3893 chmap[count++] = SNDRV_CHMAP_NA;
3894
3895 continue;
3896 }
3897
bb63f726 3898 chmap[count++] = snd_hdac_spk_to_chmap(spk);
5a613584
AH		 3899 }
3900
3901 WARN_ON(count != channels);
3902}
3903
461cf6b3
AH		 3904static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3905 bool hbr)
3906{
3907 int hbr_ctl, hbr_ctl_new;
3908
3909 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
13122e6e 3910 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
461cf6b3
AH		 3911 if (hbr)
3912 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3913 else
3914 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3915
4e76a883
TI		 3916 codec_dbg(codec,
3917 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
461cf6b3
AH		 3918 pin_nid,
3919 hbr_ctl == hbr_ctl_new ? "" : "new-",
3920 hbr_ctl_new);
3921
3922 if (hbr_ctl != hbr_ctl_new)
3923 snd_hda_codec_write(codec, pin_nid, 0,
3924 ATI_VERB_SET_HBR_CONTROL,
3925 hbr_ctl_new);
3926
3927 } else if (hbr)
3928 return -EINVAL;
3929
3930 return 0;
3931}
3932
84d69e79
AH		 3933static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3934 hda_nid_t pin_nid, u32 stream_tag, int format)
3935{
3936
3937 if (is_amdhdmi_rev3_or_later(codec)) {
3938 int ramp_rate = 180; /* default as per AMD spec */
3939 /* disable ramp-up/down for non-pcm as per AMD spec */
3940 if (format & AC_FMT_TYPE_NON_PCM)
3941 ramp_rate = 0;
3942
3943 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3944 }
3945
3946 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3947}
3948
3949
5a613584 3950static int atihdmi_init(struct hda_codec *codec)
84eb01be
TI		 3951{
3952 struct hdmi_spec *spec = codec->spec;
5a613584 3953 int pin_idx, err;
84eb01be 3954
5a613584
AH		 3955 err = generic_hdmi_init(codec);
3956
3957 if (err)
84eb01be 3958 return err;
5a613584
AH		 3959
3960 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3961 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3962
3963 /* make sure downmix information in infoframe is zero */
3964 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3965
3966 /* enable channel-wise remap mode if supported */
3967 if (has_amd_full_remap_support(codec))
3968 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3969 ATI_VERB_SET_MULTICHANNEL_MODE,
3970 ATI_MULTICHANNEL_MODE_SINGLE);
84eb01be 3971 }
5a613584 3972
84eb01be
TI		 3973 return 0;
3974}
3975
ade49db3
TI		 3976/* map from pin NID to port; port is 0-based */
3977/* for AMD: assume widget NID starting from 3, with step 2 (3, 5, 7, ...) */
3978static int atihdmi_pin2port(void *audio_ptr, int pin_nid)
3979{
3980 return pin_nid / 2 - 1;
3981}
3982
3983/* reverse-map from port to pin NID: see above */
3984static int atihdmi_port2pin(struct hda_codec *codec, int port)
3985{
3986 return port * 2 + 3;
3987}
3988
3989static const struct drm_audio_component_audio_ops atihdmi_audio_ops = {
3990 .pin2port = atihdmi_pin2port,
3991 .pin_eld_notify = generic_acomp_pin_eld_notify,
3992 .master_bind = generic_acomp_master_bind,
3993 .master_unbind = generic_acomp_master_unbind,
3994};
3995
84eb01be
TI		 3996static int patch_atihdmi(struct hda_codec *codec)
3997{
3998 struct hdmi_spec *spec;
5a613584
AH		 3999 struct hdmi_spec_per_cvt *per_cvt;
4000 int err, cvt_idx;
4001
4002 err = patch_generic_hdmi(codec);
4003
4004 if (err)
d0b1252d 4005 return err;
5a613584
AH		 4006
4007 codec->patch_ops.init = atihdmi_init;
4008
d0b1252d 4009 spec = codec->spec;
5a613584 4010
89250f84 4011 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
5a613584 4012 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
461cf6b3 4013 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
84d69e79 4014 spec->ops.setup_stream = atihdmi_setup_stream;
5a613584 4015
39669225
TI		 4016 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
4017 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
4018
5a613584
AH		 4019 if (!has_amd_full_remap_support(codec)) {
4020 /* override to ATI/AMD-specific versions with pairwise mapping */
67b90cb8 4021 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
5a613584 4022 atihdmi_paired_chmap_cea_alloc_validate_get_type;
67b90cb8
SP		 4023 spec->chmap.ops.cea_alloc_to_tlv_chmap =
4024 atihdmi_paired_cea_alloc_to_tlv_chmap;
4025 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
5a613584
AH		 4026 }
4027
4028 /* ATI/AMD converters do not advertise all of their capabilities */
4029 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
4030 per_cvt = get_cvt(spec, cvt_idx);
4031 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
4032 per_cvt->rates |= SUPPORTED_RATES;
4033 per_cvt->formats |= SUPPORTED_FORMATS;
4034 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
4035 }
4036
67b90cb8 4037 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
5a613584 4038
57cb54e5
TI		 4039 /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing
4040 * the link-down as is. Tell the core to allow it.
4041 */
4042 codec->link_down_at_suspend = 1;
4043
ade49db3
TI		 4044 generic_acomp_init(codec, &atihdmi_audio_ops, atihdmi_port2pin);
4045
84eb01be
TI		 4046 return 0;
4047}
4048
3de5ff88
AL		 4049/* VIA HDMI Implementation */
4050#define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
4051#define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
4052
3de5ff88
AL		 4053static int patch_via_hdmi(struct hda_codec *codec)
4054{
250e41ac 4055 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3de5ff88 4056}
84eb01be
TI		 4057
4058/*
4059 * patch entries
4060 */
b9a94a9c
TI		 4061static const struct hda_device_id snd_hda_id_hdmi[] = {
4062HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
4063HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
4064HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
4065HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
4066HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
4067HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
4068HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
74ec1181 4069HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch),
b9a94a9c
TI		 4070HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4071HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
74ec1181 4072HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x),
b9a94a9c
TI		 4073HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4074HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4075HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
74ec1181
DD		 4076HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi),
4077HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi),
b9a94a9c
TI		 4078HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi),
4079HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi),
4080HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi),
4081HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi),
4082HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi),
4083HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi),
4084HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi),
4085HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi),
4086HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi),
4087HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi),
4088HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi),
c8900a0f 4089/* 17 is known to be absent */
b9a94a9c
TI		 4090HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi),
4091HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi),
4092HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi),
4093HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi),
4094HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi),
4095HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
4096HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
4097HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
4098HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
917bb90c
TR		 4099HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi),
4100HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi),
4101HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi),
4102HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi),
b9a94a9c
TI		 4103HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
4104HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
4105HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
4106HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
4107HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
74ec1181
DD		 4108HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi),
4109HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi),
b9a94a9c 4110HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
74ec1181 4111HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi),
b9a94a9c 4112HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
74ec1181
DD		 4113HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi),
4114HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi),
b9a94a9c
TI		 4115HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
4116HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
4117HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
4118HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
74ec1181
DD		 4119HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi),
4120HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi),
4121HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi),
4122HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi),
4123HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi),
b9a94a9c 4124HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
74ec1181 4125HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi),
af677166 4126HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi),
74ec1181 4127HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi),
2d369c74 4128HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi),
3ec622f4 4129HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi),
74ec1181
DD		 4130HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi),
4131HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi),
4132HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi),
4133HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi),
4134HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi),
4135HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi),
4136HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi),
4137HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi),
4138HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi),
4139HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi),
b9a94a9c 4140HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
74ec1181 4141HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch),
b9a94a9c
TI		 4142HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
4143HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
4144HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
4145HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
7ff652ff 4146HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi),
b0d8bc50 4147HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi),
b9a94a9c
TI		 4148HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
4149HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
4150HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
7ff652ff 4151HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi),
e85015a3
TI		 4152HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi),
4153HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi),
a686632f
TI		 4154HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi),
4155HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi),
4156HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi),
4157HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi),
4158HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi),
2b4584d0 4159HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi),
a87a4d23 4160HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi),
b0d8bc50 4161HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi),
9a11ba73 4162HDA_CODEC_ENTRY(0x80862812, "Tigerlake HDMI", patch_i915_tgl_hdmi),
b9a94a9c 4163HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
a686632f
TI		 4164HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi),
4165HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi),
b9a94a9c 4166HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
d8a766a1 4167/* special ID for generic HDMI */
b9a94a9c 4168HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
84eb01be
TI		 4169{} /* terminator */
4170};
b9a94a9c 4171MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
84eb01be
TI		 4172
4173MODULE_LICENSE("GPL");
4174MODULE_DESCRIPTION("HDMI HD-audio codec");
4175MODULE_ALIAS("snd-hda-codec-intelhdmi");
4176MODULE_ALIAS("snd-hda-codec-nvhdmi");
4177MODULE_ALIAS("snd-hda-codec-atihdmi");
4178
d8a766a1 4179static struct hda_codec_driver hdmi_driver = {
b9a94a9c 4180 .id = snd_hda_id_hdmi,
84eb01be
TI		 4181};
4182
d8a766a1 4183module_hda_codec_driver(hdmi_driver);
Linux 6.x block layer and io_uring tree(s)