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ALSA: hda - Fix possible races in HDMI driver
[linux-2.6-block.git] / sound / pci / hda / patch_hdmi.c
CommitLineData
079d88cc
WF		 1/*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
84eb01be
TI		 6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
079d88cc
WF		 9 *
10 * Authors:
11 * Wu Fengguang <wfg@linux.intel.com>
12 *
13 * Maintained by:
14 * Wu Fengguang <wfg@linux.intel.com>
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the Free
18 * Software Foundation; either version 2 of the License, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful, but
22 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
23 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
24 * for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software Foundation,
28 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
84eb01be
TI		 31#include <linux/init.h>
32#include <linux/delay.h>
33#include <linux/slab.h>
65a77217 34#include <linux/module.h>
84eb01be 35#include <sound/core.h>
07acecc1 36#include <sound/jack.h>
433968da 37#include <sound/asoundef.h>
d45e6889 38#include <sound/tlv.h>
84eb01be
TI		 39#include "hda_codec.h"
40#include "hda_local.h"
1835a0f9 41#include "hda_jack.h"
84eb01be 42
0ebaa24c
TI		 43static bool static_hdmi_pcm;
44module_param(static_hdmi_pcm, bool, 0644);
45MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
46
fb87fa3a
ML		 47#define is_haswell(codec) ((codec)->vendor_id == 0x80862807)
48
384a48d7
SW		 49struct hdmi_spec_per_cvt {
50 hda_nid_t cvt_nid;
51 int assigned;
52 unsigned int channels_min;
53 unsigned int channels_max;
54 u32 rates;
55 u64 formats;
56 unsigned int maxbps;
57};
079d88cc 58
4eea3091
TI		 59/* max. connections to a widget */
60#define HDA_MAX_CONNECTIONS 32
61
384a48d7
SW		 62struct hdmi_spec_per_pin {
63 hda_nid_t pin_nid;
64 int num_mux_nids;
65 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
1df5a06a 66 hda_nid_t cvt_nid;
744626da
WF		 67
68 struct hda_codec *codec;
384a48d7 69 struct hdmi_eld sink_eld;
744626da 70 struct delayed_work work;
92c69e79 71 struct snd_kcontrol *eld_ctl;
c6e8453e 72 int repoll_count;
b054087d
TI		 73 bool setup; /* the stream has been set up by prepare callback */
74 int channels; /* current number of channels */
1a6003b5 75 bool non_pcm;
d45e6889
TI		 76 bool chmap_set; /* channel-map override by ALSA API? */
77 unsigned char chmap[8]; /* ALSA API channel-map */
bce0d2a8 78 char pcm_name[8]; /* filled in build_pcm callbacks */
384a48d7 79};
079d88cc 80
384a48d7
SW		 81struct hdmi_spec {
82 int num_cvts;
bce0d2a8
TI		 83 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
84 hda_nid_t cvt_nids[4]; /* only for haswell fix */
079d88cc 85
384a48d7 86 int num_pins;
bce0d2a8
TI		 87 struct snd_array pins; /* struct hdmi_spec_per_pin */
88 struct snd_array pcm_rec; /* struct hda_pcm */
d45e6889 89 unsigned int channels_max; /* max over all cvts */
079d88cc 90
4bd038f9 91 struct hdmi_eld temp_eld;
079d88cc 92 /*
384a48d7 93 * Non-generic ATI/NVIDIA specific
079d88cc
WF		 94 */
95 struct hda_multi_out multiout;
d0b1252d 96 struct hda_pcm_stream pcm_playback;
079d88cc
WF		 97};
98
99
100struct hdmi_audio_infoframe {
101 u8 type; /* 0x84 */
102 u8 ver; /* 0x01 */
103 u8 len; /* 0x0a */
104
53d7d69d
WF		 105 u8 checksum;
106
079d88cc
WF		 107 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
108 u8 SS01_SF24;
109 u8 CXT04;
110 u8 CA;
111 u8 LFEPBL01_LSV36_DM_INH7;
53d7d69d
WF		 112};
113
114struct dp_audio_infoframe {
115 u8 type; /* 0x84 */
116 u8 len; /* 0x1b */
117 u8 ver; /* 0x11 << 2 */
118
119 u8 CC02_CT47; /* match with HDMI infoframe from this on */
120 u8 SS01_SF24;
121 u8 CXT04;
122 u8 CA;
123 u8 LFEPBL01_LSV36_DM_INH7;
079d88cc
WF		 124};
125
2b203dbb
TI		 126union audio_infoframe {
127 struct hdmi_audio_infoframe hdmi;
128 struct dp_audio_infoframe dp;
129 u8 bytes[0];
130};
131
079d88cc
WF		 132/*
133 * CEA speaker placement:
134 *
135 * FLH FCH FRH
136 * FLW FL FLC FC FRC FR FRW
137 *
138 * LFE
139 * TC
140 *
141 * RL RLC RC RRC RR
142 *
143 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
144 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
145 */
146enum cea_speaker_placement {
147 FL = (1 << 0), /* Front Left */
148 FC = (1 << 1), /* Front Center */
149 FR = (1 << 2), /* Front Right */
150 FLC = (1 << 3), /* Front Left Center */
151 FRC = (1 << 4), /* Front Right Center */
152 RL = (1 << 5), /* Rear Left */
153 RC = (1 << 6), /* Rear Center */
154 RR = (1 << 7), /* Rear Right */
155 RLC = (1 << 8), /* Rear Left Center */
156 RRC = (1 << 9), /* Rear Right Center */
157 LFE = (1 << 10), /* Low Frequency Effect */
158 FLW = (1 << 11), /* Front Left Wide */
159 FRW = (1 << 12), /* Front Right Wide */
160 FLH = (1 << 13), /* Front Left High */
161 FCH = (1 << 14), /* Front Center High */
162 FRH = (1 << 15), /* Front Right High */
163 TC = (1 << 16), /* Top Center */
164};
165
166/*
167 * ELD SA bits in the CEA Speaker Allocation data block
168 */
169static int eld_speaker_allocation_bits[] = {
170 [0] = FL | FR,
171 [1] = LFE,
172 [2] = FC,
173 [3] = RL | RR,
174 [4] = RC,
175 [5] = FLC | FRC,
176 [6] = RLC | RRC,
177 /* the following are not defined in ELD yet */
178 [7] = FLW | FRW,
179 [8] = FLH | FRH,
180 [9] = TC,
181 [10] = FCH,
182};
183
184struct cea_channel_speaker_allocation {
185 int ca_index;
186 int speakers[8];
187
188 /* derived values, just for convenience */
189 int channels;
190 int spk_mask;
191};
192
193/*
194 * ALSA sequence is:
195 *
196 * surround40 surround41 surround50 surround51 surround71
197 * ch0 front left = = = =
198 * ch1 front right = = = =
199 * ch2 rear left = = = =
200 * ch3 rear right = = = =
201 * ch4 LFE center center center
202 * ch5 LFE LFE
203 * ch6 side left
204 * ch7 side right
205 *
206 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
207 */
208static int hdmi_channel_mapping[0x32][8] = {
209 /* stereo */
210 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
211 /* 2.1 */
212 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
213 /* Dolby Surround */
214 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
215 /* surround40 */
216 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
217 /* 4ch */
218 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
219 /* surround41 */
9396d317 220 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
079d88cc
WF		 221 /* surround50 */
222 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
223 /* surround51 */
224 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
225 /* 7.1 */
226 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
227};
228
229/*
230 * This is an ordered list!
231 *
232 * The preceding ones have better chances to be selected by
53d7d69d 233 * hdmi_channel_allocation().
079d88cc
WF		 234 */
235static struct cea_channel_speaker_allocation channel_allocations[] = {
236/* channel: 7 6 5 4 3 2 1 0 */
237{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
238 /* 2.1 */
239{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
240 /* Dolby Surround */
241{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
242 /* surround40 */
243{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
244 /* surround41 */
245{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
246 /* surround50 */
247{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
248 /* surround51 */
249{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
250 /* 6.1 */
251{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
252 /* surround71 */
253{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
254
255{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
256{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
257{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
258{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
259{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
260{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
261{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
262{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
263{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
264{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
265{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
266{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
267{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
268{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
269{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
270{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
271{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
272{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
273{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
274{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
275{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
276{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
277{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
278{ .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
279{ .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
280{ .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
281{ .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
282{ .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
283{ .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
284{ .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
285{ .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
286{ .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
287{ .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
288{ .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
289{ .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
290{ .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
291{ .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
292{ .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
293{ .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
294{ .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
295{ .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
296};
297
298
299/*
300 * HDMI routines
301 */
302
bce0d2a8
TI		 303#define get_pin(spec, idx) \
304 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
305#define get_cvt(spec, idx) \
306 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
307#define get_pcm_rec(spec, idx) \
308 ((struct hda_pcm *)snd_array_elem(&spec->pcm_rec, idx))
309
384a48d7 310static int pin_nid_to_pin_index(struct hdmi_spec *spec, hda_nid_t pin_nid)
079d88cc 311{
384a48d7 312 int pin_idx;
079d88cc 313
384a48d7 314 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
bce0d2a8 315 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
384a48d7 316 return pin_idx;
079d88cc 317
384a48d7
SW		 318 snd_printk(KERN_WARNING "HDMI: pin nid %d not registered\n", pin_nid);
319 return -EINVAL;
320}
321
322static int hinfo_to_pin_index(struct hdmi_spec *spec,
323 struct hda_pcm_stream *hinfo)
324{
325 int pin_idx;
326
327 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
bce0d2a8 328 if (get_pcm_rec(spec, pin_idx)->stream == hinfo)
384a48d7
SW		 329 return pin_idx;
330
331 snd_printk(KERN_WARNING "HDMI: hinfo %p not registered\n", hinfo);
332 return -EINVAL;
333}
334
335static int cvt_nid_to_cvt_index(struct hdmi_spec *spec, hda_nid_t cvt_nid)
336{
337 int cvt_idx;
338
339 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
bce0d2a8 340 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
384a48d7
SW		 341 return cvt_idx;
342
343 snd_printk(KERN_WARNING "HDMI: cvt nid %d not registered\n", cvt_nid);
079d88cc
WF		 344 return -EINVAL;
345}
346
14bc52b8
PLB		 347static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
348 struct snd_ctl_elem_info *uinfo)
349{
350 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9
DH		 351 struct hdmi_spec *spec = codec->spec;
352 struct hdmi_eld *eld;
14bc52b8
PLB		 353 int pin_idx;
354
14bc52b8
PLB		 355 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
356
357 pin_idx = kcontrol->private_value;
bce0d2a8 358 eld = &get_pin(spec, pin_idx)->sink_eld;
68e03de9 359
4bd038f9 360 mutex_lock(&eld->lock);
68e03de9 361 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
4bd038f9 362 mutex_unlock(&eld->lock);
14bc52b8
PLB		 363
364 return 0;
365}
366
367static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
368 struct snd_ctl_elem_value *ucontrol)
369{
370 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9
DH		 371 struct hdmi_spec *spec = codec->spec;
372 struct hdmi_eld *eld;
14bc52b8
PLB		 373 int pin_idx;
374
14bc52b8 375 pin_idx = kcontrol->private_value;
bce0d2a8 376 eld = &get_pin(spec, pin_idx)->sink_eld;
68e03de9 377
4bd038f9 378 mutex_lock(&eld->lock);
68e03de9 379 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data)) {
4bd038f9 380 mutex_unlock(&eld->lock);
68e03de9
DH		 381 snd_BUG();
382 return -EINVAL;
383 }
384
385 memset(ucontrol->value.bytes.data, 0,
386 ARRAY_SIZE(ucontrol->value.bytes.data));
387 if (eld->eld_valid)
388 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
389 eld->eld_size);
4bd038f9 390 mutex_unlock(&eld->lock);
14bc52b8
PLB		 391
392 return 0;
393}
394
395static struct snd_kcontrol_new eld_bytes_ctl = {
396 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
397 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
398 .name = "ELD",
399 .info = hdmi_eld_ctl_info,
400 .get = hdmi_eld_ctl_get,
401};
402
403static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
404 int device)
405{
406 struct snd_kcontrol *kctl;
407 struct hdmi_spec *spec = codec->spec;
408 int err;
409
410 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
411 if (!kctl)
412 return -ENOMEM;
413 kctl->private_value = pin_idx;
414 kctl->id.device = device;
415
bce0d2a8 416 err = snd_hda_ctl_add(codec, get_pin(spec, pin_idx)->pin_nid, kctl);
14bc52b8
PLB		 417 if (err < 0)
418 return err;
419
bce0d2a8 420 get_pin(spec, pin_idx)->eld_ctl = kctl;
14bc52b8
PLB		 421 return 0;
422}
423
079d88cc
WF		 424#ifdef BE_PARANOID
425static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
426 int *packet_index, int *byte_index)
427{
428 int val;
429
430 val = snd_hda_codec_read(codec, pin_nid, 0,
431 AC_VERB_GET_HDMI_DIP_INDEX, 0);
432
433 *packet_index = val >> 5;
434 *byte_index = val & 0x1f;
435}
436#endif
437
438static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
439 int packet_index, int byte_index)
440{
441 int val;
442
443 val = (packet_index << 5) | (byte_index & 0x1f);
444
445 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
446}
447
448static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
449 unsigned char val)
450{
451 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
452}
453
384a48d7 454static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc
WF		 455{
456 /* Unmute */
457 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
458 snd_hda_codec_write(codec, pin_nid, 0,
459 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
6169b673
TI		 460 /* Enable pin out: some machines with GM965 gets broken output when
461 * the pin is disabled or changed while using with HDMI
462 */
079d88cc 463 snd_hda_codec_write(codec, pin_nid, 0,
6169b673 464 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
079d88cc
WF		 465}
466
384a48d7 467static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc 468{
384a48d7 469 return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
079d88cc
WF		 470 AC_VERB_GET_CVT_CHAN_COUNT, 0);
471}
472
473static void hdmi_set_channel_count(struct hda_codec *codec,
384a48d7 474 hda_nid_t cvt_nid, int chs)
079d88cc 475{
384a48d7
SW		 476 if (chs != hdmi_get_channel_count(codec, cvt_nid))
477 snd_hda_codec_write(codec, cvt_nid, 0,
079d88cc
WF		 478 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
479}
480
481
482/*
483 * Channel mapping routines
484 */
485
486/*
487 * Compute derived values in channel_allocations[].
488 */
489static void init_channel_allocations(void)
490{
491 int i, j;
492 struct cea_channel_speaker_allocation *p;
493
494 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
495 p = channel_allocations + i;
496 p->channels = 0;
497 p->spk_mask = 0;
498 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
499 if (p->speakers[j]) {
500 p->channels++;
501 p->spk_mask |= p->speakers[j];
502 }
503 }
504}
505
72357c78
WX		 506static int get_channel_allocation_order(int ca)
507{
508 int i;
509
510 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
511 if (channel_allocations[i].ca_index == ca)
512 break;
513 }
514 return i;
515}
516
079d88cc
WF		 517/*
518 * The transformation takes two steps:
519 *
520 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
521 * spk_mask => (channel_allocations[]) => ai->CA
522 *
523 * TODO: it could select the wrong CA from multiple candidates.
524*/
384a48d7 525static int hdmi_channel_allocation(struct hdmi_eld *eld, int channels)
079d88cc 526{
079d88cc 527 int i;
53d7d69d 528 int ca = 0;
079d88cc 529 int spk_mask = 0;
079d88cc
WF		 530 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
531
532 /*
533 * CA defaults to 0 for basic stereo audio
534 */
535 if (channels <= 2)
536 return 0;
537
079d88cc
WF		 538 /*
539 * expand ELD's speaker allocation mask
540 *
541 * ELD tells the speaker mask in a compact(paired) form,
542 * expand ELD's notions to match the ones used by Audio InfoFrame.
543 */
544 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
1613d6b4 545 if (eld->info.spk_alloc & (1 << i))
079d88cc
WF		 546 spk_mask |= eld_speaker_allocation_bits[i];
547 }
548
549 /* search for the first working match in the CA table */
550 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
551 if (channels == channel_allocations[i].channels &&
552 (spk_mask & channel_allocations[i].spk_mask) ==
553 channel_allocations[i].spk_mask) {
53d7d69d 554 ca = channel_allocations[i].ca_index;
079d88cc
WF		 555 break;
556 }
557 }
558
18e39186
AH		 559 if (!ca) {
560 /* if there was no match, select the regular ALSA channel
561 * allocation with the matching number of channels */
562 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
563 if (channels == channel_allocations[i].channels) {
564 ca = channel_allocations[i].ca_index;
565 break;
566 }
567 }
568 }
569
1613d6b4 570 snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf));
2abbf439 571 snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n",
53d7d69d 572 ca, channels, buf);
079d88cc 573
53d7d69d 574 return ca;
079d88cc
WF		 575}
576
577static void hdmi_debug_channel_mapping(struct hda_codec *codec,
578 hda_nid_t pin_nid)
579{
580#ifdef CONFIG_SND_DEBUG_VERBOSE
581 int i;
582 int slot;
583
584 for (i = 0; i < 8; i++) {
585 slot = snd_hda_codec_read(codec, pin_nid, 0,
586 AC_VERB_GET_HDMI_CHAN_SLOT, i);
587 printk(KERN_DEBUG "HDMI: ASP channel %d => slot %d\n",
588 slot >> 4, slot & 0xf);
589 }
590#endif
591}
592
593
d45e6889 594static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
079d88cc 595 hda_nid_t pin_nid,
433968da 596 bool non_pcm,
53d7d69d 597 int ca)
079d88cc 598{
90f28002 599 struct cea_channel_speaker_allocation *ch_alloc;
079d88cc 600 int i;
079d88cc 601 int err;
72357c78 602 int order;
433968da 603 int non_pcm_mapping[8];
079d88cc 604
72357c78 605 order = get_channel_allocation_order(ca);
90f28002 606 ch_alloc = &channel_allocations[order];
433968da 607
079d88cc 608 if (hdmi_channel_mapping[ca][1] == 0) {
90f28002
AH		 609 int hdmi_slot = 0;
610 /* fill actual channel mappings in ALSA channel (i) order */
611 for (i = 0; i < ch_alloc->channels; i++) {
612 while (!ch_alloc->speakers[7 - hdmi_slot] && !WARN_ON(hdmi_slot >= 8))
613 hdmi_slot++; /* skip zero slots */
614
615 hdmi_channel_mapping[ca][i] = (i << 4) | hdmi_slot++;
616 }
617 /* fill the rest of the slots with ALSA channel 0xf */
618 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++)
619 if (!ch_alloc->speakers[7 - hdmi_slot])
620 hdmi_channel_mapping[ca][i++] = (0xf << 4) | hdmi_slot;
079d88cc
WF		 621 }
622
433968da 623 if (non_pcm) {
90f28002 624 for (i = 0; i < ch_alloc->channels; i++)
11f7c52d 625 non_pcm_mapping[i] = (i << 4) | i;
433968da 626 for (; i < 8; i++)
11f7c52d 627 non_pcm_mapping[i] = (0xf << 4) | i;
433968da
WX		 628 }
629
079d88cc
WF		 630 for (i = 0; i < 8; i++) {
631 err = snd_hda_codec_write(codec, pin_nid, 0,
632 AC_VERB_SET_HDMI_CHAN_SLOT,
433968da 633 non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i]);
079d88cc 634 if (err) {
2abbf439
WF		 635 snd_printdd(KERN_NOTICE
636 "HDMI: channel mapping failed\n");
079d88cc
WF		 637 break;
638 }
639 }
079d88cc
WF		 640}
641
d45e6889
TI		 642struct channel_map_table {
643 unsigned char map; /* ALSA API channel map position */
d45e6889
TI		 644 int spk_mask; /* speaker position bit mask */
645};
646
647static struct channel_map_table map_tables[] = {
a5b7d510
AH		 648 { SNDRV_CHMAP_FL, FL },
649 { SNDRV_CHMAP_FR, FR },
650 { SNDRV_CHMAP_RL, RL },
651 { SNDRV_CHMAP_RR, RR },
652 { SNDRV_CHMAP_LFE, LFE },
653 { SNDRV_CHMAP_FC, FC },
654 { SNDRV_CHMAP_RLC, RLC },
655 { SNDRV_CHMAP_RRC, RRC },
656 { SNDRV_CHMAP_RC, RC },
657 { SNDRV_CHMAP_FLC, FLC },
658 { SNDRV_CHMAP_FRC, FRC },
659 { SNDRV_CHMAP_FLH, FLH },
660 { SNDRV_CHMAP_FRH, FRH },
661 { SNDRV_CHMAP_FLW, FLW },
662 { SNDRV_CHMAP_FRW, FRW },
663 { SNDRV_CHMAP_TC, TC },
664 { SNDRV_CHMAP_FCH, FCH },
d45e6889
TI		 665 {} /* terminator */
666};
667
668/* from ALSA API channel position to speaker bit mask */
669static int to_spk_mask(unsigned char c)
670{
671 struct channel_map_table *t = map_tables;
672 for (; t->map; t++) {
673 if (t->map == c)
674 return t->spk_mask;
675 }
676 return 0;
677}
678
679/* from ALSA API channel position to CEA slot */
a5b7d510 680static int to_cea_slot(int ordered_ca, unsigned char pos)
d45e6889 681{
a5b7d510
AH		 682 int mask = to_spk_mask(pos);
683 int i;
d45e6889 684
a5b7d510
AH		 685 if (mask) {
686 for (i = 0; i < 8; i++) {
687 if (channel_allocations[ordered_ca].speakers[7 - i] == mask)
688 return i;
689 }
d45e6889 690 }
a5b7d510
AH		 691
692 return -1;
d45e6889
TI		 693}
694
695/* from speaker bit mask to ALSA API channel position */
696static int spk_to_chmap(int spk)
697{
698 struct channel_map_table *t = map_tables;
699 for (; t->map; t++) {
700 if (t->spk_mask == spk)
701 return t->map;
702 }
703 return 0;
704}
705
a5b7d510
AH		 706/* from CEA slot to ALSA API channel position */
707static int from_cea_slot(int ordered_ca, unsigned char slot)
708{
709 int mask = channel_allocations[ordered_ca].speakers[7 - slot];
710
711 return spk_to_chmap(mask);
712}
713
d45e6889
TI		 714/* get the CA index corresponding to the given ALSA API channel map */
715static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
716{
717 int i, spks = 0, spk_mask = 0;
718
719 for (i = 0; i < chs; i++) {
720 int mask = to_spk_mask(map[i]);
721 if (mask) {
722 spk_mask |= mask;
723 spks++;
724 }
725 }
726
727 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
728 if ((chs == channel_allocations[i].channels ||
729 spks == channel_allocations[i].channels) &&
730 (spk_mask & channel_allocations[i].spk_mask) ==
731 channel_allocations[i].spk_mask)
732 return channel_allocations[i].ca_index;
733 }
734 return -1;
735}
736
737/* set up the channel slots for the given ALSA API channel map */
738static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
739 hda_nid_t pin_nid,
a5b7d510
AH		 740 int chs, unsigned char *map,
741 int ca)
d45e6889 742{
a5b7d510 743 int ordered_ca = get_channel_allocation_order(ca);
11f7c52d
AH		 744 int alsa_pos, hdmi_slot;
745 int assignments[8] = {[0 ... 7] = 0xf};
746
747 for (alsa_pos = 0; alsa_pos < chs; alsa_pos++) {
748
a5b7d510 749 hdmi_slot = to_cea_slot(ordered_ca, map[alsa_pos]);
11f7c52d
AH		 750
751 if (hdmi_slot < 0)
752 continue; /* unassigned channel */
753
754 assignments[hdmi_slot] = alsa_pos;
755 }
756
757 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++) {
d45e6889 758 int val, err;
11f7c52d
AH		 759
760 val = (assignments[hdmi_slot] << 4) | hdmi_slot;
d45e6889
TI		 761 err = snd_hda_codec_write(codec, pin_nid, 0,
762 AC_VERB_SET_HDMI_CHAN_SLOT, val);
763 if (err)
764 return -EINVAL;
765 }
766 return 0;
767}
768
769/* store ALSA API channel map from the current default map */
770static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
771{
772 int i;
56cac413 773 int ordered_ca = get_channel_allocation_order(ca);
d45e6889 774 for (i = 0; i < 8; i++) {
56cac413 775 if (i < channel_allocations[ordered_ca].channels)
a5b7d510 776 map[i] = from_cea_slot(ordered_ca, hdmi_channel_mapping[ca][i] & 0x0f);
d45e6889
TI		 777 else
778 map[i] = 0;
779 }
780}
781
782static void hdmi_setup_channel_mapping(struct hda_codec *codec,
783 hda_nid_t pin_nid, bool non_pcm, int ca,
20608731
AH		 784 int channels, unsigned char *map,
785 bool chmap_set)
d45e6889 786{
20608731 787 if (!non_pcm && chmap_set) {
d45e6889 788 hdmi_manual_setup_channel_mapping(codec, pin_nid,
a5b7d510 789 channels, map, ca);
d45e6889
TI		 790 } else {
791 hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
792 hdmi_setup_fake_chmap(map, ca);
793 }
980b2495
AH		 794
795 hdmi_debug_channel_mapping(codec, pin_nid);
d45e6889 796}
079d88cc
WF		 797
798/*
799 * Audio InfoFrame routines
800 */
801
802/*
803 * Enable Audio InfoFrame Transmission
804 */
805static void hdmi_start_infoframe_trans(struct hda_codec *codec,
806 hda_nid_t pin_nid)
807{
808 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
809 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
810 AC_DIPXMIT_BEST);
811}
812
813/*
814 * Disable Audio InfoFrame Transmission
815 */
816static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
817 hda_nid_t pin_nid)
818{
819 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
820 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
821 AC_DIPXMIT_DISABLE);
822}
823
824static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
825{
826#ifdef CONFIG_SND_DEBUG_VERBOSE
827 int i;
828 int size;
829
830 size = snd_hdmi_get_eld_size(codec, pin_nid);
831 printk(KERN_DEBUG "HDMI: ELD buf size is %d\n", size);
832
833 for (i = 0; i < 8; i++) {
834 size = snd_hda_codec_read(codec, pin_nid, 0,
835 AC_VERB_GET_HDMI_DIP_SIZE, i);
836 printk(KERN_DEBUG "HDMI: DIP GP[%d] buf size is %d\n", i, size);
837 }
838#endif
839}
840
841static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
842{
843#ifdef BE_PARANOID
844 int i, j;
845 int size;
846 int pi, bi;
847 for (i = 0; i < 8; i++) {
848 size = snd_hda_codec_read(codec, pin_nid, 0,
849 AC_VERB_GET_HDMI_DIP_SIZE, i);
850 if (size == 0)
851 continue;
852
853 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
854 for (j = 1; j < 1000; j++) {
855 hdmi_write_dip_byte(codec, pin_nid, 0x0);
856 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
857 if (pi != i)
858 snd_printd(KERN_INFO "dip index %d: %d != %d\n",
859 bi, pi, i);
860 if (bi == 0) /* byte index wrapped around */
861 break;
862 }
863 snd_printd(KERN_INFO
864 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
865 i, size, j);
866 }
867#endif
868}
869
53d7d69d 870static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
079d88cc 871{
53d7d69d 872 u8 *bytes = (u8 *)hdmi_ai;
079d88cc
WF		 873 u8 sum = 0;
874 int i;
875
53d7d69d 876 hdmi_ai->checksum = 0;
079d88cc 877
53d7d69d 878 for (i = 0; i < sizeof(*hdmi_ai); i++)
079d88cc
WF		 879 sum += bytes[i];
880
53d7d69d 881 hdmi_ai->checksum = -sum;
079d88cc
WF		 882}
883
884static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
885 hda_nid_t pin_nid,
53d7d69d 886 u8 *dip, int size)
079d88cc 887{
079d88cc
WF		 888 int i;
889
890 hdmi_debug_dip_size(codec, pin_nid);
891 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
892
079d88cc 893 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d
WF		 894 for (i = 0; i < size; i++)
895 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
079d88cc
WF		 896}
897
898static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
53d7d69d 899 u8 *dip, int size)
079d88cc 900{
079d88cc
WF		 901 u8 val;
902 int i;
903
904 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
905 != AC_DIPXMIT_BEST)
906 return false;
907
908 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d 909 for (i = 0; i < size; i++) {
079d88cc
WF		 910 val = snd_hda_codec_read(codec, pin_nid, 0,
911 AC_VERB_GET_HDMI_DIP_DATA, 0);
53d7d69d 912 if (val != dip[i])
079d88cc
WF		 913 return false;
914 }
915
916 return true;
917}
918
b054087d
TI		 919static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
920 struct hdmi_spec_per_pin *per_pin,
921 bool non_pcm)
079d88cc 922{
384a48d7 923 hda_nid_t pin_nid = per_pin->pin_nid;
b054087d 924 int channels = per_pin->channels;
1df5a06a 925 int active_channels;
384a48d7 926 struct hdmi_eld *eld;
1df5a06a 927 int ca, ordered_ca;
2b203dbb 928 union audio_infoframe ai;
079d88cc 929
b054087d
TI		 930 if (!channels)
931 return;
932
58f7d28d
ML		 933 if (is_haswell(codec))
934 snd_hda_codec_write(codec, pin_nid, 0,
935 AC_VERB_SET_AMP_GAIN_MUTE,
936 AMP_OUT_UNMUTE);
937
bce0d2a8 938 eld = &per_pin->sink_eld;
384a48d7
SW		 939 if (!eld->monitor_present)
940 return;
079d88cc 941
d45e6889
TI		 942 if (!non_pcm && per_pin->chmap_set)
943 ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
944 else
945 ca = hdmi_channel_allocation(eld, channels);
946 if (ca < 0)
947 ca = 0;
384a48d7 948
1df5a06a
AH		 949 ordered_ca = get_channel_allocation_order(ca);
950 active_channels = channel_allocations[ordered_ca].channels;
951
952 hdmi_set_channel_count(codec, per_pin->cvt_nid, active_channels);
953
384a48d7 954 memset(&ai, 0, sizeof(ai));
1613d6b4 955 if (eld->info.conn_type == 0) { /* HDMI */
384a48d7
SW		 956 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
957
958 hdmi_ai->type = 0x84;
959 hdmi_ai->ver = 0x01;
960 hdmi_ai->len = 0x0a;
1df5a06a 961 hdmi_ai->CC02_CT47 = active_channels - 1;
384a48d7
SW		 962 hdmi_ai->CA = ca;
963 hdmi_checksum_audio_infoframe(hdmi_ai);
1613d6b4 964 } else if (eld->info.conn_type == 1) { /* DisplayPort */
384a48d7
SW		 965 struct dp_audio_infoframe *dp_ai = &ai.dp;
966
967 dp_ai->type = 0x84;
968 dp_ai->len = 0x1b;
969 dp_ai->ver = 0x11 << 2;
1df5a06a 970 dp_ai->CC02_CT47 = active_channels - 1;
384a48d7
SW		 971 dp_ai->CA = ca;
972 } else {
973 snd_printd("HDMI: unknown connection type at pin %d\n",
974 pin_nid);
975 return;
976 }
53d7d69d 977
39edac70
AH		 978 /*
979 * always configure channel mapping, it may have been changed by the
980 * user in the meantime
981 */
982 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
983 channels, per_pin->chmap,
984 per_pin->chmap_set);
985
384a48d7
SW		 986 /*
987 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
988 * sizeof(*dp_ai) to avoid partial match/update problems when
989 * the user switches between HDMI/DP monitors.
990 */
991 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
992 sizeof(ai))) {
993 snd_printdd("hdmi_setup_audio_infoframe: "
980b2495 994 "pin=%d channels=%d ca=0x%02x\n",
384a48d7 995 pin_nid,
980b2495 996 active_channels, ca);
384a48d7
SW		 997 hdmi_stop_infoframe_trans(codec, pin_nid);
998 hdmi_fill_audio_infoframe(codec, pin_nid,
999 ai.bytes, sizeof(ai));
1000 hdmi_start_infoframe_trans(codec, pin_nid);
079d88cc 1001 }
433968da 1002
1a6003b5 1003 per_pin->non_pcm = non_pcm;
079d88cc
WF		 1004}
1005
1006
1007/*
1008 * Unsolicited events
1009 */
1010
c6e8453e 1011static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
38faddb1 1012
079d88cc
WF		 1013static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
1014{
1015 struct hdmi_spec *spec = codec->spec;
3a93897e
TI		 1016 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1017 int pin_nid;
384a48d7 1018 int pin_idx;
3a93897e 1019 struct hda_jack_tbl *jack;
2e59e5ab 1020 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
3a93897e
TI		 1021
1022 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
1023 if (!jack)
1024 return;
1025 pin_nid = jack->nid;
1026 jack->jack_dirty = 1;
079d88cc 1027
fae3d88a 1028 _snd_printd(SND_PR_VERBOSE,
2e59e5ab
ML		 1029 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
1030 codec->addr, pin_nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
fae3d88a 1031 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
079d88cc 1032
384a48d7
SW		 1033 pin_idx = pin_nid_to_pin_index(spec, pin_nid);
1034 if (pin_idx < 0)
079d88cc
WF		 1035 return;
1036
bce0d2a8 1037 hdmi_present_sense(get_pin(spec, pin_idx), 1);
01a61e12 1038 snd_hda_jack_report_sync(codec);
079d88cc
WF		 1039}
1040
1041static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
1042{
1043 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1044 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1045 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
1046 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
1047
1048 printk(KERN_INFO
e9ea8e8f 1049 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
384a48d7 1050 codec->addr,
079d88cc
WF		 1051 tag,
1052 subtag,
1053 cp_state,
1054 cp_ready);
1055
1056 /* TODO */
1057 if (cp_state)
1058 ;
1059 if (cp_ready)
1060 ;
1061}
1062
1063
1064static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
1065{
079d88cc
WF		 1066 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1067 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1068
3a93897e 1069 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
079d88cc
WF		 1070 snd_printd(KERN_INFO "Unexpected HDMI event tag 0x%x\n", tag);
1071 return;
1072 }
1073
1074 if (subtag == 0)
1075 hdmi_intrinsic_event(codec, res);
1076 else
1077 hdmi_non_intrinsic_event(codec, res);
1078}
1079
58f7d28d 1080static void haswell_verify_D0(struct hda_codec *codec,
53b434f0 1081 hda_nid_t cvt_nid, hda_nid_t nid)
83f26ad2 1082{
58f7d28d 1083 int pwr;
83f26ad2 1084
53b434f0
WX		 1085 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
1086 * thus pins could only choose converter 0 for use. Make sure the
1087 * converters are in correct power state */
fd678cac 1088 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
53b434f0
WX		 1089 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
1090
fd678cac 1091 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
83f26ad2
DH		 1092 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
1093 AC_PWRST_D0);
1094 msleep(40);
1095 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
1096 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
1097 snd_printd("Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
1098 }
83f26ad2
DH		 1099}
1100
079d88cc
WF		 1101/*
1102 * Callbacks
1103 */
1104
92f10b3f
TI		 1105/* HBR should be Non-PCM, 8 channels */
1106#define is_hbr_format(format) \
1107 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
1108
384a48d7
SW		 1109static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
1110 hda_nid_t pin_nid, u32 stream_tag, int format)
079d88cc 1111{
ea87d1c4
AH		 1112 int pinctl;
1113 int new_pinctl = 0;
ea87d1c4 1114
fb87fa3a 1115 if (is_haswell(codec))
58f7d28d 1116 haswell_verify_D0(codec, cvt_nid, pin_nid);
83f26ad2 1117
384a48d7
SW		 1118 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
1119 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
ea87d1c4
AH		 1120 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1121
1122 new_pinctl = pinctl & ~AC_PINCTL_EPT;
92f10b3f 1123 if (is_hbr_format(format))
ea87d1c4
AH		 1124 new_pinctl |= AC_PINCTL_EPT_HBR;
1125 else
1126 new_pinctl |= AC_PINCTL_EPT_NATIVE;
1127
1128 snd_printdd("hdmi_setup_stream: "
1129 "NID=0x%x, %spinctl=0x%x\n",
384a48d7 1130 pin_nid,
ea87d1c4
AH		 1131 pinctl == new_pinctl ? "" : "new-",
1132 new_pinctl);
1133
1134 if (pinctl != new_pinctl)
384a48d7 1135 snd_hda_codec_write(codec, pin_nid, 0,
ea87d1c4
AH		 1136 AC_VERB_SET_PIN_WIDGET_CONTROL,
1137 new_pinctl);
ea87d1c4 1138
384a48d7 1139 }
92f10b3f 1140 if (is_hbr_format(format) && !new_pinctl) {
ea87d1c4
AH		 1141 snd_printdd("hdmi_setup_stream: HBR is not supported\n");
1142 return -EINVAL;
1143 }
079d88cc 1144
384a48d7 1145 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
ea87d1c4 1146 return 0;
079d88cc
WF		 1147}
1148
7ef166b8
WX		 1149static int hdmi_choose_cvt(struct hda_codec *codec,
1150 int pin_idx, int *cvt_id, int *mux_id)
bbbe3390
TI		 1151{
1152 struct hdmi_spec *spec = codec->spec;
384a48d7 1153 struct hdmi_spec_per_pin *per_pin;
384a48d7 1154 struct hdmi_spec_per_cvt *per_cvt = NULL;
7ef166b8 1155 int cvt_idx, mux_idx = 0;
bbbe3390 1156
bce0d2a8 1157 per_pin = get_pin(spec, pin_idx);
384a48d7
SW		 1158
1159 /* Dynamically assign converter to stream */
1160 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
bce0d2a8 1161 per_cvt = get_cvt(spec, cvt_idx);
bbbe3390 1162
384a48d7
SW		 1163 /* Must not already be assigned */
1164 if (per_cvt->assigned)
1165 continue;
1166 /* Must be in pin's mux's list of converters */
1167 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1168 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1169 break;
1170 /* Not in mux list */
1171 if (mux_idx == per_pin->num_mux_nids)
1172 continue;
1173 break;
1174 }
7ef166b8 1175
384a48d7
SW		 1176 /* No free converters */
1177 if (cvt_idx == spec->num_cvts)
1178 return -ENODEV;
1179
7ef166b8
WX		 1180 if (cvt_id)
1181 *cvt_id = cvt_idx;
1182 if (mux_id)
1183 *mux_id = mux_idx;
1184
1185 return 0;
1186}
1187
1188static void haswell_config_cvts(struct hda_codec *codec,
f82d7d16 1189 hda_nid_t pin_nid, int mux_idx)
7ef166b8
WX		 1190{
1191 struct hdmi_spec *spec = codec->spec;
f82d7d16
ML		 1192 hda_nid_t nid, end_nid;
1193 int cvt_idx, curr;
1194 struct hdmi_spec_per_cvt *per_cvt;
7ef166b8 1195
f82d7d16
ML		 1196 /* configure all pins, including "no physical connection" ones */
1197 end_nid = codec->start_nid + codec->num_nodes;
1198 for (nid = codec->start_nid; nid < end_nid; nid++) {
1199 unsigned int wid_caps = get_wcaps(codec, nid);
1200 unsigned int wid_type = get_wcaps_type(wid_caps);
1201
1202 if (wid_type != AC_WID_PIN)
1203 continue;
7ef166b8 1204
f82d7d16 1205 if (nid == pin_nid)
7ef166b8
WX		 1206 continue;
1207
f82d7d16 1208 curr = snd_hda_codec_read(codec, nid, 0,
7ef166b8 1209 AC_VERB_GET_CONNECT_SEL, 0);
f82d7d16
ML		 1210 if (curr != mux_idx)
1211 continue;
7ef166b8 1212
f82d7d16
ML		 1213 /* choose an unassigned converter. The conveters in the
1214 * connection list are in the same order as in the codec.
1215 */
1216 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1217 per_cvt = get_cvt(spec, cvt_idx);
1218 if (!per_cvt->assigned) {
1219 snd_printdd("choose cvt %d for pin nid %d\n",
1220 cvt_idx, nid);
1221 snd_hda_codec_write_cache(codec, nid, 0,
7ef166b8 1222 AC_VERB_SET_CONNECT_SEL,
f82d7d16
ML		 1223 cvt_idx);
1224 break;
1225 }
7ef166b8
WX		 1226 }
1227 }
1228}
1229
1230/*
1231 * HDA PCM callbacks
1232 */
1233static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1234 struct hda_codec *codec,
1235 struct snd_pcm_substream *substream)
1236{
1237 struct hdmi_spec *spec = codec->spec;
1238 struct snd_pcm_runtime *runtime = substream->runtime;
1239 int pin_idx, cvt_idx, mux_idx = 0;
1240 struct hdmi_spec_per_pin *per_pin;
1241 struct hdmi_eld *eld;
1242 struct hdmi_spec_per_cvt *per_cvt = NULL;
1243 int err;
1244
1245 /* Validate hinfo */
1246 pin_idx = hinfo_to_pin_index(spec, hinfo);
1247 if (snd_BUG_ON(pin_idx < 0))
1248 return -EINVAL;
1249 per_pin = get_pin(spec, pin_idx);
1250 eld = &per_pin->sink_eld;
1251
1252 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx);
1253 if (err < 0)
1254 return err;
1255
1256 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1257 /* Claim converter */
1258 per_cvt->assigned = 1;
1df5a06a 1259 per_pin->cvt_nid = per_cvt->cvt_nid;
384a48d7
SW		 1260 hinfo->nid = per_cvt->cvt_nid;
1261
bddee96b 1262 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
384a48d7
SW		 1263 AC_VERB_SET_CONNECT_SEL,
1264 mux_idx);
7ef166b8
WX		 1265
1266 /* configure unused pins to choose other converters */
fb87fa3a 1267 if (is_haswell(codec))
f82d7d16 1268 haswell_config_cvts(codec, per_pin->pin_nid, mux_idx);
7ef166b8 1269
384a48d7 1270 snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
bbbe3390 1271
2def8172 1272 /* Initially set the converter's capabilities */
384a48d7
SW		 1273 hinfo->channels_min = per_cvt->channels_min;
1274 hinfo->channels_max = per_cvt->channels_max;
1275 hinfo->rates = per_cvt->rates;
1276 hinfo->formats = per_cvt->formats;
1277 hinfo->maxbps = per_cvt->maxbps;
2def8172 1278
384a48d7 1279 /* Restrict capabilities by ELD if this isn't disabled */
c3d52105 1280 if (!static_hdmi_pcm && eld->eld_valid) {
1613d6b4 1281 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
bbbe3390 1282 if (hinfo->channels_min > hinfo->channels_max ||
2ad779b7
TI		 1283 !hinfo->rates || !hinfo->formats) {
1284 per_cvt->assigned = 0;
1285 hinfo->nid = 0;
1286 snd_hda_spdif_ctls_unassign(codec, pin_idx);
bbbe3390 1287 return -ENODEV;
2ad779b7 1288 }
bbbe3390 1289 }
2def8172
SW		 1290
1291 /* Store the updated parameters */
639cef0e
TI		 1292 runtime->hw.channels_min = hinfo->channels_min;
1293 runtime->hw.channels_max = hinfo->channels_max;
1294 runtime->hw.formats = hinfo->formats;
1295 runtime->hw.rates = hinfo->rates;
4fe2ca14
TI		 1296
1297 snd_pcm_hw_constraint_step(substream->runtime, 0,
1298 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
bbbe3390
TI		 1299 return 0;
1300}
1301
079d88cc
WF		 1302/*
1303 * HDA/HDMI auto parsing
1304 */
384a48d7 1305static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
079d88cc
WF		 1306{
1307 struct hdmi_spec *spec = codec->spec;
bce0d2a8 1308 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1309 hda_nid_t pin_nid = per_pin->pin_nid;
079d88cc
WF		 1310
1311 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1312 snd_printk(KERN_WARNING
1313 "HDMI: pin %d wcaps %#x "
1314 "does not support connection list\n",
1315 pin_nid, get_wcaps(codec, pin_nid));
1316 return -EINVAL;
1317 }
1318
384a48d7
SW		 1319 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1320 per_pin->mux_nids,
1321 HDA_MAX_CONNECTIONS);
079d88cc
WF		 1322
1323 return 0;
1324}
1325
c6e8453e 1326static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
079d88cc 1327{
744626da 1328 struct hda_codec *codec = per_pin->codec;
4bd038f9
DH		 1329 struct hdmi_spec *spec = codec->spec;
1330 struct hdmi_eld *eld = &spec->temp_eld;
1331 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
744626da 1332 hda_nid_t pin_nid = per_pin->pin_nid;
5d44f927
SW		 1333 /*
1334 * Always execute a GetPinSense verb here, even when called from
1335 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1336 * response's PD bit is not the real PD value, but indicates that
1337 * the real PD value changed. An older version of the HD-audio
1338 * specification worked this way. Hence, we just ignore the data in
1339 * the unsolicited response to avoid custom WARs.
1340 */
079d88cc 1341 int present = snd_hda_pin_sense(codec, pin_nid);
4bd038f9
DH		 1342 bool update_eld = false;
1343 bool eld_changed = false;
079d88cc 1344
cbbaa603 1345 mutex_lock(&pin_eld->lock);
4bd038f9
DH		 1346 pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1347 if (pin_eld->monitor_present)
1348 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1349 else
1350 eld->eld_valid = false;
079d88cc 1351
fae3d88a 1352 _snd_printd(SND_PR_VERBOSE,
384a48d7 1353 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
10250911 1354 codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
5d44f927 1355
4bd038f9 1356 if (eld->eld_valid) {
1613d6b4
DH		 1357 if (snd_hdmi_get_eld(codec, pin_nid, eld->eld_buffer,
1358 &eld->eld_size) < 0)
4bd038f9 1359 eld->eld_valid = false;
1613d6b4
DH		 1360 else {
1361 memset(&eld->info, 0, sizeof(struct parsed_hdmi_eld));
1362 if (snd_hdmi_parse_eld(&eld->info, eld->eld_buffer,
1363 eld->eld_size) < 0)
4bd038f9 1364 eld->eld_valid = false;
1613d6b4
DH		 1365 }
1366
4bd038f9 1367 if (eld->eld_valid) {
1613d6b4 1368 snd_hdmi_show_eld(&eld->info);
4bd038f9 1369 update_eld = true;
1613d6b4 1370 }
c6e8453e 1371 else if (repoll) {
744626da
WF		 1372 queue_delayed_work(codec->bus->workq,
1373 &per_pin->work,
1374 msecs_to_jiffies(300));
cbbaa603 1375 goto unlock;
744626da
WF		 1376 }
1377 }
4bd038f9 1378
92c69e79 1379 if (pin_eld->eld_valid && !eld->eld_valid) {
4bd038f9 1380 update_eld = true;
92c69e79
DH		 1381 eld_changed = true;
1382 }
4bd038f9 1383 if (update_eld) {
b054087d 1384 bool old_eld_valid = pin_eld->eld_valid;
4bd038f9 1385 pin_eld->eld_valid = eld->eld_valid;
92c69e79
DH		 1386 eld_changed = pin_eld->eld_size != eld->eld_size ||
1387 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
4bd038f9
DH		 1388 eld->eld_size) != 0;
1389 if (eld_changed)
1390 memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1391 eld->eld_size);
1392 pin_eld->eld_size = eld->eld_size;
1393 pin_eld->info = eld->info;
b054087d
TI		 1394
1395 /* Haswell-specific workaround: re-setup when the transcoder is
1396 * changed during the stream playback
1397 */
fb87fa3a 1398 if (is_haswell(codec) &&
58f7d28d 1399 eld->eld_valid && !old_eld_valid && per_pin->setup)
b054087d
TI		 1400 hdmi_setup_audio_infoframe(codec, per_pin,
1401 per_pin->non_pcm);
4bd038f9 1402 }
92c69e79
DH		 1403
1404 if (eld_changed)
1405 snd_ctl_notify(codec->bus->card,
1406 SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO,
1407 &per_pin->eld_ctl->id);
cbbaa603
TI		 1408 unlock:
1409 mutex_unlock(&pin_eld->lock);
079d88cc
WF		 1410}
1411
744626da
WF		 1412static void hdmi_repoll_eld(struct work_struct *work)
1413{
1414 struct hdmi_spec_per_pin *per_pin =
1415 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1416
c6e8453e
WF		 1417 if (per_pin->repoll_count++ > 6)
1418 per_pin->repoll_count = 0;
1419
1420 hdmi_present_sense(per_pin, per_pin->repoll_count);
744626da
WF		 1421}
1422
c88d4e84
TI		 1423static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1424 hda_nid_t nid);
1425
079d88cc
WF		 1426static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1427{
1428 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1429 unsigned int caps, config;
1430 int pin_idx;
1431 struct hdmi_spec_per_pin *per_pin;
07acecc1 1432 int err;
079d88cc 1433
efc2f8de 1434 caps = snd_hda_query_pin_caps(codec, pin_nid);
384a48d7
SW		 1435 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1436 return 0;
1437
efc2f8de 1438 config = snd_hda_codec_get_pincfg(codec, pin_nid);
384a48d7
SW		 1439 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1440 return 0;
1441
fb87fa3a 1442 if (is_haswell(codec))
c88d4e84
TI		 1443 intel_haswell_fixup_connect_list(codec, pin_nid);
1444
384a48d7 1445 pin_idx = spec->num_pins;
bce0d2a8
TI		 1446 per_pin = snd_array_new(&spec->pins);
1447 if (!per_pin)
1448 return -ENOMEM;
384a48d7
SW		 1449
1450 per_pin->pin_nid = pin_nid;
1a6003b5 1451 per_pin->non_pcm = false;
079d88cc 1452
384a48d7
SW		 1453 err = hdmi_read_pin_conn(codec, pin_idx);
1454 if (err < 0)
1455 return err;
079d88cc 1456
079d88cc
WF		 1457 spec->num_pins++;
1458
384a48d7 1459 return 0;
079d88cc
WF		 1460}
1461
384a48d7 1462static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc
WF		 1463{
1464 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1465 struct hdmi_spec_per_cvt *per_cvt;
1466 unsigned int chans;
1467 int err;
079d88cc 1468
384a48d7
SW		 1469 chans = get_wcaps(codec, cvt_nid);
1470 chans = get_wcaps_channels(chans);
1471
bce0d2a8
TI		 1472 per_cvt = snd_array_new(&spec->cvts);
1473 if (!per_cvt)
1474 return -ENOMEM;
384a48d7
SW		 1475
1476 per_cvt->cvt_nid = cvt_nid;
1477 per_cvt->channels_min = 2;
d45e6889 1478 if (chans <= 16) {
384a48d7 1479 per_cvt->channels_max = chans;
d45e6889
TI		 1480 if (chans > spec->channels_max)
1481 spec->channels_max = chans;
1482 }
384a48d7
SW		 1483
1484 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1485 &per_cvt->rates,
1486 &per_cvt->formats,
1487 &per_cvt->maxbps);
1488 if (err < 0)
1489 return err;
1490
bce0d2a8
TI		 1491 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1492 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1493 spec->num_cvts++;
079d88cc
WF		 1494
1495 return 0;
1496}
1497
1498static int hdmi_parse_codec(struct hda_codec *codec)
1499{
1500 hda_nid_t nid;
1501 int i, nodes;
1502
1503 nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid);
1504 if (!nid || nodes < 0) {
1505 snd_printk(KERN_WARNING "HDMI: failed to get afg sub nodes\n");
1506 return -EINVAL;
1507 }
1508
1509 for (i = 0; i < nodes; i++, nid++) {
1510 unsigned int caps;
1511 unsigned int type;
1512
efc2f8de 1513 caps = get_wcaps(codec, nid);
079d88cc
WF		 1514 type = get_wcaps_type(caps);
1515
1516 if (!(caps & AC_WCAP_DIGITAL))
1517 continue;
1518
1519 switch (type) {
1520 case AC_WID_AUD_OUT:
384a48d7 1521 hdmi_add_cvt(codec, nid);
079d88cc
WF		 1522 break;
1523 case AC_WID_PIN:
3eaead57 1524 hdmi_add_pin(codec, nid);
079d88cc
WF		 1525 break;
1526 }
1527 }
1528
c9adeefd
DH		 1529#ifdef CONFIG_PM
1530 /* We're seeing some problems with unsolicited hot plug events on
1531 * PantherPoint after S3, if this is not enabled */
1532 if (codec->vendor_id == 0x80862806)
1533 codec->bus->power_keep_link_on = 1;
079d88cc
WF		 1534 /*
1535 * G45/IbexPeak don't support EPSS: the unsolicited pin hot plug event
1536 * can be lost and presence sense verb will become inaccurate if the
1537 * HDA link is powered off at hot plug or hw initialization time.
1538 */
c9adeefd 1539 else if (!(snd_hda_param_read(codec, codec->afg, AC_PAR_POWER_STATE) &
079d88cc
WF		 1540 AC_PWRST_EPSS))
1541 codec->bus->power_keep_link_on = 1;
1542#endif
1543
1544 return 0;
1545}
1546
84eb01be
TI		 1547/*
1548 */
1a6003b5
TI		 1549static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1550{
1551 struct hda_spdif_out *spdif;
1552 bool non_pcm;
1553
1554 mutex_lock(&codec->spdif_mutex);
1555 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1556 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1557 mutex_unlock(&codec->spdif_mutex);
1558 return non_pcm;
1559}
1560
1561
84eb01be
TI		 1562/*
1563 * HDMI callbacks
1564 */
1565
1566static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1567 struct hda_codec *codec,
1568 unsigned int stream_tag,
1569 unsigned int format,
1570 struct snd_pcm_substream *substream)
1571{
384a48d7
SW		 1572 hda_nid_t cvt_nid = hinfo->nid;
1573 struct hdmi_spec *spec = codec->spec;
1574 int pin_idx = hinfo_to_pin_index(spec, hinfo);
b054087d
TI		 1575 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1576 hda_nid_t pin_nid = per_pin->pin_nid;
1a6003b5
TI		 1577 bool non_pcm;
1578
1579 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
cbbaa603 1580 mutex_lock(&per_pin->sink_eld.lock);
b054087d
TI		 1581 per_pin->channels = substream->runtime->channels;
1582 per_pin->setup = true;
384a48d7 1583
b054087d 1584 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
cbbaa603 1585 mutex_unlock(&per_pin->sink_eld.lock);
84eb01be 1586
384a48d7 1587 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
84eb01be
TI		 1588}
1589
8dfaa573
TI		 1590static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1591 struct hda_codec *codec,
1592 struct snd_pcm_substream *substream)
1593{
1594 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1595 return 0;
1596}
1597
f2ad24fa
TI		 1598static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1599 struct hda_codec *codec,
1600 struct snd_pcm_substream *substream)
384a48d7
SW		 1601{
1602 struct hdmi_spec *spec = codec->spec;
1603 int cvt_idx, pin_idx;
1604 struct hdmi_spec_per_cvt *per_cvt;
1605 struct hdmi_spec_per_pin *per_pin;
384a48d7 1606
384a48d7
SW		 1607 if (hinfo->nid) {
1608 cvt_idx = cvt_nid_to_cvt_index(spec, hinfo->nid);
1609 if (snd_BUG_ON(cvt_idx < 0))
1610 return -EINVAL;
bce0d2a8 1611 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1612
1613 snd_BUG_ON(!per_cvt->assigned);
1614 per_cvt->assigned = 0;
1615 hinfo->nid = 0;
1616
1617 pin_idx = hinfo_to_pin_index(spec, hinfo);
1618 if (snd_BUG_ON(pin_idx < 0))
1619 return -EINVAL;
bce0d2a8 1620 per_pin = get_pin(spec, pin_idx);
384a48d7 1621
384a48d7 1622 snd_hda_spdif_ctls_unassign(codec, pin_idx);
cbbaa603
TI		 1623
1624 mutex_lock(&per_pin->sink_eld.lock);
d45e6889
TI		 1625 per_pin->chmap_set = false;
1626 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
b054087d
TI		 1627
1628 per_pin->setup = false;
1629 per_pin->channels = 0;
cbbaa603 1630 mutex_unlock(&per_pin->sink_eld.lock);
384a48d7 1631 }
d45e6889 1632
384a48d7
SW		 1633 return 0;
1634}
1635
1636static const struct hda_pcm_ops generic_ops = {
1637 .open = hdmi_pcm_open,
f2ad24fa 1638 .close = hdmi_pcm_close,
384a48d7 1639 .prepare = generic_hdmi_playback_pcm_prepare,
8dfaa573 1640 .cleanup = generic_hdmi_playback_pcm_cleanup,
84eb01be
TI		 1641};
1642
d45e6889
TI		 1643/*
1644 * ALSA API channel-map control callbacks
1645 */
1646static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
1647 struct snd_ctl_elem_info *uinfo)
1648{
1649 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1650 struct hda_codec *codec = info->private_data;
1651 struct hdmi_spec *spec = codec->spec;
1652 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1653 uinfo->count = spec->channels_max;
1654 uinfo->value.integer.min = 0;
1655 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
1656 return 0;
1657}
1658
1659static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
1660 unsigned int size, unsigned int __user *tlv)
1661{
1662 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1663 struct hda_codec *codec = info->private_data;
1664 struct hdmi_spec *spec = codec->spec;
d45e6889
TI		 1665 unsigned int __user *dst;
1666 int chs, count = 0;
1667
1668 if (size < 8)
1669 return -ENOMEM;
1670 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
1671 return -EFAULT;
1672 size -= 8;
1673 dst = tlv + 2;
498dab3a 1674 for (chs = 2; chs <= spec->channels_max; chs++) {
d45e6889
TI		 1675 int i, c;
1676 struct cea_channel_speaker_allocation *cap;
1677 cap = channel_allocations;
1678 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
1679 int chs_bytes = chs * 4;
1680 if (cap->channels != chs)
1681 continue;
d45e6889
TI		 1682 if (size < 8)
1683 return -ENOMEM;
1684 if (put_user(SNDRV_CTL_TLVT_CHMAP_VAR, dst) ||
1685 put_user(chs_bytes, dst + 1))
1686 return -EFAULT;
1687 dst += 2;
1688 size -= 8;
1689 count += 8;
1690 if (size < chs_bytes)
1691 return -ENOMEM;
1692 size -= chs_bytes;
1693 count += chs_bytes;
1694 for (c = 7; c >= 0; c--) {
1695 int spk = cap->speakers[c];
1696 if (!spk)
1697 continue;
1698 if (put_user(spk_to_chmap(spk), dst))
1699 return -EFAULT;
1700 dst++;
1701 }
1702 }
1703 }
1704 if (put_user(count, tlv + 1))
1705 return -EFAULT;
1706 return 0;
1707}
1708
1709static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
1710 struct snd_ctl_elem_value *ucontrol)
1711{
1712 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1713 struct hda_codec *codec = info->private_data;
1714 struct hdmi_spec *spec = codec->spec;
1715 int pin_idx = kcontrol->private_value;
bce0d2a8 1716 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
d45e6889
TI		 1717 int i;
1718
1719 for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
1720 ucontrol->value.integer.value[i] = per_pin->chmap[i];
1721 return 0;
1722}
1723
1724static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
1725 struct snd_ctl_elem_value *ucontrol)
1726{
1727 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1728 struct hda_codec *codec = info->private_data;
1729 struct hdmi_spec *spec = codec->spec;
1730 int pin_idx = kcontrol->private_value;
bce0d2a8 1731 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
d45e6889
TI		 1732 unsigned int ctl_idx;
1733 struct snd_pcm_substream *substream;
1734 unsigned char chmap[8];
1735 int i, ca, prepared = 0;
1736
1737 ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
1738 substream = snd_pcm_chmap_substream(info, ctl_idx);
1739 if (!substream || !substream->runtime)
6f54c361 1740 return 0; /* just for avoiding error from alsactl restore */
d45e6889
TI		 1741 switch (substream->runtime->status->state) {
1742 case SNDRV_PCM_STATE_OPEN:
1743 case SNDRV_PCM_STATE_SETUP:
1744 break;
1745 case SNDRV_PCM_STATE_PREPARED:
1746 prepared = 1;
1747 break;
1748 default:
1749 return -EBUSY;
1750 }
1751 memset(chmap, 0, sizeof(chmap));
1752 for (i = 0; i < ARRAY_SIZE(chmap); i++)
1753 chmap[i] = ucontrol->value.integer.value[i];
1754 if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
1755 return 0;
1756 ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
1757 if (ca < 0)
1758 return -EINVAL;
cbbaa603 1759 mutex_lock(&per_pin->sink_eld.lock);
d45e6889
TI		 1760 per_pin->chmap_set = true;
1761 memcpy(per_pin->chmap, chmap, sizeof(chmap));
1762 if (prepared)
b054087d 1763 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
cbbaa603 1764 mutex_unlock(&per_pin->sink_eld.lock);
d45e6889
TI		 1765
1766 return 0;
1767}
1768
84eb01be
TI		 1769static int generic_hdmi_build_pcms(struct hda_codec *codec)
1770{
1771 struct hdmi_spec *spec = codec->spec;
384a48d7 1772 int pin_idx;
84eb01be 1773
384a48d7
SW		 1774 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1775 struct hda_pcm *info;
84eb01be 1776 struct hda_pcm_stream *pstr;
bce0d2a8
TI		 1777 struct hdmi_spec_per_pin *per_pin;
1778
1779 per_pin = get_pin(spec, pin_idx);
1780 sprintf(per_pin->pcm_name, "HDMI %d", pin_idx);
1781 info = snd_array_new(&spec->pcm_rec);
1782 if (!info)
1783 return -ENOMEM;
1784 info->name = per_pin->pcm_name;
84eb01be 1785 info->pcm_type = HDA_PCM_TYPE_HDMI;
d45e6889 1786 info->own_chmap = true;
384a48d7 1787
84eb01be 1788 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
384a48d7
SW		 1789 pstr->substreams = 1;
1790 pstr->ops = generic_ops;
1791 /* other pstr fields are set in open */
84eb01be
TI		 1792 }
1793
384a48d7 1794 codec->num_pcms = spec->num_pins;
bce0d2a8 1795 codec->pcm_info = spec->pcm_rec.list;
384a48d7 1796
84eb01be
TI		 1797 return 0;
1798}
1799
0b6c49b5
DH		 1800static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
1801{
31ef2257 1802 char hdmi_str[32] = "HDMI/DP";
0b6c49b5 1803 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 1804 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1805 int pcmdev = get_pcm_rec(spec, pin_idx)->device;
0b6c49b5 1806
31ef2257
TI		 1807 if (pcmdev > 0)
1808 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
30efd8de
DH		 1809 if (!is_jack_detectable(codec, per_pin->pin_nid))
1810 strncat(hdmi_str, " Phantom",
1811 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
0b6c49b5 1812
31ef2257 1813 return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, 0);
0b6c49b5
DH		 1814}
1815
84eb01be
TI		 1816static int generic_hdmi_build_controls(struct hda_codec *codec)
1817{
1818 struct hdmi_spec *spec = codec->spec;
1819 int err;
384a48d7 1820 int pin_idx;
84eb01be 1821
384a48d7 1822 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 1823 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
0b6c49b5
DH		 1824
1825 err = generic_hdmi_build_jack(codec, pin_idx);
1826 if (err < 0)
1827 return err;
1828
dcda5806
TI		 1829 err = snd_hda_create_dig_out_ctls(codec,
1830 per_pin->pin_nid,
1831 per_pin->mux_nids[0],
1832 HDA_PCM_TYPE_HDMI);
84eb01be
TI		 1833 if (err < 0)
1834 return err;
384a48d7 1835 snd_hda_spdif_ctls_unassign(codec, pin_idx);
14bc52b8
PLB		 1836
1837 /* add control for ELD Bytes */
bce0d2a8
TI		 1838 err = hdmi_create_eld_ctl(codec, pin_idx,
1839 get_pcm_rec(spec, pin_idx)->device);
14bc52b8
PLB		 1840
1841 if (err < 0)
1842 return err;
31ef2257 1843
82b1d73f 1844 hdmi_present_sense(per_pin, 0);
84eb01be
TI		 1845 }
1846
d45e6889
TI		 1847 /* add channel maps */
1848 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1849 struct snd_pcm_chmap *chmap;
1850 struct snd_kcontrol *kctl;
1851 int i;
2ca320e2
TI		 1852
1853 if (!codec->pcm_info[pin_idx].pcm)
1854 break;
d45e6889
TI		 1855 err = snd_pcm_add_chmap_ctls(codec->pcm_info[pin_idx].pcm,
1856 SNDRV_PCM_STREAM_PLAYBACK,
1857 NULL, 0, pin_idx, &chmap);
1858 if (err < 0)
1859 return err;
1860 /* override handlers */
1861 chmap->private_data = codec;
1862 kctl = chmap->kctl;
1863 for (i = 0; i < kctl->count; i++)
1864 kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
1865 kctl->info = hdmi_chmap_ctl_info;
1866 kctl->get = hdmi_chmap_ctl_get;
1867 kctl->put = hdmi_chmap_ctl_put;
1868 kctl->tlv.c = hdmi_chmap_ctl_tlv;
1869 }
1870
84eb01be
TI		 1871 return 0;
1872}
1873
8b8d654b 1874static int generic_hdmi_init_per_pins(struct hda_codec *codec)
84eb01be
TI		 1875{
1876 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1877 int pin_idx;
1878
1879 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 1880 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1881 struct hdmi_eld *eld = &per_pin->sink_eld;
84eb01be 1882
744626da 1883 per_pin->codec = codec;
4bd038f9 1884 mutex_init(&eld->lock);
744626da 1885 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
384a48d7 1886 snd_hda_eld_proc_new(codec, eld, pin_idx);
84eb01be 1887 }
8b8d654b
TI		 1888 return 0;
1889}
1890
1891static int generic_hdmi_init(struct hda_codec *codec)
1892{
1893 struct hdmi_spec *spec = codec->spec;
1894 int pin_idx;
1895
1896 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 1897 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
8b8d654b
TI		 1898 hda_nid_t pin_nid = per_pin->pin_nid;
1899
1900 hdmi_init_pin(codec, pin_nid);
1901 snd_hda_jack_detect_enable(codec, pin_nid, pin_nid);
1902 }
84eb01be
TI		 1903 return 0;
1904}
1905
bce0d2a8
TI		 1906static void hdmi_array_init(struct hdmi_spec *spec, int nums)
1907{
1908 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
1909 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
1910 snd_array_init(&spec->pcm_rec, sizeof(struct hda_pcm), nums);
1911}
1912
1913static void hdmi_array_free(struct hdmi_spec *spec)
1914{
1915 snd_array_free(&spec->pins);
1916 snd_array_free(&spec->cvts);
1917 snd_array_free(&spec->pcm_rec);
1918}
1919
84eb01be
TI		 1920static void generic_hdmi_free(struct hda_codec *codec)
1921{
1922 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1923 int pin_idx;
1924
1925 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 1926 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1927 struct hdmi_eld *eld = &per_pin->sink_eld;
84eb01be 1928
744626da 1929 cancel_delayed_work(&per_pin->work);
384a48d7
SW		 1930 snd_hda_eld_proc_free(codec, eld);
1931 }
84eb01be 1932
744626da 1933 flush_workqueue(codec->bus->workq);
bce0d2a8 1934 hdmi_array_free(spec);
84eb01be
TI		 1935 kfree(spec);
1936}
1937
28cb72e5
WX		 1938#ifdef CONFIG_PM
1939static int generic_hdmi_resume(struct hda_codec *codec)
1940{
1941 struct hdmi_spec *spec = codec->spec;
1942 int pin_idx;
1943
1944 generic_hdmi_init(codec);
1945 snd_hda_codec_resume_amp(codec);
1946 snd_hda_codec_resume_cache(codec);
1947
1948 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1949 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1950 hdmi_present_sense(per_pin, 1);
1951 }
1952 return 0;
1953}
1954#endif
1955
fb79e1e0 1956static const struct hda_codec_ops generic_hdmi_patch_ops = {
84eb01be
TI		 1957 .init = generic_hdmi_init,
1958 .free = generic_hdmi_free,
1959 .build_pcms = generic_hdmi_build_pcms,
1960 .build_controls = generic_hdmi_build_controls,
1961 .unsol_event = hdmi_unsol_event,
28cb72e5
WX		 1962#ifdef CONFIG_PM
1963 .resume = generic_hdmi_resume,
1964#endif
84eb01be
TI		 1965};
1966
6ffe168f 1967
c88d4e84
TI		 1968static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1969 hda_nid_t nid)
1970{
1971 struct hdmi_spec *spec = codec->spec;
1972 hda_nid_t conns[4];
1973 int nconns;
6ffe168f 1974
c88d4e84
TI		 1975 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
1976 if (nconns == spec->num_cvts &&
1977 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
6ffe168f
ML		 1978 return;
1979
c88d4e84
TI		 1980 /* override pins connection list */
1981 snd_printdd("hdmi: haswell: override pin connection 0x%x\n", nid);
1982 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
6ffe168f
ML		 1983}
1984
1611a9c9
ML		 1985#define INTEL_VENDOR_NID 0x08
1986#define INTEL_GET_VENDOR_VERB 0xf81
1987#define INTEL_SET_VENDOR_VERB 0x781
1988#define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
1989#define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
1990
1991static void intel_haswell_enable_all_pins(struct hda_codec *codec,
17df3f55 1992 bool update_tree)
1611a9c9
ML		 1993{
1994 unsigned int vendor_param;
1995
1611a9c9
ML		 1996 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
1997 INTEL_GET_VENDOR_VERB, 0);
1998 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
1999 return;
2000
2001 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2002 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2003 INTEL_SET_VENDOR_VERB, vendor_param);
2004 if (vendor_param == -1)
2005 return;
2006
17df3f55
TI		 2007 if (update_tree)
2008 snd_hda_codec_update_widgets(codec);
1611a9c9
ML		 2009}
2010
c88d4e84
TI		 2011static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2012{
2013 unsigned int vendor_param;
2014
2015 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2016 INTEL_GET_VENDOR_VERB, 0);
2017 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2018 return;
2019
2020 /* enable DP1.2 mode */
2021 vendor_param |= INTEL_EN_DP12;
2022 snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
2023 INTEL_SET_VENDOR_VERB, vendor_param);
2024}
2025
17df3f55
TI		 2026/* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2027 * Otherwise you may get severe h/w communication errors.
2028 */
2029static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2030 unsigned int power_state)
2031{
2032 if (power_state == AC_PWRST_D0) {
2033 intel_haswell_enable_all_pins(codec, false);
2034 intel_haswell_fixup_enable_dp12(codec);
2035 }
c88d4e84 2036
17df3f55
TI		 2037 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2038 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2039}
6ffe168f 2040
84eb01be
TI		 2041static int patch_generic_hdmi(struct hda_codec *codec)
2042{
2043 struct hdmi_spec *spec;
84eb01be
TI		 2044
2045 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2046 if (spec == NULL)
2047 return -ENOMEM;
2048
2049 codec->spec = spec;
bce0d2a8 2050 hdmi_array_init(spec, 4);
6ffe168f 2051
fb87fa3a 2052 if (is_haswell(codec)) {
17df3f55 2053 intel_haswell_enable_all_pins(codec, true);
c88d4e84 2054 intel_haswell_fixup_enable_dp12(codec);
17df3f55 2055 }
6ffe168f 2056
84eb01be
TI		 2057 if (hdmi_parse_codec(codec) < 0) {
2058 codec->spec = NULL;
2059 kfree(spec);
2060 return -EINVAL;
2061 }
2062 codec->patch_ops = generic_hdmi_patch_ops;
fb87fa3a 2063 if (is_haswell(codec)) {
17df3f55 2064 codec->patch_ops.set_power_state = haswell_set_power_state;
5dc989bd
ML		 2065 codec->dp_mst = true;
2066 }
17df3f55 2067
8b8d654b 2068 generic_hdmi_init_per_pins(codec);
84eb01be 2069
84eb01be
TI		 2070 init_channel_allocations();
2071
2072 return 0;
2073}
2074
3aaf8980
SW		 2075/*
2076 * Shared non-generic implementations
2077 */
2078
2079static int simple_playback_build_pcms(struct hda_codec *codec)
2080{
2081 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2082 struct hda_pcm *info;
8ceb332d
TI		 2083 unsigned int chans;
2084 struct hda_pcm_stream *pstr;
bce0d2a8 2085 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2086
bce0d2a8
TI		 2087 per_cvt = get_cvt(spec, 0);
2088 chans = get_wcaps(codec, per_cvt->cvt_nid);
8ceb332d 2089 chans = get_wcaps_channels(chans);
3aaf8980 2090
bce0d2a8
TI		 2091 info = snd_array_new(&spec->pcm_rec);
2092 if (!info)
2093 return -ENOMEM;
2094 info->name = get_pin(spec, 0)->pcm_name;
2095 sprintf(info->name, "HDMI 0");
8ceb332d
TI		 2096 info->pcm_type = HDA_PCM_TYPE_HDMI;
2097 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2098 *pstr = spec->pcm_playback;
bce0d2a8 2099 pstr->nid = per_cvt->cvt_nid;
8ceb332d
TI		 2100 if (pstr->channels_max <= 2 && chans && chans <= 16)
2101 pstr->channels_max = chans;
3aaf8980 2102
bce0d2a8
TI		 2103 codec->num_pcms = 1;
2104 codec->pcm_info = info;
2105
3aaf8980
SW		 2106 return 0;
2107}
2108
4b6ace9e
TI		 2109/* unsolicited event for jack sensing */
2110static void simple_hdmi_unsol_event(struct hda_codec *codec,
2111 unsigned int res)
2112{
9dd8cf12 2113 snd_hda_jack_set_dirty_all(codec);
4b6ace9e
TI		 2114 snd_hda_jack_report_sync(codec);
2115}
2116
2117/* generic_hdmi_build_jack can be used for simple_hdmi, too,
2118 * as long as spec->pins[] is set correctly
2119 */
2120#define simple_hdmi_build_jack generic_hdmi_build_jack
2121
3aaf8980
SW		 2122static int simple_playback_build_controls(struct hda_codec *codec)
2123{
2124 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2125 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2126 int err;
3aaf8980 2127
bce0d2a8
TI		 2128 per_cvt = get_cvt(spec, 0);
2129 err = snd_hda_create_spdif_out_ctls(codec, per_cvt->cvt_nid,
2130 per_cvt->cvt_nid);
8ceb332d
TI		 2131 if (err < 0)
2132 return err;
2133 return simple_hdmi_build_jack(codec, 0);
3aaf8980
SW		 2134}
2135
4f0110ce
TI		 2136static int simple_playback_init(struct hda_codec *codec)
2137{
2138 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 2139 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2140 hda_nid_t pin = per_pin->pin_nid;
8ceb332d
TI		 2141
2142 snd_hda_codec_write(codec, pin, 0,
2143 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2144 /* some codecs require to unmute the pin */
2145 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2146 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2147 AMP_OUT_UNMUTE);
2148 snd_hda_jack_detect_enable(codec, pin, pin);
4f0110ce
TI		 2149 return 0;
2150}
2151
3aaf8980
SW		 2152static void simple_playback_free(struct hda_codec *codec)
2153{
2154 struct hdmi_spec *spec = codec->spec;
2155
bce0d2a8 2156 hdmi_array_free(spec);
3aaf8980
SW		 2157 kfree(spec);
2158}
2159
84eb01be
TI		 2160/*
2161 * Nvidia specific implementations
2162 */
2163
2164#define Nv_VERB_SET_Channel_Allocation 0xF79
2165#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2166#define Nv_VERB_SET_Audio_Protection_On 0xF98
2167#define Nv_VERB_SET_Audio_Protection_Off 0xF99
2168
2169#define nvhdmi_master_con_nid_7x 0x04
2170#define nvhdmi_master_pin_nid_7x 0x05
2171
fb79e1e0 2172static const hda_nid_t nvhdmi_con_nids_7x[4] = {
84eb01be
TI		 2173 /*front, rear, clfe, rear_surr */
2174 0x6, 0x8, 0xa, 0xc,
2175};
2176
ceaa86ba
TI		 2177static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2178 /* set audio protect on */
2179 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2180 /* enable digital output on pin widget */
2181 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2182 {} /* terminator */
2183};
2184
2185static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
84eb01be
TI		 2186 /* set audio protect on */
2187 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2188 /* enable digital output on pin widget */
2189 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2190 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2191 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2192 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2193 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2194 {} /* terminator */
2195};
2196
2197#ifdef LIMITED_RATE_FMT_SUPPORT
2198/* support only the safe format and rate */
2199#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2200#define SUPPORTED_MAXBPS 16
2201#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2202#else
2203/* support all rates and formats */
2204#define SUPPORTED_RATES \
2205 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2206 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2207 SNDRV_PCM_RATE_192000)
2208#define SUPPORTED_MAXBPS 24
2209#define SUPPORTED_FORMATS \
2210 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2211#endif
2212
ceaa86ba
TI		 2213static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2214{
2215 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2216 return 0;
2217}
2218
2219static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
84eb01be 2220{
ceaa86ba 2221 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
84eb01be
TI		 2222 return 0;
2223}
2224
393004b2
ND		 2225static unsigned int channels_2_6_8[] = {
2226 2, 6, 8
2227};
2228
2229static unsigned int channels_2_8[] = {
2230 2, 8
2231};
2232
2233static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2234 .count = ARRAY_SIZE(channels_2_6_8),
2235 .list = channels_2_6_8,
2236 .mask = 0,
2237};
2238
2239static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2240 .count = ARRAY_SIZE(channels_2_8),
2241 .list = channels_2_8,
2242 .mask = 0,
2243};
2244
84eb01be
TI		 2245static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2246 struct hda_codec *codec,
2247 struct snd_pcm_substream *substream)
2248{
2249 struct hdmi_spec *spec = codec->spec;
393004b2
ND		 2250 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2251
2252 switch (codec->preset->id) {
2253 case 0x10de0002:
2254 case 0x10de0003:
2255 case 0x10de0005:
2256 case 0x10de0006:
2257 hw_constraints_channels = &hw_constraints_2_8_channels;
2258 break;
2259 case 0x10de0007:
2260 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2261 break;
2262 default:
2263 break;
2264 }
2265
2266 if (hw_constraints_channels != NULL) {
2267 snd_pcm_hw_constraint_list(substream->runtime, 0,
2268 SNDRV_PCM_HW_PARAM_CHANNELS,
2269 hw_constraints_channels);
ad09fc9d
TI		 2270 } else {
2271 snd_pcm_hw_constraint_step(substream->runtime, 0,
2272 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
393004b2
ND		 2273 }
2274
84eb01be
TI		 2275 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2276}
2277
2278static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2279 struct hda_codec *codec,
2280 struct snd_pcm_substream *substream)
2281{
2282 struct hdmi_spec *spec = codec->spec;
2283 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2284}
2285
2286static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2287 struct hda_codec *codec,
2288 unsigned int stream_tag,
2289 unsigned int format,
2290 struct snd_pcm_substream *substream)
2291{
2292 struct hdmi_spec *spec = codec->spec;
2293 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2294 stream_tag, format, substream);
2295}
2296
d0b1252d
TI		 2297static const struct hda_pcm_stream simple_pcm_playback = {
2298 .substreams = 1,
2299 .channels_min = 2,
2300 .channels_max = 2,
2301 .ops = {
2302 .open = simple_playback_pcm_open,
2303 .close = simple_playback_pcm_close,
2304 .prepare = simple_playback_pcm_prepare
2305 },
2306};
2307
2308static const struct hda_codec_ops simple_hdmi_patch_ops = {
2309 .build_controls = simple_playback_build_controls,
2310 .build_pcms = simple_playback_build_pcms,
2311 .init = simple_playback_init,
2312 .free = simple_playback_free,
250e41ac 2313 .unsol_event = simple_hdmi_unsol_event,
d0b1252d
TI		 2314};
2315
2316static int patch_simple_hdmi(struct hda_codec *codec,
2317 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2318{
2319 struct hdmi_spec *spec;
bce0d2a8
TI		 2320 struct hdmi_spec_per_cvt *per_cvt;
2321 struct hdmi_spec_per_pin *per_pin;
d0b1252d
TI		 2322
2323 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2324 if (!spec)
2325 return -ENOMEM;
2326
2327 codec->spec = spec;
bce0d2a8 2328 hdmi_array_init(spec, 1);
d0b1252d
TI		 2329
2330 spec->multiout.num_dacs = 0; /* no analog */
2331 spec->multiout.max_channels = 2;
2332 spec->multiout.dig_out_nid = cvt_nid;
2333 spec->num_cvts = 1;
2334 spec->num_pins = 1;
bce0d2a8
TI		 2335 per_pin = snd_array_new(&spec->pins);
2336 per_cvt = snd_array_new(&spec->cvts);
2337 if (!per_pin || !per_cvt) {
2338 simple_playback_free(codec);
2339 return -ENOMEM;
2340 }
2341 per_cvt->cvt_nid = cvt_nid;
2342 per_pin->pin_nid = pin_nid;
d0b1252d
TI		 2343 spec->pcm_playback = simple_pcm_playback;
2344
2345 codec->patch_ops = simple_hdmi_patch_ops;
2346
2347 return 0;
2348}
2349
1f348522
AP		 2350static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2351 int channels)
2352{
2353 unsigned int chanmask;
2354 int chan = channels ? (channels - 1) : 1;
2355
2356 switch (channels) {
2357 default:
2358 case 0:
2359 case 2:
2360 chanmask = 0x00;
2361 break;
2362 case 4:
2363 chanmask = 0x08;
2364 break;
2365 case 6:
2366 chanmask = 0x0b;
2367 break;
2368 case 8:
2369 chanmask = 0x13;
2370 break;
2371 }
2372
2373 /* Set the audio infoframe channel allocation and checksum fields. The
2374 * channel count is computed implicitly by the hardware. */
2375 snd_hda_codec_write(codec, 0x1, 0,
2376 Nv_VERB_SET_Channel_Allocation, chanmask);
2377
2378 snd_hda_codec_write(codec, 0x1, 0,
2379 Nv_VERB_SET_Info_Frame_Checksum,
2380 (0x71 - chan - chanmask));
2381}
2382
84eb01be
TI		 2383static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2384 struct hda_codec *codec,
2385 struct snd_pcm_substream *substream)
2386{
2387 struct hdmi_spec *spec = codec->spec;
2388 int i;
2389
2390 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2391 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2392 for (i = 0; i < 4; i++) {
2393 /* set the stream id */
2394 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2395 AC_VERB_SET_CHANNEL_STREAMID, 0);
2396 /* set the stream format */
2397 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2398 AC_VERB_SET_STREAM_FORMAT, 0);
2399 }
2400
1f348522
AP		 2401 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2402 * streams are disabled. */
2403 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2404
84eb01be
TI		 2405 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2406}
2407
2408static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2409 struct hda_codec *codec,
2410 unsigned int stream_tag,
2411 unsigned int format,
2412 struct snd_pcm_substream *substream)
2413{
2414 int chs;
112daa7a 2415 unsigned int dataDCC2, channel_id;
84eb01be 2416 int i;
7c935976 2417 struct hdmi_spec *spec = codec->spec;
e3245cdd 2418 struct hda_spdif_out *spdif;
bce0d2a8 2419 struct hdmi_spec_per_cvt *per_cvt;
84eb01be
TI		 2420
2421 mutex_lock(&codec->spdif_mutex);
bce0d2a8
TI		 2422 per_cvt = get_cvt(spec, 0);
2423 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
84eb01be
TI		 2424
2425 chs = substream->runtime->channels;
84eb01be 2426
84eb01be
TI		 2427 dataDCC2 = 0x2;
2428
84eb01be 2429 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
7c935976 2430 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2431 snd_hda_codec_write(codec,
2432 nvhdmi_master_con_nid_7x,
2433 0,
2434 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2435 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2436
2437 /* set the stream id */
2438 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2439 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2440
2441 /* set the stream format */
2442 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2443 AC_VERB_SET_STREAM_FORMAT, format);
2444
2445 /* turn on again (if needed) */
2446 /* enable and set the channel status audio/data flag */
7c935976 2447 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2448 snd_hda_codec_write(codec,
2449 nvhdmi_master_con_nid_7x,
2450 0,
2451 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2452 spdif->ctls & 0xff);
84eb01be
TI		 2453 snd_hda_codec_write(codec,
2454 nvhdmi_master_con_nid_7x,
2455 0,
2456 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2457 }
2458
2459 for (i = 0; i < 4; i++) {
2460 if (chs == 2)
2461 channel_id = 0;
2462 else
2463 channel_id = i * 2;
2464
2465 /* turn off SPDIF once;
2466 *otherwise the IEC958 bits won't be updated
2467 */
2468 if (codec->spdif_status_reset &&
7c935976 2469 (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2470 snd_hda_codec_write(codec,
2471 nvhdmi_con_nids_7x[i],
2472 0,
2473 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2474 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2475 /* set the stream id */
2476 snd_hda_codec_write(codec,
2477 nvhdmi_con_nids_7x[i],
2478 0,
2479 AC_VERB_SET_CHANNEL_STREAMID,
2480 (stream_tag << 4) | channel_id);
2481 /* set the stream format */
2482 snd_hda_codec_write(codec,
2483 nvhdmi_con_nids_7x[i],
2484 0,
2485 AC_VERB_SET_STREAM_FORMAT,
2486 format);
2487 /* turn on again (if needed) */
2488 /* enable and set the channel status audio/data flag */
2489 if (codec->spdif_status_reset &&
7c935976 2490 (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2491 snd_hda_codec_write(codec,
2492 nvhdmi_con_nids_7x[i],
2493 0,
2494 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2495 spdif->ctls & 0xff);
84eb01be
TI		 2496 snd_hda_codec_write(codec,
2497 nvhdmi_con_nids_7x[i],
2498 0,
2499 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2500 }
2501 }
2502
1f348522 2503 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
84eb01be
TI		 2504
2505 mutex_unlock(&codec->spdif_mutex);
2506 return 0;
2507}
2508
fb79e1e0 2509static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
84eb01be
TI		 2510 .substreams = 1,
2511 .channels_min = 2,
2512 .channels_max = 8,
2513 .nid = nvhdmi_master_con_nid_7x,
2514 .rates = SUPPORTED_RATES,
2515 .maxbps = SUPPORTED_MAXBPS,
2516 .formats = SUPPORTED_FORMATS,
2517 .ops = {
2518 .open = simple_playback_pcm_open,
2519 .close = nvhdmi_8ch_7x_pcm_close,
2520 .prepare = nvhdmi_8ch_7x_pcm_prepare
2521 },
2522};
2523
84eb01be
TI		 2524static int patch_nvhdmi_2ch(struct hda_codec *codec)
2525{
2526 struct hdmi_spec *spec;
d0b1252d
TI		 2527 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2528 nvhdmi_master_pin_nid_7x);
2529 if (err < 0)
2530 return err;
84eb01be 2531
ceaa86ba 2532 codec->patch_ops.init = nvhdmi_7x_init_2ch;
d0b1252d
TI		 2533 /* override the PCM rates, etc, as the codec doesn't give full list */
2534 spec = codec->spec;
2535 spec->pcm_playback.rates = SUPPORTED_RATES;
2536 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2537 spec->pcm_playback.formats = SUPPORTED_FORMATS;
84eb01be
TI		 2538 return 0;
2539}
2540
53775b0d
TI		 2541static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2542{
2543 struct hdmi_spec *spec = codec->spec;
2544 int err = simple_playback_build_pcms(codec);
bce0d2a8
TI		 2545 if (!err) {
2546 struct hda_pcm *info = get_pcm_rec(spec, 0);
2547 info->own_chmap = true;
2548 }
53775b0d
TI		 2549 return err;
2550}
2551
2552static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2553{
2554 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2555 struct hda_pcm *info;
53775b0d
TI		 2556 struct snd_pcm_chmap *chmap;
2557 int err;
2558
2559 err = simple_playback_build_controls(codec);
2560 if (err < 0)
2561 return err;
2562
2563 /* add channel maps */
bce0d2a8
TI		 2564 info = get_pcm_rec(spec, 0);
2565 err = snd_pcm_add_chmap_ctls(info->pcm,
53775b0d
TI		 2566 SNDRV_PCM_STREAM_PLAYBACK,
2567 snd_pcm_alt_chmaps, 8, 0, &chmap);
2568 if (err < 0)
2569 return err;
2570 switch (codec->preset->id) {
2571 case 0x10de0002:
2572 case 0x10de0003:
2573 case 0x10de0005:
2574 case 0x10de0006:
2575 chmap->channel_mask = (1U << 2) | (1U << 8);
2576 break;
2577 case 0x10de0007:
2578 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
2579 }
2580 return 0;
2581}
2582
84eb01be
TI		 2583static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
2584{
2585 struct hdmi_spec *spec;
2586 int err = patch_nvhdmi_2ch(codec);
84eb01be
TI		 2587 if (err < 0)
2588 return err;
2589 spec = codec->spec;
2590 spec->multiout.max_channels = 8;
d0b1252d 2591 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
ceaa86ba 2592 codec->patch_ops.init = nvhdmi_7x_init_8ch;
53775b0d
TI		 2593 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
2594 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
1f348522
AP		 2595
2596 /* Initialize the audio infoframe channel mask and checksum to something
2597 * valid */
2598 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2599
84eb01be
TI		 2600 return 0;
2601}
2602
2603/*
2604 * ATI-specific implementations
2605 *
2606 * FIXME: we may omit the whole this and use the generic code once after
2607 * it's confirmed to work.
2608 */
2609
2610#define ATIHDMI_CVT_NID 0x02 /* audio converter */
2611#define ATIHDMI_PIN_NID 0x03 /* HDMI output pin */
2612
2613static int atihdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2614 struct hda_codec *codec,
2615 unsigned int stream_tag,
2616 unsigned int format,
2617 struct snd_pcm_substream *substream)
2618{
2619 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2620 struct hdmi_spec_per_cvt *per_cvt = get_cvt(spec, 0);
84eb01be
TI		 2621 int chans = substream->runtime->channels;
2622 int i, err;
2623
2624 err = simple_playback_pcm_prepare(hinfo, codec, stream_tag, format,
2625 substream);
2626 if (err < 0)
2627 return err;
bce0d2a8 2628 snd_hda_codec_write(codec, per_cvt->cvt_nid, 0,
384a48d7 2629 AC_VERB_SET_CVT_CHAN_COUNT, chans - 1);
84eb01be
TI		 2630 /* FIXME: XXX */
2631 for (i = 0; i < chans; i++) {
bce0d2a8 2632 snd_hda_codec_write(codec, per_cvt->cvt_nid, 0,
84eb01be
TI		 2633 AC_VERB_SET_HDMI_CHAN_SLOT,
2634 (i << 4) | i);
2635 }
2636 return 0;
2637}
2638
84eb01be
TI		 2639static int patch_atihdmi(struct hda_codec *codec)
2640{
2641 struct hdmi_spec *spec;
d0b1252d
TI		 2642 int err = patch_simple_hdmi(codec, ATIHDMI_CVT_NID, ATIHDMI_PIN_NID);
2643 if (err < 0)
2644 return err;
2645 spec = codec->spec;
2646 spec->pcm_playback.ops.prepare = atihdmi_playback_pcm_prepare;
84eb01be
TI		 2647 return 0;
2648}
2649
3de5ff88
AL		 2650/* VIA HDMI Implementation */
2651#define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
2652#define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
2653
3de5ff88
AL		 2654static int patch_via_hdmi(struct hda_codec *codec)
2655{
250e41ac 2656 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3de5ff88 2657}
84eb01be
TI		 2658
2659/*
2660 * patch entries
2661 */
fb79e1e0 2662static const struct hda_codec_preset snd_hda_preset_hdmi[] = {
84eb01be
TI		 2663{ .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi },
2664{ .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi },
2665{ .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi },
36e9c135 2666{ .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 2667{ .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi },
2668{ .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi },
2669{ .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi },
2670{ .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2671{ .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2672{ .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2673{ .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2674{ .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x },
5d44f927
SW		 2675{ .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_generic_hdmi },
2676{ .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_generic_hdmi },
2677{ .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_generic_hdmi },
2678{ .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_generic_hdmi },
2679{ .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_generic_hdmi },
2680{ .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_generic_hdmi },
2681{ .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_generic_hdmi },
2682{ .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_generic_hdmi },
2683{ .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_generic_hdmi },
2684{ .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_generic_hdmi },
2685{ .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_generic_hdmi },
c8900a0f 2686/* 17 is known to be absent */
5d44f927
SW		 2687{ .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_generic_hdmi },
2688{ .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_generic_hdmi },
2689{ .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_generic_hdmi },
2690{ .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_generic_hdmi },
2691{ .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_generic_hdmi },
2692{ .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_generic_hdmi },
2693{ .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_generic_hdmi },
2694{ .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_generic_hdmi },
2695{ .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_generic_hdmi },
2696{ .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_generic_hdmi },
7ae48b56 2697{ .id = 0x10de0051, .name = "GPU 51 HDMI/DP", .patch = patch_generic_hdmi },
d52392b1 2698{ .id = 0x10de0060, .name = "GPU 60 HDMI/DP", .patch = patch_generic_hdmi },
84eb01be
TI		 2699{ .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
2700{ .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
3de5ff88
AL		 2701{ .id = 0x11069f80, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
2702{ .id = 0x11069f81, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
2703{ .id = 0x11069f84, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
2704{ .id = 0x11069f85, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
84eb01be
TI		 2705{ .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
2706{ .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi },
2707{ .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi },
2708{ .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi },
2709{ .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
2710{ .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
591e610d 2711{ .id = 0x80862806, .name = "PantherPoint HDMI", .patch = patch_generic_hdmi },
1c76684d 2712{ .id = 0x80862807, .name = "Haswell HDMI", .patch = patch_generic_hdmi },
6edc59e6 2713{ .id = 0x80862880, .name = "CedarTrail HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 2714{ .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
2715{} /* terminator */
2716};
2717
2718MODULE_ALIAS("snd-hda-codec-id:1002793c");
2719MODULE_ALIAS("snd-hda-codec-id:10027919");
2720MODULE_ALIAS("snd-hda-codec-id:1002791a");
2721MODULE_ALIAS("snd-hda-codec-id:1002aa01");
2722MODULE_ALIAS("snd-hda-codec-id:10951390");
2723MODULE_ALIAS("snd-hda-codec-id:10951392");
2724MODULE_ALIAS("snd-hda-codec-id:10de0002");
2725MODULE_ALIAS("snd-hda-codec-id:10de0003");
2726MODULE_ALIAS("snd-hda-codec-id:10de0005");
2727MODULE_ALIAS("snd-hda-codec-id:10de0006");
2728MODULE_ALIAS("snd-hda-codec-id:10de0007");
2729MODULE_ALIAS("snd-hda-codec-id:10de000a");
2730MODULE_ALIAS("snd-hda-codec-id:10de000b");
2731MODULE_ALIAS("snd-hda-codec-id:10de000c");
2732MODULE_ALIAS("snd-hda-codec-id:10de000d");
2733MODULE_ALIAS("snd-hda-codec-id:10de0010");
2734MODULE_ALIAS("snd-hda-codec-id:10de0011");
2735MODULE_ALIAS("snd-hda-codec-id:10de0012");
2736MODULE_ALIAS("snd-hda-codec-id:10de0013");
2737MODULE_ALIAS("snd-hda-codec-id:10de0014");
c8900a0f
RS		 2738MODULE_ALIAS("snd-hda-codec-id:10de0015");
2739MODULE_ALIAS("snd-hda-codec-id:10de0016");
84eb01be
TI		 2740MODULE_ALIAS("snd-hda-codec-id:10de0018");
2741MODULE_ALIAS("snd-hda-codec-id:10de0019");
2742MODULE_ALIAS("snd-hda-codec-id:10de001a");
2743MODULE_ALIAS("snd-hda-codec-id:10de001b");
2744MODULE_ALIAS("snd-hda-codec-id:10de001c");
2745MODULE_ALIAS("snd-hda-codec-id:10de0040");
2746MODULE_ALIAS("snd-hda-codec-id:10de0041");
2747MODULE_ALIAS("snd-hda-codec-id:10de0042");
2748MODULE_ALIAS("snd-hda-codec-id:10de0043");
2749MODULE_ALIAS("snd-hda-codec-id:10de0044");
7ae48b56 2750MODULE_ALIAS("snd-hda-codec-id:10de0051");
d52392b1 2751MODULE_ALIAS("snd-hda-codec-id:10de0060");
84eb01be
TI		 2752MODULE_ALIAS("snd-hda-codec-id:10de0067");
2753MODULE_ALIAS("snd-hda-codec-id:10de8001");
3de5ff88
AL		 2754MODULE_ALIAS("snd-hda-codec-id:11069f80");
2755MODULE_ALIAS("snd-hda-codec-id:11069f81");
2756MODULE_ALIAS("snd-hda-codec-id:11069f84");
2757MODULE_ALIAS("snd-hda-codec-id:11069f85");
84eb01be
TI		 2758MODULE_ALIAS("snd-hda-codec-id:17e80047");
2759MODULE_ALIAS("snd-hda-codec-id:80860054");
2760MODULE_ALIAS("snd-hda-codec-id:80862801");
2761MODULE_ALIAS("snd-hda-codec-id:80862802");
2762MODULE_ALIAS("snd-hda-codec-id:80862803");
2763MODULE_ALIAS("snd-hda-codec-id:80862804");
2764MODULE_ALIAS("snd-hda-codec-id:80862805");
591e610d 2765MODULE_ALIAS("snd-hda-codec-id:80862806");
1c76684d 2766MODULE_ALIAS("snd-hda-codec-id:80862807");
6edc59e6 2767MODULE_ALIAS("snd-hda-codec-id:80862880");
84eb01be
TI		 2768MODULE_ALIAS("snd-hda-codec-id:808629fb");
2769
2770MODULE_LICENSE("GPL");
2771MODULE_DESCRIPTION("HDMI HD-audio codec");
2772MODULE_ALIAS("snd-hda-codec-intelhdmi");
2773MODULE_ALIAS("snd-hda-codec-nvhdmi");
2774MODULE_ALIAS("snd-hda-codec-atihdmi");
2775
2776static struct hda_codec_preset_list intel_list = {
2777 .preset = snd_hda_preset_hdmi,
2778 .owner = THIS_MODULE,
2779};
2780
2781static int __init patch_hdmi_init(void)
2782{
2783 return snd_hda_add_codec_preset(&intel_list);
2784}
2785
2786static void __exit patch_hdmi_exit(void)
2787{
2788 snd_hda_delete_codec_preset(&intel_list);
2789}
2790
2791module_init(patch_hdmi_init)
2792module_exit(patch_hdmi_exit)
Linux 6.x block layer and io_uring tree(s)