Commit | Line | Data |
---|---|---|
1a59d1b8 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
079d88cc WF |
2 | /* |
3 | * | |
4 | * patch_hdmi.c - routines for HDMI/DisplayPort codecs | |
5 | * | |
6 | * Copyright(c) 2008-2010 Intel Corporation. All rights reserved. | |
84eb01be TI |
7 | * Copyright (c) 2006 ATI Technologies Inc. |
8 | * Copyright (c) 2008 NVIDIA Corp. All rights reserved. | |
9 | * Copyright (c) 2008 Wei Ni <wni@nvidia.com> | |
5a613584 | 10 | * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi> |
079d88cc WF |
11 | * |
12 | * Authors: | |
13 | * Wu Fengguang <wfg@linux.intel.com> | |
14 | * | |
15 | * Maintained by: | |
16 | * Wu Fengguang <wfg@linux.intel.com> | |
079d88cc WF |
17 | */ |
18 | ||
84eb01be TI |
19 | #include <linux/init.h> |
20 | #include <linux/delay.h> | |
ade49db3 | 21 | #include <linux/pci.h> |
84eb01be | 22 | #include <linux/slab.h> |
65a77217 | 23 | #include <linux/module.h> |
aaa23f86 | 24 | #include <linux/pm_runtime.h> |
84eb01be | 25 | #include <sound/core.h> |
07acecc1 | 26 | #include <sound/jack.h> |
433968da | 27 | #include <sound/asoundef.h> |
d45e6889 | 28 | #include <sound/tlv.h> |
25adc137 DH |
29 | #include <sound/hdaudio.h> |
30 | #include <sound/hda_i915.h> | |
67b90cb8 | 31 | #include <sound/hda_chmap.h> |
be57bfff | 32 | #include <sound/hda_codec.h> |
84eb01be | 33 | #include "hda_local.h" |
1835a0f9 | 34 | #include "hda_jack.h" |
84eb01be | 35 | |
0ebaa24c TI |
36 | static bool static_hdmi_pcm; |
37 | module_param(static_hdmi_pcm, bool, 0644); | |
38 | MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info"); | |
39 | ||
384a48d7 SW |
40 | struct hdmi_spec_per_cvt { |
41 | hda_nid_t cvt_nid; | |
42 | int assigned; | |
43 | unsigned int channels_min; | |
44 | unsigned int channels_max; | |
45 | u32 rates; | |
46 | u64 formats; | |
47 | unsigned int maxbps; | |
48 | }; | |
079d88cc | 49 | |
4eea3091 TI |
50 | /* max. connections to a widget */ |
51 | #define HDA_MAX_CONNECTIONS 32 | |
52 | ||
384a48d7 SW |
53 | struct hdmi_spec_per_pin { |
54 | hda_nid_t pin_nid; | |
9152085d | 55 | int dev_id; |
a76056f2 LY |
56 | /* pin idx, different device entries on the same pin use the same idx */ |
57 | int pin_nid_idx; | |
384a48d7 SW |
58 | int num_mux_nids; |
59 | hda_nid_t mux_nids[HDA_MAX_CONNECTIONS]; | |
2df6742f | 60 | int mux_idx; |
1df5a06a | 61 | hda_nid_t cvt_nid; |
744626da WF |
62 | |
63 | struct hda_codec *codec; | |
384a48d7 | 64 | struct hdmi_eld sink_eld; |
a4e9a38b | 65 | struct mutex lock; |
744626da | 66 | struct delayed_work work; |
2bea241a | 67 | struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/ |
a76056f2 | 68 | int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */ |
c6e8453e | 69 | int repoll_count; |
b054087d TI |
70 | bool setup; /* the stream has been set up by prepare callback */ |
71 | int channels; /* current number of channels */ | |
1a6003b5 | 72 | bool non_pcm; |
d45e6889 TI |
73 | bool chmap_set; /* channel-map override by ALSA API? */ |
74 | unsigned char chmap[8]; /* ALSA API channel-map */ | |
cd6a6503 | 75 | #ifdef CONFIG_SND_PROC_FS |
a4e9a38b TI |
76 | struct snd_info_entry *proc_entry; |
77 | #endif | |
384a48d7 | 78 | }; |
079d88cc | 79 | |
307229d2 AH |
80 | /* operations used by generic code that can be overridden by patches */ |
81 | struct hdmi_ops { | |
82 | int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid, | |
83 | unsigned char *buf, int *eld_size); | |
84 | ||
307229d2 AH |
85 | void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid, |
86 | int ca, int active_channels, int conn_type); | |
87 | ||
88 | /* enable/disable HBR (HD passthrough) */ | |
89 | int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr); | |
90 | ||
91 | int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid, | |
92 | hda_nid_t pin_nid, u32 stream_tag, int format); | |
93 | ||
4846a67e TI |
94 | void (*pin_cvt_fixup)(struct hda_codec *codec, |
95 | struct hdmi_spec_per_pin *per_pin, | |
96 | hda_nid_t cvt_nid); | |
307229d2 AH |
97 | }; |
98 | ||
2bea241a LY |
99 | struct hdmi_pcm { |
100 | struct hda_pcm *pcm; | |
101 | struct snd_jack *jack; | |
fb087eaa | 102 | struct snd_kcontrol *eld_ctl; |
2bea241a LY |
103 | }; |
104 | ||
384a48d7 | 105 | struct hdmi_spec { |
ade49db3 | 106 | struct hda_codec *codec; |
384a48d7 | 107 | int num_cvts; |
bce0d2a8 TI |
108 | struct snd_array cvts; /* struct hdmi_spec_per_cvt */ |
109 | hda_nid_t cvt_nids[4]; /* only for haswell fix */ | |
079d88cc | 110 | |
9152085d LY |
111 | /* |
112 | * num_pins is the number of virtual pins | |
113 | * for example, there are 3 pins, and each pin | |
114 | * has 4 device entries, then the num_pins is 12 | |
115 | */ | |
384a48d7 | 116 | int num_pins; |
9152085d LY |
117 | /* |
118 | * num_nids is the number of real pins | |
119 | * In the above example, num_nids is 3 | |
120 | */ | |
121 | int num_nids; | |
122 | /* | |
123 | * dev_num is the number of device entries | |
124 | * on each pin. | |
125 | * In the above example, dev_num is 4 | |
126 | */ | |
127 | int dev_num; | |
bce0d2a8 | 128 | struct snd_array pins; /* struct hdmi_spec_per_pin */ |
2bea241a | 129 | struct hdmi_pcm pcm_rec[16]; |
42b29870 | 130 | struct mutex pcm_lock; |
302d5a80 | 131 | struct mutex bind_lock; /* for audio component binding */ |
a76056f2 LY |
132 | /* pcm_bitmap means which pcms have been assigned to pins*/ |
133 | unsigned long pcm_bitmap; | |
2bf3c85a | 134 | int pcm_used; /* counter of pcm_rec[] */ |
ac98379a LY |
135 | /* bitmap shows whether the pcm is opened in user space |
136 | * bit 0 means the first playback PCM (PCM3); | |
137 | * bit 1 means the second playback PCM, and so on. | |
138 | */ | |
139 | unsigned long pcm_in_use; | |
079d88cc | 140 | |
4bd038f9 | 141 | struct hdmi_eld temp_eld; |
307229d2 | 142 | struct hdmi_ops ops; |
75fae117 SW |
143 | |
144 | bool dyn_pin_out; | |
6590faab | 145 | bool dyn_pcm_assign; |
cb45722b | 146 | bool intel_hsw_fixup; /* apply Intel platform-specific fixups */ |
079d88cc | 147 | /* |
5a613584 | 148 | * Non-generic VIA/NVIDIA specific |
079d88cc WF |
149 | */ |
150 | struct hda_multi_out multiout; | |
d0b1252d | 151 | struct hda_pcm_stream pcm_playback; |
25adc137 | 152 | |
ade49db3 TI |
153 | bool use_jack_detect; /* jack detection enabled */ |
154 | bool use_acomp_notifier; /* use eld_notify callback for hotplug */ | |
155 | bool acomp_registered; /* audio component registered in this driver */ | |
ae891abe | 156 | struct drm_audio_component_audio_ops drm_audio_ops; |
ade49db3 | 157 | int (*port2pin)(struct hda_codec *, int); /* reverse port/pin mapping */ |
67b90cb8 SP |
158 | |
159 | struct hdac_chmap chmap; | |
a87a4d23 | 160 | hda_nid_t vendor_nid; |
b0d8bc50 JK |
161 | const int *port_map; |
162 | int port_num; | |
079d88cc WF |
163 | }; |
164 | ||
a57942bf | 165 | #ifdef CONFIG_SND_HDA_COMPONENT |
691be973 TI |
166 | static inline bool codec_has_acomp(struct hda_codec *codec) |
167 | { | |
168 | struct hdmi_spec *spec = codec->spec; | |
169 | return spec->use_acomp_notifier; | |
170 | } | |
f4e3040b TI |
171 | #else |
172 | #define codec_has_acomp(codec) false | |
173 | #endif | |
079d88cc WF |
174 | |
175 | struct hdmi_audio_infoframe { | |
176 | u8 type; /* 0x84 */ | |
177 | u8 ver; /* 0x01 */ | |
178 | u8 len; /* 0x0a */ | |
179 | ||
53d7d69d WF |
180 | u8 checksum; |
181 | ||
079d88cc WF |
182 | u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */ |
183 | u8 SS01_SF24; | |
184 | u8 CXT04; | |
185 | u8 CA; | |
186 | u8 LFEPBL01_LSV36_DM_INH7; | |
53d7d69d WF |
187 | }; |
188 | ||
189 | struct dp_audio_infoframe { | |
190 | u8 type; /* 0x84 */ | |
191 | u8 len; /* 0x1b */ | |
192 | u8 ver; /* 0x11 << 2 */ | |
193 | ||
194 | u8 CC02_CT47; /* match with HDMI infoframe from this on */ | |
195 | u8 SS01_SF24; | |
196 | u8 CXT04; | |
197 | u8 CA; | |
198 | u8 LFEPBL01_LSV36_DM_INH7; | |
079d88cc WF |
199 | }; |
200 | ||
2b203dbb TI |
201 | union audio_infoframe { |
202 | struct hdmi_audio_infoframe hdmi; | |
203 | struct dp_audio_infoframe dp; | |
204 | u8 bytes[0]; | |
205 | }; | |
206 | ||
079d88cc WF |
207 | /* |
208 | * HDMI routines | |
209 | */ | |
210 | ||
bce0d2a8 TI |
211 | #define get_pin(spec, idx) \ |
212 | ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx)) | |
213 | #define get_cvt(spec, idx) \ | |
214 | ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx)) | |
2bea241a LY |
215 | /* obtain hdmi_pcm object assigned to idx */ |
216 | #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx]) | |
217 | /* obtain hda_pcm object assigned to idx */ | |
218 | #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm) | |
bce0d2a8 | 219 | |
9152085d LY |
220 | static int pin_id_to_pin_index(struct hda_codec *codec, |
221 | hda_nid_t pin_nid, int dev_id) | |
079d88cc | 222 | { |
4e76a883 | 223 | struct hdmi_spec *spec = codec->spec; |
384a48d7 | 224 | int pin_idx; |
9152085d | 225 | struct hdmi_spec_per_pin *per_pin; |
079d88cc | 226 | |
9152085d LY |
227 | /* |
228 | * (dev_id == -1) means it is NON-MST pin | |
229 | * return the first virtual pin on this port | |
230 | */ | |
231 | if (dev_id == -1) | |
232 | dev_id = 0; | |
233 | ||
234 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { | |
235 | per_pin = get_pin(spec, pin_idx); | |
236 | if ((per_pin->pin_nid == pin_nid) && | |
237 | (per_pin->dev_id == dev_id)) | |
384a48d7 | 238 | return pin_idx; |
9152085d | 239 | } |
079d88cc | 240 | |
4e76a883 | 241 | codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid); |
384a48d7 SW |
242 | return -EINVAL; |
243 | } | |
244 | ||
2bf3c85a LY |
245 | static int hinfo_to_pcm_index(struct hda_codec *codec, |
246 | struct hda_pcm_stream *hinfo) | |
247 | { | |
248 | struct hdmi_spec *spec = codec->spec; | |
249 | int pcm_idx; | |
250 | ||
251 | for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) | |
252 | if (get_pcm_rec(spec, pcm_idx)->stream == hinfo) | |
253 | return pcm_idx; | |
254 | ||
255 | codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo); | |
256 | return -EINVAL; | |
257 | } | |
258 | ||
4e76a883 | 259 | static int hinfo_to_pin_index(struct hda_codec *codec, |
384a48d7 SW |
260 | struct hda_pcm_stream *hinfo) |
261 | { | |
4e76a883 | 262 | struct hdmi_spec *spec = codec->spec; |
6590faab | 263 | struct hdmi_spec_per_pin *per_pin; |
384a48d7 SW |
264 | int pin_idx; |
265 | ||
6590faab LY |
266 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { |
267 | per_pin = get_pin(spec, pin_idx); | |
2bea241a LY |
268 | if (per_pin->pcm && |
269 | per_pin->pcm->pcm->stream == hinfo) | |
384a48d7 | 270 | return pin_idx; |
6590faab | 271 | } |
384a48d7 | 272 | |
6590faab | 273 | codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo); |
384a48d7 SW |
274 | return -EINVAL; |
275 | } | |
276 | ||
022f344b LY |
277 | static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec, |
278 | int pcm_idx) | |
279 | { | |
280 | int i; | |
281 | struct hdmi_spec_per_pin *per_pin; | |
282 | ||
283 | for (i = 0; i < spec->num_pins; i++) { | |
284 | per_pin = get_pin(spec, i); | |
285 | if (per_pin->pcm_idx == pcm_idx) | |
286 | return per_pin; | |
287 | } | |
288 | return NULL; | |
289 | } | |
290 | ||
4e76a883 | 291 | static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid) |
384a48d7 | 292 | { |
4e76a883 | 293 | struct hdmi_spec *spec = codec->spec; |
384a48d7 SW |
294 | int cvt_idx; |
295 | ||
296 | for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) | |
bce0d2a8 | 297 | if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid) |
384a48d7 SW |
298 | return cvt_idx; |
299 | ||
4e76a883 | 300 | codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid); |
079d88cc WF |
301 | return -EINVAL; |
302 | } | |
303 | ||
14bc52b8 PLB |
304 | static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol, |
305 | struct snd_ctl_elem_info *uinfo) | |
306 | { | |
307 | struct hda_codec *codec = snd_kcontrol_chip(kcontrol); | |
68e03de9 | 308 | struct hdmi_spec *spec = codec->spec; |
a4e9a38b | 309 | struct hdmi_spec_per_pin *per_pin; |
68e03de9 | 310 | struct hdmi_eld *eld; |
fb087eaa | 311 | int pcm_idx; |
14bc52b8 | 312 | |
14bc52b8 PLB |
313 | uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; |
314 | ||
fb087eaa LY |
315 | pcm_idx = kcontrol->private_value; |
316 | mutex_lock(&spec->pcm_lock); | |
317 | per_pin = pcm_idx_to_pin(spec, pcm_idx); | |
318 | if (!per_pin) { | |
319 | /* no pin is bound to the pcm */ | |
320 | uinfo->count = 0; | |
f69548ff | 321 | goto unlock; |
fb087eaa | 322 | } |
a4e9a38b | 323 | eld = &per_pin->sink_eld; |
68e03de9 | 324 | uinfo->count = eld->eld_valid ? eld->eld_size : 0; |
14bc52b8 | 325 | |
f69548ff TI |
326 | unlock: |
327 | mutex_unlock(&spec->pcm_lock); | |
14bc52b8 PLB |
328 | return 0; |
329 | } | |
330 | ||
331 | static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol, | |
332 | struct snd_ctl_elem_value *ucontrol) | |
333 | { | |
334 | struct hda_codec *codec = snd_kcontrol_chip(kcontrol); | |
68e03de9 | 335 | struct hdmi_spec *spec = codec->spec; |
a4e9a38b | 336 | struct hdmi_spec_per_pin *per_pin; |
68e03de9 | 337 | struct hdmi_eld *eld; |
fb087eaa | 338 | int pcm_idx; |
f69548ff | 339 | int err = 0; |
14bc52b8 | 340 | |
fb087eaa LY |
341 | pcm_idx = kcontrol->private_value; |
342 | mutex_lock(&spec->pcm_lock); | |
343 | per_pin = pcm_idx_to_pin(spec, pcm_idx); | |
344 | if (!per_pin) { | |
345 | /* no pin is bound to the pcm */ | |
346 | memset(ucontrol->value.bytes.data, 0, | |
347 | ARRAY_SIZE(ucontrol->value.bytes.data)); | |
f69548ff | 348 | goto unlock; |
fb087eaa | 349 | } |
68e03de9 | 350 | |
f69548ff | 351 | eld = &per_pin->sink_eld; |
360a8245 DH |
352 | if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) || |
353 | eld->eld_size > ELD_MAX_SIZE) { | |
68e03de9 | 354 | snd_BUG(); |
f69548ff TI |
355 | err = -EINVAL; |
356 | goto unlock; | |
68e03de9 DH |
357 | } |
358 | ||
359 | memset(ucontrol->value.bytes.data, 0, | |
360 | ARRAY_SIZE(ucontrol->value.bytes.data)); | |
361 | if (eld->eld_valid) | |
362 | memcpy(ucontrol->value.bytes.data, eld->eld_buffer, | |
363 | eld->eld_size); | |
14bc52b8 | 364 | |
f69548ff TI |
365 | unlock: |
366 | mutex_unlock(&spec->pcm_lock); | |
367 | return err; | |
14bc52b8 PLB |
368 | } |
369 | ||
f3b827e0 | 370 | static const struct snd_kcontrol_new eld_bytes_ctl = { |
14bc52b8 PLB |
371 | .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, |
372 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, | |
373 | .name = "ELD", | |
374 | .info = hdmi_eld_ctl_info, | |
375 | .get = hdmi_eld_ctl_get, | |
376 | }; | |
377 | ||
fb087eaa | 378 | static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx, |
14bc52b8 PLB |
379 | int device) |
380 | { | |
381 | struct snd_kcontrol *kctl; | |
382 | struct hdmi_spec *spec = codec->spec; | |
383 | int err; | |
384 | ||
385 | kctl = snd_ctl_new1(&eld_bytes_ctl, codec); | |
386 | if (!kctl) | |
387 | return -ENOMEM; | |
fb087eaa | 388 | kctl->private_value = pcm_idx; |
14bc52b8 PLB |
389 | kctl->id.device = device; |
390 | ||
fb087eaa LY |
391 | /* no pin nid is associated with the kctl now |
392 | * tbd: associate pin nid to eld ctl later | |
393 | */ | |
394 | err = snd_hda_ctl_add(codec, 0, kctl); | |
14bc52b8 PLB |
395 | if (err < 0) |
396 | return err; | |
397 | ||
fb087eaa | 398 | get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl; |
14bc52b8 PLB |
399 | return 0; |
400 | } | |
401 | ||
079d88cc WF |
402 | #ifdef BE_PARANOID |
403 | static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, | |
404 | int *packet_index, int *byte_index) | |
405 | { | |
406 | int val; | |
407 | ||
408 | val = snd_hda_codec_read(codec, pin_nid, 0, | |
409 | AC_VERB_GET_HDMI_DIP_INDEX, 0); | |
410 | ||
411 | *packet_index = val >> 5; | |
412 | *byte_index = val & 0x1f; | |
413 | } | |
414 | #endif | |
415 | ||
416 | static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, | |
417 | int packet_index, int byte_index) | |
418 | { | |
419 | int val; | |
420 | ||
421 | val = (packet_index << 5) | (byte_index & 0x1f); | |
422 | ||
423 | snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val); | |
424 | } | |
425 | ||
426 | static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid, | |
427 | unsigned char val) | |
428 | { | |
429 | snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val); | |
430 | } | |
431 | ||
384a48d7 | 432 | static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid) |
079d88cc | 433 | { |
75fae117 SW |
434 | struct hdmi_spec *spec = codec->spec; |
435 | int pin_out; | |
436 | ||
079d88cc WF |
437 | /* Unmute */ |
438 | if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) | |
439 | snd_hda_codec_write(codec, pin_nid, 0, | |
440 | AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE); | |
75fae117 SW |
441 | |
442 | if (spec->dyn_pin_out) | |
443 | /* Disable pin out until stream is active */ | |
444 | pin_out = 0; | |
445 | else | |
446 | /* Enable pin out: some machines with GM965 gets broken output | |
447 | * when the pin is disabled or changed while using with HDMI | |
448 | */ | |
449 | pin_out = PIN_OUT; | |
450 | ||
079d88cc | 451 | snd_hda_codec_write(codec, pin_nid, 0, |
75fae117 | 452 | AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out); |
079d88cc WF |
453 | } |
454 | ||
a4e9a38b TI |
455 | /* |
456 | * ELD proc files | |
457 | */ | |
458 | ||
cd6a6503 | 459 | #ifdef CONFIG_SND_PROC_FS |
a4e9a38b TI |
460 | static void print_eld_info(struct snd_info_entry *entry, |
461 | struct snd_info_buffer *buffer) | |
462 | { | |
463 | struct hdmi_spec_per_pin *per_pin = entry->private_data; | |
464 | ||
465 | mutex_lock(&per_pin->lock); | |
466 | snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer); | |
467 | mutex_unlock(&per_pin->lock); | |
468 | } | |
469 | ||
470 | static void write_eld_info(struct snd_info_entry *entry, | |
471 | struct snd_info_buffer *buffer) | |
472 | { | |
473 | struct hdmi_spec_per_pin *per_pin = entry->private_data; | |
474 | ||
475 | mutex_lock(&per_pin->lock); | |
476 | snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer); | |
477 | mutex_unlock(&per_pin->lock); | |
478 | } | |
479 | ||
480 | static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index) | |
481 | { | |
482 | char name[32]; | |
483 | struct hda_codec *codec = per_pin->codec; | |
484 | struct snd_info_entry *entry; | |
485 | int err; | |
486 | ||
487 | snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index); | |
6efdd851 | 488 | err = snd_card_proc_new(codec->card, name, &entry); |
a4e9a38b TI |
489 | if (err < 0) |
490 | return err; | |
491 | ||
492 | snd_info_set_text_ops(entry, per_pin, print_eld_info); | |
493 | entry->c.text.write = write_eld_info; | |
6a73cf46 | 494 | entry->mode |= 0200; |
a4e9a38b TI |
495 | per_pin->proc_entry = entry; |
496 | ||
497 | return 0; | |
498 | } | |
499 | ||
500 | static void eld_proc_free(struct hdmi_spec_per_pin *per_pin) | |
501 | { | |
1947a114 | 502 | if (!per_pin->codec->bus->shutdown) { |
c560a679 | 503 | snd_info_free_entry(per_pin->proc_entry); |
a4e9a38b TI |
504 | per_pin->proc_entry = NULL; |
505 | } | |
506 | } | |
507 | #else | |
b55447a7 TI |
508 | static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin, |
509 | int index) | |
a4e9a38b TI |
510 | { |
511 | return 0; | |
512 | } | |
b55447a7 | 513 | static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin) |
a4e9a38b TI |
514 | { |
515 | } | |
516 | #endif | |
079d88cc | 517 | |
079d88cc WF |
518 | /* |
519 | * Audio InfoFrame routines | |
520 | */ | |
521 | ||
522 | /* | |
523 | * Enable Audio InfoFrame Transmission | |
524 | */ | |
525 | static void hdmi_start_infoframe_trans(struct hda_codec *codec, | |
526 | hda_nid_t pin_nid) | |
527 | { | |
528 | hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); | |
529 | snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, | |
530 | AC_DIPXMIT_BEST); | |
531 | } | |
532 | ||
533 | /* | |
534 | * Disable Audio InfoFrame Transmission | |
535 | */ | |
536 | static void hdmi_stop_infoframe_trans(struct hda_codec *codec, | |
537 | hda_nid_t pin_nid) | |
538 | { | |
539 | hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); | |
540 | snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, | |
541 | AC_DIPXMIT_DISABLE); | |
542 | } | |
543 | ||
544 | static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid) | |
545 | { | |
546 | #ifdef CONFIG_SND_DEBUG_VERBOSE | |
547 | int i; | |
548 | int size; | |
549 | ||
550 | size = snd_hdmi_get_eld_size(codec, pin_nid); | |
4e76a883 | 551 | codec_dbg(codec, "HDMI: ELD buf size is %d\n", size); |
079d88cc WF |
552 | |
553 | for (i = 0; i < 8; i++) { | |
554 | size = snd_hda_codec_read(codec, pin_nid, 0, | |
555 | AC_VERB_GET_HDMI_DIP_SIZE, i); | |
4e76a883 | 556 | codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size); |
079d88cc WF |
557 | } |
558 | #endif | |
559 | } | |
560 | ||
561 | static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid) | |
562 | { | |
563 | #ifdef BE_PARANOID | |
564 | int i, j; | |
565 | int size; | |
566 | int pi, bi; | |
567 | for (i = 0; i < 8; i++) { | |
568 | size = snd_hda_codec_read(codec, pin_nid, 0, | |
569 | AC_VERB_GET_HDMI_DIP_SIZE, i); | |
570 | if (size == 0) | |
571 | continue; | |
572 | ||
573 | hdmi_set_dip_index(codec, pin_nid, i, 0x0); | |
574 | for (j = 1; j < 1000; j++) { | |
575 | hdmi_write_dip_byte(codec, pin_nid, 0x0); | |
576 | hdmi_get_dip_index(codec, pin_nid, &pi, &bi); | |
577 | if (pi != i) | |
4e76a883 | 578 | codec_dbg(codec, "dip index %d: %d != %d\n", |
079d88cc WF |
579 | bi, pi, i); |
580 | if (bi == 0) /* byte index wrapped around */ | |
581 | break; | |
582 | } | |
4e76a883 | 583 | codec_dbg(codec, |
079d88cc WF |
584 | "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n", |
585 | i, size, j); | |
586 | } | |
587 | #endif | |
588 | } | |
589 | ||
53d7d69d | 590 | static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai) |
079d88cc | 591 | { |
53d7d69d | 592 | u8 *bytes = (u8 *)hdmi_ai; |
079d88cc WF |
593 | u8 sum = 0; |
594 | int i; | |
595 | ||
53d7d69d | 596 | hdmi_ai->checksum = 0; |
079d88cc | 597 | |
53d7d69d | 598 | for (i = 0; i < sizeof(*hdmi_ai); i++) |
079d88cc WF |
599 | sum += bytes[i]; |
600 | ||
53d7d69d | 601 | hdmi_ai->checksum = -sum; |
079d88cc WF |
602 | } |
603 | ||
604 | static void hdmi_fill_audio_infoframe(struct hda_codec *codec, | |
605 | hda_nid_t pin_nid, | |
53d7d69d | 606 | u8 *dip, int size) |
079d88cc | 607 | { |
079d88cc WF |
608 | int i; |
609 | ||
610 | hdmi_debug_dip_size(codec, pin_nid); | |
611 | hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */ | |
612 | ||
079d88cc | 613 | hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); |
53d7d69d WF |
614 | for (i = 0; i < size; i++) |
615 | hdmi_write_dip_byte(codec, pin_nid, dip[i]); | |
079d88cc WF |
616 | } |
617 | ||
618 | static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid, | |
53d7d69d | 619 | u8 *dip, int size) |
079d88cc | 620 | { |
079d88cc WF |
621 | u8 val; |
622 | int i; | |
623 | ||
624 | if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0) | |
625 | != AC_DIPXMIT_BEST) | |
626 | return false; | |
627 | ||
628 | hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); | |
53d7d69d | 629 | for (i = 0; i < size; i++) { |
079d88cc WF |
630 | val = snd_hda_codec_read(codec, pin_nid, 0, |
631 | AC_VERB_GET_HDMI_DIP_DATA, 0); | |
53d7d69d | 632 | if (val != dip[i]) |
079d88cc WF |
633 | return false; |
634 | } | |
635 | ||
636 | return true; | |
637 | } | |
638 | ||
307229d2 AH |
639 | static void hdmi_pin_setup_infoframe(struct hda_codec *codec, |
640 | hda_nid_t pin_nid, | |
641 | int ca, int active_channels, | |
642 | int conn_type) | |
643 | { | |
644 | union audio_infoframe ai; | |
645 | ||
caaf5ef9 | 646 | memset(&ai, 0, sizeof(ai)); |
307229d2 AH |
647 | if (conn_type == 0) { /* HDMI */ |
648 | struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi; | |
649 | ||
650 | hdmi_ai->type = 0x84; | |
651 | hdmi_ai->ver = 0x01; | |
652 | hdmi_ai->len = 0x0a; | |
653 | hdmi_ai->CC02_CT47 = active_channels - 1; | |
654 | hdmi_ai->CA = ca; | |
655 | hdmi_checksum_audio_infoframe(hdmi_ai); | |
656 | } else if (conn_type == 1) { /* DisplayPort */ | |
657 | struct dp_audio_infoframe *dp_ai = &ai.dp; | |
658 | ||
659 | dp_ai->type = 0x84; | |
660 | dp_ai->len = 0x1b; | |
661 | dp_ai->ver = 0x11 << 2; | |
662 | dp_ai->CC02_CT47 = active_channels - 1; | |
663 | dp_ai->CA = ca; | |
664 | } else { | |
4e76a883 | 665 | codec_dbg(codec, "HDMI: unknown connection type at pin %d\n", |
307229d2 AH |
666 | pin_nid); |
667 | return; | |
668 | } | |
669 | ||
670 | /* | |
671 | * sizeof(ai) is used instead of sizeof(*hdmi_ai) or | |
672 | * sizeof(*dp_ai) to avoid partial match/update problems when | |
673 | * the user switches between HDMI/DP monitors. | |
674 | */ | |
675 | if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes, | |
676 | sizeof(ai))) { | |
4e76a883 TI |
677 | codec_dbg(codec, |
678 | "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n", | |
307229d2 AH |
679 | pin_nid, |
680 | active_channels, ca); | |
681 | hdmi_stop_infoframe_trans(codec, pin_nid); | |
682 | hdmi_fill_audio_infoframe(codec, pin_nid, | |
683 | ai.bytes, sizeof(ai)); | |
684 | hdmi_start_infoframe_trans(codec, pin_nid); | |
685 | } | |
686 | } | |
687 | ||
b054087d TI |
688 | static void hdmi_setup_audio_infoframe(struct hda_codec *codec, |
689 | struct hdmi_spec_per_pin *per_pin, | |
690 | bool non_pcm) | |
079d88cc | 691 | { |
307229d2 | 692 | struct hdmi_spec *spec = codec->spec; |
739ffee9 | 693 | struct hdac_chmap *chmap = &spec->chmap; |
384a48d7 | 694 | hda_nid_t pin_nid = per_pin->pin_nid; |
b054087d | 695 | int channels = per_pin->channels; |
1df5a06a | 696 | int active_channels; |
384a48d7 | 697 | struct hdmi_eld *eld; |
828cb4ed | 698 | int ca; |
079d88cc | 699 | |
b054087d TI |
700 | if (!channels) |
701 | return; | |
702 | ||
44bb6d0c TI |
703 | /* some HW (e.g. HSW+) needs reprogramming the amp at each time */ |
704 | if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) | |
58f7d28d ML |
705 | snd_hda_codec_write(codec, pin_nid, 0, |
706 | AC_VERB_SET_AMP_GAIN_MUTE, | |
707 | AMP_OUT_UNMUTE); | |
708 | ||
bce0d2a8 | 709 | eld = &per_pin->sink_eld; |
079d88cc | 710 | |
bb63f726 | 711 | ca = snd_hdac_channel_allocation(&codec->core, |
828cb4ed SP |
712 | eld->info.spk_alloc, channels, |
713 | per_pin->chmap_set, non_pcm, per_pin->chmap); | |
384a48d7 | 714 | |
bb63f726 | 715 | active_channels = snd_hdac_get_active_channels(ca); |
1df5a06a | 716 | |
739ffee9 SP |
717 | chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid, |
718 | active_channels); | |
1df5a06a | 719 | |
39edac70 AH |
720 | /* |
721 | * always configure channel mapping, it may have been changed by the | |
722 | * user in the meantime | |
723 | */ | |
bb63f726 | 724 | snd_hdac_setup_channel_mapping(&spec->chmap, |
828cb4ed SP |
725 | pin_nid, non_pcm, ca, channels, |
726 | per_pin->chmap, per_pin->chmap_set); | |
39edac70 | 727 | |
307229d2 AH |
728 | spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels, |
729 | eld->info.conn_type); | |
433968da | 730 | |
1a6003b5 | 731 | per_pin->non_pcm = non_pcm; |
079d88cc WF |
732 | } |
733 | ||
079d88cc WF |
734 | /* |
735 | * Unsolicited events | |
736 | */ | |
737 | ||
efe47108 | 738 | static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll); |
38faddb1 | 739 | |
9152085d LY |
740 | static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid, |
741 | int dev_id) | |
079d88cc WF |
742 | { |
743 | struct hdmi_spec *spec = codec->spec; | |
9152085d | 744 | int pin_idx = pin_id_to_pin_index(codec, nid, dev_id); |
1a4f69d5 | 745 | |
20ce9029 DH |
746 | if (pin_idx < 0) |
747 | return; | |
aaa23f86 | 748 | mutex_lock(&spec->pcm_lock); |
20ce9029 DH |
749 | if (hdmi_present_sense(get_pin(spec, pin_idx), 1)) |
750 | snd_hda_jack_report_sync(codec); | |
aaa23f86 | 751 | mutex_unlock(&spec->pcm_lock); |
20ce9029 DH |
752 | } |
753 | ||
1a4f69d5 TI |
754 | static void jack_callback(struct hda_codec *codec, |
755 | struct hda_jack_callback *jack) | |
756 | { | |
ade49db3 TI |
757 | /* stop polling when notification is enabled */ |
758 | if (codec_has_acomp(codec)) | |
759 | return; | |
760 | ||
9152085d LY |
761 | /* hda_jack don't support DP MST */ |
762 | check_presence_and_report(codec, jack->nid, 0); | |
1a4f69d5 TI |
763 | } |
764 | ||
20ce9029 DH |
765 | static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res) |
766 | { | |
3a93897e | 767 | int tag = res >> AC_UNSOL_RES_TAG_SHIFT; |
3a93897e | 768 | struct hda_jack_tbl *jack; |
2e59e5ab | 769 | int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT; |
3a93897e | 770 | |
9152085d LY |
771 | /* |
772 | * assume DP MST uses dyn_pcm_assign and acomp and | |
773 | * never comes here | |
774 | * if DP MST supports unsol event, below code need | |
775 | * consider dev_entry | |
776 | */ | |
3a93897e TI |
777 | jack = snd_hda_jack_tbl_get_from_tag(codec, tag); |
778 | if (!jack) | |
779 | return; | |
3a93897e | 780 | jack->jack_dirty = 1; |
079d88cc | 781 | |
4e76a883 | 782 | codec_dbg(codec, |
2e59e5ab | 783 | "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n", |
20ce9029 | 784 | codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA), |
fae3d88a | 785 | !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV)); |
079d88cc | 786 | |
9152085d LY |
787 | /* hda_jack don't support DP MST */ |
788 | check_presence_and_report(codec, jack->nid, 0); | |
079d88cc WF |
789 | } |
790 | ||
791 | static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res) | |
792 | { | |
793 | int tag = res >> AC_UNSOL_RES_TAG_SHIFT; | |
794 | int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; | |
795 | int cp_state = !!(res & AC_UNSOL_RES_CP_STATE); | |
796 | int cp_ready = !!(res & AC_UNSOL_RES_CP_READY); | |
797 | ||
4e76a883 | 798 | codec_info(codec, |
e9ea8e8f | 799 | "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n", |
384a48d7 | 800 | codec->addr, |
079d88cc WF |
801 | tag, |
802 | subtag, | |
803 | cp_state, | |
804 | cp_ready); | |
805 | ||
806 | /* TODO */ | |
807 | if (cp_state) | |
808 | ; | |
809 | if (cp_ready) | |
810 | ; | |
811 | } | |
812 | ||
813 | ||
814 | static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res) | |
815 | { | |
079d88cc WF |
816 | int tag = res >> AC_UNSOL_RES_TAG_SHIFT; |
817 | int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; | |
818 | ||
ade49db3 TI |
819 | if (codec_has_acomp(codec)) |
820 | return; | |
821 | ||
3a93897e | 822 | if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) { |
4e76a883 | 823 | codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag); |
079d88cc WF |
824 | return; |
825 | } | |
826 | ||
827 | if (subtag == 0) | |
828 | hdmi_intrinsic_event(codec, res); | |
829 | else | |
830 | hdmi_non_intrinsic_event(codec, res); | |
831 | } | |
832 | ||
58f7d28d | 833 | static void haswell_verify_D0(struct hda_codec *codec, |
53b434f0 | 834 | hda_nid_t cvt_nid, hda_nid_t nid) |
83f26ad2 | 835 | { |
58f7d28d | 836 | int pwr; |
83f26ad2 | 837 | |
53b434f0 WX |
838 | /* For Haswell, the converter 1/2 may keep in D3 state after bootup, |
839 | * thus pins could only choose converter 0 for use. Make sure the | |
840 | * converters are in correct power state */ | |
fd678cac | 841 | if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0)) |
53b434f0 WX |
842 | snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0); |
843 | ||
fd678cac | 844 | if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) { |
83f26ad2 DH |
845 | snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE, |
846 | AC_PWRST_D0); | |
847 | msleep(40); | |
848 | pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0); | |
849 | pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT; | |
4e76a883 | 850 | codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr); |
83f26ad2 | 851 | } |
83f26ad2 DH |
852 | } |
853 | ||
079d88cc WF |
854 | /* |
855 | * Callbacks | |
856 | */ | |
857 | ||
92f10b3f TI |
858 | /* HBR should be Non-PCM, 8 channels */ |
859 | #define is_hbr_format(format) \ | |
860 | ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7) | |
861 | ||
307229d2 AH |
862 | static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, |
863 | bool hbr) | |
079d88cc | 864 | { |
307229d2 | 865 | int pinctl, new_pinctl; |
83f26ad2 | 866 | |
384a48d7 SW |
867 | if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) { |
868 | pinctl = snd_hda_codec_read(codec, pin_nid, 0, | |
ea87d1c4 AH |
869 | AC_VERB_GET_PIN_WIDGET_CONTROL, 0); |
870 | ||
13122e6e AH |
871 | if (pinctl < 0) |
872 | return hbr ? -EINVAL : 0; | |
873 | ||
ea87d1c4 | 874 | new_pinctl = pinctl & ~AC_PINCTL_EPT; |
307229d2 | 875 | if (hbr) |
ea87d1c4 AH |
876 | new_pinctl |= AC_PINCTL_EPT_HBR; |
877 | else | |
878 | new_pinctl |= AC_PINCTL_EPT_NATIVE; | |
879 | ||
4e76a883 TI |
880 | codec_dbg(codec, |
881 | "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n", | |
384a48d7 | 882 | pin_nid, |
ea87d1c4 AH |
883 | pinctl == new_pinctl ? "" : "new-", |
884 | new_pinctl); | |
885 | ||
886 | if (pinctl != new_pinctl) | |
384a48d7 | 887 | snd_hda_codec_write(codec, pin_nid, 0, |
ea87d1c4 AH |
888 | AC_VERB_SET_PIN_WIDGET_CONTROL, |
889 | new_pinctl); | |
307229d2 AH |
890 | } else if (hbr) |
891 | return -EINVAL; | |
ea87d1c4 | 892 | |
307229d2 AH |
893 | return 0; |
894 | } | |
895 | ||
896 | static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, | |
897 | hda_nid_t pin_nid, u32 stream_tag, int format) | |
898 | { | |
899 | struct hdmi_spec *spec = codec->spec; | |
5a5d718f | 900 | unsigned int param; |
307229d2 AH |
901 | int err; |
902 | ||
307229d2 AH |
903 | err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format)); |
904 | ||
905 | if (err) { | |
4e76a883 | 906 | codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n"); |
307229d2 | 907 | return err; |
ea87d1c4 | 908 | } |
079d88cc | 909 | |
cb45722b | 910 | if (spec->intel_hsw_fixup) { |
5a5d718f SP |
911 | |
912 | /* | |
913 | * on recent platforms IEC Coding Type is required for HBR | |
914 | * support, read current Digital Converter settings and set | |
915 | * ICT bitfield if needed. | |
916 | */ | |
917 | param = snd_hda_codec_read(codec, cvt_nid, 0, | |
918 | AC_VERB_GET_DIGI_CONVERT_1, 0); | |
919 | ||
920 | param = (param >> 16) & ~(AC_DIG3_ICT); | |
921 | ||
922 | /* on recent platforms ICT mode is required for HBR support */ | |
923 | if (is_hbr_format(format)) | |
924 | param |= 0x1; | |
925 | ||
926 | snd_hda_codec_write(codec, cvt_nid, 0, | |
927 | AC_VERB_SET_DIGI_CONVERT_3, param); | |
928 | } | |
929 | ||
384a48d7 | 930 | snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format); |
ea87d1c4 | 931 | return 0; |
079d88cc WF |
932 | } |
933 | ||
42b29870 LY |
934 | /* Try to find an available converter |
935 | * If pin_idx is less then zero, just try to find an available converter. | |
936 | * Otherwise, try to find an available converter and get the cvt mux index | |
937 | * of the pin. | |
938 | */ | |
7ef166b8 | 939 | static int hdmi_choose_cvt(struct hda_codec *codec, |
4846a67e | 940 | int pin_idx, int *cvt_id) |
bbbe3390 TI |
941 | { |
942 | struct hdmi_spec *spec = codec->spec; | |
384a48d7 | 943 | struct hdmi_spec_per_pin *per_pin; |
384a48d7 | 944 | struct hdmi_spec_per_cvt *per_cvt = NULL; |
7ef166b8 | 945 | int cvt_idx, mux_idx = 0; |
bbbe3390 | 946 | |
42b29870 LY |
947 | /* pin_idx < 0 means no pin will be bound to the converter */ |
948 | if (pin_idx < 0) | |
949 | per_pin = NULL; | |
950 | else | |
951 | per_pin = get_pin(spec, pin_idx); | |
384a48d7 SW |
952 | |
953 | /* Dynamically assign converter to stream */ | |
954 | for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { | |
bce0d2a8 | 955 | per_cvt = get_cvt(spec, cvt_idx); |
bbbe3390 | 956 | |
384a48d7 SW |
957 | /* Must not already be assigned */ |
958 | if (per_cvt->assigned) | |
959 | continue; | |
42b29870 LY |
960 | if (per_pin == NULL) |
961 | break; | |
384a48d7 SW |
962 | /* Must be in pin's mux's list of converters */ |
963 | for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) | |
964 | if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid) | |
965 | break; | |
966 | /* Not in mux list */ | |
967 | if (mux_idx == per_pin->num_mux_nids) | |
968 | continue; | |
969 | break; | |
970 | } | |
7ef166b8 | 971 | |
384a48d7 SW |
972 | /* No free converters */ |
973 | if (cvt_idx == spec->num_cvts) | |
42b29870 | 974 | return -EBUSY; |
384a48d7 | 975 | |
42b29870 LY |
976 | if (per_pin != NULL) |
977 | per_pin->mux_idx = mux_idx; | |
2df6742f | 978 | |
7ef166b8 WX |
979 | if (cvt_id) |
980 | *cvt_id = cvt_idx; | |
7ef166b8 WX |
981 | |
982 | return 0; | |
983 | } | |
984 | ||
2df6742f ML |
985 | /* Assure the pin select the right convetor */ |
986 | static void intel_verify_pin_cvt_connect(struct hda_codec *codec, | |
987 | struct hdmi_spec_per_pin *per_pin) | |
988 | { | |
989 | hda_nid_t pin_nid = per_pin->pin_nid; | |
990 | int mux_idx, curr; | |
991 | ||
992 | mux_idx = per_pin->mux_idx; | |
993 | curr = snd_hda_codec_read(codec, pin_nid, 0, | |
994 | AC_VERB_GET_CONNECT_SEL, 0); | |
995 | if (curr != mux_idx) | |
996 | snd_hda_codec_write_cache(codec, pin_nid, 0, | |
997 | AC_VERB_SET_CONNECT_SEL, | |
998 | mux_idx); | |
999 | } | |
1000 | ||
42b29870 LY |
1001 | /* get the mux index for the converter of the pins |
1002 | * converter's mux index is the same for all pins on Intel platform | |
1003 | */ | |
1004 | static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec, | |
1005 | hda_nid_t cvt_nid) | |
1006 | { | |
1007 | int i; | |
1008 | ||
1009 | for (i = 0; i < spec->num_cvts; i++) | |
1010 | if (spec->cvt_nids[i] == cvt_nid) | |
1011 | return i; | |
1012 | return -EINVAL; | |
1013 | } | |
1014 | ||
300016b9 ML |
1015 | /* Intel HDMI workaround to fix audio routing issue: |
1016 | * For some Intel display codecs, pins share the same connection list. | |
1017 | * So a conveter can be selected by multiple pins and playback on any of these | |
1018 | * pins will generate sound on the external display, because audio flows from | |
1019 | * the same converter to the display pipeline. Also muting one pin may make | |
1020 | * other pins have no sound output. | |
1021 | * So this function assures that an assigned converter for a pin is not selected | |
1022 | * by any other pins. | |
1023 | */ | |
1024 | static void intel_not_share_assigned_cvt(struct hda_codec *codec, | |
9152085d LY |
1025 | hda_nid_t pin_nid, |
1026 | int dev_id, int mux_idx) | |
7ef166b8 WX |
1027 | { |
1028 | struct hdmi_spec *spec = codec->spec; | |
7639a06c | 1029 | hda_nid_t nid; |
f82d7d16 ML |
1030 | int cvt_idx, curr; |
1031 | struct hdmi_spec_per_cvt *per_cvt; | |
9152085d LY |
1032 | struct hdmi_spec_per_pin *per_pin; |
1033 | int pin_idx; | |
1034 | ||
1035 | /* configure the pins connections */ | |
1036 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { | |
1037 | int dev_id_saved; | |
1038 | int dev_num; | |
7ef166b8 | 1039 | |
9152085d LY |
1040 | per_pin = get_pin(spec, pin_idx); |
1041 | /* | |
1042 | * pin not connected to monitor | |
1043 | * no need to operate on it | |
1044 | */ | |
1045 | if (!per_pin->pcm) | |
1046 | continue; | |
f82d7d16 | 1047 | |
9152085d LY |
1048 | if ((per_pin->pin_nid == pin_nid) && |
1049 | (per_pin->dev_id == dev_id)) | |
f82d7d16 | 1050 | continue; |
7ef166b8 | 1051 | |
9152085d LY |
1052 | /* |
1053 | * if per_pin->dev_id >= dev_num, | |
1054 | * snd_hda_get_dev_select() will fail, | |
1055 | * and the following operation is unpredictable. | |
1056 | * So skip this situation. | |
1057 | */ | |
1058 | dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1; | |
1059 | if (per_pin->dev_id >= dev_num) | |
7ef166b8 WX |
1060 | continue; |
1061 | ||
9152085d LY |
1062 | nid = per_pin->pin_nid; |
1063 | ||
1064 | /* | |
1065 | * Calling this function should not impact | |
1066 | * on the device entry selection | |
1067 | * So let's save the dev id for each pin, | |
1068 | * and restore it when return | |
1069 | */ | |
1070 | dev_id_saved = snd_hda_get_dev_select(codec, nid); | |
1071 | snd_hda_set_dev_select(codec, nid, per_pin->dev_id); | |
f82d7d16 | 1072 | curr = snd_hda_codec_read(codec, nid, 0, |
7ef166b8 | 1073 | AC_VERB_GET_CONNECT_SEL, 0); |
9152085d LY |
1074 | if (curr != mux_idx) { |
1075 | snd_hda_set_dev_select(codec, nid, dev_id_saved); | |
f82d7d16 | 1076 | continue; |
9152085d LY |
1077 | } |
1078 | ||
7ef166b8 | 1079 | |
f82d7d16 ML |
1080 | /* choose an unassigned converter. The conveters in the |
1081 | * connection list are in the same order as in the codec. | |
1082 | */ | |
1083 | for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { | |
1084 | per_cvt = get_cvt(spec, cvt_idx); | |
1085 | if (!per_cvt->assigned) { | |
4e76a883 TI |
1086 | codec_dbg(codec, |
1087 | "choose cvt %d for pin nid %d\n", | |
f82d7d16 ML |
1088 | cvt_idx, nid); |
1089 | snd_hda_codec_write_cache(codec, nid, 0, | |
7ef166b8 | 1090 | AC_VERB_SET_CONNECT_SEL, |
f82d7d16 ML |
1091 | cvt_idx); |
1092 | break; | |
1093 | } | |
7ef166b8 | 1094 | } |
9152085d | 1095 | snd_hda_set_dev_select(codec, nid, dev_id_saved); |
7ef166b8 WX |
1096 | } |
1097 | } | |
1098 | ||
42b29870 LY |
1099 | /* A wrapper of intel_not_share_asigned_cvt() */ |
1100 | static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec, | |
9152085d | 1101 | hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid) |
42b29870 LY |
1102 | { |
1103 | int mux_idx; | |
1104 | struct hdmi_spec *spec = codec->spec; | |
1105 | ||
42b29870 LY |
1106 | /* On Intel platform, the mapping of converter nid to |
1107 | * mux index of the pins are always the same. | |
1108 | * The pin nid may be 0, this means all pins will not | |
1109 | * share the converter. | |
1110 | */ | |
1111 | mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid); | |
1112 | if (mux_idx >= 0) | |
9152085d | 1113 | intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx); |
42b29870 LY |
1114 | } |
1115 | ||
4846a67e TI |
1116 | /* skeleton caller of pin_cvt_fixup ops */ |
1117 | static void pin_cvt_fixup(struct hda_codec *codec, | |
1118 | struct hdmi_spec_per_pin *per_pin, | |
1119 | hda_nid_t cvt_nid) | |
1120 | { | |
1121 | struct hdmi_spec *spec = codec->spec; | |
1122 | ||
1123 | if (spec->ops.pin_cvt_fixup) | |
1124 | spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid); | |
1125 | } | |
1126 | ||
42b29870 LY |
1127 | /* called in hdmi_pcm_open when no pin is assigned to the PCM |
1128 | * in dyn_pcm_assign mode. | |
1129 | */ | |
1130 | static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo, | |
1131 | struct hda_codec *codec, | |
1132 | struct snd_pcm_substream *substream) | |
1133 | { | |
1134 | struct hdmi_spec *spec = codec->spec; | |
1135 | struct snd_pcm_runtime *runtime = substream->runtime; | |
ac98379a | 1136 | int cvt_idx, pcm_idx; |
42b29870 LY |
1137 | struct hdmi_spec_per_cvt *per_cvt = NULL; |
1138 | int err; | |
1139 | ||
ac98379a LY |
1140 | pcm_idx = hinfo_to_pcm_index(codec, hinfo); |
1141 | if (pcm_idx < 0) | |
1142 | return -EINVAL; | |
1143 | ||
4846a67e | 1144 | err = hdmi_choose_cvt(codec, -1, &cvt_idx); |
42b29870 LY |
1145 | if (err) |
1146 | return err; | |
1147 | ||
1148 | per_cvt = get_cvt(spec, cvt_idx); | |
1149 | per_cvt->assigned = 1; | |
1150 | hinfo->nid = per_cvt->cvt_nid; | |
1151 | ||
4846a67e | 1152 | pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid); |
42b29870 | 1153 | |
ac98379a | 1154 | set_bit(pcm_idx, &spec->pcm_in_use); |
42b29870 LY |
1155 | /* todo: setup spdif ctls assign */ |
1156 | ||
1157 | /* Initially set the converter's capabilities */ | |
1158 | hinfo->channels_min = per_cvt->channels_min; | |
1159 | hinfo->channels_max = per_cvt->channels_max; | |
1160 | hinfo->rates = per_cvt->rates; | |
1161 | hinfo->formats = per_cvt->formats; | |
1162 | hinfo->maxbps = per_cvt->maxbps; | |
1163 | ||
1164 | /* Store the updated parameters */ | |
1165 | runtime->hw.channels_min = hinfo->channels_min; | |
1166 | runtime->hw.channels_max = hinfo->channels_max; | |
1167 | runtime->hw.formats = hinfo->formats; | |
1168 | runtime->hw.rates = hinfo->rates; | |
1169 | ||
1170 | snd_pcm_hw_constraint_step(substream->runtime, 0, | |
1171 | SNDRV_PCM_HW_PARAM_CHANNELS, 2); | |
1172 | return 0; | |
1173 | } | |
1174 | ||
7ef166b8 WX |
1175 | /* |
1176 | * HDA PCM callbacks | |
1177 | */ | |
1178 | static int hdmi_pcm_open(struct hda_pcm_stream *hinfo, | |
1179 | struct hda_codec *codec, | |
1180 | struct snd_pcm_substream *substream) | |
1181 | { | |
1182 | struct hdmi_spec *spec = codec->spec; | |
1183 | struct snd_pcm_runtime *runtime = substream->runtime; | |
4846a67e | 1184 | int pin_idx, cvt_idx, pcm_idx; |
7ef166b8 WX |
1185 | struct hdmi_spec_per_pin *per_pin; |
1186 | struct hdmi_eld *eld; | |
1187 | struct hdmi_spec_per_cvt *per_cvt = NULL; | |
1188 | int err; | |
1189 | ||
1190 | /* Validate hinfo */ | |
2bf3c85a LY |
1191 | pcm_idx = hinfo_to_pcm_index(codec, hinfo); |
1192 | if (pcm_idx < 0) | |
7ef166b8 | 1193 | return -EINVAL; |
2bf3c85a | 1194 | |
42b29870 | 1195 | mutex_lock(&spec->pcm_lock); |
4e76a883 | 1196 | pin_idx = hinfo_to_pin_index(codec, hinfo); |
42b29870 LY |
1197 | if (!spec->dyn_pcm_assign) { |
1198 | if (snd_BUG_ON(pin_idx < 0)) { | |
f69548ff TI |
1199 | err = -EINVAL; |
1200 | goto unlock; | |
42b29870 LY |
1201 | } |
1202 | } else { | |
1203 | /* no pin is assigned to the PCM | |
1204 | * PA need pcm open successfully when probe | |
1205 | */ | |
1206 | if (pin_idx < 0) { | |
1207 | err = hdmi_pcm_open_no_pin(hinfo, codec, substream); | |
f69548ff | 1208 | goto unlock; |
42b29870 LY |
1209 | } |
1210 | } | |
7ef166b8 | 1211 | |
4846a67e | 1212 | err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx); |
f69548ff TI |
1213 | if (err < 0) |
1214 | goto unlock; | |
7ef166b8 WX |
1215 | |
1216 | per_cvt = get_cvt(spec, cvt_idx); | |
384a48d7 SW |
1217 | /* Claim converter */ |
1218 | per_cvt->assigned = 1; | |
42b29870 | 1219 | |
ac98379a | 1220 | set_bit(pcm_idx, &spec->pcm_in_use); |
42b29870 | 1221 | per_pin = get_pin(spec, pin_idx); |
1df5a06a | 1222 | per_pin->cvt_nid = per_cvt->cvt_nid; |
384a48d7 SW |
1223 | hinfo->nid = per_cvt->cvt_nid; |
1224 | ||
9152085d | 1225 | snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); |
bddee96b | 1226 | snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, |
384a48d7 | 1227 | AC_VERB_SET_CONNECT_SEL, |
4846a67e | 1228 | per_pin->mux_idx); |
7ef166b8 WX |
1229 | |
1230 | /* configure unused pins to choose other converters */ | |
4846a67e | 1231 | pin_cvt_fixup(codec, per_pin, 0); |
7ef166b8 | 1232 | |
2bf3c85a | 1233 | snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid); |
bbbe3390 | 1234 | |
2def8172 | 1235 | /* Initially set the converter's capabilities */ |
384a48d7 SW |
1236 | hinfo->channels_min = per_cvt->channels_min; |
1237 | hinfo->channels_max = per_cvt->channels_max; | |
1238 | hinfo->rates = per_cvt->rates; | |
1239 | hinfo->formats = per_cvt->formats; | |
1240 | hinfo->maxbps = per_cvt->maxbps; | |
2def8172 | 1241 | |
42b29870 | 1242 | eld = &per_pin->sink_eld; |
384a48d7 | 1243 | /* Restrict capabilities by ELD if this isn't disabled */ |
c3d52105 | 1244 | if (!static_hdmi_pcm && eld->eld_valid) { |
1613d6b4 | 1245 | snd_hdmi_eld_update_pcm_info(&eld->info, hinfo); |
bbbe3390 | 1246 | if (hinfo->channels_min > hinfo->channels_max || |
2ad779b7 TI |
1247 | !hinfo->rates || !hinfo->formats) { |
1248 | per_cvt->assigned = 0; | |
1249 | hinfo->nid = 0; | |
2bf3c85a | 1250 | snd_hda_spdif_ctls_unassign(codec, pcm_idx); |
f69548ff TI |
1251 | err = -ENODEV; |
1252 | goto unlock; | |
2ad779b7 | 1253 | } |
bbbe3390 | 1254 | } |
2def8172 SW |
1255 | |
1256 | /* Store the updated parameters */ | |
639cef0e TI |
1257 | runtime->hw.channels_min = hinfo->channels_min; |
1258 | runtime->hw.channels_max = hinfo->channels_max; | |
1259 | runtime->hw.formats = hinfo->formats; | |
1260 | runtime->hw.rates = hinfo->rates; | |
4fe2ca14 TI |
1261 | |
1262 | snd_pcm_hw_constraint_step(substream->runtime, 0, | |
1263 | SNDRV_PCM_HW_PARAM_CHANNELS, 2); | |
f69548ff TI |
1264 | unlock: |
1265 | mutex_unlock(&spec->pcm_lock); | |
1266 | return err; | |
bbbe3390 TI |
1267 | } |
1268 | ||
079d88cc WF |
1269 | /* |
1270 | * HDA/HDMI auto parsing | |
1271 | */ | |
384a48d7 | 1272 | static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx) |
079d88cc WF |
1273 | { |
1274 | struct hdmi_spec *spec = codec->spec; | |
bce0d2a8 | 1275 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); |
384a48d7 | 1276 | hda_nid_t pin_nid = per_pin->pin_nid; |
079d88cc WF |
1277 | |
1278 | if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) { | |
4e76a883 TI |
1279 | codec_warn(codec, |
1280 | "HDMI: pin %d wcaps %#x does not support connection list\n", | |
079d88cc WF |
1281 | pin_nid, get_wcaps(codec, pin_nid)); |
1282 | return -EINVAL; | |
1283 | } | |
1284 | ||
9152085d | 1285 | /* all the device entries on the same pin have the same conn list */ |
384a48d7 SW |
1286 | per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid, |
1287 | per_pin->mux_nids, | |
1288 | HDA_MAX_CONNECTIONS); | |
079d88cc WF |
1289 | |
1290 | return 0; | |
1291 | } | |
1292 | ||
a76056f2 LY |
1293 | static int hdmi_find_pcm_slot(struct hdmi_spec *spec, |
1294 | struct hdmi_spec_per_pin *per_pin) | |
1295 | { | |
1296 | int i; | |
1297 | ||
1298 | /* try the prefer PCM */ | |
1299 | if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap)) | |
1300 | return per_pin->pin_nid_idx; | |
1301 | ||
1302 | /* have a second try; check the "reserved area" over num_pins */ | |
9152085d | 1303 | for (i = spec->num_nids; i < spec->pcm_used; i++) { |
a76056f2 LY |
1304 | if (!test_bit(i, &spec->pcm_bitmap)) |
1305 | return i; | |
1306 | } | |
1307 | ||
1308 | /* the last try; check the empty slots in pins */ | |
9152085d | 1309 | for (i = 0; i < spec->num_nids; i++) { |
a76056f2 LY |
1310 | if (!test_bit(i, &spec->pcm_bitmap)) |
1311 | return i; | |
1312 | } | |
1313 | return -EBUSY; | |
1314 | } | |
1315 | ||
1316 | static void hdmi_attach_hda_pcm(struct hdmi_spec *spec, | |
1317 | struct hdmi_spec_per_pin *per_pin) | |
1318 | { | |
1319 | int idx; | |
1320 | ||
1321 | /* pcm already be attached to the pin */ | |
1322 | if (per_pin->pcm) | |
1323 | return; | |
1324 | idx = hdmi_find_pcm_slot(spec, per_pin); | |
d10a80de | 1325 | if (idx == -EBUSY) |
a76056f2 LY |
1326 | return; |
1327 | per_pin->pcm_idx = idx; | |
2bea241a | 1328 | per_pin->pcm = get_hdmi_pcm(spec, idx); |
a76056f2 LY |
1329 | set_bit(idx, &spec->pcm_bitmap); |
1330 | } | |
1331 | ||
1332 | static void hdmi_detach_hda_pcm(struct hdmi_spec *spec, | |
1333 | struct hdmi_spec_per_pin *per_pin) | |
1334 | { | |
1335 | int idx; | |
1336 | ||
1337 | /* pcm already be detached from the pin */ | |
1338 | if (!per_pin->pcm) | |
1339 | return; | |
1340 | idx = per_pin->pcm_idx; | |
1341 | per_pin->pcm_idx = -1; | |
1342 | per_pin->pcm = NULL; | |
1343 | if (idx >= 0 && idx < spec->pcm_used) | |
1344 | clear_bit(idx, &spec->pcm_bitmap); | |
1345 | } | |
1346 | ||
ac98379a LY |
1347 | static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec, |
1348 | struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid) | |
1349 | { | |
1350 | int mux_idx; | |
1351 | ||
1352 | for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) | |
1353 | if (per_pin->mux_nids[mux_idx] == cvt_nid) | |
1354 | break; | |
1355 | return mux_idx; | |
1356 | } | |
1357 | ||
1358 | static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid); | |
1359 | ||
1360 | static void hdmi_pcm_setup_pin(struct hdmi_spec *spec, | |
1361 | struct hdmi_spec_per_pin *per_pin) | |
1362 | { | |
1363 | struct hda_codec *codec = per_pin->codec; | |
1364 | struct hda_pcm *pcm; | |
1365 | struct hda_pcm_stream *hinfo; | |
1366 | struct snd_pcm_substream *substream; | |
1367 | int mux_idx; | |
1368 | bool non_pcm; | |
1369 | ||
1370 | if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) | |
2bea241a | 1371 | pcm = get_pcm_rec(spec, per_pin->pcm_idx); |
ac98379a LY |
1372 | else |
1373 | return; | |
8a7d6003 TI |
1374 | if (!pcm->pcm) |
1375 | return; | |
ac98379a LY |
1376 | if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use)) |
1377 | return; | |
1378 | ||
1379 | /* hdmi audio only uses playback and one substream */ | |
1380 | hinfo = pcm->stream; | |
1381 | substream = pcm->pcm->streams[0].substream; | |
1382 | ||
1383 | per_pin->cvt_nid = hinfo->nid; | |
1384 | ||
1385 | mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid); | |
9152085d LY |
1386 | if (mux_idx < per_pin->num_mux_nids) { |
1387 | snd_hda_set_dev_select(codec, per_pin->pin_nid, | |
1388 | per_pin->dev_id); | |
ac98379a LY |
1389 | snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, |
1390 | AC_VERB_SET_CONNECT_SEL, | |
1391 | mux_idx); | |
9152085d | 1392 | } |
ac98379a LY |
1393 | snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid); |
1394 | ||
1395 | non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid); | |
1396 | if (substream->runtime) | |
1397 | per_pin->channels = substream->runtime->channels; | |
1398 | per_pin->setup = true; | |
1399 | per_pin->mux_idx = mux_idx; | |
1400 | ||
1401 | hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); | |
1402 | } | |
1403 | ||
1404 | static void hdmi_pcm_reset_pin(struct hdmi_spec *spec, | |
1405 | struct hdmi_spec_per_pin *per_pin) | |
1406 | { | |
1407 | if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) | |
1408 | snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx); | |
1409 | ||
1410 | per_pin->chmap_set = false; | |
1411 | memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); | |
1412 | ||
1413 | per_pin->setup = false; | |
1414 | per_pin->channels = 0; | |
1415 | } | |
1416 | ||
e90247f9 TI |
1417 | /* update per_pin ELD from the given new ELD; |
1418 | * setup info frame and notification accordingly | |
1419 | */ | |
551626ec | 1420 | static bool update_eld(struct hda_codec *codec, |
e90247f9 TI |
1421 | struct hdmi_spec_per_pin *per_pin, |
1422 | struct hdmi_eld *eld) | |
1423 | { | |
1424 | struct hdmi_eld *pin_eld = &per_pin->sink_eld; | |
a76056f2 | 1425 | struct hdmi_spec *spec = codec->spec; |
e90247f9 TI |
1426 | bool old_eld_valid = pin_eld->eld_valid; |
1427 | bool eld_changed; | |
f953e72c | 1428 | int pcm_idx; |
e90247f9 | 1429 | |
fb087eaa LY |
1430 | /* for monitor disconnection, save pcm_idx firstly */ |
1431 | pcm_idx = per_pin->pcm_idx; | |
a76056f2 | 1432 | if (spec->dyn_pcm_assign) { |
ac98379a | 1433 | if (eld->eld_valid) { |
a76056f2 | 1434 | hdmi_attach_hda_pcm(spec, per_pin); |
ac98379a LY |
1435 | hdmi_pcm_setup_pin(spec, per_pin); |
1436 | } else { | |
1437 | hdmi_pcm_reset_pin(spec, per_pin); | |
a76056f2 | 1438 | hdmi_detach_hda_pcm(spec, per_pin); |
ac98379a | 1439 | } |
a76056f2 | 1440 | } |
fb087eaa LY |
1441 | /* if pcm_idx == -1, it means this is in monitor connection event |
1442 | * we can get the correct pcm_idx now. | |
1443 | */ | |
1444 | if (pcm_idx == -1) | |
1445 | pcm_idx = per_pin->pcm_idx; | |
a76056f2 | 1446 | |
e90247f9 TI |
1447 | if (eld->eld_valid) |
1448 | snd_hdmi_show_eld(codec, &eld->info); | |
1449 | ||
1450 | eld_changed = (pin_eld->eld_valid != eld->eld_valid); | |
551626ec TI |
1451 | eld_changed |= (pin_eld->monitor_present != eld->monitor_present); |
1452 | if (!eld_changed && eld->eld_valid && pin_eld->eld_valid) | |
e90247f9 TI |
1453 | if (pin_eld->eld_size != eld->eld_size || |
1454 | memcmp(pin_eld->eld_buffer, eld->eld_buffer, | |
1455 | eld->eld_size) != 0) | |
1456 | eld_changed = true; | |
1457 | ||
551626ec TI |
1458 | if (eld_changed) { |
1459 | pin_eld->monitor_present = eld->monitor_present; | |
1460 | pin_eld->eld_valid = eld->eld_valid; | |
1461 | pin_eld->eld_size = eld->eld_size; | |
1462 | if (eld->eld_valid) | |
1463 | memcpy(pin_eld->eld_buffer, eld->eld_buffer, | |
1464 | eld->eld_size); | |
1465 | pin_eld->info = eld->info; | |
1466 | } | |
e90247f9 TI |
1467 | |
1468 | /* | |
1469 | * Re-setup pin and infoframe. This is needed e.g. when | |
1470 | * - sink is first plugged-in | |
1471 | * - transcoder can change during stream playback on Haswell | |
1472 | * and this can make HW reset converter selection on a pin. | |
1473 | */ | |
1474 | if (eld->eld_valid && !old_eld_valid && per_pin->setup) { | |
4846a67e | 1475 | pin_cvt_fixup(codec, per_pin, 0); |
e90247f9 TI |
1476 | hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); |
1477 | } | |
1478 | ||
fb087eaa | 1479 | if (eld_changed && pcm_idx >= 0) |
e90247f9 TI |
1480 | snd_ctl_notify(codec->card, |
1481 | SNDRV_CTL_EVENT_MASK_VALUE | | |
1482 | SNDRV_CTL_EVENT_MASK_INFO, | |
fb087eaa | 1483 | &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id); |
551626ec | 1484 | return eld_changed; |
e90247f9 TI |
1485 | } |
1486 | ||
788d441a TI |
1487 | /* update ELD and jack state via HD-audio verbs */ |
1488 | static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin, | |
1489 | int repoll) | |
079d88cc | 1490 | { |
464837a7 | 1491 | struct hda_jack_tbl *jack; |
744626da | 1492 | struct hda_codec *codec = per_pin->codec; |
4bd038f9 DH |
1493 | struct hdmi_spec *spec = codec->spec; |
1494 | struct hdmi_eld *eld = &spec->temp_eld; | |
744626da | 1495 | hda_nid_t pin_nid = per_pin->pin_nid; |
5d44f927 SW |
1496 | /* |
1497 | * Always execute a GetPinSense verb here, even when called from | |
1498 | * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited | |
1499 | * response's PD bit is not the real PD value, but indicates that | |
1500 | * the real PD value changed. An older version of the HD-audio | |
1501 | * specification worked this way. Hence, we just ignore the data in | |
1502 | * the unsolicited response to avoid custom WARs. | |
1503 | */ | |
da4a7a39 | 1504 | int present; |
efe47108 | 1505 | bool ret; |
9a5e5234 | 1506 | bool do_repoll = false; |
079d88cc | 1507 | |
da4a7a39 DH |
1508 | present = snd_hda_pin_sense(codec, pin_nid); |
1509 | ||
a4e9a38b | 1510 | mutex_lock(&per_pin->lock); |
c44da62b TI |
1511 | eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE); |
1512 | if (eld->monitor_present) | |
4bd038f9 DH |
1513 | eld->eld_valid = !!(present & AC_PINSENSE_ELDV); |
1514 | else | |
1515 | eld->eld_valid = false; | |
079d88cc | 1516 | |
4e76a883 | 1517 | codec_dbg(codec, |
384a48d7 | 1518 | "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n", |
c44da62b | 1519 | codec->addr, pin_nid, eld->monitor_present, eld->eld_valid); |
5d44f927 | 1520 | |
4bd038f9 | 1521 | if (eld->eld_valid) { |
307229d2 | 1522 | if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer, |
1613d6b4 | 1523 | &eld->eld_size) < 0) |
4bd038f9 | 1524 | eld->eld_valid = false; |
1613d6b4 | 1525 | else { |
79514d47 | 1526 | if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer, |
1613d6b4 | 1527 | eld->eld_size) < 0) |
4bd038f9 | 1528 | eld->eld_valid = false; |
1613d6b4 | 1529 | } |
9a5e5234 TI |
1530 | if (!eld->eld_valid && repoll) |
1531 | do_repoll = true; | |
744626da | 1532 | } |
4bd038f9 | 1533 | |
9a5e5234 | 1534 | if (do_repoll) |
e90247f9 TI |
1535 | schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300)); |
1536 | else | |
1537 | update_eld(codec, per_pin, eld); | |
92c69e79 | 1538 | |
c44da62b | 1539 | ret = !repoll || !eld->monitor_present || eld->eld_valid; |
464837a7 DH |
1540 | |
1541 | jack = snd_hda_jack_tbl_get(codec, pin_nid); | |
7f641e26 | 1542 | if (jack) { |
464837a7 | 1543 | jack->block_report = !ret; |
7f641e26 HW |
1544 | jack->pin_sense = (eld->monitor_present && eld->eld_valid) ? |
1545 | AC_PINSENSE_PRESENCE : 0; | |
1546 | } | |
a4e9a38b | 1547 | mutex_unlock(&per_pin->lock); |
efe47108 | 1548 | return ret; |
079d88cc WF |
1549 | } |
1550 | ||
3184270e LY |
1551 | static struct snd_jack *pin_idx_to_jack(struct hda_codec *codec, |
1552 | struct hdmi_spec_per_pin *per_pin) | |
1553 | { | |
1554 | struct hdmi_spec *spec = codec->spec; | |
1555 | struct snd_jack *jack = NULL; | |
1556 | struct hda_jack_tbl *jack_tbl; | |
1557 | ||
1558 | /* if !dyn_pcm_assign, get jack from hda_jack_tbl | |
1559 | * in !dyn_pcm_assign case, spec->pcm_rec[].jack is not | |
1560 | * NULL even after snd_hda_jack_tbl_clear() is called to | |
1561 | * free snd_jack. This may cause access invalid memory | |
1562 | * when calling snd_jack_report | |
1563 | */ | |
1564 | if (per_pin->pcm_idx >= 0 && spec->dyn_pcm_assign) | |
1565 | jack = spec->pcm_rec[per_pin->pcm_idx].jack; | |
1566 | else if (!spec->dyn_pcm_assign) { | |
9152085d LY |
1567 | /* |
1568 | * jack tbl doesn't support DP MST | |
1569 | * DP MST will use dyn_pcm_assign, | |
1570 | * so DP MST will never come here | |
1571 | */ | |
3184270e LY |
1572 | jack_tbl = snd_hda_jack_tbl_get(codec, per_pin->pin_nid); |
1573 | if (jack_tbl) | |
1574 | jack = jack_tbl->jack; | |
1575 | } | |
1576 | return jack; | |
1577 | } | |
1578 | ||
788d441a TI |
1579 | /* update ELD and jack state via audio component */ |
1580 | static void sync_eld_via_acomp(struct hda_codec *codec, | |
1581 | struct hdmi_spec_per_pin *per_pin) | |
1582 | { | |
788d441a TI |
1583 | struct hdmi_spec *spec = codec->spec; |
1584 | struct hdmi_eld *eld = &spec->temp_eld; | |
25e4abb3 | 1585 | struct snd_jack *jack = NULL; |
551626ec | 1586 | bool changed; |
788d441a TI |
1587 | int size; |
1588 | ||
e2dc7d7d | 1589 | mutex_lock(&per_pin->lock); |
c64c1437 | 1590 | eld->monitor_present = false; |
9152085d LY |
1591 | size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid, |
1592 | per_pin->dev_id, &eld->monitor_present, | |
1593 | eld->eld_buffer, ELD_MAX_SIZE); | |
e2dc7d7d TI |
1594 | if (size > 0) { |
1595 | size = min(size, ELD_MAX_SIZE); | |
1596 | if (snd_hdmi_parse_eld(codec, &eld->info, | |
1597 | eld->eld_buffer, size) < 0) | |
1598 | size = -EINVAL; | |
1599 | } | |
788d441a | 1600 | |
e2dc7d7d TI |
1601 | if (size > 0) { |
1602 | eld->eld_valid = true; | |
1603 | eld->eld_size = size; | |
1604 | } else { | |
1605 | eld->eld_valid = false; | |
1606 | eld->eld_size = 0; | |
788d441a | 1607 | } |
e2dc7d7d | 1608 | |
25e4abb3 LY |
1609 | /* pcm_idx >=0 before update_eld() means it is in monitor |
1610 | * disconnected event. Jack must be fetched before update_eld() | |
1611 | */ | |
3184270e | 1612 | jack = pin_idx_to_jack(codec, per_pin); |
551626ec | 1613 | changed = update_eld(codec, per_pin, eld); |
3184270e LY |
1614 | if (jack == NULL) |
1615 | jack = pin_idx_to_jack(codec, per_pin); | |
551626ec TI |
1616 | if (changed && jack) |
1617 | snd_jack_report(jack, | |
1618 | (eld->monitor_present && eld->eld_valid) ? | |
855b5e01 | 1619 | SND_JACK_AVOUT : 0); |
e2dc7d7d | 1620 | mutex_unlock(&per_pin->lock); |
788d441a TI |
1621 | } |
1622 | ||
1623 | static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll) | |
1624 | { | |
1625 | struct hda_codec *codec = per_pin->codec; | |
a76056f2 | 1626 | int ret; |
788d441a | 1627 | |
222bde03 | 1628 | /* no temporary power up/down needed for component notifier */ |
aaa23f86 CW |
1629 | if (!codec_has_acomp(codec)) { |
1630 | ret = snd_hda_power_up_pm(codec); | |
1631 | if (ret < 0 && pm_runtime_suspended(hda_codec_dev(codec))) { | |
1632 | snd_hda_power_down_pm(codec); | |
1633 | return false; | |
1634 | } | |
ade49db3 TI |
1635 | ret = hdmi_present_sense_via_verbs(per_pin, repoll); |
1636 | snd_hda_power_down_pm(codec); | |
1637 | } else { | |
788d441a | 1638 | sync_eld_via_acomp(codec, per_pin); |
a76056f2 | 1639 | ret = false; /* don't call snd_hda_jack_report_sync() */ |
788d441a | 1640 | } |
a76056f2 LY |
1641 | |
1642 | return ret; | |
788d441a TI |
1643 | } |
1644 | ||
744626da WF |
1645 | static void hdmi_repoll_eld(struct work_struct *work) |
1646 | { | |
1647 | struct hdmi_spec_per_pin *per_pin = | |
1648 | container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work); | |
aaa23f86 CW |
1649 | struct hda_codec *codec = per_pin->codec; |
1650 | struct hdmi_spec *spec = codec->spec; | |
8c2e6728 HW |
1651 | struct hda_jack_tbl *jack; |
1652 | ||
1653 | jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid); | |
1654 | if (jack) | |
1655 | jack->jack_dirty = 1; | |
744626da | 1656 | |
c6e8453e WF |
1657 | if (per_pin->repoll_count++ > 6) |
1658 | per_pin->repoll_count = 0; | |
1659 | ||
aaa23f86 | 1660 | mutex_lock(&spec->pcm_lock); |
efe47108 TI |
1661 | if (hdmi_present_sense(per_pin, per_pin->repoll_count)) |
1662 | snd_hda_jack_report_sync(per_pin->codec); | |
aaa23f86 | 1663 | mutex_unlock(&spec->pcm_lock); |
744626da WF |
1664 | } |
1665 | ||
c88d4e84 TI |
1666 | static void intel_haswell_fixup_connect_list(struct hda_codec *codec, |
1667 | hda_nid_t nid); | |
1668 | ||
079d88cc WF |
1669 | static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid) |
1670 | { | |
1671 | struct hdmi_spec *spec = codec->spec; | |
384a48d7 SW |
1672 | unsigned int caps, config; |
1673 | int pin_idx; | |
1674 | struct hdmi_spec_per_pin *per_pin; | |
07acecc1 | 1675 | int err; |
9152085d | 1676 | int dev_num, i; |
079d88cc | 1677 | |
efc2f8de | 1678 | caps = snd_hda_query_pin_caps(codec, pin_nid); |
384a48d7 SW |
1679 | if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP))) |
1680 | return 0; | |
1681 | ||
9152085d LY |
1682 | /* |
1683 | * For DP MST audio, Configuration Default is the same for | |
1684 | * all device entries on the same pin | |
1685 | */ | |
efc2f8de | 1686 | config = snd_hda_codec_get_pincfg(codec, pin_nid); |
384a48d7 SW |
1687 | if (get_defcfg_connect(config) == AC_JACK_PORT_NONE) |
1688 | return 0; | |
1689 | ||
9152085d LY |
1690 | /* |
1691 | * To simplify the implementation, malloc all | |
1692 | * the virtual pins in the initialization statically | |
1693 | */ | |
cb45722b | 1694 | if (spec->intel_hsw_fixup) { |
9152085d LY |
1695 | /* |
1696 | * On Intel platforms, device entries number is | |
1697 | * changed dynamically. If there is a DP MST | |
1698 | * hub connected, the device entries number is 3. | |
1699 | * Otherwise, it is 1. | |
1700 | * Here we manually set dev_num to 3, so that | |
1701 | * we can initialize all the device entries when | |
1702 | * bootup statically. | |
1703 | */ | |
1704 | dev_num = 3; | |
1705 | spec->dev_num = 3; | |
1706 | } else if (spec->dyn_pcm_assign && codec->dp_mst) { | |
1707 | dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1; | |
1708 | /* | |
1709 | * spec->dev_num is the maxinum number of device entries | |
1710 | * among all the pins | |
1711 | */ | |
1712 | spec->dev_num = (spec->dev_num > dev_num) ? | |
1713 | spec->dev_num : dev_num; | |
1714 | } else { | |
1715 | /* | |
1716 | * If the platform doesn't support DP MST, | |
1717 | * manually set dev_num to 1. This means | |
1718 | * the pin has only one device entry. | |
1719 | */ | |
1720 | dev_num = 1; | |
1721 | spec->dev_num = 1; | |
2bea241a | 1722 | } |
079d88cc | 1723 | |
9152085d LY |
1724 | for (i = 0; i < dev_num; i++) { |
1725 | pin_idx = spec->num_pins; | |
1726 | per_pin = snd_array_new(&spec->pins); | |
079d88cc | 1727 | |
9152085d LY |
1728 | if (!per_pin) |
1729 | return -ENOMEM; | |
1730 | ||
1731 | if (spec->dyn_pcm_assign) { | |
1732 | per_pin->pcm = NULL; | |
1733 | per_pin->pcm_idx = -1; | |
1734 | } else { | |
1735 | per_pin->pcm = get_hdmi_pcm(spec, pin_idx); | |
1736 | per_pin->pcm_idx = pin_idx; | |
1737 | } | |
1738 | per_pin->pin_nid = pin_nid; | |
1739 | per_pin->pin_nid_idx = spec->num_nids; | |
1740 | per_pin->dev_id = i; | |
1741 | per_pin->non_pcm = false; | |
1742 | snd_hda_set_dev_select(codec, pin_nid, i); | |
cb45722b | 1743 | if (spec->intel_hsw_fixup) |
9152085d LY |
1744 | intel_haswell_fixup_connect_list(codec, pin_nid); |
1745 | err = hdmi_read_pin_conn(codec, pin_idx); | |
1746 | if (err < 0) | |
1747 | return err; | |
1748 | spec->num_pins++; | |
1749 | } | |
1750 | spec->num_nids++; | |
079d88cc | 1751 | |
384a48d7 | 1752 | return 0; |
079d88cc WF |
1753 | } |
1754 | ||
384a48d7 | 1755 | static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) |
079d88cc WF |
1756 | { |
1757 | struct hdmi_spec *spec = codec->spec; | |
384a48d7 SW |
1758 | struct hdmi_spec_per_cvt *per_cvt; |
1759 | unsigned int chans; | |
1760 | int err; | |
079d88cc | 1761 | |
384a48d7 SW |
1762 | chans = get_wcaps(codec, cvt_nid); |
1763 | chans = get_wcaps_channels(chans); | |
1764 | ||
bce0d2a8 TI |
1765 | per_cvt = snd_array_new(&spec->cvts); |
1766 | if (!per_cvt) | |
1767 | return -ENOMEM; | |
384a48d7 SW |
1768 | |
1769 | per_cvt->cvt_nid = cvt_nid; | |
1770 | per_cvt->channels_min = 2; | |
d45e6889 | 1771 | if (chans <= 16) { |
384a48d7 | 1772 | per_cvt->channels_max = chans; |
67b90cb8 SP |
1773 | if (chans > spec->chmap.channels_max) |
1774 | spec->chmap.channels_max = chans; | |
d45e6889 | 1775 | } |
384a48d7 SW |
1776 | |
1777 | err = snd_hda_query_supported_pcm(codec, cvt_nid, | |
1778 | &per_cvt->rates, | |
1779 | &per_cvt->formats, | |
1780 | &per_cvt->maxbps); | |
1781 | if (err < 0) | |
1782 | return err; | |
1783 | ||
bce0d2a8 TI |
1784 | if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids)) |
1785 | spec->cvt_nids[spec->num_cvts] = cvt_nid; | |
1786 | spec->num_cvts++; | |
079d88cc WF |
1787 | |
1788 | return 0; | |
1789 | } | |
1790 | ||
1791 | static int hdmi_parse_codec(struct hda_codec *codec) | |
1792 | { | |
1793 | hda_nid_t nid; | |
1794 | int i, nodes; | |
1795 | ||
7639a06c | 1796 | nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid); |
079d88cc | 1797 | if (!nid || nodes < 0) { |
4e76a883 | 1798 | codec_warn(codec, "HDMI: failed to get afg sub nodes\n"); |
079d88cc WF |
1799 | return -EINVAL; |
1800 | } | |
1801 | ||
1802 | for (i = 0; i < nodes; i++, nid++) { | |
1803 | unsigned int caps; | |
1804 | unsigned int type; | |
1805 | ||
efc2f8de | 1806 | caps = get_wcaps(codec, nid); |
079d88cc WF |
1807 | type = get_wcaps_type(caps); |
1808 | ||
1809 | if (!(caps & AC_WCAP_DIGITAL)) | |
1810 | continue; | |
1811 | ||
1812 | switch (type) { | |
1813 | case AC_WID_AUD_OUT: | |
384a48d7 | 1814 | hdmi_add_cvt(codec, nid); |
079d88cc WF |
1815 | break; |
1816 | case AC_WID_PIN: | |
3eaead57 | 1817 | hdmi_add_pin(codec, nid); |
079d88cc WF |
1818 | break; |
1819 | } | |
1820 | } | |
1821 | ||
079d88cc WF |
1822 | return 0; |
1823 | } | |
1824 | ||
84eb01be TI |
1825 | /* |
1826 | */ | |
1a6003b5 TI |
1827 | static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) |
1828 | { | |
1829 | struct hda_spdif_out *spdif; | |
1830 | bool non_pcm; | |
1831 | ||
1832 | mutex_lock(&codec->spdif_mutex); | |
1833 | spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid); | |
960a581e LY |
1834 | /* Add sanity check to pass klockwork check. |
1835 | * This should never happen. | |
1836 | */ | |
1837 | if (WARN_ON(spdif == NULL)) | |
1838 | return true; | |
1a6003b5 TI |
1839 | non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO); |
1840 | mutex_unlock(&codec->spdif_mutex); | |
1841 | return non_pcm; | |
1842 | } | |
1843 | ||
84eb01be TI |
1844 | /* |
1845 | * HDMI callbacks | |
1846 | */ | |
1847 | ||
1848 | static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo, | |
1849 | struct hda_codec *codec, | |
1850 | unsigned int stream_tag, | |
1851 | unsigned int format, | |
1852 | struct snd_pcm_substream *substream) | |
1853 | { | |
384a48d7 SW |
1854 | hda_nid_t cvt_nid = hinfo->nid; |
1855 | struct hdmi_spec *spec = codec->spec; | |
42b29870 LY |
1856 | int pin_idx; |
1857 | struct hdmi_spec_per_pin *per_pin; | |
1858 | hda_nid_t pin_nid; | |
ddd621fb | 1859 | struct snd_pcm_runtime *runtime = substream->runtime; |
1a6003b5 | 1860 | bool non_pcm; |
053b0559 | 1861 | int pinctl, stripe; |
f69548ff | 1862 | int err = 0; |
1a6003b5 | 1863 | |
42b29870 LY |
1864 | mutex_lock(&spec->pcm_lock); |
1865 | pin_idx = hinfo_to_pin_index(codec, hinfo); | |
1866 | if (spec->dyn_pcm_assign && pin_idx < 0) { | |
1867 | /* when dyn_pcm_assign and pcm is not bound to a pin | |
1868 | * skip pin setup and return 0 to make audio playback | |
1869 | * be ongoing | |
1870 | */ | |
4846a67e | 1871 | pin_cvt_fixup(codec, NULL, cvt_nid); |
42b29870 LY |
1872 | snd_hda_codec_setup_stream(codec, cvt_nid, |
1873 | stream_tag, 0, format); | |
f69548ff | 1874 | goto unlock; |
42b29870 | 1875 | } |
1a6003b5 | 1876 | |
42b29870 | 1877 | if (snd_BUG_ON(pin_idx < 0)) { |
f69548ff TI |
1878 | err = -EINVAL; |
1879 | goto unlock; | |
42b29870 LY |
1880 | } |
1881 | per_pin = get_pin(spec, pin_idx); | |
1882 | pin_nid = per_pin->pin_nid; | |
4846a67e TI |
1883 | |
1884 | /* Verify pin:cvt selections to avoid silent audio after S3. | |
1885 | * After S3, the audio driver restores pin:cvt selections | |
1886 | * but this can happen before gfx is ready and such selection | |
1887 | * is overlooked by HW. Thus multiple pins can share a same | |
1888 | * default convertor and mute control will affect each other, | |
1889 | * which can cause a resumed audio playback become silent | |
1890 | * after S3. | |
1891 | */ | |
1892 | pin_cvt_fixup(codec, per_pin, 0); | |
2df6742f | 1893 | |
ddd621fb LY |
1894 | /* Call sync_audio_rate to set the N/CTS/M manually if necessary */ |
1895 | /* Todo: add DP1.2 MST audio support later */ | |
93a9ff15 | 1896 | if (codec_has_acomp(codec)) |
9152085d | 1897 | snd_hdac_sync_audio_rate(&codec->core, pin_nid, per_pin->dev_id, |
f9318941 | 1898 | runtime->rate); |
ddd621fb | 1899 | |
1a6003b5 | 1900 | non_pcm = check_non_pcm_per_cvt(codec, cvt_nid); |
a4e9a38b | 1901 | mutex_lock(&per_pin->lock); |
b054087d TI |
1902 | per_pin->channels = substream->runtime->channels; |
1903 | per_pin->setup = true; | |
384a48d7 | 1904 | |
053b0559 SP |
1905 | if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) { |
1906 | stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core, | |
1907 | substream); | |
1908 | snd_hda_codec_write(codec, cvt_nid, 0, | |
1909 | AC_VERB_SET_STRIPE_CONTROL, | |
1910 | stripe); | |
1911 | } | |
1912 | ||
b054087d | 1913 | hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); |
a4e9a38b | 1914 | mutex_unlock(&per_pin->lock); |
75fae117 SW |
1915 | if (spec->dyn_pin_out) { |
1916 | pinctl = snd_hda_codec_read(codec, pin_nid, 0, | |
1917 | AC_VERB_GET_PIN_WIDGET_CONTROL, 0); | |
1918 | snd_hda_codec_write(codec, pin_nid, 0, | |
1919 | AC_VERB_SET_PIN_WIDGET_CONTROL, | |
1920 | pinctl | PIN_OUT); | |
1921 | } | |
1922 | ||
9152085d | 1923 | /* snd_hda_set_dev_select() has been called before */ |
42b29870 LY |
1924 | err = spec->ops.setup_stream(codec, cvt_nid, pin_nid, |
1925 | stream_tag, format); | |
f69548ff | 1926 | unlock: |
42b29870 LY |
1927 | mutex_unlock(&spec->pcm_lock); |
1928 | return err; | |
84eb01be TI |
1929 | } |
1930 | ||
8dfaa573 TI |
1931 | static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, |
1932 | struct hda_codec *codec, | |
1933 | struct snd_pcm_substream *substream) | |
1934 | { | |
1935 | snd_hda_codec_cleanup_stream(codec, hinfo->nid); | |
1936 | return 0; | |
1937 | } | |
1938 | ||
f2ad24fa TI |
1939 | static int hdmi_pcm_close(struct hda_pcm_stream *hinfo, |
1940 | struct hda_codec *codec, | |
1941 | struct snd_pcm_substream *substream) | |
384a48d7 SW |
1942 | { |
1943 | struct hdmi_spec *spec = codec->spec; | |
2bf3c85a | 1944 | int cvt_idx, pin_idx, pcm_idx; |
384a48d7 SW |
1945 | struct hdmi_spec_per_cvt *per_cvt; |
1946 | struct hdmi_spec_per_pin *per_pin; | |
75fae117 | 1947 | int pinctl; |
f69548ff | 1948 | int err = 0; |
384a48d7 | 1949 | |
384a48d7 | 1950 | if (hinfo->nid) { |
2bf3c85a LY |
1951 | pcm_idx = hinfo_to_pcm_index(codec, hinfo); |
1952 | if (snd_BUG_ON(pcm_idx < 0)) | |
1953 | return -EINVAL; | |
4e76a883 | 1954 | cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid); |
384a48d7 SW |
1955 | if (snd_BUG_ON(cvt_idx < 0)) |
1956 | return -EINVAL; | |
bce0d2a8 | 1957 | per_cvt = get_cvt(spec, cvt_idx); |
384a48d7 SW |
1958 | |
1959 | snd_BUG_ON(!per_cvt->assigned); | |
1960 | per_cvt->assigned = 0; | |
1961 | hinfo->nid = 0; | |
1962 | ||
42b29870 | 1963 | mutex_lock(&spec->pcm_lock); |
b09887f8 | 1964 | snd_hda_spdif_ctls_unassign(codec, pcm_idx); |
ac98379a | 1965 | clear_bit(pcm_idx, &spec->pcm_in_use); |
4e76a883 | 1966 | pin_idx = hinfo_to_pin_index(codec, hinfo); |
f69548ff TI |
1967 | if (spec->dyn_pcm_assign && pin_idx < 0) |
1968 | goto unlock; | |
42b29870 LY |
1969 | |
1970 | if (snd_BUG_ON(pin_idx < 0)) { | |
f69548ff TI |
1971 | err = -EINVAL; |
1972 | goto unlock; | |
42b29870 | 1973 | } |
bce0d2a8 | 1974 | per_pin = get_pin(spec, pin_idx); |
384a48d7 | 1975 | |
75fae117 SW |
1976 | if (spec->dyn_pin_out) { |
1977 | pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, | |
1978 | AC_VERB_GET_PIN_WIDGET_CONTROL, 0); | |
1979 | snd_hda_codec_write(codec, per_pin->pin_nid, 0, | |
1980 | AC_VERB_SET_PIN_WIDGET_CONTROL, | |
1981 | pinctl & ~PIN_OUT); | |
1982 | } | |
1983 | ||
a4e9a38b | 1984 | mutex_lock(&per_pin->lock); |
d45e6889 TI |
1985 | per_pin->chmap_set = false; |
1986 | memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); | |
b054087d TI |
1987 | |
1988 | per_pin->setup = false; | |
1989 | per_pin->channels = 0; | |
a4e9a38b | 1990 | mutex_unlock(&per_pin->lock); |
f69548ff | 1991 | unlock: |
42b29870 | 1992 | mutex_unlock(&spec->pcm_lock); |
384a48d7 | 1993 | } |
d45e6889 | 1994 | |
f69548ff | 1995 | return err; |
384a48d7 SW |
1996 | } |
1997 | ||
1998 | static const struct hda_pcm_ops generic_ops = { | |
1999 | .open = hdmi_pcm_open, | |
f2ad24fa | 2000 | .close = hdmi_pcm_close, |
384a48d7 | 2001 | .prepare = generic_hdmi_playback_pcm_prepare, |
8dfaa573 | 2002 | .cleanup = generic_hdmi_playback_pcm_cleanup, |
84eb01be TI |
2003 | }; |
2004 | ||
44fde3b8 SP |
2005 | static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx) |
2006 | { | |
2007 | struct hda_codec *codec = container_of(hdac, struct hda_codec, core); | |
2008 | struct hdmi_spec *spec = codec->spec; | |
2009 | struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); | |
2010 | ||
2011 | if (!per_pin) | |
2012 | return 0; | |
2013 | ||
2014 | return per_pin->sink_eld.info.spk_alloc; | |
2015 | } | |
2016 | ||
9b3dc8aa SP |
2017 | static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx, |
2018 | unsigned char *chmap) | |
2019 | { | |
2020 | struct hda_codec *codec = container_of(hdac, struct hda_codec, core); | |
2021 | struct hdmi_spec *spec = codec->spec; | |
2022 | struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); | |
2023 | ||
2024 | /* chmap is already set to 0 in caller */ | |
2025 | if (!per_pin) | |
2026 | return; | |
2027 | ||
2028 | memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap)); | |
2029 | } | |
2030 | ||
2031 | static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx, | |
2032 | unsigned char *chmap, int prepared) | |
2033 | { | |
2034 | struct hda_codec *codec = container_of(hdac, struct hda_codec, core); | |
2035 | struct hdmi_spec *spec = codec->spec; | |
2036 | struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); | |
2037 | ||
ed0739b5 LY |
2038 | if (!per_pin) |
2039 | return; | |
9b3dc8aa SP |
2040 | mutex_lock(&per_pin->lock); |
2041 | per_pin->chmap_set = true; | |
2042 | memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap)); | |
2043 | if (prepared) | |
2044 | hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); | |
2045 | mutex_unlock(&per_pin->lock); | |
2046 | } | |
2047 | ||
2048 | static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx) | |
2049 | { | |
2050 | struct hda_codec *codec = container_of(hdac, struct hda_codec, core); | |
2051 | struct hdmi_spec *spec = codec->spec; | |
2052 | struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); | |
2053 | ||
2054 | return per_pin ? true:false; | |
2055 | } | |
2056 | ||
84eb01be TI |
2057 | static int generic_hdmi_build_pcms(struct hda_codec *codec) |
2058 | { | |
2059 | struct hdmi_spec *spec = codec->spec; | |
2a2edfbb | 2060 | int idx, pcm_num; |
84eb01be | 2061 | |
9152085d LY |
2062 | /* |
2063 | * for non-mst mode, pcm number is the same as before | |
2a2edfbb KV |
2064 | * for DP MST mode without extra PCM, pcm number is same |
2065 | * for DP MST mode with extra PCMs, pcm number is | |
2066 | * (nid number + dev_num - 1) | |
2067 | * dev_num is the device entry number in a pin | |
9152085d | 2068 | */ |
2a2edfbb KV |
2069 | |
2070 | if (codec->mst_no_extra_pcms) | |
2071 | pcm_num = spec->num_nids; | |
2072 | else | |
2073 | pcm_num = spec->num_nids + spec->dev_num - 1; | |
2074 | ||
2075 | codec_dbg(codec, "hdmi: pcm_num set to %d\n", pcm_num); | |
2076 | ||
2077 | for (idx = 0; idx < pcm_num; idx++) { | |
384a48d7 | 2078 | struct hda_pcm *info; |
84eb01be | 2079 | struct hda_pcm_stream *pstr; |
bce0d2a8 | 2080 | |
9152085d | 2081 | info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx); |
bce0d2a8 TI |
2082 | if (!info) |
2083 | return -ENOMEM; | |
2bea241a | 2084 | |
9152085d | 2085 | spec->pcm_rec[idx].pcm = info; |
2bf3c85a | 2086 | spec->pcm_used++; |
84eb01be | 2087 | info->pcm_type = HDA_PCM_TYPE_HDMI; |
d45e6889 | 2088 | info->own_chmap = true; |
384a48d7 | 2089 | |
84eb01be | 2090 | pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; |
384a48d7 SW |
2091 | pstr->substreams = 1; |
2092 | pstr->ops = generic_ops; | |
9152085d LY |
2093 | /* pcm number is less than 16 */ |
2094 | if (spec->pcm_used >= 16) | |
2095 | break; | |
384a48d7 | 2096 | /* other pstr fields are set in open */ |
84eb01be TI |
2097 | } |
2098 | ||
2099 | return 0; | |
2100 | } | |
2101 | ||
25e4abb3 | 2102 | static void free_hdmi_jack_priv(struct snd_jack *jack) |
788d441a | 2103 | { |
25e4abb3 | 2104 | struct hdmi_pcm *pcm = jack->private_data; |
788d441a | 2105 | |
25e4abb3 | 2106 | pcm->jack = NULL; |
788d441a TI |
2107 | } |
2108 | ||
25e4abb3 LY |
2109 | static int add_hdmi_jack_kctl(struct hda_codec *codec, |
2110 | struct hdmi_spec *spec, | |
2111 | int pcm_idx, | |
788d441a TI |
2112 | const char *name) |
2113 | { | |
2114 | struct snd_jack *jack; | |
2115 | int err; | |
2116 | ||
2117 | err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack, | |
2118 | true, false); | |
2119 | if (err < 0) | |
2120 | return err; | |
25e4abb3 LY |
2121 | |
2122 | spec->pcm_rec[pcm_idx].jack = jack; | |
2123 | jack->private_data = &spec->pcm_rec[pcm_idx]; | |
2124 | jack->private_free = free_hdmi_jack_priv; | |
788d441a TI |
2125 | return 0; |
2126 | } | |
2127 | ||
25e4abb3 | 2128 | static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx) |
0b6c49b5 | 2129 | { |
31ef2257 | 2130 | char hdmi_str[32] = "HDMI/DP"; |
0b6c49b5 | 2131 | struct hdmi_spec *spec = codec->spec; |
25e4abb3 LY |
2132 | struct hdmi_spec_per_pin *per_pin; |
2133 | struct hda_jack_tbl *jack; | |
2134 | int pcmdev = get_pcm_rec(spec, pcm_idx)->device; | |
909cadc6 | 2135 | bool phantom_jack; |
25e4abb3 | 2136 | int ret; |
0b6c49b5 | 2137 | |
31ef2257 TI |
2138 | if (pcmdev > 0) |
2139 | sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev); | |
25e4abb3 LY |
2140 | |
2141 | if (spec->dyn_pcm_assign) | |
2142 | return add_hdmi_jack_kctl(codec, spec, pcm_idx, hdmi_str); | |
2143 | ||
2144 | /* for !dyn_pcm_assign, we still use hda_jack for compatibility */ | |
2145 | /* if !dyn_pcm_assign, it must be non-MST mode. | |
2146 | * This means pcms and pins are statically mapped. | |
2147 | * And pcm_idx is pin_idx. | |
2148 | */ | |
2149 | per_pin = get_pin(spec, pcm_idx); | |
909cadc6 TI |
2150 | phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid); |
2151 | if (phantom_jack) | |
30efd8de DH |
2152 | strncat(hdmi_str, " Phantom", |
2153 | sizeof(hdmi_str) - strlen(hdmi_str) - 1); | |
25e4abb3 | 2154 | ret = snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, |
911761c2 | 2155 | phantom_jack, 0, NULL); |
25e4abb3 LY |
2156 | if (ret < 0) |
2157 | return ret; | |
2158 | jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid); | |
2159 | if (jack == NULL) | |
2160 | return 0; | |
2161 | /* assign jack->jack to pcm_rec[].jack to | |
2162 | * align with dyn_pcm_assign mode | |
2163 | */ | |
2164 | spec->pcm_rec[pcm_idx].jack = jack->jack; | |
2165 | return 0; | |
0b6c49b5 DH |
2166 | } |
2167 | ||
84eb01be TI |
2168 | static int generic_hdmi_build_controls(struct hda_codec *codec) |
2169 | { | |
2170 | struct hdmi_spec *spec = codec->spec; | |
1f7f51a6 | 2171 | int dev, err; |
25e4abb3 | 2172 | int pin_idx, pcm_idx; |
84eb01be | 2173 | |
25e4abb3 | 2174 | for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { |
8a7d6003 TI |
2175 | if (!get_pcm_rec(spec, pcm_idx)->pcm) { |
2176 | /* no PCM: mark this for skipping permanently */ | |
2177 | set_bit(pcm_idx, &spec->pcm_bitmap); | |
2178 | continue; | |
2179 | } | |
2180 | ||
25e4abb3 | 2181 | err = generic_hdmi_build_jack(codec, pcm_idx); |
0b6c49b5 DH |
2182 | if (err < 0) |
2183 | return err; | |
2184 | ||
b09887f8 LY |
2185 | /* create the spdif for each pcm |
2186 | * pin will be bound when monitor is connected | |
2187 | */ | |
2188 | if (spec->dyn_pcm_assign) | |
2189 | err = snd_hda_create_dig_out_ctls(codec, | |
2190 | 0, spec->cvt_nids[0], | |
2191 | HDA_PCM_TYPE_HDMI); | |
2192 | else { | |
2193 | struct hdmi_spec_per_pin *per_pin = | |
2194 | get_pin(spec, pcm_idx); | |
2195 | err = snd_hda_create_dig_out_ctls(codec, | |
dcda5806 TI |
2196 | per_pin->pin_nid, |
2197 | per_pin->mux_nids[0], | |
2198 | HDA_PCM_TYPE_HDMI); | |
b09887f8 | 2199 | } |
84eb01be TI |
2200 | if (err < 0) |
2201 | return err; | |
b09887f8 | 2202 | snd_hda_spdif_ctls_unassign(codec, pcm_idx); |
14bc52b8 | 2203 | |
1f7f51a6 WY |
2204 | dev = get_pcm_rec(spec, pcm_idx)->device; |
2205 | if (dev != SNDRV_PCM_INVALID_DEVICE) { | |
2206 | /* add control for ELD Bytes */ | |
2207 | err = hdmi_create_eld_ctl(codec, pcm_idx, dev); | |
2208 | if (err < 0) | |
2209 | return err; | |
2210 | } | |
fb087eaa LY |
2211 | } |
2212 | ||
2213 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { | |
2214 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); | |
31ef2257 | 2215 | |
82b1d73f | 2216 | hdmi_present_sense(per_pin, 0); |
84eb01be TI |
2217 | } |
2218 | ||
d45e6889 | 2219 | /* add channel maps */ |
022f344b | 2220 | for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { |
bbbc7e85 | 2221 | struct hda_pcm *pcm; |
2ca320e2 | 2222 | |
022f344b | 2223 | pcm = get_pcm_rec(spec, pcm_idx); |
bbbc7e85 | 2224 | if (!pcm || !pcm->pcm) |
2ca320e2 | 2225 | break; |
2f6e8a85 | 2226 | err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap); |
d45e6889 TI |
2227 | if (err < 0) |
2228 | return err; | |
d45e6889 TI |
2229 | } |
2230 | ||
84eb01be TI |
2231 | return 0; |
2232 | } | |
2233 | ||
8b8d654b | 2234 | static int generic_hdmi_init_per_pins(struct hda_codec *codec) |
84eb01be TI |
2235 | { |
2236 | struct hdmi_spec *spec = codec->spec; | |
384a48d7 SW |
2237 | int pin_idx; |
2238 | ||
2239 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { | |
bce0d2a8 | 2240 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); |
84eb01be | 2241 | |
744626da | 2242 | per_pin->codec = codec; |
a4e9a38b | 2243 | mutex_init(&per_pin->lock); |
744626da | 2244 | INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld); |
a4e9a38b | 2245 | eld_proc_new(per_pin, pin_idx); |
84eb01be | 2246 | } |
8b8d654b TI |
2247 | return 0; |
2248 | } | |
2249 | ||
2250 | static int generic_hdmi_init(struct hda_codec *codec) | |
2251 | { | |
2252 | struct hdmi_spec *spec = codec->spec; | |
2253 | int pin_idx; | |
2254 | ||
302d5a80 | 2255 | mutex_lock(&spec->bind_lock); |
ade49db3 | 2256 | spec->use_jack_detect = !codec->jackpoll_interval; |
8b8d654b | 2257 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { |
bce0d2a8 | 2258 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); |
8b8d654b | 2259 | hda_nid_t pin_nid = per_pin->pin_nid; |
9152085d | 2260 | int dev_id = per_pin->dev_id; |
8b8d654b | 2261 | |
9152085d | 2262 | snd_hda_set_dev_select(codec, pin_nid, dev_id); |
8b8d654b | 2263 | hdmi_init_pin(codec, pin_nid); |
ade49db3 TI |
2264 | if (codec_has_acomp(codec)) |
2265 | continue; | |
2266 | if (spec->use_jack_detect) | |
2267 | snd_hda_jack_detect_enable(codec, pin_nid); | |
2268 | else | |
788d441a | 2269 | snd_hda_jack_detect_enable_callback(codec, pin_nid, |
ade49db3 | 2270 | jack_callback); |
8b8d654b | 2271 | } |
302d5a80 | 2272 | mutex_unlock(&spec->bind_lock); |
84eb01be TI |
2273 | return 0; |
2274 | } | |
2275 | ||
bce0d2a8 TI |
2276 | static void hdmi_array_init(struct hdmi_spec *spec, int nums) |
2277 | { | |
2278 | snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums); | |
2279 | snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums); | |
bce0d2a8 TI |
2280 | } |
2281 | ||
2282 | static void hdmi_array_free(struct hdmi_spec *spec) | |
2283 | { | |
2284 | snd_array_free(&spec->pins); | |
2285 | snd_array_free(&spec->cvts); | |
bce0d2a8 TI |
2286 | } |
2287 | ||
a686632f TI |
2288 | static void generic_spec_free(struct hda_codec *codec) |
2289 | { | |
2290 | struct hdmi_spec *spec = codec->spec; | |
2291 | ||
2292 | if (spec) { | |
2293 | hdmi_array_free(spec); | |
2294 | kfree(spec); | |
2295 | codec->spec = NULL; | |
2296 | } | |
2297 | codec->dp_mst = false; | |
2298 | } | |
2299 | ||
84eb01be TI |
2300 | static void generic_hdmi_free(struct hda_codec *codec) |
2301 | { | |
2302 | struct hdmi_spec *spec = codec->spec; | |
25e4abb3 | 2303 | int pin_idx, pcm_idx; |
384a48d7 | 2304 | |
ade49db3 TI |
2305 | if (spec->acomp_registered) { |
2306 | snd_hdac_acomp_exit(&codec->bus->core); | |
2307 | } else if (codec_has_acomp(codec)) { | |
a57942bf | 2308 | snd_hdac_acomp_register_notifier(&codec->bus->core, NULL); |
4914da2f TI |
2309 | codec->relaxed_resume = 0; |
2310 | } | |
25adc137 | 2311 | |
384a48d7 | 2312 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { |
bce0d2a8 | 2313 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); |
2f35c630 | 2314 | cancel_delayed_work_sync(&per_pin->work); |
a4e9a38b | 2315 | eld_proc_free(per_pin); |
25e4abb3 LY |
2316 | } |
2317 | ||
2318 | for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { | |
2319 | if (spec->pcm_rec[pcm_idx].jack == NULL) | |
2320 | continue; | |
2321 | if (spec->dyn_pcm_assign) | |
2322 | snd_device_free(codec->card, | |
2323 | spec->pcm_rec[pcm_idx].jack); | |
2324 | else | |
2325 | spec->pcm_rec[pcm_idx].jack = NULL; | |
384a48d7 | 2326 | } |
84eb01be | 2327 | |
a686632f | 2328 | generic_spec_free(codec); |
84eb01be TI |
2329 | } |
2330 | ||
28cb72e5 WX |
2331 | #ifdef CONFIG_PM |
2332 | static int generic_hdmi_resume(struct hda_codec *codec) | |
2333 | { | |
2334 | struct hdmi_spec *spec = codec->spec; | |
2335 | int pin_idx; | |
2336 | ||
a2833683 | 2337 | codec->patch_ops.init(codec); |
eeecd9d1 | 2338 | regcache_sync(codec->core.regmap); |
28cb72e5 WX |
2339 | |
2340 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { | |
2341 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); | |
2342 | hdmi_present_sense(per_pin, 1); | |
2343 | } | |
2344 | return 0; | |
2345 | } | |
2346 | #endif | |
2347 | ||
fb79e1e0 | 2348 | static const struct hda_codec_ops generic_hdmi_patch_ops = { |
84eb01be TI |
2349 | .init = generic_hdmi_init, |
2350 | .free = generic_hdmi_free, | |
2351 | .build_pcms = generic_hdmi_build_pcms, | |
2352 | .build_controls = generic_hdmi_build_controls, | |
2353 | .unsol_event = hdmi_unsol_event, | |
28cb72e5 WX |
2354 | #ifdef CONFIG_PM |
2355 | .resume = generic_hdmi_resume, | |
2356 | #endif | |
84eb01be TI |
2357 | }; |
2358 | ||
307229d2 AH |
2359 | static const struct hdmi_ops generic_standard_hdmi_ops = { |
2360 | .pin_get_eld = snd_hdmi_get_eld, | |
307229d2 AH |
2361 | .pin_setup_infoframe = hdmi_pin_setup_infoframe, |
2362 | .pin_hbr_setup = hdmi_pin_hbr_setup, | |
2363 | .setup_stream = hdmi_setup_stream, | |
67b90cb8 SP |
2364 | }; |
2365 | ||
a686632f TI |
2366 | /* allocate codec->spec and assign/initialize generic parser ops */ |
2367 | static int alloc_generic_hdmi(struct hda_codec *codec) | |
2368 | { | |
2369 | struct hdmi_spec *spec; | |
2370 | ||
2371 | spec = kzalloc(sizeof(*spec), GFP_KERNEL); | |
2372 | if (!spec) | |
2373 | return -ENOMEM; | |
2374 | ||
ade49db3 | 2375 | spec->codec = codec; |
a686632f | 2376 | spec->ops = generic_standard_hdmi_ops; |
9152085d | 2377 | spec->dev_num = 1; /* initialize to 1 */ |
a686632f | 2378 | mutex_init(&spec->pcm_lock); |
302d5a80 | 2379 | mutex_init(&spec->bind_lock); |
a686632f TI |
2380 | snd_hdac_register_chmap_ops(&codec->core, &spec->chmap); |
2381 | ||
2382 | spec->chmap.ops.get_chmap = hdmi_get_chmap; | |
2383 | spec->chmap.ops.set_chmap = hdmi_set_chmap; | |
2384 | spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached; | |
44fde3b8 | 2385 | spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc, |
a686632f TI |
2386 | |
2387 | codec->spec = spec; | |
2388 | hdmi_array_init(spec, 4); | |
2389 | ||
2390 | codec->patch_ops = generic_hdmi_patch_ops; | |
2391 | ||
2392 | return 0; | |
2393 | } | |
2394 | ||
2395 | /* generic HDMI parser */ | |
2396 | static int patch_generic_hdmi(struct hda_codec *codec) | |
2397 | { | |
2398 | int err; | |
2399 | ||
2400 | err = alloc_generic_hdmi(codec); | |
2401 | if (err < 0) | |
2402 | return err; | |
2403 | ||
2404 | err = hdmi_parse_codec(codec); | |
2405 | if (err < 0) { | |
2406 | generic_spec_free(codec); | |
2407 | return err; | |
2408 | } | |
2409 | ||
2410 | generic_hdmi_init_per_pins(codec); | |
2411 | return 0; | |
2412 | } | |
2413 | ||
ade49db3 TI |
2414 | /* |
2415 | * generic audio component binding | |
2416 | */ | |
2417 | ||
2418 | /* turn on / off the unsol event jack detection dynamically */ | |
2419 | static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid, | |
2420 | bool use_acomp) | |
2421 | { | |
2422 | struct hda_jack_tbl *tbl; | |
2423 | ||
2424 | tbl = snd_hda_jack_tbl_get(codec, nid); | |
2425 | if (tbl) { | |
2426 | /* clear unsol even if component notifier is used, or re-enable | |
2427 | * if notifier is cleared | |
2428 | */ | |
2429 | unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag); | |
2430 | snd_hda_codec_write_cache(codec, nid, 0, | |
2431 | AC_VERB_SET_UNSOLICITED_ENABLE, val); | |
2432 | } else { | |
2433 | /* if no jack entry was defined beforehand, create a new one | |
2434 | * at need (i.e. only when notifier is cleared) | |
2435 | */ | |
2436 | if (!use_acomp) | |
2437 | snd_hda_jack_detect_enable(codec, nid); | |
2438 | } | |
2439 | } | |
2440 | ||
2441 | /* set up / clear component notifier dynamically */ | |
2442 | static void generic_acomp_notifier_set(struct drm_audio_component *acomp, | |
2443 | bool use_acomp) | |
2444 | { | |
2445 | struct hdmi_spec *spec; | |
2446 | int i; | |
2447 | ||
2448 | spec = container_of(acomp->audio_ops, struct hdmi_spec, drm_audio_ops); | |
302d5a80 | 2449 | mutex_lock(&spec->bind_lock); |
ade49db3 TI |
2450 | spec->use_acomp_notifier = use_acomp; |
2451 | spec->codec->relaxed_resume = use_acomp; | |
2452 | /* reprogram each jack detection logic depending on the notifier */ | |
2453 | if (spec->use_jack_detect) { | |
2454 | for (i = 0; i < spec->num_pins; i++) | |
2455 | reprogram_jack_detect(spec->codec, | |
2456 | get_pin(spec, i)->pin_nid, | |
2457 | use_acomp); | |
2458 | } | |
302d5a80 | 2459 | mutex_unlock(&spec->bind_lock); |
ade49db3 TI |
2460 | } |
2461 | ||
2462 | /* enable / disable the notifier via master bind / unbind */ | |
2463 | static int generic_acomp_master_bind(struct device *dev, | |
2464 | struct drm_audio_component *acomp) | |
2465 | { | |
2466 | generic_acomp_notifier_set(acomp, true); | |
2467 | return 0; | |
2468 | } | |
2469 | ||
2470 | static void generic_acomp_master_unbind(struct device *dev, | |
2471 | struct drm_audio_component *acomp) | |
2472 | { | |
2473 | generic_acomp_notifier_set(acomp, false); | |
2474 | } | |
2475 | ||
2476 | /* check whether both HD-audio and DRM PCI devices belong to the same bus */ | |
2477 | static int match_bound_vga(struct device *dev, int subtype, void *data) | |
2478 | { | |
2479 | struct hdac_bus *bus = data; | |
2480 | struct pci_dev *pci, *master; | |
2481 | ||
2482 | if (!dev_is_pci(dev) || !dev_is_pci(bus->dev)) | |
2483 | return 0; | |
2484 | master = to_pci_dev(bus->dev); | |
2485 | pci = to_pci_dev(dev); | |
2486 | return master->bus == pci->bus; | |
2487 | } | |
2488 | ||
2489 | /* audio component notifier for AMD/Nvidia HDMI codecs */ | |
2490 | static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id) | |
2491 | { | |
2492 | struct hda_codec *codec = audio_ptr; | |
2493 | struct hdmi_spec *spec = codec->spec; | |
2494 | hda_nid_t pin_nid = spec->port2pin(codec, port); | |
2495 | ||
2496 | if (!pin_nid) | |
2497 | return; | |
2498 | if (get_wcaps_type(get_wcaps(codec, pin_nid)) != AC_WID_PIN) | |
2499 | return; | |
2500 | /* skip notification during system suspend (but not in runtime PM); | |
2501 | * the state will be updated at resume | |
2502 | */ | |
2503 | if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0) | |
2504 | return; | |
2505 | /* ditto during suspend/resume process itself */ | |
2506 | if (snd_hdac_is_in_pm(&codec->core)) | |
2507 | return; | |
2508 | ||
2509 | check_presence_and_report(codec, pin_nid, dev_id); | |
2510 | } | |
2511 | ||
2512 | /* set up the private drm_audio_ops from the template */ | |
2513 | static void setup_drm_audio_ops(struct hda_codec *codec, | |
2514 | const struct drm_audio_component_audio_ops *ops) | |
2515 | { | |
2516 | struct hdmi_spec *spec = codec->spec; | |
2517 | ||
2518 | spec->drm_audio_ops.audio_ptr = codec; | |
2519 | /* intel_audio_codec_enable() or intel_audio_codec_disable() | |
2520 | * will call pin_eld_notify with using audio_ptr pointer | |
2521 | * We need make sure audio_ptr is really setup | |
2522 | */ | |
2523 | wmb(); | |
2524 | spec->drm_audio_ops.pin2port = ops->pin2port; | |
2525 | spec->drm_audio_ops.pin_eld_notify = ops->pin_eld_notify; | |
2526 | spec->drm_audio_ops.master_bind = ops->master_bind; | |
2527 | spec->drm_audio_ops.master_unbind = ops->master_unbind; | |
2528 | } | |
2529 | ||
2530 | /* initialize the generic HDMI audio component */ | |
2531 | static void generic_acomp_init(struct hda_codec *codec, | |
2532 | const struct drm_audio_component_audio_ops *ops, | |
2533 | int (*port2pin)(struct hda_codec *, int)) | |
2534 | { | |
2535 | struct hdmi_spec *spec = codec->spec; | |
2536 | ||
2537 | spec->port2pin = port2pin; | |
2538 | setup_drm_audio_ops(codec, ops); | |
2539 | if (!snd_hdac_acomp_init(&codec->bus->core, &spec->drm_audio_ops, | |
dd23e1d5 | 2540 | match_bound_vga, 0)) { |
ade49db3 | 2541 | spec->acomp_registered = true; |
dd23e1d5 TI |
2542 | codec->bus->keep_power = 0; |
2543 | } | |
ade49db3 TI |
2544 | } |
2545 | ||
a686632f TI |
2546 | /* |
2547 | * Intel codec parsers and helpers | |
2548 | */ | |
2549 | ||
c88d4e84 TI |
2550 | static void intel_haswell_fixup_connect_list(struct hda_codec *codec, |
2551 | hda_nid_t nid) | |
2552 | { | |
2553 | struct hdmi_spec *spec = codec->spec; | |
2554 | hda_nid_t conns[4]; | |
2555 | int nconns; | |
6ffe168f | 2556 | |
c88d4e84 TI |
2557 | nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns)); |
2558 | if (nconns == spec->num_cvts && | |
2559 | !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t))) | |
6ffe168f ML |
2560 | return; |
2561 | ||
c88d4e84 | 2562 | /* override pins connection list */ |
4e76a883 | 2563 | codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid); |
c88d4e84 | 2564 | snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids); |
6ffe168f ML |
2565 | } |
2566 | ||
b0d8bc50 JK |
2567 | #define INTEL_GET_VENDOR_VERB 0xf81 |
2568 | #define INTEL_SET_VENDOR_VERB 0x781 | |
2569 | #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */ | |
2570 | #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */ | |
1611a9c9 ML |
2571 | |
2572 | static void intel_haswell_enable_all_pins(struct hda_codec *codec, | |
17df3f55 | 2573 | bool update_tree) |
1611a9c9 ML |
2574 | { |
2575 | unsigned int vendor_param; | |
a87a4d23 | 2576 | struct hdmi_spec *spec = codec->spec; |
1611a9c9 | 2577 | |
a87a4d23 | 2578 | vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, |
1611a9c9 ML |
2579 | INTEL_GET_VENDOR_VERB, 0); |
2580 | if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS) | |
2581 | return; | |
2582 | ||
2583 | vendor_param |= INTEL_EN_ALL_PIN_CVTS; | |
a87a4d23 | 2584 | vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, |
1611a9c9 ML |
2585 | INTEL_SET_VENDOR_VERB, vendor_param); |
2586 | if (vendor_param == -1) | |
2587 | return; | |
2588 | ||
17df3f55 TI |
2589 | if (update_tree) |
2590 | snd_hda_codec_update_widgets(codec); | |
1611a9c9 ML |
2591 | } |
2592 | ||
c88d4e84 TI |
2593 | static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec) |
2594 | { | |
2595 | unsigned int vendor_param; | |
a87a4d23 | 2596 | struct hdmi_spec *spec = codec->spec; |
c88d4e84 | 2597 | |
a87a4d23 | 2598 | vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, |
c88d4e84 TI |
2599 | INTEL_GET_VENDOR_VERB, 0); |
2600 | if (vendor_param == -1 || vendor_param & INTEL_EN_DP12) | |
2601 | return; | |
2602 | ||
2603 | /* enable DP1.2 mode */ | |
2604 | vendor_param |= INTEL_EN_DP12; | |
a551d914 | 2605 | snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB); |
a87a4d23 | 2606 | snd_hda_codec_write_cache(codec, spec->vendor_nid, 0, |
c88d4e84 TI |
2607 | INTEL_SET_VENDOR_VERB, vendor_param); |
2608 | } | |
2609 | ||
17df3f55 TI |
2610 | /* Haswell needs to re-issue the vendor-specific verbs before turning to D0. |
2611 | * Otherwise you may get severe h/w communication errors. | |
2612 | */ | |
2613 | static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg, | |
2614 | unsigned int power_state) | |
2615 | { | |
2616 | if (power_state == AC_PWRST_D0) { | |
2617 | intel_haswell_enable_all_pins(codec, false); | |
2618 | intel_haswell_fixup_enable_dp12(codec); | |
2619 | } | |
c88d4e84 | 2620 | |
17df3f55 TI |
2621 | snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state); |
2622 | snd_hda_codec_set_power_to_all(codec, fg, power_state); | |
2623 | } | |
6ffe168f | 2624 | |
a57942bf TI |
2625 | /* There is a fixed mapping between audio pin node and display port. |
2626 | * on SNB, IVY, HSW, BSW, SKL, BXT, KBL: | |
2627 | * Pin Widget 5 - PORT B (port = 1 in i915 driver) | |
2628 | * Pin Widget 6 - PORT C (port = 2 in i915 driver) | |
2629 | * Pin Widget 7 - PORT D (port = 3 in i915 driver) | |
2630 | * | |
2631 | * on VLV, ILK: | |
2632 | * Pin Widget 4 - PORT B (port = 1 in i915 driver) | |
2633 | * Pin Widget 5 - PORT C (port = 2 in i915 driver) | |
2634 | * Pin Widget 6 - PORT D (port = 3 in i915 driver) | |
2635 | */ | |
2636 | static int intel_base_nid(struct hda_codec *codec) | |
2637 | { | |
2638 | switch (codec->core.vendor_id) { | |
2639 | case 0x80860054: /* ILK */ | |
2640 | case 0x80862804: /* ILK */ | |
2641 | case 0x80862882: /* VLV */ | |
2642 | return 4; | |
2643 | default: | |
2644 | return 5; | |
2645 | } | |
2646 | } | |
2647 | ||
2648 | static int intel_pin2port(void *audio_ptr, int pin_nid) | |
2649 | { | |
b0d8bc50 JK |
2650 | struct hda_codec *codec = audio_ptr; |
2651 | struct hdmi_spec *spec = codec->spec; | |
2652 | int base_nid, i; | |
a57942bf | 2653 | |
b0d8bc50 JK |
2654 | if (!spec->port_num) { |
2655 | base_nid = intel_base_nid(codec); | |
2656 | if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3)) | |
2657 | return -1; | |
c8e3eb9b | 2658 | return pin_nid - base_nid + 1; |
b0d8bc50 JK |
2659 | } |
2660 | ||
2661 | /* | |
2662 | * looking for the pin number in the mapping table and return | |
2663 | * the index which indicate the port number | |
2664 | */ | |
2665 | for (i = 0; i < spec->port_num; i++) { | |
2666 | if (pin_nid == spec->port_map[i]) | |
d577cf76 | 2667 | return i; |
b0d8bc50 JK |
2668 | } |
2669 | ||
b0d8bc50 JK |
2670 | codec_info(codec, "Can't find the HDMI/DP port for pin %d\n", pin_nid); |
2671 | return -1; | |
a57942bf TI |
2672 | } |
2673 | ||
3140aafb TI |
2674 | static int intel_port2pin(struct hda_codec *codec, int port) |
2675 | { | |
2676 | struct hdmi_spec *spec = codec->spec; | |
2677 | ||
2678 | if (!spec->port_num) { | |
2679 | /* we assume only from port-B to port-D */ | |
2680 | if (port < 1 || port > 3) | |
2681 | return 0; | |
3140aafb TI |
2682 | return port + intel_base_nid(codec) - 1; |
2683 | } | |
2684 | ||
d577cf76 | 2685 | if (port < 0 || port >= spec->port_num) |
3140aafb | 2686 | return 0; |
d577cf76 | 2687 | return spec->port_map[port]; |
3140aafb TI |
2688 | } |
2689 | ||
f9318941 | 2690 | static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe) |
25adc137 DH |
2691 | { |
2692 | struct hda_codec *codec = audio_ptr; | |
7ff652ff | 2693 | int pin_nid; |
9152085d | 2694 | int dev_id = pipe; |
25adc137 | 2695 | |
3140aafb TI |
2696 | pin_nid = intel_port2pin(codec, port); |
2697 | if (!pin_nid) | |
4f8e4f35 | 2698 | return; |
8ae743e8 TI |
2699 | /* skip notification during system suspend (but not in runtime PM); |
2700 | * the state will be updated at resume | |
2701 | */ | |
2702 | if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0) | |
2703 | return; | |
eb399d3c | 2704 | /* ditto during suspend/resume process itself */ |
feb20fae | 2705 | if (snd_hdac_is_in_pm(&codec->core)) |
eb399d3c | 2706 | return; |
8ae743e8 | 2707 | |
bb03ed21 | 2708 | snd_hdac_i915_set_bclk(&codec->bus->core); |
9152085d | 2709 | check_presence_and_report(codec, pin_nid, dev_id); |
25adc137 DH |
2710 | } |
2711 | ||
ade49db3 TI |
2712 | static const struct drm_audio_component_audio_ops intel_audio_ops = { |
2713 | .pin2port = intel_pin2port, | |
2714 | .pin_eld_notify = intel_pin_eld_notify, | |
2715 | }; | |
2716 | ||
a686632f TI |
2717 | /* register i915 component pin_eld_notify callback */ |
2718 | static void register_i915_notifier(struct hda_codec *codec) | |
84eb01be | 2719 | { |
a686632f | 2720 | struct hdmi_spec *spec = codec->spec; |
84eb01be | 2721 | |
a686632f | 2722 | spec->use_acomp_notifier = true; |
ade49db3 TI |
2723 | spec->port2pin = intel_port2pin; |
2724 | setup_drm_audio_ops(codec, &intel_audio_ops); | |
a57942bf | 2725 | snd_hdac_acomp_register_notifier(&codec->bus->core, |
82887c0b | 2726 | &spec->drm_audio_ops); |
4914da2f TI |
2727 | /* no need for forcible resume for jack check thanks to notifier */ |
2728 | codec->relaxed_resume = 1; | |
a686632f | 2729 | } |
84eb01be | 2730 | |
2c1c9b86 TI |
2731 | /* setup_stream ops override for HSW+ */ |
2732 | static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, | |
2733 | hda_nid_t pin_nid, u32 stream_tag, int format) | |
2734 | { | |
2735 | haswell_verify_D0(codec, cvt_nid, pin_nid); | |
2736 | return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format); | |
2737 | } | |
739ffee9 | 2738 | |
4846a67e TI |
2739 | /* pin_cvt_fixup ops override for HSW+ and VLV+ */ |
2740 | static void i915_pin_cvt_fixup(struct hda_codec *codec, | |
2741 | struct hdmi_spec_per_pin *per_pin, | |
2742 | hda_nid_t cvt_nid) | |
2743 | { | |
2744 | if (per_pin) { | |
9152085d LY |
2745 | snd_hda_set_dev_select(codec, per_pin->pin_nid, |
2746 | per_pin->dev_id); | |
4846a67e TI |
2747 | intel_verify_pin_cvt_connect(codec, per_pin); |
2748 | intel_not_share_assigned_cvt(codec, per_pin->pin_nid, | |
9152085d | 2749 | per_pin->dev_id, per_pin->mux_idx); |
4846a67e | 2750 | } else { |
9152085d | 2751 | intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid); |
4846a67e TI |
2752 | } |
2753 | } | |
739ffee9 | 2754 | |
43f6c8d9 TI |
2755 | /* precondition and allocation for Intel codecs */ |
2756 | static int alloc_intel_hdmi(struct hda_codec *codec) | |
a686632f | 2757 | { |
f2dbe87c TI |
2758 | int err; |
2759 | ||
43f6c8d9 | 2760 | /* requires i915 binding */ |
a686632f TI |
2761 | if (!codec->bus->core.audio_component) { |
2762 | codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n"); | |
fdd49c51 TI |
2763 | /* set probe_id here to prevent generic fallback binding */ |
2764 | codec->probe_id = HDA_CODEC_ID_SKIP_PROBE; | |
a686632f | 2765 | return -ENODEV; |
691be973 | 2766 | } |
55913110 | 2767 | |
f2dbe87c TI |
2768 | err = alloc_generic_hdmi(codec); |
2769 | if (err < 0) | |
2770 | return err; | |
2771 | /* no need to handle unsol events */ | |
2772 | codec->patch_ops.unsol_event = NULL; | |
2773 | return 0; | |
43f6c8d9 TI |
2774 | } |
2775 | ||
2776 | /* parse and post-process for Intel codecs */ | |
2777 | static int parse_intel_hdmi(struct hda_codec *codec) | |
2778 | { | |
2779 | int err; | |
2780 | ||
2781 | err = hdmi_parse_codec(codec); | |
2782 | if (err < 0) { | |
2783 | generic_spec_free(codec); | |
2784 | return err; | |
2785 | } | |
2786 | ||
2787 | generic_hdmi_init_per_pins(codec); | |
2788 | register_i915_notifier(codec); | |
2789 | return 0; | |
2790 | } | |
2791 | ||
2792 | /* Intel Haswell and onwards; audio component with eld notifier */ | |
b0d8bc50 JK |
2793 | static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid, |
2794 | const int *port_map, int port_num) | |
43f6c8d9 TI |
2795 | { |
2796 | struct hdmi_spec *spec; | |
2797 | int err; | |
2798 | ||
2799 | err = alloc_intel_hdmi(codec); | |
a686632f TI |
2800 | if (err < 0) |
2801 | return err; | |
2802 | spec = codec->spec; | |
9152085d LY |
2803 | codec->dp_mst = true; |
2804 | spec->dyn_pcm_assign = true; | |
a87a4d23 | 2805 | spec->vendor_nid = vendor_nid; |
b0d8bc50 JK |
2806 | spec->port_map = port_map; |
2807 | spec->port_num = port_num; | |
cb45722b | 2808 | spec->intel_hsw_fixup = true; |
6ffe168f | 2809 | |
a686632f TI |
2810 | intel_haswell_enable_all_pins(codec, true); |
2811 | intel_haswell_fixup_enable_dp12(codec); | |
2812 | ||
46594d33 | 2813 | codec->display_power_control = 1; |
2bd1f73f | 2814 | |
a686632f | 2815 | codec->patch_ops.set_power_state = haswell_set_power_state; |
a686632f TI |
2816 | codec->depop_delay = 0; |
2817 | codec->auto_runtime_pm = 1; | |
2818 | ||
2c1c9b86 | 2819 | spec->ops.setup_stream = i915_hsw_setup_stream; |
4846a67e | 2820 | spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; |
2c1c9b86 | 2821 | |
43f6c8d9 | 2822 | return parse_intel_hdmi(codec); |
a686632f TI |
2823 | } |
2824 | ||
a87a4d23 ACDO |
2825 | static int patch_i915_hsw_hdmi(struct hda_codec *codec) |
2826 | { | |
b0d8bc50 | 2827 | return intel_hsw_common_init(codec, 0x08, NULL, 0); |
a87a4d23 ACDO |
2828 | } |
2829 | ||
2830 | static int patch_i915_glk_hdmi(struct hda_codec *codec) | |
2831 | { | |
b0d8bc50 JK |
2832 | return intel_hsw_common_init(codec, 0x0b, NULL, 0); |
2833 | } | |
2834 | ||
2835 | static int patch_i915_icl_hdmi(struct hda_codec *codec) | |
2836 | { | |
2837 | /* | |
2838 | * pin to port mapping table where the value indicate the pin number and | |
d577cf76 | 2839 | * the index indicate the port number. |
b0d8bc50 | 2840 | */ |
d577cf76 | 2841 | static const int map[] = {0x0, 0x4, 0x6, 0x8, 0xa, 0xb}; |
b0d8bc50 JK |
2842 | |
2843 | return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map)); | |
a87a4d23 ACDO |
2844 | } |
2845 | ||
9a11ba73 KV |
2846 | static int patch_i915_tgl_hdmi(struct hda_codec *codec) |
2847 | { | |
2848 | /* | |
2849 | * pin to port mapping table where the value indicate the pin number and | |
d577cf76 | 2850 | * the index indicate the port number. |
9a11ba73 KV |
2851 | */ |
2852 | static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf}; | |
2853 | ||
2854 | return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map)); | |
2855 | } | |
2856 | ||
7ff652ff | 2857 | /* Intel Baytrail and Braswell; with eld notifier */ |
a686632f TI |
2858 | static int patch_i915_byt_hdmi(struct hda_codec *codec) |
2859 | { | |
2860 | struct hdmi_spec *spec; | |
2861 | int err; | |
2862 | ||
43f6c8d9 | 2863 | err = alloc_intel_hdmi(codec); |
a686632f TI |
2864 | if (err < 0) |
2865 | return err; | |
2866 | spec = codec->spec; | |
2377c3c3 | 2867 | |
a686632f TI |
2868 | /* For Valleyview/Cherryview, only the display codec is in the display |
2869 | * power well and can use link_power ops to request/release the power. | |
2870 | */ | |
029d92c2 | 2871 | codec->display_power_control = 1; |
84eb01be | 2872 | |
a686632f TI |
2873 | codec->depop_delay = 0; |
2874 | codec->auto_runtime_pm = 1; | |
84eb01be | 2875 | |
4846a67e TI |
2876 | spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; |
2877 | ||
43f6c8d9 | 2878 | return parse_intel_hdmi(codec); |
84eb01be TI |
2879 | } |
2880 | ||
7ff652ff | 2881 | /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */ |
e85015a3 TI |
2882 | static int patch_i915_cpt_hdmi(struct hda_codec *codec) |
2883 | { | |
e85015a3 TI |
2884 | int err; |
2885 | ||
43f6c8d9 | 2886 | err = alloc_intel_hdmi(codec); |
e85015a3 TI |
2887 | if (err < 0) |
2888 | return err; | |
43f6c8d9 | 2889 | return parse_intel_hdmi(codec); |
84eb01be TI |
2890 | } |
2891 | ||
3aaf8980 SW |
2892 | /* |
2893 | * Shared non-generic implementations | |
2894 | */ | |
2895 | ||
2896 | static int simple_playback_build_pcms(struct hda_codec *codec) | |
2897 | { | |
2898 | struct hdmi_spec *spec = codec->spec; | |
bce0d2a8 | 2899 | struct hda_pcm *info; |
8ceb332d TI |
2900 | unsigned int chans; |
2901 | struct hda_pcm_stream *pstr; | |
bce0d2a8 | 2902 | struct hdmi_spec_per_cvt *per_cvt; |
3aaf8980 | 2903 | |
bce0d2a8 TI |
2904 | per_cvt = get_cvt(spec, 0); |
2905 | chans = get_wcaps(codec, per_cvt->cvt_nid); | |
8ceb332d | 2906 | chans = get_wcaps_channels(chans); |
3aaf8980 | 2907 | |
bbbc7e85 | 2908 | info = snd_hda_codec_pcm_new(codec, "HDMI 0"); |
bce0d2a8 TI |
2909 | if (!info) |
2910 | return -ENOMEM; | |
2bea241a | 2911 | spec->pcm_rec[0].pcm = info; |
8ceb332d TI |
2912 | info->pcm_type = HDA_PCM_TYPE_HDMI; |
2913 | pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; | |
2914 | *pstr = spec->pcm_playback; | |
bce0d2a8 | 2915 | pstr->nid = per_cvt->cvt_nid; |
8ceb332d TI |
2916 | if (pstr->channels_max <= 2 && chans && chans <= 16) |
2917 | pstr->channels_max = chans; | |
3aaf8980 SW |
2918 | |
2919 | return 0; | |
2920 | } | |
2921 | ||
4b6ace9e TI |
2922 | /* unsolicited event for jack sensing */ |
2923 | static void simple_hdmi_unsol_event(struct hda_codec *codec, | |
2924 | unsigned int res) | |
2925 | { | |
9dd8cf12 | 2926 | snd_hda_jack_set_dirty_all(codec); |
4b6ace9e TI |
2927 | snd_hda_jack_report_sync(codec); |
2928 | } | |
2929 | ||
2930 | /* generic_hdmi_build_jack can be used for simple_hdmi, too, | |
2931 | * as long as spec->pins[] is set correctly | |
2932 | */ | |
2933 | #define simple_hdmi_build_jack generic_hdmi_build_jack | |
2934 | ||
3aaf8980 SW |
2935 | static int simple_playback_build_controls(struct hda_codec *codec) |
2936 | { | |
2937 | struct hdmi_spec *spec = codec->spec; | |
bce0d2a8 | 2938 | struct hdmi_spec_per_cvt *per_cvt; |
3aaf8980 | 2939 | int err; |
3aaf8980 | 2940 | |
bce0d2a8 | 2941 | per_cvt = get_cvt(spec, 0); |
c9a6338a AH |
2942 | err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid, |
2943 | per_cvt->cvt_nid, | |
2944 | HDA_PCM_TYPE_HDMI); | |
8ceb332d TI |
2945 | if (err < 0) |
2946 | return err; | |
2947 | return simple_hdmi_build_jack(codec, 0); | |
3aaf8980 SW |
2948 | } |
2949 | ||
4f0110ce TI |
2950 | static int simple_playback_init(struct hda_codec *codec) |
2951 | { | |
2952 | struct hdmi_spec *spec = codec->spec; | |
bce0d2a8 TI |
2953 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0); |
2954 | hda_nid_t pin = per_pin->pin_nid; | |
8ceb332d TI |
2955 | |
2956 | snd_hda_codec_write(codec, pin, 0, | |
2957 | AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT); | |
2958 | /* some codecs require to unmute the pin */ | |
2959 | if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) | |
2960 | snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE, | |
2961 | AMP_OUT_UNMUTE); | |
62f949bf | 2962 | snd_hda_jack_detect_enable(codec, pin); |
4f0110ce TI |
2963 | return 0; |
2964 | } | |
2965 | ||
3aaf8980 SW |
2966 | static void simple_playback_free(struct hda_codec *codec) |
2967 | { | |
2968 | struct hdmi_spec *spec = codec->spec; | |
2969 | ||
bce0d2a8 | 2970 | hdmi_array_free(spec); |
3aaf8980 SW |
2971 | kfree(spec); |
2972 | } | |
2973 | ||
84eb01be TI |
2974 | /* |
2975 | * Nvidia specific implementations | |
2976 | */ | |
2977 | ||
2978 | #define Nv_VERB_SET_Channel_Allocation 0xF79 | |
2979 | #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A | |
2980 | #define Nv_VERB_SET_Audio_Protection_On 0xF98 | |
2981 | #define Nv_VERB_SET_Audio_Protection_Off 0xF99 | |
2982 | ||
2983 | #define nvhdmi_master_con_nid_7x 0x04 | |
2984 | #define nvhdmi_master_pin_nid_7x 0x05 | |
2985 | ||
fb79e1e0 | 2986 | static const hda_nid_t nvhdmi_con_nids_7x[4] = { |
84eb01be TI |
2987 | /*front, rear, clfe, rear_surr */ |
2988 | 0x6, 0x8, 0xa, 0xc, | |
2989 | }; | |
2990 | ||
ceaa86ba TI |
2991 | static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = { |
2992 | /* set audio protect on */ | |
2993 | { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, | |
2994 | /* enable digital output on pin widget */ | |
2995 | { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, | |
2996 | {} /* terminator */ | |
2997 | }; | |
2998 | ||
2999 | static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = { | |
84eb01be TI |
3000 | /* set audio protect on */ |
3001 | { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, | |
3002 | /* enable digital output on pin widget */ | |
3003 | { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, | |
3004 | { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, | |
3005 | { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, | |
3006 | { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, | |
3007 | { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, | |
3008 | {} /* terminator */ | |
3009 | }; | |
3010 | ||
3011 | #ifdef LIMITED_RATE_FMT_SUPPORT | |
3012 | /* support only the safe format and rate */ | |
3013 | #define SUPPORTED_RATES SNDRV_PCM_RATE_48000 | |
3014 | #define SUPPORTED_MAXBPS 16 | |
3015 | #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE | |
3016 | #else | |
3017 | /* support all rates and formats */ | |
3018 | #define SUPPORTED_RATES \ | |
3019 | (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ | |
3020 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\ | |
3021 | SNDRV_PCM_RATE_192000) | |
3022 | #define SUPPORTED_MAXBPS 24 | |
3023 | #define SUPPORTED_FORMATS \ | |
3024 | (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) | |
3025 | #endif | |
3026 | ||
ceaa86ba TI |
3027 | static int nvhdmi_7x_init_2ch(struct hda_codec *codec) |
3028 | { | |
3029 | snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch); | |
3030 | return 0; | |
3031 | } | |
3032 | ||
3033 | static int nvhdmi_7x_init_8ch(struct hda_codec *codec) | |
84eb01be | 3034 | { |
ceaa86ba | 3035 | snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch); |
84eb01be TI |
3036 | return 0; |
3037 | } | |
3038 | ||
50c697ad | 3039 | static const unsigned int channels_2_6_8[] = { |
393004b2 ND |
3040 | 2, 6, 8 |
3041 | }; | |
3042 | ||
50c697ad | 3043 | static const unsigned int channels_2_8[] = { |
393004b2 ND |
3044 | 2, 8 |
3045 | }; | |
3046 | ||
50c697ad | 3047 | static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = { |
393004b2 ND |
3048 | .count = ARRAY_SIZE(channels_2_6_8), |
3049 | .list = channels_2_6_8, | |
3050 | .mask = 0, | |
3051 | }; | |
3052 | ||
50c697ad | 3053 | static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = { |
393004b2 ND |
3054 | .count = ARRAY_SIZE(channels_2_8), |
3055 | .list = channels_2_8, | |
3056 | .mask = 0, | |
3057 | }; | |
3058 | ||
84eb01be TI |
3059 | static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo, |
3060 | struct hda_codec *codec, | |
3061 | struct snd_pcm_substream *substream) | |
3062 | { | |
3063 | struct hdmi_spec *spec = codec->spec; | |
50c697ad | 3064 | const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL; |
393004b2 | 3065 | |
b9a94a9c | 3066 | switch (codec->preset->vendor_id) { |
393004b2 ND |
3067 | case 0x10de0002: |
3068 | case 0x10de0003: | |
3069 | case 0x10de0005: | |
3070 | case 0x10de0006: | |
3071 | hw_constraints_channels = &hw_constraints_2_8_channels; | |
3072 | break; | |
3073 | case 0x10de0007: | |
3074 | hw_constraints_channels = &hw_constraints_2_6_8_channels; | |
3075 | break; | |
3076 | default: | |
3077 | break; | |
3078 | } | |
3079 | ||
3080 | if (hw_constraints_channels != NULL) { | |
3081 | snd_pcm_hw_constraint_list(substream->runtime, 0, | |
3082 | SNDRV_PCM_HW_PARAM_CHANNELS, | |
3083 | hw_constraints_channels); | |
ad09fc9d TI |
3084 | } else { |
3085 | snd_pcm_hw_constraint_step(substream->runtime, 0, | |
3086 | SNDRV_PCM_HW_PARAM_CHANNELS, 2); | |
393004b2 ND |
3087 | } |
3088 | ||
84eb01be TI |
3089 | return snd_hda_multi_out_dig_open(codec, &spec->multiout); |
3090 | } | |
3091 | ||
3092 | static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo, | |
3093 | struct hda_codec *codec, | |
3094 | struct snd_pcm_substream *substream) | |
3095 | { | |
3096 | struct hdmi_spec *spec = codec->spec; | |
3097 | return snd_hda_multi_out_dig_close(codec, &spec->multiout); | |
3098 | } | |
3099 | ||
3100 | static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo, | |
3101 | struct hda_codec *codec, | |
3102 | unsigned int stream_tag, | |
3103 | unsigned int format, | |
3104 | struct snd_pcm_substream *substream) | |
3105 | { | |
3106 | struct hdmi_spec *spec = codec->spec; | |
3107 | return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, | |
3108 | stream_tag, format, substream); | |
3109 | } | |
3110 | ||
d0b1252d TI |
3111 | static const struct hda_pcm_stream simple_pcm_playback = { |
3112 | .substreams = 1, | |
3113 | .channels_min = 2, | |
3114 | .channels_max = 2, | |
3115 | .ops = { | |
3116 | .open = simple_playback_pcm_open, | |
3117 | .close = simple_playback_pcm_close, | |
3118 | .prepare = simple_playback_pcm_prepare | |
3119 | }, | |
3120 | }; | |
3121 | ||
3122 | static const struct hda_codec_ops simple_hdmi_patch_ops = { | |
3123 | .build_controls = simple_playback_build_controls, | |
3124 | .build_pcms = simple_playback_build_pcms, | |
3125 | .init = simple_playback_init, | |
3126 | .free = simple_playback_free, | |
250e41ac | 3127 | .unsol_event = simple_hdmi_unsol_event, |
d0b1252d TI |
3128 | }; |
3129 | ||
3130 | static int patch_simple_hdmi(struct hda_codec *codec, | |
3131 | hda_nid_t cvt_nid, hda_nid_t pin_nid) | |
3132 | { | |
3133 | struct hdmi_spec *spec; | |
bce0d2a8 TI |
3134 | struct hdmi_spec_per_cvt *per_cvt; |
3135 | struct hdmi_spec_per_pin *per_pin; | |
d0b1252d TI |
3136 | |
3137 | spec = kzalloc(sizeof(*spec), GFP_KERNEL); | |
3138 | if (!spec) | |
3139 | return -ENOMEM; | |
3140 | ||
ade49db3 | 3141 | spec->codec = codec; |
d0b1252d | 3142 | codec->spec = spec; |
bce0d2a8 | 3143 | hdmi_array_init(spec, 1); |
d0b1252d TI |
3144 | |
3145 | spec->multiout.num_dacs = 0; /* no analog */ | |
3146 | spec->multiout.max_channels = 2; | |
3147 | spec->multiout.dig_out_nid = cvt_nid; | |
3148 | spec->num_cvts = 1; | |
3149 | spec->num_pins = 1; | |
bce0d2a8 TI |
3150 | per_pin = snd_array_new(&spec->pins); |
3151 | per_cvt = snd_array_new(&spec->cvts); | |
3152 | if (!per_pin || !per_cvt) { | |
3153 | simple_playback_free(codec); | |
3154 | return -ENOMEM; | |
3155 | } | |
3156 | per_cvt->cvt_nid = cvt_nid; | |
3157 | per_pin->pin_nid = pin_nid; | |
d0b1252d TI |
3158 | spec->pcm_playback = simple_pcm_playback; |
3159 | ||
3160 | codec->patch_ops = simple_hdmi_patch_ops; | |
3161 | ||
3162 | return 0; | |
3163 | } | |
3164 | ||
1f348522 AP |
3165 | static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec, |
3166 | int channels) | |
3167 | { | |
3168 | unsigned int chanmask; | |
3169 | int chan = channels ? (channels - 1) : 1; | |
3170 | ||
3171 | switch (channels) { | |
3172 | default: | |
3173 | case 0: | |
3174 | case 2: | |
3175 | chanmask = 0x00; | |
3176 | break; | |
3177 | case 4: | |
3178 | chanmask = 0x08; | |
3179 | break; | |
3180 | case 6: | |
3181 | chanmask = 0x0b; | |
3182 | break; | |
3183 | case 8: | |
3184 | chanmask = 0x13; | |
3185 | break; | |
3186 | } | |
3187 | ||
3188 | /* Set the audio infoframe channel allocation and checksum fields. The | |
3189 | * channel count is computed implicitly by the hardware. */ | |
3190 | snd_hda_codec_write(codec, 0x1, 0, | |
3191 | Nv_VERB_SET_Channel_Allocation, chanmask); | |
3192 | ||
3193 | snd_hda_codec_write(codec, 0x1, 0, | |
3194 | Nv_VERB_SET_Info_Frame_Checksum, | |
3195 | (0x71 - chan - chanmask)); | |
3196 | } | |
3197 | ||
84eb01be TI |
3198 | static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo, |
3199 | struct hda_codec *codec, | |
3200 | struct snd_pcm_substream *substream) | |
3201 | { | |
3202 | struct hdmi_spec *spec = codec->spec; | |
3203 | int i; | |
3204 | ||
3205 | snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, | |
3206 | 0, AC_VERB_SET_CHANNEL_STREAMID, 0); | |
3207 | for (i = 0; i < 4; i++) { | |
3208 | /* set the stream id */ | |
3209 | snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, | |
3210 | AC_VERB_SET_CHANNEL_STREAMID, 0); | |
3211 | /* set the stream format */ | |
3212 | snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, | |
3213 | AC_VERB_SET_STREAM_FORMAT, 0); | |
3214 | } | |
3215 | ||
1f348522 AP |
3216 | /* The audio hardware sends a channel count of 0x7 (8ch) when all the |
3217 | * streams are disabled. */ | |
3218 | nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); | |
3219 | ||
84eb01be TI |
3220 | return snd_hda_multi_out_dig_close(codec, &spec->multiout); |
3221 | } | |
3222 | ||
3223 | static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo, | |
3224 | struct hda_codec *codec, | |
3225 | unsigned int stream_tag, | |
3226 | unsigned int format, | |
3227 | struct snd_pcm_substream *substream) | |
3228 | { | |
3229 | int chs; | |
112daa7a | 3230 | unsigned int dataDCC2, channel_id; |
84eb01be | 3231 | int i; |
7c935976 | 3232 | struct hdmi_spec *spec = codec->spec; |
e3245cdd | 3233 | struct hda_spdif_out *spdif; |
bce0d2a8 | 3234 | struct hdmi_spec_per_cvt *per_cvt; |
84eb01be TI |
3235 | |
3236 | mutex_lock(&codec->spdif_mutex); | |
bce0d2a8 TI |
3237 | per_cvt = get_cvt(spec, 0); |
3238 | spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid); | |
84eb01be TI |
3239 | |
3240 | chs = substream->runtime->channels; | |
84eb01be | 3241 | |
84eb01be TI |
3242 | dataDCC2 = 0x2; |
3243 | ||
84eb01be | 3244 | /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */ |
7c935976 | 3245 | if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) |
84eb01be TI |
3246 | snd_hda_codec_write(codec, |
3247 | nvhdmi_master_con_nid_7x, | |
3248 | 0, | |
3249 | AC_VERB_SET_DIGI_CONVERT_1, | |
7c935976 | 3250 | spdif->ctls & ~AC_DIG1_ENABLE & 0xff); |
84eb01be TI |
3251 | |
3252 | /* set the stream id */ | |
3253 | snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, | |
3254 | AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0); | |
3255 | ||
3256 | /* set the stream format */ | |
3257 | snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, | |
3258 | AC_VERB_SET_STREAM_FORMAT, format); | |
3259 | ||
3260 | /* turn on again (if needed) */ | |
3261 | /* enable and set the channel status audio/data flag */ | |
7c935976 | 3262 | if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) { |
84eb01be TI |
3263 | snd_hda_codec_write(codec, |
3264 | nvhdmi_master_con_nid_7x, | |
3265 | 0, | |
3266 | AC_VERB_SET_DIGI_CONVERT_1, | |
7c935976 | 3267 | spdif->ctls & 0xff); |
84eb01be TI |
3268 | snd_hda_codec_write(codec, |
3269 | nvhdmi_master_con_nid_7x, | |
3270 | 0, | |
3271 | AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); | |
3272 | } | |
3273 | ||
3274 | for (i = 0; i < 4; i++) { | |
3275 | if (chs == 2) | |
3276 | channel_id = 0; | |
3277 | else | |
3278 | channel_id = i * 2; | |
3279 | ||
3280 | /* turn off SPDIF once; | |
3281 | *otherwise the IEC958 bits won't be updated | |
3282 | */ | |
3283 | if (codec->spdif_status_reset && | |
7c935976 | 3284 | (spdif->ctls & AC_DIG1_ENABLE)) |
84eb01be TI |
3285 | snd_hda_codec_write(codec, |
3286 | nvhdmi_con_nids_7x[i], | |
3287 | 0, | |
3288 | AC_VERB_SET_DIGI_CONVERT_1, | |
7c935976 | 3289 | spdif->ctls & ~AC_DIG1_ENABLE & 0xff); |
84eb01be TI |
3290 | /* set the stream id */ |
3291 | snd_hda_codec_write(codec, | |
3292 | nvhdmi_con_nids_7x[i], | |
3293 | 0, | |
3294 | AC_VERB_SET_CHANNEL_STREAMID, | |
3295 | (stream_tag << 4) | channel_id); | |
3296 | /* set the stream format */ | |
3297 | snd_hda_codec_write(codec, | |
3298 | nvhdmi_con_nids_7x[i], | |
3299 | 0, | |
3300 | AC_VERB_SET_STREAM_FORMAT, | |
3301 | format); | |
3302 | /* turn on again (if needed) */ | |
3303 | /* enable and set the channel status audio/data flag */ | |
3304 | if (codec->spdif_status_reset && | |
7c935976 | 3305 | (spdif->ctls & AC_DIG1_ENABLE)) { |
84eb01be TI |
3306 | snd_hda_codec_write(codec, |
3307 | nvhdmi_con_nids_7x[i], | |
3308 | 0, | |
3309 | AC_VERB_SET_DIGI_CONVERT_1, | |
7c935976 | 3310 | spdif->ctls & 0xff); |
84eb01be TI |
3311 | snd_hda_codec_write(codec, |
3312 | nvhdmi_con_nids_7x[i], | |
3313 | 0, | |
3314 | AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); | |
3315 | } | |
3316 | } | |
3317 | ||
1f348522 | 3318 | nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs); |
84eb01be TI |
3319 | |
3320 | mutex_unlock(&codec->spdif_mutex); | |
3321 | return 0; | |
3322 | } | |
3323 | ||
fb79e1e0 | 3324 | static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = { |
84eb01be TI |
3325 | .substreams = 1, |
3326 | .channels_min = 2, | |
3327 | .channels_max = 8, | |
3328 | .nid = nvhdmi_master_con_nid_7x, | |
3329 | .rates = SUPPORTED_RATES, | |
3330 | .maxbps = SUPPORTED_MAXBPS, | |
3331 | .formats = SUPPORTED_FORMATS, | |
3332 | .ops = { | |
3333 | .open = simple_playback_pcm_open, | |
3334 | .close = nvhdmi_8ch_7x_pcm_close, | |
3335 | .prepare = nvhdmi_8ch_7x_pcm_prepare | |
3336 | }, | |
3337 | }; | |
3338 | ||
84eb01be TI |
3339 | static int patch_nvhdmi_2ch(struct hda_codec *codec) |
3340 | { | |
3341 | struct hdmi_spec *spec; | |
d0b1252d TI |
3342 | int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x, |
3343 | nvhdmi_master_pin_nid_7x); | |
3344 | if (err < 0) | |
3345 | return err; | |
84eb01be | 3346 | |
ceaa86ba | 3347 | codec->patch_ops.init = nvhdmi_7x_init_2ch; |
d0b1252d TI |
3348 | /* override the PCM rates, etc, as the codec doesn't give full list */ |
3349 | spec = codec->spec; | |
3350 | spec->pcm_playback.rates = SUPPORTED_RATES; | |
3351 | spec->pcm_playback.maxbps = SUPPORTED_MAXBPS; | |
3352 | spec->pcm_playback.formats = SUPPORTED_FORMATS; | |
84eb01be TI |
3353 | return 0; |
3354 | } | |
3355 | ||
53775b0d TI |
3356 | static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec) |
3357 | { | |
3358 | struct hdmi_spec *spec = codec->spec; | |
3359 | int err = simple_playback_build_pcms(codec); | |
bce0d2a8 TI |
3360 | if (!err) { |
3361 | struct hda_pcm *info = get_pcm_rec(spec, 0); | |
3362 | info->own_chmap = true; | |
3363 | } | |
53775b0d TI |
3364 | return err; |
3365 | } | |
3366 | ||
3367 | static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec) | |
3368 | { | |
3369 | struct hdmi_spec *spec = codec->spec; | |
bce0d2a8 | 3370 | struct hda_pcm *info; |
53775b0d TI |
3371 | struct snd_pcm_chmap *chmap; |
3372 | int err; | |
3373 | ||
3374 | err = simple_playback_build_controls(codec); | |
3375 | if (err < 0) | |
3376 | return err; | |
3377 | ||
3378 | /* add channel maps */ | |
bce0d2a8 TI |
3379 | info = get_pcm_rec(spec, 0); |
3380 | err = snd_pcm_add_chmap_ctls(info->pcm, | |
53775b0d TI |
3381 | SNDRV_PCM_STREAM_PLAYBACK, |
3382 | snd_pcm_alt_chmaps, 8, 0, &chmap); | |
3383 | if (err < 0) | |
3384 | return err; | |
b9a94a9c | 3385 | switch (codec->preset->vendor_id) { |
53775b0d TI |
3386 | case 0x10de0002: |
3387 | case 0x10de0003: | |
3388 | case 0x10de0005: | |
3389 | case 0x10de0006: | |
3390 | chmap->channel_mask = (1U << 2) | (1U << 8); | |
3391 | break; | |
3392 | case 0x10de0007: | |
3393 | chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8); | |
3394 | } | |
3395 | return 0; | |
3396 | } | |
3397 | ||
84eb01be TI |
3398 | static int patch_nvhdmi_8ch_7x(struct hda_codec *codec) |
3399 | { | |
3400 | struct hdmi_spec *spec; | |
3401 | int err = patch_nvhdmi_2ch(codec); | |
84eb01be TI |
3402 | if (err < 0) |
3403 | return err; | |
3404 | spec = codec->spec; | |
3405 | spec->multiout.max_channels = 8; | |
d0b1252d | 3406 | spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x; |
ceaa86ba | 3407 | codec->patch_ops.init = nvhdmi_7x_init_8ch; |
53775b0d TI |
3408 | codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms; |
3409 | codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls; | |
1f348522 AP |
3410 | |
3411 | /* Initialize the audio infoframe channel mask and checksum to something | |
3412 | * valid */ | |
3413 | nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); | |
3414 | ||
84eb01be TI |
3415 | return 0; |
3416 | } | |
3417 | ||
611885bc AH |
3418 | /* |
3419 | * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on: | |
3420 | * - 0x10de0015 | |
3421 | * - 0x10de0040 | |
3422 | */ | |
67b90cb8 | 3423 | static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap, |
f302240d | 3424 | struct hdac_cea_channel_speaker_allocation *cap, int channels) |
611885bc AH |
3425 | { |
3426 | if (cap->ca_index == 0x00 && channels == 2) | |
3427 | return SNDRV_CTL_TLVT_CHMAP_FIXED; | |
3428 | ||
028cb68e SP |
3429 | /* If the speaker allocation matches the channel count, it is OK. */ |
3430 | if (cap->channels != channels) | |
3431 | return -1; | |
3432 | ||
3433 | /* all channels are remappable freely */ | |
3434 | return SNDRV_CTL_TLVT_CHMAP_VAR; | |
611885bc AH |
3435 | } |
3436 | ||
828cb4ed SP |
3437 | static int nvhdmi_chmap_validate(struct hdac_chmap *chmap, |
3438 | int ca, int chs, unsigned char *map) | |
611885bc AH |
3439 | { |
3440 | if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR)) | |
3441 | return -EINVAL; | |
3442 | ||
3443 | return 0; | |
3444 | } | |
3445 | ||
ade49db3 TI |
3446 | /* map from pin NID to port; port is 0-based */ |
3447 | /* for Nvidia: assume widget NID starting from 4, with step 1 (4, 5, 6, ...) */ | |
3448 | static int nvhdmi_pin2port(void *audio_ptr, int pin_nid) | |
3449 | { | |
3450 | return pin_nid - 4; | |
3451 | } | |
3452 | ||
3453 | /* reverse-map from port to pin NID: see above */ | |
3454 | static int nvhdmi_port2pin(struct hda_codec *codec, int port) | |
3455 | { | |
3456 | return port + 4; | |
3457 | } | |
3458 | ||
3459 | static const struct drm_audio_component_audio_ops nvhdmi_audio_ops = { | |
3460 | .pin2port = nvhdmi_pin2port, | |
3461 | .pin_eld_notify = generic_acomp_pin_eld_notify, | |
3462 | .master_bind = generic_acomp_master_bind, | |
3463 | .master_unbind = generic_acomp_master_unbind, | |
3464 | }; | |
3465 | ||
611885bc AH |
3466 | static int patch_nvhdmi(struct hda_codec *codec) |
3467 | { | |
3468 | struct hdmi_spec *spec; | |
3469 | int err; | |
3470 | ||
3471 | err = patch_generic_hdmi(codec); | |
3472 | if (err) | |
3473 | return err; | |
3474 | ||
3475 | spec = codec->spec; | |
75fae117 | 3476 | spec->dyn_pin_out = true; |
611885bc | 3477 | |
67b90cb8 | 3478 | spec->chmap.ops.chmap_cea_alloc_validate_get_type = |
611885bc | 3479 | nvhdmi_chmap_cea_alloc_validate_get_type; |
67b90cb8 | 3480 | spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; |
611885bc | 3481 | |
94989e31 LW |
3482 | codec->link_down_at_suspend = 1; |
3483 | ||
ade49db3 TI |
3484 | generic_acomp_init(codec, &nvhdmi_audio_ops, nvhdmi_port2pin); |
3485 | ||
611885bc AH |
3486 | return 0; |
3487 | } | |
3488 | ||
26e9a960 TR |
3489 | /* |
3490 | * The HDA codec on NVIDIA Tegra contains two scratch registers that are | |
3491 | * accessed using vendor-defined verbs. These registers can be used for | |
3492 | * interoperability between the HDA and HDMI drivers. | |
3493 | */ | |
3494 | ||
3495 | /* Audio Function Group node */ | |
3496 | #define NVIDIA_AFG_NID 0x01 | |
3497 | ||
3498 | /* | |
3499 | * The SCRATCH0 register is used to notify the HDMI codec of changes in audio | |
3500 | * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to | |
3501 | * be raised in the HDMI codec. The remainder of the bits is arbitrary. This | |
3502 | * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an | |
3503 | * additional bit (at position 30) to signal the validity of the format. | |
3504 | * | |
3505 | * | 31 | 30 | 29 16 | 15 0 | | |
3506 | * +---------+-------+--------+--------+ | |
3507 | * | TRIGGER | VALID | UNUSED | FORMAT | | |
3508 | * +-----------------------------------| | |
3509 | * | |
3510 | * Note that for the trigger bit to take effect it needs to change value | |
3511 | * (i.e. it needs to be toggled). | |
3512 | */ | |
3513 | #define NVIDIA_GET_SCRATCH0 0xfa6 | |
3514 | #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7 | |
3515 | #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8 | |
3516 | #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9 | |
3517 | #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa | |
3518 | #define NVIDIA_SCRATCH_TRIGGER (1 << 7) | |
3519 | #define NVIDIA_SCRATCH_VALID (1 << 6) | |
3520 | ||
3521 | #define NVIDIA_GET_SCRATCH1 0xfab | |
3522 | #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac | |
3523 | #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad | |
3524 | #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae | |
3525 | #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf | |
3526 | ||
3527 | /* | |
3528 | * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0, | |
3529 | * the format is invalidated so that the HDMI codec can be disabled. | |
3530 | */ | |
3531 | static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format) | |
3532 | { | |
3533 | unsigned int value; | |
3534 | ||
3535 | /* bits [31:30] contain the trigger and valid bits */ | |
3536 | value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0, | |
3537 | NVIDIA_GET_SCRATCH0, 0); | |
3538 | value = (value >> 24) & 0xff; | |
3539 | ||
3540 | /* bits [15:0] are used to store the HDA format */ | |
3541 | snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, | |
3542 | NVIDIA_SET_SCRATCH0_BYTE0, | |
3543 | (format >> 0) & 0xff); | |
3544 | snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, | |
3545 | NVIDIA_SET_SCRATCH0_BYTE1, | |
3546 | (format >> 8) & 0xff); | |
3547 | ||
3548 | /* bits [16:24] are unused */ | |
3549 | snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, | |
3550 | NVIDIA_SET_SCRATCH0_BYTE2, 0); | |
3551 | ||
3552 | /* | |
3553 | * Bit 30 signals that the data is valid and hence that HDMI audio can | |
3554 | * be enabled. | |
3555 | */ | |
3556 | if (format == 0) | |
3557 | value &= ~NVIDIA_SCRATCH_VALID; | |
3558 | else | |
3559 | value |= NVIDIA_SCRATCH_VALID; | |
3560 | ||
3561 | /* | |
3562 | * Whenever the trigger bit is toggled, an interrupt is raised in the | |
3563 | * HDMI codec. The HDMI driver will use that as trigger to update its | |
3564 | * configuration. | |
3565 | */ | |
3566 | value ^= NVIDIA_SCRATCH_TRIGGER; | |
3567 | ||
3568 | snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, | |
3569 | NVIDIA_SET_SCRATCH0_BYTE3, value); | |
3570 | } | |
3571 | ||
3572 | static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo, | |
3573 | struct hda_codec *codec, | |
3574 | unsigned int stream_tag, | |
3575 | unsigned int format, | |
3576 | struct snd_pcm_substream *substream) | |
3577 | { | |
3578 | int err; | |
3579 | ||
3580 | err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag, | |
3581 | format, substream); | |
3582 | if (err < 0) | |
3583 | return err; | |
3584 | ||
3585 | /* notify the HDMI codec of the format change */ | |
3586 | tegra_hdmi_set_format(codec, format); | |
3587 | ||
3588 | return 0; | |
3589 | } | |
3590 | ||
3591 | static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo, | |
3592 | struct hda_codec *codec, | |
3593 | struct snd_pcm_substream *substream) | |
3594 | { | |
3595 | /* invalidate the format in the HDMI codec */ | |
3596 | tegra_hdmi_set_format(codec, 0); | |
3597 | ||
3598 | return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream); | |
3599 | } | |
3600 | ||
3601 | static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type) | |
3602 | { | |
3603 | struct hdmi_spec *spec = codec->spec; | |
3604 | unsigned int i; | |
3605 | ||
3606 | for (i = 0; i < spec->num_pins; i++) { | |
3607 | struct hda_pcm *pcm = get_pcm_rec(spec, i); | |
3608 | ||
3609 | if (pcm->pcm_type == type) | |
3610 | return pcm; | |
3611 | } | |
3612 | ||
3613 | return NULL; | |
3614 | } | |
3615 | ||
3616 | static int tegra_hdmi_build_pcms(struct hda_codec *codec) | |
3617 | { | |
3618 | struct hda_pcm_stream *stream; | |
3619 | struct hda_pcm *pcm; | |
3620 | int err; | |
3621 | ||
3622 | err = generic_hdmi_build_pcms(codec); | |
3623 | if (err < 0) | |
3624 | return err; | |
3625 | ||
3626 | pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI); | |
3627 | if (!pcm) | |
3628 | return -ENODEV; | |
3629 | ||
3630 | /* | |
3631 | * Override ->prepare() and ->cleanup() operations to notify the HDMI | |
3632 | * codec about format changes. | |
3633 | */ | |
3634 | stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; | |
3635 | stream->ops.prepare = tegra_hdmi_pcm_prepare; | |
3636 | stream->ops.cleanup = tegra_hdmi_pcm_cleanup; | |
3637 | ||
3638 | return 0; | |
3639 | } | |
3640 | ||
3641 | static int patch_tegra_hdmi(struct hda_codec *codec) | |
3642 | { | |
3643 | int err; | |
3644 | ||
3645 | err = patch_generic_hdmi(codec); | |
3646 | if (err) | |
3647 | return err; | |
3648 | ||
3649 | codec->patch_ops.build_pcms = tegra_hdmi_build_pcms; | |
3650 | ||
3651 | return 0; | |
3652 | } | |
3653 | ||
84eb01be | 3654 | /* |
5a613584 | 3655 | * ATI/AMD-specific implementations |
84eb01be TI |
3656 | */ |
3657 | ||
5a613584 | 3658 | #define is_amdhdmi_rev3_or_later(codec) \ |
7639a06c TI |
3659 | ((codec)->core.vendor_id == 0x1002aa01 && \ |
3660 | ((codec)->core.revision_id & 0xff00) >= 0x0300) | |
5a613584 AH |
3661 | #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec) |
3662 | ||
3663 | /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */ | |
3664 | #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771 | |
3665 | #define ATI_VERB_SET_DOWNMIX_INFO 0x772 | |
3666 | #define ATI_VERB_SET_MULTICHANNEL_01 0x777 | |
3667 | #define ATI_VERB_SET_MULTICHANNEL_23 0x778 | |
3668 | #define ATI_VERB_SET_MULTICHANNEL_45 0x779 | |
3669 | #define ATI_VERB_SET_MULTICHANNEL_67 0x77a | |
461cf6b3 | 3670 | #define ATI_VERB_SET_HBR_CONTROL 0x77c |
5a613584 AH |
3671 | #define ATI_VERB_SET_MULTICHANNEL_1 0x785 |
3672 | #define ATI_VERB_SET_MULTICHANNEL_3 0x786 | |
3673 | #define ATI_VERB_SET_MULTICHANNEL_5 0x787 | |
3674 | #define ATI_VERB_SET_MULTICHANNEL_7 0x788 | |
3675 | #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789 | |
3676 | #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71 | |
3677 | #define ATI_VERB_GET_DOWNMIX_INFO 0xf72 | |
3678 | #define ATI_VERB_GET_MULTICHANNEL_01 0xf77 | |
3679 | #define ATI_VERB_GET_MULTICHANNEL_23 0xf78 | |
3680 | #define ATI_VERB_GET_MULTICHANNEL_45 0xf79 | |
3681 | #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a | |
461cf6b3 | 3682 | #define ATI_VERB_GET_HBR_CONTROL 0xf7c |
5a613584 AH |
3683 | #define ATI_VERB_GET_MULTICHANNEL_1 0xf85 |
3684 | #define ATI_VERB_GET_MULTICHANNEL_3 0xf86 | |
3685 | #define ATI_VERB_GET_MULTICHANNEL_5 0xf87 | |
3686 | #define ATI_VERB_GET_MULTICHANNEL_7 0xf88 | |
3687 | #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89 | |
3688 | ||
84d69e79 AH |
3689 | /* AMD specific HDA cvt verbs */ |
3690 | #define ATI_VERB_SET_RAMP_RATE 0x770 | |
3691 | #define ATI_VERB_GET_RAMP_RATE 0xf70 | |
3692 | ||
5a613584 AH |
3693 | #define ATI_OUT_ENABLE 0x1 |
3694 | ||
3695 | #define ATI_MULTICHANNEL_MODE_PAIRED 0 | |
3696 | #define ATI_MULTICHANNEL_MODE_SINGLE 1 | |
3697 | ||
461cf6b3 AH |
3698 | #define ATI_HBR_CAPABLE 0x01 |
3699 | #define ATI_HBR_ENABLE 0x10 | |
3700 | ||
89250f84 AH |
3701 | static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, |
3702 | unsigned char *buf, int *eld_size) | |
3703 | { | |
3704 | /* call hda_eld.c ATI/AMD-specific function */ | |
3705 | return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size, | |
3706 | is_amdhdmi_rev3_or_later(codec)); | |
3707 | } | |
3708 | ||
5a613584 AH |
3709 | static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca, |
3710 | int active_channels, int conn_type) | |
3711 | { | |
3712 | snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca); | |
3713 | } | |
3714 | ||
3715 | static int atihdmi_paired_swap_fc_lfe(int pos) | |
3716 | { | |
3717 | /* | |
3718 | * ATI/AMD have automatic FC/LFE swap built-in | |
3719 | * when in pairwise mapping mode. | |
3720 | */ | |
3721 | ||
3722 | switch (pos) { | |
3723 | /* see channel_allocations[].speakers[] */ | |
3724 | case 2: return 3; | |
3725 | case 3: return 2; | |
3726 | default: break; | |
3727 | } | |
3728 | ||
3729 | return pos; | |
3730 | } | |
3731 | ||
828cb4ed SP |
3732 | static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap, |
3733 | int ca, int chs, unsigned char *map) | |
5a613584 | 3734 | { |
f302240d | 3735 | struct hdac_cea_channel_speaker_allocation *cap; |
5a613584 AH |
3736 | int i, j; |
3737 | ||
3738 | /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */ | |
3739 | ||
bb63f726 | 3740 | cap = snd_hdac_get_ch_alloc_from_ca(ca); |
5a613584 | 3741 | for (i = 0; i < chs; ++i) { |
bb63f726 | 3742 | int mask = snd_hdac_chmap_to_spk_mask(map[i]); |
5a613584 AH |
3743 | bool ok = false; |
3744 | bool companion_ok = false; | |
3745 | ||
3746 | if (!mask) | |
3747 | continue; | |
3748 | ||
3749 | for (j = 0 + i % 2; j < 8; j += 2) { | |
3750 | int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j); | |
3751 | if (cap->speakers[chan_idx] == mask) { | |
3752 | /* channel is in a supported position */ | |
3753 | ok = true; | |
3754 | ||
3755 | if (i % 2 == 0 && i + 1 < chs) { | |
3756 | /* even channel, check the odd companion */ | |
3757 | int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1); | |
bb63f726 | 3758 | int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]); |
5a613584 AH |
3759 | int comp_mask_act = cap->speakers[comp_chan_idx]; |
3760 | ||
3761 | if (comp_mask_req == comp_mask_act) | |
3762 | companion_ok = true; | |
3763 | else | |
3764 | return -EINVAL; | |
3765 | } | |
3766 | break; | |
3767 | } | |
3768 | } | |
3769 | ||
3770 | if (!ok) | |
3771 | return -EINVAL; | |
3772 | ||
3773 | if (companion_ok) | |
3774 | i++; /* companion channel already checked */ | |
3775 | } | |
3776 | ||
3777 | return 0; | |
3778 | } | |
3779 | ||
739ffee9 SP |
3780 | static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac, |
3781 | hda_nid_t pin_nid, int hdmi_slot, int stream_channel) | |
5a613584 | 3782 | { |
739ffee9 | 3783 | struct hda_codec *codec = container_of(hdac, struct hda_codec, core); |
5a613584 AH |
3784 | int verb; |
3785 | int ati_channel_setup = 0; | |
3786 | ||
3787 | if (hdmi_slot > 7) | |
3788 | return -EINVAL; | |
3789 | ||
3790 | if (!has_amd_full_remap_support(codec)) { | |
3791 | hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot); | |
3792 | ||
3793 | /* In case this is an odd slot but without stream channel, do not | |
3794 | * disable the slot since the corresponding even slot could have a | |
3795 | * channel. In case neither have a channel, the slot pair will be | |
3796 | * disabled when this function is called for the even slot. */ | |
3797 | if (hdmi_slot % 2 != 0 && stream_channel == 0xf) | |
3798 | return 0; | |
3799 | ||
3800 | hdmi_slot -= hdmi_slot % 2; | |
3801 | ||
3802 | if (stream_channel != 0xf) | |
3803 | stream_channel -= stream_channel % 2; | |
3804 | } | |
3805 | ||
3806 | verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e; | |
3807 | ||
3808 | /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */ | |
3809 | ||
3810 | if (stream_channel != 0xf) | |
3811 | ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE; | |
3812 | ||
3813 | return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup); | |
3814 | } | |
3815 | ||
739ffee9 SP |
3816 | static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac, |
3817 | hda_nid_t pin_nid, int asp_slot) | |
5a613584 | 3818 | { |
739ffee9 | 3819 | struct hda_codec *codec = container_of(hdac, struct hda_codec, core); |
5a613584 AH |
3820 | bool was_odd = false; |
3821 | int ati_asp_slot = asp_slot; | |
3822 | int verb; | |
3823 | int ati_channel_setup; | |
3824 | ||
3825 | if (asp_slot > 7) | |
3826 | return -EINVAL; | |
3827 | ||
3828 | if (!has_amd_full_remap_support(codec)) { | |
3829 | ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot); | |
3830 | if (ati_asp_slot % 2 != 0) { | |
3831 | ati_asp_slot -= 1; | |
3832 | was_odd = true; | |
3833 | } | |
3834 | } | |
3835 | ||
3836 | verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e; | |
3837 | ||
3838 | ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0); | |
3839 | ||
3840 | if (!(ati_channel_setup & ATI_OUT_ENABLE)) | |
3841 | return 0xf; | |
3842 | ||
3843 | return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd; | |
3844 | } | |
84eb01be | 3845 | |
67b90cb8 SP |
3846 | static int atihdmi_paired_chmap_cea_alloc_validate_get_type( |
3847 | struct hdac_chmap *chmap, | |
f302240d | 3848 | struct hdac_cea_channel_speaker_allocation *cap, |
67b90cb8 | 3849 | int channels) |
5a613584 AH |
3850 | { |
3851 | int c; | |
3852 | ||
3853 | /* | |
3854 | * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so | |
3855 | * we need to take that into account (a single channel may take 2 | |
3856 | * channel slots if we need to carry a silent channel next to it). | |
3857 | * On Rev3+ AMD codecs this function is not used. | |
3858 | */ | |
3859 | int chanpairs = 0; | |
3860 | ||
3861 | /* We only produce even-numbered channel count TLVs */ | |
3862 | if ((channels % 2) != 0) | |
3863 | return -1; | |
3864 | ||
3865 | for (c = 0; c < 7; c += 2) { | |
3866 | if (cap->speakers[c] || cap->speakers[c+1]) | |
3867 | chanpairs++; | |
3868 | } | |
3869 | ||
3870 | if (chanpairs * 2 != channels) | |
3871 | return -1; | |
3872 | ||
3873 | return SNDRV_CTL_TLVT_CHMAP_PAIRED; | |
3874 | } | |
3875 | ||
828cb4ed | 3876 | static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap, |
f302240d SP |
3877 | struct hdac_cea_channel_speaker_allocation *cap, |
3878 | unsigned int *chmap, int channels) | |
5a613584 AH |
3879 | { |
3880 | /* produce paired maps for pre-rev3 ATI/AMD codecs */ | |
3881 | int count = 0; | |
3882 | int c; | |
3883 | ||
3884 | for (c = 7; c >= 0; c--) { | |
3885 | int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c); | |
3886 | int spk = cap->speakers[chan]; | |
3887 | if (!spk) { | |
3888 | /* add N/A channel if the companion channel is occupied */ | |
3889 | if (cap->speakers[chan + (chan % 2 ? -1 : 1)]) | |
3890 | chmap[count++] = SNDRV_CHMAP_NA; | |
3891 | ||
3892 | continue; | |
3893 | } | |
3894 | ||
bb63f726 | 3895 | chmap[count++] = snd_hdac_spk_to_chmap(spk); |
5a613584 AH |
3896 | } |
3897 | ||
3898 | WARN_ON(count != channels); | |
3899 | } | |
3900 | ||
461cf6b3 AH |
3901 | static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, |
3902 | bool hbr) | |
3903 | { | |
3904 | int hbr_ctl, hbr_ctl_new; | |
3905 | ||
3906 | hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0); | |
13122e6e | 3907 | if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) { |
461cf6b3 AH |
3908 | if (hbr) |
3909 | hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE; | |
3910 | else | |
3911 | hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE; | |
3912 | ||
4e76a883 TI |
3913 | codec_dbg(codec, |
3914 | "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n", | |
461cf6b3 AH |
3915 | pin_nid, |
3916 | hbr_ctl == hbr_ctl_new ? "" : "new-", | |
3917 | hbr_ctl_new); | |
3918 | ||
3919 | if (hbr_ctl != hbr_ctl_new) | |
3920 | snd_hda_codec_write(codec, pin_nid, 0, | |
3921 | ATI_VERB_SET_HBR_CONTROL, | |
3922 | hbr_ctl_new); | |
3923 | ||
3924 | } else if (hbr) | |
3925 | return -EINVAL; | |
3926 | ||
3927 | return 0; | |
3928 | } | |
3929 | ||
84d69e79 AH |
3930 | static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, |
3931 | hda_nid_t pin_nid, u32 stream_tag, int format) | |
3932 | { | |
3933 | ||
3934 | if (is_amdhdmi_rev3_or_later(codec)) { | |
3935 | int ramp_rate = 180; /* default as per AMD spec */ | |
3936 | /* disable ramp-up/down for non-pcm as per AMD spec */ | |
3937 | if (format & AC_FMT_TYPE_NON_PCM) | |
3938 | ramp_rate = 0; | |
3939 | ||
3940 | snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate); | |
3941 | } | |
3942 | ||
3943 | return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format); | |
3944 | } | |
3945 | ||
3946 | ||
5a613584 | 3947 | static int atihdmi_init(struct hda_codec *codec) |
84eb01be TI |
3948 | { |
3949 | struct hdmi_spec *spec = codec->spec; | |
5a613584 | 3950 | int pin_idx, err; |
84eb01be | 3951 | |
5a613584 AH |
3952 | err = generic_hdmi_init(codec); |
3953 | ||
3954 | if (err) | |
84eb01be | 3955 | return err; |
5a613584 AH |
3956 | |
3957 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { | |
3958 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); | |
3959 | ||
3960 | /* make sure downmix information in infoframe is zero */ | |
3961 | snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0); | |
3962 | ||
3963 | /* enable channel-wise remap mode if supported */ | |
3964 | if (has_amd_full_remap_support(codec)) | |
3965 | snd_hda_codec_write(codec, per_pin->pin_nid, 0, | |
3966 | ATI_VERB_SET_MULTICHANNEL_MODE, | |
3967 | ATI_MULTICHANNEL_MODE_SINGLE); | |
84eb01be | 3968 | } |
5a613584 | 3969 | |
84eb01be TI |
3970 | return 0; |
3971 | } | |
3972 | ||
ade49db3 TI |
3973 | /* map from pin NID to port; port is 0-based */ |
3974 | /* for AMD: assume widget NID starting from 3, with step 2 (3, 5, 7, ...) */ | |
3975 | static int atihdmi_pin2port(void *audio_ptr, int pin_nid) | |
3976 | { | |
3977 | return pin_nid / 2 - 1; | |
3978 | } | |
3979 | ||
3980 | /* reverse-map from port to pin NID: see above */ | |
3981 | static int atihdmi_port2pin(struct hda_codec *codec, int port) | |
3982 | { | |
3983 | return port * 2 + 3; | |
3984 | } | |
3985 | ||
3986 | static const struct drm_audio_component_audio_ops atihdmi_audio_ops = { | |
3987 | .pin2port = atihdmi_pin2port, | |
3988 | .pin_eld_notify = generic_acomp_pin_eld_notify, | |
3989 | .master_bind = generic_acomp_master_bind, | |
3990 | .master_unbind = generic_acomp_master_unbind, | |
3991 | }; | |
3992 | ||
84eb01be TI |
3993 | static int patch_atihdmi(struct hda_codec *codec) |
3994 | { | |
3995 | struct hdmi_spec *spec; | |
5a613584 AH |
3996 | struct hdmi_spec_per_cvt *per_cvt; |
3997 | int err, cvt_idx; | |
3998 | ||
3999 | err = patch_generic_hdmi(codec); | |
4000 | ||
4001 | if (err) | |
d0b1252d | 4002 | return err; |
5a613584 AH |
4003 | |
4004 | codec->patch_ops.init = atihdmi_init; | |
4005 | ||
d0b1252d | 4006 | spec = codec->spec; |
5a613584 | 4007 | |
89250f84 | 4008 | spec->ops.pin_get_eld = atihdmi_pin_get_eld; |
5a613584 | 4009 | spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe; |
461cf6b3 | 4010 | spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup; |
84d69e79 | 4011 | spec->ops.setup_stream = atihdmi_setup_stream; |
5a613584 | 4012 | |
39669225 TI |
4013 | spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel; |
4014 | spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel; | |
4015 | ||
5a613584 AH |
4016 | if (!has_amd_full_remap_support(codec)) { |
4017 | /* override to ATI/AMD-specific versions with pairwise mapping */ | |
67b90cb8 | 4018 | spec->chmap.ops.chmap_cea_alloc_validate_get_type = |
5a613584 | 4019 | atihdmi_paired_chmap_cea_alloc_validate_get_type; |
67b90cb8 SP |
4020 | spec->chmap.ops.cea_alloc_to_tlv_chmap = |
4021 | atihdmi_paired_cea_alloc_to_tlv_chmap; | |
4022 | spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate; | |
5a613584 AH |
4023 | } |
4024 | ||
4025 | /* ATI/AMD converters do not advertise all of their capabilities */ | |
4026 | for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { | |
4027 | per_cvt = get_cvt(spec, cvt_idx); | |
4028 | per_cvt->channels_max = max(per_cvt->channels_max, 8u); | |
4029 | per_cvt->rates |= SUPPORTED_RATES; | |
4030 | per_cvt->formats |= SUPPORTED_FORMATS; | |
4031 | per_cvt->maxbps = max(per_cvt->maxbps, 24u); | |
4032 | } | |
4033 | ||
67b90cb8 | 4034 | spec->chmap.channels_max = max(spec->chmap.channels_max, 8u); |
5a613584 | 4035 | |
57cb54e5 TI |
4036 | /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing |
4037 | * the link-down as is. Tell the core to allow it. | |
4038 | */ | |
4039 | codec->link_down_at_suspend = 1; | |
4040 | ||
ade49db3 TI |
4041 | generic_acomp_init(codec, &atihdmi_audio_ops, atihdmi_port2pin); |
4042 | ||
84eb01be TI |
4043 | return 0; |
4044 | } | |
4045 | ||
3de5ff88 AL |
4046 | /* VIA HDMI Implementation */ |
4047 | #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */ | |
4048 | #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */ | |
4049 | ||
3de5ff88 AL |
4050 | static int patch_via_hdmi(struct hda_codec *codec) |
4051 | { | |
250e41ac | 4052 | return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID); |
3de5ff88 | 4053 | } |
84eb01be TI |
4054 | |
4055 | /* | |
4056 | * patch entries | |
4057 | */ | |
b9a94a9c TI |
4058 | static const struct hda_device_id snd_hda_id_hdmi[] = { |
4059 | HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi), | |
4060 | HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi), | |
4061 | HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi), | |
4062 | HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi), | |
4063 | HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi), | |
4064 | HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi), | |
4065 | HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi), | |
74ec1181 | 4066 | HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch), |
b9a94a9c TI |
4067 | HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), |
4068 | HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), | |
74ec1181 | 4069 | HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x), |
b9a94a9c TI |
4070 | HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), |
4071 | HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), | |
4072 | HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x), | |
74ec1181 DD |
4073 | HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi), |
4074 | HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi), | |
b9a94a9c TI |
4075 | HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi), |
4076 | HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi), | |
4077 | HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi), | |
4078 | HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi), | |
4079 | HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi), | |
4080 | HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi), | |
4081 | HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi), | |
4082 | HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi), | |
4083 | HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi), | |
4084 | HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi), | |
4085 | HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi), | |
c8900a0f | 4086 | /* 17 is known to be absent */ |
b9a94a9c TI |
4087 | HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi), |
4088 | HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi), | |
4089 | HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi), | |
4090 | HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi), | |
4091 | HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi), | |
4092 | HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi), | |
4093 | HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi), | |
4094 | HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi), | |
4095 | HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi), | |
917bb90c TR |
4096 | HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi), |
4097 | HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi), | |
4098 | HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi), | |
4099 | HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi), | |
b9a94a9c TI |
4100 | HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi), |
4101 | HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi), | |
4102 | HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi), | |
4103 | HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi), | |
4104 | HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi), | |
74ec1181 DD |
4105 | HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi), |
4106 | HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi), | |
b9a94a9c | 4107 | HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi), |
74ec1181 | 4108 | HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi), |
b9a94a9c | 4109 | HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi), |
74ec1181 DD |
4110 | HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi), |
4111 | HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi), | |
b9a94a9c TI |
4112 | HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch), |
4113 | HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi), | |
4114 | HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi), | |
4115 | HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi), | |
74ec1181 DD |
4116 | HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi), |
4117 | HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi), | |
4118 | HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi), | |
4119 | HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi), | |
4120 | HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi), | |
b9a94a9c | 4121 | HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi), |
74ec1181 | 4122 | HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi), |
af677166 | 4123 | HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi), |
74ec1181 | 4124 | HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi), |
2d369c74 | 4125 | HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi), |
3ec622f4 | 4126 | HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi), |
74ec1181 DD |
4127 | HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi), |
4128 | HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi), | |
4129 | HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi), | |
4130 | HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi), | |
4131 | HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi), | |
4132 | HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi), | |
4133 | HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi), | |
4134 | HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi), | |
4135 | HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi), | |
4136 | HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi), | |
b9a94a9c | 4137 | HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch), |
74ec1181 | 4138 | HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch), |
b9a94a9c TI |
4139 | HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi), |
4140 | HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi), | |
4141 | HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi), | |
4142 | HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi), | |
7ff652ff | 4143 | HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi), |
b0d8bc50 | 4144 | HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi), |
b9a94a9c TI |
4145 | HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi), |
4146 | HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi), | |
4147 | HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi), | |
7ff652ff | 4148 | HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi), |
e85015a3 TI |
4149 | HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi), |
4150 | HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi), | |
a686632f TI |
4151 | HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi), |
4152 | HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi), | |
4153 | HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi), | |
4154 | HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi), | |
4155 | HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi), | |
2b4584d0 | 4156 | HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi), |
a87a4d23 | 4157 | HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi), |
b0d8bc50 | 4158 | HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi), |
9a11ba73 | 4159 | HDA_CODEC_ENTRY(0x80862812, "Tigerlake HDMI", patch_i915_tgl_hdmi), |
b9a94a9c | 4160 | HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi), |
a686632f TI |
4161 | HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi), |
4162 | HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi), | |
b9a94a9c | 4163 | HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi), |
d8a766a1 | 4164 | /* special ID for generic HDMI */ |
b9a94a9c | 4165 | HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi), |
84eb01be TI |
4166 | {} /* terminator */ |
4167 | }; | |
b9a94a9c | 4168 | MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi); |
84eb01be TI |
4169 | |
4170 | MODULE_LICENSE("GPL"); | |
4171 | MODULE_DESCRIPTION("HDMI HD-audio codec"); | |
4172 | MODULE_ALIAS("snd-hda-codec-intelhdmi"); | |
4173 | MODULE_ALIAS("snd-hda-codec-nvhdmi"); | |
4174 | MODULE_ALIAS("snd-hda-codec-atihdmi"); | |
4175 | ||
d8a766a1 | 4176 | static struct hda_codec_driver hdmi_driver = { |
b9a94a9c | 4177 | .id = snd_hda_id_hdmi, |
84eb01be TI |
4178 | }; |
4179 | ||
d8a766a1 | 4180 | module_hda_codec_driver(hdmi_driver); |