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ALSA: hda - Fix the wrong pincaps set in ALC861VD dallas/hp fixup
[linux-block.git] / sound / pci / hda / patch_hdmi.c
CommitLineData
079d88cc
WF		 1/*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
84eb01be
TI		 6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
079d88cc
WF		 9 *
10 * Authors:
11 * Wu Fengguang <wfg@linux.intel.com>
12 *
13 * Maintained by:
14 * Wu Fengguang <wfg@linux.intel.com>
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the Free
18 * Software Foundation; either version 2 of the License, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful, but
22 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
23 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
24 * for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software Foundation,
28 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
84eb01be
TI		 31#include <linux/init.h>
32#include <linux/delay.h>
33#include <linux/slab.h>
65a77217 34#include <linux/module.h>
84eb01be 35#include <sound/core.h>
07acecc1 36#include <sound/jack.h>
433968da 37#include <sound/asoundef.h>
d45e6889 38#include <sound/tlv.h>
84eb01be
TI		 39#include "hda_codec.h"
40#include "hda_local.h"
1835a0f9 41#include "hda_jack.h"
84eb01be 42
0ebaa24c
TI		 43static bool static_hdmi_pcm;
44module_param(static_hdmi_pcm, bool, 0644);
45MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
46
84eb01be
TI		 47/*
48 * The HDMI/DisplayPort configuration can be highly dynamic. A graphics device
384a48d7 49 * could support N independent pipes, each of them can be connected to one or
84eb01be
TI		 50 * more ports (DVI, HDMI or DisplayPort).
51 *
52 * The HDA correspondence of pipes/ports are converter/pin nodes.
53 */
a4567cb3
TI		 54#define MAX_HDMI_CVTS 8
55#define MAX_HDMI_PINS 8
079d88cc 56
384a48d7
SW		 57struct hdmi_spec_per_cvt {
58 hda_nid_t cvt_nid;
59 int assigned;
60 unsigned int channels_min;
61 unsigned int channels_max;
62 u32 rates;
63 u64 formats;
64 unsigned int maxbps;
65};
079d88cc 66
384a48d7
SW		 67struct hdmi_spec_per_pin {
68 hda_nid_t pin_nid;
69 int num_mux_nids;
70 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
744626da
WF		 71
72 struct hda_codec *codec;
384a48d7 73 struct hdmi_eld sink_eld;
744626da 74 struct delayed_work work;
c6e8453e 75 int repoll_count;
1a6003b5 76 bool non_pcm;
d45e6889
TI		 77 bool chmap_set; /* channel-map override by ALSA API? */
78 unsigned char chmap[8]; /* ALSA API channel-map */
384a48d7 79};
079d88cc 80
384a48d7
SW		 81struct hdmi_spec {
82 int num_cvts;
83 struct hdmi_spec_per_cvt cvts[MAX_HDMI_CVTS];
079d88cc 84
384a48d7
SW		 85 int num_pins;
86 struct hdmi_spec_per_pin pins[MAX_HDMI_PINS];
87 struct hda_pcm pcm_rec[MAX_HDMI_PINS];
d45e6889 88 unsigned int channels_max; /* max over all cvts */
079d88cc
WF		 89
90 /*
384a48d7 91 * Non-generic ATI/NVIDIA specific
079d88cc
WF		 92 */
93 struct hda_multi_out multiout;
d0b1252d 94 struct hda_pcm_stream pcm_playback;
079d88cc
WF		 95};
96
97
98struct hdmi_audio_infoframe {
99 u8 type; /* 0x84 */
100 u8 ver; /* 0x01 */
101 u8 len; /* 0x0a */
102
53d7d69d
WF		 103 u8 checksum;
104
079d88cc
WF		 105 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
106 u8 SS01_SF24;
107 u8 CXT04;
108 u8 CA;
109 u8 LFEPBL01_LSV36_DM_INH7;
53d7d69d
WF		 110};
111
112struct dp_audio_infoframe {
113 u8 type; /* 0x84 */
114 u8 len; /* 0x1b */
115 u8 ver; /* 0x11 << 2 */
116
117 u8 CC02_CT47; /* match with HDMI infoframe from this on */
118 u8 SS01_SF24;
119 u8 CXT04;
120 u8 CA;
121 u8 LFEPBL01_LSV36_DM_INH7;
079d88cc
WF		 122};
123
2b203dbb
TI		 124union audio_infoframe {
125 struct hdmi_audio_infoframe hdmi;
126 struct dp_audio_infoframe dp;
127 u8 bytes[0];
128};
129
079d88cc
WF		 130/*
131 * CEA speaker placement:
132 *
133 * FLH FCH FRH
134 * FLW FL FLC FC FRC FR FRW
135 *
136 * LFE
137 * TC
138 *
139 * RL RLC RC RRC RR
140 *
141 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
142 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
143 */
144enum cea_speaker_placement {
145 FL = (1 << 0), /* Front Left */
146 FC = (1 << 1), /* Front Center */
147 FR = (1 << 2), /* Front Right */
148 FLC = (1 << 3), /* Front Left Center */
149 FRC = (1 << 4), /* Front Right Center */
150 RL = (1 << 5), /* Rear Left */
151 RC = (1 << 6), /* Rear Center */
152 RR = (1 << 7), /* Rear Right */
153 RLC = (1 << 8), /* Rear Left Center */
154 RRC = (1 << 9), /* Rear Right Center */
155 LFE = (1 << 10), /* Low Frequency Effect */
156 FLW = (1 << 11), /* Front Left Wide */
157 FRW = (1 << 12), /* Front Right Wide */
158 FLH = (1 << 13), /* Front Left High */
159 FCH = (1 << 14), /* Front Center High */
160 FRH = (1 << 15), /* Front Right High */
161 TC = (1 << 16), /* Top Center */
162};
163
164/*
165 * ELD SA bits in the CEA Speaker Allocation data block
166 */
167static int eld_speaker_allocation_bits[] = {
168 [0] = FL | FR,
169 [1] = LFE,
170 [2] = FC,
171 [3] = RL | RR,
172 [4] = RC,
173 [5] = FLC | FRC,
174 [6] = RLC | RRC,
175 /* the following are not defined in ELD yet */
176 [7] = FLW | FRW,
177 [8] = FLH | FRH,
178 [9] = TC,
179 [10] = FCH,
180};
181
182struct cea_channel_speaker_allocation {
183 int ca_index;
184 int speakers[8];
185
186 /* derived values, just for convenience */
187 int channels;
188 int spk_mask;
189};
190
191/*
192 * ALSA sequence is:
193 *
194 * surround40 surround41 surround50 surround51 surround71
195 * ch0 front left = = = =
196 * ch1 front right = = = =
197 * ch2 rear left = = = =
198 * ch3 rear right = = = =
199 * ch4 LFE center center center
200 * ch5 LFE LFE
201 * ch6 side left
202 * ch7 side right
203 *
204 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
205 */
206static int hdmi_channel_mapping[0x32][8] = {
207 /* stereo */
208 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
209 /* 2.1 */
210 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
211 /* Dolby Surround */
212 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
213 /* surround40 */
214 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
215 /* 4ch */
216 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
217 /* surround41 */
9396d317 218 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
079d88cc
WF		 219 /* surround50 */
220 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
221 /* surround51 */
222 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
223 /* 7.1 */
224 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
225};
226
227/*
228 * This is an ordered list!
229 *
230 * The preceding ones have better chances to be selected by
53d7d69d 231 * hdmi_channel_allocation().
079d88cc
WF		 232 */
233static struct cea_channel_speaker_allocation channel_allocations[] = {
234/* channel: 7 6 5 4 3 2 1 0 */
235{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
236 /* 2.1 */
237{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
238 /* Dolby Surround */
239{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
240 /* surround40 */
241{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
242 /* surround41 */
243{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
244 /* surround50 */
245{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
246 /* surround51 */
247{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
248 /* 6.1 */
249{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
250 /* surround71 */
251{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
252
253{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
254{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
255{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
256{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
257{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
258{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
259{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
260{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
261{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
262{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
263{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
264{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
265{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
266{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
267{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
268{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
269{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
270{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
271{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
272{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
273{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
274{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
275{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
276{ .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
277{ .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
278{ .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
279{ .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
280{ .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
281{ .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
282{ .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
283{ .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
284{ .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
285{ .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
286{ .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
287{ .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
288{ .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
289{ .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
290{ .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
291{ .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
292{ .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
293{ .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
294};
295
296
297/*
298 * HDMI routines
299 */
300
384a48d7 301static int pin_nid_to_pin_index(struct hdmi_spec *spec, hda_nid_t pin_nid)
079d88cc 302{
384a48d7 303 int pin_idx;
079d88cc 304
384a48d7
SW		 305 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
306 if (spec->pins[pin_idx].pin_nid == pin_nid)
307 return pin_idx;
079d88cc 308
384a48d7
SW		 309 snd_printk(KERN_WARNING "HDMI: pin nid %d not registered\n", pin_nid);
310 return -EINVAL;
311}
312
313static int hinfo_to_pin_index(struct hdmi_spec *spec,
314 struct hda_pcm_stream *hinfo)
315{
316 int pin_idx;
317
318 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
319 if (&spec->pcm_rec[pin_idx].stream[0] == hinfo)
320 return pin_idx;
321
322 snd_printk(KERN_WARNING "HDMI: hinfo %p not registered\n", hinfo);
323 return -EINVAL;
324}
325
326static int cvt_nid_to_cvt_index(struct hdmi_spec *spec, hda_nid_t cvt_nid)
327{
328 int cvt_idx;
329
330 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
331 if (spec->cvts[cvt_idx].cvt_nid == cvt_nid)
332 return cvt_idx;
333
334 snd_printk(KERN_WARNING "HDMI: cvt nid %d not registered\n", cvt_nid);
079d88cc
WF		 335 return -EINVAL;
336}
337
14bc52b8
PLB		 338static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
339 struct snd_ctl_elem_info *uinfo)
340{
341 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
342 struct hdmi_spec *spec;
343 int pin_idx;
344
345 spec = codec->spec;
346 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
347
348 pin_idx = kcontrol->private_value;
349 uinfo->count = spec->pins[pin_idx].sink_eld.eld_size;
350
351 return 0;
352}
353
354static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
355 struct snd_ctl_elem_value *ucontrol)
356{
357 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
358 struct hdmi_spec *spec;
359 int pin_idx;
360
361 spec = codec->spec;
362 pin_idx = kcontrol->private_value;
363
364 memcpy(ucontrol->value.bytes.data,
365 spec->pins[pin_idx].sink_eld.eld_buffer, ELD_MAX_SIZE);
366
367 return 0;
368}
369
370static struct snd_kcontrol_new eld_bytes_ctl = {
371 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
372 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
373 .name = "ELD",
374 .info = hdmi_eld_ctl_info,
375 .get = hdmi_eld_ctl_get,
376};
377
378static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
379 int device)
380{
381 struct snd_kcontrol *kctl;
382 struct hdmi_spec *spec = codec->spec;
383 int err;
384
385 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
386 if (!kctl)
387 return -ENOMEM;
388 kctl->private_value = pin_idx;
389 kctl->id.device = device;
390
391 err = snd_hda_ctl_add(codec, spec->pins[pin_idx].pin_nid, kctl);
392 if (err < 0)
393 return err;
394
395 return 0;
396}
397
079d88cc
WF		 398#ifdef BE_PARANOID
399static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
400 int *packet_index, int *byte_index)
401{
402 int val;
403
404 val = snd_hda_codec_read(codec, pin_nid, 0,
405 AC_VERB_GET_HDMI_DIP_INDEX, 0);
406
407 *packet_index = val >> 5;
408 *byte_index = val & 0x1f;
409}
410#endif
411
412static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
413 int packet_index, int byte_index)
414{
415 int val;
416
417 val = (packet_index << 5) | (byte_index & 0x1f);
418
419 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
420}
421
422static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
423 unsigned char val)
424{
425 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
426}
427
384a48d7 428static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc
WF		 429{
430 /* Unmute */
431 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
432 snd_hda_codec_write(codec, pin_nid, 0,
433 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
6169b673
TI		 434 /* Enable pin out: some machines with GM965 gets broken output when
435 * the pin is disabled or changed while using with HDMI
436 */
079d88cc 437 snd_hda_codec_write(codec, pin_nid, 0,
6169b673 438 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
079d88cc
WF		 439}
440
384a48d7 441static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc 442{
384a48d7 443 return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
079d88cc
WF		 444 AC_VERB_GET_CVT_CHAN_COUNT, 0);
445}
446
447static void hdmi_set_channel_count(struct hda_codec *codec,
384a48d7 448 hda_nid_t cvt_nid, int chs)
079d88cc 449{
384a48d7
SW		 450 if (chs != hdmi_get_channel_count(codec, cvt_nid))
451 snd_hda_codec_write(codec, cvt_nid, 0,
079d88cc
WF		 452 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
453}
454
455
456/*
457 * Channel mapping routines
458 */
459
460/*
461 * Compute derived values in channel_allocations[].
462 */
463static void init_channel_allocations(void)
464{
465 int i, j;
466 struct cea_channel_speaker_allocation *p;
467
468 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
469 p = channel_allocations + i;
470 p->channels = 0;
471 p->spk_mask = 0;
472 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
473 if (p->speakers[j]) {
474 p->channels++;
475 p->spk_mask |= p->speakers[j];
476 }
477 }
478}
479
72357c78
WX		 480static int get_channel_allocation_order(int ca)
481{
482 int i;
483
484 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
485 if (channel_allocations[i].ca_index == ca)
486 break;
487 }
488 return i;
489}
490
079d88cc
WF		 491/*
492 * The transformation takes two steps:
493 *
494 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
495 * spk_mask => (channel_allocations[]) => ai->CA
496 *
497 * TODO: it could select the wrong CA from multiple candidates.
498*/
384a48d7 499static int hdmi_channel_allocation(struct hdmi_eld *eld, int channels)
079d88cc 500{
079d88cc 501 int i;
53d7d69d 502 int ca = 0;
079d88cc 503 int spk_mask = 0;
079d88cc
WF		 504 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
505
506 /*
507 * CA defaults to 0 for basic stereo audio
508 */
509 if (channels <= 2)
510 return 0;
511
079d88cc
WF		 512 /*
513 * expand ELD's speaker allocation mask
514 *
515 * ELD tells the speaker mask in a compact(paired) form,
516 * expand ELD's notions to match the ones used by Audio InfoFrame.
517 */
518 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
519 if (eld->spk_alloc & (1 << i))
520 spk_mask |= eld_speaker_allocation_bits[i];
521 }
522
523 /* search for the first working match in the CA table */
524 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
525 if (channels == channel_allocations[i].channels &&
526 (spk_mask & channel_allocations[i].spk_mask) ==
527 channel_allocations[i].spk_mask) {
53d7d69d 528 ca = channel_allocations[i].ca_index;
079d88cc
WF		 529 break;
530 }
531 }
532
533 snd_print_channel_allocation(eld->spk_alloc, buf, sizeof(buf));
2abbf439 534 snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n",
53d7d69d 535 ca, channels, buf);
079d88cc 536
53d7d69d 537 return ca;
079d88cc
WF		 538}
539
540static void hdmi_debug_channel_mapping(struct hda_codec *codec,
541 hda_nid_t pin_nid)
542{
543#ifdef CONFIG_SND_DEBUG_VERBOSE
544 int i;
545 int slot;
546
547 for (i = 0; i < 8; i++) {
548 slot = snd_hda_codec_read(codec, pin_nid, 0,
549 AC_VERB_GET_HDMI_CHAN_SLOT, i);
550 printk(KERN_DEBUG "HDMI: ASP channel %d => slot %d\n",
551 slot >> 4, slot & 0xf);
552 }
553#endif
554}
555
556
d45e6889 557static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
079d88cc 558 hda_nid_t pin_nid,
433968da 559 bool non_pcm,
53d7d69d 560 int ca)
079d88cc
WF		 561{
562 int i;
079d88cc 563 int err;
72357c78 564 int order;
433968da 565 int non_pcm_mapping[8];
079d88cc 566
72357c78 567 order = get_channel_allocation_order(ca);
433968da 568
079d88cc 569 if (hdmi_channel_mapping[ca][1] == 0) {
72357c78 570 for (i = 0; i < channel_allocations[order].channels; i++)
079d88cc
WF		 571 hdmi_channel_mapping[ca][i] = i | (i << 4);
572 for (; i < 8; i++)
573 hdmi_channel_mapping[ca][i] = 0xf | (i << 4);
574 }
575
433968da
WX		 576 if (non_pcm) {
577 for (i = 0; i < channel_allocations[order].channels; i++)
578 non_pcm_mapping[i] = i | (i << 4);
579 for (; i < 8; i++)
580 non_pcm_mapping[i] = 0xf | (i << 4);
581 }
582
079d88cc
WF		 583 for (i = 0; i < 8; i++) {
584 err = snd_hda_codec_write(codec, pin_nid, 0,
585 AC_VERB_SET_HDMI_CHAN_SLOT,
433968da 586 non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i]);
079d88cc 587 if (err) {
2abbf439
WF		 588 snd_printdd(KERN_NOTICE
589 "HDMI: channel mapping failed\n");
079d88cc
WF		 590 break;
591 }
592 }
593
594 hdmi_debug_channel_mapping(codec, pin_nid);
595}
596
d45e6889
TI		 597struct channel_map_table {
598 unsigned char map; /* ALSA API channel map position */
599 unsigned char cea_slot; /* CEA slot value */
600 int spk_mask; /* speaker position bit mask */
601};
602
603static struct channel_map_table map_tables[] = {
604 { SNDRV_CHMAP_FL, 0x00, FL },
605 { SNDRV_CHMAP_FR, 0x01, FR },
606 { SNDRV_CHMAP_RL, 0x04, RL },
607 { SNDRV_CHMAP_RR, 0x05, RR },
608 { SNDRV_CHMAP_LFE, 0x02, LFE },
609 { SNDRV_CHMAP_FC, 0x03, FC },
610 { SNDRV_CHMAP_RLC, 0x06, RLC },
611 { SNDRV_CHMAP_RRC, 0x07, RRC },
612 {} /* terminator */
613};
614
615/* from ALSA API channel position to speaker bit mask */
616static int to_spk_mask(unsigned char c)
617{
618 struct channel_map_table *t = map_tables;
619 for (; t->map; t++) {
620 if (t->map == c)
621 return t->spk_mask;
622 }
623 return 0;
624}
625
626/* from ALSA API channel position to CEA slot */
627static int to_cea_slot(unsigned char c)
628{
629 struct channel_map_table *t = map_tables;
630 for (; t->map; t++) {
631 if (t->map == c)
632 return t->cea_slot;
633 }
634 return 0x0f;
635}
636
637/* from CEA slot to ALSA API channel position */
638static int from_cea_slot(unsigned char c)
639{
640 struct channel_map_table *t = map_tables;
641 for (; t->map; t++) {
642 if (t->cea_slot == c)
643 return t->map;
644 }
645 return 0;
646}
647
648/* from speaker bit mask to ALSA API channel position */
649static int spk_to_chmap(int spk)
650{
651 struct channel_map_table *t = map_tables;
652 for (; t->map; t++) {
653 if (t->spk_mask == spk)
654 return t->map;
655 }
656 return 0;
657}
658
659/* get the CA index corresponding to the given ALSA API channel map */
660static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
661{
662 int i, spks = 0, spk_mask = 0;
663
664 for (i = 0; i < chs; i++) {
665 int mask = to_spk_mask(map[i]);
666 if (mask) {
667 spk_mask |= mask;
668 spks++;
669 }
670 }
671
672 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
673 if ((chs == channel_allocations[i].channels ||
674 spks == channel_allocations[i].channels) &&
675 (spk_mask & channel_allocations[i].spk_mask) ==
676 channel_allocations[i].spk_mask)
677 return channel_allocations[i].ca_index;
678 }
679 return -1;
680}
681
682/* set up the channel slots for the given ALSA API channel map */
683static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
684 hda_nid_t pin_nid,
685 int chs, unsigned char *map)
686{
687 int i;
688 for (i = 0; i < 8; i++) {
689 int val, err;
690 if (i < chs)
691 val = to_cea_slot(map[i]);
692 else
693 val = 0xf;
694 val |= (i << 4);
695 err = snd_hda_codec_write(codec, pin_nid, 0,
696 AC_VERB_SET_HDMI_CHAN_SLOT, val);
697 if (err)
698 return -EINVAL;
699 }
700 return 0;
701}
702
703/* store ALSA API channel map from the current default map */
704static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
705{
706 int i;
707 for (i = 0; i < 8; i++) {
708 if (i < channel_allocations[ca].channels)
709 map[i] = from_cea_slot((hdmi_channel_mapping[ca][i] >> 4) & 0x0f);
710 else
711 map[i] = 0;
712 }
713}
714
715static void hdmi_setup_channel_mapping(struct hda_codec *codec,
716 hda_nid_t pin_nid, bool non_pcm, int ca,
717 int channels, unsigned char *map)
718{
719 if (!non_pcm && map) {
720 hdmi_manual_setup_channel_mapping(codec, pin_nid,
721 channels, map);
722 } else {
723 hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
724 hdmi_setup_fake_chmap(map, ca);
725 }
726}
079d88cc
WF		 727
728/*
729 * Audio InfoFrame routines
730 */
731
732/*
733 * Enable Audio InfoFrame Transmission
734 */
735static void hdmi_start_infoframe_trans(struct hda_codec *codec,
736 hda_nid_t pin_nid)
737{
738 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
739 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
740 AC_DIPXMIT_BEST);
741}
742
743/*
744 * Disable Audio InfoFrame Transmission
745 */
746static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
747 hda_nid_t pin_nid)
748{
749 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
750 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
751 AC_DIPXMIT_DISABLE);
752}
753
754static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
755{
756#ifdef CONFIG_SND_DEBUG_VERBOSE
757 int i;
758 int size;
759
760 size = snd_hdmi_get_eld_size(codec, pin_nid);
761 printk(KERN_DEBUG "HDMI: ELD buf size is %d\n", size);
762
763 for (i = 0; i < 8; i++) {
764 size = snd_hda_codec_read(codec, pin_nid, 0,
765 AC_VERB_GET_HDMI_DIP_SIZE, i);
766 printk(KERN_DEBUG "HDMI: DIP GP[%d] buf size is %d\n", i, size);
767 }
768#endif
769}
770
771static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
772{
773#ifdef BE_PARANOID
774 int i, j;
775 int size;
776 int pi, bi;
777 for (i = 0; i < 8; i++) {
778 size = snd_hda_codec_read(codec, pin_nid, 0,
779 AC_VERB_GET_HDMI_DIP_SIZE, i);
780 if (size == 0)
781 continue;
782
783 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
784 for (j = 1; j < 1000; j++) {
785 hdmi_write_dip_byte(codec, pin_nid, 0x0);
786 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
787 if (pi != i)
788 snd_printd(KERN_INFO "dip index %d: %d != %d\n",
789 bi, pi, i);
790 if (bi == 0) /* byte index wrapped around */
791 break;
792 }
793 snd_printd(KERN_INFO
794 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
795 i, size, j);
796 }
797#endif
798}
799
53d7d69d 800static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
079d88cc 801{
53d7d69d 802 u8 *bytes = (u8 *)hdmi_ai;
079d88cc
WF		 803 u8 sum = 0;
804 int i;
805
53d7d69d 806 hdmi_ai->checksum = 0;
079d88cc 807
53d7d69d 808 for (i = 0; i < sizeof(*hdmi_ai); i++)
079d88cc
WF		 809 sum += bytes[i];
810
53d7d69d 811 hdmi_ai->checksum = -sum;
079d88cc
WF		 812}
813
814static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
815 hda_nid_t pin_nid,
53d7d69d 816 u8 *dip, int size)
079d88cc 817{
079d88cc
WF		 818 int i;
819
820 hdmi_debug_dip_size(codec, pin_nid);
821 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
822
079d88cc 823 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d
WF		 824 for (i = 0; i < size; i++)
825 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
079d88cc
WF		 826}
827
828static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
53d7d69d 829 u8 *dip, int size)
079d88cc 830{
079d88cc
WF		 831 u8 val;
832 int i;
833
834 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
835 != AC_DIPXMIT_BEST)
836 return false;
837
838 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d 839 for (i = 0; i < size; i++) {
079d88cc
WF		 840 val = snd_hda_codec_read(codec, pin_nid, 0,
841 AC_VERB_GET_HDMI_DIP_DATA, 0);
53d7d69d 842 if (val != dip[i])
079d88cc
WF		 843 return false;
844 }
845
846 return true;
847}
848
384a48d7 849static void hdmi_setup_audio_infoframe(struct hda_codec *codec, int pin_idx,
1a6003b5
TI		 850 bool non_pcm,
851 struct snd_pcm_substream *substream)
079d88cc
WF		 852{
853 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 854 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
855 hda_nid_t pin_nid = per_pin->pin_nid;
53d7d69d 856 int channels = substream->runtime->channels;
384a48d7 857 struct hdmi_eld *eld;
53d7d69d 858 int ca;
2b203dbb 859 union audio_infoframe ai;
079d88cc 860
384a48d7
SW		 861 eld = &spec->pins[pin_idx].sink_eld;
862 if (!eld->monitor_present)
863 return;
079d88cc 864
d45e6889
TI		 865 if (!non_pcm && per_pin->chmap_set)
866 ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
867 else
868 ca = hdmi_channel_allocation(eld, channels);
869 if (ca < 0)
870 ca = 0;
384a48d7
SW		 871
872 memset(&ai, 0, sizeof(ai));
873 if (eld->conn_type == 0) { /* HDMI */
874 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
875
876 hdmi_ai->type = 0x84;
877 hdmi_ai->ver = 0x01;
878 hdmi_ai->len = 0x0a;
879 hdmi_ai->CC02_CT47 = channels - 1;
880 hdmi_ai->CA = ca;
881 hdmi_checksum_audio_infoframe(hdmi_ai);
882 } else if (eld->conn_type == 1) { /* DisplayPort */
883 struct dp_audio_infoframe *dp_ai = &ai.dp;
884
885 dp_ai->type = 0x84;
886 dp_ai->len = 0x1b;
887 dp_ai->ver = 0x11 << 2;
888 dp_ai->CC02_CT47 = channels - 1;
889 dp_ai->CA = ca;
890 } else {
891 snd_printd("HDMI: unknown connection type at pin %d\n",
892 pin_nid);
893 return;
894 }
53d7d69d 895
384a48d7
SW		 896 /*
897 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
898 * sizeof(*dp_ai) to avoid partial match/update problems when
899 * the user switches between HDMI/DP monitors.
900 */
901 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
902 sizeof(ai))) {
903 snd_printdd("hdmi_setup_audio_infoframe: "
904 "pin=%d channels=%d\n",
905 pin_nid,
906 channels);
d45e6889
TI		 907 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
908 channels, per_pin->chmap);
384a48d7
SW		 909 hdmi_stop_infoframe_trans(codec, pin_nid);
910 hdmi_fill_audio_infoframe(codec, pin_nid,
911 ai.bytes, sizeof(ai));
912 hdmi_start_infoframe_trans(codec, pin_nid);
2d7e887c
WX		 913 } else {
914 /* For non-pcm audio switch, setup new channel mapping
915 * accordingly */
1a6003b5 916 if (per_pin->non_pcm != non_pcm)
d45e6889
TI		 917 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
918 channels, per_pin->chmap);
079d88cc 919 }
433968da 920
1a6003b5 921 per_pin->non_pcm = non_pcm;
079d88cc
WF		 922}
923
924
925/*
926 * Unsolicited events
927 */
928
c6e8453e 929static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
38faddb1 930
079d88cc
WF		 931static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
932{
933 struct hdmi_spec *spec = codec->spec;
3a93897e
TI		 934 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
935 int pin_nid;
384a48d7 936 int pin_idx;
3a93897e
TI		 937 struct hda_jack_tbl *jack;
938
939 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
940 if (!jack)
941 return;
942 pin_nid = jack->nid;
943 jack->jack_dirty = 1;
079d88cc 944
fae3d88a 945 _snd_printd(SND_PR_VERBOSE,
384a48d7 946 "HDMI hot plug event: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
fae3d88a
FW		 947 codec->addr, pin_nid,
948 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
079d88cc 949
384a48d7
SW		 950 pin_idx = pin_nid_to_pin_index(spec, pin_nid);
951 if (pin_idx < 0)
079d88cc
WF		 952 return;
953
c6e8453e 954 hdmi_present_sense(&spec->pins[pin_idx], 1);
01a61e12 955 snd_hda_jack_report_sync(codec);
079d88cc
WF		 956}
957
958static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
959{
960 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
961 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
962 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
963 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
964
965 printk(KERN_INFO
e9ea8e8f 966 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
384a48d7 967 codec->addr,
079d88cc
WF		 968 tag,
969 subtag,
970 cp_state,
971 cp_ready);
972
973 /* TODO */
974 if (cp_state)
975 ;
976 if (cp_ready)
977 ;
978}
979
980
981static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
982{
079d88cc
WF		 983 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
984 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
985
3a93897e 986 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
079d88cc
WF		 987 snd_printd(KERN_INFO "Unexpected HDMI event tag 0x%x\n", tag);
988 return;
989 }
990
991 if (subtag == 0)
992 hdmi_intrinsic_event(codec, res);
993 else
994 hdmi_non_intrinsic_event(codec, res);
995}
996
997/*
998 * Callbacks
999 */
1000
92f10b3f
TI		 1001/* HBR should be Non-PCM, 8 channels */
1002#define is_hbr_format(format) \
1003 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
1004
384a48d7
SW		 1005static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
1006 hda_nid_t pin_nid, u32 stream_tag, int format)
079d88cc 1007{
ea87d1c4
AH		 1008 int pinctl;
1009 int new_pinctl = 0;
ea87d1c4 1010
384a48d7
SW		 1011 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
1012 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
ea87d1c4
AH		 1013 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1014
1015 new_pinctl = pinctl & ~AC_PINCTL_EPT;
92f10b3f 1016 if (is_hbr_format(format))
ea87d1c4
AH		 1017 new_pinctl |= AC_PINCTL_EPT_HBR;
1018 else
1019 new_pinctl |= AC_PINCTL_EPT_NATIVE;
1020
1021 snd_printdd("hdmi_setup_stream: "
1022 "NID=0x%x, %spinctl=0x%x\n",
384a48d7 1023 pin_nid,
ea87d1c4
AH		 1024 pinctl == new_pinctl ? "" : "new-",
1025 new_pinctl);
1026
1027 if (pinctl != new_pinctl)
384a48d7 1028 snd_hda_codec_write(codec, pin_nid, 0,
ea87d1c4
AH		 1029 AC_VERB_SET_PIN_WIDGET_CONTROL,
1030 new_pinctl);
ea87d1c4 1031
384a48d7 1032 }
92f10b3f 1033 if (is_hbr_format(format) && !new_pinctl) {
ea87d1c4
AH		 1034 snd_printdd("hdmi_setup_stream: HBR is not supported\n");
1035 return -EINVAL;
1036 }
079d88cc 1037
384a48d7 1038 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
ea87d1c4 1039 return 0;
079d88cc
WF		 1040}
1041
bbbe3390
TI		 1042/*
1043 * HDA PCM callbacks
1044 */
1045static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1046 struct hda_codec *codec,
1047 struct snd_pcm_substream *substream)
1048{
1049 struct hdmi_spec *spec = codec->spec;
639cef0e 1050 struct snd_pcm_runtime *runtime = substream->runtime;
384a48d7
SW		 1051 int pin_idx, cvt_idx, mux_idx = 0;
1052 struct hdmi_spec_per_pin *per_pin;
1053 struct hdmi_eld *eld;
1054 struct hdmi_spec_per_cvt *per_cvt = NULL;
bbbe3390 1055
384a48d7
SW		 1056 /* Validate hinfo */
1057 pin_idx = hinfo_to_pin_index(spec, hinfo);
1058 if (snd_BUG_ON(pin_idx < 0))
bbbe3390 1059 return -EINVAL;
384a48d7
SW		 1060 per_pin = &spec->pins[pin_idx];
1061 eld = &per_pin->sink_eld;
1062
1063 /* Dynamically assign converter to stream */
1064 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1065 per_cvt = &spec->cvts[cvt_idx];
bbbe3390 1066
384a48d7
SW		 1067 /* Must not already be assigned */
1068 if (per_cvt->assigned)
1069 continue;
1070 /* Must be in pin's mux's list of converters */
1071 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1072 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1073 break;
1074 /* Not in mux list */
1075 if (mux_idx == per_pin->num_mux_nids)
1076 continue;
1077 break;
1078 }
1079 /* No free converters */
1080 if (cvt_idx == spec->num_cvts)
1081 return -ENODEV;
1082
1083 /* Claim converter */
1084 per_cvt->assigned = 1;
1085 hinfo->nid = per_cvt->cvt_nid;
1086
1087 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1088 AC_VERB_SET_CONNECT_SEL,
1089 mux_idx);
384a48d7 1090 snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
bbbe3390 1091
2def8172 1092 /* Initially set the converter's capabilities */
384a48d7
SW		 1093 hinfo->channels_min = per_cvt->channels_min;
1094 hinfo->channels_max = per_cvt->channels_max;
1095 hinfo->rates = per_cvt->rates;
1096 hinfo->formats = per_cvt->formats;
1097 hinfo->maxbps = per_cvt->maxbps;
2def8172 1098
384a48d7 1099 /* Restrict capabilities by ELD if this isn't disabled */
c3d52105 1100 if (!static_hdmi_pcm && eld->eld_valid) {
2def8172 1101 snd_hdmi_eld_update_pcm_info(eld, hinfo);
bbbe3390
TI		 1102 if (hinfo->channels_min > hinfo->channels_max ||
1103 !hinfo->rates || !hinfo->formats)
1104 return -ENODEV;
bbbe3390 1105 }
2def8172
SW		 1106
1107 /* Store the updated parameters */
639cef0e
TI		 1108 runtime->hw.channels_min = hinfo->channels_min;
1109 runtime->hw.channels_max = hinfo->channels_max;
1110 runtime->hw.formats = hinfo->formats;
1111 runtime->hw.rates = hinfo->rates;
4fe2ca14
TI		 1112
1113 snd_pcm_hw_constraint_step(substream->runtime, 0,
1114 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
bbbe3390
TI		 1115 return 0;
1116}
1117
079d88cc
WF		 1118/*
1119 * HDA/HDMI auto parsing
1120 */
384a48d7 1121static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
079d88cc
WF		 1122{
1123 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1124 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
1125 hda_nid_t pin_nid = per_pin->pin_nid;
079d88cc
WF		 1126
1127 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1128 snd_printk(KERN_WARNING
1129 "HDMI: pin %d wcaps %#x "
1130 "does not support connection list\n",
1131 pin_nid, get_wcaps(codec, pin_nid));
1132 return -EINVAL;
1133 }
1134
384a48d7
SW		 1135 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1136 per_pin->mux_nids,
1137 HDA_MAX_CONNECTIONS);
079d88cc
WF		 1138
1139 return 0;
1140}
1141
c6e8453e 1142static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
079d88cc 1143{
744626da
WF		 1144 struct hda_codec *codec = per_pin->codec;
1145 struct hdmi_eld *eld = &per_pin->sink_eld;
1146 hda_nid_t pin_nid = per_pin->pin_nid;
5d44f927
SW		 1147 /*
1148 * Always execute a GetPinSense verb here, even when called from
1149 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1150 * response's PD bit is not the real PD value, but indicates that
1151 * the real PD value changed. An older version of the HD-audio
1152 * specification worked this way. Hence, we just ignore the data in
1153 * the unsolicited response to avoid custom WARs.
1154 */
079d88cc 1155 int present = snd_hda_pin_sense(codec, pin_nid);
b95d68b8 1156 bool eld_valid = false;
079d88cc 1157
b95d68b8 1158 memset(eld, 0, offsetof(struct hdmi_eld, eld_buffer));
5d44f927 1159
079d88cc 1160 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
5d44f927 1161 if (eld->monitor_present)
b95d68b8 1162 eld_valid = !!(present & AC_PINSENSE_ELDV);
079d88cc 1163
fae3d88a 1164 _snd_printd(SND_PR_VERBOSE,
384a48d7 1165 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
b95d68b8 1166 codec->addr, pin_nid, eld->monitor_present, eld_valid);
5d44f927 1167
744626da 1168 if (eld_valid) {
5d44f927
SW		 1169 if (!snd_hdmi_get_eld(eld, codec, pin_nid))
1170 snd_hdmi_show_eld(eld);
c6e8453e 1171 else if (repoll) {
744626da
WF		 1172 queue_delayed_work(codec->bus->workq,
1173 &per_pin->work,
1174 msecs_to_jiffies(300));
1175 }
1176 }
079d88cc
WF		 1177}
1178
744626da
WF		 1179static void hdmi_repoll_eld(struct work_struct *work)
1180{
1181 struct hdmi_spec_per_pin *per_pin =
1182 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1183
c6e8453e
WF		 1184 if (per_pin->repoll_count++ > 6)
1185 per_pin->repoll_count = 0;
1186
1187 hdmi_present_sense(per_pin, per_pin->repoll_count);
744626da
WF		 1188}
1189
079d88cc
WF		 1190static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1191{
1192 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1193 unsigned int caps, config;
1194 int pin_idx;
1195 struct hdmi_spec_per_pin *per_pin;
07acecc1 1196 int err;
079d88cc 1197
efc2f8de 1198 caps = snd_hda_query_pin_caps(codec, pin_nid);
384a48d7
SW		 1199 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1200 return 0;
1201
efc2f8de 1202 config = snd_hda_codec_get_pincfg(codec, pin_nid);
384a48d7
SW		 1203 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1204 return 0;
1205
1206 if (snd_BUG_ON(spec->num_pins >= MAX_HDMI_PINS))
3eaead57 1207 return -E2BIG;
384a48d7
SW		 1208
1209 pin_idx = spec->num_pins;
1210 per_pin = &spec->pins[pin_idx];
384a48d7
SW		 1211
1212 per_pin->pin_nid = pin_nid;
1a6003b5 1213 per_pin->non_pcm = false;
079d88cc 1214
384a48d7
SW		 1215 err = hdmi_read_pin_conn(codec, pin_idx);
1216 if (err < 0)
1217 return err;
079d88cc 1218
079d88cc
WF		 1219 spec->num_pins++;
1220
384a48d7 1221 return 0;
079d88cc
WF		 1222}
1223
384a48d7 1224static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc
WF		 1225{
1226 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1227 int cvt_idx;
1228 struct hdmi_spec_per_cvt *per_cvt;
1229 unsigned int chans;
1230 int err;
079d88cc 1231
116dcde6
DH		 1232 if (snd_BUG_ON(spec->num_cvts >= MAX_HDMI_CVTS))
1233 return -E2BIG;
1234
384a48d7
SW		 1235 chans = get_wcaps(codec, cvt_nid);
1236 chans = get_wcaps_channels(chans);
1237
1238 cvt_idx = spec->num_cvts;
1239 per_cvt = &spec->cvts[cvt_idx];
1240
1241 per_cvt->cvt_nid = cvt_nid;
1242 per_cvt->channels_min = 2;
d45e6889 1243 if (chans <= 16) {
384a48d7 1244 per_cvt->channels_max = chans;
d45e6889
TI		 1245 if (chans > spec->channels_max)
1246 spec->channels_max = chans;
1247 }
384a48d7
SW		 1248
1249 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1250 &per_cvt->rates,
1251 &per_cvt->formats,
1252 &per_cvt->maxbps);
1253 if (err < 0)
1254 return err;
1255
079d88cc
WF		 1256 spec->num_cvts++;
1257
1258 return 0;
1259}
1260
1261static int hdmi_parse_codec(struct hda_codec *codec)
1262{
1263 hda_nid_t nid;
1264 int i, nodes;
1265
1266 nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid);
1267 if (!nid || nodes < 0) {
1268 snd_printk(KERN_WARNING "HDMI: failed to get afg sub nodes\n");
1269 return -EINVAL;
1270 }
1271
1272 for (i = 0; i < nodes; i++, nid++) {
1273 unsigned int caps;
1274 unsigned int type;
1275
efc2f8de 1276 caps = get_wcaps(codec, nid);
079d88cc
WF		 1277 type = get_wcaps_type(caps);
1278
1279 if (!(caps & AC_WCAP_DIGITAL))
1280 continue;
1281
1282 switch (type) {
1283 case AC_WID_AUD_OUT:
384a48d7 1284 hdmi_add_cvt(codec, nid);
079d88cc
WF		 1285 break;
1286 case AC_WID_PIN:
3eaead57 1287 hdmi_add_pin(codec, nid);
079d88cc
WF		 1288 break;
1289 }
1290 }
1291
c9adeefd
DH		 1292#ifdef CONFIG_PM
1293 /* We're seeing some problems with unsolicited hot plug events on
1294 * PantherPoint after S3, if this is not enabled */
1295 if (codec->vendor_id == 0x80862806)
1296 codec->bus->power_keep_link_on = 1;
079d88cc
WF		 1297 /*
1298 * G45/IbexPeak don't support EPSS: the unsolicited pin hot plug event
1299 * can be lost and presence sense verb will become inaccurate if the
1300 * HDA link is powered off at hot plug or hw initialization time.
1301 */
c9adeefd 1302 else if (!(snd_hda_param_read(codec, codec->afg, AC_PAR_POWER_STATE) &
079d88cc
WF		 1303 AC_PWRST_EPSS))
1304 codec->bus->power_keep_link_on = 1;
1305#endif
1306
1307 return 0;
1308}
1309
84eb01be
TI		 1310/*
1311 */
a4567cb3
TI		 1312static char *get_hdmi_pcm_name(int idx)
1313{
1314 static char names[MAX_HDMI_PINS][8];
1315 sprintf(&names[idx][0], "HDMI %d", idx);
1316 return &names[idx][0];
1317}
84eb01be 1318
1a6003b5
TI		 1319static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1320{
1321 struct hda_spdif_out *spdif;
1322 bool non_pcm;
1323
1324 mutex_lock(&codec->spdif_mutex);
1325 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1326 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1327 mutex_unlock(&codec->spdif_mutex);
1328 return non_pcm;
1329}
1330
1331
84eb01be
TI		 1332/*
1333 * HDMI callbacks
1334 */
1335
1336static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1337 struct hda_codec *codec,
1338 unsigned int stream_tag,
1339 unsigned int format,
1340 struct snd_pcm_substream *substream)
1341{
384a48d7
SW		 1342 hda_nid_t cvt_nid = hinfo->nid;
1343 struct hdmi_spec *spec = codec->spec;
1344 int pin_idx = hinfo_to_pin_index(spec, hinfo);
1345 hda_nid_t pin_nid = spec->pins[pin_idx].pin_nid;
1a6003b5
TI		 1346 bool non_pcm;
1347
1348 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
384a48d7
SW		 1349
1350 hdmi_set_channel_count(codec, cvt_nid, substream->runtime->channels);
84eb01be 1351
1a6003b5 1352 hdmi_setup_audio_infoframe(codec, pin_idx, non_pcm, substream);
84eb01be 1353
384a48d7 1354 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
84eb01be
TI		 1355}
1356
8dfaa573
TI		 1357static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1358 struct hda_codec *codec,
1359 struct snd_pcm_substream *substream)
1360{
1361 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1362 return 0;
1363}
1364
f2ad24fa
TI		 1365static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1366 struct hda_codec *codec,
1367 struct snd_pcm_substream *substream)
384a48d7
SW		 1368{
1369 struct hdmi_spec *spec = codec->spec;
1370 int cvt_idx, pin_idx;
1371 struct hdmi_spec_per_cvt *per_cvt;
1372 struct hdmi_spec_per_pin *per_pin;
384a48d7 1373
384a48d7
SW		 1374 if (hinfo->nid) {
1375 cvt_idx = cvt_nid_to_cvt_index(spec, hinfo->nid);
1376 if (snd_BUG_ON(cvt_idx < 0))
1377 return -EINVAL;
1378 per_cvt = &spec->cvts[cvt_idx];
1379
1380 snd_BUG_ON(!per_cvt->assigned);
1381 per_cvt->assigned = 0;
1382 hinfo->nid = 0;
1383
1384 pin_idx = hinfo_to_pin_index(spec, hinfo);
1385 if (snd_BUG_ON(pin_idx < 0))
1386 return -EINVAL;
1387 per_pin = &spec->pins[pin_idx];
1388
384a48d7 1389 snd_hda_spdif_ctls_unassign(codec, pin_idx);
d45e6889
TI		 1390 per_pin->chmap_set = false;
1391 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
384a48d7 1392 }
d45e6889 1393
384a48d7
SW		 1394 return 0;
1395}
1396
1397static const struct hda_pcm_ops generic_ops = {
1398 .open = hdmi_pcm_open,
f2ad24fa 1399 .close = hdmi_pcm_close,
384a48d7 1400 .prepare = generic_hdmi_playback_pcm_prepare,
8dfaa573 1401 .cleanup = generic_hdmi_playback_pcm_cleanup,
84eb01be
TI		 1402};
1403
d45e6889
TI		 1404/*
1405 * ALSA API channel-map control callbacks
1406 */
1407static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
1408 struct snd_ctl_elem_info *uinfo)
1409{
1410 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1411 struct hda_codec *codec = info->private_data;
1412 struct hdmi_spec *spec = codec->spec;
1413 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1414 uinfo->count = spec->channels_max;
1415 uinfo->value.integer.min = 0;
1416 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
1417 return 0;
1418}
1419
1420static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
1421 unsigned int size, unsigned int __user *tlv)
1422{
1423 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1424 struct hda_codec *codec = info->private_data;
1425 struct hdmi_spec *spec = codec->spec;
1426 const unsigned int valid_mask =
1427 FL | FR | RL | RR | LFE | FC | RLC | RRC;
1428 unsigned int __user *dst;
1429 int chs, count = 0;
1430
1431 if (size < 8)
1432 return -ENOMEM;
1433 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
1434 return -EFAULT;
1435 size -= 8;
1436 dst = tlv + 2;
498dab3a 1437 for (chs = 2; chs <= spec->channels_max; chs++) {
d45e6889
TI		 1438 int i, c;
1439 struct cea_channel_speaker_allocation *cap;
1440 cap = channel_allocations;
1441 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
1442 int chs_bytes = chs * 4;
1443 if (cap->channels != chs)
1444 continue;
1445 if (cap->spk_mask & ~valid_mask)
1446 continue;
1447 if (size < 8)
1448 return -ENOMEM;
1449 if (put_user(SNDRV_CTL_TLVT_CHMAP_VAR, dst) ||
1450 put_user(chs_bytes, dst + 1))
1451 return -EFAULT;
1452 dst += 2;
1453 size -= 8;
1454 count += 8;
1455 if (size < chs_bytes)
1456 return -ENOMEM;
1457 size -= chs_bytes;
1458 count += chs_bytes;
1459 for (c = 7; c >= 0; c--) {
1460 int spk = cap->speakers[c];
1461 if (!spk)
1462 continue;
1463 if (put_user(spk_to_chmap(spk), dst))
1464 return -EFAULT;
1465 dst++;
1466 }
1467 }
1468 }
1469 if (put_user(count, tlv + 1))
1470 return -EFAULT;
1471 return 0;
1472}
1473
1474static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
1475 struct snd_ctl_elem_value *ucontrol)
1476{
1477 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1478 struct hda_codec *codec = info->private_data;
1479 struct hdmi_spec *spec = codec->spec;
1480 int pin_idx = kcontrol->private_value;
1481 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
1482 int i;
1483
1484 for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
1485 ucontrol->value.integer.value[i] = per_pin->chmap[i];
1486 return 0;
1487}
1488
1489static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
1490 struct snd_ctl_elem_value *ucontrol)
1491{
1492 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1493 struct hda_codec *codec = info->private_data;
1494 struct hdmi_spec *spec = codec->spec;
1495 int pin_idx = kcontrol->private_value;
1496 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
1497 unsigned int ctl_idx;
1498 struct snd_pcm_substream *substream;
1499 unsigned char chmap[8];
1500 int i, ca, prepared = 0;
1501
1502 ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
1503 substream = snd_pcm_chmap_substream(info, ctl_idx);
1504 if (!substream || !substream->runtime)
1505 return -EBADFD;
1506 switch (substream->runtime->status->state) {
1507 case SNDRV_PCM_STATE_OPEN:
1508 case SNDRV_PCM_STATE_SETUP:
1509 break;
1510 case SNDRV_PCM_STATE_PREPARED:
1511 prepared = 1;
1512 break;
1513 default:
1514 return -EBUSY;
1515 }
1516 memset(chmap, 0, sizeof(chmap));
1517 for (i = 0; i < ARRAY_SIZE(chmap); i++)
1518 chmap[i] = ucontrol->value.integer.value[i];
1519 if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
1520 return 0;
1521 ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
1522 if (ca < 0)
1523 return -EINVAL;
1524 per_pin->chmap_set = true;
1525 memcpy(per_pin->chmap, chmap, sizeof(chmap));
1526 if (prepared)
1527 hdmi_setup_audio_infoframe(codec, pin_idx, per_pin->non_pcm,
1528 substream);
1529
1530 return 0;
1531}
1532
84eb01be
TI		 1533static int generic_hdmi_build_pcms(struct hda_codec *codec)
1534{
1535 struct hdmi_spec *spec = codec->spec;
384a48d7 1536 int pin_idx;
84eb01be 1537
384a48d7
SW		 1538 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1539 struct hda_pcm *info;
84eb01be
TI		 1540 struct hda_pcm_stream *pstr;
1541
384a48d7 1542 info = &spec->pcm_rec[pin_idx];
a4567cb3 1543 info->name = get_hdmi_pcm_name(pin_idx);
84eb01be 1544 info->pcm_type = HDA_PCM_TYPE_HDMI;
d45e6889 1545 info->own_chmap = true;
384a48d7 1546
84eb01be 1547 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
384a48d7
SW		 1548 pstr->substreams = 1;
1549 pstr->ops = generic_ops;
1550 /* other pstr fields are set in open */
84eb01be
TI		 1551 }
1552
384a48d7
SW		 1553 codec->num_pcms = spec->num_pins;
1554 codec->pcm_info = spec->pcm_rec;
1555
84eb01be
TI		 1556 return 0;
1557}
1558
0b6c49b5
DH		 1559static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
1560{
31ef2257 1561 char hdmi_str[32] = "HDMI/DP";
0b6c49b5
DH		 1562 struct hdmi_spec *spec = codec->spec;
1563 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
1564 int pcmdev = spec->pcm_rec[pin_idx].device;
1565
31ef2257
TI		 1566 if (pcmdev > 0)
1567 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
0b6c49b5 1568
31ef2257 1569 return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, 0);
0b6c49b5
DH		 1570}
1571
84eb01be
TI		 1572static int generic_hdmi_build_controls(struct hda_codec *codec)
1573{
1574 struct hdmi_spec *spec = codec->spec;
1575 int err;
384a48d7 1576 int pin_idx;
84eb01be 1577
384a48d7
SW		 1578 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1579 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
0b6c49b5
DH		 1580
1581 err = generic_hdmi_build_jack(codec, pin_idx);
1582 if (err < 0)
1583 return err;
1584
dcda5806
TI		 1585 err = snd_hda_create_dig_out_ctls(codec,
1586 per_pin->pin_nid,
1587 per_pin->mux_nids[0],
1588 HDA_PCM_TYPE_HDMI);
84eb01be
TI		 1589 if (err < 0)
1590 return err;
384a48d7 1591 snd_hda_spdif_ctls_unassign(codec, pin_idx);
14bc52b8
PLB		 1592
1593 /* add control for ELD Bytes */
1594 err = hdmi_create_eld_ctl(codec,
1595 pin_idx,
1596 spec->pcm_rec[pin_idx].device);
1597
1598 if (err < 0)
1599 return err;
31ef2257 1600
82b1d73f 1601 hdmi_present_sense(per_pin, 0);
84eb01be
TI		 1602 }
1603
d45e6889
TI		 1604 /* add channel maps */
1605 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1606 struct snd_pcm_chmap *chmap;
1607 struct snd_kcontrol *kctl;
1608 int i;
1609 err = snd_pcm_add_chmap_ctls(codec->pcm_info[pin_idx].pcm,
1610 SNDRV_PCM_STREAM_PLAYBACK,
1611 NULL, 0, pin_idx, &chmap);
1612 if (err < 0)
1613 return err;
1614 /* override handlers */
1615 chmap->private_data = codec;
1616 kctl = chmap->kctl;
1617 for (i = 0; i < kctl->count; i++)
1618 kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
1619 kctl->info = hdmi_chmap_ctl_info;
1620 kctl->get = hdmi_chmap_ctl_get;
1621 kctl->put = hdmi_chmap_ctl_put;
1622 kctl->tlv.c = hdmi_chmap_ctl_tlv;
1623 }
1624
84eb01be
TI		 1625 return 0;
1626}
1627
8b8d654b 1628static int generic_hdmi_init_per_pins(struct hda_codec *codec)
84eb01be
TI		 1629{
1630 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1631 int pin_idx;
1632
1633 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1634 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
384a48d7 1635 struct hdmi_eld *eld = &per_pin->sink_eld;
84eb01be 1636
744626da
WF		 1637 per_pin->codec = codec;
1638 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
384a48d7 1639 snd_hda_eld_proc_new(codec, eld, pin_idx);
84eb01be 1640 }
8b8d654b
TI		 1641 return 0;
1642}
1643
1644static int generic_hdmi_init(struct hda_codec *codec)
1645{
1646 struct hdmi_spec *spec = codec->spec;
1647 int pin_idx;
1648
1649 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1650 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
1651 hda_nid_t pin_nid = per_pin->pin_nid;
1652
1653 hdmi_init_pin(codec, pin_nid);
1654 snd_hda_jack_detect_enable(codec, pin_nid, pin_nid);
1655 }
84eb01be
TI		 1656 return 0;
1657}
1658
1659static void generic_hdmi_free(struct hda_codec *codec)
1660{
1661 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1662 int pin_idx;
1663
1664 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1665 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
1666 struct hdmi_eld *eld = &per_pin->sink_eld;
84eb01be 1667
744626da 1668 cancel_delayed_work(&per_pin->work);
384a48d7
SW		 1669 snd_hda_eld_proc_free(codec, eld);
1670 }
84eb01be 1671
744626da 1672 flush_workqueue(codec->bus->workq);
84eb01be
TI		 1673 kfree(spec);
1674}
1675
fb79e1e0 1676static const struct hda_codec_ops generic_hdmi_patch_ops = {
84eb01be
TI		 1677 .init = generic_hdmi_init,
1678 .free = generic_hdmi_free,
1679 .build_pcms = generic_hdmi_build_pcms,
1680 .build_controls = generic_hdmi_build_controls,
1681 .unsol_event = hdmi_unsol_event,
1682};
1683
1684static int patch_generic_hdmi(struct hda_codec *codec)
1685{
1686 struct hdmi_spec *spec;
84eb01be
TI		 1687
1688 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1689 if (spec == NULL)
1690 return -ENOMEM;
1691
1692 codec->spec = spec;
1693 if (hdmi_parse_codec(codec) < 0) {
1694 codec->spec = NULL;
1695 kfree(spec);
1696 return -EINVAL;
1697 }
1698 codec->patch_ops = generic_hdmi_patch_ops;
8b8d654b 1699 generic_hdmi_init_per_pins(codec);
84eb01be 1700
84eb01be
TI		 1701 init_channel_allocations();
1702
1703 return 0;
1704}
1705
3aaf8980
SW		 1706/*
1707 * Shared non-generic implementations
1708 */
1709
1710static int simple_playback_build_pcms(struct hda_codec *codec)
1711{
1712 struct hdmi_spec *spec = codec->spec;
1713 struct hda_pcm *info = spec->pcm_rec;
8ceb332d
TI		 1714 unsigned int chans;
1715 struct hda_pcm_stream *pstr;
3aaf8980 1716
8ceb332d 1717 codec->num_pcms = 1;
3aaf8980
SW		 1718 codec->pcm_info = info;
1719
8ceb332d
TI		 1720 chans = get_wcaps(codec, spec->cvts[0].cvt_nid);
1721 chans = get_wcaps_channels(chans);
3aaf8980 1722
8ceb332d
TI		 1723 info->name = get_hdmi_pcm_name(0);
1724 info->pcm_type = HDA_PCM_TYPE_HDMI;
1725 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
1726 *pstr = spec->pcm_playback;
1727 pstr->nid = spec->cvts[0].cvt_nid;
1728 if (pstr->channels_max <= 2 && chans && chans <= 16)
1729 pstr->channels_max = chans;
3aaf8980
SW		 1730
1731 return 0;
1732}
1733
4b6ace9e
TI		 1734/* unsolicited event for jack sensing */
1735static void simple_hdmi_unsol_event(struct hda_codec *codec,
1736 unsigned int res)
1737{
9dd8cf12 1738 snd_hda_jack_set_dirty_all(codec);
4b6ace9e
TI		 1739 snd_hda_jack_report_sync(codec);
1740}
1741
1742/* generic_hdmi_build_jack can be used for simple_hdmi, too,
1743 * as long as spec->pins[] is set correctly
1744 */
1745#define simple_hdmi_build_jack generic_hdmi_build_jack
1746
3aaf8980
SW		 1747static int simple_playback_build_controls(struct hda_codec *codec)
1748{
1749 struct hdmi_spec *spec = codec->spec;
1750 int err;
3aaf8980 1751
8ceb332d
TI		 1752 err = snd_hda_create_spdif_out_ctls(codec,
1753 spec->cvts[0].cvt_nid,
1754 spec->cvts[0].cvt_nid);
1755 if (err < 0)
1756 return err;
1757 return simple_hdmi_build_jack(codec, 0);
3aaf8980
SW		 1758}
1759
4f0110ce
TI		 1760static int simple_playback_init(struct hda_codec *codec)
1761{
1762 struct hdmi_spec *spec = codec->spec;
8ceb332d
TI		 1763 hda_nid_t pin = spec->pins[0].pin_nid;
1764
1765 snd_hda_codec_write(codec, pin, 0,
1766 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
1767 /* some codecs require to unmute the pin */
1768 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
1769 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
1770 AMP_OUT_UNMUTE);
1771 snd_hda_jack_detect_enable(codec, pin, pin);
4f0110ce
TI		 1772 return 0;
1773}
1774
3aaf8980
SW		 1775static void simple_playback_free(struct hda_codec *codec)
1776{
1777 struct hdmi_spec *spec = codec->spec;
1778
1779 kfree(spec);
1780}
1781
84eb01be
TI		 1782/*
1783 * Nvidia specific implementations
1784 */
1785
1786#define Nv_VERB_SET_Channel_Allocation 0xF79
1787#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
1788#define Nv_VERB_SET_Audio_Protection_On 0xF98
1789#define Nv_VERB_SET_Audio_Protection_Off 0xF99
1790
1791#define nvhdmi_master_con_nid_7x 0x04
1792#define nvhdmi_master_pin_nid_7x 0x05
1793
fb79e1e0 1794static const hda_nid_t nvhdmi_con_nids_7x[4] = {
84eb01be
TI		 1795 /*front, rear, clfe, rear_surr */
1796 0x6, 0x8, 0xa, 0xc,
1797};
1798
ceaa86ba
TI		 1799static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
1800 /* set audio protect on */
1801 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
1802 /* enable digital output on pin widget */
1803 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1804 {} /* terminator */
1805};
1806
1807static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
84eb01be
TI		 1808 /* set audio protect on */
1809 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
1810 /* enable digital output on pin widget */
1811 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1812 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1813 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1814 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1815 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1816 {} /* terminator */
1817};
1818
1819#ifdef LIMITED_RATE_FMT_SUPPORT
1820/* support only the safe format and rate */
1821#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
1822#define SUPPORTED_MAXBPS 16
1823#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
1824#else
1825/* support all rates and formats */
1826#define SUPPORTED_RATES \
1827 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
1828 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
1829 SNDRV_PCM_RATE_192000)
1830#define SUPPORTED_MAXBPS 24
1831#define SUPPORTED_FORMATS \
1832 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
1833#endif
1834
ceaa86ba
TI		 1835static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
1836{
1837 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
1838 return 0;
1839}
1840
1841static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
84eb01be 1842{
ceaa86ba 1843 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
84eb01be
TI		 1844 return 0;
1845}
1846
393004b2
ND		 1847static unsigned int channels_2_6_8[] = {
1848 2, 6, 8
1849};
1850
1851static unsigned int channels_2_8[] = {
1852 2, 8
1853};
1854
1855static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
1856 .count = ARRAY_SIZE(channels_2_6_8),
1857 .list = channels_2_6_8,
1858 .mask = 0,
1859};
1860
1861static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
1862 .count = ARRAY_SIZE(channels_2_8),
1863 .list = channels_2_8,
1864 .mask = 0,
1865};
1866
84eb01be
TI		 1867static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
1868 struct hda_codec *codec,
1869 struct snd_pcm_substream *substream)
1870{
1871 struct hdmi_spec *spec = codec->spec;
393004b2
ND		 1872 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
1873
1874 switch (codec->preset->id) {
1875 case 0x10de0002:
1876 case 0x10de0003:
1877 case 0x10de0005:
1878 case 0x10de0006:
1879 hw_constraints_channels = &hw_constraints_2_8_channels;
1880 break;
1881 case 0x10de0007:
1882 hw_constraints_channels = &hw_constraints_2_6_8_channels;
1883 break;
1884 default:
1885 break;
1886 }
1887
1888 if (hw_constraints_channels != NULL) {
1889 snd_pcm_hw_constraint_list(substream->runtime, 0,
1890 SNDRV_PCM_HW_PARAM_CHANNELS,
1891 hw_constraints_channels);
ad09fc9d
TI		 1892 } else {
1893 snd_pcm_hw_constraint_step(substream->runtime, 0,
1894 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
393004b2
ND		 1895 }
1896
84eb01be
TI		 1897 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
1898}
1899
1900static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
1901 struct hda_codec *codec,
1902 struct snd_pcm_substream *substream)
1903{
1904 struct hdmi_spec *spec = codec->spec;
1905 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
1906}
1907
1908static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1909 struct hda_codec *codec,
1910 unsigned int stream_tag,
1911 unsigned int format,
1912 struct snd_pcm_substream *substream)
1913{
1914 struct hdmi_spec *spec = codec->spec;
1915 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
1916 stream_tag, format, substream);
1917}
1918
d0b1252d
TI		 1919static const struct hda_pcm_stream simple_pcm_playback = {
1920 .substreams = 1,
1921 .channels_min = 2,
1922 .channels_max = 2,
1923 .ops = {
1924 .open = simple_playback_pcm_open,
1925 .close = simple_playback_pcm_close,
1926 .prepare = simple_playback_pcm_prepare
1927 },
1928};
1929
1930static const struct hda_codec_ops simple_hdmi_patch_ops = {
1931 .build_controls = simple_playback_build_controls,
1932 .build_pcms = simple_playback_build_pcms,
1933 .init = simple_playback_init,
1934 .free = simple_playback_free,
250e41ac 1935 .unsol_event = simple_hdmi_unsol_event,
d0b1252d
TI		 1936};
1937
1938static int patch_simple_hdmi(struct hda_codec *codec,
1939 hda_nid_t cvt_nid, hda_nid_t pin_nid)
1940{
1941 struct hdmi_spec *spec;
1942
1943 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1944 if (!spec)
1945 return -ENOMEM;
1946
1947 codec->spec = spec;
1948
1949 spec->multiout.num_dacs = 0; /* no analog */
1950 spec->multiout.max_channels = 2;
1951 spec->multiout.dig_out_nid = cvt_nid;
1952 spec->num_cvts = 1;
1953 spec->num_pins = 1;
1954 spec->cvts[0].cvt_nid = cvt_nid;
21cd683d 1955 spec->pins[0].pin_nid = pin_nid;
d0b1252d
TI		 1956 spec->pcm_playback = simple_pcm_playback;
1957
1958 codec->patch_ops = simple_hdmi_patch_ops;
1959
1960 return 0;
1961}
1962
1f348522
AP		 1963static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
1964 int channels)
1965{
1966 unsigned int chanmask;
1967 int chan = channels ? (channels - 1) : 1;
1968
1969 switch (channels) {
1970 default:
1971 case 0:
1972 case 2:
1973 chanmask = 0x00;
1974 break;
1975 case 4:
1976 chanmask = 0x08;
1977 break;
1978 case 6:
1979 chanmask = 0x0b;
1980 break;
1981 case 8:
1982 chanmask = 0x13;
1983 break;
1984 }
1985
1986 /* Set the audio infoframe channel allocation and checksum fields. The
1987 * channel count is computed implicitly by the hardware. */
1988 snd_hda_codec_write(codec, 0x1, 0,
1989 Nv_VERB_SET_Channel_Allocation, chanmask);
1990
1991 snd_hda_codec_write(codec, 0x1, 0,
1992 Nv_VERB_SET_Info_Frame_Checksum,
1993 (0x71 - chan - chanmask));
1994}
1995
84eb01be
TI		 1996static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
1997 struct hda_codec *codec,
1998 struct snd_pcm_substream *substream)
1999{
2000 struct hdmi_spec *spec = codec->spec;
2001 int i;
2002
2003 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2004 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2005 for (i = 0; i < 4; i++) {
2006 /* set the stream id */
2007 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2008 AC_VERB_SET_CHANNEL_STREAMID, 0);
2009 /* set the stream format */
2010 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2011 AC_VERB_SET_STREAM_FORMAT, 0);
2012 }
2013
1f348522
AP		 2014 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2015 * streams are disabled. */
2016 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2017
84eb01be
TI		 2018 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2019}
2020
2021static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2022 struct hda_codec *codec,
2023 unsigned int stream_tag,
2024 unsigned int format,
2025 struct snd_pcm_substream *substream)
2026{
2027 int chs;
112daa7a 2028 unsigned int dataDCC2, channel_id;
84eb01be 2029 int i;
7c935976 2030 struct hdmi_spec *spec = codec->spec;
e3245cdd 2031 struct hda_spdif_out *spdif;
84eb01be
TI		 2032
2033 mutex_lock(&codec->spdif_mutex);
e3245cdd 2034 spdif = snd_hda_spdif_out_of_nid(codec, spec->cvts[0].cvt_nid);
84eb01be
TI		 2035
2036 chs = substream->runtime->channels;
84eb01be 2037
84eb01be
TI		 2038 dataDCC2 = 0x2;
2039
84eb01be 2040 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
7c935976 2041 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2042 snd_hda_codec_write(codec,
2043 nvhdmi_master_con_nid_7x,
2044 0,
2045 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2046 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2047
2048 /* set the stream id */
2049 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2050 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2051
2052 /* set the stream format */
2053 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2054 AC_VERB_SET_STREAM_FORMAT, format);
2055
2056 /* turn on again (if needed) */
2057 /* enable and set the channel status audio/data flag */
7c935976 2058 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2059 snd_hda_codec_write(codec,
2060 nvhdmi_master_con_nid_7x,
2061 0,
2062 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2063 spdif->ctls & 0xff);
84eb01be
TI		 2064 snd_hda_codec_write(codec,
2065 nvhdmi_master_con_nid_7x,
2066 0,
2067 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2068 }
2069
2070 for (i = 0; i < 4; i++) {
2071 if (chs == 2)
2072 channel_id = 0;
2073 else
2074 channel_id = i * 2;
2075
2076 /* turn off SPDIF once;
2077 *otherwise the IEC958 bits won't be updated
2078 */
2079 if (codec->spdif_status_reset &&
7c935976 2080 (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2081 snd_hda_codec_write(codec,
2082 nvhdmi_con_nids_7x[i],
2083 0,
2084 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2085 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2086 /* set the stream id */
2087 snd_hda_codec_write(codec,
2088 nvhdmi_con_nids_7x[i],
2089 0,
2090 AC_VERB_SET_CHANNEL_STREAMID,
2091 (stream_tag << 4) | channel_id);
2092 /* set the stream format */
2093 snd_hda_codec_write(codec,
2094 nvhdmi_con_nids_7x[i],
2095 0,
2096 AC_VERB_SET_STREAM_FORMAT,
2097 format);
2098 /* turn on again (if needed) */
2099 /* enable and set the channel status audio/data flag */
2100 if (codec->spdif_status_reset &&
7c935976 2101 (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2102 snd_hda_codec_write(codec,
2103 nvhdmi_con_nids_7x[i],
2104 0,
2105 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2106 spdif->ctls & 0xff);
84eb01be
TI		 2107 snd_hda_codec_write(codec,
2108 nvhdmi_con_nids_7x[i],
2109 0,
2110 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2111 }
2112 }
2113
1f348522 2114 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
84eb01be
TI		 2115
2116 mutex_unlock(&codec->spdif_mutex);
2117 return 0;
2118}
2119
fb79e1e0 2120static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
84eb01be
TI		 2121 .substreams = 1,
2122 .channels_min = 2,
2123 .channels_max = 8,
2124 .nid = nvhdmi_master_con_nid_7x,
2125 .rates = SUPPORTED_RATES,
2126 .maxbps = SUPPORTED_MAXBPS,
2127 .formats = SUPPORTED_FORMATS,
2128 .ops = {
2129 .open = simple_playback_pcm_open,
2130 .close = nvhdmi_8ch_7x_pcm_close,
2131 .prepare = nvhdmi_8ch_7x_pcm_prepare
2132 },
2133};
2134
84eb01be
TI		 2135static int patch_nvhdmi_2ch(struct hda_codec *codec)
2136{
2137 struct hdmi_spec *spec;
d0b1252d
TI		 2138 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2139 nvhdmi_master_pin_nid_7x);
2140 if (err < 0)
2141 return err;
84eb01be 2142
ceaa86ba 2143 codec->patch_ops.init = nvhdmi_7x_init_2ch;
d0b1252d
TI		 2144 /* override the PCM rates, etc, as the codec doesn't give full list */
2145 spec = codec->spec;
2146 spec->pcm_playback.rates = SUPPORTED_RATES;
2147 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2148 spec->pcm_playback.formats = SUPPORTED_FORMATS;
84eb01be
TI		 2149 return 0;
2150}
2151
53775b0d
TI		 2152static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2153{
2154 struct hdmi_spec *spec = codec->spec;
2155 int err = simple_playback_build_pcms(codec);
2156 spec->pcm_rec[0].own_chmap = true;
2157 return err;
2158}
2159
2160static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2161{
2162 struct hdmi_spec *spec = codec->spec;
2163 struct snd_pcm_chmap *chmap;
2164 int err;
2165
2166 err = simple_playback_build_controls(codec);
2167 if (err < 0)
2168 return err;
2169
2170 /* add channel maps */
2171 err = snd_pcm_add_chmap_ctls(spec->pcm_rec[0].pcm,
2172 SNDRV_PCM_STREAM_PLAYBACK,
2173 snd_pcm_alt_chmaps, 8, 0, &chmap);
2174 if (err < 0)
2175 return err;
2176 switch (codec->preset->id) {
2177 case 0x10de0002:
2178 case 0x10de0003:
2179 case 0x10de0005:
2180 case 0x10de0006:
2181 chmap->channel_mask = (1U << 2) | (1U << 8);
2182 break;
2183 case 0x10de0007:
2184 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
2185 }
2186 return 0;
2187}
2188
84eb01be
TI		 2189static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
2190{
2191 struct hdmi_spec *spec;
2192 int err = patch_nvhdmi_2ch(codec);
84eb01be
TI		 2193 if (err < 0)
2194 return err;
2195 spec = codec->spec;
2196 spec->multiout.max_channels = 8;
d0b1252d 2197 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
ceaa86ba 2198 codec->patch_ops.init = nvhdmi_7x_init_8ch;
53775b0d
TI		 2199 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
2200 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
1f348522
AP		 2201
2202 /* Initialize the audio infoframe channel mask and checksum to something
2203 * valid */
2204 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2205
84eb01be
TI		 2206 return 0;
2207}
2208
2209/*
2210 * ATI-specific implementations
2211 *
2212 * FIXME: we may omit the whole this and use the generic code once after
2213 * it's confirmed to work.
2214 */
2215
2216#define ATIHDMI_CVT_NID 0x02 /* audio converter */
2217#define ATIHDMI_PIN_NID 0x03 /* HDMI output pin */
2218
2219static int atihdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2220 struct hda_codec *codec,
2221 unsigned int stream_tag,
2222 unsigned int format,
2223 struct snd_pcm_substream *substream)
2224{
2225 struct hdmi_spec *spec = codec->spec;
2226 int chans = substream->runtime->channels;
2227 int i, err;
2228
2229 err = simple_playback_pcm_prepare(hinfo, codec, stream_tag, format,
2230 substream);
2231 if (err < 0)
2232 return err;
384a48d7
SW		 2233 snd_hda_codec_write(codec, spec->cvts[0].cvt_nid, 0,
2234 AC_VERB_SET_CVT_CHAN_COUNT, chans - 1);
84eb01be
TI		 2235 /* FIXME: XXX */
2236 for (i = 0; i < chans; i++) {
384a48d7 2237 snd_hda_codec_write(codec, spec->cvts[0].cvt_nid, 0,
84eb01be
TI		 2238 AC_VERB_SET_HDMI_CHAN_SLOT,
2239 (i << 4) | i);
2240 }
2241 return 0;
2242}
2243
84eb01be
TI		 2244static int patch_atihdmi(struct hda_codec *codec)
2245{
2246 struct hdmi_spec *spec;
d0b1252d
TI		 2247 int err = patch_simple_hdmi(codec, ATIHDMI_CVT_NID, ATIHDMI_PIN_NID);
2248 if (err < 0)
2249 return err;
2250 spec = codec->spec;
2251 spec->pcm_playback.ops.prepare = atihdmi_playback_pcm_prepare;
84eb01be
TI		 2252 return 0;
2253}
2254
3de5ff88
AL		 2255/* VIA HDMI Implementation */
2256#define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
2257#define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
2258
3de5ff88
AL		 2259static int patch_via_hdmi(struct hda_codec *codec)
2260{
250e41ac 2261 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3de5ff88 2262}
84eb01be
TI		 2263
2264/*
2265 * patch entries
2266 */
fb79e1e0 2267static const struct hda_codec_preset snd_hda_preset_hdmi[] = {
84eb01be
TI		 2268{ .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi },
2269{ .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi },
2270{ .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi },
36e9c135 2271{ .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 2272{ .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi },
2273{ .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi },
2274{ .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi },
2275{ .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2276{ .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2277{ .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2278{ .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2279{ .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x },
5d44f927
SW		 2280{ .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_generic_hdmi },
2281{ .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_generic_hdmi },
2282{ .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_generic_hdmi },
2283{ .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_generic_hdmi },
2284{ .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_generic_hdmi },
2285{ .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_generic_hdmi },
2286{ .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_generic_hdmi },
2287{ .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_generic_hdmi },
2288{ .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_generic_hdmi },
2289{ .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_generic_hdmi },
2290{ .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_generic_hdmi },
c8900a0f 2291/* 17 is known to be absent */
5d44f927
SW		 2292{ .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_generic_hdmi },
2293{ .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_generic_hdmi },
2294{ .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_generic_hdmi },
2295{ .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_generic_hdmi },
2296{ .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_generic_hdmi },
2297{ .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_generic_hdmi },
2298{ .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_generic_hdmi },
2299{ .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_generic_hdmi },
2300{ .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_generic_hdmi },
2301{ .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_generic_hdmi },
7ae48b56 2302{ .id = 0x10de0051, .name = "GPU 51 HDMI/DP", .patch = patch_generic_hdmi },
84eb01be
TI		 2303{ .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
2304{ .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
3de5ff88
AL		 2305{ .id = 0x11069f80, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
2306{ .id = 0x11069f81, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
2307{ .id = 0x11069f84, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
2308{ .id = 0x11069f85, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
84eb01be
TI		 2309{ .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
2310{ .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi },
2311{ .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi },
2312{ .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi },
2313{ .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
2314{ .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
591e610d 2315{ .id = 0x80862806, .name = "PantherPoint HDMI", .patch = patch_generic_hdmi },
1c76684d 2316{ .id = 0x80862807, .name = "Haswell HDMI", .patch = patch_generic_hdmi },
6edc59e6 2317{ .id = 0x80862880, .name = "CedarTrail HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 2318{ .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
2319{} /* terminator */
2320};
2321
2322MODULE_ALIAS("snd-hda-codec-id:1002793c");
2323MODULE_ALIAS("snd-hda-codec-id:10027919");
2324MODULE_ALIAS("snd-hda-codec-id:1002791a");
2325MODULE_ALIAS("snd-hda-codec-id:1002aa01");
2326MODULE_ALIAS("snd-hda-codec-id:10951390");
2327MODULE_ALIAS("snd-hda-codec-id:10951392");
2328MODULE_ALIAS("snd-hda-codec-id:10de0002");
2329MODULE_ALIAS("snd-hda-codec-id:10de0003");
2330MODULE_ALIAS("snd-hda-codec-id:10de0005");
2331MODULE_ALIAS("snd-hda-codec-id:10de0006");
2332MODULE_ALIAS("snd-hda-codec-id:10de0007");
2333MODULE_ALIAS("snd-hda-codec-id:10de000a");
2334MODULE_ALIAS("snd-hda-codec-id:10de000b");
2335MODULE_ALIAS("snd-hda-codec-id:10de000c");
2336MODULE_ALIAS("snd-hda-codec-id:10de000d");
2337MODULE_ALIAS("snd-hda-codec-id:10de0010");
2338MODULE_ALIAS("snd-hda-codec-id:10de0011");
2339MODULE_ALIAS("snd-hda-codec-id:10de0012");
2340MODULE_ALIAS("snd-hda-codec-id:10de0013");
2341MODULE_ALIAS("snd-hda-codec-id:10de0014");
c8900a0f
RS		 2342MODULE_ALIAS("snd-hda-codec-id:10de0015");
2343MODULE_ALIAS("snd-hda-codec-id:10de0016");
84eb01be
TI		 2344MODULE_ALIAS("snd-hda-codec-id:10de0018");
2345MODULE_ALIAS("snd-hda-codec-id:10de0019");
2346MODULE_ALIAS("snd-hda-codec-id:10de001a");
2347MODULE_ALIAS("snd-hda-codec-id:10de001b");
2348MODULE_ALIAS("snd-hda-codec-id:10de001c");
2349MODULE_ALIAS("snd-hda-codec-id:10de0040");
2350MODULE_ALIAS("snd-hda-codec-id:10de0041");
2351MODULE_ALIAS("snd-hda-codec-id:10de0042");
2352MODULE_ALIAS("snd-hda-codec-id:10de0043");
2353MODULE_ALIAS("snd-hda-codec-id:10de0044");
7ae48b56 2354MODULE_ALIAS("snd-hda-codec-id:10de0051");
84eb01be
TI		 2355MODULE_ALIAS("snd-hda-codec-id:10de0067");
2356MODULE_ALIAS("snd-hda-codec-id:10de8001");
3de5ff88
AL		 2357MODULE_ALIAS("snd-hda-codec-id:11069f80");
2358MODULE_ALIAS("snd-hda-codec-id:11069f81");
2359MODULE_ALIAS("snd-hda-codec-id:11069f84");
2360MODULE_ALIAS("snd-hda-codec-id:11069f85");
84eb01be
TI		 2361MODULE_ALIAS("snd-hda-codec-id:17e80047");
2362MODULE_ALIAS("snd-hda-codec-id:80860054");
2363MODULE_ALIAS("snd-hda-codec-id:80862801");
2364MODULE_ALIAS("snd-hda-codec-id:80862802");
2365MODULE_ALIAS("snd-hda-codec-id:80862803");
2366MODULE_ALIAS("snd-hda-codec-id:80862804");
2367MODULE_ALIAS("snd-hda-codec-id:80862805");
591e610d 2368MODULE_ALIAS("snd-hda-codec-id:80862806");
1c76684d 2369MODULE_ALIAS("snd-hda-codec-id:80862807");
6edc59e6 2370MODULE_ALIAS("snd-hda-codec-id:80862880");
84eb01be
TI		 2371MODULE_ALIAS("snd-hda-codec-id:808629fb");
2372
2373MODULE_LICENSE("GPL");
2374MODULE_DESCRIPTION("HDMI HD-audio codec");
2375MODULE_ALIAS("snd-hda-codec-intelhdmi");
2376MODULE_ALIAS("snd-hda-codec-nvhdmi");
2377MODULE_ALIAS("snd-hda-codec-atihdmi");
2378
2379static struct hda_codec_preset_list intel_list = {
2380 .preset = snd_hda_preset_hdmi,
2381 .owner = THIS_MODULE,
2382};
2383
2384static int __init patch_hdmi_init(void)
2385{
2386 return snd_hda_add_codec_preset(&intel_list);
2387}
2388
2389static void __exit patch_hdmi_exit(void)
2390{
2391 snd_hda_delete_codec_preset(&intel_list);
2392}
2393
2394module_init(patch_hdmi_init)
2395module_exit(patch_hdmi_exit)
Linux 6.x block layer and io_uring tree(s)