Commit | Line | Data |
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1a59d1b8 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
079d88cc WF |
2 | /* |
3 | * | |
4 | * patch_hdmi.c - routines for HDMI/DisplayPort codecs | |
5 | * | |
6 | * Copyright(c) 2008-2010 Intel Corporation. All rights reserved. | |
84eb01be TI |
7 | * Copyright (c) 2006 ATI Technologies Inc. |
8 | * Copyright (c) 2008 NVIDIA Corp. All rights reserved. | |
9 | * Copyright (c) 2008 Wei Ni <wni@nvidia.com> | |
5a613584 | 10 | * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi> |
079d88cc WF |
11 | * |
12 | * Authors: | |
13 | * Wu Fengguang <wfg@linux.intel.com> | |
14 | * | |
15 | * Maintained by: | |
16 | * Wu Fengguang <wfg@linux.intel.com> | |
079d88cc WF |
17 | */ |
18 | ||
84eb01be TI |
19 | #include <linux/init.h> |
20 | #include <linux/delay.h> | |
ade49db3 | 21 | #include <linux/pci.h> |
84eb01be | 22 | #include <linux/slab.h> |
65a77217 | 23 | #include <linux/module.h> |
aaa23f86 | 24 | #include <linux/pm_runtime.h> |
84eb01be | 25 | #include <sound/core.h> |
07acecc1 | 26 | #include <sound/jack.h> |
433968da | 27 | #include <sound/asoundef.h> |
d45e6889 | 28 | #include <sound/tlv.h> |
25adc137 DH |
29 | #include <sound/hdaudio.h> |
30 | #include <sound/hda_i915.h> | |
67b90cb8 | 31 | #include <sound/hda_chmap.h> |
be57bfff | 32 | #include <sound/hda_codec.h> |
84eb01be | 33 | #include "hda_local.h" |
1835a0f9 | 34 | #include "hda_jack.h" |
84eb01be | 35 | |
0ebaa24c TI |
36 | static bool static_hdmi_pcm; |
37 | module_param(static_hdmi_pcm, bool, 0644); | |
38 | MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info"); | |
39 | ||
7639a06c TI |
40 | #define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807) |
41 | #define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808) | |
42 | #define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809) | |
e2656412 | 43 | #define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a) |
91815d8a | 44 | #define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b) |
b9091b1c SP |
45 | #define is_geminilake(codec) (((codec)->core.vendor_id == 0x8086280d) || \ |
46 | ((codec)->core.vendor_id == 0x80862800)) | |
2b4584d0 | 47 | #define is_cannonlake(codec) ((codec)->core.vendor_id == 0x8086280c) |
b0d8bc50 | 48 | #define is_icelake(codec) ((codec)->core.vendor_id == 0x8086280f) |
432ac1a2 | 49 | #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \ |
91815d8a | 50 | || is_skylake(codec) || is_broxton(codec) \ |
b0d8bc50 JK |
51 | || is_kabylake(codec) || is_geminilake(codec) \ |
52 | || is_cannonlake(codec) || is_icelake(codec)) | |
7639a06c TI |
53 | #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882) |
54 | #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883) | |
ca2e7224 | 55 | #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec)) |
fb87fa3a | 56 | |
384a48d7 SW |
57 | struct hdmi_spec_per_cvt { |
58 | hda_nid_t cvt_nid; | |
59 | int assigned; | |
60 | unsigned int channels_min; | |
61 | unsigned int channels_max; | |
62 | u32 rates; | |
63 | u64 formats; | |
64 | unsigned int maxbps; | |
65 | }; | |
079d88cc | 66 | |
4eea3091 TI |
67 | /* max. connections to a widget */ |
68 | #define HDA_MAX_CONNECTIONS 32 | |
69 | ||
384a48d7 SW |
70 | struct hdmi_spec_per_pin { |
71 | hda_nid_t pin_nid; | |
9152085d | 72 | int dev_id; |
a76056f2 LY |
73 | /* pin idx, different device entries on the same pin use the same idx */ |
74 | int pin_nid_idx; | |
384a48d7 SW |
75 | int num_mux_nids; |
76 | hda_nid_t mux_nids[HDA_MAX_CONNECTIONS]; | |
2df6742f | 77 | int mux_idx; |
1df5a06a | 78 | hda_nid_t cvt_nid; |
744626da WF |
79 | |
80 | struct hda_codec *codec; | |
384a48d7 | 81 | struct hdmi_eld sink_eld; |
a4e9a38b | 82 | struct mutex lock; |
744626da | 83 | struct delayed_work work; |
2bea241a | 84 | struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/ |
a76056f2 | 85 | int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */ |
c6e8453e | 86 | int repoll_count; |
b054087d TI |
87 | bool setup; /* the stream has been set up by prepare callback */ |
88 | int channels; /* current number of channels */ | |
1a6003b5 | 89 | bool non_pcm; |
d45e6889 TI |
90 | bool chmap_set; /* channel-map override by ALSA API? */ |
91 | unsigned char chmap[8]; /* ALSA API channel-map */ | |
cd6a6503 | 92 | #ifdef CONFIG_SND_PROC_FS |
a4e9a38b TI |
93 | struct snd_info_entry *proc_entry; |
94 | #endif | |
384a48d7 | 95 | }; |
079d88cc | 96 | |
307229d2 AH |
97 | /* operations used by generic code that can be overridden by patches */ |
98 | struct hdmi_ops { | |
99 | int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid, | |
100 | unsigned char *buf, int *eld_size); | |
101 | ||
307229d2 AH |
102 | void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid, |
103 | int ca, int active_channels, int conn_type); | |
104 | ||
105 | /* enable/disable HBR (HD passthrough) */ | |
106 | int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr); | |
107 | ||
108 | int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid, | |
109 | hda_nid_t pin_nid, u32 stream_tag, int format); | |
110 | ||
4846a67e TI |
111 | void (*pin_cvt_fixup)(struct hda_codec *codec, |
112 | struct hdmi_spec_per_pin *per_pin, | |
113 | hda_nid_t cvt_nid); | |
307229d2 AH |
114 | }; |
115 | ||
2bea241a LY |
116 | struct hdmi_pcm { |
117 | struct hda_pcm *pcm; | |
118 | struct snd_jack *jack; | |
fb087eaa | 119 | struct snd_kcontrol *eld_ctl; |
2bea241a LY |
120 | }; |
121 | ||
384a48d7 | 122 | struct hdmi_spec { |
ade49db3 | 123 | struct hda_codec *codec; |
384a48d7 | 124 | int num_cvts; |
bce0d2a8 TI |
125 | struct snd_array cvts; /* struct hdmi_spec_per_cvt */ |
126 | hda_nid_t cvt_nids[4]; /* only for haswell fix */ | |
079d88cc | 127 | |
9152085d LY |
128 | /* |
129 | * num_pins is the number of virtual pins | |
130 | * for example, there are 3 pins, and each pin | |
131 | * has 4 device entries, then the num_pins is 12 | |
132 | */ | |
384a48d7 | 133 | int num_pins; |
9152085d LY |
134 | /* |
135 | * num_nids is the number of real pins | |
136 | * In the above example, num_nids is 3 | |
137 | */ | |
138 | int num_nids; | |
139 | /* | |
140 | * dev_num is the number of device entries | |
141 | * on each pin. | |
142 | * In the above example, dev_num is 4 | |
143 | */ | |
144 | int dev_num; | |
bce0d2a8 | 145 | struct snd_array pins; /* struct hdmi_spec_per_pin */ |
2bea241a | 146 | struct hdmi_pcm pcm_rec[16]; |
42b29870 | 147 | struct mutex pcm_lock; |
a76056f2 LY |
148 | /* pcm_bitmap means which pcms have been assigned to pins*/ |
149 | unsigned long pcm_bitmap; | |
2bf3c85a | 150 | int pcm_used; /* counter of pcm_rec[] */ |
ac98379a LY |
151 | /* bitmap shows whether the pcm is opened in user space |
152 | * bit 0 means the first playback PCM (PCM3); | |
153 | * bit 1 means the second playback PCM, and so on. | |
154 | */ | |
155 | unsigned long pcm_in_use; | |
079d88cc | 156 | |
4bd038f9 | 157 | struct hdmi_eld temp_eld; |
307229d2 | 158 | struct hdmi_ops ops; |
75fae117 SW |
159 | |
160 | bool dyn_pin_out; | |
6590faab | 161 | bool dyn_pcm_assign; |
079d88cc | 162 | /* |
5a613584 | 163 | * Non-generic VIA/NVIDIA specific |
079d88cc WF |
164 | */ |
165 | struct hda_multi_out multiout; | |
d0b1252d | 166 | struct hda_pcm_stream pcm_playback; |
25adc137 | 167 | |
ade49db3 TI |
168 | bool use_jack_detect; /* jack detection enabled */ |
169 | bool use_acomp_notifier; /* use eld_notify callback for hotplug */ | |
170 | bool acomp_registered; /* audio component registered in this driver */ | |
ae891abe | 171 | struct drm_audio_component_audio_ops drm_audio_ops; |
ade49db3 | 172 | int (*port2pin)(struct hda_codec *, int); /* reverse port/pin mapping */ |
67b90cb8 SP |
173 | |
174 | struct hdac_chmap chmap; | |
a87a4d23 | 175 | hda_nid_t vendor_nid; |
b0d8bc50 JK |
176 | const int *port_map; |
177 | int port_num; | |
079d88cc WF |
178 | }; |
179 | ||
a57942bf | 180 | #ifdef CONFIG_SND_HDA_COMPONENT |
691be973 TI |
181 | static inline bool codec_has_acomp(struct hda_codec *codec) |
182 | { | |
183 | struct hdmi_spec *spec = codec->spec; | |
184 | return spec->use_acomp_notifier; | |
185 | } | |
f4e3040b TI |
186 | #else |
187 | #define codec_has_acomp(codec) false | |
188 | #endif | |
079d88cc WF |
189 | |
190 | struct hdmi_audio_infoframe { | |
191 | u8 type; /* 0x84 */ | |
192 | u8 ver; /* 0x01 */ | |
193 | u8 len; /* 0x0a */ | |
194 | ||
53d7d69d WF |
195 | u8 checksum; |
196 | ||
079d88cc WF |
197 | u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */ |
198 | u8 SS01_SF24; | |
199 | u8 CXT04; | |
200 | u8 CA; | |
201 | u8 LFEPBL01_LSV36_DM_INH7; | |
53d7d69d WF |
202 | }; |
203 | ||
204 | struct dp_audio_infoframe { | |
205 | u8 type; /* 0x84 */ | |
206 | u8 len; /* 0x1b */ | |
207 | u8 ver; /* 0x11 << 2 */ | |
208 | ||
209 | u8 CC02_CT47; /* match with HDMI infoframe from this on */ | |
210 | u8 SS01_SF24; | |
211 | u8 CXT04; | |
212 | u8 CA; | |
213 | u8 LFEPBL01_LSV36_DM_INH7; | |
079d88cc WF |
214 | }; |
215 | ||
2b203dbb TI |
216 | union audio_infoframe { |
217 | struct hdmi_audio_infoframe hdmi; | |
218 | struct dp_audio_infoframe dp; | |
219 | u8 bytes[0]; | |
220 | }; | |
221 | ||
079d88cc WF |
222 | /* |
223 | * HDMI routines | |
224 | */ | |
225 | ||
bce0d2a8 TI |
226 | #define get_pin(spec, idx) \ |
227 | ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx)) | |
228 | #define get_cvt(spec, idx) \ | |
229 | ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx)) | |
2bea241a LY |
230 | /* obtain hdmi_pcm object assigned to idx */ |
231 | #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx]) | |
232 | /* obtain hda_pcm object assigned to idx */ | |
233 | #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm) | |
bce0d2a8 | 234 | |
9152085d LY |
235 | static int pin_id_to_pin_index(struct hda_codec *codec, |
236 | hda_nid_t pin_nid, int dev_id) | |
079d88cc | 237 | { |
4e76a883 | 238 | struct hdmi_spec *spec = codec->spec; |
384a48d7 | 239 | int pin_idx; |
9152085d | 240 | struct hdmi_spec_per_pin *per_pin; |
079d88cc | 241 | |
9152085d LY |
242 | /* |
243 | * (dev_id == -1) means it is NON-MST pin | |
244 | * return the first virtual pin on this port | |
245 | */ | |
246 | if (dev_id == -1) | |
247 | dev_id = 0; | |
248 | ||
249 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { | |
250 | per_pin = get_pin(spec, pin_idx); | |
251 | if ((per_pin->pin_nid == pin_nid) && | |
252 | (per_pin->dev_id == dev_id)) | |
384a48d7 | 253 | return pin_idx; |
9152085d | 254 | } |
079d88cc | 255 | |
4e76a883 | 256 | codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid); |
384a48d7 SW |
257 | return -EINVAL; |
258 | } | |
259 | ||
2bf3c85a LY |
260 | static int hinfo_to_pcm_index(struct hda_codec *codec, |
261 | struct hda_pcm_stream *hinfo) | |
262 | { | |
263 | struct hdmi_spec *spec = codec->spec; | |
264 | int pcm_idx; | |
265 | ||
266 | for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) | |
267 | if (get_pcm_rec(spec, pcm_idx)->stream == hinfo) | |
268 | return pcm_idx; | |
269 | ||
270 | codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo); | |
271 | return -EINVAL; | |
272 | } | |
273 | ||
4e76a883 | 274 | static int hinfo_to_pin_index(struct hda_codec *codec, |
384a48d7 SW |
275 | struct hda_pcm_stream *hinfo) |
276 | { | |
4e76a883 | 277 | struct hdmi_spec *spec = codec->spec; |
6590faab | 278 | struct hdmi_spec_per_pin *per_pin; |
384a48d7 SW |
279 | int pin_idx; |
280 | ||
6590faab LY |
281 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { |
282 | per_pin = get_pin(spec, pin_idx); | |
2bea241a LY |
283 | if (per_pin->pcm && |
284 | per_pin->pcm->pcm->stream == hinfo) | |
384a48d7 | 285 | return pin_idx; |
6590faab | 286 | } |
384a48d7 | 287 | |
6590faab | 288 | codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo); |
384a48d7 SW |
289 | return -EINVAL; |
290 | } | |
291 | ||
022f344b LY |
292 | static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec, |
293 | int pcm_idx) | |
294 | { | |
295 | int i; | |
296 | struct hdmi_spec_per_pin *per_pin; | |
297 | ||
298 | for (i = 0; i < spec->num_pins; i++) { | |
299 | per_pin = get_pin(spec, i); | |
300 | if (per_pin->pcm_idx == pcm_idx) | |
301 | return per_pin; | |
302 | } | |
303 | return NULL; | |
304 | } | |
305 | ||
4e76a883 | 306 | static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid) |
384a48d7 | 307 | { |
4e76a883 | 308 | struct hdmi_spec *spec = codec->spec; |
384a48d7 SW |
309 | int cvt_idx; |
310 | ||
311 | for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) | |
bce0d2a8 | 312 | if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid) |
384a48d7 SW |
313 | return cvt_idx; |
314 | ||
4e76a883 | 315 | codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid); |
079d88cc WF |
316 | return -EINVAL; |
317 | } | |
318 | ||
14bc52b8 PLB |
319 | static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol, |
320 | struct snd_ctl_elem_info *uinfo) | |
321 | { | |
322 | struct hda_codec *codec = snd_kcontrol_chip(kcontrol); | |
68e03de9 | 323 | struct hdmi_spec *spec = codec->spec; |
a4e9a38b | 324 | struct hdmi_spec_per_pin *per_pin; |
68e03de9 | 325 | struct hdmi_eld *eld; |
fb087eaa | 326 | int pcm_idx; |
14bc52b8 | 327 | |
14bc52b8 PLB |
328 | uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; |
329 | ||
fb087eaa LY |
330 | pcm_idx = kcontrol->private_value; |
331 | mutex_lock(&spec->pcm_lock); | |
332 | per_pin = pcm_idx_to_pin(spec, pcm_idx); | |
333 | if (!per_pin) { | |
334 | /* no pin is bound to the pcm */ | |
335 | uinfo->count = 0; | |
f69548ff | 336 | goto unlock; |
fb087eaa | 337 | } |
a4e9a38b | 338 | eld = &per_pin->sink_eld; |
68e03de9 | 339 | uinfo->count = eld->eld_valid ? eld->eld_size : 0; |
14bc52b8 | 340 | |
f69548ff TI |
341 | unlock: |
342 | mutex_unlock(&spec->pcm_lock); | |
14bc52b8 PLB |
343 | return 0; |
344 | } | |
345 | ||
346 | static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol, | |
347 | struct snd_ctl_elem_value *ucontrol) | |
348 | { | |
349 | struct hda_codec *codec = snd_kcontrol_chip(kcontrol); | |
68e03de9 | 350 | struct hdmi_spec *spec = codec->spec; |
a4e9a38b | 351 | struct hdmi_spec_per_pin *per_pin; |
68e03de9 | 352 | struct hdmi_eld *eld; |
fb087eaa | 353 | int pcm_idx; |
f69548ff | 354 | int err = 0; |
14bc52b8 | 355 | |
fb087eaa LY |
356 | pcm_idx = kcontrol->private_value; |
357 | mutex_lock(&spec->pcm_lock); | |
358 | per_pin = pcm_idx_to_pin(spec, pcm_idx); | |
359 | if (!per_pin) { | |
360 | /* no pin is bound to the pcm */ | |
361 | memset(ucontrol->value.bytes.data, 0, | |
362 | ARRAY_SIZE(ucontrol->value.bytes.data)); | |
f69548ff | 363 | goto unlock; |
fb087eaa | 364 | } |
68e03de9 | 365 | |
f69548ff | 366 | eld = &per_pin->sink_eld; |
360a8245 DH |
367 | if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) || |
368 | eld->eld_size > ELD_MAX_SIZE) { | |
68e03de9 | 369 | snd_BUG(); |
f69548ff TI |
370 | err = -EINVAL; |
371 | goto unlock; | |
68e03de9 DH |
372 | } |
373 | ||
374 | memset(ucontrol->value.bytes.data, 0, | |
375 | ARRAY_SIZE(ucontrol->value.bytes.data)); | |
376 | if (eld->eld_valid) | |
377 | memcpy(ucontrol->value.bytes.data, eld->eld_buffer, | |
378 | eld->eld_size); | |
14bc52b8 | 379 | |
f69548ff TI |
380 | unlock: |
381 | mutex_unlock(&spec->pcm_lock); | |
382 | return err; | |
14bc52b8 PLB |
383 | } |
384 | ||
f3b827e0 | 385 | static const struct snd_kcontrol_new eld_bytes_ctl = { |
14bc52b8 PLB |
386 | .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, |
387 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, | |
388 | .name = "ELD", | |
389 | .info = hdmi_eld_ctl_info, | |
390 | .get = hdmi_eld_ctl_get, | |
391 | }; | |
392 | ||
fb087eaa | 393 | static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx, |
14bc52b8 PLB |
394 | int device) |
395 | { | |
396 | struct snd_kcontrol *kctl; | |
397 | struct hdmi_spec *spec = codec->spec; | |
398 | int err; | |
399 | ||
400 | kctl = snd_ctl_new1(&eld_bytes_ctl, codec); | |
401 | if (!kctl) | |
402 | return -ENOMEM; | |
fb087eaa | 403 | kctl->private_value = pcm_idx; |
14bc52b8 PLB |
404 | kctl->id.device = device; |
405 | ||
fb087eaa LY |
406 | /* no pin nid is associated with the kctl now |
407 | * tbd: associate pin nid to eld ctl later | |
408 | */ | |
409 | err = snd_hda_ctl_add(codec, 0, kctl); | |
14bc52b8 PLB |
410 | if (err < 0) |
411 | return err; | |
412 | ||
fb087eaa | 413 | get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl; |
14bc52b8 PLB |
414 | return 0; |
415 | } | |
416 | ||
079d88cc WF |
417 | #ifdef BE_PARANOID |
418 | static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, | |
419 | int *packet_index, int *byte_index) | |
420 | { | |
421 | int val; | |
422 | ||
423 | val = snd_hda_codec_read(codec, pin_nid, 0, | |
424 | AC_VERB_GET_HDMI_DIP_INDEX, 0); | |
425 | ||
426 | *packet_index = val >> 5; | |
427 | *byte_index = val & 0x1f; | |
428 | } | |
429 | #endif | |
430 | ||
431 | static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, | |
432 | int packet_index, int byte_index) | |
433 | { | |
434 | int val; | |
435 | ||
436 | val = (packet_index << 5) | (byte_index & 0x1f); | |
437 | ||
438 | snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val); | |
439 | } | |
440 | ||
441 | static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid, | |
442 | unsigned char val) | |
443 | { | |
444 | snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val); | |
445 | } | |
446 | ||
384a48d7 | 447 | static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid) |
079d88cc | 448 | { |
75fae117 SW |
449 | struct hdmi_spec *spec = codec->spec; |
450 | int pin_out; | |
451 | ||
079d88cc WF |
452 | /* Unmute */ |
453 | if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) | |
454 | snd_hda_codec_write(codec, pin_nid, 0, | |
455 | AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE); | |
75fae117 SW |
456 | |
457 | if (spec->dyn_pin_out) | |
458 | /* Disable pin out until stream is active */ | |
459 | pin_out = 0; | |
460 | else | |
461 | /* Enable pin out: some machines with GM965 gets broken output | |
462 | * when the pin is disabled or changed while using with HDMI | |
463 | */ | |
464 | pin_out = PIN_OUT; | |
465 | ||
079d88cc | 466 | snd_hda_codec_write(codec, pin_nid, 0, |
75fae117 | 467 | AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out); |
079d88cc WF |
468 | } |
469 | ||
a4e9a38b TI |
470 | /* |
471 | * ELD proc files | |
472 | */ | |
473 | ||
cd6a6503 | 474 | #ifdef CONFIG_SND_PROC_FS |
a4e9a38b TI |
475 | static void print_eld_info(struct snd_info_entry *entry, |
476 | struct snd_info_buffer *buffer) | |
477 | { | |
478 | struct hdmi_spec_per_pin *per_pin = entry->private_data; | |
479 | ||
480 | mutex_lock(&per_pin->lock); | |
481 | snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer); | |
482 | mutex_unlock(&per_pin->lock); | |
483 | } | |
484 | ||
485 | static void write_eld_info(struct snd_info_entry *entry, | |
486 | struct snd_info_buffer *buffer) | |
487 | { | |
488 | struct hdmi_spec_per_pin *per_pin = entry->private_data; | |
489 | ||
490 | mutex_lock(&per_pin->lock); | |
491 | snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer); | |
492 | mutex_unlock(&per_pin->lock); | |
493 | } | |
494 | ||
495 | static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index) | |
496 | { | |
497 | char name[32]; | |
498 | struct hda_codec *codec = per_pin->codec; | |
499 | struct snd_info_entry *entry; | |
500 | int err; | |
501 | ||
502 | snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index); | |
6efdd851 | 503 | err = snd_card_proc_new(codec->card, name, &entry); |
a4e9a38b TI |
504 | if (err < 0) |
505 | return err; | |
506 | ||
507 | snd_info_set_text_ops(entry, per_pin, print_eld_info); | |
508 | entry->c.text.write = write_eld_info; | |
6a73cf46 | 509 | entry->mode |= 0200; |
a4e9a38b TI |
510 | per_pin->proc_entry = entry; |
511 | ||
512 | return 0; | |
513 | } | |
514 | ||
515 | static void eld_proc_free(struct hdmi_spec_per_pin *per_pin) | |
516 | { | |
1947a114 | 517 | if (!per_pin->codec->bus->shutdown) { |
c560a679 | 518 | snd_info_free_entry(per_pin->proc_entry); |
a4e9a38b TI |
519 | per_pin->proc_entry = NULL; |
520 | } | |
521 | } | |
522 | #else | |
b55447a7 TI |
523 | static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin, |
524 | int index) | |
a4e9a38b TI |
525 | { |
526 | return 0; | |
527 | } | |
b55447a7 | 528 | static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin) |
a4e9a38b TI |
529 | { |
530 | } | |
531 | #endif | |
079d88cc | 532 | |
079d88cc WF |
533 | /* |
534 | * Audio InfoFrame routines | |
535 | */ | |
536 | ||
537 | /* | |
538 | * Enable Audio InfoFrame Transmission | |
539 | */ | |
540 | static void hdmi_start_infoframe_trans(struct hda_codec *codec, | |
541 | hda_nid_t pin_nid) | |
542 | { | |
543 | hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); | |
544 | snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, | |
545 | AC_DIPXMIT_BEST); | |
546 | } | |
547 | ||
548 | /* | |
549 | * Disable Audio InfoFrame Transmission | |
550 | */ | |
551 | static void hdmi_stop_infoframe_trans(struct hda_codec *codec, | |
552 | hda_nid_t pin_nid) | |
553 | { | |
554 | hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); | |
555 | snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, | |
556 | AC_DIPXMIT_DISABLE); | |
557 | } | |
558 | ||
559 | static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid) | |
560 | { | |
561 | #ifdef CONFIG_SND_DEBUG_VERBOSE | |
562 | int i; | |
563 | int size; | |
564 | ||
565 | size = snd_hdmi_get_eld_size(codec, pin_nid); | |
4e76a883 | 566 | codec_dbg(codec, "HDMI: ELD buf size is %d\n", size); |
079d88cc WF |
567 | |
568 | for (i = 0; i < 8; i++) { | |
569 | size = snd_hda_codec_read(codec, pin_nid, 0, | |
570 | AC_VERB_GET_HDMI_DIP_SIZE, i); | |
4e76a883 | 571 | codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size); |
079d88cc WF |
572 | } |
573 | #endif | |
574 | } | |
575 | ||
576 | static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid) | |
577 | { | |
578 | #ifdef BE_PARANOID | |
579 | int i, j; | |
580 | int size; | |
581 | int pi, bi; | |
582 | for (i = 0; i < 8; i++) { | |
583 | size = snd_hda_codec_read(codec, pin_nid, 0, | |
584 | AC_VERB_GET_HDMI_DIP_SIZE, i); | |
585 | if (size == 0) | |
586 | continue; | |
587 | ||
588 | hdmi_set_dip_index(codec, pin_nid, i, 0x0); | |
589 | for (j = 1; j < 1000; j++) { | |
590 | hdmi_write_dip_byte(codec, pin_nid, 0x0); | |
591 | hdmi_get_dip_index(codec, pin_nid, &pi, &bi); | |
592 | if (pi != i) | |
4e76a883 | 593 | codec_dbg(codec, "dip index %d: %d != %d\n", |
079d88cc WF |
594 | bi, pi, i); |
595 | if (bi == 0) /* byte index wrapped around */ | |
596 | break; | |
597 | } | |
4e76a883 | 598 | codec_dbg(codec, |
079d88cc WF |
599 | "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n", |
600 | i, size, j); | |
601 | } | |
602 | #endif | |
603 | } | |
604 | ||
53d7d69d | 605 | static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai) |
079d88cc | 606 | { |
53d7d69d | 607 | u8 *bytes = (u8 *)hdmi_ai; |
079d88cc WF |
608 | u8 sum = 0; |
609 | int i; | |
610 | ||
53d7d69d | 611 | hdmi_ai->checksum = 0; |
079d88cc | 612 | |
53d7d69d | 613 | for (i = 0; i < sizeof(*hdmi_ai); i++) |
079d88cc WF |
614 | sum += bytes[i]; |
615 | ||
53d7d69d | 616 | hdmi_ai->checksum = -sum; |
079d88cc WF |
617 | } |
618 | ||
619 | static void hdmi_fill_audio_infoframe(struct hda_codec *codec, | |
620 | hda_nid_t pin_nid, | |
53d7d69d | 621 | u8 *dip, int size) |
079d88cc | 622 | { |
079d88cc WF |
623 | int i; |
624 | ||
625 | hdmi_debug_dip_size(codec, pin_nid); | |
626 | hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */ | |
627 | ||
079d88cc | 628 | hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); |
53d7d69d WF |
629 | for (i = 0; i < size; i++) |
630 | hdmi_write_dip_byte(codec, pin_nid, dip[i]); | |
079d88cc WF |
631 | } |
632 | ||
633 | static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid, | |
53d7d69d | 634 | u8 *dip, int size) |
079d88cc | 635 | { |
079d88cc WF |
636 | u8 val; |
637 | int i; | |
638 | ||
639 | if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0) | |
640 | != AC_DIPXMIT_BEST) | |
641 | return false; | |
642 | ||
643 | hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); | |
53d7d69d | 644 | for (i = 0; i < size; i++) { |
079d88cc WF |
645 | val = snd_hda_codec_read(codec, pin_nid, 0, |
646 | AC_VERB_GET_HDMI_DIP_DATA, 0); | |
53d7d69d | 647 | if (val != dip[i]) |
079d88cc WF |
648 | return false; |
649 | } | |
650 | ||
651 | return true; | |
652 | } | |
653 | ||
307229d2 AH |
654 | static void hdmi_pin_setup_infoframe(struct hda_codec *codec, |
655 | hda_nid_t pin_nid, | |
656 | int ca, int active_channels, | |
657 | int conn_type) | |
658 | { | |
659 | union audio_infoframe ai; | |
660 | ||
caaf5ef9 | 661 | memset(&ai, 0, sizeof(ai)); |
307229d2 AH |
662 | if (conn_type == 0) { /* HDMI */ |
663 | struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi; | |
664 | ||
665 | hdmi_ai->type = 0x84; | |
666 | hdmi_ai->ver = 0x01; | |
667 | hdmi_ai->len = 0x0a; | |
668 | hdmi_ai->CC02_CT47 = active_channels - 1; | |
669 | hdmi_ai->CA = ca; | |
670 | hdmi_checksum_audio_infoframe(hdmi_ai); | |
671 | } else if (conn_type == 1) { /* DisplayPort */ | |
672 | struct dp_audio_infoframe *dp_ai = &ai.dp; | |
673 | ||
674 | dp_ai->type = 0x84; | |
675 | dp_ai->len = 0x1b; | |
676 | dp_ai->ver = 0x11 << 2; | |
677 | dp_ai->CC02_CT47 = active_channels - 1; | |
678 | dp_ai->CA = ca; | |
679 | } else { | |
4e76a883 | 680 | codec_dbg(codec, "HDMI: unknown connection type at pin %d\n", |
307229d2 AH |
681 | pin_nid); |
682 | return; | |
683 | } | |
684 | ||
685 | /* | |
686 | * sizeof(ai) is used instead of sizeof(*hdmi_ai) or | |
687 | * sizeof(*dp_ai) to avoid partial match/update problems when | |
688 | * the user switches between HDMI/DP monitors. | |
689 | */ | |
690 | if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes, | |
691 | sizeof(ai))) { | |
4e76a883 TI |
692 | codec_dbg(codec, |
693 | "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n", | |
307229d2 AH |
694 | pin_nid, |
695 | active_channels, ca); | |
696 | hdmi_stop_infoframe_trans(codec, pin_nid); | |
697 | hdmi_fill_audio_infoframe(codec, pin_nid, | |
698 | ai.bytes, sizeof(ai)); | |
699 | hdmi_start_infoframe_trans(codec, pin_nid); | |
700 | } | |
701 | } | |
702 | ||
b054087d TI |
703 | static void hdmi_setup_audio_infoframe(struct hda_codec *codec, |
704 | struct hdmi_spec_per_pin *per_pin, | |
705 | bool non_pcm) | |
079d88cc | 706 | { |
307229d2 | 707 | struct hdmi_spec *spec = codec->spec; |
739ffee9 | 708 | struct hdac_chmap *chmap = &spec->chmap; |
384a48d7 | 709 | hda_nid_t pin_nid = per_pin->pin_nid; |
b054087d | 710 | int channels = per_pin->channels; |
1df5a06a | 711 | int active_channels; |
384a48d7 | 712 | struct hdmi_eld *eld; |
828cb4ed | 713 | int ca; |
079d88cc | 714 | |
b054087d TI |
715 | if (!channels) |
716 | return; | |
717 | ||
44bb6d0c TI |
718 | /* some HW (e.g. HSW+) needs reprogramming the amp at each time */ |
719 | if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) | |
58f7d28d ML |
720 | snd_hda_codec_write(codec, pin_nid, 0, |
721 | AC_VERB_SET_AMP_GAIN_MUTE, | |
722 | AMP_OUT_UNMUTE); | |
723 | ||
bce0d2a8 | 724 | eld = &per_pin->sink_eld; |
079d88cc | 725 | |
bb63f726 | 726 | ca = snd_hdac_channel_allocation(&codec->core, |
828cb4ed SP |
727 | eld->info.spk_alloc, channels, |
728 | per_pin->chmap_set, non_pcm, per_pin->chmap); | |
384a48d7 | 729 | |
bb63f726 | 730 | active_channels = snd_hdac_get_active_channels(ca); |
1df5a06a | 731 | |
739ffee9 SP |
732 | chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid, |
733 | active_channels); | |
1df5a06a | 734 | |
39edac70 AH |
735 | /* |
736 | * always configure channel mapping, it may have been changed by the | |
737 | * user in the meantime | |
738 | */ | |
bb63f726 | 739 | snd_hdac_setup_channel_mapping(&spec->chmap, |
828cb4ed SP |
740 | pin_nid, non_pcm, ca, channels, |
741 | per_pin->chmap, per_pin->chmap_set); | |
39edac70 | 742 | |
307229d2 AH |
743 | spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels, |
744 | eld->info.conn_type); | |
433968da | 745 | |
1a6003b5 | 746 | per_pin->non_pcm = non_pcm; |
079d88cc WF |
747 | } |
748 | ||
079d88cc WF |
749 | /* |
750 | * Unsolicited events | |
751 | */ | |
752 | ||
efe47108 | 753 | static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll); |
38faddb1 | 754 | |
9152085d LY |
755 | static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid, |
756 | int dev_id) | |
079d88cc WF |
757 | { |
758 | struct hdmi_spec *spec = codec->spec; | |
9152085d | 759 | int pin_idx = pin_id_to_pin_index(codec, nid, dev_id); |
1a4f69d5 | 760 | |
20ce9029 DH |
761 | if (pin_idx < 0) |
762 | return; | |
aaa23f86 | 763 | mutex_lock(&spec->pcm_lock); |
20ce9029 DH |
764 | if (hdmi_present_sense(get_pin(spec, pin_idx), 1)) |
765 | snd_hda_jack_report_sync(codec); | |
aaa23f86 | 766 | mutex_unlock(&spec->pcm_lock); |
20ce9029 DH |
767 | } |
768 | ||
1a4f69d5 TI |
769 | static void jack_callback(struct hda_codec *codec, |
770 | struct hda_jack_callback *jack) | |
771 | { | |
ade49db3 TI |
772 | /* stop polling when notification is enabled */ |
773 | if (codec_has_acomp(codec)) | |
774 | return; | |
775 | ||
9152085d LY |
776 | /* hda_jack don't support DP MST */ |
777 | check_presence_and_report(codec, jack->nid, 0); | |
1a4f69d5 TI |
778 | } |
779 | ||
20ce9029 DH |
780 | static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res) |
781 | { | |
3a93897e | 782 | int tag = res >> AC_UNSOL_RES_TAG_SHIFT; |
3a93897e | 783 | struct hda_jack_tbl *jack; |
2e59e5ab | 784 | int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT; |
3a93897e | 785 | |
9152085d LY |
786 | /* |
787 | * assume DP MST uses dyn_pcm_assign and acomp and | |
788 | * never comes here | |
789 | * if DP MST supports unsol event, below code need | |
790 | * consider dev_entry | |
791 | */ | |
3a93897e TI |
792 | jack = snd_hda_jack_tbl_get_from_tag(codec, tag); |
793 | if (!jack) | |
794 | return; | |
3a93897e | 795 | jack->jack_dirty = 1; |
079d88cc | 796 | |
4e76a883 | 797 | codec_dbg(codec, |
2e59e5ab | 798 | "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n", |
20ce9029 | 799 | codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA), |
fae3d88a | 800 | !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV)); |
079d88cc | 801 | |
9152085d LY |
802 | /* hda_jack don't support DP MST */ |
803 | check_presence_and_report(codec, jack->nid, 0); | |
079d88cc WF |
804 | } |
805 | ||
806 | static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res) | |
807 | { | |
808 | int tag = res >> AC_UNSOL_RES_TAG_SHIFT; | |
809 | int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; | |
810 | int cp_state = !!(res & AC_UNSOL_RES_CP_STATE); | |
811 | int cp_ready = !!(res & AC_UNSOL_RES_CP_READY); | |
812 | ||
4e76a883 | 813 | codec_info(codec, |
e9ea8e8f | 814 | "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n", |
384a48d7 | 815 | codec->addr, |
079d88cc WF |
816 | tag, |
817 | subtag, | |
818 | cp_state, | |
819 | cp_ready); | |
820 | ||
821 | /* TODO */ | |
822 | if (cp_state) | |
823 | ; | |
824 | if (cp_ready) | |
825 | ; | |
826 | } | |
827 | ||
828 | ||
829 | static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res) | |
830 | { | |
079d88cc WF |
831 | int tag = res >> AC_UNSOL_RES_TAG_SHIFT; |
832 | int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; | |
833 | ||
ade49db3 TI |
834 | if (codec_has_acomp(codec)) |
835 | return; | |
836 | ||
3a93897e | 837 | if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) { |
4e76a883 | 838 | codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag); |
079d88cc WF |
839 | return; |
840 | } | |
841 | ||
842 | if (subtag == 0) | |
843 | hdmi_intrinsic_event(codec, res); | |
844 | else | |
845 | hdmi_non_intrinsic_event(codec, res); | |
846 | } | |
847 | ||
58f7d28d | 848 | static void haswell_verify_D0(struct hda_codec *codec, |
53b434f0 | 849 | hda_nid_t cvt_nid, hda_nid_t nid) |
83f26ad2 | 850 | { |
58f7d28d | 851 | int pwr; |
83f26ad2 | 852 | |
53b434f0 WX |
853 | /* For Haswell, the converter 1/2 may keep in D3 state after bootup, |
854 | * thus pins could only choose converter 0 for use. Make sure the | |
855 | * converters are in correct power state */ | |
fd678cac | 856 | if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0)) |
53b434f0 WX |
857 | snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0); |
858 | ||
fd678cac | 859 | if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) { |
83f26ad2 DH |
860 | snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE, |
861 | AC_PWRST_D0); | |
862 | msleep(40); | |
863 | pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0); | |
864 | pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT; | |
4e76a883 | 865 | codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr); |
83f26ad2 | 866 | } |
83f26ad2 DH |
867 | } |
868 | ||
079d88cc WF |
869 | /* |
870 | * Callbacks | |
871 | */ | |
872 | ||
92f10b3f TI |
873 | /* HBR should be Non-PCM, 8 channels */ |
874 | #define is_hbr_format(format) \ | |
875 | ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7) | |
876 | ||
307229d2 AH |
877 | static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, |
878 | bool hbr) | |
079d88cc | 879 | { |
307229d2 | 880 | int pinctl, new_pinctl; |
83f26ad2 | 881 | |
384a48d7 SW |
882 | if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) { |
883 | pinctl = snd_hda_codec_read(codec, pin_nid, 0, | |
ea87d1c4 AH |
884 | AC_VERB_GET_PIN_WIDGET_CONTROL, 0); |
885 | ||
13122e6e AH |
886 | if (pinctl < 0) |
887 | return hbr ? -EINVAL : 0; | |
888 | ||
ea87d1c4 | 889 | new_pinctl = pinctl & ~AC_PINCTL_EPT; |
307229d2 | 890 | if (hbr) |
ea87d1c4 AH |
891 | new_pinctl |= AC_PINCTL_EPT_HBR; |
892 | else | |
893 | new_pinctl |= AC_PINCTL_EPT_NATIVE; | |
894 | ||
4e76a883 TI |
895 | codec_dbg(codec, |
896 | "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n", | |
384a48d7 | 897 | pin_nid, |
ea87d1c4 AH |
898 | pinctl == new_pinctl ? "" : "new-", |
899 | new_pinctl); | |
900 | ||
901 | if (pinctl != new_pinctl) | |
384a48d7 | 902 | snd_hda_codec_write(codec, pin_nid, 0, |
ea87d1c4 AH |
903 | AC_VERB_SET_PIN_WIDGET_CONTROL, |
904 | new_pinctl); | |
307229d2 AH |
905 | } else if (hbr) |
906 | return -EINVAL; | |
ea87d1c4 | 907 | |
307229d2 AH |
908 | return 0; |
909 | } | |
910 | ||
911 | static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, | |
912 | hda_nid_t pin_nid, u32 stream_tag, int format) | |
913 | { | |
914 | struct hdmi_spec *spec = codec->spec; | |
5a5d718f | 915 | unsigned int param; |
307229d2 AH |
916 | int err; |
917 | ||
307229d2 AH |
918 | err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format)); |
919 | ||
920 | if (err) { | |
4e76a883 | 921 | codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n"); |
307229d2 | 922 | return err; |
ea87d1c4 | 923 | } |
079d88cc | 924 | |
5a5d718f SP |
925 | if (is_haswell_plus(codec)) { |
926 | ||
927 | /* | |
928 | * on recent platforms IEC Coding Type is required for HBR | |
929 | * support, read current Digital Converter settings and set | |
930 | * ICT bitfield if needed. | |
931 | */ | |
932 | param = snd_hda_codec_read(codec, cvt_nid, 0, | |
933 | AC_VERB_GET_DIGI_CONVERT_1, 0); | |
934 | ||
935 | param = (param >> 16) & ~(AC_DIG3_ICT); | |
936 | ||
937 | /* on recent platforms ICT mode is required for HBR support */ | |
938 | if (is_hbr_format(format)) | |
939 | param |= 0x1; | |
940 | ||
941 | snd_hda_codec_write(codec, cvt_nid, 0, | |
942 | AC_VERB_SET_DIGI_CONVERT_3, param); | |
943 | } | |
944 | ||
384a48d7 | 945 | snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format); |
ea87d1c4 | 946 | return 0; |
079d88cc WF |
947 | } |
948 | ||
42b29870 LY |
949 | /* Try to find an available converter |
950 | * If pin_idx is less then zero, just try to find an available converter. | |
951 | * Otherwise, try to find an available converter and get the cvt mux index | |
952 | * of the pin. | |
953 | */ | |
7ef166b8 | 954 | static int hdmi_choose_cvt(struct hda_codec *codec, |
4846a67e | 955 | int pin_idx, int *cvt_id) |
bbbe3390 TI |
956 | { |
957 | struct hdmi_spec *spec = codec->spec; | |
384a48d7 | 958 | struct hdmi_spec_per_pin *per_pin; |
384a48d7 | 959 | struct hdmi_spec_per_cvt *per_cvt = NULL; |
7ef166b8 | 960 | int cvt_idx, mux_idx = 0; |
bbbe3390 | 961 | |
42b29870 LY |
962 | /* pin_idx < 0 means no pin will be bound to the converter */ |
963 | if (pin_idx < 0) | |
964 | per_pin = NULL; | |
965 | else | |
966 | per_pin = get_pin(spec, pin_idx); | |
384a48d7 SW |
967 | |
968 | /* Dynamically assign converter to stream */ | |
969 | for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { | |
bce0d2a8 | 970 | per_cvt = get_cvt(spec, cvt_idx); |
bbbe3390 | 971 | |
384a48d7 SW |
972 | /* Must not already be assigned */ |
973 | if (per_cvt->assigned) | |
974 | continue; | |
42b29870 LY |
975 | if (per_pin == NULL) |
976 | break; | |
384a48d7 SW |
977 | /* Must be in pin's mux's list of converters */ |
978 | for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) | |
979 | if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid) | |
980 | break; | |
981 | /* Not in mux list */ | |
982 | if (mux_idx == per_pin->num_mux_nids) | |
983 | continue; | |
984 | break; | |
985 | } | |
7ef166b8 | 986 | |
384a48d7 SW |
987 | /* No free converters */ |
988 | if (cvt_idx == spec->num_cvts) | |
42b29870 | 989 | return -EBUSY; |
384a48d7 | 990 | |
42b29870 LY |
991 | if (per_pin != NULL) |
992 | per_pin->mux_idx = mux_idx; | |
2df6742f | 993 | |
7ef166b8 WX |
994 | if (cvt_id) |
995 | *cvt_id = cvt_idx; | |
7ef166b8 WX |
996 | |
997 | return 0; | |
998 | } | |
999 | ||
2df6742f ML |
1000 | /* Assure the pin select the right convetor */ |
1001 | static void intel_verify_pin_cvt_connect(struct hda_codec *codec, | |
1002 | struct hdmi_spec_per_pin *per_pin) | |
1003 | { | |
1004 | hda_nid_t pin_nid = per_pin->pin_nid; | |
1005 | int mux_idx, curr; | |
1006 | ||
1007 | mux_idx = per_pin->mux_idx; | |
1008 | curr = snd_hda_codec_read(codec, pin_nid, 0, | |
1009 | AC_VERB_GET_CONNECT_SEL, 0); | |
1010 | if (curr != mux_idx) | |
1011 | snd_hda_codec_write_cache(codec, pin_nid, 0, | |
1012 | AC_VERB_SET_CONNECT_SEL, | |
1013 | mux_idx); | |
1014 | } | |
1015 | ||
42b29870 LY |
1016 | /* get the mux index for the converter of the pins |
1017 | * converter's mux index is the same for all pins on Intel platform | |
1018 | */ | |
1019 | static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec, | |
1020 | hda_nid_t cvt_nid) | |
1021 | { | |
1022 | int i; | |
1023 | ||
1024 | for (i = 0; i < spec->num_cvts; i++) | |
1025 | if (spec->cvt_nids[i] == cvt_nid) | |
1026 | return i; | |
1027 | return -EINVAL; | |
1028 | } | |
1029 | ||
300016b9 ML |
1030 | /* Intel HDMI workaround to fix audio routing issue: |
1031 | * For some Intel display codecs, pins share the same connection list. | |
1032 | * So a conveter can be selected by multiple pins and playback on any of these | |
1033 | * pins will generate sound on the external display, because audio flows from | |
1034 | * the same converter to the display pipeline. Also muting one pin may make | |
1035 | * other pins have no sound output. | |
1036 | * So this function assures that an assigned converter for a pin is not selected | |
1037 | * by any other pins. | |
1038 | */ | |
1039 | static void intel_not_share_assigned_cvt(struct hda_codec *codec, | |
9152085d LY |
1040 | hda_nid_t pin_nid, |
1041 | int dev_id, int mux_idx) | |
7ef166b8 WX |
1042 | { |
1043 | struct hdmi_spec *spec = codec->spec; | |
7639a06c | 1044 | hda_nid_t nid; |
f82d7d16 ML |
1045 | int cvt_idx, curr; |
1046 | struct hdmi_spec_per_cvt *per_cvt; | |
9152085d LY |
1047 | struct hdmi_spec_per_pin *per_pin; |
1048 | int pin_idx; | |
1049 | ||
1050 | /* configure the pins connections */ | |
1051 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { | |
1052 | int dev_id_saved; | |
1053 | int dev_num; | |
7ef166b8 | 1054 | |
9152085d LY |
1055 | per_pin = get_pin(spec, pin_idx); |
1056 | /* | |
1057 | * pin not connected to monitor | |
1058 | * no need to operate on it | |
1059 | */ | |
1060 | if (!per_pin->pcm) | |
1061 | continue; | |
f82d7d16 | 1062 | |
9152085d LY |
1063 | if ((per_pin->pin_nid == pin_nid) && |
1064 | (per_pin->dev_id == dev_id)) | |
f82d7d16 | 1065 | continue; |
7ef166b8 | 1066 | |
9152085d LY |
1067 | /* |
1068 | * if per_pin->dev_id >= dev_num, | |
1069 | * snd_hda_get_dev_select() will fail, | |
1070 | * and the following operation is unpredictable. | |
1071 | * So skip this situation. | |
1072 | */ | |
1073 | dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1; | |
1074 | if (per_pin->dev_id >= dev_num) | |
7ef166b8 WX |
1075 | continue; |
1076 | ||
9152085d LY |
1077 | nid = per_pin->pin_nid; |
1078 | ||
1079 | /* | |
1080 | * Calling this function should not impact | |
1081 | * on the device entry selection | |
1082 | * So let's save the dev id for each pin, | |
1083 | * and restore it when return | |
1084 | */ | |
1085 | dev_id_saved = snd_hda_get_dev_select(codec, nid); | |
1086 | snd_hda_set_dev_select(codec, nid, per_pin->dev_id); | |
f82d7d16 | 1087 | curr = snd_hda_codec_read(codec, nid, 0, |
7ef166b8 | 1088 | AC_VERB_GET_CONNECT_SEL, 0); |
9152085d LY |
1089 | if (curr != mux_idx) { |
1090 | snd_hda_set_dev_select(codec, nid, dev_id_saved); | |
f82d7d16 | 1091 | continue; |
9152085d LY |
1092 | } |
1093 | ||
7ef166b8 | 1094 | |
f82d7d16 ML |
1095 | /* choose an unassigned converter. The conveters in the |
1096 | * connection list are in the same order as in the codec. | |
1097 | */ | |
1098 | for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { | |
1099 | per_cvt = get_cvt(spec, cvt_idx); | |
1100 | if (!per_cvt->assigned) { | |
4e76a883 TI |
1101 | codec_dbg(codec, |
1102 | "choose cvt %d for pin nid %d\n", | |
f82d7d16 ML |
1103 | cvt_idx, nid); |
1104 | snd_hda_codec_write_cache(codec, nid, 0, | |
7ef166b8 | 1105 | AC_VERB_SET_CONNECT_SEL, |
f82d7d16 ML |
1106 | cvt_idx); |
1107 | break; | |
1108 | } | |
7ef166b8 | 1109 | } |
9152085d | 1110 | snd_hda_set_dev_select(codec, nid, dev_id_saved); |
7ef166b8 WX |
1111 | } |
1112 | } | |
1113 | ||
42b29870 LY |
1114 | /* A wrapper of intel_not_share_asigned_cvt() */ |
1115 | static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec, | |
9152085d | 1116 | hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid) |
42b29870 LY |
1117 | { |
1118 | int mux_idx; | |
1119 | struct hdmi_spec *spec = codec->spec; | |
1120 | ||
42b29870 LY |
1121 | /* On Intel platform, the mapping of converter nid to |
1122 | * mux index of the pins are always the same. | |
1123 | * The pin nid may be 0, this means all pins will not | |
1124 | * share the converter. | |
1125 | */ | |
1126 | mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid); | |
1127 | if (mux_idx >= 0) | |
9152085d | 1128 | intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx); |
42b29870 LY |
1129 | } |
1130 | ||
4846a67e TI |
1131 | /* skeleton caller of pin_cvt_fixup ops */ |
1132 | static void pin_cvt_fixup(struct hda_codec *codec, | |
1133 | struct hdmi_spec_per_pin *per_pin, | |
1134 | hda_nid_t cvt_nid) | |
1135 | { | |
1136 | struct hdmi_spec *spec = codec->spec; | |
1137 | ||
1138 | if (spec->ops.pin_cvt_fixup) | |
1139 | spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid); | |
1140 | } | |
1141 | ||
42b29870 LY |
1142 | /* called in hdmi_pcm_open when no pin is assigned to the PCM |
1143 | * in dyn_pcm_assign mode. | |
1144 | */ | |
1145 | static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo, | |
1146 | struct hda_codec *codec, | |
1147 | struct snd_pcm_substream *substream) | |
1148 | { | |
1149 | struct hdmi_spec *spec = codec->spec; | |
1150 | struct snd_pcm_runtime *runtime = substream->runtime; | |
ac98379a | 1151 | int cvt_idx, pcm_idx; |
42b29870 LY |
1152 | struct hdmi_spec_per_cvt *per_cvt = NULL; |
1153 | int err; | |
1154 | ||
ac98379a LY |
1155 | pcm_idx = hinfo_to_pcm_index(codec, hinfo); |
1156 | if (pcm_idx < 0) | |
1157 | return -EINVAL; | |
1158 | ||
4846a67e | 1159 | err = hdmi_choose_cvt(codec, -1, &cvt_idx); |
42b29870 LY |
1160 | if (err) |
1161 | return err; | |
1162 | ||
1163 | per_cvt = get_cvt(spec, cvt_idx); | |
1164 | per_cvt->assigned = 1; | |
1165 | hinfo->nid = per_cvt->cvt_nid; | |
1166 | ||
4846a67e | 1167 | pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid); |
42b29870 | 1168 | |
ac98379a | 1169 | set_bit(pcm_idx, &spec->pcm_in_use); |
42b29870 LY |
1170 | /* todo: setup spdif ctls assign */ |
1171 | ||
1172 | /* Initially set the converter's capabilities */ | |
1173 | hinfo->channels_min = per_cvt->channels_min; | |
1174 | hinfo->channels_max = per_cvt->channels_max; | |
1175 | hinfo->rates = per_cvt->rates; | |
1176 | hinfo->formats = per_cvt->formats; | |
1177 | hinfo->maxbps = per_cvt->maxbps; | |
1178 | ||
1179 | /* Store the updated parameters */ | |
1180 | runtime->hw.channels_min = hinfo->channels_min; | |
1181 | runtime->hw.channels_max = hinfo->channels_max; | |
1182 | runtime->hw.formats = hinfo->formats; | |
1183 | runtime->hw.rates = hinfo->rates; | |
1184 | ||
1185 | snd_pcm_hw_constraint_step(substream->runtime, 0, | |
1186 | SNDRV_PCM_HW_PARAM_CHANNELS, 2); | |
1187 | return 0; | |
1188 | } | |
1189 | ||
7ef166b8 WX |
1190 | /* |
1191 | * HDA PCM callbacks | |
1192 | */ | |
1193 | static int hdmi_pcm_open(struct hda_pcm_stream *hinfo, | |
1194 | struct hda_codec *codec, | |
1195 | struct snd_pcm_substream *substream) | |
1196 | { | |
1197 | struct hdmi_spec *spec = codec->spec; | |
1198 | struct snd_pcm_runtime *runtime = substream->runtime; | |
4846a67e | 1199 | int pin_idx, cvt_idx, pcm_idx; |
7ef166b8 WX |
1200 | struct hdmi_spec_per_pin *per_pin; |
1201 | struct hdmi_eld *eld; | |
1202 | struct hdmi_spec_per_cvt *per_cvt = NULL; | |
1203 | int err; | |
1204 | ||
1205 | /* Validate hinfo */ | |
2bf3c85a LY |
1206 | pcm_idx = hinfo_to_pcm_index(codec, hinfo); |
1207 | if (pcm_idx < 0) | |
7ef166b8 | 1208 | return -EINVAL; |
2bf3c85a | 1209 | |
42b29870 | 1210 | mutex_lock(&spec->pcm_lock); |
4e76a883 | 1211 | pin_idx = hinfo_to_pin_index(codec, hinfo); |
42b29870 LY |
1212 | if (!spec->dyn_pcm_assign) { |
1213 | if (snd_BUG_ON(pin_idx < 0)) { | |
f69548ff TI |
1214 | err = -EINVAL; |
1215 | goto unlock; | |
42b29870 LY |
1216 | } |
1217 | } else { | |
1218 | /* no pin is assigned to the PCM | |
1219 | * PA need pcm open successfully when probe | |
1220 | */ | |
1221 | if (pin_idx < 0) { | |
1222 | err = hdmi_pcm_open_no_pin(hinfo, codec, substream); | |
f69548ff | 1223 | goto unlock; |
42b29870 LY |
1224 | } |
1225 | } | |
7ef166b8 | 1226 | |
4846a67e | 1227 | err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx); |
f69548ff TI |
1228 | if (err < 0) |
1229 | goto unlock; | |
7ef166b8 WX |
1230 | |
1231 | per_cvt = get_cvt(spec, cvt_idx); | |
384a48d7 SW |
1232 | /* Claim converter */ |
1233 | per_cvt->assigned = 1; | |
42b29870 | 1234 | |
ac98379a | 1235 | set_bit(pcm_idx, &spec->pcm_in_use); |
42b29870 | 1236 | per_pin = get_pin(spec, pin_idx); |
1df5a06a | 1237 | per_pin->cvt_nid = per_cvt->cvt_nid; |
384a48d7 SW |
1238 | hinfo->nid = per_cvt->cvt_nid; |
1239 | ||
9152085d | 1240 | snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); |
bddee96b | 1241 | snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, |
384a48d7 | 1242 | AC_VERB_SET_CONNECT_SEL, |
4846a67e | 1243 | per_pin->mux_idx); |
7ef166b8 WX |
1244 | |
1245 | /* configure unused pins to choose other converters */ | |
4846a67e | 1246 | pin_cvt_fixup(codec, per_pin, 0); |
7ef166b8 | 1247 | |
2bf3c85a | 1248 | snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid); |
bbbe3390 | 1249 | |
2def8172 | 1250 | /* Initially set the converter's capabilities */ |
384a48d7 SW |
1251 | hinfo->channels_min = per_cvt->channels_min; |
1252 | hinfo->channels_max = per_cvt->channels_max; | |
1253 | hinfo->rates = per_cvt->rates; | |
1254 | hinfo->formats = per_cvt->formats; | |
1255 | hinfo->maxbps = per_cvt->maxbps; | |
2def8172 | 1256 | |
42b29870 | 1257 | eld = &per_pin->sink_eld; |
384a48d7 | 1258 | /* Restrict capabilities by ELD if this isn't disabled */ |
c3d52105 | 1259 | if (!static_hdmi_pcm && eld->eld_valid) { |
1613d6b4 | 1260 | snd_hdmi_eld_update_pcm_info(&eld->info, hinfo); |
bbbe3390 | 1261 | if (hinfo->channels_min > hinfo->channels_max || |
2ad779b7 TI |
1262 | !hinfo->rates || !hinfo->formats) { |
1263 | per_cvt->assigned = 0; | |
1264 | hinfo->nid = 0; | |
2bf3c85a | 1265 | snd_hda_spdif_ctls_unassign(codec, pcm_idx); |
f69548ff TI |
1266 | err = -ENODEV; |
1267 | goto unlock; | |
2ad779b7 | 1268 | } |
bbbe3390 | 1269 | } |
2def8172 SW |
1270 | |
1271 | /* Store the updated parameters */ | |
639cef0e TI |
1272 | runtime->hw.channels_min = hinfo->channels_min; |
1273 | runtime->hw.channels_max = hinfo->channels_max; | |
1274 | runtime->hw.formats = hinfo->formats; | |
1275 | runtime->hw.rates = hinfo->rates; | |
4fe2ca14 TI |
1276 | |
1277 | snd_pcm_hw_constraint_step(substream->runtime, 0, | |
1278 | SNDRV_PCM_HW_PARAM_CHANNELS, 2); | |
f69548ff TI |
1279 | unlock: |
1280 | mutex_unlock(&spec->pcm_lock); | |
1281 | return err; | |
bbbe3390 TI |
1282 | } |
1283 | ||
079d88cc WF |
1284 | /* |
1285 | * HDA/HDMI auto parsing | |
1286 | */ | |
384a48d7 | 1287 | static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx) |
079d88cc WF |
1288 | { |
1289 | struct hdmi_spec *spec = codec->spec; | |
bce0d2a8 | 1290 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); |
384a48d7 | 1291 | hda_nid_t pin_nid = per_pin->pin_nid; |
079d88cc WF |
1292 | |
1293 | if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) { | |
4e76a883 TI |
1294 | codec_warn(codec, |
1295 | "HDMI: pin %d wcaps %#x does not support connection list\n", | |
079d88cc WF |
1296 | pin_nid, get_wcaps(codec, pin_nid)); |
1297 | return -EINVAL; | |
1298 | } | |
1299 | ||
9152085d | 1300 | /* all the device entries on the same pin have the same conn list */ |
384a48d7 SW |
1301 | per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid, |
1302 | per_pin->mux_nids, | |
1303 | HDA_MAX_CONNECTIONS); | |
079d88cc WF |
1304 | |
1305 | return 0; | |
1306 | } | |
1307 | ||
a76056f2 LY |
1308 | static int hdmi_find_pcm_slot(struct hdmi_spec *spec, |
1309 | struct hdmi_spec_per_pin *per_pin) | |
1310 | { | |
1311 | int i; | |
1312 | ||
1313 | /* try the prefer PCM */ | |
1314 | if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap)) | |
1315 | return per_pin->pin_nid_idx; | |
1316 | ||
1317 | /* have a second try; check the "reserved area" over num_pins */ | |
9152085d | 1318 | for (i = spec->num_nids; i < spec->pcm_used; i++) { |
a76056f2 LY |
1319 | if (!test_bit(i, &spec->pcm_bitmap)) |
1320 | return i; | |
1321 | } | |
1322 | ||
1323 | /* the last try; check the empty slots in pins */ | |
9152085d | 1324 | for (i = 0; i < spec->num_nids; i++) { |
a76056f2 LY |
1325 | if (!test_bit(i, &spec->pcm_bitmap)) |
1326 | return i; | |
1327 | } | |
1328 | return -EBUSY; | |
1329 | } | |
1330 | ||
1331 | static void hdmi_attach_hda_pcm(struct hdmi_spec *spec, | |
1332 | struct hdmi_spec_per_pin *per_pin) | |
1333 | { | |
1334 | int idx; | |
1335 | ||
1336 | /* pcm already be attached to the pin */ | |
1337 | if (per_pin->pcm) | |
1338 | return; | |
1339 | idx = hdmi_find_pcm_slot(spec, per_pin); | |
d10a80de | 1340 | if (idx == -EBUSY) |
a76056f2 LY |
1341 | return; |
1342 | per_pin->pcm_idx = idx; | |
2bea241a | 1343 | per_pin->pcm = get_hdmi_pcm(spec, idx); |
a76056f2 LY |
1344 | set_bit(idx, &spec->pcm_bitmap); |
1345 | } | |
1346 | ||
1347 | static void hdmi_detach_hda_pcm(struct hdmi_spec *spec, | |
1348 | struct hdmi_spec_per_pin *per_pin) | |
1349 | { | |
1350 | int idx; | |
1351 | ||
1352 | /* pcm already be detached from the pin */ | |
1353 | if (!per_pin->pcm) | |
1354 | return; | |
1355 | idx = per_pin->pcm_idx; | |
1356 | per_pin->pcm_idx = -1; | |
1357 | per_pin->pcm = NULL; | |
1358 | if (idx >= 0 && idx < spec->pcm_used) | |
1359 | clear_bit(idx, &spec->pcm_bitmap); | |
1360 | } | |
1361 | ||
ac98379a LY |
1362 | static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec, |
1363 | struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid) | |
1364 | { | |
1365 | int mux_idx; | |
1366 | ||
1367 | for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) | |
1368 | if (per_pin->mux_nids[mux_idx] == cvt_nid) | |
1369 | break; | |
1370 | return mux_idx; | |
1371 | } | |
1372 | ||
1373 | static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid); | |
1374 | ||
1375 | static void hdmi_pcm_setup_pin(struct hdmi_spec *spec, | |
1376 | struct hdmi_spec_per_pin *per_pin) | |
1377 | { | |
1378 | struct hda_codec *codec = per_pin->codec; | |
1379 | struct hda_pcm *pcm; | |
1380 | struct hda_pcm_stream *hinfo; | |
1381 | struct snd_pcm_substream *substream; | |
1382 | int mux_idx; | |
1383 | bool non_pcm; | |
1384 | ||
1385 | if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) | |
2bea241a | 1386 | pcm = get_pcm_rec(spec, per_pin->pcm_idx); |
ac98379a LY |
1387 | else |
1388 | return; | |
8a7d6003 TI |
1389 | if (!pcm->pcm) |
1390 | return; | |
ac98379a LY |
1391 | if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use)) |
1392 | return; | |
1393 | ||
1394 | /* hdmi audio only uses playback and one substream */ | |
1395 | hinfo = pcm->stream; | |
1396 | substream = pcm->pcm->streams[0].substream; | |
1397 | ||
1398 | per_pin->cvt_nid = hinfo->nid; | |
1399 | ||
1400 | mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid); | |
9152085d LY |
1401 | if (mux_idx < per_pin->num_mux_nids) { |
1402 | snd_hda_set_dev_select(codec, per_pin->pin_nid, | |
1403 | per_pin->dev_id); | |
ac98379a LY |
1404 | snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, |
1405 | AC_VERB_SET_CONNECT_SEL, | |
1406 | mux_idx); | |
9152085d | 1407 | } |
ac98379a LY |
1408 | snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid); |
1409 | ||
1410 | non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid); | |
1411 | if (substream->runtime) | |
1412 | per_pin->channels = substream->runtime->channels; | |
1413 | per_pin->setup = true; | |
1414 | per_pin->mux_idx = mux_idx; | |
1415 | ||
1416 | hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); | |
1417 | } | |
1418 | ||
1419 | static void hdmi_pcm_reset_pin(struct hdmi_spec *spec, | |
1420 | struct hdmi_spec_per_pin *per_pin) | |
1421 | { | |
1422 | if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) | |
1423 | snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx); | |
1424 | ||
1425 | per_pin->chmap_set = false; | |
1426 | memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); | |
1427 | ||
1428 | per_pin->setup = false; | |
1429 | per_pin->channels = 0; | |
1430 | } | |
1431 | ||
e90247f9 TI |
1432 | /* update per_pin ELD from the given new ELD; |
1433 | * setup info frame and notification accordingly | |
1434 | */ | |
551626ec | 1435 | static bool update_eld(struct hda_codec *codec, |
e90247f9 TI |
1436 | struct hdmi_spec_per_pin *per_pin, |
1437 | struct hdmi_eld *eld) | |
1438 | { | |
1439 | struct hdmi_eld *pin_eld = &per_pin->sink_eld; | |
a76056f2 | 1440 | struct hdmi_spec *spec = codec->spec; |
e90247f9 TI |
1441 | bool old_eld_valid = pin_eld->eld_valid; |
1442 | bool eld_changed; | |
fb087eaa | 1443 | int pcm_idx = -1; |
e90247f9 | 1444 | |
fb087eaa LY |
1445 | /* for monitor disconnection, save pcm_idx firstly */ |
1446 | pcm_idx = per_pin->pcm_idx; | |
a76056f2 | 1447 | if (spec->dyn_pcm_assign) { |
ac98379a | 1448 | if (eld->eld_valid) { |
a76056f2 | 1449 | hdmi_attach_hda_pcm(spec, per_pin); |
ac98379a LY |
1450 | hdmi_pcm_setup_pin(spec, per_pin); |
1451 | } else { | |
1452 | hdmi_pcm_reset_pin(spec, per_pin); | |
a76056f2 | 1453 | hdmi_detach_hda_pcm(spec, per_pin); |
ac98379a | 1454 | } |
a76056f2 | 1455 | } |
fb087eaa LY |
1456 | /* if pcm_idx == -1, it means this is in monitor connection event |
1457 | * we can get the correct pcm_idx now. | |
1458 | */ | |
1459 | if (pcm_idx == -1) | |
1460 | pcm_idx = per_pin->pcm_idx; | |
a76056f2 | 1461 | |
e90247f9 TI |
1462 | if (eld->eld_valid) |
1463 | snd_hdmi_show_eld(codec, &eld->info); | |
1464 | ||
1465 | eld_changed = (pin_eld->eld_valid != eld->eld_valid); | |
551626ec TI |
1466 | eld_changed |= (pin_eld->monitor_present != eld->monitor_present); |
1467 | if (!eld_changed && eld->eld_valid && pin_eld->eld_valid) | |
e90247f9 TI |
1468 | if (pin_eld->eld_size != eld->eld_size || |
1469 | memcmp(pin_eld->eld_buffer, eld->eld_buffer, | |
1470 | eld->eld_size) != 0) | |
1471 | eld_changed = true; | |
1472 | ||
551626ec TI |
1473 | if (eld_changed) { |
1474 | pin_eld->monitor_present = eld->monitor_present; | |
1475 | pin_eld->eld_valid = eld->eld_valid; | |
1476 | pin_eld->eld_size = eld->eld_size; | |
1477 | if (eld->eld_valid) | |
1478 | memcpy(pin_eld->eld_buffer, eld->eld_buffer, | |
1479 | eld->eld_size); | |
1480 | pin_eld->info = eld->info; | |
1481 | } | |
e90247f9 TI |
1482 | |
1483 | /* | |
1484 | * Re-setup pin and infoframe. This is needed e.g. when | |
1485 | * - sink is first plugged-in | |
1486 | * - transcoder can change during stream playback on Haswell | |
1487 | * and this can make HW reset converter selection on a pin. | |
1488 | */ | |
1489 | if (eld->eld_valid && !old_eld_valid && per_pin->setup) { | |
4846a67e | 1490 | pin_cvt_fixup(codec, per_pin, 0); |
e90247f9 TI |
1491 | hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); |
1492 | } | |
1493 | ||
fb087eaa | 1494 | if (eld_changed && pcm_idx >= 0) |
e90247f9 TI |
1495 | snd_ctl_notify(codec->card, |
1496 | SNDRV_CTL_EVENT_MASK_VALUE | | |
1497 | SNDRV_CTL_EVENT_MASK_INFO, | |
fb087eaa | 1498 | &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id); |
551626ec | 1499 | return eld_changed; |
e90247f9 TI |
1500 | } |
1501 | ||
788d441a TI |
1502 | /* update ELD and jack state via HD-audio verbs */ |
1503 | static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin, | |
1504 | int repoll) | |
079d88cc | 1505 | { |
464837a7 | 1506 | struct hda_jack_tbl *jack; |
744626da | 1507 | struct hda_codec *codec = per_pin->codec; |
4bd038f9 DH |
1508 | struct hdmi_spec *spec = codec->spec; |
1509 | struct hdmi_eld *eld = &spec->temp_eld; | |
744626da | 1510 | hda_nid_t pin_nid = per_pin->pin_nid; |
5d44f927 SW |
1511 | /* |
1512 | * Always execute a GetPinSense verb here, even when called from | |
1513 | * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited | |
1514 | * response's PD bit is not the real PD value, but indicates that | |
1515 | * the real PD value changed. An older version of the HD-audio | |
1516 | * specification worked this way. Hence, we just ignore the data in | |
1517 | * the unsolicited response to avoid custom WARs. | |
1518 | */ | |
da4a7a39 | 1519 | int present; |
efe47108 | 1520 | bool ret; |
9a5e5234 | 1521 | bool do_repoll = false; |
079d88cc | 1522 | |
da4a7a39 DH |
1523 | present = snd_hda_pin_sense(codec, pin_nid); |
1524 | ||
a4e9a38b | 1525 | mutex_lock(&per_pin->lock); |
c44da62b TI |
1526 | eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE); |
1527 | if (eld->monitor_present) | |
4bd038f9 DH |
1528 | eld->eld_valid = !!(present & AC_PINSENSE_ELDV); |
1529 | else | |
1530 | eld->eld_valid = false; | |
079d88cc | 1531 | |
4e76a883 | 1532 | codec_dbg(codec, |
384a48d7 | 1533 | "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n", |
c44da62b | 1534 | codec->addr, pin_nid, eld->monitor_present, eld->eld_valid); |
5d44f927 | 1535 | |
4bd038f9 | 1536 | if (eld->eld_valid) { |
307229d2 | 1537 | if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer, |
1613d6b4 | 1538 | &eld->eld_size) < 0) |
4bd038f9 | 1539 | eld->eld_valid = false; |
1613d6b4 | 1540 | else { |
79514d47 | 1541 | if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer, |
1613d6b4 | 1542 | eld->eld_size) < 0) |
4bd038f9 | 1543 | eld->eld_valid = false; |
1613d6b4 | 1544 | } |
9a5e5234 TI |
1545 | if (!eld->eld_valid && repoll) |
1546 | do_repoll = true; | |
744626da | 1547 | } |
4bd038f9 | 1548 | |
9a5e5234 | 1549 | if (do_repoll) |
e90247f9 TI |
1550 | schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300)); |
1551 | else | |
1552 | update_eld(codec, per_pin, eld); | |
92c69e79 | 1553 | |
c44da62b | 1554 | ret = !repoll || !eld->monitor_present || eld->eld_valid; |
464837a7 DH |
1555 | |
1556 | jack = snd_hda_jack_tbl_get(codec, pin_nid); | |
7f641e26 | 1557 | if (jack) { |
464837a7 | 1558 | jack->block_report = !ret; |
7f641e26 HW |
1559 | jack->pin_sense = (eld->monitor_present && eld->eld_valid) ? |
1560 | AC_PINSENSE_PRESENCE : 0; | |
1561 | } | |
a4e9a38b | 1562 | mutex_unlock(&per_pin->lock); |
efe47108 | 1563 | return ret; |
079d88cc WF |
1564 | } |
1565 | ||
3184270e LY |
1566 | static struct snd_jack *pin_idx_to_jack(struct hda_codec *codec, |
1567 | struct hdmi_spec_per_pin *per_pin) | |
1568 | { | |
1569 | struct hdmi_spec *spec = codec->spec; | |
1570 | struct snd_jack *jack = NULL; | |
1571 | struct hda_jack_tbl *jack_tbl; | |
1572 | ||
1573 | /* if !dyn_pcm_assign, get jack from hda_jack_tbl | |
1574 | * in !dyn_pcm_assign case, spec->pcm_rec[].jack is not | |
1575 | * NULL even after snd_hda_jack_tbl_clear() is called to | |
1576 | * free snd_jack. This may cause access invalid memory | |
1577 | * when calling snd_jack_report | |
1578 | */ | |
1579 | if (per_pin->pcm_idx >= 0 && spec->dyn_pcm_assign) | |
1580 | jack = spec->pcm_rec[per_pin->pcm_idx].jack; | |
1581 | else if (!spec->dyn_pcm_assign) { | |
9152085d LY |
1582 | /* |
1583 | * jack tbl doesn't support DP MST | |
1584 | * DP MST will use dyn_pcm_assign, | |
1585 | * so DP MST will never come here | |
1586 | */ | |
3184270e LY |
1587 | jack_tbl = snd_hda_jack_tbl_get(codec, per_pin->pin_nid); |
1588 | if (jack_tbl) | |
1589 | jack = jack_tbl->jack; | |
1590 | } | |
1591 | return jack; | |
1592 | } | |
1593 | ||
788d441a TI |
1594 | /* update ELD and jack state via audio component */ |
1595 | static void sync_eld_via_acomp(struct hda_codec *codec, | |
1596 | struct hdmi_spec_per_pin *per_pin) | |
1597 | { | |
788d441a TI |
1598 | struct hdmi_spec *spec = codec->spec; |
1599 | struct hdmi_eld *eld = &spec->temp_eld; | |
25e4abb3 | 1600 | struct snd_jack *jack = NULL; |
551626ec | 1601 | bool changed; |
788d441a TI |
1602 | int size; |
1603 | ||
e2dc7d7d | 1604 | mutex_lock(&per_pin->lock); |
c64c1437 | 1605 | eld->monitor_present = false; |
9152085d LY |
1606 | size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid, |
1607 | per_pin->dev_id, &eld->monitor_present, | |
1608 | eld->eld_buffer, ELD_MAX_SIZE); | |
e2dc7d7d TI |
1609 | if (size > 0) { |
1610 | size = min(size, ELD_MAX_SIZE); | |
1611 | if (snd_hdmi_parse_eld(codec, &eld->info, | |
1612 | eld->eld_buffer, size) < 0) | |
1613 | size = -EINVAL; | |
1614 | } | |
788d441a | 1615 | |
e2dc7d7d TI |
1616 | if (size > 0) { |
1617 | eld->eld_valid = true; | |
1618 | eld->eld_size = size; | |
1619 | } else { | |
1620 | eld->eld_valid = false; | |
1621 | eld->eld_size = 0; | |
788d441a | 1622 | } |
e2dc7d7d | 1623 | |
25e4abb3 LY |
1624 | /* pcm_idx >=0 before update_eld() means it is in monitor |
1625 | * disconnected event. Jack must be fetched before update_eld() | |
1626 | */ | |
3184270e | 1627 | jack = pin_idx_to_jack(codec, per_pin); |
551626ec | 1628 | changed = update_eld(codec, per_pin, eld); |
3184270e LY |
1629 | if (jack == NULL) |
1630 | jack = pin_idx_to_jack(codec, per_pin); | |
551626ec TI |
1631 | if (changed && jack) |
1632 | snd_jack_report(jack, | |
1633 | (eld->monitor_present && eld->eld_valid) ? | |
855b5e01 | 1634 | SND_JACK_AVOUT : 0); |
e2dc7d7d | 1635 | mutex_unlock(&per_pin->lock); |
788d441a TI |
1636 | } |
1637 | ||
1638 | static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll) | |
1639 | { | |
1640 | struct hda_codec *codec = per_pin->codec; | |
a76056f2 | 1641 | int ret; |
788d441a | 1642 | |
222bde03 | 1643 | /* no temporary power up/down needed for component notifier */ |
aaa23f86 CW |
1644 | if (!codec_has_acomp(codec)) { |
1645 | ret = snd_hda_power_up_pm(codec); | |
1646 | if (ret < 0 && pm_runtime_suspended(hda_codec_dev(codec))) { | |
1647 | snd_hda_power_down_pm(codec); | |
1648 | return false; | |
1649 | } | |
ade49db3 TI |
1650 | ret = hdmi_present_sense_via_verbs(per_pin, repoll); |
1651 | snd_hda_power_down_pm(codec); | |
1652 | } else { | |
788d441a | 1653 | sync_eld_via_acomp(codec, per_pin); |
a76056f2 | 1654 | ret = false; /* don't call snd_hda_jack_report_sync() */ |
788d441a | 1655 | } |
a76056f2 LY |
1656 | |
1657 | return ret; | |
788d441a TI |
1658 | } |
1659 | ||
744626da WF |
1660 | static void hdmi_repoll_eld(struct work_struct *work) |
1661 | { | |
1662 | struct hdmi_spec_per_pin *per_pin = | |
1663 | container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work); | |
aaa23f86 CW |
1664 | struct hda_codec *codec = per_pin->codec; |
1665 | struct hdmi_spec *spec = codec->spec; | |
8c2e6728 HW |
1666 | struct hda_jack_tbl *jack; |
1667 | ||
1668 | jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid); | |
1669 | if (jack) | |
1670 | jack->jack_dirty = 1; | |
744626da | 1671 | |
c6e8453e WF |
1672 | if (per_pin->repoll_count++ > 6) |
1673 | per_pin->repoll_count = 0; | |
1674 | ||
aaa23f86 | 1675 | mutex_lock(&spec->pcm_lock); |
efe47108 TI |
1676 | if (hdmi_present_sense(per_pin, per_pin->repoll_count)) |
1677 | snd_hda_jack_report_sync(per_pin->codec); | |
aaa23f86 | 1678 | mutex_unlock(&spec->pcm_lock); |
744626da WF |
1679 | } |
1680 | ||
c88d4e84 TI |
1681 | static void intel_haswell_fixup_connect_list(struct hda_codec *codec, |
1682 | hda_nid_t nid); | |
1683 | ||
079d88cc WF |
1684 | static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid) |
1685 | { | |
1686 | struct hdmi_spec *spec = codec->spec; | |
384a48d7 SW |
1687 | unsigned int caps, config; |
1688 | int pin_idx; | |
1689 | struct hdmi_spec_per_pin *per_pin; | |
07acecc1 | 1690 | int err; |
9152085d | 1691 | int dev_num, i; |
079d88cc | 1692 | |
efc2f8de | 1693 | caps = snd_hda_query_pin_caps(codec, pin_nid); |
384a48d7 SW |
1694 | if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP))) |
1695 | return 0; | |
1696 | ||
9152085d LY |
1697 | /* |
1698 | * For DP MST audio, Configuration Default is the same for | |
1699 | * all device entries on the same pin | |
1700 | */ | |
efc2f8de | 1701 | config = snd_hda_codec_get_pincfg(codec, pin_nid); |
384a48d7 SW |
1702 | if (get_defcfg_connect(config) == AC_JACK_PORT_NONE) |
1703 | return 0; | |
1704 | ||
9152085d LY |
1705 | /* |
1706 | * To simplify the implementation, malloc all | |
1707 | * the virtual pins in the initialization statically | |
1708 | */ | |
1709 | if (is_haswell_plus(codec)) { | |
1710 | /* | |
1711 | * On Intel platforms, device entries number is | |
1712 | * changed dynamically. If there is a DP MST | |
1713 | * hub connected, the device entries number is 3. | |
1714 | * Otherwise, it is 1. | |
1715 | * Here we manually set dev_num to 3, so that | |
1716 | * we can initialize all the device entries when | |
1717 | * bootup statically. | |
1718 | */ | |
1719 | dev_num = 3; | |
1720 | spec->dev_num = 3; | |
1721 | } else if (spec->dyn_pcm_assign && codec->dp_mst) { | |
1722 | dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1; | |
1723 | /* | |
1724 | * spec->dev_num is the maxinum number of device entries | |
1725 | * among all the pins | |
1726 | */ | |
1727 | spec->dev_num = (spec->dev_num > dev_num) ? | |
1728 | spec->dev_num : dev_num; | |
1729 | } else { | |
1730 | /* | |
1731 | * If the platform doesn't support DP MST, | |
1732 | * manually set dev_num to 1. This means | |
1733 | * the pin has only one device entry. | |
1734 | */ | |
1735 | dev_num = 1; | |
1736 | spec->dev_num = 1; | |
2bea241a | 1737 | } |
079d88cc | 1738 | |
9152085d LY |
1739 | for (i = 0; i < dev_num; i++) { |
1740 | pin_idx = spec->num_pins; | |
1741 | per_pin = snd_array_new(&spec->pins); | |
079d88cc | 1742 | |
9152085d LY |
1743 | if (!per_pin) |
1744 | return -ENOMEM; | |
1745 | ||
1746 | if (spec->dyn_pcm_assign) { | |
1747 | per_pin->pcm = NULL; | |
1748 | per_pin->pcm_idx = -1; | |
1749 | } else { | |
1750 | per_pin->pcm = get_hdmi_pcm(spec, pin_idx); | |
1751 | per_pin->pcm_idx = pin_idx; | |
1752 | } | |
1753 | per_pin->pin_nid = pin_nid; | |
1754 | per_pin->pin_nid_idx = spec->num_nids; | |
1755 | per_pin->dev_id = i; | |
1756 | per_pin->non_pcm = false; | |
1757 | snd_hda_set_dev_select(codec, pin_nid, i); | |
1758 | if (is_haswell_plus(codec)) | |
1759 | intel_haswell_fixup_connect_list(codec, pin_nid); | |
1760 | err = hdmi_read_pin_conn(codec, pin_idx); | |
1761 | if (err < 0) | |
1762 | return err; | |
1763 | spec->num_pins++; | |
1764 | } | |
1765 | spec->num_nids++; | |
079d88cc | 1766 | |
384a48d7 | 1767 | return 0; |
079d88cc WF |
1768 | } |
1769 | ||
384a48d7 | 1770 | static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) |
079d88cc WF |
1771 | { |
1772 | struct hdmi_spec *spec = codec->spec; | |
384a48d7 SW |
1773 | struct hdmi_spec_per_cvt *per_cvt; |
1774 | unsigned int chans; | |
1775 | int err; | |
079d88cc | 1776 | |
384a48d7 SW |
1777 | chans = get_wcaps(codec, cvt_nid); |
1778 | chans = get_wcaps_channels(chans); | |
1779 | ||
bce0d2a8 TI |
1780 | per_cvt = snd_array_new(&spec->cvts); |
1781 | if (!per_cvt) | |
1782 | return -ENOMEM; | |
384a48d7 SW |
1783 | |
1784 | per_cvt->cvt_nid = cvt_nid; | |
1785 | per_cvt->channels_min = 2; | |
d45e6889 | 1786 | if (chans <= 16) { |
384a48d7 | 1787 | per_cvt->channels_max = chans; |
67b90cb8 SP |
1788 | if (chans > spec->chmap.channels_max) |
1789 | spec->chmap.channels_max = chans; | |
d45e6889 | 1790 | } |
384a48d7 SW |
1791 | |
1792 | err = snd_hda_query_supported_pcm(codec, cvt_nid, | |
1793 | &per_cvt->rates, | |
1794 | &per_cvt->formats, | |
1795 | &per_cvt->maxbps); | |
1796 | if (err < 0) | |
1797 | return err; | |
1798 | ||
bce0d2a8 TI |
1799 | if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids)) |
1800 | spec->cvt_nids[spec->num_cvts] = cvt_nid; | |
1801 | spec->num_cvts++; | |
079d88cc WF |
1802 | |
1803 | return 0; | |
1804 | } | |
1805 | ||
1806 | static int hdmi_parse_codec(struct hda_codec *codec) | |
1807 | { | |
1808 | hda_nid_t nid; | |
1809 | int i, nodes; | |
1810 | ||
7639a06c | 1811 | nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid); |
079d88cc | 1812 | if (!nid || nodes < 0) { |
4e76a883 | 1813 | codec_warn(codec, "HDMI: failed to get afg sub nodes\n"); |
079d88cc WF |
1814 | return -EINVAL; |
1815 | } | |
1816 | ||
1817 | for (i = 0; i < nodes; i++, nid++) { | |
1818 | unsigned int caps; | |
1819 | unsigned int type; | |
1820 | ||
efc2f8de | 1821 | caps = get_wcaps(codec, nid); |
079d88cc WF |
1822 | type = get_wcaps_type(caps); |
1823 | ||
1824 | if (!(caps & AC_WCAP_DIGITAL)) | |
1825 | continue; | |
1826 | ||
1827 | switch (type) { | |
1828 | case AC_WID_AUD_OUT: | |
384a48d7 | 1829 | hdmi_add_cvt(codec, nid); |
079d88cc WF |
1830 | break; |
1831 | case AC_WID_PIN: | |
3eaead57 | 1832 | hdmi_add_pin(codec, nid); |
079d88cc WF |
1833 | break; |
1834 | } | |
1835 | } | |
1836 | ||
079d88cc WF |
1837 | return 0; |
1838 | } | |
1839 | ||
84eb01be TI |
1840 | /* |
1841 | */ | |
1a6003b5 TI |
1842 | static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) |
1843 | { | |
1844 | struct hda_spdif_out *spdif; | |
1845 | bool non_pcm; | |
1846 | ||
1847 | mutex_lock(&codec->spdif_mutex); | |
1848 | spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid); | |
960a581e LY |
1849 | /* Add sanity check to pass klockwork check. |
1850 | * This should never happen. | |
1851 | */ | |
1852 | if (WARN_ON(spdif == NULL)) | |
1853 | return true; | |
1a6003b5 TI |
1854 | non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO); |
1855 | mutex_unlock(&codec->spdif_mutex); | |
1856 | return non_pcm; | |
1857 | } | |
1858 | ||
84eb01be TI |
1859 | /* |
1860 | * HDMI callbacks | |
1861 | */ | |
1862 | ||
1863 | static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo, | |
1864 | struct hda_codec *codec, | |
1865 | unsigned int stream_tag, | |
1866 | unsigned int format, | |
1867 | struct snd_pcm_substream *substream) | |
1868 | { | |
384a48d7 SW |
1869 | hda_nid_t cvt_nid = hinfo->nid; |
1870 | struct hdmi_spec *spec = codec->spec; | |
42b29870 LY |
1871 | int pin_idx; |
1872 | struct hdmi_spec_per_pin *per_pin; | |
1873 | hda_nid_t pin_nid; | |
ddd621fb | 1874 | struct snd_pcm_runtime *runtime = substream->runtime; |
1a6003b5 | 1875 | bool non_pcm; |
053b0559 | 1876 | int pinctl, stripe; |
f69548ff | 1877 | int err = 0; |
1a6003b5 | 1878 | |
42b29870 LY |
1879 | mutex_lock(&spec->pcm_lock); |
1880 | pin_idx = hinfo_to_pin_index(codec, hinfo); | |
1881 | if (spec->dyn_pcm_assign && pin_idx < 0) { | |
1882 | /* when dyn_pcm_assign and pcm is not bound to a pin | |
1883 | * skip pin setup and return 0 to make audio playback | |
1884 | * be ongoing | |
1885 | */ | |
4846a67e | 1886 | pin_cvt_fixup(codec, NULL, cvt_nid); |
42b29870 LY |
1887 | snd_hda_codec_setup_stream(codec, cvt_nid, |
1888 | stream_tag, 0, format); | |
f69548ff | 1889 | goto unlock; |
42b29870 | 1890 | } |
1a6003b5 | 1891 | |
42b29870 | 1892 | if (snd_BUG_ON(pin_idx < 0)) { |
f69548ff TI |
1893 | err = -EINVAL; |
1894 | goto unlock; | |
42b29870 LY |
1895 | } |
1896 | per_pin = get_pin(spec, pin_idx); | |
1897 | pin_nid = per_pin->pin_nid; | |
4846a67e TI |
1898 | |
1899 | /* Verify pin:cvt selections to avoid silent audio after S3. | |
1900 | * After S3, the audio driver restores pin:cvt selections | |
1901 | * but this can happen before gfx is ready and such selection | |
1902 | * is overlooked by HW. Thus multiple pins can share a same | |
1903 | * default convertor and mute control will affect each other, | |
1904 | * which can cause a resumed audio playback become silent | |
1905 | * after S3. | |
1906 | */ | |
1907 | pin_cvt_fixup(codec, per_pin, 0); | |
2df6742f | 1908 | |
ddd621fb LY |
1909 | /* Call sync_audio_rate to set the N/CTS/M manually if necessary */ |
1910 | /* Todo: add DP1.2 MST audio support later */ | |
93a9ff15 | 1911 | if (codec_has_acomp(codec)) |
9152085d | 1912 | snd_hdac_sync_audio_rate(&codec->core, pin_nid, per_pin->dev_id, |
f9318941 | 1913 | runtime->rate); |
ddd621fb | 1914 | |
1a6003b5 | 1915 | non_pcm = check_non_pcm_per_cvt(codec, cvt_nid); |
a4e9a38b | 1916 | mutex_lock(&per_pin->lock); |
b054087d TI |
1917 | per_pin->channels = substream->runtime->channels; |
1918 | per_pin->setup = true; | |
384a48d7 | 1919 | |
053b0559 SP |
1920 | if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) { |
1921 | stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core, | |
1922 | substream); | |
1923 | snd_hda_codec_write(codec, cvt_nid, 0, | |
1924 | AC_VERB_SET_STRIPE_CONTROL, | |
1925 | stripe); | |
1926 | } | |
1927 | ||
b054087d | 1928 | hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); |
a4e9a38b | 1929 | mutex_unlock(&per_pin->lock); |
75fae117 SW |
1930 | if (spec->dyn_pin_out) { |
1931 | pinctl = snd_hda_codec_read(codec, pin_nid, 0, | |
1932 | AC_VERB_GET_PIN_WIDGET_CONTROL, 0); | |
1933 | snd_hda_codec_write(codec, pin_nid, 0, | |
1934 | AC_VERB_SET_PIN_WIDGET_CONTROL, | |
1935 | pinctl | PIN_OUT); | |
1936 | } | |
1937 | ||
9152085d | 1938 | /* snd_hda_set_dev_select() has been called before */ |
42b29870 LY |
1939 | err = spec->ops.setup_stream(codec, cvt_nid, pin_nid, |
1940 | stream_tag, format); | |
f69548ff | 1941 | unlock: |
42b29870 LY |
1942 | mutex_unlock(&spec->pcm_lock); |
1943 | return err; | |
84eb01be TI |
1944 | } |
1945 | ||
8dfaa573 TI |
1946 | static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, |
1947 | struct hda_codec *codec, | |
1948 | struct snd_pcm_substream *substream) | |
1949 | { | |
1950 | snd_hda_codec_cleanup_stream(codec, hinfo->nid); | |
1951 | return 0; | |
1952 | } | |
1953 | ||
f2ad24fa TI |
1954 | static int hdmi_pcm_close(struct hda_pcm_stream *hinfo, |
1955 | struct hda_codec *codec, | |
1956 | struct snd_pcm_substream *substream) | |
384a48d7 SW |
1957 | { |
1958 | struct hdmi_spec *spec = codec->spec; | |
2bf3c85a | 1959 | int cvt_idx, pin_idx, pcm_idx; |
384a48d7 SW |
1960 | struct hdmi_spec_per_cvt *per_cvt; |
1961 | struct hdmi_spec_per_pin *per_pin; | |
75fae117 | 1962 | int pinctl; |
f69548ff | 1963 | int err = 0; |
384a48d7 | 1964 | |
384a48d7 | 1965 | if (hinfo->nid) { |
2bf3c85a LY |
1966 | pcm_idx = hinfo_to_pcm_index(codec, hinfo); |
1967 | if (snd_BUG_ON(pcm_idx < 0)) | |
1968 | return -EINVAL; | |
4e76a883 | 1969 | cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid); |
384a48d7 SW |
1970 | if (snd_BUG_ON(cvt_idx < 0)) |
1971 | return -EINVAL; | |
bce0d2a8 | 1972 | per_cvt = get_cvt(spec, cvt_idx); |
384a48d7 SW |
1973 | |
1974 | snd_BUG_ON(!per_cvt->assigned); | |
1975 | per_cvt->assigned = 0; | |
1976 | hinfo->nid = 0; | |
1977 | ||
42b29870 | 1978 | mutex_lock(&spec->pcm_lock); |
b09887f8 | 1979 | snd_hda_spdif_ctls_unassign(codec, pcm_idx); |
ac98379a | 1980 | clear_bit(pcm_idx, &spec->pcm_in_use); |
4e76a883 | 1981 | pin_idx = hinfo_to_pin_index(codec, hinfo); |
f69548ff TI |
1982 | if (spec->dyn_pcm_assign && pin_idx < 0) |
1983 | goto unlock; | |
42b29870 LY |
1984 | |
1985 | if (snd_BUG_ON(pin_idx < 0)) { | |
f69548ff TI |
1986 | err = -EINVAL; |
1987 | goto unlock; | |
42b29870 | 1988 | } |
bce0d2a8 | 1989 | per_pin = get_pin(spec, pin_idx); |
384a48d7 | 1990 | |
75fae117 SW |
1991 | if (spec->dyn_pin_out) { |
1992 | pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, | |
1993 | AC_VERB_GET_PIN_WIDGET_CONTROL, 0); | |
1994 | snd_hda_codec_write(codec, per_pin->pin_nid, 0, | |
1995 | AC_VERB_SET_PIN_WIDGET_CONTROL, | |
1996 | pinctl & ~PIN_OUT); | |
1997 | } | |
1998 | ||
a4e9a38b | 1999 | mutex_lock(&per_pin->lock); |
d45e6889 TI |
2000 | per_pin->chmap_set = false; |
2001 | memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); | |
b054087d TI |
2002 | |
2003 | per_pin->setup = false; | |
2004 | per_pin->channels = 0; | |
a4e9a38b | 2005 | mutex_unlock(&per_pin->lock); |
f69548ff | 2006 | unlock: |
42b29870 | 2007 | mutex_unlock(&spec->pcm_lock); |
384a48d7 | 2008 | } |
d45e6889 | 2009 | |
f69548ff | 2010 | return err; |
384a48d7 SW |
2011 | } |
2012 | ||
2013 | static const struct hda_pcm_ops generic_ops = { | |
2014 | .open = hdmi_pcm_open, | |
f2ad24fa | 2015 | .close = hdmi_pcm_close, |
384a48d7 | 2016 | .prepare = generic_hdmi_playback_pcm_prepare, |
8dfaa573 | 2017 | .cleanup = generic_hdmi_playback_pcm_cleanup, |
84eb01be TI |
2018 | }; |
2019 | ||
44fde3b8 SP |
2020 | static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx) |
2021 | { | |
2022 | struct hda_codec *codec = container_of(hdac, struct hda_codec, core); | |
2023 | struct hdmi_spec *spec = codec->spec; | |
2024 | struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); | |
2025 | ||
2026 | if (!per_pin) | |
2027 | return 0; | |
2028 | ||
2029 | return per_pin->sink_eld.info.spk_alloc; | |
2030 | } | |
2031 | ||
9b3dc8aa SP |
2032 | static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx, |
2033 | unsigned char *chmap) | |
2034 | { | |
2035 | struct hda_codec *codec = container_of(hdac, struct hda_codec, core); | |
2036 | struct hdmi_spec *spec = codec->spec; | |
2037 | struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); | |
2038 | ||
2039 | /* chmap is already set to 0 in caller */ | |
2040 | if (!per_pin) | |
2041 | return; | |
2042 | ||
2043 | memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap)); | |
2044 | } | |
2045 | ||
2046 | static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx, | |
2047 | unsigned char *chmap, int prepared) | |
2048 | { | |
2049 | struct hda_codec *codec = container_of(hdac, struct hda_codec, core); | |
2050 | struct hdmi_spec *spec = codec->spec; | |
2051 | struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); | |
2052 | ||
ed0739b5 LY |
2053 | if (!per_pin) |
2054 | return; | |
9b3dc8aa SP |
2055 | mutex_lock(&per_pin->lock); |
2056 | per_pin->chmap_set = true; | |
2057 | memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap)); | |
2058 | if (prepared) | |
2059 | hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); | |
2060 | mutex_unlock(&per_pin->lock); | |
2061 | } | |
2062 | ||
2063 | static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx) | |
2064 | { | |
2065 | struct hda_codec *codec = container_of(hdac, struct hda_codec, core); | |
2066 | struct hdmi_spec *spec = codec->spec; | |
2067 | struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); | |
2068 | ||
2069 | return per_pin ? true:false; | |
2070 | } | |
2071 | ||
84eb01be TI |
2072 | static int generic_hdmi_build_pcms(struct hda_codec *codec) |
2073 | { | |
2074 | struct hdmi_spec *spec = codec->spec; | |
9152085d | 2075 | int idx; |
84eb01be | 2076 | |
9152085d LY |
2077 | /* |
2078 | * for non-mst mode, pcm number is the same as before | |
2079 | * for DP MST mode, pcm number is (nid number + dev_num - 1) | |
2080 | * dev_num is the device entry number in a pin | |
2081 | * | |
2082 | */ | |
2083 | for (idx = 0; idx < spec->num_nids + spec->dev_num - 1; idx++) { | |
384a48d7 | 2084 | struct hda_pcm *info; |
84eb01be | 2085 | struct hda_pcm_stream *pstr; |
bce0d2a8 | 2086 | |
9152085d | 2087 | info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx); |
bce0d2a8 TI |
2088 | if (!info) |
2089 | return -ENOMEM; | |
2bea241a | 2090 | |
9152085d | 2091 | spec->pcm_rec[idx].pcm = info; |
2bf3c85a | 2092 | spec->pcm_used++; |
84eb01be | 2093 | info->pcm_type = HDA_PCM_TYPE_HDMI; |
d45e6889 | 2094 | info->own_chmap = true; |
384a48d7 | 2095 | |
84eb01be | 2096 | pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; |
384a48d7 SW |
2097 | pstr->substreams = 1; |
2098 | pstr->ops = generic_ops; | |
9152085d LY |
2099 | /* pcm number is less than 16 */ |
2100 | if (spec->pcm_used >= 16) | |
2101 | break; | |
384a48d7 | 2102 | /* other pstr fields are set in open */ |
84eb01be TI |
2103 | } |
2104 | ||
2105 | return 0; | |
2106 | } | |
2107 | ||
25e4abb3 | 2108 | static void free_hdmi_jack_priv(struct snd_jack *jack) |
788d441a | 2109 | { |
25e4abb3 | 2110 | struct hdmi_pcm *pcm = jack->private_data; |
788d441a | 2111 | |
25e4abb3 | 2112 | pcm->jack = NULL; |
788d441a TI |
2113 | } |
2114 | ||
25e4abb3 LY |
2115 | static int add_hdmi_jack_kctl(struct hda_codec *codec, |
2116 | struct hdmi_spec *spec, | |
2117 | int pcm_idx, | |
788d441a TI |
2118 | const char *name) |
2119 | { | |
2120 | struct snd_jack *jack; | |
2121 | int err; | |
2122 | ||
2123 | err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack, | |
2124 | true, false); | |
2125 | if (err < 0) | |
2126 | return err; | |
25e4abb3 LY |
2127 | |
2128 | spec->pcm_rec[pcm_idx].jack = jack; | |
2129 | jack->private_data = &spec->pcm_rec[pcm_idx]; | |
2130 | jack->private_free = free_hdmi_jack_priv; | |
788d441a TI |
2131 | return 0; |
2132 | } | |
2133 | ||
25e4abb3 | 2134 | static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx) |
0b6c49b5 | 2135 | { |
31ef2257 | 2136 | char hdmi_str[32] = "HDMI/DP"; |
0b6c49b5 | 2137 | struct hdmi_spec *spec = codec->spec; |
25e4abb3 LY |
2138 | struct hdmi_spec_per_pin *per_pin; |
2139 | struct hda_jack_tbl *jack; | |
2140 | int pcmdev = get_pcm_rec(spec, pcm_idx)->device; | |
909cadc6 | 2141 | bool phantom_jack; |
25e4abb3 | 2142 | int ret; |
0b6c49b5 | 2143 | |
31ef2257 TI |
2144 | if (pcmdev > 0) |
2145 | sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev); | |
25e4abb3 LY |
2146 | |
2147 | if (spec->dyn_pcm_assign) | |
2148 | return add_hdmi_jack_kctl(codec, spec, pcm_idx, hdmi_str); | |
2149 | ||
2150 | /* for !dyn_pcm_assign, we still use hda_jack for compatibility */ | |
2151 | /* if !dyn_pcm_assign, it must be non-MST mode. | |
2152 | * This means pcms and pins are statically mapped. | |
2153 | * And pcm_idx is pin_idx. | |
2154 | */ | |
2155 | per_pin = get_pin(spec, pcm_idx); | |
909cadc6 TI |
2156 | phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid); |
2157 | if (phantom_jack) | |
30efd8de DH |
2158 | strncat(hdmi_str, " Phantom", |
2159 | sizeof(hdmi_str) - strlen(hdmi_str) - 1); | |
25e4abb3 | 2160 | ret = snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, |
911761c2 | 2161 | phantom_jack, 0, NULL); |
25e4abb3 LY |
2162 | if (ret < 0) |
2163 | return ret; | |
2164 | jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid); | |
2165 | if (jack == NULL) | |
2166 | return 0; | |
2167 | /* assign jack->jack to pcm_rec[].jack to | |
2168 | * align with dyn_pcm_assign mode | |
2169 | */ | |
2170 | spec->pcm_rec[pcm_idx].jack = jack->jack; | |
2171 | return 0; | |
0b6c49b5 DH |
2172 | } |
2173 | ||
84eb01be TI |
2174 | static int generic_hdmi_build_controls(struct hda_codec *codec) |
2175 | { | |
2176 | struct hdmi_spec *spec = codec->spec; | |
1f7f51a6 | 2177 | int dev, err; |
25e4abb3 | 2178 | int pin_idx, pcm_idx; |
84eb01be | 2179 | |
25e4abb3 | 2180 | for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { |
8a7d6003 TI |
2181 | if (!get_pcm_rec(spec, pcm_idx)->pcm) { |
2182 | /* no PCM: mark this for skipping permanently */ | |
2183 | set_bit(pcm_idx, &spec->pcm_bitmap); | |
2184 | continue; | |
2185 | } | |
2186 | ||
25e4abb3 | 2187 | err = generic_hdmi_build_jack(codec, pcm_idx); |
0b6c49b5 DH |
2188 | if (err < 0) |
2189 | return err; | |
2190 | ||
b09887f8 LY |
2191 | /* create the spdif for each pcm |
2192 | * pin will be bound when monitor is connected | |
2193 | */ | |
2194 | if (spec->dyn_pcm_assign) | |
2195 | err = snd_hda_create_dig_out_ctls(codec, | |
2196 | 0, spec->cvt_nids[0], | |
2197 | HDA_PCM_TYPE_HDMI); | |
2198 | else { | |
2199 | struct hdmi_spec_per_pin *per_pin = | |
2200 | get_pin(spec, pcm_idx); | |
2201 | err = snd_hda_create_dig_out_ctls(codec, | |
dcda5806 TI |
2202 | per_pin->pin_nid, |
2203 | per_pin->mux_nids[0], | |
2204 | HDA_PCM_TYPE_HDMI); | |
b09887f8 | 2205 | } |
84eb01be TI |
2206 | if (err < 0) |
2207 | return err; | |
b09887f8 | 2208 | snd_hda_spdif_ctls_unassign(codec, pcm_idx); |
14bc52b8 | 2209 | |
1f7f51a6 WY |
2210 | dev = get_pcm_rec(spec, pcm_idx)->device; |
2211 | if (dev != SNDRV_PCM_INVALID_DEVICE) { | |
2212 | /* add control for ELD Bytes */ | |
2213 | err = hdmi_create_eld_ctl(codec, pcm_idx, dev); | |
2214 | if (err < 0) | |
2215 | return err; | |
2216 | } | |
fb087eaa LY |
2217 | } |
2218 | ||
2219 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { | |
2220 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); | |
31ef2257 | 2221 | |
82b1d73f | 2222 | hdmi_present_sense(per_pin, 0); |
84eb01be TI |
2223 | } |
2224 | ||
d45e6889 | 2225 | /* add channel maps */ |
022f344b | 2226 | for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { |
bbbc7e85 | 2227 | struct hda_pcm *pcm; |
2ca320e2 | 2228 | |
022f344b | 2229 | pcm = get_pcm_rec(spec, pcm_idx); |
bbbc7e85 | 2230 | if (!pcm || !pcm->pcm) |
2ca320e2 | 2231 | break; |
2f6e8a85 | 2232 | err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap); |
d45e6889 TI |
2233 | if (err < 0) |
2234 | return err; | |
d45e6889 TI |
2235 | } |
2236 | ||
84eb01be TI |
2237 | return 0; |
2238 | } | |
2239 | ||
8b8d654b | 2240 | static int generic_hdmi_init_per_pins(struct hda_codec *codec) |
84eb01be TI |
2241 | { |
2242 | struct hdmi_spec *spec = codec->spec; | |
384a48d7 SW |
2243 | int pin_idx; |
2244 | ||
2245 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { | |
bce0d2a8 | 2246 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); |
84eb01be | 2247 | |
744626da | 2248 | per_pin->codec = codec; |
a4e9a38b | 2249 | mutex_init(&per_pin->lock); |
744626da | 2250 | INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld); |
a4e9a38b | 2251 | eld_proc_new(per_pin, pin_idx); |
84eb01be | 2252 | } |
8b8d654b TI |
2253 | return 0; |
2254 | } | |
2255 | ||
2256 | static int generic_hdmi_init(struct hda_codec *codec) | |
2257 | { | |
2258 | struct hdmi_spec *spec = codec->spec; | |
2259 | int pin_idx; | |
2260 | ||
ade49db3 TI |
2261 | mutex_lock(&spec->pcm_lock); |
2262 | spec->use_jack_detect = !codec->jackpoll_interval; | |
8b8d654b | 2263 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { |
bce0d2a8 | 2264 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); |
8b8d654b | 2265 | hda_nid_t pin_nid = per_pin->pin_nid; |
9152085d | 2266 | int dev_id = per_pin->dev_id; |
8b8d654b | 2267 | |
9152085d | 2268 | snd_hda_set_dev_select(codec, pin_nid, dev_id); |
8b8d654b | 2269 | hdmi_init_pin(codec, pin_nid); |
ade49db3 TI |
2270 | if (codec_has_acomp(codec)) |
2271 | continue; | |
2272 | if (spec->use_jack_detect) | |
2273 | snd_hda_jack_detect_enable(codec, pin_nid); | |
2274 | else | |
788d441a | 2275 | snd_hda_jack_detect_enable_callback(codec, pin_nid, |
ade49db3 | 2276 | jack_callback); |
8b8d654b | 2277 | } |
ade49db3 | 2278 | mutex_unlock(&spec->pcm_lock); |
84eb01be TI |
2279 | return 0; |
2280 | } | |
2281 | ||
bce0d2a8 TI |
2282 | static void hdmi_array_init(struct hdmi_spec *spec, int nums) |
2283 | { | |
2284 | snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums); | |
2285 | snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums); | |
bce0d2a8 TI |
2286 | } |
2287 | ||
2288 | static void hdmi_array_free(struct hdmi_spec *spec) | |
2289 | { | |
2290 | snd_array_free(&spec->pins); | |
2291 | snd_array_free(&spec->cvts); | |
bce0d2a8 TI |
2292 | } |
2293 | ||
a686632f TI |
2294 | static void generic_spec_free(struct hda_codec *codec) |
2295 | { | |
2296 | struct hdmi_spec *spec = codec->spec; | |
2297 | ||
2298 | if (spec) { | |
2299 | hdmi_array_free(spec); | |
2300 | kfree(spec); | |
2301 | codec->spec = NULL; | |
2302 | } | |
2303 | codec->dp_mst = false; | |
2304 | } | |
2305 | ||
84eb01be TI |
2306 | static void generic_hdmi_free(struct hda_codec *codec) |
2307 | { | |
2308 | struct hdmi_spec *spec = codec->spec; | |
25e4abb3 | 2309 | int pin_idx, pcm_idx; |
384a48d7 | 2310 | |
ade49db3 TI |
2311 | if (spec->acomp_registered) { |
2312 | snd_hdac_acomp_exit(&codec->bus->core); | |
2313 | } else if (codec_has_acomp(codec)) { | |
a57942bf | 2314 | snd_hdac_acomp_register_notifier(&codec->bus->core, NULL); |
4914da2f TI |
2315 | codec->relaxed_resume = 0; |
2316 | } | |
25adc137 | 2317 | |
384a48d7 | 2318 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { |
bce0d2a8 | 2319 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); |
2f35c630 | 2320 | cancel_delayed_work_sync(&per_pin->work); |
a4e9a38b | 2321 | eld_proc_free(per_pin); |
25e4abb3 LY |
2322 | } |
2323 | ||
2324 | for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { | |
2325 | if (spec->pcm_rec[pcm_idx].jack == NULL) | |
2326 | continue; | |
2327 | if (spec->dyn_pcm_assign) | |
2328 | snd_device_free(codec->card, | |
2329 | spec->pcm_rec[pcm_idx].jack); | |
2330 | else | |
2331 | spec->pcm_rec[pcm_idx].jack = NULL; | |
384a48d7 | 2332 | } |
84eb01be | 2333 | |
a686632f | 2334 | generic_spec_free(codec); |
84eb01be TI |
2335 | } |
2336 | ||
28cb72e5 WX |
2337 | #ifdef CONFIG_PM |
2338 | static int generic_hdmi_resume(struct hda_codec *codec) | |
2339 | { | |
2340 | struct hdmi_spec *spec = codec->spec; | |
2341 | int pin_idx; | |
2342 | ||
a2833683 | 2343 | codec->patch_ops.init(codec); |
eeecd9d1 | 2344 | regcache_sync(codec->core.regmap); |
28cb72e5 WX |
2345 | |
2346 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { | |
2347 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); | |
2348 | hdmi_present_sense(per_pin, 1); | |
2349 | } | |
2350 | return 0; | |
2351 | } | |
2352 | #endif | |
2353 | ||
fb79e1e0 | 2354 | static const struct hda_codec_ops generic_hdmi_patch_ops = { |
84eb01be TI |
2355 | .init = generic_hdmi_init, |
2356 | .free = generic_hdmi_free, | |
2357 | .build_pcms = generic_hdmi_build_pcms, | |
2358 | .build_controls = generic_hdmi_build_controls, | |
2359 | .unsol_event = hdmi_unsol_event, | |
28cb72e5 WX |
2360 | #ifdef CONFIG_PM |
2361 | .resume = generic_hdmi_resume, | |
2362 | #endif | |
84eb01be TI |
2363 | }; |
2364 | ||
307229d2 AH |
2365 | static const struct hdmi_ops generic_standard_hdmi_ops = { |
2366 | .pin_get_eld = snd_hdmi_get_eld, | |
307229d2 AH |
2367 | .pin_setup_infoframe = hdmi_pin_setup_infoframe, |
2368 | .pin_hbr_setup = hdmi_pin_hbr_setup, | |
2369 | .setup_stream = hdmi_setup_stream, | |
67b90cb8 SP |
2370 | }; |
2371 | ||
a686632f TI |
2372 | /* allocate codec->spec and assign/initialize generic parser ops */ |
2373 | static int alloc_generic_hdmi(struct hda_codec *codec) | |
2374 | { | |
2375 | struct hdmi_spec *spec; | |
2376 | ||
2377 | spec = kzalloc(sizeof(*spec), GFP_KERNEL); | |
2378 | if (!spec) | |
2379 | return -ENOMEM; | |
2380 | ||
ade49db3 | 2381 | spec->codec = codec; |
a686632f | 2382 | spec->ops = generic_standard_hdmi_ops; |
9152085d | 2383 | spec->dev_num = 1; /* initialize to 1 */ |
a686632f TI |
2384 | mutex_init(&spec->pcm_lock); |
2385 | snd_hdac_register_chmap_ops(&codec->core, &spec->chmap); | |
2386 | ||
2387 | spec->chmap.ops.get_chmap = hdmi_get_chmap; | |
2388 | spec->chmap.ops.set_chmap = hdmi_set_chmap; | |
2389 | spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached; | |
44fde3b8 | 2390 | spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc, |
a686632f TI |
2391 | |
2392 | codec->spec = spec; | |
2393 | hdmi_array_init(spec, 4); | |
2394 | ||
2395 | codec->patch_ops = generic_hdmi_patch_ops; | |
2396 | ||
2397 | return 0; | |
2398 | } | |
2399 | ||
2400 | /* generic HDMI parser */ | |
2401 | static int patch_generic_hdmi(struct hda_codec *codec) | |
2402 | { | |
2403 | int err; | |
2404 | ||
2405 | err = alloc_generic_hdmi(codec); | |
2406 | if (err < 0) | |
2407 | return err; | |
2408 | ||
2409 | err = hdmi_parse_codec(codec); | |
2410 | if (err < 0) { | |
2411 | generic_spec_free(codec); | |
2412 | return err; | |
2413 | } | |
2414 | ||
2415 | generic_hdmi_init_per_pins(codec); | |
2416 | return 0; | |
2417 | } | |
2418 | ||
ade49db3 TI |
2419 | /* |
2420 | * generic audio component binding | |
2421 | */ | |
2422 | ||
2423 | /* turn on / off the unsol event jack detection dynamically */ | |
2424 | static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid, | |
2425 | bool use_acomp) | |
2426 | { | |
2427 | struct hda_jack_tbl *tbl; | |
2428 | ||
2429 | tbl = snd_hda_jack_tbl_get(codec, nid); | |
2430 | if (tbl) { | |
2431 | /* clear unsol even if component notifier is used, or re-enable | |
2432 | * if notifier is cleared | |
2433 | */ | |
2434 | unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag); | |
2435 | snd_hda_codec_write_cache(codec, nid, 0, | |
2436 | AC_VERB_SET_UNSOLICITED_ENABLE, val); | |
2437 | } else { | |
2438 | /* if no jack entry was defined beforehand, create a new one | |
2439 | * at need (i.e. only when notifier is cleared) | |
2440 | */ | |
2441 | if (!use_acomp) | |
2442 | snd_hda_jack_detect_enable(codec, nid); | |
2443 | } | |
2444 | } | |
2445 | ||
2446 | /* set up / clear component notifier dynamically */ | |
2447 | static void generic_acomp_notifier_set(struct drm_audio_component *acomp, | |
2448 | bool use_acomp) | |
2449 | { | |
2450 | struct hdmi_spec *spec; | |
2451 | int i; | |
2452 | ||
2453 | spec = container_of(acomp->audio_ops, struct hdmi_spec, drm_audio_ops); | |
2454 | mutex_lock(&spec->pcm_lock); | |
2455 | spec->use_acomp_notifier = use_acomp; | |
2456 | spec->codec->relaxed_resume = use_acomp; | |
2457 | /* reprogram each jack detection logic depending on the notifier */ | |
2458 | if (spec->use_jack_detect) { | |
2459 | for (i = 0; i < spec->num_pins; i++) | |
2460 | reprogram_jack_detect(spec->codec, | |
2461 | get_pin(spec, i)->pin_nid, | |
2462 | use_acomp); | |
2463 | } | |
2464 | mutex_unlock(&spec->pcm_lock); | |
2465 | } | |
2466 | ||
2467 | /* enable / disable the notifier via master bind / unbind */ | |
2468 | static int generic_acomp_master_bind(struct device *dev, | |
2469 | struct drm_audio_component *acomp) | |
2470 | { | |
2471 | generic_acomp_notifier_set(acomp, true); | |
2472 | return 0; | |
2473 | } | |
2474 | ||
2475 | static void generic_acomp_master_unbind(struct device *dev, | |
2476 | struct drm_audio_component *acomp) | |
2477 | { | |
2478 | generic_acomp_notifier_set(acomp, false); | |
2479 | } | |
2480 | ||
2481 | /* check whether both HD-audio and DRM PCI devices belong to the same bus */ | |
2482 | static int match_bound_vga(struct device *dev, int subtype, void *data) | |
2483 | { | |
2484 | struct hdac_bus *bus = data; | |
2485 | struct pci_dev *pci, *master; | |
2486 | ||
2487 | if (!dev_is_pci(dev) || !dev_is_pci(bus->dev)) | |
2488 | return 0; | |
2489 | master = to_pci_dev(bus->dev); | |
2490 | pci = to_pci_dev(dev); | |
2491 | return master->bus == pci->bus; | |
2492 | } | |
2493 | ||
2494 | /* audio component notifier for AMD/Nvidia HDMI codecs */ | |
2495 | static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id) | |
2496 | { | |
2497 | struct hda_codec *codec = audio_ptr; | |
2498 | struct hdmi_spec *spec = codec->spec; | |
2499 | hda_nid_t pin_nid = spec->port2pin(codec, port); | |
2500 | ||
2501 | if (!pin_nid) | |
2502 | return; | |
2503 | if (get_wcaps_type(get_wcaps(codec, pin_nid)) != AC_WID_PIN) | |
2504 | return; | |
2505 | /* skip notification during system suspend (but not in runtime PM); | |
2506 | * the state will be updated at resume | |
2507 | */ | |
2508 | if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0) | |
2509 | return; | |
2510 | /* ditto during suspend/resume process itself */ | |
2511 | if (snd_hdac_is_in_pm(&codec->core)) | |
2512 | return; | |
2513 | ||
2514 | check_presence_and_report(codec, pin_nid, dev_id); | |
2515 | } | |
2516 | ||
2517 | /* set up the private drm_audio_ops from the template */ | |
2518 | static void setup_drm_audio_ops(struct hda_codec *codec, | |
2519 | const struct drm_audio_component_audio_ops *ops) | |
2520 | { | |
2521 | struct hdmi_spec *spec = codec->spec; | |
2522 | ||
2523 | spec->drm_audio_ops.audio_ptr = codec; | |
2524 | /* intel_audio_codec_enable() or intel_audio_codec_disable() | |
2525 | * will call pin_eld_notify with using audio_ptr pointer | |
2526 | * We need make sure audio_ptr is really setup | |
2527 | */ | |
2528 | wmb(); | |
2529 | spec->drm_audio_ops.pin2port = ops->pin2port; | |
2530 | spec->drm_audio_ops.pin_eld_notify = ops->pin_eld_notify; | |
2531 | spec->drm_audio_ops.master_bind = ops->master_bind; | |
2532 | spec->drm_audio_ops.master_unbind = ops->master_unbind; | |
2533 | } | |
2534 | ||
2535 | /* initialize the generic HDMI audio component */ | |
2536 | static void generic_acomp_init(struct hda_codec *codec, | |
2537 | const struct drm_audio_component_audio_ops *ops, | |
2538 | int (*port2pin)(struct hda_codec *, int)) | |
2539 | { | |
2540 | struct hdmi_spec *spec = codec->spec; | |
2541 | ||
2542 | spec->port2pin = port2pin; | |
2543 | setup_drm_audio_ops(codec, ops); | |
2544 | if (!snd_hdac_acomp_init(&codec->bus->core, &spec->drm_audio_ops, | |
2545 | match_bound_vga, 0)) | |
2546 | spec->acomp_registered = true; | |
2547 | } | |
2548 | ||
a686632f TI |
2549 | /* |
2550 | * Intel codec parsers and helpers | |
2551 | */ | |
2552 | ||
c88d4e84 TI |
2553 | static void intel_haswell_fixup_connect_list(struct hda_codec *codec, |
2554 | hda_nid_t nid) | |
2555 | { | |
2556 | struct hdmi_spec *spec = codec->spec; | |
2557 | hda_nid_t conns[4]; | |
2558 | int nconns; | |
6ffe168f | 2559 | |
c88d4e84 TI |
2560 | nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns)); |
2561 | if (nconns == spec->num_cvts && | |
2562 | !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t))) | |
6ffe168f ML |
2563 | return; |
2564 | ||
c88d4e84 | 2565 | /* override pins connection list */ |
4e76a883 | 2566 | codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid); |
c88d4e84 | 2567 | snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids); |
6ffe168f ML |
2568 | } |
2569 | ||
b0d8bc50 JK |
2570 | #define INTEL_GET_VENDOR_VERB 0xf81 |
2571 | #define INTEL_SET_VENDOR_VERB 0x781 | |
2572 | #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */ | |
2573 | #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */ | |
1611a9c9 ML |
2574 | |
2575 | static void intel_haswell_enable_all_pins(struct hda_codec *codec, | |
17df3f55 | 2576 | bool update_tree) |
1611a9c9 ML |
2577 | { |
2578 | unsigned int vendor_param; | |
a87a4d23 | 2579 | struct hdmi_spec *spec = codec->spec; |
1611a9c9 | 2580 | |
a87a4d23 | 2581 | vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, |
1611a9c9 ML |
2582 | INTEL_GET_VENDOR_VERB, 0); |
2583 | if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS) | |
2584 | return; | |
2585 | ||
2586 | vendor_param |= INTEL_EN_ALL_PIN_CVTS; | |
a87a4d23 | 2587 | vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, |
1611a9c9 ML |
2588 | INTEL_SET_VENDOR_VERB, vendor_param); |
2589 | if (vendor_param == -1) | |
2590 | return; | |
2591 | ||
17df3f55 TI |
2592 | if (update_tree) |
2593 | snd_hda_codec_update_widgets(codec); | |
1611a9c9 ML |
2594 | } |
2595 | ||
c88d4e84 TI |
2596 | static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec) |
2597 | { | |
2598 | unsigned int vendor_param; | |
a87a4d23 | 2599 | struct hdmi_spec *spec = codec->spec; |
c88d4e84 | 2600 | |
a87a4d23 | 2601 | vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, |
c88d4e84 TI |
2602 | INTEL_GET_VENDOR_VERB, 0); |
2603 | if (vendor_param == -1 || vendor_param & INTEL_EN_DP12) | |
2604 | return; | |
2605 | ||
2606 | /* enable DP1.2 mode */ | |
2607 | vendor_param |= INTEL_EN_DP12; | |
a551d914 | 2608 | snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB); |
a87a4d23 | 2609 | snd_hda_codec_write_cache(codec, spec->vendor_nid, 0, |
c88d4e84 TI |
2610 | INTEL_SET_VENDOR_VERB, vendor_param); |
2611 | } | |
2612 | ||
17df3f55 TI |
2613 | /* Haswell needs to re-issue the vendor-specific verbs before turning to D0. |
2614 | * Otherwise you may get severe h/w communication errors. | |
2615 | */ | |
2616 | static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg, | |
2617 | unsigned int power_state) | |
2618 | { | |
2619 | if (power_state == AC_PWRST_D0) { | |
2620 | intel_haswell_enable_all_pins(codec, false); | |
2621 | intel_haswell_fixup_enable_dp12(codec); | |
2622 | } | |
c88d4e84 | 2623 | |
17df3f55 TI |
2624 | snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state); |
2625 | snd_hda_codec_set_power_to_all(codec, fg, power_state); | |
2626 | } | |
6ffe168f | 2627 | |
a57942bf TI |
2628 | /* There is a fixed mapping between audio pin node and display port. |
2629 | * on SNB, IVY, HSW, BSW, SKL, BXT, KBL: | |
2630 | * Pin Widget 5 - PORT B (port = 1 in i915 driver) | |
2631 | * Pin Widget 6 - PORT C (port = 2 in i915 driver) | |
2632 | * Pin Widget 7 - PORT D (port = 3 in i915 driver) | |
2633 | * | |
2634 | * on VLV, ILK: | |
2635 | * Pin Widget 4 - PORT B (port = 1 in i915 driver) | |
2636 | * Pin Widget 5 - PORT C (port = 2 in i915 driver) | |
2637 | * Pin Widget 6 - PORT D (port = 3 in i915 driver) | |
2638 | */ | |
2639 | static int intel_base_nid(struct hda_codec *codec) | |
2640 | { | |
2641 | switch (codec->core.vendor_id) { | |
2642 | case 0x80860054: /* ILK */ | |
2643 | case 0x80862804: /* ILK */ | |
2644 | case 0x80862882: /* VLV */ | |
2645 | return 4; | |
2646 | default: | |
2647 | return 5; | |
2648 | } | |
2649 | } | |
2650 | ||
2651 | static int intel_pin2port(void *audio_ptr, int pin_nid) | |
2652 | { | |
b0d8bc50 JK |
2653 | struct hda_codec *codec = audio_ptr; |
2654 | struct hdmi_spec *spec = codec->spec; | |
2655 | int base_nid, i; | |
a57942bf | 2656 | |
b0d8bc50 JK |
2657 | if (!spec->port_num) { |
2658 | base_nid = intel_base_nid(codec); | |
2659 | if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3)) | |
2660 | return -1; | |
2661 | return pin_nid - base_nid + 1; /* intel port is 1-based */ | |
2662 | } | |
2663 | ||
2664 | /* | |
2665 | * looking for the pin number in the mapping table and return | |
2666 | * the index which indicate the port number | |
2667 | */ | |
2668 | for (i = 0; i < spec->port_num; i++) { | |
2669 | if (pin_nid == spec->port_map[i]) | |
2670 | return i + 1; | |
2671 | } | |
2672 | ||
2673 | /* return -1 if pin number exceeds our expectation */ | |
2674 | codec_info(codec, "Can't find the HDMI/DP port for pin %d\n", pin_nid); | |
2675 | return -1; | |
a57942bf TI |
2676 | } |
2677 | ||
3140aafb TI |
2678 | static int intel_port2pin(struct hda_codec *codec, int port) |
2679 | { | |
2680 | struct hdmi_spec *spec = codec->spec; | |
2681 | ||
2682 | if (!spec->port_num) { | |
2683 | /* we assume only from port-B to port-D */ | |
2684 | if (port < 1 || port > 3) | |
2685 | return 0; | |
2686 | /* intel port is 1-based */ | |
2687 | return port + intel_base_nid(codec) - 1; | |
2688 | } | |
2689 | ||
2690 | if (port < 1 || port > spec->port_num) | |
2691 | return 0; | |
2692 | return spec->port_map[port - 1]; | |
2693 | } | |
2694 | ||
f9318941 | 2695 | static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe) |
25adc137 DH |
2696 | { |
2697 | struct hda_codec *codec = audio_ptr; | |
7ff652ff | 2698 | int pin_nid; |
9152085d | 2699 | int dev_id = pipe; |
25adc137 | 2700 | |
3140aafb TI |
2701 | pin_nid = intel_port2pin(codec, port); |
2702 | if (!pin_nid) | |
4f8e4f35 | 2703 | return; |
8ae743e8 TI |
2704 | /* skip notification during system suspend (but not in runtime PM); |
2705 | * the state will be updated at resume | |
2706 | */ | |
2707 | if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0) | |
2708 | return; | |
eb399d3c | 2709 | /* ditto during suspend/resume process itself */ |
feb20fae | 2710 | if (snd_hdac_is_in_pm(&codec->core)) |
eb399d3c | 2711 | return; |
8ae743e8 | 2712 | |
bb03ed21 | 2713 | snd_hdac_i915_set_bclk(&codec->bus->core); |
9152085d | 2714 | check_presence_and_report(codec, pin_nid, dev_id); |
25adc137 DH |
2715 | } |
2716 | ||
ade49db3 TI |
2717 | static const struct drm_audio_component_audio_ops intel_audio_ops = { |
2718 | .pin2port = intel_pin2port, | |
2719 | .pin_eld_notify = intel_pin_eld_notify, | |
2720 | }; | |
2721 | ||
a686632f TI |
2722 | /* register i915 component pin_eld_notify callback */ |
2723 | static void register_i915_notifier(struct hda_codec *codec) | |
84eb01be | 2724 | { |
a686632f | 2725 | struct hdmi_spec *spec = codec->spec; |
84eb01be | 2726 | |
a686632f | 2727 | spec->use_acomp_notifier = true; |
ade49db3 TI |
2728 | spec->port2pin = intel_port2pin; |
2729 | setup_drm_audio_ops(codec, &intel_audio_ops); | |
a57942bf | 2730 | snd_hdac_acomp_register_notifier(&codec->bus->core, |
82887c0b | 2731 | &spec->drm_audio_ops); |
4914da2f TI |
2732 | /* no need for forcible resume for jack check thanks to notifier */ |
2733 | codec->relaxed_resume = 1; | |
a686632f | 2734 | } |
84eb01be | 2735 | |
2c1c9b86 TI |
2736 | /* setup_stream ops override for HSW+ */ |
2737 | static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, | |
2738 | hda_nid_t pin_nid, u32 stream_tag, int format) | |
2739 | { | |
2740 | haswell_verify_D0(codec, cvt_nid, pin_nid); | |
2741 | return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format); | |
2742 | } | |
739ffee9 | 2743 | |
4846a67e TI |
2744 | /* pin_cvt_fixup ops override for HSW+ and VLV+ */ |
2745 | static void i915_pin_cvt_fixup(struct hda_codec *codec, | |
2746 | struct hdmi_spec_per_pin *per_pin, | |
2747 | hda_nid_t cvt_nid) | |
2748 | { | |
2749 | if (per_pin) { | |
9152085d LY |
2750 | snd_hda_set_dev_select(codec, per_pin->pin_nid, |
2751 | per_pin->dev_id); | |
4846a67e TI |
2752 | intel_verify_pin_cvt_connect(codec, per_pin); |
2753 | intel_not_share_assigned_cvt(codec, per_pin->pin_nid, | |
9152085d | 2754 | per_pin->dev_id, per_pin->mux_idx); |
4846a67e | 2755 | } else { |
9152085d | 2756 | intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid); |
4846a67e TI |
2757 | } |
2758 | } | |
739ffee9 | 2759 | |
43f6c8d9 TI |
2760 | /* precondition and allocation for Intel codecs */ |
2761 | static int alloc_intel_hdmi(struct hda_codec *codec) | |
a686632f | 2762 | { |
43f6c8d9 | 2763 | /* requires i915 binding */ |
a686632f TI |
2764 | if (!codec->bus->core.audio_component) { |
2765 | codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n"); | |
fdd49c51 TI |
2766 | /* set probe_id here to prevent generic fallback binding */ |
2767 | codec->probe_id = HDA_CODEC_ID_SKIP_PROBE; | |
a686632f | 2768 | return -ENODEV; |
691be973 | 2769 | } |
55913110 | 2770 | |
43f6c8d9 TI |
2771 | return alloc_generic_hdmi(codec); |
2772 | } | |
2773 | ||
2774 | /* parse and post-process for Intel codecs */ | |
2775 | static int parse_intel_hdmi(struct hda_codec *codec) | |
2776 | { | |
2777 | int err; | |
2778 | ||
2779 | err = hdmi_parse_codec(codec); | |
2780 | if (err < 0) { | |
2781 | generic_spec_free(codec); | |
2782 | return err; | |
2783 | } | |
2784 | ||
2785 | generic_hdmi_init_per_pins(codec); | |
2786 | register_i915_notifier(codec); | |
2787 | return 0; | |
2788 | } | |
2789 | ||
2790 | /* Intel Haswell and onwards; audio component with eld notifier */ | |
b0d8bc50 JK |
2791 | static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid, |
2792 | const int *port_map, int port_num) | |
43f6c8d9 TI |
2793 | { |
2794 | struct hdmi_spec *spec; | |
2795 | int err; | |
2796 | ||
2797 | err = alloc_intel_hdmi(codec); | |
a686632f TI |
2798 | if (err < 0) |
2799 | return err; | |
2800 | spec = codec->spec; | |
9152085d LY |
2801 | codec->dp_mst = true; |
2802 | spec->dyn_pcm_assign = true; | |
a87a4d23 | 2803 | spec->vendor_nid = vendor_nid; |
b0d8bc50 JK |
2804 | spec->port_map = port_map; |
2805 | spec->port_num = port_num; | |
6ffe168f | 2806 | |
a686632f TI |
2807 | intel_haswell_enable_all_pins(codec, true); |
2808 | intel_haswell_fixup_enable_dp12(codec); | |
2809 | ||
46594d33 | 2810 | codec->display_power_control = 1; |
2bd1f73f | 2811 | |
a686632f | 2812 | codec->patch_ops.set_power_state = haswell_set_power_state; |
a686632f TI |
2813 | codec->depop_delay = 0; |
2814 | codec->auto_runtime_pm = 1; | |
2815 | ||
2c1c9b86 | 2816 | spec->ops.setup_stream = i915_hsw_setup_stream; |
4846a67e | 2817 | spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; |
2c1c9b86 | 2818 | |
43f6c8d9 | 2819 | return parse_intel_hdmi(codec); |
a686632f TI |
2820 | } |
2821 | ||
a87a4d23 ACDO |
2822 | static int patch_i915_hsw_hdmi(struct hda_codec *codec) |
2823 | { | |
b0d8bc50 | 2824 | return intel_hsw_common_init(codec, 0x08, NULL, 0); |
a87a4d23 ACDO |
2825 | } |
2826 | ||
2827 | static int patch_i915_glk_hdmi(struct hda_codec *codec) | |
2828 | { | |
b0d8bc50 JK |
2829 | return intel_hsw_common_init(codec, 0x0b, NULL, 0); |
2830 | } | |
2831 | ||
2832 | static int patch_i915_icl_hdmi(struct hda_codec *codec) | |
2833 | { | |
2834 | /* | |
2835 | * pin to port mapping table where the value indicate the pin number and | |
2836 | * the index indicate the port number with 1 base. | |
2837 | */ | |
2838 | static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb}; | |
2839 | ||
2840 | return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map)); | |
a87a4d23 ACDO |
2841 | } |
2842 | ||
7ff652ff | 2843 | /* Intel Baytrail and Braswell; with eld notifier */ |
a686632f TI |
2844 | static int patch_i915_byt_hdmi(struct hda_codec *codec) |
2845 | { | |
2846 | struct hdmi_spec *spec; | |
2847 | int err; | |
2848 | ||
43f6c8d9 | 2849 | err = alloc_intel_hdmi(codec); |
a686632f TI |
2850 | if (err < 0) |
2851 | return err; | |
2852 | spec = codec->spec; | |
2377c3c3 | 2853 | |
a686632f TI |
2854 | /* For Valleyview/Cherryview, only the display codec is in the display |
2855 | * power well and can use link_power ops to request/release the power. | |
2856 | */ | |
029d92c2 | 2857 | codec->display_power_control = 1; |
84eb01be | 2858 | |
a686632f TI |
2859 | codec->depop_delay = 0; |
2860 | codec->auto_runtime_pm = 1; | |
84eb01be | 2861 | |
4846a67e TI |
2862 | spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; |
2863 | ||
43f6c8d9 | 2864 | return parse_intel_hdmi(codec); |
84eb01be TI |
2865 | } |
2866 | ||
7ff652ff | 2867 | /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */ |
e85015a3 TI |
2868 | static int patch_i915_cpt_hdmi(struct hda_codec *codec) |
2869 | { | |
e85015a3 TI |
2870 | int err; |
2871 | ||
43f6c8d9 | 2872 | err = alloc_intel_hdmi(codec); |
e85015a3 TI |
2873 | if (err < 0) |
2874 | return err; | |
43f6c8d9 | 2875 | return parse_intel_hdmi(codec); |
84eb01be TI |
2876 | } |
2877 | ||
3aaf8980 SW |
2878 | /* |
2879 | * Shared non-generic implementations | |
2880 | */ | |
2881 | ||
2882 | static int simple_playback_build_pcms(struct hda_codec *codec) | |
2883 | { | |
2884 | struct hdmi_spec *spec = codec->spec; | |
bce0d2a8 | 2885 | struct hda_pcm *info; |
8ceb332d TI |
2886 | unsigned int chans; |
2887 | struct hda_pcm_stream *pstr; | |
bce0d2a8 | 2888 | struct hdmi_spec_per_cvt *per_cvt; |
3aaf8980 | 2889 | |
bce0d2a8 TI |
2890 | per_cvt = get_cvt(spec, 0); |
2891 | chans = get_wcaps(codec, per_cvt->cvt_nid); | |
8ceb332d | 2892 | chans = get_wcaps_channels(chans); |
3aaf8980 | 2893 | |
bbbc7e85 | 2894 | info = snd_hda_codec_pcm_new(codec, "HDMI 0"); |
bce0d2a8 TI |
2895 | if (!info) |
2896 | return -ENOMEM; | |
2bea241a | 2897 | spec->pcm_rec[0].pcm = info; |
8ceb332d TI |
2898 | info->pcm_type = HDA_PCM_TYPE_HDMI; |
2899 | pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; | |
2900 | *pstr = spec->pcm_playback; | |
bce0d2a8 | 2901 | pstr->nid = per_cvt->cvt_nid; |
8ceb332d TI |
2902 | if (pstr->channels_max <= 2 && chans && chans <= 16) |
2903 | pstr->channels_max = chans; | |
3aaf8980 SW |
2904 | |
2905 | return 0; | |
2906 | } | |
2907 | ||
4b6ace9e TI |
2908 | /* unsolicited event for jack sensing */ |
2909 | static void simple_hdmi_unsol_event(struct hda_codec *codec, | |
2910 | unsigned int res) | |
2911 | { | |
9dd8cf12 | 2912 | snd_hda_jack_set_dirty_all(codec); |
4b6ace9e TI |
2913 | snd_hda_jack_report_sync(codec); |
2914 | } | |
2915 | ||
2916 | /* generic_hdmi_build_jack can be used for simple_hdmi, too, | |
2917 | * as long as spec->pins[] is set correctly | |
2918 | */ | |
2919 | #define simple_hdmi_build_jack generic_hdmi_build_jack | |
2920 | ||
3aaf8980 SW |
2921 | static int simple_playback_build_controls(struct hda_codec *codec) |
2922 | { | |
2923 | struct hdmi_spec *spec = codec->spec; | |
bce0d2a8 | 2924 | struct hdmi_spec_per_cvt *per_cvt; |
3aaf8980 | 2925 | int err; |
3aaf8980 | 2926 | |
bce0d2a8 | 2927 | per_cvt = get_cvt(spec, 0); |
c9a6338a AH |
2928 | err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid, |
2929 | per_cvt->cvt_nid, | |
2930 | HDA_PCM_TYPE_HDMI); | |
8ceb332d TI |
2931 | if (err < 0) |
2932 | return err; | |
2933 | return simple_hdmi_build_jack(codec, 0); | |
3aaf8980 SW |
2934 | } |
2935 | ||
4f0110ce TI |
2936 | static int simple_playback_init(struct hda_codec *codec) |
2937 | { | |
2938 | struct hdmi_spec *spec = codec->spec; | |
bce0d2a8 TI |
2939 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0); |
2940 | hda_nid_t pin = per_pin->pin_nid; | |
8ceb332d TI |
2941 | |
2942 | snd_hda_codec_write(codec, pin, 0, | |
2943 | AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT); | |
2944 | /* some codecs require to unmute the pin */ | |
2945 | if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) | |
2946 | snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE, | |
2947 | AMP_OUT_UNMUTE); | |
62f949bf | 2948 | snd_hda_jack_detect_enable(codec, pin); |
4f0110ce TI |
2949 | return 0; |
2950 | } | |
2951 | ||
3aaf8980 SW |
2952 | static void simple_playback_free(struct hda_codec *codec) |
2953 | { | |
2954 | struct hdmi_spec *spec = codec->spec; | |
2955 | ||
bce0d2a8 | 2956 | hdmi_array_free(spec); |
3aaf8980 SW |
2957 | kfree(spec); |
2958 | } | |
2959 | ||
84eb01be TI |
2960 | /* |
2961 | * Nvidia specific implementations | |
2962 | */ | |
2963 | ||
2964 | #define Nv_VERB_SET_Channel_Allocation 0xF79 | |
2965 | #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A | |
2966 | #define Nv_VERB_SET_Audio_Protection_On 0xF98 | |
2967 | #define Nv_VERB_SET_Audio_Protection_Off 0xF99 | |
2968 | ||
2969 | #define nvhdmi_master_con_nid_7x 0x04 | |
2970 | #define nvhdmi_master_pin_nid_7x 0x05 | |
2971 | ||
fb79e1e0 | 2972 | static const hda_nid_t nvhdmi_con_nids_7x[4] = { |
84eb01be TI |
2973 | /*front, rear, clfe, rear_surr */ |
2974 | 0x6, 0x8, 0xa, 0xc, | |
2975 | }; | |
2976 | ||
ceaa86ba TI |
2977 | static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = { |
2978 | /* set audio protect on */ | |
2979 | { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, | |
2980 | /* enable digital output on pin widget */ | |
2981 | { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, | |
2982 | {} /* terminator */ | |
2983 | }; | |
2984 | ||
2985 | static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = { | |
84eb01be TI |
2986 | /* set audio protect on */ |
2987 | { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, | |
2988 | /* enable digital output on pin widget */ | |
2989 | { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, | |
2990 | { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, | |
2991 | { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, | |
2992 | { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, | |
2993 | { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, | |
2994 | {} /* terminator */ | |
2995 | }; | |
2996 | ||
2997 | #ifdef LIMITED_RATE_FMT_SUPPORT | |
2998 | /* support only the safe format and rate */ | |
2999 | #define SUPPORTED_RATES SNDRV_PCM_RATE_48000 | |
3000 | #define SUPPORTED_MAXBPS 16 | |
3001 | #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE | |
3002 | #else | |
3003 | /* support all rates and formats */ | |
3004 | #define SUPPORTED_RATES \ | |
3005 | (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ | |
3006 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\ | |
3007 | SNDRV_PCM_RATE_192000) | |
3008 | #define SUPPORTED_MAXBPS 24 | |
3009 | #define SUPPORTED_FORMATS \ | |
3010 | (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) | |
3011 | #endif | |
3012 | ||
ceaa86ba TI |
3013 | static int nvhdmi_7x_init_2ch(struct hda_codec *codec) |
3014 | { | |
3015 | snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch); | |
3016 | return 0; | |
3017 | } | |
3018 | ||
3019 | static int nvhdmi_7x_init_8ch(struct hda_codec *codec) | |
84eb01be | 3020 | { |
ceaa86ba | 3021 | snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch); |
84eb01be TI |
3022 | return 0; |
3023 | } | |
3024 | ||
50c697ad | 3025 | static const unsigned int channels_2_6_8[] = { |
393004b2 ND |
3026 | 2, 6, 8 |
3027 | }; | |
3028 | ||
50c697ad | 3029 | static const unsigned int channels_2_8[] = { |
393004b2 ND |
3030 | 2, 8 |
3031 | }; | |
3032 | ||
50c697ad | 3033 | static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = { |
393004b2 ND |
3034 | .count = ARRAY_SIZE(channels_2_6_8), |
3035 | .list = channels_2_6_8, | |
3036 | .mask = 0, | |
3037 | }; | |
3038 | ||
50c697ad | 3039 | static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = { |
393004b2 ND |
3040 | .count = ARRAY_SIZE(channels_2_8), |
3041 | .list = channels_2_8, | |
3042 | .mask = 0, | |
3043 | }; | |
3044 | ||
84eb01be TI |
3045 | static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo, |
3046 | struct hda_codec *codec, | |
3047 | struct snd_pcm_substream *substream) | |
3048 | { | |
3049 | struct hdmi_spec *spec = codec->spec; | |
50c697ad | 3050 | const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL; |
393004b2 | 3051 | |
b9a94a9c | 3052 | switch (codec->preset->vendor_id) { |
393004b2 ND |
3053 | case 0x10de0002: |
3054 | case 0x10de0003: | |
3055 | case 0x10de0005: | |
3056 | case 0x10de0006: | |
3057 | hw_constraints_channels = &hw_constraints_2_8_channels; | |
3058 | break; | |
3059 | case 0x10de0007: | |
3060 | hw_constraints_channels = &hw_constraints_2_6_8_channels; | |
3061 | break; | |
3062 | default: | |
3063 | break; | |
3064 | } | |
3065 | ||
3066 | if (hw_constraints_channels != NULL) { | |
3067 | snd_pcm_hw_constraint_list(substream->runtime, 0, | |
3068 | SNDRV_PCM_HW_PARAM_CHANNELS, | |
3069 | hw_constraints_channels); | |
ad09fc9d TI |
3070 | } else { |
3071 | snd_pcm_hw_constraint_step(substream->runtime, 0, | |
3072 | SNDRV_PCM_HW_PARAM_CHANNELS, 2); | |
393004b2 ND |
3073 | } |
3074 | ||
84eb01be TI |
3075 | return snd_hda_multi_out_dig_open(codec, &spec->multiout); |
3076 | } | |
3077 | ||
3078 | static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo, | |
3079 | struct hda_codec *codec, | |
3080 | struct snd_pcm_substream *substream) | |
3081 | { | |
3082 | struct hdmi_spec *spec = codec->spec; | |
3083 | return snd_hda_multi_out_dig_close(codec, &spec->multiout); | |
3084 | } | |
3085 | ||
3086 | static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo, | |
3087 | struct hda_codec *codec, | |
3088 | unsigned int stream_tag, | |
3089 | unsigned int format, | |
3090 | struct snd_pcm_substream *substream) | |
3091 | { | |
3092 | struct hdmi_spec *spec = codec->spec; | |
3093 | return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, | |
3094 | stream_tag, format, substream); | |
3095 | } | |
3096 | ||
d0b1252d TI |
3097 | static const struct hda_pcm_stream simple_pcm_playback = { |
3098 | .substreams = 1, | |
3099 | .channels_min = 2, | |
3100 | .channels_max = 2, | |
3101 | .ops = { | |
3102 | .open = simple_playback_pcm_open, | |
3103 | .close = simple_playback_pcm_close, | |
3104 | .prepare = simple_playback_pcm_prepare | |
3105 | }, | |
3106 | }; | |
3107 | ||
3108 | static const struct hda_codec_ops simple_hdmi_patch_ops = { | |
3109 | .build_controls = simple_playback_build_controls, | |
3110 | .build_pcms = simple_playback_build_pcms, | |
3111 | .init = simple_playback_init, | |
3112 | .free = simple_playback_free, | |
250e41ac | 3113 | .unsol_event = simple_hdmi_unsol_event, |
d0b1252d TI |
3114 | }; |
3115 | ||
3116 | static int patch_simple_hdmi(struct hda_codec *codec, | |
3117 | hda_nid_t cvt_nid, hda_nid_t pin_nid) | |
3118 | { | |
3119 | struct hdmi_spec *spec; | |
bce0d2a8 TI |
3120 | struct hdmi_spec_per_cvt *per_cvt; |
3121 | struct hdmi_spec_per_pin *per_pin; | |
d0b1252d TI |
3122 | |
3123 | spec = kzalloc(sizeof(*spec), GFP_KERNEL); | |
3124 | if (!spec) | |
3125 | return -ENOMEM; | |
3126 | ||
ade49db3 | 3127 | spec->codec = codec; |
d0b1252d | 3128 | codec->spec = spec; |
bce0d2a8 | 3129 | hdmi_array_init(spec, 1); |
d0b1252d TI |
3130 | |
3131 | spec->multiout.num_dacs = 0; /* no analog */ | |
3132 | spec->multiout.max_channels = 2; | |
3133 | spec->multiout.dig_out_nid = cvt_nid; | |
3134 | spec->num_cvts = 1; | |
3135 | spec->num_pins = 1; | |
bce0d2a8 TI |
3136 | per_pin = snd_array_new(&spec->pins); |
3137 | per_cvt = snd_array_new(&spec->cvts); | |
3138 | if (!per_pin || !per_cvt) { | |
3139 | simple_playback_free(codec); | |
3140 | return -ENOMEM; | |
3141 | } | |
3142 | per_cvt->cvt_nid = cvt_nid; | |
3143 | per_pin->pin_nid = pin_nid; | |
d0b1252d TI |
3144 | spec->pcm_playback = simple_pcm_playback; |
3145 | ||
3146 | codec->patch_ops = simple_hdmi_patch_ops; | |
3147 | ||
3148 | return 0; | |
3149 | } | |
3150 | ||
1f348522 AP |
3151 | static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec, |
3152 | int channels) | |
3153 | { | |
3154 | unsigned int chanmask; | |
3155 | int chan = channels ? (channels - 1) : 1; | |
3156 | ||
3157 | switch (channels) { | |
3158 | default: | |
3159 | case 0: | |
3160 | case 2: | |
3161 | chanmask = 0x00; | |
3162 | break; | |
3163 | case 4: | |
3164 | chanmask = 0x08; | |
3165 | break; | |
3166 | case 6: | |
3167 | chanmask = 0x0b; | |
3168 | break; | |
3169 | case 8: | |
3170 | chanmask = 0x13; | |
3171 | break; | |
3172 | } | |
3173 | ||
3174 | /* Set the audio infoframe channel allocation and checksum fields. The | |
3175 | * channel count is computed implicitly by the hardware. */ | |
3176 | snd_hda_codec_write(codec, 0x1, 0, | |
3177 | Nv_VERB_SET_Channel_Allocation, chanmask); | |
3178 | ||
3179 | snd_hda_codec_write(codec, 0x1, 0, | |
3180 | Nv_VERB_SET_Info_Frame_Checksum, | |
3181 | (0x71 - chan - chanmask)); | |
3182 | } | |
3183 | ||
84eb01be TI |
3184 | static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo, |
3185 | struct hda_codec *codec, | |
3186 | struct snd_pcm_substream *substream) | |
3187 | { | |
3188 | struct hdmi_spec *spec = codec->spec; | |
3189 | int i; | |
3190 | ||
3191 | snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, | |
3192 | 0, AC_VERB_SET_CHANNEL_STREAMID, 0); | |
3193 | for (i = 0; i < 4; i++) { | |
3194 | /* set the stream id */ | |
3195 | snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, | |
3196 | AC_VERB_SET_CHANNEL_STREAMID, 0); | |
3197 | /* set the stream format */ | |
3198 | snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, | |
3199 | AC_VERB_SET_STREAM_FORMAT, 0); | |
3200 | } | |
3201 | ||
1f348522 AP |
3202 | /* The audio hardware sends a channel count of 0x7 (8ch) when all the |
3203 | * streams are disabled. */ | |
3204 | nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); | |
3205 | ||
84eb01be TI |
3206 | return snd_hda_multi_out_dig_close(codec, &spec->multiout); |
3207 | } | |
3208 | ||
3209 | static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo, | |
3210 | struct hda_codec *codec, | |
3211 | unsigned int stream_tag, | |
3212 | unsigned int format, | |
3213 | struct snd_pcm_substream *substream) | |
3214 | { | |
3215 | int chs; | |
112daa7a | 3216 | unsigned int dataDCC2, channel_id; |
84eb01be | 3217 | int i; |
7c935976 | 3218 | struct hdmi_spec *spec = codec->spec; |
e3245cdd | 3219 | struct hda_spdif_out *spdif; |
bce0d2a8 | 3220 | struct hdmi_spec_per_cvt *per_cvt; |
84eb01be TI |
3221 | |
3222 | mutex_lock(&codec->spdif_mutex); | |
bce0d2a8 TI |
3223 | per_cvt = get_cvt(spec, 0); |
3224 | spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid); | |
84eb01be TI |
3225 | |
3226 | chs = substream->runtime->channels; | |
84eb01be | 3227 | |
84eb01be TI |
3228 | dataDCC2 = 0x2; |
3229 | ||
84eb01be | 3230 | /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */ |
7c935976 | 3231 | if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) |
84eb01be TI |
3232 | snd_hda_codec_write(codec, |
3233 | nvhdmi_master_con_nid_7x, | |
3234 | 0, | |
3235 | AC_VERB_SET_DIGI_CONVERT_1, | |
7c935976 | 3236 | spdif->ctls & ~AC_DIG1_ENABLE & 0xff); |
84eb01be TI |
3237 | |
3238 | /* set the stream id */ | |
3239 | snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, | |
3240 | AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0); | |
3241 | ||
3242 | /* set the stream format */ | |
3243 | snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, | |
3244 | AC_VERB_SET_STREAM_FORMAT, format); | |
3245 | ||
3246 | /* turn on again (if needed) */ | |
3247 | /* enable and set the channel status audio/data flag */ | |
7c935976 | 3248 | if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) { |
84eb01be TI |
3249 | snd_hda_codec_write(codec, |
3250 | nvhdmi_master_con_nid_7x, | |
3251 | 0, | |
3252 | AC_VERB_SET_DIGI_CONVERT_1, | |
7c935976 | 3253 | spdif->ctls & 0xff); |
84eb01be TI |
3254 | snd_hda_codec_write(codec, |
3255 | nvhdmi_master_con_nid_7x, | |
3256 | 0, | |
3257 | AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); | |
3258 | } | |
3259 | ||
3260 | for (i = 0; i < 4; i++) { | |
3261 | if (chs == 2) | |
3262 | channel_id = 0; | |
3263 | else | |
3264 | channel_id = i * 2; | |
3265 | ||
3266 | /* turn off SPDIF once; | |
3267 | *otherwise the IEC958 bits won't be updated | |
3268 | */ | |
3269 | if (codec->spdif_status_reset && | |
7c935976 | 3270 | (spdif->ctls & AC_DIG1_ENABLE)) |
84eb01be TI |
3271 | snd_hda_codec_write(codec, |
3272 | nvhdmi_con_nids_7x[i], | |
3273 | 0, | |
3274 | AC_VERB_SET_DIGI_CONVERT_1, | |
7c935976 | 3275 | spdif->ctls & ~AC_DIG1_ENABLE & 0xff); |
84eb01be TI |
3276 | /* set the stream id */ |
3277 | snd_hda_codec_write(codec, | |
3278 | nvhdmi_con_nids_7x[i], | |
3279 | 0, | |
3280 | AC_VERB_SET_CHANNEL_STREAMID, | |
3281 | (stream_tag << 4) | channel_id); | |
3282 | /* set the stream format */ | |
3283 | snd_hda_codec_write(codec, | |
3284 | nvhdmi_con_nids_7x[i], | |
3285 | 0, | |
3286 | AC_VERB_SET_STREAM_FORMAT, | |
3287 | format); | |
3288 | /* turn on again (if needed) */ | |
3289 | /* enable and set the channel status audio/data flag */ | |
3290 | if (codec->spdif_status_reset && | |
7c935976 | 3291 | (spdif->ctls & AC_DIG1_ENABLE)) { |
84eb01be TI |
3292 | snd_hda_codec_write(codec, |
3293 | nvhdmi_con_nids_7x[i], | |
3294 | 0, | |
3295 | AC_VERB_SET_DIGI_CONVERT_1, | |
7c935976 | 3296 | spdif->ctls & 0xff); |
84eb01be TI |
3297 | snd_hda_codec_write(codec, |
3298 | nvhdmi_con_nids_7x[i], | |
3299 | 0, | |
3300 | AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); | |
3301 | } | |
3302 | } | |
3303 | ||
1f348522 | 3304 | nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs); |
84eb01be TI |
3305 | |
3306 | mutex_unlock(&codec->spdif_mutex); | |
3307 | return 0; | |
3308 | } | |
3309 | ||
fb79e1e0 | 3310 | static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = { |
84eb01be TI |
3311 | .substreams = 1, |
3312 | .channels_min = 2, | |
3313 | .channels_max = 8, | |
3314 | .nid = nvhdmi_master_con_nid_7x, | |
3315 | .rates = SUPPORTED_RATES, | |
3316 | .maxbps = SUPPORTED_MAXBPS, | |
3317 | .formats = SUPPORTED_FORMATS, | |
3318 | .ops = { | |
3319 | .open = simple_playback_pcm_open, | |
3320 | .close = nvhdmi_8ch_7x_pcm_close, | |
3321 | .prepare = nvhdmi_8ch_7x_pcm_prepare | |
3322 | }, | |
3323 | }; | |
3324 | ||
84eb01be TI |
3325 | static int patch_nvhdmi_2ch(struct hda_codec *codec) |
3326 | { | |
3327 | struct hdmi_spec *spec; | |
d0b1252d TI |
3328 | int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x, |
3329 | nvhdmi_master_pin_nid_7x); | |
3330 | if (err < 0) | |
3331 | return err; | |
84eb01be | 3332 | |
ceaa86ba | 3333 | codec->patch_ops.init = nvhdmi_7x_init_2ch; |
d0b1252d TI |
3334 | /* override the PCM rates, etc, as the codec doesn't give full list */ |
3335 | spec = codec->spec; | |
3336 | spec->pcm_playback.rates = SUPPORTED_RATES; | |
3337 | spec->pcm_playback.maxbps = SUPPORTED_MAXBPS; | |
3338 | spec->pcm_playback.formats = SUPPORTED_FORMATS; | |
84eb01be TI |
3339 | return 0; |
3340 | } | |
3341 | ||
53775b0d TI |
3342 | static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec) |
3343 | { | |
3344 | struct hdmi_spec *spec = codec->spec; | |
3345 | int err = simple_playback_build_pcms(codec); | |
bce0d2a8 TI |
3346 | if (!err) { |
3347 | struct hda_pcm *info = get_pcm_rec(spec, 0); | |
3348 | info->own_chmap = true; | |
3349 | } | |
53775b0d TI |
3350 | return err; |
3351 | } | |
3352 | ||
3353 | static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec) | |
3354 | { | |
3355 | struct hdmi_spec *spec = codec->spec; | |
bce0d2a8 | 3356 | struct hda_pcm *info; |
53775b0d TI |
3357 | struct snd_pcm_chmap *chmap; |
3358 | int err; | |
3359 | ||
3360 | err = simple_playback_build_controls(codec); | |
3361 | if (err < 0) | |
3362 | return err; | |
3363 | ||
3364 | /* add channel maps */ | |
bce0d2a8 TI |
3365 | info = get_pcm_rec(spec, 0); |
3366 | err = snd_pcm_add_chmap_ctls(info->pcm, | |
53775b0d TI |
3367 | SNDRV_PCM_STREAM_PLAYBACK, |
3368 | snd_pcm_alt_chmaps, 8, 0, &chmap); | |
3369 | if (err < 0) | |
3370 | return err; | |
b9a94a9c | 3371 | switch (codec->preset->vendor_id) { |
53775b0d TI |
3372 | case 0x10de0002: |
3373 | case 0x10de0003: | |
3374 | case 0x10de0005: | |
3375 | case 0x10de0006: | |
3376 | chmap->channel_mask = (1U << 2) | (1U << 8); | |
3377 | break; | |
3378 | case 0x10de0007: | |
3379 | chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8); | |
3380 | } | |
3381 | return 0; | |
3382 | } | |
3383 | ||
84eb01be TI |
3384 | static int patch_nvhdmi_8ch_7x(struct hda_codec *codec) |
3385 | { | |
3386 | struct hdmi_spec *spec; | |
3387 | int err = patch_nvhdmi_2ch(codec); | |
84eb01be TI |
3388 | if (err < 0) |
3389 | return err; | |
3390 | spec = codec->spec; | |
3391 | spec->multiout.max_channels = 8; | |
d0b1252d | 3392 | spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x; |
ceaa86ba | 3393 | codec->patch_ops.init = nvhdmi_7x_init_8ch; |
53775b0d TI |
3394 | codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms; |
3395 | codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls; | |
1f348522 AP |
3396 | |
3397 | /* Initialize the audio infoframe channel mask and checksum to something | |
3398 | * valid */ | |
3399 | nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); | |
3400 | ||
84eb01be TI |
3401 | return 0; |
3402 | } | |
3403 | ||
611885bc AH |
3404 | /* |
3405 | * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on: | |
3406 | * - 0x10de0015 | |
3407 | * - 0x10de0040 | |
3408 | */ | |
67b90cb8 | 3409 | static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap, |
f302240d | 3410 | struct hdac_cea_channel_speaker_allocation *cap, int channels) |
611885bc AH |
3411 | { |
3412 | if (cap->ca_index == 0x00 && channels == 2) | |
3413 | return SNDRV_CTL_TLVT_CHMAP_FIXED; | |
3414 | ||
028cb68e SP |
3415 | /* If the speaker allocation matches the channel count, it is OK. */ |
3416 | if (cap->channels != channels) | |
3417 | return -1; | |
3418 | ||
3419 | /* all channels are remappable freely */ | |
3420 | return SNDRV_CTL_TLVT_CHMAP_VAR; | |
611885bc AH |
3421 | } |
3422 | ||
828cb4ed SP |
3423 | static int nvhdmi_chmap_validate(struct hdac_chmap *chmap, |
3424 | int ca, int chs, unsigned char *map) | |
611885bc AH |
3425 | { |
3426 | if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR)) | |
3427 | return -EINVAL; | |
3428 | ||
3429 | return 0; | |
3430 | } | |
3431 | ||
ade49db3 TI |
3432 | /* map from pin NID to port; port is 0-based */ |
3433 | /* for Nvidia: assume widget NID starting from 4, with step 1 (4, 5, 6, ...) */ | |
3434 | static int nvhdmi_pin2port(void *audio_ptr, int pin_nid) | |
3435 | { | |
3436 | return pin_nid - 4; | |
3437 | } | |
3438 | ||
3439 | /* reverse-map from port to pin NID: see above */ | |
3440 | static int nvhdmi_port2pin(struct hda_codec *codec, int port) | |
3441 | { | |
3442 | return port + 4; | |
3443 | } | |
3444 | ||
3445 | static const struct drm_audio_component_audio_ops nvhdmi_audio_ops = { | |
3446 | .pin2port = nvhdmi_pin2port, | |
3447 | .pin_eld_notify = generic_acomp_pin_eld_notify, | |
3448 | .master_bind = generic_acomp_master_bind, | |
3449 | .master_unbind = generic_acomp_master_unbind, | |
3450 | }; | |
3451 | ||
611885bc AH |
3452 | static int patch_nvhdmi(struct hda_codec *codec) |
3453 | { | |
3454 | struct hdmi_spec *spec; | |
3455 | int err; | |
3456 | ||
3457 | err = patch_generic_hdmi(codec); | |
3458 | if (err) | |
3459 | return err; | |
3460 | ||
3461 | spec = codec->spec; | |
75fae117 | 3462 | spec->dyn_pin_out = true; |
611885bc | 3463 | |
67b90cb8 | 3464 | spec->chmap.ops.chmap_cea_alloc_validate_get_type = |
611885bc | 3465 | nvhdmi_chmap_cea_alloc_validate_get_type; |
67b90cb8 | 3466 | spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; |
611885bc | 3467 | |
ade49db3 TI |
3468 | generic_acomp_init(codec, &nvhdmi_audio_ops, nvhdmi_port2pin); |
3469 | ||
611885bc AH |
3470 | return 0; |
3471 | } | |
3472 | ||
26e9a960 TR |
3473 | /* |
3474 | * The HDA codec on NVIDIA Tegra contains two scratch registers that are | |
3475 | * accessed using vendor-defined verbs. These registers can be used for | |
3476 | * interoperability between the HDA and HDMI drivers. | |
3477 | */ | |
3478 | ||
3479 | /* Audio Function Group node */ | |
3480 | #define NVIDIA_AFG_NID 0x01 | |
3481 | ||
3482 | /* | |
3483 | * The SCRATCH0 register is used to notify the HDMI codec of changes in audio | |
3484 | * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to | |
3485 | * be raised in the HDMI codec. The remainder of the bits is arbitrary. This | |
3486 | * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an | |
3487 | * additional bit (at position 30) to signal the validity of the format. | |
3488 | * | |
3489 | * | 31 | 30 | 29 16 | 15 0 | | |
3490 | * +---------+-------+--------+--------+ | |
3491 | * | TRIGGER | VALID | UNUSED | FORMAT | | |
3492 | * +-----------------------------------| | |
3493 | * | |
3494 | * Note that for the trigger bit to take effect it needs to change value | |
3495 | * (i.e. it needs to be toggled). | |
3496 | */ | |
3497 | #define NVIDIA_GET_SCRATCH0 0xfa6 | |
3498 | #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7 | |
3499 | #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8 | |
3500 | #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9 | |
3501 | #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa | |
3502 | #define NVIDIA_SCRATCH_TRIGGER (1 << 7) | |
3503 | #define NVIDIA_SCRATCH_VALID (1 << 6) | |
3504 | ||
3505 | #define NVIDIA_GET_SCRATCH1 0xfab | |
3506 | #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac | |
3507 | #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad | |
3508 | #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae | |
3509 | #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf | |
3510 | ||
3511 | /* | |
3512 | * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0, | |
3513 | * the format is invalidated so that the HDMI codec can be disabled. | |
3514 | */ | |
3515 | static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format) | |
3516 | { | |
3517 | unsigned int value; | |
3518 | ||
3519 | /* bits [31:30] contain the trigger and valid bits */ | |
3520 | value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0, | |
3521 | NVIDIA_GET_SCRATCH0, 0); | |
3522 | value = (value >> 24) & 0xff; | |
3523 | ||
3524 | /* bits [15:0] are used to store the HDA format */ | |
3525 | snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, | |
3526 | NVIDIA_SET_SCRATCH0_BYTE0, | |
3527 | (format >> 0) & 0xff); | |
3528 | snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, | |
3529 | NVIDIA_SET_SCRATCH0_BYTE1, | |
3530 | (format >> 8) & 0xff); | |
3531 | ||
3532 | /* bits [16:24] are unused */ | |
3533 | snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, | |
3534 | NVIDIA_SET_SCRATCH0_BYTE2, 0); | |
3535 | ||
3536 | /* | |
3537 | * Bit 30 signals that the data is valid and hence that HDMI audio can | |
3538 | * be enabled. | |
3539 | */ | |
3540 | if (format == 0) | |
3541 | value &= ~NVIDIA_SCRATCH_VALID; | |
3542 | else | |
3543 | value |= NVIDIA_SCRATCH_VALID; | |
3544 | ||
3545 | /* | |
3546 | * Whenever the trigger bit is toggled, an interrupt is raised in the | |
3547 | * HDMI codec. The HDMI driver will use that as trigger to update its | |
3548 | * configuration. | |
3549 | */ | |
3550 | value ^= NVIDIA_SCRATCH_TRIGGER; | |
3551 | ||
3552 | snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, | |
3553 | NVIDIA_SET_SCRATCH0_BYTE3, value); | |
3554 | } | |
3555 | ||
3556 | static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo, | |
3557 | struct hda_codec *codec, | |
3558 | unsigned int stream_tag, | |
3559 | unsigned int format, | |
3560 | struct snd_pcm_substream *substream) | |
3561 | { | |
3562 | int err; | |
3563 | ||
3564 | err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag, | |
3565 | format, substream); | |
3566 | if (err < 0) | |
3567 | return err; | |
3568 | ||
3569 | /* notify the HDMI codec of the format change */ | |
3570 | tegra_hdmi_set_format(codec, format); | |
3571 | ||
3572 | return 0; | |
3573 | } | |
3574 | ||
3575 | static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo, | |
3576 | struct hda_codec *codec, | |
3577 | struct snd_pcm_substream *substream) | |
3578 | { | |
3579 | /* invalidate the format in the HDMI codec */ | |
3580 | tegra_hdmi_set_format(codec, 0); | |
3581 | ||
3582 | return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream); | |
3583 | } | |
3584 | ||
3585 | static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type) | |
3586 | { | |
3587 | struct hdmi_spec *spec = codec->spec; | |
3588 | unsigned int i; | |
3589 | ||
3590 | for (i = 0; i < spec->num_pins; i++) { | |
3591 | struct hda_pcm *pcm = get_pcm_rec(spec, i); | |
3592 | ||
3593 | if (pcm->pcm_type == type) | |
3594 | return pcm; | |
3595 | } | |
3596 | ||
3597 | return NULL; | |
3598 | } | |
3599 | ||
3600 | static int tegra_hdmi_build_pcms(struct hda_codec *codec) | |
3601 | { | |
3602 | struct hda_pcm_stream *stream; | |
3603 | struct hda_pcm *pcm; | |
3604 | int err; | |
3605 | ||
3606 | err = generic_hdmi_build_pcms(codec); | |
3607 | if (err < 0) | |
3608 | return err; | |
3609 | ||
3610 | pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI); | |
3611 | if (!pcm) | |
3612 | return -ENODEV; | |
3613 | ||
3614 | /* | |
3615 | * Override ->prepare() and ->cleanup() operations to notify the HDMI | |
3616 | * codec about format changes. | |
3617 | */ | |
3618 | stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; | |
3619 | stream->ops.prepare = tegra_hdmi_pcm_prepare; | |
3620 | stream->ops.cleanup = tegra_hdmi_pcm_cleanup; | |
3621 | ||
3622 | return 0; | |
3623 | } | |
3624 | ||
3625 | static int patch_tegra_hdmi(struct hda_codec *codec) | |
3626 | { | |
3627 | int err; | |
3628 | ||
3629 | err = patch_generic_hdmi(codec); | |
3630 | if (err) | |
3631 | return err; | |
3632 | ||
3633 | codec->patch_ops.build_pcms = tegra_hdmi_build_pcms; | |
3634 | ||
3635 | return 0; | |
3636 | } | |
3637 | ||
84eb01be | 3638 | /* |
5a613584 | 3639 | * ATI/AMD-specific implementations |
84eb01be TI |
3640 | */ |
3641 | ||
5a613584 | 3642 | #define is_amdhdmi_rev3_or_later(codec) \ |
7639a06c TI |
3643 | ((codec)->core.vendor_id == 0x1002aa01 && \ |
3644 | ((codec)->core.revision_id & 0xff00) >= 0x0300) | |
5a613584 AH |
3645 | #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec) |
3646 | ||
3647 | /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */ | |
3648 | #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771 | |
3649 | #define ATI_VERB_SET_DOWNMIX_INFO 0x772 | |
3650 | #define ATI_VERB_SET_MULTICHANNEL_01 0x777 | |
3651 | #define ATI_VERB_SET_MULTICHANNEL_23 0x778 | |
3652 | #define ATI_VERB_SET_MULTICHANNEL_45 0x779 | |
3653 | #define ATI_VERB_SET_MULTICHANNEL_67 0x77a | |
461cf6b3 | 3654 | #define ATI_VERB_SET_HBR_CONTROL 0x77c |
5a613584 AH |
3655 | #define ATI_VERB_SET_MULTICHANNEL_1 0x785 |
3656 | #define ATI_VERB_SET_MULTICHANNEL_3 0x786 | |
3657 | #define ATI_VERB_SET_MULTICHANNEL_5 0x787 | |
3658 | #define ATI_VERB_SET_MULTICHANNEL_7 0x788 | |
3659 | #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789 | |
3660 | #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71 | |
3661 | #define ATI_VERB_GET_DOWNMIX_INFO 0xf72 | |
3662 | #define ATI_VERB_GET_MULTICHANNEL_01 0xf77 | |
3663 | #define ATI_VERB_GET_MULTICHANNEL_23 0xf78 | |
3664 | #define ATI_VERB_GET_MULTICHANNEL_45 0xf79 | |
3665 | #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a | |
461cf6b3 | 3666 | #define ATI_VERB_GET_HBR_CONTROL 0xf7c |
5a613584 AH |
3667 | #define ATI_VERB_GET_MULTICHANNEL_1 0xf85 |
3668 | #define ATI_VERB_GET_MULTICHANNEL_3 0xf86 | |
3669 | #define ATI_VERB_GET_MULTICHANNEL_5 0xf87 | |
3670 | #define ATI_VERB_GET_MULTICHANNEL_7 0xf88 | |
3671 | #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89 | |
3672 | ||
84d69e79 AH |
3673 | /* AMD specific HDA cvt verbs */ |
3674 | #define ATI_VERB_SET_RAMP_RATE 0x770 | |
3675 | #define ATI_VERB_GET_RAMP_RATE 0xf70 | |
3676 | ||
5a613584 AH |
3677 | #define ATI_OUT_ENABLE 0x1 |
3678 | ||
3679 | #define ATI_MULTICHANNEL_MODE_PAIRED 0 | |
3680 | #define ATI_MULTICHANNEL_MODE_SINGLE 1 | |
3681 | ||
461cf6b3 AH |
3682 | #define ATI_HBR_CAPABLE 0x01 |
3683 | #define ATI_HBR_ENABLE 0x10 | |
3684 | ||
89250f84 AH |
3685 | static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, |
3686 | unsigned char *buf, int *eld_size) | |
3687 | { | |
3688 | /* call hda_eld.c ATI/AMD-specific function */ | |
3689 | return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size, | |
3690 | is_amdhdmi_rev3_or_later(codec)); | |
3691 | } | |
3692 | ||
5a613584 AH |
3693 | static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca, |
3694 | int active_channels, int conn_type) | |
3695 | { | |
3696 | snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca); | |
3697 | } | |
3698 | ||
3699 | static int atihdmi_paired_swap_fc_lfe(int pos) | |
3700 | { | |
3701 | /* | |
3702 | * ATI/AMD have automatic FC/LFE swap built-in | |
3703 | * when in pairwise mapping mode. | |
3704 | */ | |
3705 | ||
3706 | switch (pos) { | |
3707 | /* see channel_allocations[].speakers[] */ | |
3708 | case 2: return 3; | |
3709 | case 3: return 2; | |
3710 | default: break; | |
3711 | } | |
3712 | ||
3713 | return pos; | |
3714 | } | |
3715 | ||
828cb4ed SP |
3716 | static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap, |
3717 | int ca, int chs, unsigned char *map) | |
5a613584 | 3718 | { |
f302240d | 3719 | struct hdac_cea_channel_speaker_allocation *cap; |
5a613584 AH |
3720 | int i, j; |
3721 | ||
3722 | /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */ | |
3723 | ||
bb63f726 | 3724 | cap = snd_hdac_get_ch_alloc_from_ca(ca); |
5a613584 | 3725 | for (i = 0; i < chs; ++i) { |
bb63f726 | 3726 | int mask = snd_hdac_chmap_to_spk_mask(map[i]); |
5a613584 AH |
3727 | bool ok = false; |
3728 | bool companion_ok = false; | |
3729 | ||
3730 | if (!mask) | |
3731 | continue; | |
3732 | ||
3733 | for (j = 0 + i % 2; j < 8; j += 2) { | |
3734 | int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j); | |
3735 | if (cap->speakers[chan_idx] == mask) { | |
3736 | /* channel is in a supported position */ | |
3737 | ok = true; | |
3738 | ||
3739 | if (i % 2 == 0 && i + 1 < chs) { | |
3740 | /* even channel, check the odd companion */ | |
3741 | int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1); | |
bb63f726 | 3742 | int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]); |
5a613584 AH |
3743 | int comp_mask_act = cap->speakers[comp_chan_idx]; |
3744 | ||
3745 | if (comp_mask_req == comp_mask_act) | |
3746 | companion_ok = true; | |
3747 | else | |
3748 | return -EINVAL; | |
3749 | } | |
3750 | break; | |
3751 | } | |
3752 | } | |
3753 | ||
3754 | if (!ok) | |
3755 | return -EINVAL; | |
3756 | ||
3757 | if (companion_ok) | |
3758 | i++; /* companion channel already checked */ | |
3759 | } | |
3760 | ||
3761 | return 0; | |
3762 | } | |
3763 | ||
739ffee9 SP |
3764 | static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac, |
3765 | hda_nid_t pin_nid, int hdmi_slot, int stream_channel) | |
5a613584 | 3766 | { |
739ffee9 | 3767 | struct hda_codec *codec = container_of(hdac, struct hda_codec, core); |
5a613584 AH |
3768 | int verb; |
3769 | int ati_channel_setup = 0; | |
3770 | ||
3771 | if (hdmi_slot > 7) | |
3772 | return -EINVAL; | |
3773 | ||
3774 | if (!has_amd_full_remap_support(codec)) { | |
3775 | hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot); | |
3776 | ||
3777 | /* In case this is an odd slot but without stream channel, do not | |
3778 | * disable the slot since the corresponding even slot could have a | |
3779 | * channel. In case neither have a channel, the slot pair will be | |
3780 | * disabled when this function is called for the even slot. */ | |
3781 | if (hdmi_slot % 2 != 0 && stream_channel == 0xf) | |
3782 | return 0; | |
3783 | ||
3784 | hdmi_slot -= hdmi_slot % 2; | |
3785 | ||
3786 | if (stream_channel != 0xf) | |
3787 | stream_channel -= stream_channel % 2; | |
3788 | } | |
3789 | ||
3790 | verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e; | |
3791 | ||
3792 | /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */ | |
3793 | ||
3794 | if (stream_channel != 0xf) | |
3795 | ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE; | |
3796 | ||
3797 | return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup); | |
3798 | } | |
3799 | ||
739ffee9 SP |
3800 | static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac, |
3801 | hda_nid_t pin_nid, int asp_slot) | |
5a613584 | 3802 | { |
739ffee9 | 3803 | struct hda_codec *codec = container_of(hdac, struct hda_codec, core); |
5a613584 AH |
3804 | bool was_odd = false; |
3805 | int ati_asp_slot = asp_slot; | |
3806 | int verb; | |
3807 | int ati_channel_setup; | |
3808 | ||
3809 | if (asp_slot > 7) | |
3810 | return -EINVAL; | |
3811 | ||
3812 | if (!has_amd_full_remap_support(codec)) { | |
3813 | ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot); | |
3814 | if (ati_asp_slot % 2 != 0) { | |
3815 | ati_asp_slot -= 1; | |
3816 | was_odd = true; | |
3817 | } | |
3818 | } | |
3819 | ||
3820 | verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e; | |
3821 | ||
3822 | ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0); | |
3823 | ||
3824 | if (!(ati_channel_setup & ATI_OUT_ENABLE)) | |
3825 | return 0xf; | |
3826 | ||
3827 | return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd; | |
3828 | } | |
84eb01be | 3829 | |
67b90cb8 SP |
3830 | static int atihdmi_paired_chmap_cea_alloc_validate_get_type( |
3831 | struct hdac_chmap *chmap, | |
f302240d | 3832 | struct hdac_cea_channel_speaker_allocation *cap, |
67b90cb8 | 3833 | int channels) |
5a613584 AH |
3834 | { |
3835 | int c; | |
3836 | ||
3837 | /* | |
3838 | * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so | |
3839 | * we need to take that into account (a single channel may take 2 | |
3840 | * channel slots if we need to carry a silent channel next to it). | |
3841 | * On Rev3+ AMD codecs this function is not used. | |
3842 | */ | |
3843 | int chanpairs = 0; | |
3844 | ||
3845 | /* We only produce even-numbered channel count TLVs */ | |
3846 | if ((channels % 2) != 0) | |
3847 | return -1; | |
3848 | ||
3849 | for (c = 0; c < 7; c += 2) { | |
3850 | if (cap->speakers[c] || cap->speakers[c+1]) | |
3851 | chanpairs++; | |
3852 | } | |
3853 | ||
3854 | if (chanpairs * 2 != channels) | |
3855 | return -1; | |
3856 | ||
3857 | return SNDRV_CTL_TLVT_CHMAP_PAIRED; | |
3858 | } | |
3859 | ||
828cb4ed | 3860 | static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap, |
f302240d SP |
3861 | struct hdac_cea_channel_speaker_allocation *cap, |
3862 | unsigned int *chmap, int channels) | |
5a613584 AH |
3863 | { |
3864 | /* produce paired maps for pre-rev3 ATI/AMD codecs */ | |
3865 | int count = 0; | |
3866 | int c; | |
3867 | ||
3868 | for (c = 7; c >= 0; c--) { | |
3869 | int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c); | |
3870 | int spk = cap->speakers[chan]; | |
3871 | if (!spk) { | |
3872 | /* add N/A channel if the companion channel is occupied */ | |
3873 | if (cap->speakers[chan + (chan % 2 ? -1 : 1)]) | |
3874 | chmap[count++] = SNDRV_CHMAP_NA; | |
3875 | ||
3876 | continue; | |
3877 | } | |
3878 | ||
bb63f726 | 3879 | chmap[count++] = snd_hdac_spk_to_chmap(spk); |
5a613584 AH |
3880 | } |
3881 | ||
3882 | WARN_ON(count != channels); | |
3883 | } | |
3884 | ||
461cf6b3 AH |
3885 | static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, |
3886 | bool hbr) | |
3887 | { | |
3888 | int hbr_ctl, hbr_ctl_new; | |
3889 | ||
3890 | hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0); | |
13122e6e | 3891 | if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) { |
461cf6b3 AH |
3892 | if (hbr) |
3893 | hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE; | |
3894 | else | |
3895 | hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE; | |
3896 | ||
4e76a883 TI |
3897 | codec_dbg(codec, |
3898 | "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n", | |
461cf6b3 AH |
3899 | pin_nid, |
3900 | hbr_ctl == hbr_ctl_new ? "" : "new-", | |
3901 | hbr_ctl_new); | |
3902 | ||
3903 | if (hbr_ctl != hbr_ctl_new) | |
3904 | snd_hda_codec_write(codec, pin_nid, 0, | |
3905 | ATI_VERB_SET_HBR_CONTROL, | |
3906 | hbr_ctl_new); | |
3907 | ||
3908 | } else if (hbr) | |
3909 | return -EINVAL; | |
3910 | ||
3911 | return 0; | |
3912 | } | |
3913 | ||
84d69e79 AH |
3914 | static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, |
3915 | hda_nid_t pin_nid, u32 stream_tag, int format) | |
3916 | { | |
3917 | ||
3918 | if (is_amdhdmi_rev3_or_later(codec)) { | |
3919 | int ramp_rate = 180; /* default as per AMD spec */ | |
3920 | /* disable ramp-up/down for non-pcm as per AMD spec */ | |
3921 | if (format & AC_FMT_TYPE_NON_PCM) | |
3922 | ramp_rate = 0; | |
3923 | ||
3924 | snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate); | |
3925 | } | |
3926 | ||
3927 | return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format); | |
3928 | } | |
3929 | ||
3930 | ||
5a613584 | 3931 | static int atihdmi_init(struct hda_codec *codec) |
84eb01be TI |
3932 | { |
3933 | struct hdmi_spec *spec = codec->spec; | |
5a613584 | 3934 | int pin_idx, err; |
84eb01be | 3935 | |
5a613584 AH |
3936 | err = generic_hdmi_init(codec); |
3937 | ||
3938 | if (err) | |
84eb01be | 3939 | return err; |
5a613584 AH |
3940 | |
3941 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { | |
3942 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); | |
3943 | ||
3944 | /* make sure downmix information in infoframe is zero */ | |
3945 | snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0); | |
3946 | ||
3947 | /* enable channel-wise remap mode if supported */ | |
3948 | if (has_amd_full_remap_support(codec)) | |
3949 | snd_hda_codec_write(codec, per_pin->pin_nid, 0, | |
3950 | ATI_VERB_SET_MULTICHANNEL_MODE, | |
3951 | ATI_MULTICHANNEL_MODE_SINGLE); | |
84eb01be | 3952 | } |
5a613584 | 3953 | |
84eb01be TI |
3954 | return 0; |
3955 | } | |
3956 | ||
ade49db3 TI |
3957 | /* map from pin NID to port; port is 0-based */ |
3958 | /* for AMD: assume widget NID starting from 3, with step 2 (3, 5, 7, ...) */ | |
3959 | static int atihdmi_pin2port(void *audio_ptr, int pin_nid) | |
3960 | { | |
3961 | return pin_nid / 2 - 1; | |
3962 | } | |
3963 | ||
3964 | /* reverse-map from port to pin NID: see above */ | |
3965 | static int atihdmi_port2pin(struct hda_codec *codec, int port) | |
3966 | { | |
3967 | return port * 2 + 3; | |
3968 | } | |
3969 | ||
3970 | static const struct drm_audio_component_audio_ops atihdmi_audio_ops = { | |
3971 | .pin2port = atihdmi_pin2port, | |
3972 | .pin_eld_notify = generic_acomp_pin_eld_notify, | |
3973 | .master_bind = generic_acomp_master_bind, | |
3974 | .master_unbind = generic_acomp_master_unbind, | |
3975 | }; | |
3976 | ||
84eb01be TI |
3977 | static int patch_atihdmi(struct hda_codec *codec) |
3978 | { | |
3979 | struct hdmi_spec *spec; | |
5a613584 AH |
3980 | struct hdmi_spec_per_cvt *per_cvt; |
3981 | int err, cvt_idx; | |
3982 | ||
3983 | err = patch_generic_hdmi(codec); | |
3984 | ||
3985 | if (err) | |
d0b1252d | 3986 | return err; |
5a613584 AH |
3987 | |
3988 | codec->patch_ops.init = atihdmi_init; | |
3989 | ||
d0b1252d | 3990 | spec = codec->spec; |
5a613584 | 3991 | |
89250f84 | 3992 | spec->ops.pin_get_eld = atihdmi_pin_get_eld; |
5a613584 | 3993 | spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe; |
461cf6b3 | 3994 | spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup; |
84d69e79 | 3995 | spec->ops.setup_stream = atihdmi_setup_stream; |
5a613584 | 3996 | |
39669225 TI |
3997 | spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel; |
3998 | spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel; | |
3999 | ||
5a613584 AH |
4000 | if (!has_amd_full_remap_support(codec)) { |
4001 | /* override to ATI/AMD-specific versions with pairwise mapping */ | |
67b90cb8 | 4002 | spec->chmap.ops.chmap_cea_alloc_validate_get_type = |
5a613584 | 4003 | atihdmi_paired_chmap_cea_alloc_validate_get_type; |
67b90cb8 SP |
4004 | spec->chmap.ops.cea_alloc_to_tlv_chmap = |
4005 | atihdmi_paired_cea_alloc_to_tlv_chmap; | |
4006 | spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate; | |
5a613584 AH |
4007 | } |
4008 | ||
4009 | /* ATI/AMD converters do not advertise all of their capabilities */ | |
4010 | for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { | |
4011 | per_cvt = get_cvt(spec, cvt_idx); | |
4012 | per_cvt->channels_max = max(per_cvt->channels_max, 8u); | |
4013 | per_cvt->rates |= SUPPORTED_RATES; | |
4014 | per_cvt->formats |= SUPPORTED_FORMATS; | |
4015 | per_cvt->maxbps = max(per_cvt->maxbps, 24u); | |
4016 | } | |
4017 | ||
67b90cb8 | 4018 | spec->chmap.channels_max = max(spec->chmap.channels_max, 8u); |
5a613584 | 4019 | |
57cb54e5 TI |
4020 | /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing |
4021 | * the link-down as is. Tell the core to allow it. | |
4022 | */ | |
4023 | codec->link_down_at_suspend = 1; | |
4024 | ||
ade49db3 TI |
4025 | generic_acomp_init(codec, &atihdmi_audio_ops, atihdmi_port2pin); |
4026 | ||
84eb01be TI |
4027 | return 0; |
4028 | } | |
4029 | ||
3de5ff88 AL |
4030 | /* VIA HDMI Implementation */ |
4031 | #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */ | |
4032 | #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */ | |
4033 | ||
3de5ff88 AL |
4034 | static int patch_via_hdmi(struct hda_codec *codec) |
4035 | { | |
250e41ac | 4036 | return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID); |
3de5ff88 | 4037 | } |
84eb01be TI |
4038 | |
4039 | /* | |
4040 | * patch entries | |
4041 | */ | |
b9a94a9c TI |
4042 | static const struct hda_device_id snd_hda_id_hdmi[] = { |
4043 | HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi), | |
4044 | HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi), | |
4045 | HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi), | |
4046 | HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi), | |
4047 | HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi), | |
4048 | HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi), | |
4049 | HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi), | |
74ec1181 | 4050 | HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch), |
b9a94a9c TI |
4051 | HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), |
4052 | HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), | |
74ec1181 | 4053 | HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x), |
b9a94a9c TI |
4054 | HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), |
4055 | HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), | |
4056 | HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x), | |
74ec1181 DD |
4057 | HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi), |
4058 | HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi), | |
b9a94a9c TI |
4059 | HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi), |
4060 | HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi), | |
4061 | HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi), | |
4062 | HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi), | |
4063 | HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi), | |
4064 | HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi), | |
4065 | HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi), | |
4066 | HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi), | |
4067 | HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi), | |
4068 | HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi), | |
4069 | HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi), | |
c8900a0f | 4070 | /* 17 is known to be absent */ |
b9a94a9c TI |
4071 | HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi), |
4072 | HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi), | |
4073 | HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi), | |
4074 | HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi), | |
4075 | HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi), | |
4076 | HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi), | |
4077 | HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi), | |
4078 | HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi), | |
4079 | HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi), | |
917bb90c TR |
4080 | HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi), |
4081 | HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi), | |
4082 | HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi), | |
4083 | HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi), | |
b9a94a9c TI |
4084 | HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi), |
4085 | HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi), | |
4086 | HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi), | |
4087 | HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi), | |
4088 | HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi), | |
74ec1181 DD |
4089 | HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi), |
4090 | HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi), | |
b9a94a9c | 4091 | HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi), |
74ec1181 | 4092 | HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi), |
b9a94a9c | 4093 | HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi), |
74ec1181 DD |
4094 | HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi), |
4095 | HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi), | |
b9a94a9c TI |
4096 | HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch), |
4097 | HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi), | |
4098 | HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi), | |
4099 | HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi), | |
74ec1181 DD |
4100 | HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi), |
4101 | HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi), | |
4102 | HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi), | |
4103 | HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi), | |
4104 | HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi), | |
b9a94a9c | 4105 | HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi), |
74ec1181 | 4106 | HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi), |
af677166 | 4107 | HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi), |
74ec1181 | 4108 | HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi), |
2d369c74 | 4109 | HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi), |
3ec622f4 | 4110 | HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi), |
74ec1181 DD |
4111 | HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi), |
4112 | HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi), | |
4113 | HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi), | |
4114 | HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi), | |
4115 | HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi), | |
4116 | HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi), | |
4117 | HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi), | |
4118 | HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi), | |
4119 | HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi), | |
4120 | HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi), | |
b9a94a9c | 4121 | HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch), |
74ec1181 | 4122 | HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch), |
b9a94a9c TI |
4123 | HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi), |
4124 | HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi), | |
4125 | HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi), | |
4126 | HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi), | |
7ff652ff | 4127 | HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi), |
b0d8bc50 | 4128 | HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi), |
b9a94a9c TI |
4129 | HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi), |
4130 | HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi), | |
4131 | HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi), | |
7ff652ff | 4132 | HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi), |
e85015a3 TI |
4133 | HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi), |
4134 | HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi), | |
a686632f TI |
4135 | HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi), |
4136 | HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi), | |
4137 | HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi), | |
4138 | HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi), | |
4139 | HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi), | |
2b4584d0 | 4140 | HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi), |
a87a4d23 | 4141 | HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi), |
b0d8bc50 | 4142 | HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi), |
b9a94a9c | 4143 | HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi), |
a686632f TI |
4144 | HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi), |
4145 | HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi), | |
b9a94a9c | 4146 | HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi), |
d8a766a1 | 4147 | /* special ID for generic HDMI */ |
b9a94a9c | 4148 | HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi), |
84eb01be TI |
4149 | {} /* terminator */ |
4150 | }; | |
b9a94a9c | 4151 | MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi); |
84eb01be TI |
4152 | |
4153 | MODULE_LICENSE("GPL"); | |
4154 | MODULE_DESCRIPTION("HDMI HD-audio codec"); | |
4155 | MODULE_ALIAS("snd-hda-codec-intelhdmi"); | |
4156 | MODULE_ALIAS("snd-hda-codec-nvhdmi"); | |
4157 | MODULE_ALIAS("snd-hda-codec-atihdmi"); | |
4158 | ||
d8a766a1 | 4159 | static struct hda_codec_driver hdmi_driver = { |
b9a94a9c | 4160 | .id = snd_hda_id_hdmi, |
84eb01be TI |
4161 | }; |
4162 | ||
d8a766a1 | 4163 | module_hda_codec_driver(hdmi_driver); |