Commit | Line | Data |
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079d88cc WF |
1 | /* |
2 | * | |
3 | * patch_hdmi.c - routines for HDMI/DisplayPort codecs | |
4 | * | |
5 | * Copyright(c) 2008-2010 Intel Corporation. All rights reserved. | |
84eb01be TI |
6 | * Copyright (c) 2006 ATI Technologies Inc. |
7 | * Copyright (c) 2008 NVIDIA Corp. All rights reserved. | |
8 | * Copyright (c) 2008 Wei Ni <wni@nvidia.com> | |
5a613584 | 9 | * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi> |
079d88cc WF |
10 | * |
11 | * Authors: | |
12 | * Wu Fengguang <wfg@linux.intel.com> | |
13 | * | |
14 | * Maintained by: | |
15 | * Wu Fengguang <wfg@linux.intel.com> | |
16 | * | |
17 | * This program is free software; you can redistribute it and/or modify it | |
18 | * under the terms of the GNU General Public License as published by the Free | |
19 | * Software Foundation; either version 2 of the License, or (at your option) | |
20 | * any later version. | |
21 | * | |
22 | * This program is distributed in the hope that it will be useful, but | |
23 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
24 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
25 | * for more details. | |
26 | * | |
27 | * You should have received a copy of the GNU General Public License | |
28 | * along with this program; if not, write to the Free Software Foundation, | |
29 | * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
30 | */ | |
31 | ||
84eb01be TI |
32 | #include <linux/init.h> |
33 | #include <linux/delay.h> | |
34 | #include <linux/slab.h> | |
65a77217 | 35 | #include <linux/module.h> |
84eb01be | 36 | #include <sound/core.h> |
07acecc1 | 37 | #include <sound/jack.h> |
433968da | 38 | #include <sound/asoundef.h> |
d45e6889 | 39 | #include <sound/tlv.h> |
25adc137 DH |
40 | #include <sound/hdaudio.h> |
41 | #include <sound/hda_i915.h> | |
84eb01be TI |
42 | #include "hda_codec.h" |
43 | #include "hda_local.h" | |
1835a0f9 | 44 | #include "hda_jack.h" |
84eb01be | 45 | |
0ebaa24c TI |
46 | static bool static_hdmi_pcm; |
47 | module_param(static_hdmi_pcm, bool, 0644); | |
48 | MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info"); | |
49 | ||
7639a06c TI |
50 | #define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807) |
51 | #define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808) | |
52 | #define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809) | |
e2656412 | 53 | #define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a) |
432ac1a2 | 54 | #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \ |
e2656412 | 55 | || is_skylake(codec) || is_broxton(codec)) |
75dcbe4d | 56 | |
7639a06c TI |
57 | #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882) |
58 | #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883) | |
ca2e7224 | 59 | #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec)) |
fb87fa3a | 60 | |
384a48d7 SW |
61 | struct hdmi_spec_per_cvt { |
62 | hda_nid_t cvt_nid; | |
63 | int assigned; | |
64 | unsigned int channels_min; | |
65 | unsigned int channels_max; | |
66 | u32 rates; | |
67 | u64 formats; | |
68 | unsigned int maxbps; | |
69 | }; | |
079d88cc | 70 | |
4eea3091 TI |
71 | /* max. connections to a widget */ |
72 | #define HDA_MAX_CONNECTIONS 32 | |
73 | ||
384a48d7 SW |
74 | struct hdmi_spec_per_pin { |
75 | hda_nid_t pin_nid; | |
76 | int num_mux_nids; | |
77 | hda_nid_t mux_nids[HDA_MAX_CONNECTIONS]; | |
2df6742f | 78 | int mux_idx; |
1df5a06a | 79 | hda_nid_t cvt_nid; |
744626da WF |
80 | |
81 | struct hda_codec *codec; | |
384a48d7 | 82 | struct hdmi_eld sink_eld; |
a4e9a38b | 83 | struct mutex lock; |
744626da | 84 | struct delayed_work work; |
92c69e79 | 85 | struct snd_kcontrol *eld_ctl; |
c6e8453e | 86 | int repoll_count; |
b054087d TI |
87 | bool setup; /* the stream has been set up by prepare callback */ |
88 | int channels; /* current number of channels */ | |
1a6003b5 | 89 | bool non_pcm; |
d45e6889 TI |
90 | bool chmap_set; /* channel-map override by ALSA API? */ |
91 | unsigned char chmap[8]; /* ALSA API channel-map */ | |
cd6a6503 | 92 | #ifdef CONFIG_SND_PROC_FS |
a4e9a38b TI |
93 | struct snd_info_entry *proc_entry; |
94 | #endif | |
384a48d7 | 95 | }; |
079d88cc | 96 | |
307229d2 AH |
97 | struct cea_channel_speaker_allocation; |
98 | ||
99 | /* operations used by generic code that can be overridden by patches */ | |
100 | struct hdmi_ops { | |
101 | int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid, | |
102 | unsigned char *buf, int *eld_size); | |
103 | ||
104 | /* get and set channel assigned to each HDMI ASP (audio sample packet) slot */ | |
105 | int (*pin_get_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid, | |
106 | int asp_slot); | |
107 | int (*pin_set_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid, | |
108 | int asp_slot, int channel); | |
109 | ||
110 | void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid, | |
111 | int ca, int active_channels, int conn_type); | |
112 | ||
113 | /* enable/disable HBR (HD passthrough) */ | |
114 | int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr); | |
115 | ||
116 | int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid, | |
117 | hda_nid_t pin_nid, u32 stream_tag, int format); | |
118 | ||
119 | /* Helpers for producing the channel map TLVs. These can be overridden | |
120 | * for devices that have non-standard mapping requirements. */ | |
121 | int (*chmap_cea_alloc_validate_get_type)(struct cea_channel_speaker_allocation *cap, | |
122 | int channels); | |
123 | void (*cea_alloc_to_tlv_chmap)(struct cea_channel_speaker_allocation *cap, | |
124 | unsigned int *chmap, int channels); | |
125 | ||
126 | /* check that the user-given chmap is supported */ | |
127 | int (*chmap_validate)(int ca, int channels, unsigned char *chmap); | |
128 | }; | |
129 | ||
384a48d7 SW |
130 | struct hdmi_spec { |
131 | int num_cvts; | |
bce0d2a8 TI |
132 | struct snd_array cvts; /* struct hdmi_spec_per_cvt */ |
133 | hda_nid_t cvt_nids[4]; /* only for haswell fix */ | |
079d88cc | 134 | |
384a48d7 | 135 | int num_pins; |
bce0d2a8 | 136 | struct snd_array pins; /* struct hdmi_spec_per_pin */ |
bbbc7e85 | 137 | struct hda_pcm *pcm_rec[16]; |
d45e6889 | 138 | unsigned int channels_max; /* max over all cvts */ |
079d88cc | 139 | |
4bd038f9 | 140 | struct hdmi_eld temp_eld; |
307229d2 | 141 | struct hdmi_ops ops; |
75fae117 SW |
142 | |
143 | bool dyn_pin_out; | |
144 | ||
079d88cc | 145 | /* |
5a613584 | 146 | * Non-generic VIA/NVIDIA specific |
079d88cc WF |
147 | */ |
148 | struct hda_multi_out multiout; | |
d0b1252d | 149 | struct hda_pcm_stream pcm_playback; |
25adc137 DH |
150 | |
151 | /* i915/powerwell (Haswell+/Valleyview+) specific */ | |
152 | struct i915_audio_component_audio_ops i915_audio_ops; | |
55913110 | 153 | bool i915_bound; /* was i915 bound in this driver? */ |
079d88cc WF |
154 | }; |
155 | ||
f4e3040b | 156 | #ifdef CONFIG_SND_HDA_I915 |
6603249d TI |
157 | #define codec_has_acomp(codec) \ |
158 | ((codec)->bus->core.audio_component != NULL) | |
f4e3040b TI |
159 | #else |
160 | #define codec_has_acomp(codec) false | |
161 | #endif | |
079d88cc WF |
162 | |
163 | struct hdmi_audio_infoframe { | |
164 | u8 type; /* 0x84 */ | |
165 | u8 ver; /* 0x01 */ | |
166 | u8 len; /* 0x0a */ | |
167 | ||
53d7d69d WF |
168 | u8 checksum; |
169 | ||
079d88cc WF |
170 | u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */ |
171 | u8 SS01_SF24; | |
172 | u8 CXT04; | |
173 | u8 CA; | |
174 | u8 LFEPBL01_LSV36_DM_INH7; | |
53d7d69d WF |
175 | }; |
176 | ||
177 | struct dp_audio_infoframe { | |
178 | u8 type; /* 0x84 */ | |
179 | u8 len; /* 0x1b */ | |
180 | u8 ver; /* 0x11 << 2 */ | |
181 | ||
182 | u8 CC02_CT47; /* match with HDMI infoframe from this on */ | |
183 | u8 SS01_SF24; | |
184 | u8 CXT04; | |
185 | u8 CA; | |
186 | u8 LFEPBL01_LSV36_DM_INH7; | |
079d88cc WF |
187 | }; |
188 | ||
2b203dbb TI |
189 | union audio_infoframe { |
190 | struct hdmi_audio_infoframe hdmi; | |
191 | struct dp_audio_infoframe dp; | |
192 | u8 bytes[0]; | |
193 | }; | |
194 | ||
079d88cc WF |
195 | /* |
196 | * CEA speaker placement: | |
197 | * | |
198 | * FLH FCH FRH | |
199 | * FLW FL FLC FC FRC FR FRW | |
200 | * | |
201 | * LFE | |
202 | * TC | |
203 | * | |
204 | * RL RLC RC RRC RR | |
205 | * | |
206 | * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to | |
207 | * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC. | |
208 | */ | |
209 | enum cea_speaker_placement { | |
210 | FL = (1 << 0), /* Front Left */ | |
211 | FC = (1 << 1), /* Front Center */ | |
212 | FR = (1 << 2), /* Front Right */ | |
213 | FLC = (1 << 3), /* Front Left Center */ | |
214 | FRC = (1 << 4), /* Front Right Center */ | |
215 | RL = (1 << 5), /* Rear Left */ | |
216 | RC = (1 << 6), /* Rear Center */ | |
217 | RR = (1 << 7), /* Rear Right */ | |
218 | RLC = (1 << 8), /* Rear Left Center */ | |
219 | RRC = (1 << 9), /* Rear Right Center */ | |
220 | LFE = (1 << 10), /* Low Frequency Effect */ | |
221 | FLW = (1 << 11), /* Front Left Wide */ | |
222 | FRW = (1 << 12), /* Front Right Wide */ | |
223 | FLH = (1 << 13), /* Front Left High */ | |
224 | FCH = (1 << 14), /* Front Center High */ | |
225 | FRH = (1 << 15), /* Front Right High */ | |
226 | TC = (1 << 16), /* Top Center */ | |
227 | }; | |
228 | ||
229 | /* | |
230 | * ELD SA bits in the CEA Speaker Allocation data block | |
231 | */ | |
232 | static int eld_speaker_allocation_bits[] = { | |
233 | [0] = FL | FR, | |
234 | [1] = LFE, | |
235 | [2] = FC, | |
236 | [3] = RL | RR, | |
237 | [4] = RC, | |
238 | [5] = FLC | FRC, | |
239 | [6] = RLC | RRC, | |
240 | /* the following are not defined in ELD yet */ | |
241 | [7] = FLW | FRW, | |
242 | [8] = FLH | FRH, | |
243 | [9] = TC, | |
244 | [10] = FCH, | |
245 | }; | |
246 | ||
247 | struct cea_channel_speaker_allocation { | |
248 | int ca_index; | |
249 | int speakers[8]; | |
250 | ||
251 | /* derived values, just for convenience */ | |
252 | int channels; | |
253 | int spk_mask; | |
254 | }; | |
255 | ||
256 | /* | |
257 | * ALSA sequence is: | |
258 | * | |
259 | * surround40 surround41 surround50 surround51 surround71 | |
260 | * ch0 front left = = = = | |
261 | * ch1 front right = = = = | |
262 | * ch2 rear left = = = = | |
263 | * ch3 rear right = = = = | |
264 | * ch4 LFE center center center | |
265 | * ch5 LFE LFE | |
266 | * ch6 side left | |
267 | * ch7 side right | |
268 | * | |
269 | * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR} | |
270 | */ | |
271 | static int hdmi_channel_mapping[0x32][8] = { | |
272 | /* stereo */ | |
273 | [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 }, | |
274 | /* 2.1 */ | |
275 | [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 }, | |
276 | /* Dolby Surround */ | |
277 | [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 }, | |
278 | /* surround40 */ | |
279 | [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 }, | |
280 | /* 4ch */ | |
281 | [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 }, | |
282 | /* surround41 */ | |
9396d317 | 283 | [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 }, |
079d88cc WF |
284 | /* surround50 */ |
285 | [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 }, | |
286 | /* surround51 */ | |
287 | [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 }, | |
288 | /* 7.1 */ | |
289 | [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 }, | |
290 | }; | |
291 | ||
292 | /* | |
293 | * This is an ordered list! | |
294 | * | |
295 | * The preceding ones have better chances to be selected by | |
53d7d69d | 296 | * hdmi_channel_allocation(). |
079d88cc WF |
297 | */ |
298 | static struct cea_channel_speaker_allocation channel_allocations[] = { | |
299 | /* channel: 7 6 5 4 3 2 1 0 */ | |
300 | { .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } }, | |
301 | /* 2.1 */ | |
302 | { .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } }, | |
303 | /* Dolby Surround */ | |
304 | { .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } }, | |
305 | /* surround40 */ | |
306 | { .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } }, | |
307 | /* surround41 */ | |
308 | { .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } }, | |
309 | /* surround50 */ | |
310 | { .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } }, | |
311 | /* surround51 */ | |
312 | { .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } }, | |
313 | /* 6.1 */ | |
314 | { .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } }, | |
315 | /* surround71 */ | |
316 | { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } }, | |
317 | ||
318 | { .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } }, | |
319 | { .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } }, | |
320 | { .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } }, | |
321 | { .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } }, | |
322 | { .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } }, | |
323 | { .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } }, | |
324 | { .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } }, | |
325 | { .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } }, | |
326 | { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } }, | |
327 | { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } }, | |
328 | { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } }, | |
329 | { .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } }, | |
330 | { .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } }, | |
331 | { .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } }, | |
332 | { .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } }, | |
333 | { .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } }, | |
334 | { .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } }, | |
335 | { .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } }, | |
336 | { .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } }, | |
337 | { .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } }, | |
338 | { .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } }, | |
339 | { .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } }, | |
340 | { .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } }, | |
341 | { .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } }, | |
342 | { .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } }, | |
343 | { .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } }, | |
344 | { .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } }, | |
345 | { .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } }, | |
346 | { .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } }, | |
347 | { .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } }, | |
348 | { .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } }, | |
349 | { .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } }, | |
350 | { .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } }, | |
351 | { .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } }, | |
352 | { .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } }, | |
353 | { .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } }, | |
354 | { .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } }, | |
355 | { .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } }, | |
356 | { .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } }, | |
357 | { .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } }, | |
358 | { .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } }, | |
359 | }; | |
360 | ||
361 | ||
362 | /* | |
363 | * HDMI routines | |
364 | */ | |
365 | ||
bce0d2a8 TI |
366 | #define get_pin(spec, idx) \ |
367 | ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx)) | |
368 | #define get_cvt(spec, idx) \ | |
369 | ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx)) | |
bbbc7e85 | 370 | #define get_pcm_rec(spec, idx) ((spec)->pcm_rec[idx]) |
bce0d2a8 | 371 | |
4e76a883 | 372 | static int pin_nid_to_pin_index(struct hda_codec *codec, hda_nid_t pin_nid) |
079d88cc | 373 | { |
4e76a883 | 374 | struct hdmi_spec *spec = codec->spec; |
384a48d7 | 375 | int pin_idx; |
079d88cc | 376 | |
384a48d7 | 377 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) |
bce0d2a8 | 378 | if (get_pin(spec, pin_idx)->pin_nid == pin_nid) |
384a48d7 | 379 | return pin_idx; |
079d88cc | 380 | |
4e76a883 | 381 | codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid); |
384a48d7 SW |
382 | return -EINVAL; |
383 | } | |
384 | ||
4e76a883 | 385 | static int hinfo_to_pin_index(struct hda_codec *codec, |
384a48d7 SW |
386 | struct hda_pcm_stream *hinfo) |
387 | { | |
4e76a883 | 388 | struct hdmi_spec *spec = codec->spec; |
384a48d7 SW |
389 | int pin_idx; |
390 | ||
391 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) | |
bce0d2a8 | 392 | if (get_pcm_rec(spec, pin_idx)->stream == hinfo) |
384a48d7 SW |
393 | return pin_idx; |
394 | ||
4e76a883 | 395 | codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo); |
384a48d7 SW |
396 | return -EINVAL; |
397 | } | |
398 | ||
4e76a883 | 399 | static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid) |
384a48d7 | 400 | { |
4e76a883 | 401 | struct hdmi_spec *spec = codec->spec; |
384a48d7 SW |
402 | int cvt_idx; |
403 | ||
404 | for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) | |
bce0d2a8 | 405 | if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid) |
384a48d7 SW |
406 | return cvt_idx; |
407 | ||
4e76a883 | 408 | codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid); |
079d88cc WF |
409 | return -EINVAL; |
410 | } | |
411 | ||
14bc52b8 PLB |
412 | static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol, |
413 | struct snd_ctl_elem_info *uinfo) | |
414 | { | |
415 | struct hda_codec *codec = snd_kcontrol_chip(kcontrol); | |
68e03de9 | 416 | struct hdmi_spec *spec = codec->spec; |
a4e9a38b | 417 | struct hdmi_spec_per_pin *per_pin; |
68e03de9 | 418 | struct hdmi_eld *eld; |
14bc52b8 PLB |
419 | int pin_idx; |
420 | ||
14bc52b8 PLB |
421 | uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; |
422 | ||
423 | pin_idx = kcontrol->private_value; | |
a4e9a38b TI |
424 | per_pin = get_pin(spec, pin_idx); |
425 | eld = &per_pin->sink_eld; | |
68e03de9 | 426 | |
a4e9a38b | 427 | mutex_lock(&per_pin->lock); |
68e03de9 | 428 | uinfo->count = eld->eld_valid ? eld->eld_size : 0; |
a4e9a38b | 429 | mutex_unlock(&per_pin->lock); |
14bc52b8 PLB |
430 | |
431 | return 0; | |
432 | } | |
433 | ||
434 | static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol, | |
435 | struct snd_ctl_elem_value *ucontrol) | |
436 | { | |
437 | struct hda_codec *codec = snd_kcontrol_chip(kcontrol); | |
68e03de9 | 438 | struct hdmi_spec *spec = codec->spec; |
a4e9a38b | 439 | struct hdmi_spec_per_pin *per_pin; |
68e03de9 | 440 | struct hdmi_eld *eld; |
14bc52b8 PLB |
441 | int pin_idx; |
442 | ||
14bc52b8 | 443 | pin_idx = kcontrol->private_value; |
a4e9a38b TI |
444 | per_pin = get_pin(spec, pin_idx); |
445 | eld = &per_pin->sink_eld; | |
68e03de9 | 446 | |
a4e9a38b | 447 | mutex_lock(&per_pin->lock); |
68e03de9 | 448 | if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data)) { |
a4e9a38b | 449 | mutex_unlock(&per_pin->lock); |
68e03de9 DH |
450 | snd_BUG(); |
451 | return -EINVAL; | |
452 | } | |
453 | ||
454 | memset(ucontrol->value.bytes.data, 0, | |
455 | ARRAY_SIZE(ucontrol->value.bytes.data)); | |
456 | if (eld->eld_valid) | |
457 | memcpy(ucontrol->value.bytes.data, eld->eld_buffer, | |
458 | eld->eld_size); | |
a4e9a38b | 459 | mutex_unlock(&per_pin->lock); |
14bc52b8 PLB |
460 | |
461 | return 0; | |
462 | } | |
463 | ||
464 | static struct snd_kcontrol_new eld_bytes_ctl = { | |
465 | .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, | |
466 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, | |
467 | .name = "ELD", | |
468 | .info = hdmi_eld_ctl_info, | |
469 | .get = hdmi_eld_ctl_get, | |
470 | }; | |
471 | ||
472 | static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx, | |
473 | int device) | |
474 | { | |
475 | struct snd_kcontrol *kctl; | |
476 | struct hdmi_spec *spec = codec->spec; | |
477 | int err; | |
478 | ||
479 | kctl = snd_ctl_new1(&eld_bytes_ctl, codec); | |
480 | if (!kctl) | |
481 | return -ENOMEM; | |
482 | kctl->private_value = pin_idx; | |
483 | kctl->id.device = device; | |
484 | ||
bce0d2a8 | 485 | err = snd_hda_ctl_add(codec, get_pin(spec, pin_idx)->pin_nid, kctl); |
14bc52b8 PLB |
486 | if (err < 0) |
487 | return err; | |
488 | ||
bce0d2a8 | 489 | get_pin(spec, pin_idx)->eld_ctl = kctl; |
14bc52b8 PLB |
490 | return 0; |
491 | } | |
492 | ||
079d88cc WF |
493 | #ifdef BE_PARANOID |
494 | static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, | |
495 | int *packet_index, int *byte_index) | |
496 | { | |
497 | int val; | |
498 | ||
499 | val = snd_hda_codec_read(codec, pin_nid, 0, | |
500 | AC_VERB_GET_HDMI_DIP_INDEX, 0); | |
501 | ||
502 | *packet_index = val >> 5; | |
503 | *byte_index = val & 0x1f; | |
504 | } | |
505 | #endif | |
506 | ||
507 | static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, | |
508 | int packet_index, int byte_index) | |
509 | { | |
510 | int val; | |
511 | ||
512 | val = (packet_index << 5) | (byte_index & 0x1f); | |
513 | ||
514 | snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val); | |
515 | } | |
516 | ||
517 | static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid, | |
518 | unsigned char val) | |
519 | { | |
520 | snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val); | |
521 | } | |
522 | ||
384a48d7 | 523 | static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid) |
079d88cc | 524 | { |
75fae117 SW |
525 | struct hdmi_spec *spec = codec->spec; |
526 | int pin_out; | |
527 | ||
079d88cc WF |
528 | /* Unmute */ |
529 | if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) | |
530 | snd_hda_codec_write(codec, pin_nid, 0, | |
531 | AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE); | |
75fae117 SW |
532 | |
533 | if (spec->dyn_pin_out) | |
534 | /* Disable pin out until stream is active */ | |
535 | pin_out = 0; | |
536 | else | |
537 | /* Enable pin out: some machines with GM965 gets broken output | |
538 | * when the pin is disabled or changed while using with HDMI | |
539 | */ | |
540 | pin_out = PIN_OUT; | |
541 | ||
079d88cc | 542 | snd_hda_codec_write(codec, pin_nid, 0, |
75fae117 | 543 | AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out); |
079d88cc WF |
544 | } |
545 | ||
384a48d7 | 546 | static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid) |
079d88cc | 547 | { |
384a48d7 | 548 | return 1 + snd_hda_codec_read(codec, cvt_nid, 0, |
079d88cc WF |
549 | AC_VERB_GET_CVT_CHAN_COUNT, 0); |
550 | } | |
551 | ||
552 | static void hdmi_set_channel_count(struct hda_codec *codec, | |
384a48d7 | 553 | hda_nid_t cvt_nid, int chs) |
079d88cc | 554 | { |
384a48d7 SW |
555 | if (chs != hdmi_get_channel_count(codec, cvt_nid)) |
556 | snd_hda_codec_write(codec, cvt_nid, 0, | |
079d88cc WF |
557 | AC_VERB_SET_CVT_CHAN_COUNT, chs - 1); |
558 | } | |
559 | ||
a4e9a38b TI |
560 | /* |
561 | * ELD proc files | |
562 | */ | |
563 | ||
cd6a6503 | 564 | #ifdef CONFIG_SND_PROC_FS |
a4e9a38b TI |
565 | static void print_eld_info(struct snd_info_entry *entry, |
566 | struct snd_info_buffer *buffer) | |
567 | { | |
568 | struct hdmi_spec_per_pin *per_pin = entry->private_data; | |
569 | ||
570 | mutex_lock(&per_pin->lock); | |
571 | snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer); | |
572 | mutex_unlock(&per_pin->lock); | |
573 | } | |
574 | ||
575 | static void write_eld_info(struct snd_info_entry *entry, | |
576 | struct snd_info_buffer *buffer) | |
577 | { | |
578 | struct hdmi_spec_per_pin *per_pin = entry->private_data; | |
579 | ||
580 | mutex_lock(&per_pin->lock); | |
581 | snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer); | |
582 | mutex_unlock(&per_pin->lock); | |
583 | } | |
584 | ||
585 | static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index) | |
586 | { | |
587 | char name[32]; | |
588 | struct hda_codec *codec = per_pin->codec; | |
589 | struct snd_info_entry *entry; | |
590 | int err; | |
591 | ||
592 | snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index); | |
6efdd851 | 593 | err = snd_card_proc_new(codec->card, name, &entry); |
a4e9a38b TI |
594 | if (err < 0) |
595 | return err; | |
596 | ||
597 | snd_info_set_text_ops(entry, per_pin, print_eld_info); | |
598 | entry->c.text.write = write_eld_info; | |
599 | entry->mode |= S_IWUSR; | |
600 | per_pin->proc_entry = entry; | |
601 | ||
602 | return 0; | |
603 | } | |
604 | ||
605 | static void eld_proc_free(struct hdmi_spec_per_pin *per_pin) | |
606 | { | |
1947a114 | 607 | if (!per_pin->codec->bus->shutdown) { |
c560a679 | 608 | snd_info_free_entry(per_pin->proc_entry); |
a4e9a38b TI |
609 | per_pin->proc_entry = NULL; |
610 | } | |
611 | } | |
612 | #else | |
b55447a7 TI |
613 | static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin, |
614 | int index) | |
a4e9a38b TI |
615 | { |
616 | return 0; | |
617 | } | |
b55447a7 | 618 | static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin) |
a4e9a38b TI |
619 | { |
620 | } | |
621 | #endif | |
079d88cc WF |
622 | |
623 | /* | |
624 | * Channel mapping routines | |
625 | */ | |
626 | ||
627 | /* | |
628 | * Compute derived values in channel_allocations[]. | |
629 | */ | |
630 | static void init_channel_allocations(void) | |
631 | { | |
632 | int i, j; | |
633 | struct cea_channel_speaker_allocation *p; | |
634 | ||
635 | for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { | |
636 | p = channel_allocations + i; | |
637 | p->channels = 0; | |
638 | p->spk_mask = 0; | |
639 | for (j = 0; j < ARRAY_SIZE(p->speakers); j++) | |
640 | if (p->speakers[j]) { | |
641 | p->channels++; | |
642 | p->spk_mask |= p->speakers[j]; | |
643 | } | |
644 | } | |
645 | } | |
646 | ||
72357c78 WX |
647 | static int get_channel_allocation_order(int ca) |
648 | { | |
649 | int i; | |
650 | ||
651 | for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { | |
652 | if (channel_allocations[i].ca_index == ca) | |
653 | break; | |
654 | } | |
655 | return i; | |
656 | } | |
657 | ||
079d88cc WF |
658 | /* |
659 | * The transformation takes two steps: | |
660 | * | |
661 | * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask | |
662 | * spk_mask => (channel_allocations[]) => ai->CA | |
663 | * | |
664 | * TODO: it could select the wrong CA from multiple candidates. | |
665 | */ | |
79514d47 TI |
666 | static int hdmi_channel_allocation(struct hda_codec *codec, |
667 | struct hdmi_eld *eld, int channels) | |
079d88cc | 668 | { |
079d88cc | 669 | int i; |
53d7d69d | 670 | int ca = 0; |
079d88cc | 671 | int spk_mask = 0; |
079d88cc WF |
672 | char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE]; |
673 | ||
674 | /* | |
675 | * CA defaults to 0 for basic stereo audio | |
676 | */ | |
677 | if (channels <= 2) | |
678 | return 0; | |
679 | ||
079d88cc WF |
680 | /* |
681 | * expand ELD's speaker allocation mask | |
682 | * | |
683 | * ELD tells the speaker mask in a compact(paired) form, | |
684 | * expand ELD's notions to match the ones used by Audio InfoFrame. | |
685 | */ | |
686 | for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) { | |
1613d6b4 | 687 | if (eld->info.spk_alloc & (1 << i)) |
079d88cc WF |
688 | spk_mask |= eld_speaker_allocation_bits[i]; |
689 | } | |
690 | ||
691 | /* search for the first working match in the CA table */ | |
692 | for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { | |
693 | if (channels == channel_allocations[i].channels && | |
694 | (spk_mask & channel_allocations[i].spk_mask) == | |
695 | channel_allocations[i].spk_mask) { | |
53d7d69d | 696 | ca = channel_allocations[i].ca_index; |
079d88cc WF |
697 | break; |
698 | } | |
699 | } | |
700 | ||
18e39186 AH |
701 | if (!ca) { |
702 | /* if there was no match, select the regular ALSA channel | |
703 | * allocation with the matching number of channels */ | |
704 | for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { | |
705 | if (channels == channel_allocations[i].channels) { | |
706 | ca = channel_allocations[i].ca_index; | |
707 | break; | |
708 | } | |
709 | } | |
710 | } | |
711 | ||
1613d6b4 | 712 | snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf)); |
79514d47 | 713 | codec_dbg(codec, "HDMI: select CA 0x%x for %d-channel allocation: %s\n", |
53d7d69d | 714 | ca, channels, buf); |
079d88cc | 715 | |
53d7d69d | 716 | return ca; |
079d88cc WF |
717 | } |
718 | ||
719 | static void hdmi_debug_channel_mapping(struct hda_codec *codec, | |
720 | hda_nid_t pin_nid) | |
721 | { | |
722 | #ifdef CONFIG_SND_DEBUG_VERBOSE | |
307229d2 | 723 | struct hdmi_spec *spec = codec->spec; |
079d88cc | 724 | int i; |
307229d2 | 725 | int channel; |
079d88cc WF |
726 | |
727 | for (i = 0; i < 8; i++) { | |
307229d2 | 728 | channel = spec->ops.pin_get_slot_channel(codec, pin_nid, i); |
4e76a883 | 729 | codec_dbg(codec, "HDMI: ASP channel %d => slot %d\n", |
307229d2 | 730 | channel, i); |
079d88cc WF |
731 | } |
732 | #endif | |
733 | } | |
734 | ||
d45e6889 | 735 | static void hdmi_std_setup_channel_mapping(struct hda_codec *codec, |
079d88cc | 736 | hda_nid_t pin_nid, |
433968da | 737 | bool non_pcm, |
53d7d69d | 738 | int ca) |
079d88cc | 739 | { |
307229d2 | 740 | struct hdmi_spec *spec = codec->spec; |
90f28002 | 741 | struct cea_channel_speaker_allocation *ch_alloc; |
079d88cc | 742 | int i; |
079d88cc | 743 | int err; |
72357c78 | 744 | int order; |
433968da | 745 | int non_pcm_mapping[8]; |
079d88cc | 746 | |
72357c78 | 747 | order = get_channel_allocation_order(ca); |
90f28002 | 748 | ch_alloc = &channel_allocations[order]; |
433968da | 749 | |
079d88cc | 750 | if (hdmi_channel_mapping[ca][1] == 0) { |
90f28002 AH |
751 | int hdmi_slot = 0; |
752 | /* fill actual channel mappings in ALSA channel (i) order */ | |
753 | for (i = 0; i < ch_alloc->channels; i++) { | |
754 | while (!ch_alloc->speakers[7 - hdmi_slot] && !WARN_ON(hdmi_slot >= 8)) | |
755 | hdmi_slot++; /* skip zero slots */ | |
756 | ||
757 | hdmi_channel_mapping[ca][i] = (i << 4) | hdmi_slot++; | |
758 | } | |
759 | /* fill the rest of the slots with ALSA channel 0xf */ | |
760 | for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++) | |
761 | if (!ch_alloc->speakers[7 - hdmi_slot]) | |
762 | hdmi_channel_mapping[ca][i++] = (0xf << 4) | hdmi_slot; | |
079d88cc WF |
763 | } |
764 | ||
433968da | 765 | if (non_pcm) { |
90f28002 | 766 | for (i = 0; i < ch_alloc->channels; i++) |
11f7c52d | 767 | non_pcm_mapping[i] = (i << 4) | i; |
433968da | 768 | for (; i < 8; i++) |
11f7c52d | 769 | non_pcm_mapping[i] = (0xf << 4) | i; |
433968da WX |
770 | } |
771 | ||
079d88cc | 772 | for (i = 0; i < 8; i++) { |
307229d2 AH |
773 | int slotsetup = non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i]; |
774 | int hdmi_slot = slotsetup & 0x0f; | |
775 | int channel = (slotsetup & 0xf0) >> 4; | |
776 | err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot, channel); | |
079d88cc | 777 | if (err) { |
4e76a883 | 778 | codec_dbg(codec, "HDMI: channel mapping failed\n"); |
079d88cc WF |
779 | break; |
780 | } | |
781 | } | |
079d88cc WF |
782 | } |
783 | ||
d45e6889 TI |
784 | struct channel_map_table { |
785 | unsigned char map; /* ALSA API channel map position */ | |
d45e6889 TI |
786 | int spk_mask; /* speaker position bit mask */ |
787 | }; | |
788 | ||
789 | static struct channel_map_table map_tables[] = { | |
a5b7d510 AH |
790 | { SNDRV_CHMAP_FL, FL }, |
791 | { SNDRV_CHMAP_FR, FR }, | |
792 | { SNDRV_CHMAP_RL, RL }, | |
793 | { SNDRV_CHMAP_RR, RR }, | |
794 | { SNDRV_CHMAP_LFE, LFE }, | |
795 | { SNDRV_CHMAP_FC, FC }, | |
796 | { SNDRV_CHMAP_RLC, RLC }, | |
797 | { SNDRV_CHMAP_RRC, RRC }, | |
798 | { SNDRV_CHMAP_RC, RC }, | |
799 | { SNDRV_CHMAP_FLC, FLC }, | |
800 | { SNDRV_CHMAP_FRC, FRC }, | |
94908a39 AH |
801 | { SNDRV_CHMAP_TFL, FLH }, |
802 | { SNDRV_CHMAP_TFR, FRH }, | |
a5b7d510 AH |
803 | { SNDRV_CHMAP_FLW, FLW }, |
804 | { SNDRV_CHMAP_FRW, FRW }, | |
805 | { SNDRV_CHMAP_TC, TC }, | |
94908a39 | 806 | { SNDRV_CHMAP_TFC, FCH }, |
d45e6889 TI |
807 | {} /* terminator */ |
808 | }; | |
809 | ||
810 | /* from ALSA API channel position to speaker bit mask */ | |
811 | static int to_spk_mask(unsigned char c) | |
812 | { | |
813 | struct channel_map_table *t = map_tables; | |
814 | for (; t->map; t++) { | |
815 | if (t->map == c) | |
816 | return t->spk_mask; | |
817 | } | |
818 | return 0; | |
819 | } | |
820 | ||
821 | /* from ALSA API channel position to CEA slot */ | |
a5b7d510 | 822 | static int to_cea_slot(int ordered_ca, unsigned char pos) |
d45e6889 | 823 | { |
a5b7d510 AH |
824 | int mask = to_spk_mask(pos); |
825 | int i; | |
d45e6889 | 826 | |
a5b7d510 AH |
827 | if (mask) { |
828 | for (i = 0; i < 8; i++) { | |
829 | if (channel_allocations[ordered_ca].speakers[7 - i] == mask) | |
830 | return i; | |
831 | } | |
d45e6889 | 832 | } |
a5b7d510 AH |
833 | |
834 | return -1; | |
d45e6889 TI |
835 | } |
836 | ||
837 | /* from speaker bit mask to ALSA API channel position */ | |
838 | static int spk_to_chmap(int spk) | |
839 | { | |
840 | struct channel_map_table *t = map_tables; | |
841 | for (; t->map; t++) { | |
842 | if (t->spk_mask == spk) | |
843 | return t->map; | |
844 | } | |
845 | return 0; | |
846 | } | |
847 | ||
a5b7d510 AH |
848 | /* from CEA slot to ALSA API channel position */ |
849 | static int from_cea_slot(int ordered_ca, unsigned char slot) | |
850 | { | |
851 | int mask = channel_allocations[ordered_ca].speakers[7 - slot]; | |
852 | ||
853 | return spk_to_chmap(mask); | |
854 | } | |
855 | ||
d45e6889 TI |
856 | /* get the CA index corresponding to the given ALSA API channel map */ |
857 | static int hdmi_manual_channel_allocation(int chs, unsigned char *map) | |
858 | { | |
859 | int i, spks = 0, spk_mask = 0; | |
860 | ||
861 | for (i = 0; i < chs; i++) { | |
862 | int mask = to_spk_mask(map[i]); | |
863 | if (mask) { | |
864 | spk_mask |= mask; | |
865 | spks++; | |
866 | } | |
867 | } | |
868 | ||
869 | for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { | |
870 | if ((chs == channel_allocations[i].channels || | |
871 | spks == channel_allocations[i].channels) && | |
872 | (spk_mask & channel_allocations[i].spk_mask) == | |
873 | channel_allocations[i].spk_mask) | |
874 | return channel_allocations[i].ca_index; | |
875 | } | |
876 | return -1; | |
877 | } | |
878 | ||
879 | /* set up the channel slots for the given ALSA API channel map */ | |
880 | static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec, | |
881 | hda_nid_t pin_nid, | |
a5b7d510 AH |
882 | int chs, unsigned char *map, |
883 | int ca) | |
d45e6889 | 884 | { |
307229d2 | 885 | struct hdmi_spec *spec = codec->spec; |
a5b7d510 | 886 | int ordered_ca = get_channel_allocation_order(ca); |
11f7c52d AH |
887 | int alsa_pos, hdmi_slot; |
888 | int assignments[8] = {[0 ... 7] = 0xf}; | |
889 | ||
890 | for (alsa_pos = 0; alsa_pos < chs; alsa_pos++) { | |
891 | ||
a5b7d510 | 892 | hdmi_slot = to_cea_slot(ordered_ca, map[alsa_pos]); |
11f7c52d AH |
893 | |
894 | if (hdmi_slot < 0) | |
895 | continue; /* unassigned channel */ | |
896 | ||
897 | assignments[hdmi_slot] = alsa_pos; | |
898 | } | |
899 | ||
900 | for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++) { | |
307229d2 | 901 | int err; |
11f7c52d | 902 | |
307229d2 AH |
903 | err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot, |
904 | assignments[hdmi_slot]); | |
d45e6889 TI |
905 | if (err) |
906 | return -EINVAL; | |
907 | } | |
908 | return 0; | |
909 | } | |
910 | ||
911 | /* store ALSA API channel map from the current default map */ | |
912 | static void hdmi_setup_fake_chmap(unsigned char *map, int ca) | |
913 | { | |
914 | int i; | |
56cac413 | 915 | int ordered_ca = get_channel_allocation_order(ca); |
d45e6889 | 916 | for (i = 0; i < 8; i++) { |
56cac413 | 917 | if (i < channel_allocations[ordered_ca].channels) |
a5b7d510 | 918 | map[i] = from_cea_slot(ordered_ca, hdmi_channel_mapping[ca][i] & 0x0f); |
d45e6889 TI |
919 | else |
920 | map[i] = 0; | |
921 | } | |
922 | } | |
923 | ||
924 | static void hdmi_setup_channel_mapping(struct hda_codec *codec, | |
925 | hda_nid_t pin_nid, bool non_pcm, int ca, | |
20608731 AH |
926 | int channels, unsigned char *map, |
927 | bool chmap_set) | |
d45e6889 | 928 | { |
20608731 | 929 | if (!non_pcm && chmap_set) { |
d45e6889 | 930 | hdmi_manual_setup_channel_mapping(codec, pin_nid, |
a5b7d510 | 931 | channels, map, ca); |
d45e6889 TI |
932 | } else { |
933 | hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca); | |
934 | hdmi_setup_fake_chmap(map, ca); | |
935 | } | |
980b2495 AH |
936 | |
937 | hdmi_debug_channel_mapping(codec, pin_nid); | |
d45e6889 | 938 | } |
079d88cc | 939 | |
307229d2 AH |
940 | static int hdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid, |
941 | int asp_slot, int channel) | |
942 | { | |
943 | return snd_hda_codec_write(codec, pin_nid, 0, | |
944 | AC_VERB_SET_HDMI_CHAN_SLOT, | |
945 | (channel << 4) | asp_slot); | |
946 | } | |
947 | ||
948 | static int hdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid, | |
949 | int asp_slot) | |
950 | { | |
951 | return (snd_hda_codec_read(codec, pin_nid, 0, | |
952 | AC_VERB_GET_HDMI_CHAN_SLOT, | |
953 | asp_slot) & 0xf0) >> 4; | |
954 | } | |
955 | ||
079d88cc WF |
956 | /* |
957 | * Audio InfoFrame routines | |
958 | */ | |
959 | ||
960 | /* | |
961 | * Enable Audio InfoFrame Transmission | |
962 | */ | |
963 | static void hdmi_start_infoframe_trans(struct hda_codec *codec, | |
964 | hda_nid_t pin_nid) | |
965 | { | |
966 | hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); | |
967 | snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, | |
968 | AC_DIPXMIT_BEST); | |
969 | } | |
970 | ||
971 | /* | |
972 | * Disable Audio InfoFrame Transmission | |
973 | */ | |
974 | static void hdmi_stop_infoframe_trans(struct hda_codec *codec, | |
975 | hda_nid_t pin_nid) | |
976 | { | |
977 | hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); | |
978 | snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, | |
979 | AC_DIPXMIT_DISABLE); | |
980 | } | |
981 | ||
982 | static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid) | |
983 | { | |
984 | #ifdef CONFIG_SND_DEBUG_VERBOSE | |
985 | int i; | |
986 | int size; | |
987 | ||
988 | size = snd_hdmi_get_eld_size(codec, pin_nid); | |
4e76a883 | 989 | codec_dbg(codec, "HDMI: ELD buf size is %d\n", size); |
079d88cc WF |
990 | |
991 | for (i = 0; i < 8; i++) { | |
992 | size = snd_hda_codec_read(codec, pin_nid, 0, | |
993 | AC_VERB_GET_HDMI_DIP_SIZE, i); | |
4e76a883 | 994 | codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size); |
079d88cc WF |
995 | } |
996 | #endif | |
997 | } | |
998 | ||
999 | static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid) | |
1000 | { | |
1001 | #ifdef BE_PARANOID | |
1002 | int i, j; | |
1003 | int size; | |
1004 | int pi, bi; | |
1005 | for (i = 0; i < 8; i++) { | |
1006 | size = snd_hda_codec_read(codec, pin_nid, 0, | |
1007 | AC_VERB_GET_HDMI_DIP_SIZE, i); | |
1008 | if (size == 0) | |
1009 | continue; | |
1010 | ||
1011 | hdmi_set_dip_index(codec, pin_nid, i, 0x0); | |
1012 | for (j = 1; j < 1000; j++) { | |
1013 | hdmi_write_dip_byte(codec, pin_nid, 0x0); | |
1014 | hdmi_get_dip_index(codec, pin_nid, &pi, &bi); | |
1015 | if (pi != i) | |
4e76a883 | 1016 | codec_dbg(codec, "dip index %d: %d != %d\n", |
079d88cc WF |
1017 | bi, pi, i); |
1018 | if (bi == 0) /* byte index wrapped around */ | |
1019 | break; | |
1020 | } | |
4e76a883 | 1021 | codec_dbg(codec, |
079d88cc WF |
1022 | "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n", |
1023 | i, size, j); | |
1024 | } | |
1025 | #endif | |
1026 | } | |
1027 | ||
53d7d69d | 1028 | static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai) |
079d88cc | 1029 | { |
53d7d69d | 1030 | u8 *bytes = (u8 *)hdmi_ai; |
079d88cc WF |
1031 | u8 sum = 0; |
1032 | int i; | |
1033 | ||
53d7d69d | 1034 | hdmi_ai->checksum = 0; |
079d88cc | 1035 | |
53d7d69d | 1036 | for (i = 0; i < sizeof(*hdmi_ai); i++) |
079d88cc WF |
1037 | sum += bytes[i]; |
1038 | ||
53d7d69d | 1039 | hdmi_ai->checksum = -sum; |
079d88cc WF |
1040 | } |
1041 | ||
1042 | static void hdmi_fill_audio_infoframe(struct hda_codec *codec, | |
1043 | hda_nid_t pin_nid, | |
53d7d69d | 1044 | u8 *dip, int size) |
079d88cc | 1045 | { |
079d88cc WF |
1046 | int i; |
1047 | ||
1048 | hdmi_debug_dip_size(codec, pin_nid); | |
1049 | hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */ | |
1050 | ||
079d88cc | 1051 | hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); |
53d7d69d WF |
1052 | for (i = 0; i < size; i++) |
1053 | hdmi_write_dip_byte(codec, pin_nid, dip[i]); | |
079d88cc WF |
1054 | } |
1055 | ||
1056 | static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid, | |
53d7d69d | 1057 | u8 *dip, int size) |
079d88cc | 1058 | { |
079d88cc WF |
1059 | u8 val; |
1060 | int i; | |
1061 | ||
1062 | if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0) | |
1063 | != AC_DIPXMIT_BEST) | |
1064 | return false; | |
1065 | ||
1066 | hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); | |
53d7d69d | 1067 | for (i = 0; i < size; i++) { |
079d88cc WF |
1068 | val = snd_hda_codec_read(codec, pin_nid, 0, |
1069 | AC_VERB_GET_HDMI_DIP_DATA, 0); | |
53d7d69d | 1070 | if (val != dip[i]) |
079d88cc WF |
1071 | return false; |
1072 | } | |
1073 | ||
1074 | return true; | |
1075 | } | |
1076 | ||
307229d2 AH |
1077 | static void hdmi_pin_setup_infoframe(struct hda_codec *codec, |
1078 | hda_nid_t pin_nid, | |
1079 | int ca, int active_channels, | |
1080 | int conn_type) | |
1081 | { | |
1082 | union audio_infoframe ai; | |
1083 | ||
caaf5ef9 | 1084 | memset(&ai, 0, sizeof(ai)); |
307229d2 AH |
1085 | if (conn_type == 0) { /* HDMI */ |
1086 | struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi; | |
1087 | ||
1088 | hdmi_ai->type = 0x84; | |
1089 | hdmi_ai->ver = 0x01; | |
1090 | hdmi_ai->len = 0x0a; | |
1091 | hdmi_ai->CC02_CT47 = active_channels - 1; | |
1092 | hdmi_ai->CA = ca; | |
1093 | hdmi_checksum_audio_infoframe(hdmi_ai); | |
1094 | } else if (conn_type == 1) { /* DisplayPort */ | |
1095 | struct dp_audio_infoframe *dp_ai = &ai.dp; | |
1096 | ||
1097 | dp_ai->type = 0x84; | |
1098 | dp_ai->len = 0x1b; | |
1099 | dp_ai->ver = 0x11 << 2; | |
1100 | dp_ai->CC02_CT47 = active_channels - 1; | |
1101 | dp_ai->CA = ca; | |
1102 | } else { | |
4e76a883 | 1103 | codec_dbg(codec, "HDMI: unknown connection type at pin %d\n", |
307229d2 AH |
1104 | pin_nid); |
1105 | return; | |
1106 | } | |
1107 | ||
1108 | /* | |
1109 | * sizeof(ai) is used instead of sizeof(*hdmi_ai) or | |
1110 | * sizeof(*dp_ai) to avoid partial match/update problems when | |
1111 | * the user switches between HDMI/DP monitors. | |
1112 | */ | |
1113 | if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes, | |
1114 | sizeof(ai))) { | |
4e76a883 TI |
1115 | codec_dbg(codec, |
1116 | "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n", | |
307229d2 AH |
1117 | pin_nid, |
1118 | active_channels, ca); | |
1119 | hdmi_stop_infoframe_trans(codec, pin_nid); | |
1120 | hdmi_fill_audio_infoframe(codec, pin_nid, | |
1121 | ai.bytes, sizeof(ai)); | |
1122 | hdmi_start_infoframe_trans(codec, pin_nid); | |
1123 | } | |
1124 | } | |
1125 | ||
b054087d TI |
1126 | static void hdmi_setup_audio_infoframe(struct hda_codec *codec, |
1127 | struct hdmi_spec_per_pin *per_pin, | |
1128 | bool non_pcm) | |
079d88cc | 1129 | { |
307229d2 | 1130 | struct hdmi_spec *spec = codec->spec; |
384a48d7 | 1131 | hda_nid_t pin_nid = per_pin->pin_nid; |
b054087d | 1132 | int channels = per_pin->channels; |
1df5a06a | 1133 | int active_channels; |
384a48d7 | 1134 | struct hdmi_eld *eld; |
1df5a06a | 1135 | int ca, ordered_ca; |
079d88cc | 1136 | |
b054087d TI |
1137 | if (!channels) |
1138 | return; | |
1139 | ||
75dcbe4d | 1140 | if (is_haswell_plus(codec)) |
58f7d28d ML |
1141 | snd_hda_codec_write(codec, pin_nid, 0, |
1142 | AC_VERB_SET_AMP_GAIN_MUTE, | |
1143 | AMP_OUT_UNMUTE); | |
1144 | ||
bce0d2a8 | 1145 | eld = &per_pin->sink_eld; |
079d88cc | 1146 | |
d45e6889 TI |
1147 | if (!non_pcm && per_pin->chmap_set) |
1148 | ca = hdmi_manual_channel_allocation(channels, per_pin->chmap); | |
1149 | else | |
79514d47 | 1150 | ca = hdmi_channel_allocation(codec, eld, channels); |
d45e6889 TI |
1151 | if (ca < 0) |
1152 | ca = 0; | |
384a48d7 | 1153 | |
1df5a06a AH |
1154 | ordered_ca = get_channel_allocation_order(ca); |
1155 | active_channels = channel_allocations[ordered_ca].channels; | |
1156 | ||
1157 | hdmi_set_channel_count(codec, per_pin->cvt_nid, active_channels); | |
1158 | ||
39edac70 AH |
1159 | /* |
1160 | * always configure channel mapping, it may have been changed by the | |
1161 | * user in the meantime | |
1162 | */ | |
1163 | hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca, | |
1164 | channels, per_pin->chmap, | |
1165 | per_pin->chmap_set); | |
1166 | ||
307229d2 AH |
1167 | spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels, |
1168 | eld->info.conn_type); | |
433968da | 1169 | |
1a6003b5 | 1170 | per_pin->non_pcm = non_pcm; |
079d88cc WF |
1171 | } |
1172 | ||
079d88cc WF |
1173 | /* |
1174 | * Unsolicited events | |
1175 | */ | |
1176 | ||
efe47108 | 1177 | static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll); |
38faddb1 | 1178 | |
1a4f69d5 | 1179 | static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid) |
079d88cc WF |
1180 | { |
1181 | struct hdmi_spec *spec = codec->spec; | |
1a4f69d5 TI |
1182 | int pin_idx = pin_nid_to_pin_index(codec, nid); |
1183 | ||
20ce9029 DH |
1184 | if (pin_idx < 0) |
1185 | return; | |
20ce9029 DH |
1186 | if (hdmi_present_sense(get_pin(spec, pin_idx), 1)) |
1187 | snd_hda_jack_report_sync(codec); | |
1188 | } | |
1189 | ||
1a4f69d5 TI |
1190 | static void jack_callback(struct hda_codec *codec, |
1191 | struct hda_jack_callback *jack) | |
1192 | { | |
1193 | check_presence_and_report(codec, jack->tbl->nid); | |
1194 | } | |
1195 | ||
20ce9029 DH |
1196 | static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res) |
1197 | { | |
3a93897e | 1198 | int tag = res >> AC_UNSOL_RES_TAG_SHIFT; |
3a93897e | 1199 | struct hda_jack_tbl *jack; |
2e59e5ab | 1200 | int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT; |
3a93897e TI |
1201 | |
1202 | jack = snd_hda_jack_tbl_get_from_tag(codec, tag); | |
1203 | if (!jack) | |
1204 | return; | |
3a93897e | 1205 | jack->jack_dirty = 1; |
079d88cc | 1206 | |
4e76a883 | 1207 | codec_dbg(codec, |
2e59e5ab | 1208 | "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n", |
20ce9029 | 1209 | codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA), |
fae3d88a | 1210 | !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV)); |
079d88cc | 1211 | |
1a4f69d5 | 1212 | check_presence_and_report(codec, jack->nid); |
079d88cc WF |
1213 | } |
1214 | ||
1215 | static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res) | |
1216 | { | |
1217 | int tag = res >> AC_UNSOL_RES_TAG_SHIFT; | |
1218 | int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; | |
1219 | int cp_state = !!(res & AC_UNSOL_RES_CP_STATE); | |
1220 | int cp_ready = !!(res & AC_UNSOL_RES_CP_READY); | |
1221 | ||
4e76a883 | 1222 | codec_info(codec, |
e9ea8e8f | 1223 | "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n", |
384a48d7 | 1224 | codec->addr, |
079d88cc WF |
1225 | tag, |
1226 | subtag, | |
1227 | cp_state, | |
1228 | cp_ready); | |
1229 | ||
1230 | /* TODO */ | |
1231 | if (cp_state) | |
1232 | ; | |
1233 | if (cp_ready) | |
1234 | ; | |
1235 | } | |
1236 | ||
1237 | ||
1238 | static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res) | |
1239 | { | |
079d88cc WF |
1240 | int tag = res >> AC_UNSOL_RES_TAG_SHIFT; |
1241 | int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; | |
1242 | ||
3a93897e | 1243 | if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) { |
4e76a883 | 1244 | codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag); |
079d88cc WF |
1245 | return; |
1246 | } | |
1247 | ||
1248 | if (subtag == 0) | |
1249 | hdmi_intrinsic_event(codec, res); | |
1250 | else | |
1251 | hdmi_non_intrinsic_event(codec, res); | |
1252 | } | |
1253 | ||
58f7d28d | 1254 | static void haswell_verify_D0(struct hda_codec *codec, |
53b434f0 | 1255 | hda_nid_t cvt_nid, hda_nid_t nid) |
83f26ad2 | 1256 | { |
58f7d28d | 1257 | int pwr; |
83f26ad2 | 1258 | |
53b434f0 WX |
1259 | /* For Haswell, the converter 1/2 may keep in D3 state after bootup, |
1260 | * thus pins could only choose converter 0 for use. Make sure the | |
1261 | * converters are in correct power state */ | |
fd678cac | 1262 | if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0)) |
53b434f0 WX |
1263 | snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0); |
1264 | ||
fd678cac | 1265 | if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) { |
83f26ad2 DH |
1266 | snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE, |
1267 | AC_PWRST_D0); | |
1268 | msleep(40); | |
1269 | pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0); | |
1270 | pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT; | |
4e76a883 | 1271 | codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr); |
83f26ad2 | 1272 | } |
83f26ad2 DH |
1273 | } |
1274 | ||
079d88cc WF |
1275 | /* |
1276 | * Callbacks | |
1277 | */ | |
1278 | ||
92f10b3f TI |
1279 | /* HBR should be Non-PCM, 8 channels */ |
1280 | #define is_hbr_format(format) \ | |
1281 | ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7) | |
1282 | ||
307229d2 AH |
1283 | static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, |
1284 | bool hbr) | |
079d88cc | 1285 | { |
307229d2 | 1286 | int pinctl, new_pinctl; |
83f26ad2 | 1287 | |
384a48d7 SW |
1288 | if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) { |
1289 | pinctl = snd_hda_codec_read(codec, pin_nid, 0, | |
ea87d1c4 AH |
1290 | AC_VERB_GET_PIN_WIDGET_CONTROL, 0); |
1291 | ||
13122e6e AH |
1292 | if (pinctl < 0) |
1293 | return hbr ? -EINVAL : 0; | |
1294 | ||
ea87d1c4 | 1295 | new_pinctl = pinctl & ~AC_PINCTL_EPT; |
307229d2 | 1296 | if (hbr) |
ea87d1c4 AH |
1297 | new_pinctl |= AC_PINCTL_EPT_HBR; |
1298 | else | |
1299 | new_pinctl |= AC_PINCTL_EPT_NATIVE; | |
1300 | ||
4e76a883 TI |
1301 | codec_dbg(codec, |
1302 | "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n", | |
384a48d7 | 1303 | pin_nid, |
ea87d1c4 AH |
1304 | pinctl == new_pinctl ? "" : "new-", |
1305 | new_pinctl); | |
1306 | ||
1307 | if (pinctl != new_pinctl) | |
384a48d7 | 1308 | snd_hda_codec_write(codec, pin_nid, 0, |
ea87d1c4 AH |
1309 | AC_VERB_SET_PIN_WIDGET_CONTROL, |
1310 | new_pinctl); | |
307229d2 AH |
1311 | } else if (hbr) |
1312 | return -EINVAL; | |
ea87d1c4 | 1313 | |
307229d2 AH |
1314 | return 0; |
1315 | } | |
1316 | ||
1317 | static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, | |
1318 | hda_nid_t pin_nid, u32 stream_tag, int format) | |
1319 | { | |
1320 | struct hdmi_spec *spec = codec->spec; | |
1321 | int err; | |
1322 | ||
75dcbe4d | 1323 | if (is_haswell_plus(codec)) |
307229d2 AH |
1324 | haswell_verify_D0(codec, cvt_nid, pin_nid); |
1325 | ||
1326 | err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format)); | |
1327 | ||
1328 | if (err) { | |
4e76a883 | 1329 | codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n"); |
307229d2 | 1330 | return err; |
ea87d1c4 | 1331 | } |
079d88cc | 1332 | |
384a48d7 | 1333 | snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format); |
ea87d1c4 | 1334 | return 0; |
079d88cc WF |
1335 | } |
1336 | ||
7ef166b8 WX |
1337 | static int hdmi_choose_cvt(struct hda_codec *codec, |
1338 | int pin_idx, int *cvt_id, int *mux_id) | |
bbbe3390 TI |
1339 | { |
1340 | struct hdmi_spec *spec = codec->spec; | |
384a48d7 | 1341 | struct hdmi_spec_per_pin *per_pin; |
384a48d7 | 1342 | struct hdmi_spec_per_cvt *per_cvt = NULL; |
7ef166b8 | 1343 | int cvt_idx, mux_idx = 0; |
bbbe3390 | 1344 | |
bce0d2a8 | 1345 | per_pin = get_pin(spec, pin_idx); |
384a48d7 SW |
1346 | |
1347 | /* Dynamically assign converter to stream */ | |
1348 | for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { | |
bce0d2a8 | 1349 | per_cvt = get_cvt(spec, cvt_idx); |
bbbe3390 | 1350 | |
384a48d7 SW |
1351 | /* Must not already be assigned */ |
1352 | if (per_cvt->assigned) | |
1353 | continue; | |
1354 | /* Must be in pin's mux's list of converters */ | |
1355 | for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) | |
1356 | if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid) | |
1357 | break; | |
1358 | /* Not in mux list */ | |
1359 | if (mux_idx == per_pin->num_mux_nids) | |
1360 | continue; | |
1361 | break; | |
1362 | } | |
7ef166b8 | 1363 | |
384a48d7 SW |
1364 | /* No free converters */ |
1365 | if (cvt_idx == spec->num_cvts) | |
1366 | return -ENODEV; | |
1367 | ||
2df6742f ML |
1368 | per_pin->mux_idx = mux_idx; |
1369 | ||
7ef166b8 WX |
1370 | if (cvt_id) |
1371 | *cvt_id = cvt_idx; | |
1372 | if (mux_id) | |
1373 | *mux_id = mux_idx; | |
1374 | ||
1375 | return 0; | |
1376 | } | |
1377 | ||
2df6742f ML |
1378 | /* Assure the pin select the right convetor */ |
1379 | static void intel_verify_pin_cvt_connect(struct hda_codec *codec, | |
1380 | struct hdmi_spec_per_pin *per_pin) | |
1381 | { | |
1382 | hda_nid_t pin_nid = per_pin->pin_nid; | |
1383 | int mux_idx, curr; | |
1384 | ||
1385 | mux_idx = per_pin->mux_idx; | |
1386 | curr = snd_hda_codec_read(codec, pin_nid, 0, | |
1387 | AC_VERB_GET_CONNECT_SEL, 0); | |
1388 | if (curr != mux_idx) | |
1389 | snd_hda_codec_write_cache(codec, pin_nid, 0, | |
1390 | AC_VERB_SET_CONNECT_SEL, | |
1391 | mux_idx); | |
1392 | } | |
1393 | ||
300016b9 ML |
1394 | /* Intel HDMI workaround to fix audio routing issue: |
1395 | * For some Intel display codecs, pins share the same connection list. | |
1396 | * So a conveter can be selected by multiple pins and playback on any of these | |
1397 | * pins will generate sound on the external display, because audio flows from | |
1398 | * the same converter to the display pipeline. Also muting one pin may make | |
1399 | * other pins have no sound output. | |
1400 | * So this function assures that an assigned converter for a pin is not selected | |
1401 | * by any other pins. | |
1402 | */ | |
1403 | static void intel_not_share_assigned_cvt(struct hda_codec *codec, | |
f82d7d16 | 1404 | hda_nid_t pin_nid, int mux_idx) |
7ef166b8 WX |
1405 | { |
1406 | struct hdmi_spec *spec = codec->spec; | |
7639a06c | 1407 | hda_nid_t nid; |
f82d7d16 ML |
1408 | int cvt_idx, curr; |
1409 | struct hdmi_spec_per_cvt *per_cvt; | |
7ef166b8 | 1410 | |
f82d7d16 | 1411 | /* configure all pins, including "no physical connection" ones */ |
7639a06c | 1412 | for_each_hda_codec_node(nid, codec) { |
f82d7d16 ML |
1413 | unsigned int wid_caps = get_wcaps(codec, nid); |
1414 | unsigned int wid_type = get_wcaps_type(wid_caps); | |
1415 | ||
1416 | if (wid_type != AC_WID_PIN) | |
1417 | continue; | |
7ef166b8 | 1418 | |
f82d7d16 | 1419 | if (nid == pin_nid) |
7ef166b8 WX |
1420 | continue; |
1421 | ||
f82d7d16 | 1422 | curr = snd_hda_codec_read(codec, nid, 0, |
7ef166b8 | 1423 | AC_VERB_GET_CONNECT_SEL, 0); |
f82d7d16 ML |
1424 | if (curr != mux_idx) |
1425 | continue; | |
7ef166b8 | 1426 | |
f82d7d16 ML |
1427 | /* choose an unassigned converter. The conveters in the |
1428 | * connection list are in the same order as in the codec. | |
1429 | */ | |
1430 | for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { | |
1431 | per_cvt = get_cvt(spec, cvt_idx); | |
1432 | if (!per_cvt->assigned) { | |
4e76a883 TI |
1433 | codec_dbg(codec, |
1434 | "choose cvt %d for pin nid %d\n", | |
f82d7d16 ML |
1435 | cvt_idx, nid); |
1436 | snd_hda_codec_write_cache(codec, nid, 0, | |
7ef166b8 | 1437 | AC_VERB_SET_CONNECT_SEL, |
f82d7d16 ML |
1438 | cvt_idx); |
1439 | break; | |
1440 | } | |
7ef166b8 WX |
1441 | } |
1442 | } | |
1443 | } | |
1444 | ||
1445 | /* | |
1446 | * HDA PCM callbacks | |
1447 | */ | |
1448 | static int hdmi_pcm_open(struct hda_pcm_stream *hinfo, | |
1449 | struct hda_codec *codec, | |
1450 | struct snd_pcm_substream *substream) | |
1451 | { | |
1452 | struct hdmi_spec *spec = codec->spec; | |
1453 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1454 | int pin_idx, cvt_idx, mux_idx = 0; | |
1455 | struct hdmi_spec_per_pin *per_pin; | |
1456 | struct hdmi_eld *eld; | |
1457 | struct hdmi_spec_per_cvt *per_cvt = NULL; | |
1458 | int err; | |
1459 | ||
1460 | /* Validate hinfo */ | |
4e76a883 | 1461 | pin_idx = hinfo_to_pin_index(codec, hinfo); |
7ef166b8 WX |
1462 | if (snd_BUG_ON(pin_idx < 0)) |
1463 | return -EINVAL; | |
1464 | per_pin = get_pin(spec, pin_idx); | |
1465 | eld = &per_pin->sink_eld; | |
1466 | ||
1467 | err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx); | |
1468 | if (err < 0) | |
1469 | return err; | |
1470 | ||
1471 | per_cvt = get_cvt(spec, cvt_idx); | |
384a48d7 SW |
1472 | /* Claim converter */ |
1473 | per_cvt->assigned = 1; | |
1df5a06a | 1474 | per_pin->cvt_nid = per_cvt->cvt_nid; |
384a48d7 SW |
1475 | hinfo->nid = per_cvt->cvt_nid; |
1476 | ||
bddee96b | 1477 | snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, |
384a48d7 SW |
1478 | AC_VERB_SET_CONNECT_SEL, |
1479 | mux_idx); | |
7ef166b8 WX |
1480 | |
1481 | /* configure unused pins to choose other converters */ | |
ca2e7224 | 1482 | if (is_haswell_plus(codec) || is_valleyview_plus(codec)) |
300016b9 | 1483 | intel_not_share_assigned_cvt(codec, per_pin->pin_nid, mux_idx); |
7ef166b8 | 1484 | |
384a48d7 | 1485 | snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid); |
bbbe3390 | 1486 | |
2def8172 | 1487 | /* Initially set the converter's capabilities */ |
384a48d7 SW |
1488 | hinfo->channels_min = per_cvt->channels_min; |
1489 | hinfo->channels_max = per_cvt->channels_max; | |
1490 | hinfo->rates = per_cvt->rates; | |
1491 | hinfo->formats = per_cvt->formats; | |
1492 | hinfo->maxbps = per_cvt->maxbps; | |
2def8172 | 1493 | |
384a48d7 | 1494 | /* Restrict capabilities by ELD if this isn't disabled */ |
c3d52105 | 1495 | if (!static_hdmi_pcm && eld->eld_valid) { |
1613d6b4 | 1496 | snd_hdmi_eld_update_pcm_info(&eld->info, hinfo); |
bbbe3390 | 1497 | if (hinfo->channels_min > hinfo->channels_max || |
2ad779b7 TI |
1498 | !hinfo->rates || !hinfo->formats) { |
1499 | per_cvt->assigned = 0; | |
1500 | hinfo->nid = 0; | |
1501 | snd_hda_spdif_ctls_unassign(codec, pin_idx); | |
bbbe3390 | 1502 | return -ENODEV; |
2ad779b7 | 1503 | } |
bbbe3390 | 1504 | } |
2def8172 SW |
1505 | |
1506 | /* Store the updated parameters */ | |
639cef0e TI |
1507 | runtime->hw.channels_min = hinfo->channels_min; |
1508 | runtime->hw.channels_max = hinfo->channels_max; | |
1509 | runtime->hw.formats = hinfo->formats; | |
1510 | runtime->hw.rates = hinfo->rates; | |
4fe2ca14 TI |
1511 | |
1512 | snd_pcm_hw_constraint_step(substream->runtime, 0, | |
1513 | SNDRV_PCM_HW_PARAM_CHANNELS, 2); | |
bbbe3390 TI |
1514 | return 0; |
1515 | } | |
1516 | ||
079d88cc WF |
1517 | /* |
1518 | * HDA/HDMI auto parsing | |
1519 | */ | |
384a48d7 | 1520 | static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx) |
079d88cc WF |
1521 | { |
1522 | struct hdmi_spec *spec = codec->spec; | |
bce0d2a8 | 1523 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); |
384a48d7 | 1524 | hda_nid_t pin_nid = per_pin->pin_nid; |
079d88cc WF |
1525 | |
1526 | if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) { | |
4e76a883 TI |
1527 | codec_warn(codec, |
1528 | "HDMI: pin %d wcaps %#x does not support connection list\n", | |
079d88cc WF |
1529 | pin_nid, get_wcaps(codec, pin_nid)); |
1530 | return -EINVAL; | |
1531 | } | |
1532 | ||
384a48d7 SW |
1533 | per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid, |
1534 | per_pin->mux_nids, | |
1535 | HDA_MAX_CONNECTIONS); | |
079d88cc WF |
1536 | |
1537 | return 0; | |
1538 | } | |
1539 | ||
e90247f9 TI |
1540 | /* update per_pin ELD from the given new ELD; |
1541 | * setup info frame and notification accordingly | |
1542 | */ | |
1543 | static void update_eld(struct hda_codec *codec, | |
1544 | struct hdmi_spec_per_pin *per_pin, | |
1545 | struct hdmi_eld *eld) | |
1546 | { | |
1547 | struct hdmi_eld *pin_eld = &per_pin->sink_eld; | |
1548 | bool old_eld_valid = pin_eld->eld_valid; | |
1549 | bool eld_changed; | |
1550 | ||
1551 | if (eld->eld_valid) | |
1552 | snd_hdmi_show_eld(codec, &eld->info); | |
1553 | ||
1554 | eld_changed = (pin_eld->eld_valid != eld->eld_valid); | |
1555 | if (eld->eld_valid && pin_eld->eld_valid) | |
1556 | if (pin_eld->eld_size != eld->eld_size || | |
1557 | memcmp(pin_eld->eld_buffer, eld->eld_buffer, | |
1558 | eld->eld_size) != 0) | |
1559 | eld_changed = true; | |
1560 | ||
1561 | pin_eld->eld_valid = eld->eld_valid; | |
1562 | pin_eld->eld_size = eld->eld_size; | |
1563 | if (eld->eld_valid) | |
1564 | memcpy(pin_eld->eld_buffer, eld->eld_buffer, eld->eld_size); | |
1565 | pin_eld->info = eld->info; | |
1566 | ||
1567 | /* | |
1568 | * Re-setup pin and infoframe. This is needed e.g. when | |
1569 | * - sink is first plugged-in | |
1570 | * - transcoder can change during stream playback on Haswell | |
1571 | * and this can make HW reset converter selection on a pin. | |
1572 | */ | |
1573 | if (eld->eld_valid && !old_eld_valid && per_pin->setup) { | |
1574 | if (is_haswell_plus(codec) || is_valleyview_plus(codec)) { | |
1575 | intel_verify_pin_cvt_connect(codec, per_pin); | |
1576 | intel_not_share_assigned_cvt(codec, per_pin->pin_nid, | |
1577 | per_pin->mux_idx); | |
1578 | } | |
1579 | ||
1580 | hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); | |
1581 | } | |
1582 | ||
1583 | if (eld_changed) | |
1584 | snd_ctl_notify(codec->card, | |
1585 | SNDRV_CTL_EVENT_MASK_VALUE | | |
1586 | SNDRV_CTL_EVENT_MASK_INFO, | |
1587 | &per_pin->eld_ctl->id); | |
1588 | } | |
1589 | ||
efe47108 | 1590 | static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll) |
079d88cc | 1591 | { |
464837a7 | 1592 | struct hda_jack_tbl *jack; |
744626da | 1593 | struct hda_codec *codec = per_pin->codec; |
4bd038f9 DH |
1594 | struct hdmi_spec *spec = codec->spec; |
1595 | struct hdmi_eld *eld = &spec->temp_eld; | |
1596 | struct hdmi_eld *pin_eld = &per_pin->sink_eld; | |
744626da | 1597 | hda_nid_t pin_nid = per_pin->pin_nid; |
5d44f927 SW |
1598 | /* |
1599 | * Always execute a GetPinSense verb here, even when called from | |
1600 | * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited | |
1601 | * response's PD bit is not the real PD value, but indicates that | |
1602 | * the real PD value changed. An older version of the HD-audio | |
1603 | * specification worked this way. Hence, we just ignore the data in | |
1604 | * the unsolicited response to avoid custom WARs. | |
1605 | */ | |
da4a7a39 | 1606 | int present; |
efe47108 | 1607 | bool ret; |
9a5e5234 | 1608 | bool do_repoll = false; |
079d88cc | 1609 | |
664c7155 | 1610 | snd_hda_power_up_pm(codec); |
da4a7a39 DH |
1611 | present = snd_hda_pin_sense(codec, pin_nid); |
1612 | ||
a4e9a38b | 1613 | mutex_lock(&per_pin->lock); |
4bd038f9 DH |
1614 | pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE); |
1615 | if (pin_eld->monitor_present) | |
1616 | eld->eld_valid = !!(present & AC_PINSENSE_ELDV); | |
1617 | else | |
1618 | eld->eld_valid = false; | |
079d88cc | 1619 | |
4e76a883 | 1620 | codec_dbg(codec, |
384a48d7 | 1621 | "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n", |
10250911 | 1622 | codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid); |
5d44f927 | 1623 | |
4bd038f9 | 1624 | if (eld->eld_valid) { |
307229d2 | 1625 | if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer, |
1613d6b4 | 1626 | &eld->eld_size) < 0) |
4bd038f9 | 1627 | eld->eld_valid = false; |
1613d6b4 | 1628 | else { |
79514d47 | 1629 | if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer, |
1613d6b4 | 1630 | eld->eld_size) < 0) |
4bd038f9 | 1631 | eld->eld_valid = false; |
1613d6b4 | 1632 | } |
9a5e5234 TI |
1633 | if (!eld->eld_valid && repoll) |
1634 | do_repoll = true; | |
744626da | 1635 | } |
4bd038f9 | 1636 | |
9a5e5234 | 1637 | if (do_repoll) |
e90247f9 TI |
1638 | schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300)); |
1639 | else | |
1640 | update_eld(codec, per_pin, eld); | |
92c69e79 | 1641 | |
aff747eb | 1642 | ret = !repoll || !pin_eld->monitor_present || pin_eld->eld_valid; |
464837a7 DH |
1643 | |
1644 | jack = snd_hda_jack_tbl_get(codec, pin_nid); | |
1645 | if (jack) | |
1646 | jack->block_report = !ret; | |
1647 | ||
a4e9a38b | 1648 | mutex_unlock(&per_pin->lock); |
664c7155 | 1649 | snd_hda_power_down_pm(codec); |
efe47108 | 1650 | return ret; |
079d88cc WF |
1651 | } |
1652 | ||
744626da WF |
1653 | static void hdmi_repoll_eld(struct work_struct *work) |
1654 | { | |
1655 | struct hdmi_spec_per_pin *per_pin = | |
1656 | container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work); | |
1657 | ||
c6e8453e WF |
1658 | if (per_pin->repoll_count++ > 6) |
1659 | per_pin->repoll_count = 0; | |
1660 | ||
efe47108 TI |
1661 | if (hdmi_present_sense(per_pin, per_pin->repoll_count)) |
1662 | snd_hda_jack_report_sync(per_pin->codec); | |
744626da WF |
1663 | } |
1664 | ||
c88d4e84 TI |
1665 | static void intel_haswell_fixup_connect_list(struct hda_codec *codec, |
1666 | hda_nid_t nid); | |
1667 | ||
079d88cc WF |
1668 | static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid) |
1669 | { | |
1670 | struct hdmi_spec *spec = codec->spec; | |
384a48d7 SW |
1671 | unsigned int caps, config; |
1672 | int pin_idx; | |
1673 | struct hdmi_spec_per_pin *per_pin; | |
07acecc1 | 1674 | int err; |
079d88cc | 1675 | |
efc2f8de | 1676 | caps = snd_hda_query_pin_caps(codec, pin_nid); |
384a48d7 SW |
1677 | if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP))) |
1678 | return 0; | |
1679 | ||
efc2f8de | 1680 | config = snd_hda_codec_get_pincfg(codec, pin_nid); |
384a48d7 SW |
1681 | if (get_defcfg_connect(config) == AC_JACK_PORT_NONE) |
1682 | return 0; | |
1683 | ||
75dcbe4d | 1684 | if (is_haswell_plus(codec)) |
c88d4e84 TI |
1685 | intel_haswell_fixup_connect_list(codec, pin_nid); |
1686 | ||
384a48d7 | 1687 | pin_idx = spec->num_pins; |
bce0d2a8 TI |
1688 | per_pin = snd_array_new(&spec->pins); |
1689 | if (!per_pin) | |
1690 | return -ENOMEM; | |
384a48d7 SW |
1691 | |
1692 | per_pin->pin_nid = pin_nid; | |
1a6003b5 | 1693 | per_pin->non_pcm = false; |
079d88cc | 1694 | |
384a48d7 SW |
1695 | err = hdmi_read_pin_conn(codec, pin_idx); |
1696 | if (err < 0) | |
1697 | return err; | |
079d88cc | 1698 | |
079d88cc WF |
1699 | spec->num_pins++; |
1700 | ||
384a48d7 | 1701 | return 0; |
079d88cc WF |
1702 | } |
1703 | ||
384a48d7 | 1704 | static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) |
079d88cc WF |
1705 | { |
1706 | struct hdmi_spec *spec = codec->spec; | |
384a48d7 SW |
1707 | struct hdmi_spec_per_cvt *per_cvt; |
1708 | unsigned int chans; | |
1709 | int err; | |
079d88cc | 1710 | |
384a48d7 SW |
1711 | chans = get_wcaps(codec, cvt_nid); |
1712 | chans = get_wcaps_channels(chans); | |
1713 | ||
bce0d2a8 TI |
1714 | per_cvt = snd_array_new(&spec->cvts); |
1715 | if (!per_cvt) | |
1716 | return -ENOMEM; | |
384a48d7 SW |
1717 | |
1718 | per_cvt->cvt_nid = cvt_nid; | |
1719 | per_cvt->channels_min = 2; | |
d45e6889 | 1720 | if (chans <= 16) { |
384a48d7 | 1721 | per_cvt->channels_max = chans; |
d45e6889 TI |
1722 | if (chans > spec->channels_max) |
1723 | spec->channels_max = chans; | |
1724 | } | |
384a48d7 SW |
1725 | |
1726 | err = snd_hda_query_supported_pcm(codec, cvt_nid, | |
1727 | &per_cvt->rates, | |
1728 | &per_cvt->formats, | |
1729 | &per_cvt->maxbps); | |
1730 | if (err < 0) | |
1731 | return err; | |
1732 | ||
bce0d2a8 TI |
1733 | if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids)) |
1734 | spec->cvt_nids[spec->num_cvts] = cvt_nid; | |
1735 | spec->num_cvts++; | |
079d88cc WF |
1736 | |
1737 | return 0; | |
1738 | } | |
1739 | ||
1740 | static int hdmi_parse_codec(struct hda_codec *codec) | |
1741 | { | |
1742 | hda_nid_t nid; | |
1743 | int i, nodes; | |
1744 | ||
7639a06c | 1745 | nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid); |
079d88cc | 1746 | if (!nid || nodes < 0) { |
4e76a883 | 1747 | codec_warn(codec, "HDMI: failed to get afg sub nodes\n"); |
079d88cc WF |
1748 | return -EINVAL; |
1749 | } | |
1750 | ||
1751 | for (i = 0; i < nodes; i++, nid++) { | |
1752 | unsigned int caps; | |
1753 | unsigned int type; | |
1754 | ||
efc2f8de | 1755 | caps = get_wcaps(codec, nid); |
079d88cc WF |
1756 | type = get_wcaps_type(caps); |
1757 | ||
1758 | if (!(caps & AC_WCAP_DIGITAL)) | |
1759 | continue; | |
1760 | ||
1761 | switch (type) { | |
1762 | case AC_WID_AUD_OUT: | |
384a48d7 | 1763 | hdmi_add_cvt(codec, nid); |
079d88cc WF |
1764 | break; |
1765 | case AC_WID_PIN: | |
3eaead57 | 1766 | hdmi_add_pin(codec, nid); |
079d88cc WF |
1767 | break; |
1768 | } | |
1769 | } | |
1770 | ||
079d88cc WF |
1771 | return 0; |
1772 | } | |
1773 | ||
84eb01be TI |
1774 | /* |
1775 | */ | |
1a6003b5 TI |
1776 | static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) |
1777 | { | |
1778 | struct hda_spdif_out *spdif; | |
1779 | bool non_pcm; | |
1780 | ||
1781 | mutex_lock(&codec->spdif_mutex); | |
1782 | spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid); | |
1783 | non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO); | |
1784 | mutex_unlock(&codec->spdif_mutex); | |
1785 | return non_pcm; | |
1786 | } | |
1787 | ||
ddd621fb LY |
1788 | /* There is a fixed mapping between audio pin node and display port |
1789 | * on current Intel platforms: | |
1790 | * Pin Widget 5 - PORT B (port = 1 in i915 driver) | |
1791 | * Pin Widget 6 - PORT C (port = 2 in i915 driver) | |
1792 | * Pin Widget 7 - PORT D (port = 3 in i915 driver) | |
1793 | */ | |
1794 | static int intel_pin2port(hda_nid_t pin_nid) | |
1795 | { | |
1796 | return pin_nid - 4; | |
1797 | } | |
1a6003b5 | 1798 | |
84eb01be TI |
1799 | /* |
1800 | * HDMI callbacks | |
1801 | */ | |
1802 | ||
1803 | static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo, | |
1804 | struct hda_codec *codec, | |
1805 | unsigned int stream_tag, | |
1806 | unsigned int format, | |
1807 | struct snd_pcm_substream *substream) | |
1808 | { | |
384a48d7 SW |
1809 | hda_nid_t cvt_nid = hinfo->nid; |
1810 | struct hdmi_spec *spec = codec->spec; | |
4e76a883 | 1811 | int pin_idx = hinfo_to_pin_index(codec, hinfo); |
b054087d TI |
1812 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); |
1813 | hda_nid_t pin_nid = per_pin->pin_nid; | |
ddd621fb LY |
1814 | struct snd_pcm_runtime *runtime = substream->runtime; |
1815 | struct i915_audio_component *acomp = codec->bus->core.audio_component; | |
1a6003b5 | 1816 | bool non_pcm; |
75fae117 | 1817 | int pinctl; |
1a6003b5 | 1818 | |
ca2e7224 | 1819 | if (is_haswell_plus(codec) || is_valleyview_plus(codec)) { |
2df6742f ML |
1820 | /* Verify pin:cvt selections to avoid silent audio after S3. |
1821 | * After S3, the audio driver restores pin:cvt selections | |
1822 | * but this can happen before gfx is ready and such selection | |
1823 | * is overlooked by HW. Thus multiple pins can share a same | |
1824 | * default convertor and mute control will affect each other, | |
1825 | * which can cause a resumed audio playback become silent | |
1826 | * after S3. | |
1827 | */ | |
1828 | intel_verify_pin_cvt_connect(codec, per_pin); | |
1829 | intel_not_share_assigned_cvt(codec, pin_nid, per_pin->mux_idx); | |
1830 | } | |
1831 | ||
ddd621fb LY |
1832 | /* Call sync_audio_rate to set the N/CTS/M manually if necessary */ |
1833 | /* Todo: add DP1.2 MST audio support later */ | |
1834 | if (acomp && acomp->ops && acomp->ops->sync_audio_rate) | |
1835 | acomp->ops->sync_audio_rate(acomp->dev, | |
1836 | intel_pin2port(pin_nid), | |
1837 | runtime->rate); | |
1838 | ||
1a6003b5 | 1839 | non_pcm = check_non_pcm_per_cvt(codec, cvt_nid); |
a4e9a38b | 1840 | mutex_lock(&per_pin->lock); |
b054087d TI |
1841 | per_pin->channels = substream->runtime->channels; |
1842 | per_pin->setup = true; | |
384a48d7 | 1843 | |
b054087d | 1844 | hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); |
a4e9a38b | 1845 | mutex_unlock(&per_pin->lock); |
84eb01be | 1846 | |
75fae117 SW |
1847 | if (spec->dyn_pin_out) { |
1848 | pinctl = snd_hda_codec_read(codec, pin_nid, 0, | |
1849 | AC_VERB_GET_PIN_WIDGET_CONTROL, 0); | |
1850 | snd_hda_codec_write(codec, pin_nid, 0, | |
1851 | AC_VERB_SET_PIN_WIDGET_CONTROL, | |
1852 | pinctl | PIN_OUT); | |
1853 | } | |
1854 | ||
307229d2 | 1855 | return spec->ops.setup_stream(codec, cvt_nid, pin_nid, stream_tag, format); |
84eb01be TI |
1856 | } |
1857 | ||
8dfaa573 TI |
1858 | static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, |
1859 | struct hda_codec *codec, | |
1860 | struct snd_pcm_substream *substream) | |
1861 | { | |
1862 | snd_hda_codec_cleanup_stream(codec, hinfo->nid); | |
1863 | return 0; | |
1864 | } | |
1865 | ||
f2ad24fa TI |
1866 | static int hdmi_pcm_close(struct hda_pcm_stream *hinfo, |
1867 | struct hda_codec *codec, | |
1868 | struct snd_pcm_substream *substream) | |
384a48d7 SW |
1869 | { |
1870 | struct hdmi_spec *spec = codec->spec; | |
1871 | int cvt_idx, pin_idx; | |
1872 | struct hdmi_spec_per_cvt *per_cvt; | |
1873 | struct hdmi_spec_per_pin *per_pin; | |
75fae117 | 1874 | int pinctl; |
384a48d7 | 1875 | |
384a48d7 | 1876 | if (hinfo->nid) { |
4e76a883 | 1877 | cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid); |
384a48d7 SW |
1878 | if (snd_BUG_ON(cvt_idx < 0)) |
1879 | return -EINVAL; | |
bce0d2a8 | 1880 | per_cvt = get_cvt(spec, cvt_idx); |
384a48d7 SW |
1881 | |
1882 | snd_BUG_ON(!per_cvt->assigned); | |
1883 | per_cvt->assigned = 0; | |
1884 | hinfo->nid = 0; | |
1885 | ||
4e76a883 | 1886 | pin_idx = hinfo_to_pin_index(codec, hinfo); |
384a48d7 SW |
1887 | if (snd_BUG_ON(pin_idx < 0)) |
1888 | return -EINVAL; | |
bce0d2a8 | 1889 | per_pin = get_pin(spec, pin_idx); |
384a48d7 | 1890 | |
75fae117 SW |
1891 | if (spec->dyn_pin_out) { |
1892 | pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, | |
1893 | AC_VERB_GET_PIN_WIDGET_CONTROL, 0); | |
1894 | snd_hda_codec_write(codec, per_pin->pin_nid, 0, | |
1895 | AC_VERB_SET_PIN_WIDGET_CONTROL, | |
1896 | pinctl & ~PIN_OUT); | |
1897 | } | |
1898 | ||
384a48d7 | 1899 | snd_hda_spdif_ctls_unassign(codec, pin_idx); |
cbbaa603 | 1900 | |
a4e9a38b | 1901 | mutex_lock(&per_pin->lock); |
d45e6889 TI |
1902 | per_pin->chmap_set = false; |
1903 | memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); | |
b054087d TI |
1904 | |
1905 | per_pin->setup = false; | |
1906 | per_pin->channels = 0; | |
a4e9a38b | 1907 | mutex_unlock(&per_pin->lock); |
384a48d7 | 1908 | } |
d45e6889 | 1909 | |
384a48d7 SW |
1910 | return 0; |
1911 | } | |
1912 | ||
1913 | static const struct hda_pcm_ops generic_ops = { | |
1914 | .open = hdmi_pcm_open, | |
f2ad24fa | 1915 | .close = hdmi_pcm_close, |
384a48d7 | 1916 | .prepare = generic_hdmi_playback_pcm_prepare, |
8dfaa573 | 1917 | .cleanup = generic_hdmi_playback_pcm_cleanup, |
84eb01be TI |
1918 | }; |
1919 | ||
d45e6889 TI |
1920 | /* |
1921 | * ALSA API channel-map control callbacks | |
1922 | */ | |
1923 | static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol, | |
1924 | struct snd_ctl_elem_info *uinfo) | |
1925 | { | |
1926 | struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol); | |
1927 | struct hda_codec *codec = info->private_data; | |
1928 | struct hdmi_spec *spec = codec->spec; | |
1929 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; | |
1930 | uinfo->count = spec->channels_max; | |
1931 | uinfo->value.integer.min = 0; | |
1932 | uinfo->value.integer.max = SNDRV_CHMAP_LAST; | |
1933 | return 0; | |
1934 | } | |
1935 | ||
307229d2 AH |
1936 | static int hdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap, |
1937 | int channels) | |
1938 | { | |
1939 | /* If the speaker allocation matches the channel count, it is OK.*/ | |
1940 | if (cap->channels != channels) | |
1941 | return -1; | |
1942 | ||
1943 | /* all channels are remappable freely */ | |
1944 | return SNDRV_CTL_TLVT_CHMAP_VAR; | |
1945 | } | |
1946 | ||
1947 | static void hdmi_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap, | |
1948 | unsigned int *chmap, int channels) | |
1949 | { | |
1950 | int count = 0; | |
1951 | int c; | |
1952 | ||
1953 | for (c = 7; c >= 0; c--) { | |
1954 | int spk = cap->speakers[c]; | |
1955 | if (!spk) | |
1956 | continue; | |
1957 | ||
1958 | chmap[count++] = spk_to_chmap(spk); | |
1959 | } | |
1960 | ||
1961 | WARN_ON(count != channels); | |
1962 | } | |
1963 | ||
d45e6889 TI |
1964 | static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag, |
1965 | unsigned int size, unsigned int __user *tlv) | |
1966 | { | |
1967 | struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol); | |
1968 | struct hda_codec *codec = info->private_data; | |
1969 | struct hdmi_spec *spec = codec->spec; | |
d45e6889 TI |
1970 | unsigned int __user *dst; |
1971 | int chs, count = 0; | |
1972 | ||
1973 | if (size < 8) | |
1974 | return -ENOMEM; | |
1975 | if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv)) | |
1976 | return -EFAULT; | |
1977 | size -= 8; | |
1978 | dst = tlv + 2; | |
498dab3a | 1979 | for (chs = 2; chs <= spec->channels_max; chs++) { |
307229d2 | 1980 | int i; |
d45e6889 TI |
1981 | struct cea_channel_speaker_allocation *cap; |
1982 | cap = channel_allocations; | |
1983 | for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) { | |
1984 | int chs_bytes = chs * 4; | |
307229d2 AH |
1985 | int type = spec->ops.chmap_cea_alloc_validate_get_type(cap, chs); |
1986 | unsigned int tlv_chmap[8]; | |
1987 | ||
1988 | if (type < 0) | |
d45e6889 | 1989 | continue; |
d45e6889 TI |
1990 | if (size < 8) |
1991 | return -ENOMEM; | |
307229d2 | 1992 | if (put_user(type, dst) || |
d45e6889 TI |
1993 | put_user(chs_bytes, dst + 1)) |
1994 | return -EFAULT; | |
1995 | dst += 2; | |
1996 | size -= 8; | |
1997 | count += 8; | |
1998 | if (size < chs_bytes) | |
1999 | return -ENOMEM; | |
2000 | size -= chs_bytes; | |
2001 | count += chs_bytes; | |
307229d2 AH |
2002 | spec->ops.cea_alloc_to_tlv_chmap(cap, tlv_chmap, chs); |
2003 | if (copy_to_user(dst, tlv_chmap, chs_bytes)) | |
2004 | return -EFAULT; | |
2005 | dst += chs; | |
d45e6889 TI |
2006 | } |
2007 | } | |
2008 | if (put_user(count, tlv + 1)) | |
2009 | return -EFAULT; | |
2010 | return 0; | |
2011 | } | |
2012 | ||
2013 | static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol, | |
2014 | struct snd_ctl_elem_value *ucontrol) | |
2015 | { | |
2016 | struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol); | |
2017 | struct hda_codec *codec = info->private_data; | |
2018 | struct hdmi_spec *spec = codec->spec; | |
2019 | int pin_idx = kcontrol->private_value; | |
bce0d2a8 | 2020 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); |
d45e6889 TI |
2021 | int i; |
2022 | ||
2023 | for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++) | |
2024 | ucontrol->value.integer.value[i] = per_pin->chmap[i]; | |
2025 | return 0; | |
2026 | } | |
2027 | ||
2028 | static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol, | |
2029 | struct snd_ctl_elem_value *ucontrol) | |
2030 | { | |
2031 | struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol); | |
2032 | struct hda_codec *codec = info->private_data; | |
2033 | struct hdmi_spec *spec = codec->spec; | |
2034 | int pin_idx = kcontrol->private_value; | |
bce0d2a8 | 2035 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); |
d45e6889 TI |
2036 | unsigned int ctl_idx; |
2037 | struct snd_pcm_substream *substream; | |
2038 | unsigned char chmap[8]; | |
307229d2 | 2039 | int i, err, ca, prepared = 0; |
d45e6889 TI |
2040 | |
2041 | ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); | |
2042 | substream = snd_pcm_chmap_substream(info, ctl_idx); | |
2043 | if (!substream || !substream->runtime) | |
6f54c361 | 2044 | return 0; /* just for avoiding error from alsactl restore */ |
d45e6889 TI |
2045 | switch (substream->runtime->status->state) { |
2046 | case SNDRV_PCM_STATE_OPEN: | |
2047 | case SNDRV_PCM_STATE_SETUP: | |
2048 | break; | |
2049 | case SNDRV_PCM_STATE_PREPARED: | |
2050 | prepared = 1; | |
2051 | break; | |
2052 | default: | |
2053 | return -EBUSY; | |
2054 | } | |
2055 | memset(chmap, 0, sizeof(chmap)); | |
2056 | for (i = 0; i < ARRAY_SIZE(chmap); i++) | |
2057 | chmap[i] = ucontrol->value.integer.value[i]; | |
2058 | if (!memcmp(chmap, per_pin->chmap, sizeof(chmap))) | |
2059 | return 0; | |
2060 | ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap); | |
2061 | if (ca < 0) | |
2062 | return -EINVAL; | |
307229d2 AH |
2063 | if (spec->ops.chmap_validate) { |
2064 | err = spec->ops.chmap_validate(ca, ARRAY_SIZE(chmap), chmap); | |
2065 | if (err) | |
2066 | return err; | |
2067 | } | |
a4e9a38b | 2068 | mutex_lock(&per_pin->lock); |
d45e6889 TI |
2069 | per_pin->chmap_set = true; |
2070 | memcpy(per_pin->chmap, chmap, sizeof(chmap)); | |
2071 | if (prepared) | |
b054087d | 2072 | hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); |
a4e9a38b | 2073 | mutex_unlock(&per_pin->lock); |
d45e6889 TI |
2074 | |
2075 | return 0; | |
2076 | } | |
2077 | ||
84eb01be TI |
2078 | static int generic_hdmi_build_pcms(struct hda_codec *codec) |
2079 | { | |
2080 | struct hdmi_spec *spec = codec->spec; | |
384a48d7 | 2081 | int pin_idx; |
84eb01be | 2082 | |
384a48d7 SW |
2083 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { |
2084 | struct hda_pcm *info; | |
84eb01be | 2085 | struct hda_pcm_stream *pstr; |
bce0d2a8 | 2086 | |
bbbc7e85 | 2087 | info = snd_hda_codec_pcm_new(codec, "HDMI %d", pin_idx); |
bce0d2a8 TI |
2088 | if (!info) |
2089 | return -ENOMEM; | |
bbbc7e85 | 2090 | spec->pcm_rec[pin_idx] = info; |
84eb01be | 2091 | info->pcm_type = HDA_PCM_TYPE_HDMI; |
d45e6889 | 2092 | info->own_chmap = true; |
384a48d7 | 2093 | |
84eb01be | 2094 | pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; |
384a48d7 SW |
2095 | pstr->substreams = 1; |
2096 | pstr->ops = generic_ops; | |
2097 | /* other pstr fields are set in open */ | |
84eb01be TI |
2098 | } |
2099 | ||
2100 | return 0; | |
2101 | } | |
2102 | ||
0b6c49b5 DH |
2103 | static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx) |
2104 | { | |
31ef2257 | 2105 | char hdmi_str[32] = "HDMI/DP"; |
0b6c49b5 | 2106 | struct hdmi_spec *spec = codec->spec; |
bce0d2a8 TI |
2107 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); |
2108 | int pcmdev = get_pcm_rec(spec, pin_idx)->device; | |
909cadc6 | 2109 | bool phantom_jack; |
0b6c49b5 | 2110 | |
31ef2257 TI |
2111 | if (pcmdev > 0) |
2112 | sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev); | |
909cadc6 TI |
2113 | phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid); |
2114 | if (phantom_jack) | |
30efd8de DH |
2115 | strncat(hdmi_str, " Phantom", |
2116 | sizeof(hdmi_str) - strlen(hdmi_str) - 1); | |
0b6c49b5 | 2117 | |
909cadc6 TI |
2118 | return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, |
2119 | phantom_jack); | |
0b6c49b5 DH |
2120 | } |
2121 | ||
84eb01be TI |
2122 | static int generic_hdmi_build_controls(struct hda_codec *codec) |
2123 | { | |
2124 | struct hdmi_spec *spec = codec->spec; | |
2125 | int err; | |
384a48d7 | 2126 | int pin_idx; |
84eb01be | 2127 | |
384a48d7 | 2128 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { |
bce0d2a8 | 2129 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); |
0b6c49b5 DH |
2130 | |
2131 | err = generic_hdmi_build_jack(codec, pin_idx); | |
2132 | if (err < 0) | |
2133 | return err; | |
2134 | ||
dcda5806 TI |
2135 | err = snd_hda_create_dig_out_ctls(codec, |
2136 | per_pin->pin_nid, | |
2137 | per_pin->mux_nids[0], | |
2138 | HDA_PCM_TYPE_HDMI); | |
84eb01be TI |
2139 | if (err < 0) |
2140 | return err; | |
384a48d7 | 2141 | snd_hda_spdif_ctls_unassign(codec, pin_idx); |
14bc52b8 PLB |
2142 | |
2143 | /* add control for ELD Bytes */ | |
bce0d2a8 TI |
2144 | err = hdmi_create_eld_ctl(codec, pin_idx, |
2145 | get_pcm_rec(spec, pin_idx)->device); | |
14bc52b8 PLB |
2146 | |
2147 | if (err < 0) | |
2148 | return err; | |
31ef2257 | 2149 | |
82b1d73f | 2150 | hdmi_present_sense(per_pin, 0); |
84eb01be TI |
2151 | } |
2152 | ||
d45e6889 TI |
2153 | /* add channel maps */ |
2154 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { | |
bbbc7e85 | 2155 | struct hda_pcm *pcm; |
d45e6889 TI |
2156 | struct snd_pcm_chmap *chmap; |
2157 | struct snd_kcontrol *kctl; | |
2158 | int i; | |
2ca320e2 | 2159 | |
bbbc7e85 TI |
2160 | pcm = spec->pcm_rec[pin_idx]; |
2161 | if (!pcm || !pcm->pcm) | |
2ca320e2 | 2162 | break; |
bbbc7e85 | 2163 | err = snd_pcm_add_chmap_ctls(pcm->pcm, |
d45e6889 TI |
2164 | SNDRV_PCM_STREAM_PLAYBACK, |
2165 | NULL, 0, pin_idx, &chmap); | |
2166 | if (err < 0) | |
2167 | return err; | |
2168 | /* override handlers */ | |
2169 | chmap->private_data = codec; | |
2170 | kctl = chmap->kctl; | |
2171 | for (i = 0; i < kctl->count; i++) | |
2172 | kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE; | |
2173 | kctl->info = hdmi_chmap_ctl_info; | |
2174 | kctl->get = hdmi_chmap_ctl_get; | |
2175 | kctl->put = hdmi_chmap_ctl_put; | |
2176 | kctl->tlv.c = hdmi_chmap_ctl_tlv; | |
2177 | } | |
2178 | ||
84eb01be TI |
2179 | return 0; |
2180 | } | |
2181 | ||
8b8d654b | 2182 | static int generic_hdmi_init_per_pins(struct hda_codec *codec) |
84eb01be TI |
2183 | { |
2184 | struct hdmi_spec *spec = codec->spec; | |
384a48d7 SW |
2185 | int pin_idx; |
2186 | ||
2187 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { | |
bce0d2a8 | 2188 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); |
84eb01be | 2189 | |
744626da | 2190 | per_pin->codec = codec; |
a4e9a38b | 2191 | mutex_init(&per_pin->lock); |
744626da | 2192 | INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld); |
a4e9a38b | 2193 | eld_proc_new(per_pin, pin_idx); |
84eb01be | 2194 | } |
8b8d654b TI |
2195 | return 0; |
2196 | } | |
2197 | ||
2198 | static int generic_hdmi_init(struct hda_codec *codec) | |
2199 | { | |
2200 | struct hdmi_spec *spec = codec->spec; | |
2201 | int pin_idx; | |
2202 | ||
2203 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { | |
bce0d2a8 | 2204 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); |
8b8d654b TI |
2205 | hda_nid_t pin_nid = per_pin->pin_nid; |
2206 | ||
2207 | hdmi_init_pin(codec, pin_nid); | |
62f949bf | 2208 | snd_hda_jack_detect_enable_callback(codec, pin_nid, |
20ce9029 | 2209 | codec->jackpoll_interval > 0 ? jack_callback : NULL); |
8b8d654b | 2210 | } |
84eb01be TI |
2211 | return 0; |
2212 | } | |
2213 | ||
bce0d2a8 TI |
2214 | static void hdmi_array_init(struct hdmi_spec *spec, int nums) |
2215 | { | |
2216 | snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums); | |
2217 | snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums); | |
bce0d2a8 TI |
2218 | } |
2219 | ||
2220 | static void hdmi_array_free(struct hdmi_spec *spec) | |
2221 | { | |
2222 | snd_array_free(&spec->pins); | |
2223 | snd_array_free(&spec->cvts); | |
bce0d2a8 TI |
2224 | } |
2225 | ||
84eb01be TI |
2226 | static void generic_hdmi_free(struct hda_codec *codec) |
2227 | { | |
2228 | struct hdmi_spec *spec = codec->spec; | |
384a48d7 SW |
2229 | int pin_idx; |
2230 | ||
6603249d | 2231 | if (codec_has_acomp(codec)) |
25adc137 DH |
2232 | snd_hdac_i915_register_notifier(NULL); |
2233 | ||
384a48d7 | 2234 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { |
bce0d2a8 | 2235 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); |
84eb01be | 2236 | |
2f35c630 | 2237 | cancel_delayed_work_sync(&per_pin->work); |
a4e9a38b | 2238 | eld_proc_free(per_pin); |
384a48d7 | 2239 | } |
84eb01be | 2240 | |
55913110 TI |
2241 | if (spec->i915_bound) |
2242 | snd_hdac_i915_exit(&codec->bus->core); | |
bce0d2a8 | 2243 | hdmi_array_free(spec); |
84eb01be TI |
2244 | kfree(spec); |
2245 | } | |
2246 | ||
28cb72e5 WX |
2247 | #ifdef CONFIG_PM |
2248 | static int generic_hdmi_resume(struct hda_codec *codec) | |
2249 | { | |
2250 | struct hdmi_spec *spec = codec->spec; | |
2251 | int pin_idx; | |
2252 | ||
a2833683 | 2253 | codec->patch_ops.init(codec); |
eeecd9d1 | 2254 | regcache_sync(codec->core.regmap); |
28cb72e5 WX |
2255 | |
2256 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { | |
2257 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); | |
2258 | hdmi_present_sense(per_pin, 1); | |
2259 | } | |
2260 | return 0; | |
2261 | } | |
2262 | #endif | |
2263 | ||
fb79e1e0 | 2264 | static const struct hda_codec_ops generic_hdmi_patch_ops = { |
84eb01be TI |
2265 | .init = generic_hdmi_init, |
2266 | .free = generic_hdmi_free, | |
2267 | .build_pcms = generic_hdmi_build_pcms, | |
2268 | .build_controls = generic_hdmi_build_controls, | |
2269 | .unsol_event = hdmi_unsol_event, | |
28cb72e5 WX |
2270 | #ifdef CONFIG_PM |
2271 | .resume = generic_hdmi_resume, | |
2272 | #endif | |
84eb01be TI |
2273 | }; |
2274 | ||
307229d2 AH |
2275 | static const struct hdmi_ops generic_standard_hdmi_ops = { |
2276 | .pin_get_eld = snd_hdmi_get_eld, | |
2277 | .pin_get_slot_channel = hdmi_pin_get_slot_channel, | |
2278 | .pin_set_slot_channel = hdmi_pin_set_slot_channel, | |
2279 | .pin_setup_infoframe = hdmi_pin_setup_infoframe, | |
2280 | .pin_hbr_setup = hdmi_pin_hbr_setup, | |
2281 | .setup_stream = hdmi_setup_stream, | |
2282 | .chmap_cea_alloc_validate_get_type = hdmi_chmap_cea_alloc_validate_get_type, | |
2283 | .cea_alloc_to_tlv_chmap = hdmi_cea_alloc_to_tlv_chmap, | |
2284 | }; | |
2285 | ||
6ffe168f | 2286 | |
c88d4e84 TI |
2287 | static void intel_haswell_fixup_connect_list(struct hda_codec *codec, |
2288 | hda_nid_t nid) | |
2289 | { | |
2290 | struct hdmi_spec *spec = codec->spec; | |
2291 | hda_nid_t conns[4]; | |
2292 | int nconns; | |
6ffe168f | 2293 | |
c88d4e84 TI |
2294 | nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns)); |
2295 | if (nconns == spec->num_cvts && | |
2296 | !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t))) | |
6ffe168f ML |
2297 | return; |
2298 | ||
c88d4e84 | 2299 | /* override pins connection list */ |
4e76a883 | 2300 | codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid); |
c88d4e84 | 2301 | snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids); |
6ffe168f ML |
2302 | } |
2303 | ||
1611a9c9 ML |
2304 | #define INTEL_VENDOR_NID 0x08 |
2305 | #define INTEL_GET_VENDOR_VERB 0xf81 | |
2306 | #define INTEL_SET_VENDOR_VERB 0x781 | |
2307 | #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */ | |
2308 | #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */ | |
2309 | ||
2310 | static void intel_haswell_enable_all_pins(struct hda_codec *codec, | |
17df3f55 | 2311 | bool update_tree) |
1611a9c9 ML |
2312 | { |
2313 | unsigned int vendor_param; | |
2314 | ||
1611a9c9 ML |
2315 | vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0, |
2316 | INTEL_GET_VENDOR_VERB, 0); | |
2317 | if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS) | |
2318 | return; | |
2319 | ||
2320 | vendor_param |= INTEL_EN_ALL_PIN_CVTS; | |
2321 | vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0, | |
2322 | INTEL_SET_VENDOR_VERB, vendor_param); | |
2323 | if (vendor_param == -1) | |
2324 | return; | |
2325 | ||
17df3f55 TI |
2326 | if (update_tree) |
2327 | snd_hda_codec_update_widgets(codec); | |
1611a9c9 ML |
2328 | } |
2329 | ||
c88d4e84 TI |
2330 | static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec) |
2331 | { | |
2332 | unsigned int vendor_param; | |
2333 | ||
2334 | vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0, | |
2335 | INTEL_GET_VENDOR_VERB, 0); | |
2336 | if (vendor_param == -1 || vendor_param & INTEL_EN_DP12) | |
2337 | return; | |
2338 | ||
2339 | /* enable DP1.2 mode */ | |
2340 | vendor_param |= INTEL_EN_DP12; | |
a551d914 | 2341 | snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB); |
c88d4e84 TI |
2342 | snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0, |
2343 | INTEL_SET_VENDOR_VERB, vendor_param); | |
2344 | } | |
2345 | ||
17df3f55 TI |
2346 | /* Haswell needs to re-issue the vendor-specific verbs before turning to D0. |
2347 | * Otherwise you may get severe h/w communication errors. | |
2348 | */ | |
2349 | static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg, | |
2350 | unsigned int power_state) | |
2351 | { | |
2352 | if (power_state == AC_PWRST_D0) { | |
2353 | intel_haswell_enable_all_pins(codec, false); | |
2354 | intel_haswell_fixup_enable_dp12(codec); | |
2355 | } | |
c88d4e84 | 2356 | |
17df3f55 TI |
2357 | snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state); |
2358 | snd_hda_codec_set_power_to_all(codec, fg, power_state); | |
2359 | } | |
6ffe168f | 2360 | |
f0675d4a | 2361 | static void intel_pin_eld_notify(void *audio_ptr, int port) |
25adc137 DH |
2362 | { |
2363 | struct hda_codec *codec = audio_ptr; | |
2364 | int pin_nid = port + 0x04; | |
2365 | ||
8ae743e8 TI |
2366 | /* skip notification during system suspend (but not in runtime PM); |
2367 | * the state will be updated at resume | |
2368 | */ | |
2369 | if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0) | |
2370 | return; | |
eb399d3c TI |
2371 | /* ditto during suspend/resume process itself */ |
2372 | if (atomic_read(&(codec)->core.in_pm)) | |
2373 | return; | |
8ae743e8 | 2374 | |
25adc137 DH |
2375 | check_presence_and_report(codec, pin_nid); |
2376 | } | |
2377 | ||
84eb01be TI |
2378 | static int patch_generic_hdmi(struct hda_codec *codec) |
2379 | { | |
2380 | struct hdmi_spec *spec; | |
84eb01be TI |
2381 | |
2382 | spec = kzalloc(sizeof(*spec), GFP_KERNEL); | |
2383 | if (spec == NULL) | |
2384 | return -ENOMEM; | |
2385 | ||
307229d2 | 2386 | spec->ops = generic_standard_hdmi_ops; |
84eb01be | 2387 | codec->spec = spec; |
bce0d2a8 | 2388 | hdmi_array_init(spec, 4); |
6ffe168f | 2389 | |
55913110 TI |
2390 | /* Try to bind with i915 for any Intel codecs (if not done yet) */ |
2391 | if (!codec_has_acomp(codec) && | |
2392 | (codec->core.vendor_id >> 16) == 0x8086) | |
2393 | if (!snd_hdac_i915_init(&codec->bus->core)) | |
2394 | spec->i915_bound = true; | |
2395 | ||
75dcbe4d | 2396 | if (is_haswell_plus(codec)) { |
17df3f55 | 2397 | intel_haswell_enable_all_pins(codec, true); |
c88d4e84 | 2398 | intel_haswell_fixup_enable_dp12(codec); |
17df3f55 | 2399 | } |
6ffe168f | 2400 | |
2bd1f73f ML |
2401 | /* For Valleyview/Cherryview, only the display codec is in the display |
2402 | * power well and can use link_power ops to request/release the power. | |
2403 | * For Haswell/Broadwell, the controller is also in the power well and | |
2404 | * can cover the codec power request, and so need not set this flag. | |
2405 | * For previous platforms, there is no such power well feature. | |
2406 | */ | |
ff9d8859 LH |
2407 | if (is_valleyview_plus(codec) || is_skylake(codec) || |
2408 | is_broxton(codec)) | |
2bd1f73f ML |
2409 | codec->core.link_power_control = 1; |
2410 | ||
6603249d | 2411 | if (codec_has_acomp(codec)) { |
5b8620bb | 2412 | codec->depop_delay = 0; |
25adc137 DH |
2413 | spec->i915_audio_ops.audio_ptr = codec; |
2414 | spec->i915_audio_ops.pin_eld_notify = intel_pin_eld_notify; | |
2415 | snd_hdac_i915_register_notifier(&spec->i915_audio_ops); | |
2416 | } | |
5b8620bb | 2417 | |
84eb01be | 2418 | if (hdmi_parse_codec(codec) < 0) { |
55913110 TI |
2419 | if (spec->i915_bound) |
2420 | snd_hdac_i915_exit(&codec->bus->core); | |
84eb01be TI |
2421 | codec->spec = NULL; |
2422 | kfree(spec); | |
2423 | return -EINVAL; | |
2424 | } | |
2425 | codec->patch_ops = generic_hdmi_patch_ops; | |
75dcbe4d | 2426 | if (is_haswell_plus(codec)) { |
17df3f55 | 2427 | codec->patch_ops.set_power_state = haswell_set_power_state; |
5dc989bd ML |
2428 | codec->dp_mst = true; |
2429 | } | |
17df3f55 | 2430 | |
2377c3c3 LH |
2431 | /* Enable runtime pm for HDMI audio codec of HSW/BDW/SKL/BYT/BSW */ |
2432 | if (is_haswell_plus(codec) || is_valleyview_plus(codec)) | |
2433 | codec->auto_runtime_pm = 1; | |
2434 | ||
8b8d654b | 2435 | generic_hdmi_init_per_pins(codec); |
84eb01be | 2436 | |
84eb01be TI |
2437 | init_channel_allocations(); |
2438 | ||
2439 | return 0; | |
2440 | } | |
2441 | ||
3aaf8980 SW |
2442 | /* |
2443 | * Shared non-generic implementations | |
2444 | */ | |
2445 | ||
2446 | static int simple_playback_build_pcms(struct hda_codec *codec) | |
2447 | { | |
2448 | struct hdmi_spec *spec = codec->spec; | |
bce0d2a8 | 2449 | struct hda_pcm *info; |
8ceb332d TI |
2450 | unsigned int chans; |
2451 | struct hda_pcm_stream *pstr; | |
bce0d2a8 | 2452 | struct hdmi_spec_per_cvt *per_cvt; |
3aaf8980 | 2453 | |
bce0d2a8 TI |
2454 | per_cvt = get_cvt(spec, 0); |
2455 | chans = get_wcaps(codec, per_cvt->cvt_nid); | |
8ceb332d | 2456 | chans = get_wcaps_channels(chans); |
3aaf8980 | 2457 | |
bbbc7e85 | 2458 | info = snd_hda_codec_pcm_new(codec, "HDMI 0"); |
bce0d2a8 TI |
2459 | if (!info) |
2460 | return -ENOMEM; | |
bbbc7e85 | 2461 | spec->pcm_rec[0] = info; |
8ceb332d TI |
2462 | info->pcm_type = HDA_PCM_TYPE_HDMI; |
2463 | pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; | |
2464 | *pstr = spec->pcm_playback; | |
bce0d2a8 | 2465 | pstr->nid = per_cvt->cvt_nid; |
8ceb332d TI |
2466 | if (pstr->channels_max <= 2 && chans && chans <= 16) |
2467 | pstr->channels_max = chans; | |
3aaf8980 SW |
2468 | |
2469 | return 0; | |
2470 | } | |
2471 | ||
4b6ace9e TI |
2472 | /* unsolicited event for jack sensing */ |
2473 | static void simple_hdmi_unsol_event(struct hda_codec *codec, | |
2474 | unsigned int res) | |
2475 | { | |
9dd8cf12 | 2476 | snd_hda_jack_set_dirty_all(codec); |
4b6ace9e TI |
2477 | snd_hda_jack_report_sync(codec); |
2478 | } | |
2479 | ||
2480 | /* generic_hdmi_build_jack can be used for simple_hdmi, too, | |
2481 | * as long as spec->pins[] is set correctly | |
2482 | */ | |
2483 | #define simple_hdmi_build_jack generic_hdmi_build_jack | |
2484 | ||
3aaf8980 SW |
2485 | static int simple_playback_build_controls(struct hda_codec *codec) |
2486 | { | |
2487 | struct hdmi_spec *spec = codec->spec; | |
bce0d2a8 | 2488 | struct hdmi_spec_per_cvt *per_cvt; |
3aaf8980 | 2489 | int err; |
3aaf8980 | 2490 | |
bce0d2a8 | 2491 | per_cvt = get_cvt(spec, 0); |
c9a6338a AH |
2492 | err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid, |
2493 | per_cvt->cvt_nid, | |
2494 | HDA_PCM_TYPE_HDMI); | |
8ceb332d TI |
2495 | if (err < 0) |
2496 | return err; | |
2497 | return simple_hdmi_build_jack(codec, 0); | |
3aaf8980 SW |
2498 | } |
2499 | ||
4f0110ce TI |
2500 | static int simple_playback_init(struct hda_codec *codec) |
2501 | { | |
2502 | struct hdmi_spec *spec = codec->spec; | |
bce0d2a8 TI |
2503 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0); |
2504 | hda_nid_t pin = per_pin->pin_nid; | |
8ceb332d TI |
2505 | |
2506 | snd_hda_codec_write(codec, pin, 0, | |
2507 | AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT); | |
2508 | /* some codecs require to unmute the pin */ | |
2509 | if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) | |
2510 | snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE, | |
2511 | AMP_OUT_UNMUTE); | |
62f949bf | 2512 | snd_hda_jack_detect_enable(codec, pin); |
4f0110ce TI |
2513 | return 0; |
2514 | } | |
2515 | ||
3aaf8980 SW |
2516 | static void simple_playback_free(struct hda_codec *codec) |
2517 | { | |
2518 | struct hdmi_spec *spec = codec->spec; | |
2519 | ||
bce0d2a8 | 2520 | hdmi_array_free(spec); |
3aaf8980 SW |
2521 | kfree(spec); |
2522 | } | |
2523 | ||
84eb01be TI |
2524 | /* |
2525 | * Nvidia specific implementations | |
2526 | */ | |
2527 | ||
2528 | #define Nv_VERB_SET_Channel_Allocation 0xF79 | |
2529 | #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A | |
2530 | #define Nv_VERB_SET_Audio_Protection_On 0xF98 | |
2531 | #define Nv_VERB_SET_Audio_Protection_Off 0xF99 | |
2532 | ||
2533 | #define nvhdmi_master_con_nid_7x 0x04 | |
2534 | #define nvhdmi_master_pin_nid_7x 0x05 | |
2535 | ||
fb79e1e0 | 2536 | static const hda_nid_t nvhdmi_con_nids_7x[4] = { |
84eb01be TI |
2537 | /*front, rear, clfe, rear_surr */ |
2538 | 0x6, 0x8, 0xa, 0xc, | |
2539 | }; | |
2540 | ||
ceaa86ba TI |
2541 | static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = { |
2542 | /* set audio protect on */ | |
2543 | { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, | |
2544 | /* enable digital output on pin widget */ | |
2545 | { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, | |
2546 | {} /* terminator */ | |
2547 | }; | |
2548 | ||
2549 | static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = { | |
84eb01be TI |
2550 | /* set audio protect on */ |
2551 | { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, | |
2552 | /* enable digital output on pin widget */ | |
2553 | { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, | |
2554 | { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, | |
2555 | { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, | |
2556 | { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, | |
2557 | { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, | |
2558 | {} /* terminator */ | |
2559 | }; | |
2560 | ||
2561 | #ifdef LIMITED_RATE_FMT_SUPPORT | |
2562 | /* support only the safe format and rate */ | |
2563 | #define SUPPORTED_RATES SNDRV_PCM_RATE_48000 | |
2564 | #define SUPPORTED_MAXBPS 16 | |
2565 | #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE | |
2566 | #else | |
2567 | /* support all rates and formats */ | |
2568 | #define SUPPORTED_RATES \ | |
2569 | (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ | |
2570 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\ | |
2571 | SNDRV_PCM_RATE_192000) | |
2572 | #define SUPPORTED_MAXBPS 24 | |
2573 | #define SUPPORTED_FORMATS \ | |
2574 | (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) | |
2575 | #endif | |
2576 | ||
ceaa86ba TI |
2577 | static int nvhdmi_7x_init_2ch(struct hda_codec *codec) |
2578 | { | |
2579 | snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch); | |
2580 | return 0; | |
2581 | } | |
2582 | ||
2583 | static int nvhdmi_7x_init_8ch(struct hda_codec *codec) | |
84eb01be | 2584 | { |
ceaa86ba | 2585 | snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch); |
84eb01be TI |
2586 | return 0; |
2587 | } | |
2588 | ||
393004b2 ND |
2589 | static unsigned int channels_2_6_8[] = { |
2590 | 2, 6, 8 | |
2591 | }; | |
2592 | ||
2593 | static unsigned int channels_2_8[] = { | |
2594 | 2, 8 | |
2595 | }; | |
2596 | ||
2597 | static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = { | |
2598 | .count = ARRAY_SIZE(channels_2_6_8), | |
2599 | .list = channels_2_6_8, | |
2600 | .mask = 0, | |
2601 | }; | |
2602 | ||
2603 | static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = { | |
2604 | .count = ARRAY_SIZE(channels_2_8), | |
2605 | .list = channels_2_8, | |
2606 | .mask = 0, | |
2607 | }; | |
2608 | ||
84eb01be TI |
2609 | static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo, |
2610 | struct hda_codec *codec, | |
2611 | struct snd_pcm_substream *substream) | |
2612 | { | |
2613 | struct hdmi_spec *spec = codec->spec; | |
393004b2 ND |
2614 | struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL; |
2615 | ||
b9a94a9c | 2616 | switch (codec->preset->vendor_id) { |
393004b2 ND |
2617 | case 0x10de0002: |
2618 | case 0x10de0003: | |
2619 | case 0x10de0005: | |
2620 | case 0x10de0006: | |
2621 | hw_constraints_channels = &hw_constraints_2_8_channels; | |
2622 | break; | |
2623 | case 0x10de0007: | |
2624 | hw_constraints_channels = &hw_constraints_2_6_8_channels; | |
2625 | break; | |
2626 | default: | |
2627 | break; | |
2628 | } | |
2629 | ||
2630 | if (hw_constraints_channels != NULL) { | |
2631 | snd_pcm_hw_constraint_list(substream->runtime, 0, | |
2632 | SNDRV_PCM_HW_PARAM_CHANNELS, | |
2633 | hw_constraints_channels); | |
ad09fc9d TI |
2634 | } else { |
2635 | snd_pcm_hw_constraint_step(substream->runtime, 0, | |
2636 | SNDRV_PCM_HW_PARAM_CHANNELS, 2); | |
393004b2 ND |
2637 | } |
2638 | ||
84eb01be TI |
2639 | return snd_hda_multi_out_dig_open(codec, &spec->multiout); |
2640 | } | |
2641 | ||
2642 | static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo, | |
2643 | struct hda_codec *codec, | |
2644 | struct snd_pcm_substream *substream) | |
2645 | { | |
2646 | struct hdmi_spec *spec = codec->spec; | |
2647 | return snd_hda_multi_out_dig_close(codec, &spec->multiout); | |
2648 | } | |
2649 | ||
2650 | static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo, | |
2651 | struct hda_codec *codec, | |
2652 | unsigned int stream_tag, | |
2653 | unsigned int format, | |
2654 | struct snd_pcm_substream *substream) | |
2655 | { | |
2656 | struct hdmi_spec *spec = codec->spec; | |
2657 | return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, | |
2658 | stream_tag, format, substream); | |
2659 | } | |
2660 | ||
d0b1252d TI |
2661 | static const struct hda_pcm_stream simple_pcm_playback = { |
2662 | .substreams = 1, | |
2663 | .channels_min = 2, | |
2664 | .channels_max = 2, | |
2665 | .ops = { | |
2666 | .open = simple_playback_pcm_open, | |
2667 | .close = simple_playback_pcm_close, | |
2668 | .prepare = simple_playback_pcm_prepare | |
2669 | }, | |
2670 | }; | |
2671 | ||
2672 | static const struct hda_codec_ops simple_hdmi_patch_ops = { | |
2673 | .build_controls = simple_playback_build_controls, | |
2674 | .build_pcms = simple_playback_build_pcms, | |
2675 | .init = simple_playback_init, | |
2676 | .free = simple_playback_free, | |
250e41ac | 2677 | .unsol_event = simple_hdmi_unsol_event, |
d0b1252d TI |
2678 | }; |
2679 | ||
2680 | static int patch_simple_hdmi(struct hda_codec *codec, | |
2681 | hda_nid_t cvt_nid, hda_nid_t pin_nid) | |
2682 | { | |
2683 | struct hdmi_spec *spec; | |
bce0d2a8 TI |
2684 | struct hdmi_spec_per_cvt *per_cvt; |
2685 | struct hdmi_spec_per_pin *per_pin; | |
d0b1252d TI |
2686 | |
2687 | spec = kzalloc(sizeof(*spec), GFP_KERNEL); | |
2688 | if (!spec) | |
2689 | return -ENOMEM; | |
2690 | ||
2691 | codec->spec = spec; | |
bce0d2a8 | 2692 | hdmi_array_init(spec, 1); |
d0b1252d TI |
2693 | |
2694 | spec->multiout.num_dacs = 0; /* no analog */ | |
2695 | spec->multiout.max_channels = 2; | |
2696 | spec->multiout.dig_out_nid = cvt_nid; | |
2697 | spec->num_cvts = 1; | |
2698 | spec->num_pins = 1; | |
bce0d2a8 TI |
2699 | per_pin = snd_array_new(&spec->pins); |
2700 | per_cvt = snd_array_new(&spec->cvts); | |
2701 | if (!per_pin || !per_cvt) { | |
2702 | simple_playback_free(codec); | |
2703 | return -ENOMEM; | |
2704 | } | |
2705 | per_cvt->cvt_nid = cvt_nid; | |
2706 | per_pin->pin_nid = pin_nid; | |
d0b1252d TI |
2707 | spec->pcm_playback = simple_pcm_playback; |
2708 | ||
2709 | codec->patch_ops = simple_hdmi_patch_ops; | |
2710 | ||
2711 | return 0; | |
2712 | } | |
2713 | ||
1f348522 AP |
2714 | static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec, |
2715 | int channels) | |
2716 | { | |
2717 | unsigned int chanmask; | |
2718 | int chan = channels ? (channels - 1) : 1; | |
2719 | ||
2720 | switch (channels) { | |
2721 | default: | |
2722 | case 0: | |
2723 | case 2: | |
2724 | chanmask = 0x00; | |
2725 | break; | |
2726 | case 4: | |
2727 | chanmask = 0x08; | |
2728 | break; | |
2729 | case 6: | |
2730 | chanmask = 0x0b; | |
2731 | break; | |
2732 | case 8: | |
2733 | chanmask = 0x13; | |
2734 | break; | |
2735 | } | |
2736 | ||
2737 | /* Set the audio infoframe channel allocation and checksum fields. The | |
2738 | * channel count is computed implicitly by the hardware. */ | |
2739 | snd_hda_codec_write(codec, 0x1, 0, | |
2740 | Nv_VERB_SET_Channel_Allocation, chanmask); | |
2741 | ||
2742 | snd_hda_codec_write(codec, 0x1, 0, | |
2743 | Nv_VERB_SET_Info_Frame_Checksum, | |
2744 | (0x71 - chan - chanmask)); | |
2745 | } | |
2746 | ||
84eb01be TI |
2747 | static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo, |
2748 | struct hda_codec *codec, | |
2749 | struct snd_pcm_substream *substream) | |
2750 | { | |
2751 | struct hdmi_spec *spec = codec->spec; | |
2752 | int i; | |
2753 | ||
2754 | snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, | |
2755 | 0, AC_VERB_SET_CHANNEL_STREAMID, 0); | |
2756 | for (i = 0; i < 4; i++) { | |
2757 | /* set the stream id */ | |
2758 | snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, | |
2759 | AC_VERB_SET_CHANNEL_STREAMID, 0); | |
2760 | /* set the stream format */ | |
2761 | snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, | |
2762 | AC_VERB_SET_STREAM_FORMAT, 0); | |
2763 | } | |
2764 | ||
1f348522 AP |
2765 | /* The audio hardware sends a channel count of 0x7 (8ch) when all the |
2766 | * streams are disabled. */ | |
2767 | nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); | |
2768 | ||
84eb01be TI |
2769 | return snd_hda_multi_out_dig_close(codec, &spec->multiout); |
2770 | } | |
2771 | ||
2772 | static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo, | |
2773 | struct hda_codec *codec, | |
2774 | unsigned int stream_tag, | |
2775 | unsigned int format, | |
2776 | struct snd_pcm_substream *substream) | |
2777 | { | |
2778 | int chs; | |
112daa7a | 2779 | unsigned int dataDCC2, channel_id; |
84eb01be | 2780 | int i; |
7c935976 | 2781 | struct hdmi_spec *spec = codec->spec; |
e3245cdd | 2782 | struct hda_spdif_out *spdif; |
bce0d2a8 | 2783 | struct hdmi_spec_per_cvt *per_cvt; |
84eb01be TI |
2784 | |
2785 | mutex_lock(&codec->spdif_mutex); | |
bce0d2a8 TI |
2786 | per_cvt = get_cvt(spec, 0); |
2787 | spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid); | |
84eb01be TI |
2788 | |
2789 | chs = substream->runtime->channels; | |
84eb01be | 2790 | |
84eb01be TI |
2791 | dataDCC2 = 0x2; |
2792 | ||
84eb01be | 2793 | /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */ |
7c935976 | 2794 | if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) |
84eb01be TI |
2795 | snd_hda_codec_write(codec, |
2796 | nvhdmi_master_con_nid_7x, | |
2797 | 0, | |
2798 | AC_VERB_SET_DIGI_CONVERT_1, | |
7c935976 | 2799 | spdif->ctls & ~AC_DIG1_ENABLE & 0xff); |
84eb01be TI |
2800 | |
2801 | /* set the stream id */ | |
2802 | snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, | |
2803 | AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0); | |
2804 | ||
2805 | /* set the stream format */ | |
2806 | snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, | |
2807 | AC_VERB_SET_STREAM_FORMAT, format); | |
2808 | ||
2809 | /* turn on again (if needed) */ | |
2810 | /* enable and set the channel status audio/data flag */ | |
7c935976 | 2811 | if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) { |
84eb01be TI |
2812 | snd_hda_codec_write(codec, |
2813 | nvhdmi_master_con_nid_7x, | |
2814 | 0, | |
2815 | AC_VERB_SET_DIGI_CONVERT_1, | |
7c935976 | 2816 | spdif->ctls & 0xff); |
84eb01be TI |
2817 | snd_hda_codec_write(codec, |
2818 | nvhdmi_master_con_nid_7x, | |
2819 | 0, | |
2820 | AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); | |
2821 | } | |
2822 | ||
2823 | for (i = 0; i < 4; i++) { | |
2824 | if (chs == 2) | |
2825 | channel_id = 0; | |
2826 | else | |
2827 | channel_id = i * 2; | |
2828 | ||
2829 | /* turn off SPDIF once; | |
2830 | *otherwise the IEC958 bits won't be updated | |
2831 | */ | |
2832 | if (codec->spdif_status_reset && | |
7c935976 | 2833 | (spdif->ctls & AC_DIG1_ENABLE)) |
84eb01be TI |
2834 | snd_hda_codec_write(codec, |
2835 | nvhdmi_con_nids_7x[i], | |
2836 | 0, | |
2837 | AC_VERB_SET_DIGI_CONVERT_1, | |
7c935976 | 2838 | spdif->ctls & ~AC_DIG1_ENABLE & 0xff); |
84eb01be TI |
2839 | /* set the stream id */ |
2840 | snd_hda_codec_write(codec, | |
2841 | nvhdmi_con_nids_7x[i], | |
2842 | 0, | |
2843 | AC_VERB_SET_CHANNEL_STREAMID, | |
2844 | (stream_tag << 4) | channel_id); | |
2845 | /* set the stream format */ | |
2846 | snd_hda_codec_write(codec, | |
2847 | nvhdmi_con_nids_7x[i], | |
2848 | 0, | |
2849 | AC_VERB_SET_STREAM_FORMAT, | |
2850 | format); | |
2851 | /* turn on again (if needed) */ | |
2852 | /* enable and set the channel status audio/data flag */ | |
2853 | if (codec->spdif_status_reset && | |
7c935976 | 2854 | (spdif->ctls & AC_DIG1_ENABLE)) { |
84eb01be TI |
2855 | snd_hda_codec_write(codec, |
2856 | nvhdmi_con_nids_7x[i], | |
2857 | 0, | |
2858 | AC_VERB_SET_DIGI_CONVERT_1, | |
7c935976 | 2859 | spdif->ctls & 0xff); |
84eb01be TI |
2860 | snd_hda_codec_write(codec, |
2861 | nvhdmi_con_nids_7x[i], | |
2862 | 0, | |
2863 | AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); | |
2864 | } | |
2865 | } | |
2866 | ||
1f348522 | 2867 | nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs); |
84eb01be TI |
2868 | |
2869 | mutex_unlock(&codec->spdif_mutex); | |
2870 | return 0; | |
2871 | } | |
2872 | ||
fb79e1e0 | 2873 | static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = { |
84eb01be TI |
2874 | .substreams = 1, |
2875 | .channels_min = 2, | |
2876 | .channels_max = 8, | |
2877 | .nid = nvhdmi_master_con_nid_7x, | |
2878 | .rates = SUPPORTED_RATES, | |
2879 | .maxbps = SUPPORTED_MAXBPS, | |
2880 | .formats = SUPPORTED_FORMATS, | |
2881 | .ops = { | |
2882 | .open = simple_playback_pcm_open, | |
2883 | .close = nvhdmi_8ch_7x_pcm_close, | |
2884 | .prepare = nvhdmi_8ch_7x_pcm_prepare | |
2885 | }, | |
2886 | }; | |
2887 | ||
84eb01be TI |
2888 | static int patch_nvhdmi_2ch(struct hda_codec *codec) |
2889 | { | |
2890 | struct hdmi_spec *spec; | |
d0b1252d TI |
2891 | int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x, |
2892 | nvhdmi_master_pin_nid_7x); | |
2893 | if (err < 0) | |
2894 | return err; | |
84eb01be | 2895 | |
ceaa86ba | 2896 | codec->patch_ops.init = nvhdmi_7x_init_2ch; |
d0b1252d TI |
2897 | /* override the PCM rates, etc, as the codec doesn't give full list */ |
2898 | spec = codec->spec; | |
2899 | spec->pcm_playback.rates = SUPPORTED_RATES; | |
2900 | spec->pcm_playback.maxbps = SUPPORTED_MAXBPS; | |
2901 | spec->pcm_playback.formats = SUPPORTED_FORMATS; | |
84eb01be TI |
2902 | return 0; |
2903 | } | |
2904 | ||
53775b0d TI |
2905 | static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec) |
2906 | { | |
2907 | struct hdmi_spec *spec = codec->spec; | |
2908 | int err = simple_playback_build_pcms(codec); | |
bce0d2a8 TI |
2909 | if (!err) { |
2910 | struct hda_pcm *info = get_pcm_rec(spec, 0); | |
2911 | info->own_chmap = true; | |
2912 | } | |
53775b0d TI |
2913 | return err; |
2914 | } | |
2915 | ||
2916 | static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec) | |
2917 | { | |
2918 | struct hdmi_spec *spec = codec->spec; | |
bce0d2a8 | 2919 | struct hda_pcm *info; |
53775b0d TI |
2920 | struct snd_pcm_chmap *chmap; |
2921 | int err; | |
2922 | ||
2923 | err = simple_playback_build_controls(codec); | |
2924 | if (err < 0) | |
2925 | return err; | |
2926 | ||
2927 | /* add channel maps */ | |
bce0d2a8 TI |
2928 | info = get_pcm_rec(spec, 0); |
2929 | err = snd_pcm_add_chmap_ctls(info->pcm, | |
53775b0d TI |
2930 | SNDRV_PCM_STREAM_PLAYBACK, |
2931 | snd_pcm_alt_chmaps, 8, 0, &chmap); | |
2932 | if (err < 0) | |
2933 | return err; | |
b9a94a9c | 2934 | switch (codec->preset->vendor_id) { |
53775b0d TI |
2935 | case 0x10de0002: |
2936 | case 0x10de0003: | |
2937 | case 0x10de0005: | |
2938 | case 0x10de0006: | |
2939 | chmap->channel_mask = (1U << 2) | (1U << 8); | |
2940 | break; | |
2941 | case 0x10de0007: | |
2942 | chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8); | |
2943 | } | |
2944 | return 0; | |
2945 | } | |
2946 | ||
84eb01be TI |
2947 | static int patch_nvhdmi_8ch_7x(struct hda_codec *codec) |
2948 | { | |
2949 | struct hdmi_spec *spec; | |
2950 | int err = patch_nvhdmi_2ch(codec); | |
84eb01be TI |
2951 | if (err < 0) |
2952 | return err; | |
2953 | spec = codec->spec; | |
2954 | spec->multiout.max_channels = 8; | |
d0b1252d | 2955 | spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x; |
ceaa86ba | 2956 | codec->patch_ops.init = nvhdmi_7x_init_8ch; |
53775b0d TI |
2957 | codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms; |
2958 | codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls; | |
1f348522 AP |
2959 | |
2960 | /* Initialize the audio infoframe channel mask and checksum to something | |
2961 | * valid */ | |
2962 | nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); | |
2963 | ||
84eb01be TI |
2964 | return 0; |
2965 | } | |
2966 | ||
611885bc AH |
2967 | /* |
2968 | * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on: | |
2969 | * - 0x10de0015 | |
2970 | * - 0x10de0040 | |
2971 | */ | |
2972 | static int nvhdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap, | |
2973 | int channels) | |
2974 | { | |
2975 | if (cap->ca_index == 0x00 && channels == 2) | |
2976 | return SNDRV_CTL_TLVT_CHMAP_FIXED; | |
2977 | ||
2978 | return hdmi_chmap_cea_alloc_validate_get_type(cap, channels); | |
2979 | } | |
2980 | ||
2981 | static int nvhdmi_chmap_validate(int ca, int chs, unsigned char *map) | |
2982 | { | |
2983 | if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR)) | |
2984 | return -EINVAL; | |
2985 | ||
2986 | return 0; | |
2987 | } | |
2988 | ||
2989 | static int patch_nvhdmi(struct hda_codec *codec) | |
2990 | { | |
2991 | struct hdmi_spec *spec; | |
2992 | int err; | |
2993 | ||
2994 | err = patch_generic_hdmi(codec); | |
2995 | if (err) | |
2996 | return err; | |
2997 | ||
2998 | spec = codec->spec; | |
75fae117 | 2999 | spec->dyn_pin_out = true; |
611885bc AH |
3000 | |
3001 | spec->ops.chmap_cea_alloc_validate_get_type = | |
3002 | nvhdmi_chmap_cea_alloc_validate_get_type; | |
3003 | spec->ops.chmap_validate = nvhdmi_chmap_validate; | |
3004 | ||
3005 | return 0; | |
3006 | } | |
3007 | ||
26e9a960 TR |
3008 | /* |
3009 | * The HDA codec on NVIDIA Tegra contains two scratch registers that are | |
3010 | * accessed using vendor-defined verbs. These registers can be used for | |
3011 | * interoperability between the HDA and HDMI drivers. | |
3012 | */ | |
3013 | ||
3014 | /* Audio Function Group node */ | |
3015 | #define NVIDIA_AFG_NID 0x01 | |
3016 | ||
3017 | /* | |
3018 | * The SCRATCH0 register is used to notify the HDMI codec of changes in audio | |
3019 | * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to | |
3020 | * be raised in the HDMI codec. The remainder of the bits is arbitrary. This | |
3021 | * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an | |
3022 | * additional bit (at position 30) to signal the validity of the format. | |
3023 | * | |
3024 | * | 31 | 30 | 29 16 | 15 0 | | |
3025 | * +---------+-------+--------+--------+ | |
3026 | * | TRIGGER | VALID | UNUSED | FORMAT | | |
3027 | * +-----------------------------------| | |
3028 | * | |
3029 | * Note that for the trigger bit to take effect it needs to change value | |
3030 | * (i.e. it needs to be toggled). | |
3031 | */ | |
3032 | #define NVIDIA_GET_SCRATCH0 0xfa6 | |
3033 | #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7 | |
3034 | #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8 | |
3035 | #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9 | |
3036 | #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa | |
3037 | #define NVIDIA_SCRATCH_TRIGGER (1 << 7) | |
3038 | #define NVIDIA_SCRATCH_VALID (1 << 6) | |
3039 | ||
3040 | #define NVIDIA_GET_SCRATCH1 0xfab | |
3041 | #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac | |
3042 | #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad | |
3043 | #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae | |
3044 | #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf | |
3045 | ||
3046 | /* | |
3047 | * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0, | |
3048 | * the format is invalidated so that the HDMI codec can be disabled. | |
3049 | */ | |
3050 | static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format) | |
3051 | { | |
3052 | unsigned int value; | |
3053 | ||
3054 | /* bits [31:30] contain the trigger and valid bits */ | |
3055 | value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0, | |
3056 | NVIDIA_GET_SCRATCH0, 0); | |
3057 | value = (value >> 24) & 0xff; | |
3058 | ||
3059 | /* bits [15:0] are used to store the HDA format */ | |
3060 | snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, | |
3061 | NVIDIA_SET_SCRATCH0_BYTE0, | |
3062 | (format >> 0) & 0xff); | |
3063 | snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, | |
3064 | NVIDIA_SET_SCRATCH0_BYTE1, | |
3065 | (format >> 8) & 0xff); | |
3066 | ||
3067 | /* bits [16:24] are unused */ | |
3068 | snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, | |
3069 | NVIDIA_SET_SCRATCH0_BYTE2, 0); | |
3070 | ||
3071 | /* | |
3072 | * Bit 30 signals that the data is valid and hence that HDMI audio can | |
3073 | * be enabled. | |
3074 | */ | |
3075 | if (format == 0) | |
3076 | value &= ~NVIDIA_SCRATCH_VALID; | |
3077 | else | |
3078 | value |= NVIDIA_SCRATCH_VALID; | |
3079 | ||
3080 | /* | |
3081 | * Whenever the trigger bit is toggled, an interrupt is raised in the | |
3082 | * HDMI codec. The HDMI driver will use that as trigger to update its | |
3083 | * configuration. | |
3084 | */ | |
3085 | value ^= NVIDIA_SCRATCH_TRIGGER; | |
3086 | ||
3087 | snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, | |
3088 | NVIDIA_SET_SCRATCH0_BYTE3, value); | |
3089 | } | |
3090 | ||
3091 | static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo, | |
3092 | struct hda_codec *codec, | |
3093 | unsigned int stream_tag, | |
3094 | unsigned int format, | |
3095 | struct snd_pcm_substream *substream) | |
3096 | { | |
3097 | int err; | |
3098 | ||
3099 | err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag, | |
3100 | format, substream); | |
3101 | if (err < 0) | |
3102 | return err; | |
3103 | ||
3104 | /* notify the HDMI codec of the format change */ | |
3105 | tegra_hdmi_set_format(codec, format); | |
3106 | ||
3107 | return 0; | |
3108 | } | |
3109 | ||
3110 | static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo, | |
3111 | struct hda_codec *codec, | |
3112 | struct snd_pcm_substream *substream) | |
3113 | { | |
3114 | /* invalidate the format in the HDMI codec */ | |
3115 | tegra_hdmi_set_format(codec, 0); | |
3116 | ||
3117 | return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream); | |
3118 | } | |
3119 | ||
3120 | static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type) | |
3121 | { | |
3122 | struct hdmi_spec *spec = codec->spec; | |
3123 | unsigned int i; | |
3124 | ||
3125 | for (i = 0; i < spec->num_pins; i++) { | |
3126 | struct hda_pcm *pcm = get_pcm_rec(spec, i); | |
3127 | ||
3128 | if (pcm->pcm_type == type) | |
3129 | return pcm; | |
3130 | } | |
3131 | ||
3132 | return NULL; | |
3133 | } | |
3134 | ||
3135 | static int tegra_hdmi_build_pcms(struct hda_codec *codec) | |
3136 | { | |
3137 | struct hda_pcm_stream *stream; | |
3138 | struct hda_pcm *pcm; | |
3139 | int err; | |
3140 | ||
3141 | err = generic_hdmi_build_pcms(codec); | |
3142 | if (err < 0) | |
3143 | return err; | |
3144 | ||
3145 | pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI); | |
3146 | if (!pcm) | |
3147 | return -ENODEV; | |
3148 | ||
3149 | /* | |
3150 | * Override ->prepare() and ->cleanup() operations to notify the HDMI | |
3151 | * codec about format changes. | |
3152 | */ | |
3153 | stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; | |
3154 | stream->ops.prepare = tegra_hdmi_pcm_prepare; | |
3155 | stream->ops.cleanup = tegra_hdmi_pcm_cleanup; | |
3156 | ||
3157 | return 0; | |
3158 | } | |
3159 | ||
3160 | static int patch_tegra_hdmi(struct hda_codec *codec) | |
3161 | { | |
3162 | int err; | |
3163 | ||
3164 | err = patch_generic_hdmi(codec); | |
3165 | if (err) | |
3166 | return err; | |
3167 | ||
3168 | codec->patch_ops.build_pcms = tegra_hdmi_build_pcms; | |
3169 | ||
3170 | return 0; | |
3171 | } | |
3172 | ||
84eb01be | 3173 | /* |
5a613584 | 3174 | * ATI/AMD-specific implementations |
84eb01be TI |
3175 | */ |
3176 | ||
5a613584 | 3177 | #define is_amdhdmi_rev3_or_later(codec) \ |
7639a06c TI |
3178 | ((codec)->core.vendor_id == 0x1002aa01 && \ |
3179 | ((codec)->core.revision_id & 0xff00) >= 0x0300) | |
5a613584 AH |
3180 | #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec) |
3181 | ||
3182 | /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */ | |
3183 | #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771 | |
3184 | #define ATI_VERB_SET_DOWNMIX_INFO 0x772 | |
3185 | #define ATI_VERB_SET_MULTICHANNEL_01 0x777 | |
3186 | #define ATI_VERB_SET_MULTICHANNEL_23 0x778 | |
3187 | #define ATI_VERB_SET_MULTICHANNEL_45 0x779 | |
3188 | #define ATI_VERB_SET_MULTICHANNEL_67 0x77a | |
461cf6b3 | 3189 | #define ATI_VERB_SET_HBR_CONTROL 0x77c |
5a613584 AH |
3190 | #define ATI_VERB_SET_MULTICHANNEL_1 0x785 |
3191 | #define ATI_VERB_SET_MULTICHANNEL_3 0x786 | |
3192 | #define ATI_VERB_SET_MULTICHANNEL_5 0x787 | |
3193 | #define ATI_VERB_SET_MULTICHANNEL_7 0x788 | |
3194 | #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789 | |
3195 | #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71 | |
3196 | #define ATI_VERB_GET_DOWNMIX_INFO 0xf72 | |
3197 | #define ATI_VERB_GET_MULTICHANNEL_01 0xf77 | |
3198 | #define ATI_VERB_GET_MULTICHANNEL_23 0xf78 | |
3199 | #define ATI_VERB_GET_MULTICHANNEL_45 0xf79 | |
3200 | #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a | |
461cf6b3 | 3201 | #define ATI_VERB_GET_HBR_CONTROL 0xf7c |
5a613584 AH |
3202 | #define ATI_VERB_GET_MULTICHANNEL_1 0xf85 |
3203 | #define ATI_VERB_GET_MULTICHANNEL_3 0xf86 | |
3204 | #define ATI_VERB_GET_MULTICHANNEL_5 0xf87 | |
3205 | #define ATI_VERB_GET_MULTICHANNEL_7 0xf88 | |
3206 | #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89 | |
3207 | ||
84d69e79 AH |
3208 | /* AMD specific HDA cvt verbs */ |
3209 | #define ATI_VERB_SET_RAMP_RATE 0x770 | |
3210 | #define ATI_VERB_GET_RAMP_RATE 0xf70 | |
3211 | ||
5a613584 AH |
3212 | #define ATI_OUT_ENABLE 0x1 |
3213 | ||
3214 | #define ATI_MULTICHANNEL_MODE_PAIRED 0 | |
3215 | #define ATI_MULTICHANNEL_MODE_SINGLE 1 | |
3216 | ||
461cf6b3 AH |
3217 | #define ATI_HBR_CAPABLE 0x01 |
3218 | #define ATI_HBR_ENABLE 0x10 | |
3219 | ||
89250f84 AH |
3220 | static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, |
3221 | unsigned char *buf, int *eld_size) | |
3222 | { | |
3223 | /* call hda_eld.c ATI/AMD-specific function */ | |
3224 | return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size, | |
3225 | is_amdhdmi_rev3_or_later(codec)); | |
3226 | } | |
3227 | ||
5a613584 AH |
3228 | static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca, |
3229 | int active_channels, int conn_type) | |
3230 | { | |
3231 | snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca); | |
3232 | } | |
3233 | ||
3234 | static int atihdmi_paired_swap_fc_lfe(int pos) | |
3235 | { | |
3236 | /* | |
3237 | * ATI/AMD have automatic FC/LFE swap built-in | |
3238 | * when in pairwise mapping mode. | |
3239 | */ | |
3240 | ||
3241 | switch (pos) { | |
3242 | /* see channel_allocations[].speakers[] */ | |
3243 | case 2: return 3; | |
3244 | case 3: return 2; | |
3245 | default: break; | |
3246 | } | |
3247 | ||
3248 | return pos; | |
3249 | } | |
3250 | ||
3251 | static int atihdmi_paired_chmap_validate(int ca, int chs, unsigned char *map) | |
3252 | { | |
3253 | struct cea_channel_speaker_allocation *cap; | |
3254 | int i, j; | |
3255 | ||
3256 | /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */ | |
3257 | ||
3258 | cap = &channel_allocations[get_channel_allocation_order(ca)]; | |
3259 | for (i = 0; i < chs; ++i) { | |
3260 | int mask = to_spk_mask(map[i]); | |
3261 | bool ok = false; | |
3262 | bool companion_ok = false; | |
3263 | ||
3264 | if (!mask) | |
3265 | continue; | |
3266 | ||
3267 | for (j = 0 + i % 2; j < 8; j += 2) { | |
3268 | int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j); | |
3269 | if (cap->speakers[chan_idx] == mask) { | |
3270 | /* channel is in a supported position */ | |
3271 | ok = true; | |
3272 | ||
3273 | if (i % 2 == 0 && i + 1 < chs) { | |
3274 | /* even channel, check the odd companion */ | |
3275 | int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1); | |
3276 | int comp_mask_req = to_spk_mask(map[i+1]); | |
3277 | int comp_mask_act = cap->speakers[comp_chan_idx]; | |
3278 | ||
3279 | if (comp_mask_req == comp_mask_act) | |
3280 | companion_ok = true; | |
3281 | else | |
3282 | return -EINVAL; | |
3283 | } | |
3284 | break; | |
3285 | } | |
3286 | } | |
3287 | ||
3288 | if (!ok) | |
3289 | return -EINVAL; | |
3290 | ||
3291 | if (companion_ok) | |
3292 | i++; /* companion channel already checked */ | |
3293 | } | |
3294 | ||
3295 | return 0; | |
3296 | } | |
3297 | ||
3298 | static int atihdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid, | |
3299 | int hdmi_slot, int stream_channel) | |
3300 | { | |
3301 | int verb; | |
3302 | int ati_channel_setup = 0; | |
3303 | ||
3304 | if (hdmi_slot > 7) | |
3305 | return -EINVAL; | |
3306 | ||
3307 | if (!has_amd_full_remap_support(codec)) { | |
3308 | hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot); | |
3309 | ||
3310 | /* In case this is an odd slot but without stream channel, do not | |
3311 | * disable the slot since the corresponding even slot could have a | |
3312 | * channel. In case neither have a channel, the slot pair will be | |
3313 | * disabled when this function is called for the even slot. */ | |
3314 | if (hdmi_slot % 2 != 0 && stream_channel == 0xf) | |
3315 | return 0; | |
3316 | ||
3317 | hdmi_slot -= hdmi_slot % 2; | |
3318 | ||
3319 | if (stream_channel != 0xf) | |
3320 | stream_channel -= stream_channel % 2; | |
3321 | } | |
3322 | ||
3323 | verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e; | |
3324 | ||
3325 | /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */ | |
3326 | ||
3327 | if (stream_channel != 0xf) | |
3328 | ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE; | |
3329 | ||
3330 | return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup); | |
3331 | } | |
3332 | ||
3333 | static int atihdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid, | |
3334 | int asp_slot) | |
3335 | { | |
3336 | bool was_odd = false; | |
3337 | int ati_asp_slot = asp_slot; | |
3338 | int verb; | |
3339 | int ati_channel_setup; | |
3340 | ||
3341 | if (asp_slot > 7) | |
3342 | return -EINVAL; | |
3343 | ||
3344 | if (!has_amd_full_remap_support(codec)) { | |
3345 | ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot); | |
3346 | if (ati_asp_slot % 2 != 0) { | |
3347 | ati_asp_slot -= 1; | |
3348 | was_odd = true; | |
3349 | } | |
3350 | } | |
3351 | ||
3352 | verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e; | |
3353 | ||
3354 | ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0); | |
3355 | ||
3356 | if (!(ati_channel_setup & ATI_OUT_ENABLE)) | |
3357 | return 0xf; | |
3358 | ||
3359 | return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd; | |
3360 | } | |
84eb01be | 3361 | |
5a613584 AH |
3362 | static int atihdmi_paired_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap, |
3363 | int channels) | |
3364 | { | |
3365 | int c; | |
3366 | ||
3367 | /* | |
3368 | * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so | |
3369 | * we need to take that into account (a single channel may take 2 | |
3370 | * channel slots if we need to carry a silent channel next to it). | |
3371 | * On Rev3+ AMD codecs this function is not used. | |
3372 | */ | |
3373 | int chanpairs = 0; | |
3374 | ||
3375 | /* We only produce even-numbered channel count TLVs */ | |
3376 | if ((channels % 2) != 0) | |
3377 | return -1; | |
3378 | ||
3379 | for (c = 0; c < 7; c += 2) { | |
3380 | if (cap->speakers[c] || cap->speakers[c+1]) | |
3381 | chanpairs++; | |
3382 | } | |
3383 | ||
3384 | if (chanpairs * 2 != channels) | |
3385 | return -1; | |
3386 | ||
3387 | return SNDRV_CTL_TLVT_CHMAP_PAIRED; | |
3388 | } | |
3389 | ||
3390 | static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap, | |
3391 | unsigned int *chmap, int channels) | |
3392 | { | |
3393 | /* produce paired maps for pre-rev3 ATI/AMD codecs */ | |
3394 | int count = 0; | |
3395 | int c; | |
3396 | ||
3397 | for (c = 7; c >= 0; c--) { | |
3398 | int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c); | |
3399 | int spk = cap->speakers[chan]; | |
3400 | if (!spk) { | |
3401 | /* add N/A channel if the companion channel is occupied */ | |
3402 | if (cap->speakers[chan + (chan % 2 ? -1 : 1)]) | |
3403 | chmap[count++] = SNDRV_CHMAP_NA; | |
3404 | ||
3405 | continue; | |
3406 | } | |
3407 | ||
3408 | chmap[count++] = spk_to_chmap(spk); | |
3409 | } | |
3410 | ||
3411 | WARN_ON(count != channels); | |
3412 | } | |
3413 | ||
461cf6b3 AH |
3414 | static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, |
3415 | bool hbr) | |
3416 | { | |
3417 | int hbr_ctl, hbr_ctl_new; | |
3418 | ||
3419 | hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0); | |
13122e6e | 3420 | if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) { |
461cf6b3 AH |
3421 | if (hbr) |
3422 | hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE; | |
3423 | else | |
3424 | hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE; | |
3425 | ||
4e76a883 TI |
3426 | codec_dbg(codec, |
3427 | "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n", | |
461cf6b3 AH |
3428 | pin_nid, |
3429 | hbr_ctl == hbr_ctl_new ? "" : "new-", | |
3430 | hbr_ctl_new); | |
3431 | ||
3432 | if (hbr_ctl != hbr_ctl_new) | |
3433 | snd_hda_codec_write(codec, pin_nid, 0, | |
3434 | ATI_VERB_SET_HBR_CONTROL, | |
3435 | hbr_ctl_new); | |
3436 | ||
3437 | } else if (hbr) | |
3438 | return -EINVAL; | |
3439 | ||
3440 | return 0; | |
3441 | } | |
3442 | ||
84d69e79 AH |
3443 | static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, |
3444 | hda_nid_t pin_nid, u32 stream_tag, int format) | |
3445 | { | |
3446 | ||
3447 | if (is_amdhdmi_rev3_or_later(codec)) { | |
3448 | int ramp_rate = 180; /* default as per AMD spec */ | |
3449 | /* disable ramp-up/down for non-pcm as per AMD spec */ | |
3450 | if (format & AC_FMT_TYPE_NON_PCM) | |
3451 | ramp_rate = 0; | |
3452 | ||
3453 | snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate); | |
3454 | } | |
3455 | ||
3456 | return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format); | |
3457 | } | |
3458 | ||
3459 | ||
5a613584 | 3460 | static int atihdmi_init(struct hda_codec *codec) |
84eb01be TI |
3461 | { |
3462 | struct hdmi_spec *spec = codec->spec; | |
5a613584 | 3463 | int pin_idx, err; |
84eb01be | 3464 | |
5a613584 AH |
3465 | err = generic_hdmi_init(codec); |
3466 | ||
3467 | if (err) | |
84eb01be | 3468 | return err; |
5a613584 AH |
3469 | |
3470 | for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { | |
3471 | struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); | |
3472 | ||
3473 | /* make sure downmix information in infoframe is zero */ | |
3474 | snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0); | |
3475 | ||
3476 | /* enable channel-wise remap mode if supported */ | |
3477 | if (has_amd_full_remap_support(codec)) | |
3478 | snd_hda_codec_write(codec, per_pin->pin_nid, 0, | |
3479 | ATI_VERB_SET_MULTICHANNEL_MODE, | |
3480 | ATI_MULTICHANNEL_MODE_SINGLE); | |
84eb01be | 3481 | } |
5a613584 | 3482 | |
84eb01be TI |
3483 | return 0; |
3484 | } | |
3485 | ||
84eb01be TI |
3486 | static int patch_atihdmi(struct hda_codec *codec) |
3487 | { | |
3488 | struct hdmi_spec *spec; | |
5a613584 AH |
3489 | struct hdmi_spec_per_cvt *per_cvt; |
3490 | int err, cvt_idx; | |
3491 | ||
3492 | err = patch_generic_hdmi(codec); | |
3493 | ||
3494 | if (err) | |
d0b1252d | 3495 | return err; |
5a613584 AH |
3496 | |
3497 | codec->patch_ops.init = atihdmi_init; | |
3498 | ||
d0b1252d | 3499 | spec = codec->spec; |
5a613584 | 3500 | |
89250f84 | 3501 | spec->ops.pin_get_eld = atihdmi_pin_get_eld; |
5a613584 AH |
3502 | spec->ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel; |
3503 | spec->ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel; | |
3504 | spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe; | |
461cf6b3 | 3505 | spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup; |
84d69e79 | 3506 | spec->ops.setup_stream = atihdmi_setup_stream; |
5a613584 AH |
3507 | |
3508 | if (!has_amd_full_remap_support(codec)) { | |
3509 | /* override to ATI/AMD-specific versions with pairwise mapping */ | |
3510 | spec->ops.chmap_cea_alloc_validate_get_type = | |
3511 | atihdmi_paired_chmap_cea_alloc_validate_get_type; | |
3512 | spec->ops.cea_alloc_to_tlv_chmap = atihdmi_paired_cea_alloc_to_tlv_chmap; | |
3513 | spec->ops.chmap_validate = atihdmi_paired_chmap_validate; | |
3514 | } | |
3515 | ||
3516 | /* ATI/AMD converters do not advertise all of their capabilities */ | |
3517 | for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { | |
3518 | per_cvt = get_cvt(spec, cvt_idx); | |
3519 | per_cvt->channels_max = max(per_cvt->channels_max, 8u); | |
3520 | per_cvt->rates |= SUPPORTED_RATES; | |
3521 | per_cvt->formats |= SUPPORTED_FORMATS; | |
3522 | per_cvt->maxbps = max(per_cvt->maxbps, 24u); | |
3523 | } | |
3524 | ||
3525 | spec->channels_max = max(spec->channels_max, 8u); | |
3526 | ||
84eb01be TI |
3527 | return 0; |
3528 | } | |
3529 | ||
3de5ff88 AL |
3530 | /* VIA HDMI Implementation */ |
3531 | #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */ | |
3532 | #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */ | |
3533 | ||
3de5ff88 AL |
3534 | static int patch_via_hdmi(struct hda_codec *codec) |
3535 | { | |
250e41ac | 3536 | return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID); |
3de5ff88 | 3537 | } |
84eb01be TI |
3538 | |
3539 | /* | |
3540 | * patch entries | |
3541 | */ | |
b9a94a9c TI |
3542 | static const struct hda_device_id snd_hda_id_hdmi[] = { |
3543 | HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi), | |
3544 | HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi), | |
3545 | HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi), | |
3546 | HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi), | |
3547 | HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi), | |
3548 | HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi), | |
3549 | HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi), | |
3550 | HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), | |
3551 | HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), | |
3552 | HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), | |
3553 | HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), | |
3554 | HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x), | |
3555 | HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi), | |
3556 | HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi), | |
3557 | HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi), | |
3558 | HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi), | |
3559 | HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi), | |
3560 | HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi), | |
3561 | HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi), | |
3562 | HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi), | |
3563 | HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi), | |
3564 | HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi), | |
3565 | HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi), | |
c8900a0f | 3566 | /* 17 is known to be absent */ |
b9a94a9c TI |
3567 | HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi), |
3568 | HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi), | |
3569 | HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi), | |
3570 | HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi), | |
3571 | HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi), | |
3572 | HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi), | |
3573 | HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi), | |
3574 | HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi), | |
3575 | HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi), | |
3576 | HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi), | |
3577 | HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi), | |
3578 | HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi), | |
3579 | HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi), | |
3580 | HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi), | |
3581 | HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi), | |
3582 | HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi), | |
3583 | HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch), | |
3584 | HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi), | |
3585 | HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi), | |
3586 | HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi), | |
3587 | HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi), | |
3588 | HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch), | |
3589 | HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi), | |
3590 | HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi), | |
3591 | HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi), | |
3592 | HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi), | |
3593 | HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_generic_hdmi), | |
3594 | HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi), | |
3595 | HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi), | |
3596 | HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi), | |
3597 | HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_generic_hdmi), | |
3598 | HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_generic_hdmi), | |
3599 | HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_generic_hdmi), | |
3600 | HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_generic_hdmi), | |
3601 | HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_generic_hdmi), | |
3602 | HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_generic_hdmi), | |
3603 | HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_generic_hdmi), | |
3604 | HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi), | |
3605 | HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_generic_hdmi), | |
3606 | HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_generic_hdmi), | |
3607 | HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi), | |
d8a766a1 | 3608 | /* special ID for generic HDMI */ |
b9a94a9c | 3609 | HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi), |
84eb01be TI |
3610 | {} /* terminator */ |
3611 | }; | |
b9a94a9c | 3612 | MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi); |
84eb01be TI |
3613 | |
3614 | MODULE_LICENSE("GPL"); | |
3615 | MODULE_DESCRIPTION("HDMI HD-audio codec"); | |
3616 | MODULE_ALIAS("snd-hda-codec-intelhdmi"); | |
3617 | MODULE_ALIAS("snd-hda-codec-nvhdmi"); | |
3618 | MODULE_ALIAS("snd-hda-codec-atihdmi"); | |
3619 | ||
d8a766a1 | 3620 | static struct hda_codec_driver hdmi_driver = { |
b9a94a9c | 3621 | .id = snd_hda_id_hdmi, |
84eb01be TI |
3622 | }; |
3623 | ||
d8a766a1 | 3624 | module_hda_codec_driver(hdmi_driver); |