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ALSA: hda - Add extra chmap for 2.1 outputs on ASUS laptops
[linux-2.6-block.git] / sound / pci / hda / patch_hdmi.c
CommitLineData
079d88cc
WF		 1/*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
84eb01be
TI		 6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
5a613584 9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
079d88cc
WF		 10 *
11 * Authors:
12 * Wu Fengguang <wfg@linux.intel.com>
13 *
14 * Maintained by:
15 * Wu Fengguang <wfg@linux.intel.com>
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the Free
19 * Software Foundation; either version 2 of the License, or (at your option)
20 * any later version.
21 *
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 * for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software Foundation,
29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
84eb01be
TI		 32#include <linux/init.h>
33#include <linux/delay.h>
34#include <linux/slab.h>
65a77217 35#include <linux/module.h>
84eb01be 36#include <sound/core.h>
07acecc1 37#include <sound/jack.h>
433968da 38#include <sound/asoundef.h>
d45e6889 39#include <sound/tlv.h>
84eb01be
TI		 40#include "hda_codec.h"
41#include "hda_local.h"
1835a0f9 42#include "hda_jack.h"
84eb01be 43
0ebaa24c
TI		 44static bool static_hdmi_pcm;
45module_param(static_hdmi_pcm, bool, 0644);
46MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
47
fb87fa3a
ML		 48#define is_haswell(codec) ((codec)->vendor_id == 0x80862807)
49
384a48d7
SW		 50struct hdmi_spec_per_cvt {
51 hda_nid_t cvt_nid;
52 int assigned;
53 unsigned int channels_min;
54 unsigned int channels_max;
55 u32 rates;
56 u64 formats;
57 unsigned int maxbps;
58};
079d88cc 59
4eea3091
TI		 60/* max. connections to a widget */
61#define HDA_MAX_CONNECTIONS 32
62
384a48d7
SW		 63struct hdmi_spec_per_pin {
64 hda_nid_t pin_nid;
65 int num_mux_nids;
66 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
1df5a06a 67 hda_nid_t cvt_nid;
744626da
WF		 68
69 struct hda_codec *codec;
384a48d7 70 struct hdmi_eld sink_eld;
a4e9a38b 71 struct mutex lock;
744626da 72 struct delayed_work work;
92c69e79 73 struct snd_kcontrol *eld_ctl;
c6e8453e 74 int repoll_count;
b054087d
TI		 75 bool setup; /* the stream has been set up by prepare callback */
76 int channels; /* current number of channels */
1a6003b5 77 bool non_pcm;
d45e6889
TI		 78 bool chmap_set; /* channel-map override by ALSA API? */
79 unsigned char chmap[8]; /* ALSA API channel-map */
bce0d2a8 80 char pcm_name[8]; /* filled in build_pcm callbacks */
a4e9a38b
TI		 81#ifdef CONFIG_PROC_FS
82 struct snd_info_entry *proc_entry;
83#endif
384a48d7 84};
079d88cc 85
307229d2
AH		 86struct cea_channel_speaker_allocation;
87
88/* operations used by generic code that can be overridden by patches */
89struct hdmi_ops {
90 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
91 unsigned char *buf, int *eld_size);
92
93 /* get and set channel assigned to each HDMI ASP (audio sample packet) slot */
94 int (*pin_get_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
95 int asp_slot);
96 int (*pin_set_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
97 int asp_slot, int channel);
98
99 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
100 int ca, int active_channels, int conn_type);
101
102 /* enable/disable HBR (HD passthrough) */
103 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
104
105 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
106 hda_nid_t pin_nid, u32 stream_tag, int format);
107
108 /* Helpers for producing the channel map TLVs. These can be overridden
109 * for devices that have non-standard mapping requirements. */
110 int (*chmap_cea_alloc_validate_get_type)(struct cea_channel_speaker_allocation *cap,
111 int channels);
112 void (*cea_alloc_to_tlv_chmap)(struct cea_channel_speaker_allocation *cap,
113 unsigned int *chmap, int channels);
114
115 /* check that the user-given chmap is supported */
116 int (*chmap_validate)(int ca, int channels, unsigned char *chmap);
117};
118
384a48d7
SW		 119struct hdmi_spec {
120 int num_cvts;
bce0d2a8
TI		 121 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
122 hda_nid_t cvt_nids[4]; /* only for haswell fix */
079d88cc 123
384a48d7 124 int num_pins;
bce0d2a8
TI		 125 struct snd_array pins; /* struct hdmi_spec_per_pin */
126 struct snd_array pcm_rec; /* struct hda_pcm */
d45e6889 127 unsigned int channels_max; /* max over all cvts */
079d88cc 128
4bd038f9 129 struct hdmi_eld temp_eld;
307229d2 130 struct hdmi_ops ops;
079d88cc 131 /*
5a613584 132 * Non-generic VIA/NVIDIA specific
079d88cc
WF		 133 */
134 struct hda_multi_out multiout;
d0b1252d 135 struct hda_pcm_stream pcm_playback;
079d88cc
WF		 136};
137
138
139struct hdmi_audio_infoframe {
140 u8 type; /* 0x84 */
141 u8 ver; /* 0x01 */
142 u8 len; /* 0x0a */
143
53d7d69d
WF		 144 u8 checksum;
145
079d88cc
WF		 146 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
147 u8 SS01_SF24;
148 u8 CXT04;
149 u8 CA;
150 u8 LFEPBL01_LSV36_DM_INH7;
53d7d69d
WF		 151};
152
153struct dp_audio_infoframe {
154 u8 type; /* 0x84 */
155 u8 len; /* 0x1b */
156 u8 ver; /* 0x11 << 2 */
157
158 u8 CC02_CT47; /* match with HDMI infoframe from this on */
159 u8 SS01_SF24;
160 u8 CXT04;
161 u8 CA;
162 u8 LFEPBL01_LSV36_DM_INH7;
079d88cc
WF		 163};
164
2b203dbb
TI		 165union audio_infoframe {
166 struct hdmi_audio_infoframe hdmi;
167 struct dp_audio_infoframe dp;
168 u8 bytes[0];
169};
170
079d88cc
WF		 171/*
172 * CEA speaker placement:
173 *
174 * FLH FCH FRH
175 * FLW FL FLC FC FRC FR FRW
176 *
177 * LFE
178 * TC
179 *
180 * RL RLC RC RRC RR
181 *
182 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
183 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
184 */
185enum cea_speaker_placement {
186 FL = (1 << 0), /* Front Left */
187 FC = (1 << 1), /* Front Center */
188 FR = (1 << 2), /* Front Right */
189 FLC = (1 << 3), /* Front Left Center */
190 FRC = (1 << 4), /* Front Right Center */
191 RL = (1 << 5), /* Rear Left */
192 RC = (1 << 6), /* Rear Center */
193 RR = (1 << 7), /* Rear Right */
194 RLC = (1 << 8), /* Rear Left Center */
195 RRC = (1 << 9), /* Rear Right Center */
196 LFE = (1 << 10), /* Low Frequency Effect */
197 FLW = (1 << 11), /* Front Left Wide */
198 FRW = (1 << 12), /* Front Right Wide */
199 FLH = (1 << 13), /* Front Left High */
200 FCH = (1 << 14), /* Front Center High */
201 FRH = (1 << 15), /* Front Right High */
202 TC = (1 << 16), /* Top Center */
203};
204
205/*
206 * ELD SA bits in the CEA Speaker Allocation data block
207 */
208static int eld_speaker_allocation_bits[] = {
209 [0] = FL | FR,
210 [1] = LFE,
211 [2] = FC,
212 [3] = RL | RR,
213 [4] = RC,
214 [5] = FLC | FRC,
215 [6] = RLC | RRC,
216 /* the following are not defined in ELD yet */
217 [7] = FLW | FRW,
218 [8] = FLH | FRH,
219 [9] = TC,
220 [10] = FCH,
221};
222
223struct cea_channel_speaker_allocation {
224 int ca_index;
225 int speakers[8];
226
227 /* derived values, just for convenience */
228 int channels;
229 int spk_mask;
230};
231
232/*
233 * ALSA sequence is:
234 *
235 * surround40 surround41 surround50 surround51 surround71
236 * ch0 front left = = = =
237 * ch1 front right = = = =
238 * ch2 rear left = = = =
239 * ch3 rear right = = = =
240 * ch4 LFE center center center
241 * ch5 LFE LFE
242 * ch6 side left
243 * ch7 side right
244 *
245 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
246 */
247static int hdmi_channel_mapping[0x32][8] = {
248 /* stereo */
249 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
250 /* 2.1 */
251 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
252 /* Dolby Surround */
253 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
254 /* surround40 */
255 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
256 /* 4ch */
257 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
258 /* surround41 */
9396d317 259 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
079d88cc
WF		 260 /* surround50 */
261 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
262 /* surround51 */
263 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
264 /* 7.1 */
265 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
266};
267
268/*
269 * This is an ordered list!
270 *
271 * The preceding ones have better chances to be selected by
53d7d69d 272 * hdmi_channel_allocation().
079d88cc
WF		 273 */
274static struct cea_channel_speaker_allocation channel_allocations[] = {
275/* channel: 7 6 5 4 3 2 1 0 */
276{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
277 /* 2.1 */
278{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
279 /* Dolby Surround */
280{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
281 /* surround40 */
282{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
283 /* surround41 */
284{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
285 /* surround50 */
286{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
287 /* surround51 */
288{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
289 /* 6.1 */
290{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
291 /* surround71 */
292{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
293
294{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
295{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
296{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
297{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
298{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
299{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
300{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
301{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
302{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
303{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
304{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
305{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
306{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
307{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
308{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
309{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
310{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
311{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
312{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
313{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
314{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
315{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
316{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
317{ .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
318{ .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
319{ .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
320{ .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
321{ .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
322{ .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
323{ .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
324{ .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
325{ .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
326{ .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
327{ .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
328{ .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
329{ .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
330{ .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
331{ .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
332{ .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
333{ .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
334{ .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
335};
336
337
338/*
339 * HDMI routines
340 */
341
bce0d2a8
TI		 342#define get_pin(spec, idx) \
343 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
344#define get_cvt(spec, idx) \
345 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
346#define get_pcm_rec(spec, idx) \
347 ((struct hda_pcm *)snd_array_elem(&spec->pcm_rec, idx))
348
384a48d7 349static int pin_nid_to_pin_index(struct hdmi_spec *spec, hda_nid_t pin_nid)
079d88cc 350{
384a48d7 351 int pin_idx;
079d88cc 352
384a48d7 353 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
bce0d2a8 354 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
384a48d7 355 return pin_idx;
079d88cc 356
384a48d7
SW		 357 snd_printk(KERN_WARNING "HDMI: pin nid %d not registered\n", pin_nid);
358 return -EINVAL;
359}
360
361static int hinfo_to_pin_index(struct hdmi_spec *spec,
362 struct hda_pcm_stream *hinfo)
363{
364 int pin_idx;
365
366 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
bce0d2a8 367 if (get_pcm_rec(spec, pin_idx)->stream == hinfo)
384a48d7
SW		 368 return pin_idx;
369
370 snd_printk(KERN_WARNING "HDMI: hinfo %p not registered\n", hinfo);
371 return -EINVAL;
372}
373
374static int cvt_nid_to_cvt_index(struct hdmi_spec *spec, hda_nid_t cvt_nid)
375{
376 int cvt_idx;
377
378 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
bce0d2a8 379 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
384a48d7
SW		 380 return cvt_idx;
381
382 snd_printk(KERN_WARNING "HDMI: cvt nid %d not registered\n", cvt_nid);
079d88cc
WF		 383 return -EINVAL;
384}
385
14bc52b8
PLB		 386static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
387 struct snd_ctl_elem_info *uinfo)
388{
389 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9 390 struct hdmi_spec *spec = codec->spec;
a4e9a38b 391 struct hdmi_spec_per_pin *per_pin;
68e03de9 392 struct hdmi_eld *eld;
14bc52b8
PLB		 393 int pin_idx;
394
14bc52b8
PLB		 395 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
396
397 pin_idx = kcontrol->private_value;
a4e9a38b
TI		 398 per_pin = get_pin(spec, pin_idx);
399 eld = &per_pin->sink_eld;
68e03de9 400
a4e9a38b 401 mutex_lock(&per_pin->lock);
68e03de9 402 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
a4e9a38b 403 mutex_unlock(&per_pin->lock);
14bc52b8
PLB		 404
405 return 0;
406}
407
408static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
409 struct snd_ctl_elem_value *ucontrol)
410{
411 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9 412 struct hdmi_spec *spec = codec->spec;
a4e9a38b 413 struct hdmi_spec_per_pin *per_pin;
68e03de9 414 struct hdmi_eld *eld;
14bc52b8
PLB		 415 int pin_idx;
416
14bc52b8 417 pin_idx = kcontrol->private_value;
a4e9a38b
TI		 418 per_pin = get_pin(spec, pin_idx);
419 eld = &per_pin->sink_eld;
68e03de9 420
a4e9a38b 421 mutex_lock(&per_pin->lock);
68e03de9 422 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data)) {
a4e9a38b 423 mutex_unlock(&per_pin->lock);
68e03de9
DH		 424 snd_BUG();
425 return -EINVAL;
426 }
427
428 memset(ucontrol->value.bytes.data, 0,
429 ARRAY_SIZE(ucontrol->value.bytes.data));
430 if (eld->eld_valid)
431 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
432 eld->eld_size);
a4e9a38b 433 mutex_unlock(&per_pin->lock);
14bc52b8
PLB		 434
435 return 0;
436}
437
438static struct snd_kcontrol_new eld_bytes_ctl = {
439 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
440 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
441 .name = "ELD",
442 .info = hdmi_eld_ctl_info,
443 .get = hdmi_eld_ctl_get,
444};
445
446static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
447 int device)
448{
449 struct snd_kcontrol *kctl;
450 struct hdmi_spec *spec = codec->spec;
451 int err;
452
453 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
454 if (!kctl)
455 return -ENOMEM;
456 kctl->private_value = pin_idx;
457 kctl->id.device = device;
458
bce0d2a8 459 err = snd_hda_ctl_add(codec, get_pin(spec, pin_idx)->pin_nid, kctl);
14bc52b8
PLB		 460 if (err < 0)
461 return err;
462
bce0d2a8 463 get_pin(spec, pin_idx)->eld_ctl = kctl;
14bc52b8
PLB		 464 return 0;
465}
466
079d88cc
WF		 467#ifdef BE_PARANOID
468static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
469 int *packet_index, int *byte_index)
470{
471 int val;
472
473 val = snd_hda_codec_read(codec, pin_nid, 0,
474 AC_VERB_GET_HDMI_DIP_INDEX, 0);
475
476 *packet_index = val >> 5;
477 *byte_index = val & 0x1f;
478}
479#endif
480
481static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
482 int packet_index, int byte_index)
483{
484 int val;
485
486 val = (packet_index << 5) | (byte_index & 0x1f);
487
488 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
489}
490
491static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
492 unsigned char val)
493{
494 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
495}
496
384a48d7 497static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc
WF		 498{
499 /* Unmute */
500 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
501 snd_hda_codec_write(codec, pin_nid, 0,
502 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
6169b673
TI		 503 /* Enable pin out: some machines with GM965 gets broken output when
504 * the pin is disabled or changed while using with HDMI
505 */
079d88cc 506 snd_hda_codec_write(codec, pin_nid, 0,
6169b673 507 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
079d88cc
WF		 508}
509
384a48d7 510static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc 511{
384a48d7 512 return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
079d88cc
WF		 513 AC_VERB_GET_CVT_CHAN_COUNT, 0);
514}
515
516static void hdmi_set_channel_count(struct hda_codec *codec,
384a48d7 517 hda_nid_t cvt_nid, int chs)
079d88cc 518{
384a48d7
SW		 519 if (chs != hdmi_get_channel_count(codec, cvt_nid))
520 snd_hda_codec_write(codec, cvt_nid, 0,
079d88cc
WF		 521 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
522}
523
a4e9a38b
TI		 524/*
525 * ELD proc files
526 */
527
528#ifdef CONFIG_PROC_FS
529static void print_eld_info(struct snd_info_entry *entry,
530 struct snd_info_buffer *buffer)
531{
532 struct hdmi_spec_per_pin *per_pin = entry->private_data;
533
534 mutex_lock(&per_pin->lock);
535 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
536 mutex_unlock(&per_pin->lock);
537}
538
539static void write_eld_info(struct snd_info_entry *entry,
540 struct snd_info_buffer *buffer)
541{
542 struct hdmi_spec_per_pin *per_pin = entry->private_data;
543
544 mutex_lock(&per_pin->lock);
545 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
546 mutex_unlock(&per_pin->lock);
547}
548
549static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
550{
551 char name[32];
552 struct hda_codec *codec = per_pin->codec;
553 struct snd_info_entry *entry;
554 int err;
555
556 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
557 err = snd_card_proc_new(codec->bus->card, name, &entry);
558 if (err < 0)
559 return err;
560
561 snd_info_set_text_ops(entry, per_pin, print_eld_info);
562 entry->c.text.write = write_eld_info;
563 entry->mode |= S_IWUSR;
564 per_pin->proc_entry = entry;
565
566 return 0;
567}
568
569static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
570{
571 if (!per_pin->codec->bus->shutdown && per_pin->proc_entry) {
572 snd_device_free(per_pin->codec->bus->card, per_pin->proc_entry);
573 per_pin->proc_entry = NULL;
574 }
575}
576#else
b55447a7
TI		 577static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
578 int index)
a4e9a38b
TI		 579{
580 return 0;
581}
b55447a7 582static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
a4e9a38b
TI		 583{
584}
585#endif
079d88cc
WF		 586
587/*
588 * Channel mapping routines
589 */
590
591/*
592 * Compute derived values in channel_allocations[].
593 */
594static void init_channel_allocations(void)
595{
596 int i, j;
597 struct cea_channel_speaker_allocation *p;
598
599 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
600 p = channel_allocations + i;
601 p->channels = 0;
602 p->spk_mask = 0;
603 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
604 if (p->speakers[j]) {
605 p->channels++;
606 p->spk_mask |= p->speakers[j];
607 }
608 }
609}
610
72357c78
WX		 611static int get_channel_allocation_order(int ca)
612{
613 int i;
614
615 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
616 if (channel_allocations[i].ca_index == ca)
617 break;
618 }
619 return i;
620}
621
079d88cc
WF		 622/*
623 * The transformation takes two steps:
624 *
625 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
626 * spk_mask => (channel_allocations[]) => ai->CA
627 *
628 * TODO: it could select the wrong CA from multiple candidates.
629*/
384a48d7 630static int hdmi_channel_allocation(struct hdmi_eld *eld, int channels)
079d88cc 631{
079d88cc 632 int i;
53d7d69d 633 int ca = 0;
079d88cc 634 int spk_mask = 0;
079d88cc
WF		 635 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
636
637 /*
638 * CA defaults to 0 for basic stereo audio
639 */
640 if (channels <= 2)
641 return 0;
642
079d88cc
WF		 643 /*
644 * expand ELD's speaker allocation mask
645 *
646 * ELD tells the speaker mask in a compact(paired) form,
647 * expand ELD's notions to match the ones used by Audio InfoFrame.
648 */
649 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
1613d6b4 650 if (eld->info.spk_alloc & (1 << i))
079d88cc
WF		 651 spk_mask |= eld_speaker_allocation_bits[i];
652 }
653
654 /* search for the first working match in the CA table */
655 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
656 if (channels == channel_allocations[i].channels &&
657 (spk_mask & channel_allocations[i].spk_mask) ==
658 channel_allocations[i].spk_mask) {
53d7d69d 659 ca = channel_allocations[i].ca_index;
079d88cc
WF		 660 break;
661 }
662 }
663
18e39186
AH		 664 if (!ca) {
665 /* if there was no match, select the regular ALSA channel
666 * allocation with the matching number of channels */
667 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
668 if (channels == channel_allocations[i].channels) {
669 ca = channel_allocations[i].ca_index;
670 break;
671 }
672 }
673 }
674
1613d6b4 675 snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf));
2abbf439 676 snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n",
53d7d69d 677 ca, channels, buf);
079d88cc 678
53d7d69d 679 return ca;
079d88cc
WF		 680}
681
682static void hdmi_debug_channel_mapping(struct hda_codec *codec,
683 hda_nid_t pin_nid)
684{
685#ifdef CONFIG_SND_DEBUG_VERBOSE
307229d2 686 struct hdmi_spec *spec = codec->spec;
079d88cc 687 int i;
307229d2 688 int channel;
079d88cc
WF		 689
690 for (i = 0; i < 8; i++) {
307229d2 691 channel = spec->ops.pin_get_slot_channel(codec, pin_nid, i);
079d88cc 692 printk(KERN_DEBUG "HDMI: ASP channel %d => slot %d\n",
307229d2 693 channel, i);
079d88cc
WF		 694 }
695#endif
696}
697
d45e6889 698static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
079d88cc 699 hda_nid_t pin_nid,
433968da 700 bool non_pcm,
53d7d69d 701 int ca)
079d88cc 702{
307229d2 703 struct hdmi_spec *spec = codec->spec;
90f28002 704 struct cea_channel_speaker_allocation *ch_alloc;
079d88cc 705 int i;
079d88cc 706 int err;
72357c78 707 int order;
433968da 708 int non_pcm_mapping[8];
079d88cc 709
72357c78 710 order = get_channel_allocation_order(ca);
90f28002 711 ch_alloc = &channel_allocations[order];
433968da 712
079d88cc 713 if (hdmi_channel_mapping[ca][1] == 0) {
90f28002
AH		 714 int hdmi_slot = 0;
715 /* fill actual channel mappings in ALSA channel (i) order */
716 for (i = 0; i < ch_alloc->channels; i++) {
717 while (!ch_alloc->speakers[7 - hdmi_slot] && !WARN_ON(hdmi_slot >= 8))
718 hdmi_slot++; /* skip zero slots */
719
720 hdmi_channel_mapping[ca][i] = (i << 4) | hdmi_slot++;
721 }
722 /* fill the rest of the slots with ALSA channel 0xf */
723 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++)
724 if (!ch_alloc->speakers[7 - hdmi_slot])
725 hdmi_channel_mapping[ca][i++] = (0xf << 4) | hdmi_slot;
079d88cc
WF		 726 }
727
433968da 728 if (non_pcm) {
90f28002 729 for (i = 0; i < ch_alloc->channels; i++)
11f7c52d 730 non_pcm_mapping[i] = (i << 4) | i;
433968da 731 for (; i < 8; i++)
11f7c52d 732 non_pcm_mapping[i] = (0xf << 4) | i;
433968da
WX		 733 }
734
079d88cc 735 for (i = 0; i < 8; i++) {
307229d2
AH		 736 int slotsetup = non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i];
737 int hdmi_slot = slotsetup & 0x0f;
738 int channel = (slotsetup & 0xf0) >> 4;
739 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot, channel);
079d88cc 740 if (err) {
2abbf439
WF		 741 snd_printdd(KERN_NOTICE
742 "HDMI: channel mapping failed\n");
079d88cc
WF		 743 break;
744 }
745 }
079d88cc
WF		 746}
747
d45e6889
TI		 748struct channel_map_table {
749 unsigned char map; /* ALSA API channel map position */
d45e6889
TI		 750 int spk_mask; /* speaker position bit mask */
751};
752
753static struct channel_map_table map_tables[] = {
a5b7d510
AH		 754 { SNDRV_CHMAP_FL, FL },
755 { SNDRV_CHMAP_FR, FR },
756 { SNDRV_CHMAP_RL, RL },
757 { SNDRV_CHMAP_RR, RR },
758 { SNDRV_CHMAP_LFE, LFE },
759 { SNDRV_CHMAP_FC, FC },
760 { SNDRV_CHMAP_RLC, RLC },
761 { SNDRV_CHMAP_RRC, RRC },
762 { SNDRV_CHMAP_RC, RC },
763 { SNDRV_CHMAP_FLC, FLC },
764 { SNDRV_CHMAP_FRC, FRC },
765 { SNDRV_CHMAP_FLH, FLH },
766 { SNDRV_CHMAP_FRH, FRH },
767 { SNDRV_CHMAP_FLW, FLW },
768 { SNDRV_CHMAP_FRW, FRW },
769 { SNDRV_CHMAP_TC, TC },
770 { SNDRV_CHMAP_FCH, FCH },
d45e6889
TI		 771 {} /* terminator */
772};
773
774/* from ALSA API channel position to speaker bit mask */
775static int to_spk_mask(unsigned char c)
776{
777 struct channel_map_table *t = map_tables;
778 for (; t->map; t++) {
779 if (t->map == c)
780 return t->spk_mask;
781 }
782 return 0;
783}
784
785/* from ALSA API channel position to CEA slot */
a5b7d510 786static int to_cea_slot(int ordered_ca, unsigned char pos)
d45e6889 787{
a5b7d510
AH		 788 int mask = to_spk_mask(pos);
789 int i;
d45e6889 790
a5b7d510
AH		 791 if (mask) {
792 for (i = 0; i < 8; i++) {
793 if (channel_allocations[ordered_ca].speakers[7 - i] == mask)
794 return i;
795 }
d45e6889 796 }
a5b7d510
AH		 797
798 return -1;
d45e6889
TI		 799}
800
801/* from speaker bit mask to ALSA API channel position */
802static int spk_to_chmap(int spk)
803{
804 struct channel_map_table *t = map_tables;
805 for (; t->map; t++) {
806 if (t->spk_mask == spk)
807 return t->map;
808 }
809 return 0;
810}
811
a5b7d510
AH		 812/* from CEA slot to ALSA API channel position */
813static int from_cea_slot(int ordered_ca, unsigned char slot)
814{
815 int mask = channel_allocations[ordered_ca].speakers[7 - slot];
816
817 return spk_to_chmap(mask);
818}
819
d45e6889
TI		 820/* get the CA index corresponding to the given ALSA API channel map */
821static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
822{
823 int i, spks = 0, spk_mask = 0;
824
825 for (i = 0; i < chs; i++) {
826 int mask = to_spk_mask(map[i]);
827 if (mask) {
828 spk_mask |= mask;
829 spks++;
830 }
831 }
832
833 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
834 if ((chs == channel_allocations[i].channels ||
835 spks == channel_allocations[i].channels) &&
836 (spk_mask & channel_allocations[i].spk_mask) ==
837 channel_allocations[i].spk_mask)
838 return channel_allocations[i].ca_index;
839 }
840 return -1;
841}
842
843/* set up the channel slots for the given ALSA API channel map */
844static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
845 hda_nid_t pin_nid,
a5b7d510
AH		 846 int chs, unsigned char *map,
847 int ca)
d45e6889 848{
307229d2 849 struct hdmi_spec *spec = codec->spec;
a5b7d510 850 int ordered_ca = get_channel_allocation_order(ca);
11f7c52d
AH		 851 int alsa_pos, hdmi_slot;
852 int assignments[8] = {[0 ... 7] = 0xf};
853
854 for (alsa_pos = 0; alsa_pos < chs; alsa_pos++) {
855
a5b7d510 856 hdmi_slot = to_cea_slot(ordered_ca, map[alsa_pos]);
11f7c52d
AH		 857
858 if (hdmi_slot < 0)
859 continue; /* unassigned channel */
860
861 assignments[hdmi_slot] = alsa_pos;
862 }
863
864 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++) {
307229d2 865 int err;
11f7c52d 866
307229d2
AH		 867 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot,
868 assignments[hdmi_slot]);
d45e6889
TI		 869 if (err)
870 return -EINVAL;
871 }
872 return 0;
873}
874
875/* store ALSA API channel map from the current default map */
876static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
877{
878 int i;
56cac413 879 int ordered_ca = get_channel_allocation_order(ca);
d45e6889 880 for (i = 0; i < 8; i++) {
56cac413 881 if (i < channel_allocations[ordered_ca].channels)
a5b7d510 882 map[i] = from_cea_slot(ordered_ca, hdmi_channel_mapping[ca][i] & 0x0f);
d45e6889
TI		 883 else
884 map[i] = 0;
885 }
886}
887
888static void hdmi_setup_channel_mapping(struct hda_codec *codec,
889 hda_nid_t pin_nid, bool non_pcm, int ca,
20608731
AH		 890 int channels, unsigned char *map,
891 bool chmap_set)
d45e6889 892{
20608731 893 if (!non_pcm && chmap_set) {
d45e6889 894 hdmi_manual_setup_channel_mapping(codec, pin_nid,
a5b7d510 895 channels, map, ca);
d45e6889
TI		 896 } else {
897 hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
898 hdmi_setup_fake_chmap(map, ca);
899 }
980b2495
AH		 900
901 hdmi_debug_channel_mapping(codec, pin_nid);
d45e6889 902}
079d88cc 903
307229d2
AH		 904static int hdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
905 int asp_slot, int channel)
906{
907 return snd_hda_codec_write(codec, pin_nid, 0,
908 AC_VERB_SET_HDMI_CHAN_SLOT,
909 (channel << 4) | asp_slot);
910}
911
912static int hdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
913 int asp_slot)
914{
915 return (snd_hda_codec_read(codec, pin_nid, 0,
916 AC_VERB_GET_HDMI_CHAN_SLOT,
917 asp_slot) & 0xf0) >> 4;
918}
919
079d88cc
WF		 920/*
921 * Audio InfoFrame routines
922 */
923
924/*
925 * Enable Audio InfoFrame Transmission
926 */
927static void hdmi_start_infoframe_trans(struct hda_codec *codec,
928 hda_nid_t pin_nid)
929{
930 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
931 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
932 AC_DIPXMIT_BEST);
933}
934
935/*
936 * Disable Audio InfoFrame Transmission
937 */
938static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
939 hda_nid_t pin_nid)
940{
941 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
942 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
943 AC_DIPXMIT_DISABLE);
944}
945
946static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
947{
948#ifdef CONFIG_SND_DEBUG_VERBOSE
949 int i;
950 int size;
951
952 size = snd_hdmi_get_eld_size(codec, pin_nid);
953 printk(KERN_DEBUG "HDMI: ELD buf size is %d\n", size);
954
955 for (i = 0; i < 8; i++) {
956 size = snd_hda_codec_read(codec, pin_nid, 0,
957 AC_VERB_GET_HDMI_DIP_SIZE, i);
958 printk(KERN_DEBUG "HDMI: DIP GP[%d] buf size is %d\n", i, size);
959 }
960#endif
961}
962
963static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
964{
965#ifdef BE_PARANOID
966 int i, j;
967 int size;
968 int pi, bi;
969 for (i = 0; i < 8; i++) {
970 size = snd_hda_codec_read(codec, pin_nid, 0,
971 AC_VERB_GET_HDMI_DIP_SIZE, i);
972 if (size == 0)
973 continue;
974
975 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
976 for (j = 1; j < 1000; j++) {
977 hdmi_write_dip_byte(codec, pin_nid, 0x0);
978 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
979 if (pi != i)
980 snd_printd(KERN_INFO "dip index %d: %d != %d\n",
981 bi, pi, i);
982 if (bi == 0) /* byte index wrapped around */
983 break;
984 }
985 snd_printd(KERN_INFO
986 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
987 i, size, j);
988 }
989#endif
990}
991
53d7d69d 992static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
079d88cc 993{
53d7d69d 994 u8 *bytes = (u8 *)hdmi_ai;
079d88cc
WF		 995 u8 sum = 0;
996 int i;
997
53d7d69d 998 hdmi_ai->checksum = 0;
079d88cc 999
53d7d69d 1000 for (i = 0; i < sizeof(*hdmi_ai); i++)
079d88cc
WF		 1001 sum += bytes[i];
1002
53d7d69d 1003 hdmi_ai->checksum = -sum;
079d88cc
WF		 1004}
1005
1006static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
1007 hda_nid_t pin_nid,
53d7d69d 1008 u8 *dip, int size)
079d88cc 1009{
079d88cc
WF		 1010 int i;
1011
1012 hdmi_debug_dip_size(codec, pin_nid);
1013 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
1014
079d88cc 1015 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d
WF		 1016 for (i = 0; i < size; i++)
1017 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
079d88cc
WF		 1018}
1019
1020static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
53d7d69d 1021 u8 *dip, int size)
079d88cc 1022{
079d88cc
WF		 1023 u8 val;
1024 int i;
1025
1026 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
1027 != AC_DIPXMIT_BEST)
1028 return false;
1029
1030 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d 1031 for (i = 0; i < size; i++) {
079d88cc
WF		 1032 val = snd_hda_codec_read(codec, pin_nid, 0,
1033 AC_VERB_GET_HDMI_DIP_DATA, 0);
53d7d69d 1034 if (val != dip[i])
079d88cc
WF		 1035 return false;
1036 }
1037
1038 return true;
1039}
1040
307229d2
AH		 1041static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
1042 hda_nid_t pin_nid,
1043 int ca, int active_channels,
1044 int conn_type)
1045{
1046 union audio_infoframe ai;
1047
1048 if (conn_type == 0) { /* HDMI */
1049 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
1050
1051 hdmi_ai->type = 0x84;
1052 hdmi_ai->ver = 0x01;
1053 hdmi_ai->len = 0x0a;
1054 hdmi_ai->CC02_CT47 = active_channels - 1;
1055 hdmi_ai->CA = ca;
1056 hdmi_checksum_audio_infoframe(hdmi_ai);
1057 } else if (conn_type == 1) { /* DisplayPort */
1058 struct dp_audio_infoframe *dp_ai = &ai.dp;
1059
1060 dp_ai->type = 0x84;
1061 dp_ai->len = 0x1b;
1062 dp_ai->ver = 0x11 << 2;
1063 dp_ai->CC02_CT47 = active_channels - 1;
1064 dp_ai->CA = ca;
1065 } else {
1066 snd_printd("HDMI: unknown connection type at pin %d\n",
1067 pin_nid);
1068 return;
1069 }
1070
1071 /*
1072 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
1073 * sizeof(*dp_ai) to avoid partial match/update problems when
1074 * the user switches between HDMI/DP monitors.
1075 */
1076 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
1077 sizeof(ai))) {
1078 snd_printdd("hdmi_pin_setup_infoframe: "
1079 "pin=%d channels=%d ca=0x%02x\n",
1080 pin_nid,
1081 active_channels, ca);
1082 hdmi_stop_infoframe_trans(codec, pin_nid);
1083 hdmi_fill_audio_infoframe(codec, pin_nid,
1084 ai.bytes, sizeof(ai));
1085 hdmi_start_infoframe_trans(codec, pin_nid);
1086 }
1087}
1088
b054087d
TI		 1089static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
1090 struct hdmi_spec_per_pin *per_pin,
1091 bool non_pcm)
079d88cc 1092{
307229d2 1093 struct hdmi_spec *spec = codec->spec;
384a48d7 1094 hda_nid_t pin_nid = per_pin->pin_nid;
b054087d 1095 int channels = per_pin->channels;
1df5a06a 1096 int active_channels;
384a48d7 1097 struct hdmi_eld *eld;
1df5a06a 1098 int ca, ordered_ca;
079d88cc 1099
b054087d
TI		 1100 if (!channels)
1101 return;
1102
58f7d28d
ML		 1103 if (is_haswell(codec))
1104 snd_hda_codec_write(codec, pin_nid, 0,
1105 AC_VERB_SET_AMP_GAIN_MUTE,
1106 AMP_OUT_UNMUTE);
1107
bce0d2a8 1108 eld = &per_pin->sink_eld;
384a48d7
SW		 1109 if (!eld->monitor_present)
1110 return;
079d88cc 1111
d45e6889
TI		 1112 if (!non_pcm && per_pin->chmap_set)
1113 ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
1114 else
1115 ca = hdmi_channel_allocation(eld, channels);
1116 if (ca < 0)
1117 ca = 0;
384a48d7 1118
1df5a06a
AH		 1119 ordered_ca = get_channel_allocation_order(ca);
1120 active_channels = channel_allocations[ordered_ca].channels;
1121
1122 hdmi_set_channel_count(codec, per_pin->cvt_nid, active_channels);
1123
39edac70
AH		 1124 /*
1125 * always configure channel mapping, it may have been changed by the
1126 * user in the meantime
1127 */
1128 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
1129 channels, per_pin->chmap,
1130 per_pin->chmap_set);
1131
307229d2
AH		 1132 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
1133 eld->info.conn_type);
433968da 1134
1a6003b5 1135 per_pin->non_pcm = non_pcm;
079d88cc
WF		 1136}
1137
079d88cc
WF		 1138/*
1139 * Unsolicited events
1140 */
1141
c6e8453e 1142static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
38faddb1 1143
079d88cc
WF		 1144static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
1145{
1146 struct hdmi_spec *spec = codec->spec;
3a93897e
TI		 1147 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1148 int pin_nid;
384a48d7 1149 int pin_idx;
3a93897e 1150 struct hda_jack_tbl *jack;
2e59e5ab 1151 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
3a93897e
TI		 1152
1153 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
1154 if (!jack)
1155 return;
1156 pin_nid = jack->nid;
1157 jack->jack_dirty = 1;
079d88cc 1158
fae3d88a 1159 _snd_printd(SND_PR_VERBOSE,
2e59e5ab
ML		 1160 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
1161 codec->addr, pin_nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
fae3d88a 1162 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
079d88cc 1163
384a48d7
SW		 1164 pin_idx = pin_nid_to_pin_index(spec, pin_nid);
1165 if (pin_idx < 0)
079d88cc
WF		 1166 return;
1167
bce0d2a8 1168 hdmi_present_sense(get_pin(spec, pin_idx), 1);
01a61e12 1169 snd_hda_jack_report_sync(codec);
079d88cc
WF		 1170}
1171
1172static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
1173{
1174 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1175 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1176 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
1177 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
1178
1179 printk(KERN_INFO
e9ea8e8f 1180 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
384a48d7 1181 codec->addr,
079d88cc
WF		 1182 tag,
1183 subtag,
1184 cp_state,
1185 cp_ready);
1186
1187 /* TODO */
1188 if (cp_state)
1189 ;
1190 if (cp_ready)
1191 ;
1192}
1193
1194
1195static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
1196{
079d88cc
WF		 1197 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1198 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1199
3a93897e 1200 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
079d88cc
WF		 1201 snd_printd(KERN_INFO "Unexpected HDMI event tag 0x%x\n", tag);
1202 return;
1203 }
1204
1205 if (subtag == 0)
1206 hdmi_intrinsic_event(codec, res);
1207 else
1208 hdmi_non_intrinsic_event(codec, res);
1209}
1210
58f7d28d 1211static void haswell_verify_D0(struct hda_codec *codec,
53b434f0 1212 hda_nid_t cvt_nid, hda_nid_t nid)
83f26ad2 1213{
58f7d28d 1214 int pwr;
83f26ad2 1215
53b434f0
WX		 1216 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
1217 * thus pins could only choose converter 0 for use. Make sure the
1218 * converters are in correct power state */
fd678cac 1219 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
53b434f0
WX		 1220 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
1221
fd678cac 1222 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
83f26ad2
DH		 1223 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
1224 AC_PWRST_D0);
1225 msleep(40);
1226 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
1227 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
1228 snd_printd("Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
1229 }
83f26ad2
DH		 1230}
1231
079d88cc
WF		 1232/*
1233 * Callbacks
1234 */
1235
92f10b3f
TI		 1236/* HBR should be Non-PCM, 8 channels */
1237#define is_hbr_format(format) \
1238 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
1239
307229d2
AH		 1240static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
1241 bool hbr)
079d88cc 1242{
307229d2 1243 int pinctl, new_pinctl;
83f26ad2 1244
384a48d7
SW		 1245 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
1246 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
ea87d1c4
AH		 1247 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1248
1249 new_pinctl = pinctl & ~AC_PINCTL_EPT;
307229d2 1250 if (hbr)
ea87d1c4
AH		 1251 new_pinctl |= AC_PINCTL_EPT_HBR;
1252 else
1253 new_pinctl |= AC_PINCTL_EPT_NATIVE;
1254
307229d2 1255 snd_printdd("hdmi_pin_hbr_setup: "
ea87d1c4 1256 "NID=0x%x, %spinctl=0x%x\n",
384a48d7 1257 pin_nid,
ea87d1c4
AH		 1258 pinctl == new_pinctl ? "" : "new-",
1259 new_pinctl);
1260
1261 if (pinctl != new_pinctl)
384a48d7 1262 snd_hda_codec_write(codec, pin_nid, 0,
ea87d1c4
AH		 1263 AC_VERB_SET_PIN_WIDGET_CONTROL,
1264 new_pinctl);
307229d2
AH		 1265 } else if (hbr)
1266 return -EINVAL;
ea87d1c4 1267
307229d2
AH		 1268 return 0;
1269}
1270
1271static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
1272 hda_nid_t pin_nid, u32 stream_tag, int format)
1273{
1274 struct hdmi_spec *spec = codec->spec;
1275 int err;
1276
1277 if (is_haswell(codec))
1278 haswell_verify_D0(codec, cvt_nid, pin_nid);
1279
1280 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
1281
1282 if (err) {
ea87d1c4 1283 snd_printdd("hdmi_setup_stream: HBR is not supported\n");
307229d2 1284 return err;
ea87d1c4 1285 }
079d88cc 1286
384a48d7 1287 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
ea87d1c4 1288 return 0;
079d88cc
WF		 1289}
1290
7ef166b8
WX		 1291static int hdmi_choose_cvt(struct hda_codec *codec,
1292 int pin_idx, int *cvt_id, int *mux_id)
bbbe3390
TI		 1293{
1294 struct hdmi_spec *spec = codec->spec;
384a48d7 1295 struct hdmi_spec_per_pin *per_pin;
384a48d7 1296 struct hdmi_spec_per_cvt *per_cvt = NULL;
7ef166b8 1297 int cvt_idx, mux_idx = 0;
bbbe3390 1298
bce0d2a8 1299 per_pin = get_pin(spec, pin_idx);
384a48d7
SW		 1300
1301 /* Dynamically assign converter to stream */
1302 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
bce0d2a8 1303 per_cvt = get_cvt(spec, cvt_idx);
bbbe3390 1304
384a48d7
SW		 1305 /* Must not already be assigned */
1306 if (per_cvt->assigned)
1307 continue;
1308 /* Must be in pin's mux's list of converters */
1309 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1310 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1311 break;
1312 /* Not in mux list */
1313 if (mux_idx == per_pin->num_mux_nids)
1314 continue;
1315 break;
1316 }
7ef166b8 1317
384a48d7
SW		 1318 /* No free converters */
1319 if (cvt_idx == spec->num_cvts)
1320 return -ENODEV;
1321
7ef166b8
WX		 1322 if (cvt_id)
1323 *cvt_id = cvt_idx;
1324 if (mux_id)
1325 *mux_id = mux_idx;
1326
1327 return 0;
1328}
1329
1330static void haswell_config_cvts(struct hda_codec *codec,
f82d7d16 1331 hda_nid_t pin_nid, int mux_idx)
7ef166b8
WX		 1332{
1333 struct hdmi_spec *spec = codec->spec;
f82d7d16
ML		 1334 hda_nid_t nid, end_nid;
1335 int cvt_idx, curr;
1336 struct hdmi_spec_per_cvt *per_cvt;
7ef166b8 1337
f82d7d16
ML		 1338 /* configure all pins, including "no physical connection" ones */
1339 end_nid = codec->start_nid + codec->num_nodes;
1340 for (nid = codec->start_nid; nid < end_nid; nid++) {
1341 unsigned int wid_caps = get_wcaps(codec, nid);
1342 unsigned int wid_type = get_wcaps_type(wid_caps);
1343
1344 if (wid_type != AC_WID_PIN)
1345 continue;
7ef166b8 1346
f82d7d16 1347 if (nid == pin_nid)
7ef166b8
WX		 1348 continue;
1349
f82d7d16 1350 curr = snd_hda_codec_read(codec, nid, 0,
7ef166b8 1351 AC_VERB_GET_CONNECT_SEL, 0);
f82d7d16
ML		 1352 if (curr != mux_idx)
1353 continue;
7ef166b8 1354
f82d7d16
ML		 1355 /* choose an unassigned converter. The conveters in the
1356 * connection list are in the same order as in the codec.
1357 */
1358 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1359 per_cvt = get_cvt(spec, cvt_idx);
1360 if (!per_cvt->assigned) {
1361 snd_printdd("choose cvt %d for pin nid %d\n",
1362 cvt_idx, nid);
1363 snd_hda_codec_write_cache(codec, nid, 0,
7ef166b8 1364 AC_VERB_SET_CONNECT_SEL,
f82d7d16
ML		 1365 cvt_idx);
1366 break;
1367 }
7ef166b8
WX		 1368 }
1369 }
1370}
1371
1372/*
1373 * HDA PCM callbacks
1374 */
1375static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1376 struct hda_codec *codec,
1377 struct snd_pcm_substream *substream)
1378{
1379 struct hdmi_spec *spec = codec->spec;
1380 struct snd_pcm_runtime *runtime = substream->runtime;
1381 int pin_idx, cvt_idx, mux_idx = 0;
1382 struct hdmi_spec_per_pin *per_pin;
1383 struct hdmi_eld *eld;
1384 struct hdmi_spec_per_cvt *per_cvt = NULL;
1385 int err;
1386
1387 /* Validate hinfo */
1388 pin_idx = hinfo_to_pin_index(spec, hinfo);
1389 if (snd_BUG_ON(pin_idx < 0))
1390 return -EINVAL;
1391 per_pin = get_pin(spec, pin_idx);
1392 eld = &per_pin->sink_eld;
1393
1394 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx);
1395 if (err < 0)
1396 return err;
1397
1398 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1399 /* Claim converter */
1400 per_cvt->assigned = 1;
1df5a06a 1401 per_pin->cvt_nid = per_cvt->cvt_nid;
384a48d7
SW		 1402 hinfo->nid = per_cvt->cvt_nid;
1403
bddee96b 1404 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
384a48d7
SW		 1405 AC_VERB_SET_CONNECT_SEL,
1406 mux_idx);
7ef166b8
WX		 1407
1408 /* configure unused pins to choose other converters */
fb87fa3a 1409 if (is_haswell(codec))
f82d7d16 1410 haswell_config_cvts(codec, per_pin->pin_nid, mux_idx);
7ef166b8 1411
384a48d7 1412 snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
bbbe3390 1413
2def8172 1414 /* Initially set the converter's capabilities */
384a48d7
SW		 1415 hinfo->channels_min = per_cvt->channels_min;
1416 hinfo->channels_max = per_cvt->channels_max;
1417 hinfo->rates = per_cvt->rates;
1418 hinfo->formats = per_cvt->formats;
1419 hinfo->maxbps = per_cvt->maxbps;
2def8172 1420
384a48d7 1421 /* Restrict capabilities by ELD if this isn't disabled */
c3d52105 1422 if (!static_hdmi_pcm && eld->eld_valid) {
1613d6b4 1423 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
bbbe3390 1424 if (hinfo->channels_min > hinfo->channels_max ||
2ad779b7
TI		 1425 !hinfo->rates || !hinfo->formats) {
1426 per_cvt->assigned = 0;
1427 hinfo->nid = 0;
1428 snd_hda_spdif_ctls_unassign(codec, pin_idx);
bbbe3390 1429 return -ENODEV;
2ad779b7 1430 }
bbbe3390 1431 }
2def8172
SW		 1432
1433 /* Store the updated parameters */
639cef0e
TI		 1434 runtime->hw.channels_min = hinfo->channels_min;
1435 runtime->hw.channels_max = hinfo->channels_max;
1436 runtime->hw.formats = hinfo->formats;
1437 runtime->hw.rates = hinfo->rates;
4fe2ca14
TI		 1438
1439 snd_pcm_hw_constraint_step(substream->runtime, 0,
1440 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
bbbe3390
TI		 1441 return 0;
1442}
1443
079d88cc
WF		 1444/*
1445 * HDA/HDMI auto parsing
1446 */
384a48d7 1447static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
079d88cc
WF		 1448{
1449 struct hdmi_spec *spec = codec->spec;
bce0d2a8 1450 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1451 hda_nid_t pin_nid = per_pin->pin_nid;
079d88cc
WF		 1452
1453 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1454 snd_printk(KERN_WARNING
1455 "HDMI: pin %d wcaps %#x "
1456 "does not support connection list\n",
1457 pin_nid, get_wcaps(codec, pin_nid));
1458 return -EINVAL;
1459 }
1460
384a48d7
SW		 1461 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1462 per_pin->mux_nids,
1463 HDA_MAX_CONNECTIONS);
079d88cc
WF		 1464
1465 return 0;
1466}
1467
c6e8453e 1468static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
079d88cc 1469{
744626da 1470 struct hda_codec *codec = per_pin->codec;
4bd038f9
DH		 1471 struct hdmi_spec *spec = codec->spec;
1472 struct hdmi_eld *eld = &spec->temp_eld;
1473 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
744626da 1474 hda_nid_t pin_nid = per_pin->pin_nid;
5d44f927
SW		 1475 /*
1476 * Always execute a GetPinSense verb here, even when called from
1477 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1478 * response's PD bit is not the real PD value, but indicates that
1479 * the real PD value changed. An older version of the HD-audio
1480 * specification worked this way. Hence, we just ignore the data in
1481 * the unsolicited response to avoid custom WARs.
1482 */
079d88cc 1483 int present = snd_hda_pin_sense(codec, pin_nid);
4bd038f9
DH		 1484 bool update_eld = false;
1485 bool eld_changed = false;
079d88cc 1486
a4e9a38b 1487 mutex_lock(&per_pin->lock);
4bd038f9
DH		 1488 pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1489 if (pin_eld->monitor_present)
1490 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1491 else
1492 eld->eld_valid = false;
079d88cc 1493
fae3d88a 1494 _snd_printd(SND_PR_VERBOSE,
384a48d7 1495 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
10250911 1496 codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
5d44f927 1497
4bd038f9 1498 if (eld->eld_valid) {
307229d2 1499 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1613d6b4 1500 &eld->eld_size) < 0)
4bd038f9 1501 eld->eld_valid = false;
1613d6b4
DH		 1502 else {
1503 memset(&eld->info, 0, sizeof(struct parsed_hdmi_eld));
1504 if (snd_hdmi_parse_eld(&eld->info, eld->eld_buffer,
1505 eld->eld_size) < 0)
4bd038f9 1506 eld->eld_valid = false;
1613d6b4
DH		 1507 }
1508
4bd038f9 1509 if (eld->eld_valid) {
1613d6b4 1510 snd_hdmi_show_eld(&eld->info);
4bd038f9 1511 update_eld = true;
1613d6b4 1512 }
c6e8453e 1513 else if (repoll) {
744626da
WF		 1514 queue_delayed_work(codec->bus->workq,
1515 &per_pin->work,
1516 msecs_to_jiffies(300));
cbbaa603 1517 goto unlock;
744626da
WF		 1518 }
1519 }
4bd038f9 1520
92c69e79 1521 if (pin_eld->eld_valid && !eld->eld_valid) {
4bd038f9 1522 update_eld = true;
92c69e79
DH		 1523 eld_changed = true;
1524 }
4bd038f9 1525 if (update_eld) {
b054087d 1526 bool old_eld_valid = pin_eld->eld_valid;
4bd038f9 1527 pin_eld->eld_valid = eld->eld_valid;
92c69e79
DH		 1528 eld_changed = pin_eld->eld_size != eld->eld_size ||
1529 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
4bd038f9
DH		 1530 eld->eld_size) != 0;
1531 if (eld_changed)
1532 memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1533 eld->eld_size);
1534 pin_eld->eld_size = eld->eld_size;
1535 pin_eld->info = eld->info;
b054087d 1536
7342017f
AH		 1537 /*
1538 * Re-setup pin and infoframe. This is needed e.g. when
1539 * - sink is first plugged-in (infoframe is not set up if !monitor_present)
1540 * - transcoder can change during stream playback on Haswell
b054087d 1541 */
7342017f 1542 if (eld->eld_valid && !old_eld_valid && per_pin->setup)
b054087d
TI		 1543 hdmi_setup_audio_infoframe(codec, per_pin,
1544 per_pin->non_pcm);
4bd038f9 1545 }
92c69e79
DH		 1546
1547 if (eld_changed)
1548 snd_ctl_notify(codec->bus->card,
1549 SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO,
1550 &per_pin->eld_ctl->id);
cbbaa603 1551 unlock:
a4e9a38b 1552 mutex_unlock(&per_pin->lock);
079d88cc
WF		 1553}
1554
744626da
WF		 1555static void hdmi_repoll_eld(struct work_struct *work)
1556{
1557 struct hdmi_spec_per_pin *per_pin =
1558 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1559
c6e8453e
WF		 1560 if (per_pin->repoll_count++ > 6)
1561 per_pin->repoll_count = 0;
1562
1563 hdmi_present_sense(per_pin, per_pin->repoll_count);
744626da
WF		 1564}
1565
c88d4e84
TI		 1566static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1567 hda_nid_t nid);
1568
079d88cc
WF		 1569static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1570{
1571 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1572 unsigned int caps, config;
1573 int pin_idx;
1574 struct hdmi_spec_per_pin *per_pin;
07acecc1 1575 int err;
079d88cc 1576
efc2f8de 1577 caps = snd_hda_query_pin_caps(codec, pin_nid);
384a48d7
SW		 1578 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1579 return 0;
1580
efc2f8de 1581 config = snd_hda_codec_get_pincfg(codec, pin_nid);
384a48d7
SW		 1582 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1583 return 0;
1584
fb87fa3a 1585 if (is_haswell(codec))
c88d4e84
TI		 1586 intel_haswell_fixup_connect_list(codec, pin_nid);
1587
384a48d7 1588 pin_idx = spec->num_pins;
bce0d2a8
TI		 1589 per_pin = snd_array_new(&spec->pins);
1590 if (!per_pin)
1591 return -ENOMEM;
384a48d7
SW		 1592
1593 per_pin->pin_nid = pin_nid;
1a6003b5 1594 per_pin->non_pcm = false;
079d88cc 1595
384a48d7
SW		 1596 err = hdmi_read_pin_conn(codec, pin_idx);
1597 if (err < 0)
1598 return err;
079d88cc 1599
079d88cc
WF		 1600 spec->num_pins++;
1601
384a48d7 1602 return 0;
079d88cc
WF		 1603}
1604
384a48d7 1605static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc
WF		 1606{
1607 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1608 struct hdmi_spec_per_cvt *per_cvt;
1609 unsigned int chans;
1610 int err;
079d88cc 1611
384a48d7
SW		 1612 chans = get_wcaps(codec, cvt_nid);
1613 chans = get_wcaps_channels(chans);
1614
bce0d2a8
TI		 1615 per_cvt = snd_array_new(&spec->cvts);
1616 if (!per_cvt)
1617 return -ENOMEM;
384a48d7
SW		 1618
1619 per_cvt->cvt_nid = cvt_nid;
1620 per_cvt->channels_min = 2;
d45e6889 1621 if (chans <= 16) {
384a48d7 1622 per_cvt->channels_max = chans;
d45e6889
TI		 1623 if (chans > spec->channels_max)
1624 spec->channels_max = chans;
1625 }
384a48d7
SW		 1626
1627 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1628 &per_cvt->rates,
1629 &per_cvt->formats,
1630 &per_cvt->maxbps);
1631 if (err < 0)
1632 return err;
1633
bce0d2a8
TI		 1634 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1635 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1636 spec->num_cvts++;
079d88cc
WF		 1637
1638 return 0;
1639}
1640
1641static int hdmi_parse_codec(struct hda_codec *codec)
1642{
1643 hda_nid_t nid;
1644 int i, nodes;
1645
1646 nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid);
1647 if (!nid || nodes < 0) {
1648 snd_printk(KERN_WARNING "HDMI: failed to get afg sub nodes\n");
1649 return -EINVAL;
1650 }
1651
1652 for (i = 0; i < nodes; i++, nid++) {
1653 unsigned int caps;
1654 unsigned int type;
1655
efc2f8de 1656 caps = get_wcaps(codec, nid);
079d88cc
WF		 1657 type = get_wcaps_type(caps);
1658
1659 if (!(caps & AC_WCAP_DIGITAL))
1660 continue;
1661
1662 switch (type) {
1663 case AC_WID_AUD_OUT:
384a48d7 1664 hdmi_add_cvt(codec, nid);
079d88cc
WF		 1665 break;
1666 case AC_WID_PIN:
3eaead57 1667 hdmi_add_pin(codec, nid);
079d88cc
WF		 1668 break;
1669 }
1670 }
1671
c9adeefd
DH		 1672#ifdef CONFIG_PM
1673 /* We're seeing some problems with unsolicited hot plug events on
1674 * PantherPoint after S3, if this is not enabled */
1675 if (codec->vendor_id == 0x80862806)
1676 codec->bus->power_keep_link_on = 1;
079d88cc
WF		 1677 /*
1678 * G45/IbexPeak don't support EPSS: the unsolicited pin hot plug event
1679 * can be lost and presence sense verb will become inaccurate if the
1680 * HDA link is powered off at hot plug or hw initialization time.
1681 */
c9adeefd 1682 else if (!(snd_hda_param_read(codec, codec->afg, AC_PAR_POWER_STATE) &
079d88cc
WF		 1683 AC_PWRST_EPSS))
1684 codec->bus->power_keep_link_on = 1;
1685#endif
1686
1687 return 0;
1688}
1689
84eb01be
TI		 1690/*
1691 */
1a6003b5
TI		 1692static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1693{
1694 struct hda_spdif_out *spdif;
1695 bool non_pcm;
1696
1697 mutex_lock(&codec->spdif_mutex);
1698 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1699 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1700 mutex_unlock(&codec->spdif_mutex);
1701 return non_pcm;
1702}
1703
1704
84eb01be
TI		 1705/*
1706 * HDMI callbacks
1707 */
1708
1709static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1710 struct hda_codec *codec,
1711 unsigned int stream_tag,
1712 unsigned int format,
1713 struct snd_pcm_substream *substream)
1714{
384a48d7
SW		 1715 hda_nid_t cvt_nid = hinfo->nid;
1716 struct hdmi_spec *spec = codec->spec;
1717 int pin_idx = hinfo_to_pin_index(spec, hinfo);
b054087d
TI		 1718 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1719 hda_nid_t pin_nid = per_pin->pin_nid;
1a6003b5
TI		 1720 bool non_pcm;
1721
1722 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
a4e9a38b 1723 mutex_lock(&per_pin->lock);
b054087d
TI		 1724 per_pin->channels = substream->runtime->channels;
1725 per_pin->setup = true;
384a48d7 1726
b054087d 1727 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
a4e9a38b 1728 mutex_unlock(&per_pin->lock);
84eb01be 1729
307229d2 1730 return spec->ops.setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
84eb01be
TI		 1731}
1732
8dfaa573
TI		 1733static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1734 struct hda_codec *codec,
1735 struct snd_pcm_substream *substream)
1736{
1737 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1738 return 0;
1739}
1740
f2ad24fa
TI		 1741static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1742 struct hda_codec *codec,
1743 struct snd_pcm_substream *substream)
384a48d7
SW		 1744{
1745 struct hdmi_spec *spec = codec->spec;
1746 int cvt_idx, pin_idx;
1747 struct hdmi_spec_per_cvt *per_cvt;
1748 struct hdmi_spec_per_pin *per_pin;
384a48d7 1749
384a48d7
SW		 1750 if (hinfo->nid) {
1751 cvt_idx = cvt_nid_to_cvt_index(spec, hinfo->nid);
1752 if (snd_BUG_ON(cvt_idx < 0))
1753 return -EINVAL;
bce0d2a8 1754 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1755
1756 snd_BUG_ON(!per_cvt->assigned);
1757 per_cvt->assigned = 0;
1758 hinfo->nid = 0;
1759
1760 pin_idx = hinfo_to_pin_index(spec, hinfo);
1761 if (snd_BUG_ON(pin_idx < 0))
1762 return -EINVAL;
bce0d2a8 1763 per_pin = get_pin(spec, pin_idx);
384a48d7 1764
384a48d7 1765 snd_hda_spdif_ctls_unassign(codec, pin_idx);
cbbaa603 1766
a4e9a38b 1767 mutex_lock(&per_pin->lock);
d45e6889
TI		 1768 per_pin->chmap_set = false;
1769 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
b054087d
TI		 1770
1771 per_pin->setup = false;
1772 per_pin->channels = 0;
a4e9a38b 1773 mutex_unlock(&per_pin->lock);
384a48d7 1774 }
d45e6889 1775
384a48d7
SW		 1776 return 0;
1777}
1778
1779static const struct hda_pcm_ops generic_ops = {
1780 .open = hdmi_pcm_open,
f2ad24fa 1781 .close = hdmi_pcm_close,
384a48d7 1782 .prepare = generic_hdmi_playback_pcm_prepare,
8dfaa573 1783 .cleanup = generic_hdmi_playback_pcm_cleanup,
84eb01be
TI		 1784};
1785
d45e6889
TI		 1786/*
1787 * ALSA API channel-map control callbacks
1788 */
1789static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
1790 struct snd_ctl_elem_info *uinfo)
1791{
1792 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1793 struct hda_codec *codec = info->private_data;
1794 struct hdmi_spec *spec = codec->spec;
1795 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1796 uinfo->count = spec->channels_max;
1797 uinfo->value.integer.min = 0;
1798 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
1799 return 0;
1800}
1801
307229d2
AH		 1802static int hdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
1803 int channels)
1804{
1805 /* If the speaker allocation matches the channel count, it is OK.*/
1806 if (cap->channels != channels)
1807 return -1;
1808
1809 /* all channels are remappable freely */
1810 return SNDRV_CTL_TLVT_CHMAP_VAR;
1811}
1812
1813static void hdmi_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
1814 unsigned int *chmap, int channels)
1815{
1816 int count = 0;
1817 int c;
1818
1819 for (c = 7; c >= 0; c--) {
1820 int spk = cap->speakers[c];
1821 if (!spk)
1822 continue;
1823
1824 chmap[count++] = spk_to_chmap(spk);
1825 }
1826
1827 WARN_ON(count != channels);
1828}
1829
d45e6889
TI		 1830static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
1831 unsigned int size, unsigned int __user *tlv)
1832{
1833 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1834 struct hda_codec *codec = info->private_data;
1835 struct hdmi_spec *spec = codec->spec;
d45e6889
TI		 1836 unsigned int __user *dst;
1837 int chs, count = 0;
1838
1839 if (size < 8)
1840 return -ENOMEM;
1841 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
1842 return -EFAULT;
1843 size -= 8;
1844 dst = tlv + 2;
498dab3a 1845 for (chs = 2; chs <= spec->channels_max; chs++) {
307229d2 1846 int i;
d45e6889
TI		 1847 struct cea_channel_speaker_allocation *cap;
1848 cap = channel_allocations;
1849 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
1850 int chs_bytes = chs * 4;
307229d2
AH		 1851 int type = spec->ops.chmap_cea_alloc_validate_get_type(cap, chs);
1852 unsigned int tlv_chmap[8];
1853
1854 if (type < 0)
d45e6889 1855 continue;
d45e6889
TI		 1856 if (size < 8)
1857 return -ENOMEM;
307229d2 1858 if (put_user(type, dst) ||
d45e6889
TI		 1859 put_user(chs_bytes, dst + 1))
1860 return -EFAULT;
1861 dst += 2;
1862 size -= 8;
1863 count += 8;
1864 if (size < chs_bytes)
1865 return -ENOMEM;
1866 size -= chs_bytes;
1867 count += chs_bytes;
307229d2
AH		 1868 spec->ops.cea_alloc_to_tlv_chmap(cap, tlv_chmap, chs);
1869 if (copy_to_user(dst, tlv_chmap, chs_bytes))
1870 return -EFAULT;
1871 dst += chs;
d45e6889
TI		 1872 }
1873 }
1874 if (put_user(count, tlv + 1))
1875 return -EFAULT;
1876 return 0;
1877}
1878
1879static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
1880 struct snd_ctl_elem_value *ucontrol)
1881{
1882 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1883 struct hda_codec *codec = info->private_data;
1884 struct hdmi_spec *spec = codec->spec;
1885 int pin_idx = kcontrol->private_value;
bce0d2a8 1886 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
d45e6889
TI		 1887 int i;
1888
1889 for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
1890 ucontrol->value.integer.value[i] = per_pin->chmap[i];
1891 return 0;
1892}
1893
1894static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
1895 struct snd_ctl_elem_value *ucontrol)
1896{
1897 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1898 struct hda_codec *codec = info->private_data;
1899 struct hdmi_spec *spec = codec->spec;
1900 int pin_idx = kcontrol->private_value;
bce0d2a8 1901 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
d45e6889
TI		 1902 unsigned int ctl_idx;
1903 struct snd_pcm_substream *substream;
1904 unsigned char chmap[8];
307229d2 1905 int i, err, ca, prepared = 0;
d45e6889
TI		 1906
1907 ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
1908 substream = snd_pcm_chmap_substream(info, ctl_idx);
1909 if (!substream || !substream->runtime)
6f54c361 1910 return 0; /* just for avoiding error from alsactl restore */
d45e6889
TI		 1911 switch (substream->runtime->status->state) {
1912 case SNDRV_PCM_STATE_OPEN:
1913 case SNDRV_PCM_STATE_SETUP:
1914 break;
1915 case SNDRV_PCM_STATE_PREPARED:
1916 prepared = 1;
1917 break;
1918 default:
1919 return -EBUSY;
1920 }
1921 memset(chmap, 0, sizeof(chmap));
1922 for (i = 0; i < ARRAY_SIZE(chmap); i++)
1923 chmap[i] = ucontrol->value.integer.value[i];
1924 if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
1925 return 0;
1926 ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
1927 if (ca < 0)
1928 return -EINVAL;
307229d2
AH		 1929 if (spec->ops.chmap_validate) {
1930 err = spec->ops.chmap_validate(ca, ARRAY_SIZE(chmap), chmap);
1931 if (err)
1932 return err;
1933 }
a4e9a38b 1934 mutex_lock(&per_pin->lock);
d45e6889
TI		 1935 per_pin->chmap_set = true;
1936 memcpy(per_pin->chmap, chmap, sizeof(chmap));
1937 if (prepared)
b054087d 1938 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
a4e9a38b 1939 mutex_unlock(&per_pin->lock);
d45e6889
TI		 1940
1941 return 0;
1942}
1943
84eb01be
TI		 1944static int generic_hdmi_build_pcms(struct hda_codec *codec)
1945{
1946 struct hdmi_spec *spec = codec->spec;
384a48d7 1947 int pin_idx;
84eb01be 1948
384a48d7
SW		 1949 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1950 struct hda_pcm *info;
84eb01be 1951 struct hda_pcm_stream *pstr;
bce0d2a8
TI		 1952 struct hdmi_spec_per_pin *per_pin;
1953
1954 per_pin = get_pin(spec, pin_idx);
1955 sprintf(per_pin->pcm_name, "HDMI %d", pin_idx);
1956 info = snd_array_new(&spec->pcm_rec);
1957 if (!info)
1958 return -ENOMEM;
1959 info->name = per_pin->pcm_name;
84eb01be 1960 info->pcm_type = HDA_PCM_TYPE_HDMI;
d45e6889 1961 info->own_chmap = true;
384a48d7 1962
84eb01be 1963 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
384a48d7
SW		 1964 pstr->substreams = 1;
1965 pstr->ops = generic_ops;
1966 /* other pstr fields are set in open */
84eb01be
TI		 1967 }
1968
384a48d7 1969 codec->num_pcms = spec->num_pins;
bce0d2a8 1970 codec->pcm_info = spec->pcm_rec.list;
384a48d7 1971
84eb01be
TI		 1972 return 0;
1973}
1974
0b6c49b5
DH		 1975static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
1976{
31ef2257 1977 char hdmi_str[32] = "HDMI/DP";
0b6c49b5 1978 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 1979 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1980 int pcmdev = get_pcm_rec(spec, pin_idx)->device;
0b6c49b5 1981
31ef2257
TI		 1982 if (pcmdev > 0)
1983 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
30efd8de
DH		 1984 if (!is_jack_detectable(codec, per_pin->pin_nid))
1985 strncat(hdmi_str, " Phantom",
1986 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
0b6c49b5 1987
31ef2257 1988 return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, 0);
0b6c49b5
DH		 1989}
1990
84eb01be
TI		 1991static int generic_hdmi_build_controls(struct hda_codec *codec)
1992{
1993 struct hdmi_spec *spec = codec->spec;
1994 int err;
384a48d7 1995 int pin_idx;
84eb01be 1996
384a48d7 1997 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 1998 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
0b6c49b5
DH		 1999
2000 err = generic_hdmi_build_jack(codec, pin_idx);
2001 if (err < 0)
2002 return err;
2003
dcda5806
TI		 2004 err = snd_hda_create_dig_out_ctls(codec,
2005 per_pin->pin_nid,
2006 per_pin->mux_nids[0],
2007 HDA_PCM_TYPE_HDMI);
84eb01be
TI		 2008 if (err < 0)
2009 return err;
384a48d7 2010 snd_hda_spdif_ctls_unassign(codec, pin_idx);
14bc52b8
PLB		 2011
2012 /* add control for ELD Bytes */
bce0d2a8
TI		 2013 err = hdmi_create_eld_ctl(codec, pin_idx,
2014 get_pcm_rec(spec, pin_idx)->device);
14bc52b8
PLB		 2015
2016 if (err < 0)
2017 return err;
31ef2257 2018
82b1d73f 2019 hdmi_present_sense(per_pin, 0);
84eb01be
TI		 2020 }
2021
d45e6889
TI		 2022 /* add channel maps */
2023 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2024 struct snd_pcm_chmap *chmap;
2025 struct snd_kcontrol *kctl;
2026 int i;
2ca320e2
TI		 2027
2028 if (!codec->pcm_info[pin_idx].pcm)
2029 break;
d45e6889
TI		 2030 err = snd_pcm_add_chmap_ctls(codec->pcm_info[pin_idx].pcm,
2031 SNDRV_PCM_STREAM_PLAYBACK,
2032 NULL, 0, pin_idx, &chmap);
2033 if (err < 0)
2034 return err;
2035 /* override handlers */
2036 chmap->private_data = codec;
2037 kctl = chmap->kctl;
2038 for (i = 0; i < kctl->count; i++)
2039 kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
2040 kctl->info = hdmi_chmap_ctl_info;
2041 kctl->get = hdmi_chmap_ctl_get;
2042 kctl->put = hdmi_chmap_ctl_put;
2043 kctl->tlv.c = hdmi_chmap_ctl_tlv;
2044 }
2045
84eb01be
TI		 2046 return 0;
2047}
2048
8b8d654b 2049static int generic_hdmi_init_per_pins(struct hda_codec *codec)
84eb01be
TI		 2050{
2051 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 2052 int pin_idx;
2053
2054 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2055 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
84eb01be 2056
744626da 2057 per_pin->codec = codec;
a4e9a38b 2058 mutex_init(&per_pin->lock);
744626da 2059 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
a4e9a38b 2060 eld_proc_new(per_pin, pin_idx);
84eb01be 2061 }
8b8d654b
TI		 2062 return 0;
2063}
2064
2065static int generic_hdmi_init(struct hda_codec *codec)
2066{
2067 struct hdmi_spec *spec = codec->spec;
2068 int pin_idx;
2069
2070 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2071 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
8b8d654b
TI		 2072 hda_nid_t pin_nid = per_pin->pin_nid;
2073
2074 hdmi_init_pin(codec, pin_nid);
2075 snd_hda_jack_detect_enable(codec, pin_nid, pin_nid);
2076 }
84eb01be
TI		 2077 return 0;
2078}
2079
bce0d2a8
TI		 2080static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2081{
2082 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2083 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2084 snd_array_init(&spec->pcm_rec, sizeof(struct hda_pcm), nums);
2085}
2086
2087static void hdmi_array_free(struct hdmi_spec *spec)
2088{
2089 snd_array_free(&spec->pins);
2090 snd_array_free(&spec->cvts);
2091 snd_array_free(&spec->pcm_rec);
2092}
2093
84eb01be
TI		 2094static void generic_hdmi_free(struct hda_codec *codec)
2095{
2096 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 2097 int pin_idx;
2098
2099 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 2100 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
84eb01be 2101
744626da 2102 cancel_delayed_work(&per_pin->work);
a4e9a38b 2103 eld_proc_free(per_pin);
384a48d7 2104 }
84eb01be 2105
744626da 2106 flush_workqueue(codec->bus->workq);
bce0d2a8 2107 hdmi_array_free(spec);
84eb01be
TI		 2108 kfree(spec);
2109}
2110
28cb72e5
WX		 2111#ifdef CONFIG_PM
2112static int generic_hdmi_resume(struct hda_codec *codec)
2113{
2114 struct hdmi_spec *spec = codec->spec;
2115 int pin_idx;
2116
2117 generic_hdmi_init(codec);
2118 snd_hda_codec_resume_amp(codec);
2119 snd_hda_codec_resume_cache(codec);
2120
2121 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2122 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2123 hdmi_present_sense(per_pin, 1);
2124 }
2125 return 0;
2126}
2127#endif
2128
fb79e1e0 2129static const struct hda_codec_ops generic_hdmi_patch_ops = {
84eb01be
TI		 2130 .init = generic_hdmi_init,
2131 .free = generic_hdmi_free,
2132 .build_pcms = generic_hdmi_build_pcms,
2133 .build_controls = generic_hdmi_build_controls,
2134 .unsol_event = hdmi_unsol_event,
28cb72e5
WX		 2135#ifdef CONFIG_PM
2136 .resume = generic_hdmi_resume,
2137#endif
84eb01be
TI		 2138};
2139
307229d2
AH		 2140static const struct hdmi_ops generic_standard_hdmi_ops = {
2141 .pin_get_eld = snd_hdmi_get_eld,
2142 .pin_get_slot_channel = hdmi_pin_get_slot_channel,
2143 .pin_set_slot_channel = hdmi_pin_set_slot_channel,
2144 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2145 .pin_hbr_setup = hdmi_pin_hbr_setup,
2146 .setup_stream = hdmi_setup_stream,
2147 .chmap_cea_alloc_validate_get_type = hdmi_chmap_cea_alloc_validate_get_type,
2148 .cea_alloc_to_tlv_chmap = hdmi_cea_alloc_to_tlv_chmap,
2149};
2150
6ffe168f 2151
c88d4e84
TI		 2152static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2153 hda_nid_t nid)
2154{
2155 struct hdmi_spec *spec = codec->spec;
2156 hda_nid_t conns[4];
2157 int nconns;
6ffe168f 2158
c88d4e84
TI		 2159 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2160 if (nconns == spec->num_cvts &&
2161 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
6ffe168f
ML		 2162 return;
2163
c88d4e84
TI		 2164 /* override pins connection list */
2165 snd_printdd("hdmi: haswell: override pin connection 0x%x\n", nid);
2166 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
6ffe168f
ML		 2167}
2168
1611a9c9
ML		 2169#define INTEL_VENDOR_NID 0x08
2170#define INTEL_GET_VENDOR_VERB 0xf81
2171#define INTEL_SET_VENDOR_VERB 0x781
2172#define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2173#define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2174
2175static void intel_haswell_enable_all_pins(struct hda_codec *codec,
17df3f55 2176 bool update_tree)
1611a9c9
ML		 2177{
2178 unsigned int vendor_param;
2179
1611a9c9
ML		 2180 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2181 INTEL_GET_VENDOR_VERB, 0);
2182 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2183 return;
2184
2185 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2186 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2187 INTEL_SET_VENDOR_VERB, vendor_param);
2188 if (vendor_param == -1)
2189 return;
2190
17df3f55
TI		 2191 if (update_tree)
2192 snd_hda_codec_update_widgets(codec);
1611a9c9
ML		 2193}
2194
c88d4e84
TI		 2195static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2196{
2197 unsigned int vendor_param;
2198
2199 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2200 INTEL_GET_VENDOR_VERB, 0);
2201 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2202 return;
2203
2204 /* enable DP1.2 mode */
2205 vendor_param |= INTEL_EN_DP12;
2206 snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
2207 INTEL_SET_VENDOR_VERB, vendor_param);
2208}
2209
17df3f55
TI		 2210/* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2211 * Otherwise you may get severe h/w communication errors.
2212 */
2213static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2214 unsigned int power_state)
2215{
2216 if (power_state == AC_PWRST_D0) {
2217 intel_haswell_enable_all_pins(codec, false);
2218 intel_haswell_fixup_enable_dp12(codec);
2219 }
c88d4e84 2220
17df3f55
TI		 2221 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2222 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2223}
6ffe168f 2224
84eb01be
TI		 2225static int patch_generic_hdmi(struct hda_codec *codec)
2226{
2227 struct hdmi_spec *spec;
84eb01be
TI		 2228
2229 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2230 if (spec == NULL)
2231 return -ENOMEM;
2232
307229d2 2233 spec->ops = generic_standard_hdmi_ops;
84eb01be 2234 codec->spec = spec;
bce0d2a8 2235 hdmi_array_init(spec, 4);
6ffe168f 2236
fb87fa3a 2237 if (is_haswell(codec)) {
17df3f55 2238 intel_haswell_enable_all_pins(codec, true);
c88d4e84 2239 intel_haswell_fixup_enable_dp12(codec);
17df3f55 2240 }
6ffe168f 2241
84eb01be
TI		 2242 if (hdmi_parse_codec(codec) < 0) {
2243 codec->spec = NULL;
2244 kfree(spec);
2245 return -EINVAL;
2246 }
2247 codec->patch_ops = generic_hdmi_patch_ops;
fb87fa3a 2248 if (is_haswell(codec)) {
17df3f55 2249 codec->patch_ops.set_power_state = haswell_set_power_state;
5dc989bd
ML		 2250 codec->dp_mst = true;
2251 }
17df3f55 2252
8b8d654b 2253 generic_hdmi_init_per_pins(codec);
84eb01be 2254
84eb01be
TI		 2255 init_channel_allocations();
2256
2257 return 0;
2258}
2259
3aaf8980
SW		 2260/*
2261 * Shared non-generic implementations
2262 */
2263
2264static int simple_playback_build_pcms(struct hda_codec *codec)
2265{
2266 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2267 struct hda_pcm *info;
8ceb332d
TI		 2268 unsigned int chans;
2269 struct hda_pcm_stream *pstr;
bce0d2a8 2270 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2271
bce0d2a8
TI		 2272 per_cvt = get_cvt(spec, 0);
2273 chans = get_wcaps(codec, per_cvt->cvt_nid);
8ceb332d 2274 chans = get_wcaps_channels(chans);
3aaf8980 2275
bce0d2a8
TI		 2276 info = snd_array_new(&spec->pcm_rec);
2277 if (!info)
2278 return -ENOMEM;
2279 info->name = get_pin(spec, 0)->pcm_name;
2280 sprintf(info->name, "HDMI 0");
8ceb332d
TI		 2281 info->pcm_type = HDA_PCM_TYPE_HDMI;
2282 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2283 *pstr = spec->pcm_playback;
bce0d2a8 2284 pstr->nid = per_cvt->cvt_nid;
8ceb332d
TI		 2285 if (pstr->channels_max <= 2 && chans && chans <= 16)
2286 pstr->channels_max = chans;
3aaf8980 2287
bce0d2a8
TI		 2288 codec->num_pcms = 1;
2289 codec->pcm_info = info;
2290
3aaf8980
SW		 2291 return 0;
2292}
2293
4b6ace9e
TI		 2294/* unsolicited event for jack sensing */
2295static void simple_hdmi_unsol_event(struct hda_codec *codec,
2296 unsigned int res)
2297{
9dd8cf12 2298 snd_hda_jack_set_dirty_all(codec);
4b6ace9e
TI		 2299 snd_hda_jack_report_sync(codec);
2300}
2301
2302/* generic_hdmi_build_jack can be used for simple_hdmi, too,
2303 * as long as spec->pins[] is set correctly
2304 */
2305#define simple_hdmi_build_jack generic_hdmi_build_jack
2306
3aaf8980
SW		 2307static int simple_playback_build_controls(struct hda_codec *codec)
2308{
2309 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2310 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2311 int err;
3aaf8980 2312
bce0d2a8
TI		 2313 per_cvt = get_cvt(spec, 0);
2314 err = snd_hda_create_spdif_out_ctls(codec, per_cvt->cvt_nid,
2315 per_cvt->cvt_nid);
8ceb332d
TI		 2316 if (err < 0)
2317 return err;
2318 return simple_hdmi_build_jack(codec, 0);
3aaf8980
SW		 2319}
2320
4f0110ce
TI		 2321static int simple_playback_init(struct hda_codec *codec)
2322{
2323 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 2324 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2325 hda_nid_t pin = per_pin->pin_nid;
8ceb332d
TI		 2326
2327 snd_hda_codec_write(codec, pin, 0,
2328 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2329 /* some codecs require to unmute the pin */
2330 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2331 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2332 AMP_OUT_UNMUTE);
2333 snd_hda_jack_detect_enable(codec, pin, pin);
4f0110ce
TI		 2334 return 0;
2335}
2336
3aaf8980
SW		 2337static void simple_playback_free(struct hda_codec *codec)
2338{
2339 struct hdmi_spec *spec = codec->spec;
2340
bce0d2a8 2341 hdmi_array_free(spec);
3aaf8980
SW		 2342 kfree(spec);
2343}
2344
84eb01be
TI		 2345/*
2346 * Nvidia specific implementations
2347 */
2348
2349#define Nv_VERB_SET_Channel_Allocation 0xF79
2350#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2351#define Nv_VERB_SET_Audio_Protection_On 0xF98
2352#define Nv_VERB_SET_Audio_Protection_Off 0xF99
2353
2354#define nvhdmi_master_con_nid_7x 0x04
2355#define nvhdmi_master_pin_nid_7x 0x05
2356
fb79e1e0 2357static const hda_nid_t nvhdmi_con_nids_7x[4] = {
84eb01be
TI		 2358 /*front, rear, clfe, rear_surr */
2359 0x6, 0x8, 0xa, 0xc,
2360};
2361
ceaa86ba
TI		 2362static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2363 /* set audio protect on */
2364 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2365 /* enable digital output on pin widget */
2366 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2367 {} /* terminator */
2368};
2369
2370static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
84eb01be
TI		 2371 /* set audio protect on */
2372 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2373 /* enable digital output on pin widget */
2374 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2375 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2376 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2377 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2378 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2379 {} /* terminator */
2380};
2381
2382#ifdef LIMITED_RATE_FMT_SUPPORT
2383/* support only the safe format and rate */
2384#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2385#define SUPPORTED_MAXBPS 16
2386#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2387#else
2388/* support all rates and formats */
2389#define SUPPORTED_RATES \
2390 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2391 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2392 SNDRV_PCM_RATE_192000)
2393#define SUPPORTED_MAXBPS 24
2394#define SUPPORTED_FORMATS \
2395 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2396#endif
2397
ceaa86ba
TI		 2398static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2399{
2400 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2401 return 0;
2402}
2403
2404static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
84eb01be 2405{
ceaa86ba 2406 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
84eb01be
TI		 2407 return 0;
2408}
2409
393004b2
ND		 2410static unsigned int channels_2_6_8[] = {
2411 2, 6, 8
2412};
2413
2414static unsigned int channels_2_8[] = {
2415 2, 8
2416};
2417
2418static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2419 .count = ARRAY_SIZE(channels_2_6_8),
2420 .list = channels_2_6_8,
2421 .mask = 0,
2422};
2423
2424static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2425 .count = ARRAY_SIZE(channels_2_8),
2426 .list = channels_2_8,
2427 .mask = 0,
2428};
2429
84eb01be
TI		 2430static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2431 struct hda_codec *codec,
2432 struct snd_pcm_substream *substream)
2433{
2434 struct hdmi_spec *spec = codec->spec;
393004b2
ND		 2435 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2436
2437 switch (codec->preset->id) {
2438 case 0x10de0002:
2439 case 0x10de0003:
2440 case 0x10de0005:
2441 case 0x10de0006:
2442 hw_constraints_channels = &hw_constraints_2_8_channels;
2443 break;
2444 case 0x10de0007:
2445 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2446 break;
2447 default:
2448 break;
2449 }
2450
2451 if (hw_constraints_channels != NULL) {
2452 snd_pcm_hw_constraint_list(substream->runtime, 0,
2453 SNDRV_PCM_HW_PARAM_CHANNELS,
2454 hw_constraints_channels);
ad09fc9d
TI		 2455 } else {
2456 snd_pcm_hw_constraint_step(substream->runtime, 0,
2457 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
393004b2
ND		 2458 }
2459
84eb01be
TI		 2460 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2461}
2462
2463static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2464 struct hda_codec *codec,
2465 struct snd_pcm_substream *substream)
2466{
2467 struct hdmi_spec *spec = codec->spec;
2468 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2469}
2470
2471static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2472 struct hda_codec *codec,
2473 unsigned int stream_tag,
2474 unsigned int format,
2475 struct snd_pcm_substream *substream)
2476{
2477 struct hdmi_spec *spec = codec->spec;
2478 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2479 stream_tag, format, substream);
2480}
2481
d0b1252d
TI		 2482static const struct hda_pcm_stream simple_pcm_playback = {
2483 .substreams = 1,
2484 .channels_min = 2,
2485 .channels_max = 2,
2486 .ops = {
2487 .open = simple_playback_pcm_open,
2488 .close = simple_playback_pcm_close,
2489 .prepare = simple_playback_pcm_prepare
2490 },
2491};
2492
2493static const struct hda_codec_ops simple_hdmi_patch_ops = {
2494 .build_controls = simple_playback_build_controls,
2495 .build_pcms = simple_playback_build_pcms,
2496 .init = simple_playback_init,
2497 .free = simple_playback_free,
250e41ac 2498 .unsol_event = simple_hdmi_unsol_event,
d0b1252d
TI		 2499};
2500
2501static int patch_simple_hdmi(struct hda_codec *codec,
2502 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2503{
2504 struct hdmi_spec *spec;
bce0d2a8
TI		 2505 struct hdmi_spec_per_cvt *per_cvt;
2506 struct hdmi_spec_per_pin *per_pin;
d0b1252d
TI		 2507
2508 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2509 if (!spec)
2510 return -ENOMEM;
2511
2512 codec->spec = spec;
bce0d2a8 2513 hdmi_array_init(spec, 1);
d0b1252d
TI		 2514
2515 spec->multiout.num_dacs = 0; /* no analog */
2516 spec->multiout.max_channels = 2;
2517 spec->multiout.dig_out_nid = cvt_nid;
2518 spec->num_cvts = 1;
2519 spec->num_pins = 1;
bce0d2a8
TI		 2520 per_pin = snd_array_new(&spec->pins);
2521 per_cvt = snd_array_new(&spec->cvts);
2522 if (!per_pin || !per_cvt) {
2523 simple_playback_free(codec);
2524 return -ENOMEM;
2525 }
2526 per_cvt->cvt_nid = cvt_nid;
2527 per_pin->pin_nid = pin_nid;
d0b1252d
TI		 2528 spec->pcm_playback = simple_pcm_playback;
2529
2530 codec->patch_ops = simple_hdmi_patch_ops;
2531
2532 return 0;
2533}
2534
1f348522
AP		 2535static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2536 int channels)
2537{
2538 unsigned int chanmask;
2539 int chan = channels ? (channels - 1) : 1;
2540
2541 switch (channels) {
2542 default:
2543 case 0:
2544 case 2:
2545 chanmask = 0x00;
2546 break;
2547 case 4:
2548 chanmask = 0x08;
2549 break;
2550 case 6:
2551 chanmask = 0x0b;
2552 break;
2553 case 8:
2554 chanmask = 0x13;
2555 break;
2556 }
2557
2558 /* Set the audio infoframe channel allocation and checksum fields. The
2559 * channel count is computed implicitly by the hardware. */
2560 snd_hda_codec_write(codec, 0x1, 0,
2561 Nv_VERB_SET_Channel_Allocation, chanmask);
2562
2563 snd_hda_codec_write(codec, 0x1, 0,
2564 Nv_VERB_SET_Info_Frame_Checksum,
2565 (0x71 - chan - chanmask));
2566}
2567
84eb01be
TI		 2568static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2569 struct hda_codec *codec,
2570 struct snd_pcm_substream *substream)
2571{
2572 struct hdmi_spec *spec = codec->spec;
2573 int i;
2574
2575 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2576 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2577 for (i = 0; i < 4; i++) {
2578 /* set the stream id */
2579 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2580 AC_VERB_SET_CHANNEL_STREAMID, 0);
2581 /* set the stream format */
2582 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2583 AC_VERB_SET_STREAM_FORMAT, 0);
2584 }
2585
1f348522
AP		 2586 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2587 * streams are disabled. */
2588 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2589
84eb01be
TI		 2590 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2591}
2592
2593static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2594 struct hda_codec *codec,
2595 unsigned int stream_tag,
2596 unsigned int format,
2597 struct snd_pcm_substream *substream)
2598{
2599 int chs;
112daa7a 2600 unsigned int dataDCC2, channel_id;
84eb01be 2601 int i;
7c935976 2602 struct hdmi_spec *spec = codec->spec;
e3245cdd 2603 struct hda_spdif_out *spdif;
bce0d2a8 2604 struct hdmi_spec_per_cvt *per_cvt;
84eb01be
TI		 2605
2606 mutex_lock(&codec->spdif_mutex);
bce0d2a8
TI		 2607 per_cvt = get_cvt(spec, 0);
2608 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
84eb01be
TI		 2609
2610 chs = substream->runtime->channels;
84eb01be 2611
84eb01be
TI		 2612 dataDCC2 = 0x2;
2613
84eb01be 2614 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
7c935976 2615 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2616 snd_hda_codec_write(codec,
2617 nvhdmi_master_con_nid_7x,
2618 0,
2619 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2620 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2621
2622 /* set the stream id */
2623 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2624 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2625
2626 /* set the stream format */
2627 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2628 AC_VERB_SET_STREAM_FORMAT, format);
2629
2630 /* turn on again (if needed) */
2631 /* enable and set the channel status audio/data flag */
7c935976 2632 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2633 snd_hda_codec_write(codec,
2634 nvhdmi_master_con_nid_7x,
2635 0,
2636 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2637 spdif->ctls & 0xff);
84eb01be
TI		 2638 snd_hda_codec_write(codec,
2639 nvhdmi_master_con_nid_7x,
2640 0,
2641 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2642 }
2643
2644 for (i = 0; i < 4; i++) {
2645 if (chs == 2)
2646 channel_id = 0;
2647 else
2648 channel_id = i * 2;
2649
2650 /* turn off SPDIF once;
2651 *otherwise the IEC958 bits won't be updated
2652 */
2653 if (codec->spdif_status_reset &&
7c935976 2654 (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2655 snd_hda_codec_write(codec,
2656 nvhdmi_con_nids_7x[i],
2657 0,
2658 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2659 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2660 /* set the stream id */
2661 snd_hda_codec_write(codec,
2662 nvhdmi_con_nids_7x[i],
2663 0,
2664 AC_VERB_SET_CHANNEL_STREAMID,
2665 (stream_tag << 4) | channel_id);
2666 /* set the stream format */
2667 snd_hda_codec_write(codec,
2668 nvhdmi_con_nids_7x[i],
2669 0,
2670 AC_VERB_SET_STREAM_FORMAT,
2671 format);
2672 /* turn on again (if needed) */
2673 /* enable and set the channel status audio/data flag */
2674 if (codec->spdif_status_reset &&
7c935976 2675 (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2676 snd_hda_codec_write(codec,
2677 nvhdmi_con_nids_7x[i],
2678 0,
2679 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2680 spdif->ctls & 0xff);
84eb01be
TI		 2681 snd_hda_codec_write(codec,
2682 nvhdmi_con_nids_7x[i],
2683 0,
2684 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2685 }
2686 }
2687
1f348522 2688 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
84eb01be
TI		 2689
2690 mutex_unlock(&codec->spdif_mutex);
2691 return 0;
2692}
2693
fb79e1e0 2694static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
84eb01be
TI		 2695 .substreams = 1,
2696 .channels_min = 2,
2697 .channels_max = 8,
2698 .nid = nvhdmi_master_con_nid_7x,
2699 .rates = SUPPORTED_RATES,
2700 .maxbps = SUPPORTED_MAXBPS,
2701 .formats = SUPPORTED_FORMATS,
2702 .ops = {
2703 .open = simple_playback_pcm_open,
2704 .close = nvhdmi_8ch_7x_pcm_close,
2705 .prepare = nvhdmi_8ch_7x_pcm_prepare
2706 },
2707};
2708
84eb01be
TI		 2709static int patch_nvhdmi_2ch(struct hda_codec *codec)
2710{
2711 struct hdmi_spec *spec;
d0b1252d
TI		 2712 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2713 nvhdmi_master_pin_nid_7x);
2714 if (err < 0)
2715 return err;
84eb01be 2716
ceaa86ba 2717 codec->patch_ops.init = nvhdmi_7x_init_2ch;
d0b1252d
TI		 2718 /* override the PCM rates, etc, as the codec doesn't give full list */
2719 spec = codec->spec;
2720 spec->pcm_playback.rates = SUPPORTED_RATES;
2721 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2722 spec->pcm_playback.formats = SUPPORTED_FORMATS;
84eb01be
TI		 2723 return 0;
2724}
2725
53775b0d
TI		 2726static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2727{
2728 struct hdmi_spec *spec = codec->spec;
2729 int err = simple_playback_build_pcms(codec);
bce0d2a8
TI		 2730 if (!err) {
2731 struct hda_pcm *info = get_pcm_rec(spec, 0);
2732 info->own_chmap = true;
2733 }
53775b0d
TI		 2734 return err;
2735}
2736
2737static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2738{
2739 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2740 struct hda_pcm *info;
53775b0d
TI		 2741 struct snd_pcm_chmap *chmap;
2742 int err;
2743
2744 err = simple_playback_build_controls(codec);
2745 if (err < 0)
2746 return err;
2747
2748 /* add channel maps */
bce0d2a8
TI		 2749 info = get_pcm_rec(spec, 0);
2750 err = snd_pcm_add_chmap_ctls(info->pcm,
53775b0d
TI		 2751 SNDRV_PCM_STREAM_PLAYBACK,
2752 snd_pcm_alt_chmaps, 8, 0, &chmap);
2753 if (err < 0)
2754 return err;
2755 switch (codec->preset->id) {
2756 case 0x10de0002:
2757 case 0x10de0003:
2758 case 0x10de0005:
2759 case 0x10de0006:
2760 chmap->channel_mask = (1U << 2) | (1U << 8);
2761 break;
2762 case 0x10de0007:
2763 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
2764 }
2765 return 0;
2766}
2767
84eb01be
TI		 2768static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
2769{
2770 struct hdmi_spec *spec;
2771 int err = patch_nvhdmi_2ch(codec);
84eb01be
TI		 2772 if (err < 0)
2773 return err;
2774 spec = codec->spec;
2775 spec->multiout.max_channels = 8;
d0b1252d 2776 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
ceaa86ba 2777 codec->patch_ops.init = nvhdmi_7x_init_8ch;
53775b0d
TI		 2778 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
2779 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
1f348522
AP		 2780
2781 /* Initialize the audio infoframe channel mask and checksum to something
2782 * valid */
2783 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2784
84eb01be
TI		 2785 return 0;
2786}
2787
2788/*
5a613584 2789 * ATI/AMD-specific implementations
84eb01be
TI		 2790 */
2791
5a613584
AH		 2792#define is_amdhdmi_rev3_or_later(codec) \
2793 ((codec)->vendor_id == 0x1002aa01 && ((codec)->revision_id & 0xff00) >= 0x0300)
2794#define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
2795
2796/* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
2797#define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
2798#define ATI_VERB_SET_DOWNMIX_INFO 0x772
2799#define ATI_VERB_SET_MULTICHANNEL_01 0x777
2800#define ATI_VERB_SET_MULTICHANNEL_23 0x778
2801#define ATI_VERB_SET_MULTICHANNEL_45 0x779
2802#define ATI_VERB_SET_MULTICHANNEL_67 0x77a
461cf6b3 2803#define ATI_VERB_SET_HBR_CONTROL 0x77c
5a613584
AH		 2804#define ATI_VERB_SET_MULTICHANNEL_1 0x785
2805#define ATI_VERB_SET_MULTICHANNEL_3 0x786
2806#define ATI_VERB_SET_MULTICHANNEL_5 0x787
2807#define ATI_VERB_SET_MULTICHANNEL_7 0x788
2808#define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
2809#define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
2810#define ATI_VERB_GET_DOWNMIX_INFO 0xf72
2811#define ATI_VERB_GET_MULTICHANNEL_01 0xf77
2812#define ATI_VERB_GET_MULTICHANNEL_23 0xf78
2813#define ATI_VERB_GET_MULTICHANNEL_45 0xf79
2814#define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
461cf6b3 2815#define ATI_VERB_GET_HBR_CONTROL 0xf7c
5a613584
AH		 2816#define ATI_VERB_GET_MULTICHANNEL_1 0xf85
2817#define ATI_VERB_GET_MULTICHANNEL_3 0xf86
2818#define ATI_VERB_GET_MULTICHANNEL_5 0xf87
2819#define ATI_VERB_GET_MULTICHANNEL_7 0xf88
2820#define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
2821
84d69e79
AH		 2822/* AMD specific HDA cvt verbs */
2823#define ATI_VERB_SET_RAMP_RATE 0x770
2824#define ATI_VERB_GET_RAMP_RATE 0xf70
2825
5a613584
AH		 2826#define ATI_OUT_ENABLE 0x1
2827
2828#define ATI_MULTICHANNEL_MODE_PAIRED 0
2829#define ATI_MULTICHANNEL_MODE_SINGLE 1
2830
461cf6b3
AH		 2831#define ATI_HBR_CAPABLE 0x01
2832#define ATI_HBR_ENABLE 0x10
2833
89250f84
AH		 2834static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
2835 unsigned char *buf, int *eld_size)
2836{
2837 /* call hda_eld.c ATI/AMD-specific function */
2838 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
2839 is_amdhdmi_rev3_or_later(codec));
2840}
2841
5a613584
AH		 2842static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
2843 int active_channels, int conn_type)
2844{
2845 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
2846}
2847
2848static int atihdmi_paired_swap_fc_lfe(int pos)
2849{
2850 /*
2851 * ATI/AMD have automatic FC/LFE swap built-in
2852 * when in pairwise mapping mode.
2853 */
2854
2855 switch (pos) {
2856 /* see channel_allocations[].speakers[] */
2857 case 2: return 3;
2858 case 3: return 2;
2859 default: break;
2860 }
2861
2862 return pos;
2863}
2864
2865static int atihdmi_paired_chmap_validate(int ca, int chs, unsigned char *map)
2866{
2867 struct cea_channel_speaker_allocation *cap;
2868 int i, j;
2869
2870 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
2871
2872 cap = &channel_allocations[get_channel_allocation_order(ca)];
2873 for (i = 0; i < chs; ++i) {
2874 int mask = to_spk_mask(map[i]);
2875 bool ok = false;
2876 bool companion_ok = false;
2877
2878 if (!mask)
2879 continue;
2880
2881 for (j = 0 + i % 2; j < 8; j += 2) {
2882 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
2883 if (cap->speakers[chan_idx] == mask) {
2884 /* channel is in a supported position */
2885 ok = true;
2886
2887 if (i % 2 == 0 && i + 1 < chs) {
2888 /* even channel, check the odd companion */
2889 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
2890 int comp_mask_req = to_spk_mask(map[i+1]);
2891 int comp_mask_act = cap->speakers[comp_chan_idx];
2892
2893 if (comp_mask_req == comp_mask_act)
2894 companion_ok = true;
2895 else
2896 return -EINVAL;
2897 }
2898 break;
2899 }
2900 }
2901
2902 if (!ok)
2903 return -EINVAL;
2904
2905 if (companion_ok)
2906 i++; /* companion channel already checked */
2907 }
2908
2909 return 0;
2910}
2911
2912static int atihdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
2913 int hdmi_slot, int stream_channel)
2914{
2915 int verb;
2916 int ati_channel_setup = 0;
2917
2918 if (hdmi_slot > 7)
2919 return -EINVAL;
2920
2921 if (!has_amd_full_remap_support(codec)) {
2922 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
2923
2924 /* In case this is an odd slot but without stream channel, do not
2925 * disable the slot since the corresponding even slot could have a
2926 * channel. In case neither have a channel, the slot pair will be
2927 * disabled when this function is called for the even slot. */
2928 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
2929 return 0;
2930
2931 hdmi_slot -= hdmi_slot % 2;
2932
2933 if (stream_channel != 0xf)
2934 stream_channel -= stream_channel % 2;
2935 }
2936
2937 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
2938
2939 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
2940
2941 if (stream_channel != 0xf)
2942 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
2943
2944 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
2945}
2946
2947static int atihdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
2948 int asp_slot)
2949{
2950 bool was_odd = false;
2951 int ati_asp_slot = asp_slot;
2952 int verb;
2953 int ati_channel_setup;
2954
2955 if (asp_slot > 7)
2956 return -EINVAL;
2957
2958 if (!has_amd_full_remap_support(codec)) {
2959 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
2960 if (ati_asp_slot % 2 != 0) {
2961 ati_asp_slot -= 1;
2962 was_odd = true;
2963 }
2964 }
2965
2966 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
2967
2968 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
2969
2970 if (!(ati_channel_setup & ATI_OUT_ENABLE))
2971 return 0xf;
2972
2973 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
2974}
84eb01be 2975
5a613584
AH		 2976static int atihdmi_paired_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
2977 int channels)
2978{
2979 int c;
2980
2981 /*
2982 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
2983 * we need to take that into account (a single channel may take 2
2984 * channel slots if we need to carry a silent channel next to it).
2985 * On Rev3+ AMD codecs this function is not used.
2986 */
2987 int chanpairs = 0;
2988
2989 /* We only produce even-numbered channel count TLVs */
2990 if ((channels % 2) != 0)
2991 return -1;
2992
2993 for (c = 0; c < 7; c += 2) {
2994 if (cap->speakers[c] || cap->speakers[c+1])
2995 chanpairs++;
2996 }
2997
2998 if (chanpairs * 2 != channels)
2999 return -1;
3000
3001 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3002}
3003
3004static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
3005 unsigned int *chmap, int channels)
3006{
3007 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3008 int count = 0;
3009 int c;
3010
3011 for (c = 7; c >= 0; c--) {
3012 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3013 int spk = cap->speakers[chan];
3014 if (!spk) {
3015 /* add N/A channel if the companion channel is occupied */
3016 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3017 chmap[count++] = SNDRV_CHMAP_NA;
3018
3019 continue;
3020 }
3021
3022 chmap[count++] = spk_to_chmap(spk);
3023 }
3024
3025 WARN_ON(count != channels);
3026}
3027
461cf6b3
AH		 3028static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3029 bool hbr)
3030{
3031 int hbr_ctl, hbr_ctl_new;
3032
3033 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
3034 if (hbr_ctl & ATI_HBR_CAPABLE) {
3035 if (hbr)
3036 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3037 else
3038 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3039
3040 snd_printdd("atihdmi_pin_hbr_setup: "
3041 "NID=0x%x, %shbr-ctl=0x%x\n",
3042 pin_nid,
3043 hbr_ctl == hbr_ctl_new ? "" : "new-",
3044 hbr_ctl_new);
3045
3046 if (hbr_ctl != hbr_ctl_new)
3047 snd_hda_codec_write(codec, pin_nid, 0,
3048 ATI_VERB_SET_HBR_CONTROL,
3049 hbr_ctl_new);
3050
3051 } else if (hbr)
3052 return -EINVAL;
3053
3054 return 0;
3055}
3056
84d69e79
AH		 3057static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3058 hda_nid_t pin_nid, u32 stream_tag, int format)
3059{
3060
3061 if (is_amdhdmi_rev3_or_later(codec)) {
3062 int ramp_rate = 180; /* default as per AMD spec */
3063 /* disable ramp-up/down for non-pcm as per AMD spec */
3064 if (format & AC_FMT_TYPE_NON_PCM)
3065 ramp_rate = 0;
3066
3067 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3068 }
3069
3070 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3071}
3072
3073
5a613584 3074static int atihdmi_init(struct hda_codec *codec)
84eb01be
TI		 3075{
3076 struct hdmi_spec *spec = codec->spec;
5a613584 3077 int pin_idx, err;
84eb01be 3078
5a613584
AH		 3079 err = generic_hdmi_init(codec);
3080
3081 if (err)
84eb01be 3082 return err;
5a613584
AH		 3083
3084 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3085 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3086
3087 /* make sure downmix information in infoframe is zero */
3088 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3089
3090 /* enable channel-wise remap mode if supported */
3091 if (has_amd_full_remap_support(codec))
3092 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3093 ATI_VERB_SET_MULTICHANNEL_MODE,
3094 ATI_MULTICHANNEL_MODE_SINGLE);
84eb01be 3095 }
5a613584 3096
84eb01be
TI		 3097 return 0;
3098}
3099
84eb01be
TI		 3100static int patch_atihdmi(struct hda_codec *codec)
3101{
3102 struct hdmi_spec *spec;
5a613584
AH		 3103 struct hdmi_spec_per_cvt *per_cvt;
3104 int err, cvt_idx;
3105
3106 err = patch_generic_hdmi(codec);
3107
3108 if (err)
d0b1252d 3109 return err;
5a613584
AH		 3110
3111 codec->patch_ops.init = atihdmi_init;
3112
d0b1252d 3113 spec = codec->spec;
5a613584 3114
89250f84 3115 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
5a613584
AH		 3116 spec->ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3117 spec->ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3118 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
461cf6b3 3119 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
84d69e79 3120 spec->ops.setup_stream = atihdmi_setup_stream;
5a613584
AH		 3121
3122 if (!has_amd_full_remap_support(codec)) {
3123 /* override to ATI/AMD-specific versions with pairwise mapping */
3124 spec->ops.chmap_cea_alloc_validate_get_type =
3125 atihdmi_paired_chmap_cea_alloc_validate_get_type;
3126 spec->ops.cea_alloc_to_tlv_chmap = atihdmi_paired_cea_alloc_to_tlv_chmap;
3127 spec->ops.chmap_validate = atihdmi_paired_chmap_validate;
3128 }
3129
3130 /* ATI/AMD converters do not advertise all of their capabilities */
3131 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3132 per_cvt = get_cvt(spec, cvt_idx);
3133 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3134 per_cvt->rates |= SUPPORTED_RATES;
3135 per_cvt->formats |= SUPPORTED_FORMATS;
3136 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3137 }
3138
3139 spec->channels_max = max(spec->channels_max, 8u);
3140
84eb01be
TI		 3141 return 0;
3142}
3143
3de5ff88
AL		 3144/* VIA HDMI Implementation */
3145#define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
3146#define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
3147
3de5ff88
AL		 3148static int patch_via_hdmi(struct hda_codec *codec)
3149{
250e41ac 3150 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3de5ff88 3151}
84eb01be
TI		 3152
3153/*
3154 * patch entries
3155 */
fb79e1e0 3156static const struct hda_codec_preset snd_hda_preset_hdmi[] = {
84eb01be
TI		 3157{ .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi },
3158{ .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi },
3159{ .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi },
5a613584 3160{ .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_atihdmi },
84eb01be
TI		 3161{ .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi },
3162{ .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi },
3163{ .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi },
3164{ .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3165{ .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3166{ .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3167{ .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3168{ .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x },
5d44f927
SW		 3169{ .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_generic_hdmi },
3170{ .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_generic_hdmi },
3171{ .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_generic_hdmi },
3172{ .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_generic_hdmi },
3173{ .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_generic_hdmi },
3174{ .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_generic_hdmi },
3175{ .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_generic_hdmi },
3176{ .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_generic_hdmi },
3177{ .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_generic_hdmi },
3178{ .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_generic_hdmi },
3179{ .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_generic_hdmi },
c8900a0f 3180/* 17 is known to be absent */
5d44f927
SW		 3181{ .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_generic_hdmi },
3182{ .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_generic_hdmi },
3183{ .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_generic_hdmi },
3184{ .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_generic_hdmi },
3185{ .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_generic_hdmi },
3186{ .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_generic_hdmi },
3187{ .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_generic_hdmi },
3188{ .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_generic_hdmi },
3189{ .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_generic_hdmi },
3190{ .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_generic_hdmi },
7ae48b56 3191{ .id = 0x10de0051, .name = "GPU 51 HDMI/DP", .patch = patch_generic_hdmi },
d52392b1 3192{ .id = 0x10de0060, .name = "GPU 60 HDMI/DP", .patch = patch_generic_hdmi },
84eb01be
TI		 3193{ .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
3194{ .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
3de5ff88
AL		 3195{ .id = 0x11069f80, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
3196{ .id = 0x11069f81, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
3197{ .id = 0x11069f84, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
3198{ .id = 0x11069f85, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
84eb01be
TI		 3199{ .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
3200{ .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi },
3201{ .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi },
3202{ .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi },
3203{ .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
3204{ .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
591e610d 3205{ .id = 0x80862806, .name = "PantherPoint HDMI", .patch = patch_generic_hdmi },
1c76684d 3206{ .id = 0x80862807, .name = "Haswell HDMI", .patch = patch_generic_hdmi },
6edc59e6 3207{ .id = 0x80862880, .name = "CedarTrail HDMI", .patch = patch_generic_hdmi },
cc1a95d9 3208{ .id = 0x80862882, .name = "Valleyview2 HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 3209{ .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
3210{} /* terminator */
3211};
3212
3213MODULE_ALIAS("snd-hda-codec-id:1002793c");
3214MODULE_ALIAS("snd-hda-codec-id:10027919");
3215MODULE_ALIAS("snd-hda-codec-id:1002791a");
3216MODULE_ALIAS("snd-hda-codec-id:1002aa01");
3217MODULE_ALIAS("snd-hda-codec-id:10951390");
3218MODULE_ALIAS("snd-hda-codec-id:10951392");
3219MODULE_ALIAS("snd-hda-codec-id:10de0002");
3220MODULE_ALIAS("snd-hda-codec-id:10de0003");
3221MODULE_ALIAS("snd-hda-codec-id:10de0005");
3222MODULE_ALIAS("snd-hda-codec-id:10de0006");
3223MODULE_ALIAS("snd-hda-codec-id:10de0007");
3224MODULE_ALIAS("snd-hda-codec-id:10de000a");
3225MODULE_ALIAS("snd-hda-codec-id:10de000b");
3226MODULE_ALIAS("snd-hda-codec-id:10de000c");
3227MODULE_ALIAS("snd-hda-codec-id:10de000d");
3228MODULE_ALIAS("snd-hda-codec-id:10de0010");
3229MODULE_ALIAS("snd-hda-codec-id:10de0011");
3230MODULE_ALIAS("snd-hda-codec-id:10de0012");
3231MODULE_ALIAS("snd-hda-codec-id:10de0013");
3232MODULE_ALIAS("snd-hda-codec-id:10de0014");
c8900a0f
RS		 3233MODULE_ALIAS("snd-hda-codec-id:10de0015");
3234MODULE_ALIAS("snd-hda-codec-id:10de0016");
84eb01be
TI		 3235MODULE_ALIAS("snd-hda-codec-id:10de0018");
3236MODULE_ALIAS("snd-hda-codec-id:10de0019");
3237MODULE_ALIAS("snd-hda-codec-id:10de001a");
3238MODULE_ALIAS("snd-hda-codec-id:10de001b");
3239MODULE_ALIAS("snd-hda-codec-id:10de001c");
3240MODULE_ALIAS("snd-hda-codec-id:10de0040");
3241MODULE_ALIAS("snd-hda-codec-id:10de0041");
3242MODULE_ALIAS("snd-hda-codec-id:10de0042");
3243MODULE_ALIAS("snd-hda-codec-id:10de0043");
3244MODULE_ALIAS("snd-hda-codec-id:10de0044");
7ae48b56 3245MODULE_ALIAS("snd-hda-codec-id:10de0051");
d52392b1 3246MODULE_ALIAS("snd-hda-codec-id:10de0060");
84eb01be
TI		 3247MODULE_ALIAS("snd-hda-codec-id:10de0067");
3248MODULE_ALIAS("snd-hda-codec-id:10de8001");
3de5ff88
AL		 3249MODULE_ALIAS("snd-hda-codec-id:11069f80");
3250MODULE_ALIAS("snd-hda-codec-id:11069f81");
3251MODULE_ALIAS("snd-hda-codec-id:11069f84");
3252MODULE_ALIAS("snd-hda-codec-id:11069f85");
84eb01be
TI		 3253MODULE_ALIAS("snd-hda-codec-id:17e80047");
3254MODULE_ALIAS("snd-hda-codec-id:80860054");
3255MODULE_ALIAS("snd-hda-codec-id:80862801");
3256MODULE_ALIAS("snd-hda-codec-id:80862802");
3257MODULE_ALIAS("snd-hda-codec-id:80862803");
3258MODULE_ALIAS("snd-hda-codec-id:80862804");
3259MODULE_ALIAS("snd-hda-codec-id:80862805");
591e610d 3260MODULE_ALIAS("snd-hda-codec-id:80862806");
1c76684d 3261MODULE_ALIAS("snd-hda-codec-id:80862807");
6edc59e6 3262MODULE_ALIAS("snd-hda-codec-id:80862880");
cc1a95d9 3263MODULE_ALIAS("snd-hda-codec-id:80862882");
84eb01be
TI		 3264MODULE_ALIAS("snd-hda-codec-id:808629fb");
3265
3266MODULE_LICENSE("GPL");
3267MODULE_DESCRIPTION("HDMI HD-audio codec");
3268MODULE_ALIAS("snd-hda-codec-intelhdmi");
3269MODULE_ALIAS("snd-hda-codec-nvhdmi");
3270MODULE_ALIAS("snd-hda-codec-atihdmi");
3271
3272static struct hda_codec_preset_list intel_list = {
3273 .preset = snd_hda_preset_hdmi,
3274 .owner = THIS_MODULE,
3275};
3276
3277static int __init patch_hdmi_init(void)
3278{
3279 return snd_hda_add_codec_preset(&intel_list);
3280}
3281
3282static void __exit patch_hdmi_exit(void)
3283{
3284 snd_hda_delete_codec_preset(&intel_list);
3285}
3286
3287module_init(patch_hdmi_init)
3288module_exit(patch_hdmi_exit)
Linux 6.x block layer and io_uring tree(s)