projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ALSA: hda: Virtualize SPDIF out controls
[linux-block.git] / sound / pci / hda / patch_hdmi.c
CommitLineData
079d88cc
WF		 1/*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
84eb01be
TI		 6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
079d88cc
WF		 9 *
10 * Authors:
11 * Wu Fengguang <wfg@linux.intel.com>
12 *
13 * Maintained by:
14 * Wu Fengguang <wfg@linux.intel.com>
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the Free
18 * Software Foundation; either version 2 of the License, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful, but
22 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
23 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
24 * for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software Foundation,
28 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
84eb01be
TI		 31#include <linux/init.h>
32#include <linux/delay.h>
33#include <linux/slab.h>
0ebaa24c 34#include <linux/moduleparam.h>
84eb01be 35#include <sound/core.h>
07acecc1 36#include <sound/jack.h>
84eb01be
TI		 37#include "hda_codec.h"
38#include "hda_local.h"
39
0ebaa24c
TI		 40static bool static_hdmi_pcm;
41module_param(static_hdmi_pcm, bool, 0644);
42MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
43
84eb01be
TI		 44/*
45 * The HDMI/DisplayPort configuration can be highly dynamic. A graphics device
46 * could support two independent pipes, each of them can be connected to one or
47 * more ports (DVI, HDMI or DisplayPort).
48 *
49 * The HDA correspondence of pipes/ports are converter/pin nodes.
50 */
73926656
SW		 51#define MAX_HDMI_CVTS 4
52#define MAX_HDMI_PINS 4
079d88cc
WF		 53
54struct hdmi_spec {
55 int num_cvts;
56 int num_pins;
57 hda_nid_t cvt[MAX_HDMI_CVTS+1]; /* audio sources */
58 hda_nid_t pin[MAX_HDMI_PINS+1]; /* audio sinks */
59
60 /*
61 * source connection for each pin
62 */
63 hda_nid_t pin_cvt[MAX_HDMI_PINS+1];
64
65 /*
66 * HDMI sink attached to each pin
67 */
68 struct hdmi_eld sink_eld[MAX_HDMI_PINS];
69
70 /*
71 * export one pcm per pipe
72 */
73 struct hda_pcm pcm_rec[MAX_HDMI_CVTS];
bbbe3390 74 struct hda_pcm_stream codec_pcm_pars[MAX_HDMI_CVTS];
079d88cc
WF		 75
76 /*
84eb01be 77 * ati/nvhdmi specific
079d88cc
WF		 78 */
79 struct hda_multi_out multiout;
fb79e1e0 80 const struct hda_pcm_stream *pcm_playback;
079d88cc
WF		 81};
82
83
84struct hdmi_audio_infoframe {
85 u8 type; /* 0x84 */
86 u8 ver; /* 0x01 */
87 u8 len; /* 0x0a */
88
53d7d69d
WF		 89 u8 checksum;
90
079d88cc
WF		 91 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
92 u8 SS01_SF24;
93 u8 CXT04;
94 u8 CA;
95 u8 LFEPBL01_LSV36_DM_INH7;
53d7d69d
WF		 96};
97
98struct dp_audio_infoframe {
99 u8 type; /* 0x84 */
100 u8 len; /* 0x1b */
101 u8 ver; /* 0x11 << 2 */
102
103 u8 CC02_CT47; /* match with HDMI infoframe from this on */
104 u8 SS01_SF24;
105 u8 CXT04;
106 u8 CA;
107 u8 LFEPBL01_LSV36_DM_INH7;
079d88cc
WF		 108};
109
2b203dbb
TI		 110union audio_infoframe {
111 struct hdmi_audio_infoframe hdmi;
112 struct dp_audio_infoframe dp;
113 u8 bytes[0];
114};
115
079d88cc
WF		 116/*
117 * CEA speaker placement:
118 *
119 * FLH FCH FRH
120 * FLW FL FLC FC FRC FR FRW
121 *
122 * LFE
123 * TC
124 *
125 * RL RLC RC RRC RR
126 *
127 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
128 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
129 */
130enum cea_speaker_placement {
131 FL = (1 << 0), /* Front Left */
132 FC = (1 << 1), /* Front Center */
133 FR = (1 << 2), /* Front Right */
134 FLC = (1 << 3), /* Front Left Center */
135 FRC = (1 << 4), /* Front Right Center */
136 RL = (1 << 5), /* Rear Left */
137 RC = (1 << 6), /* Rear Center */
138 RR = (1 << 7), /* Rear Right */
139 RLC = (1 << 8), /* Rear Left Center */
140 RRC = (1 << 9), /* Rear Right Center */
141 LFE = (1 << 10), /* Low Frequency Effect */
142 FLW = (1 << 11), /* Front Left Wide */
143 FRW = (1 << 12), /* Front Right Wide */
144 FLH = (1 << 13), /* Front Left High */
145 FCH = (1 << 14), /* Front Center High */
146 FRH = (1 << 15), /* Front Right High */
147 TC = (1 << 16), /* Top Center */
148};
149
150/*
151 * ELD SA bits in the CEA Speaker Allocation data block
152 */
153static int eld_speaker_allocation_bits[] = {
154 [0] = FL | FR,
155 [1] = LFE,
156 [2] = FC,
157 [3] = RL | RR,
158 [4] = RC,
159 [5] = FLC | FRC,
160 [6] = RLC | RRC,
161 /* the following are not defined in ELD yet */
162 [7] = FLW | FRW,
163 [8] = FLH | FRH,
164 [9] = TC,
165 [10] = FCH,
166};
167
168struct cea_channel_speaker_allocation {
169 int ca_index;
170 int speakers[8];
171
172 /* derived values, just for convenience */
173 int channels;
174 int spk_mask;
175};
176
177/*
178 * ALSA sequence is:
179 *
180 * surround40 surround41 surround50 surround51 surround71
181 * ch0 front left = = = =
182 * ch1 front right = = = =
183 * ch2 rear left = = = =
184 * ch3 rear right = = = =
185 * ch4 LFE center center center
186 * ch5 LFE LFE
187 * ch6 side left
188 * ch7 side right
189 *
190 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
191 */
192static int hdmi_channel_mapping[0x32][8] = {
193 /* stereo */
194 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
195 /* 2.1 */
196 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
197 /* Dolby Surround */
198 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
199 /* surround40 */
200 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
201 /* 4ch */
202 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
203 /* surround41 */
9396d317 204 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
079d88cc
WF		 205 /* surround50 */
206 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
207 /* surround51 */
208 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
209 /* 7.1 */
210 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
211};
212
213/*
214 * This is an ordered list!
215 *
216 * The preceding ones have better chances to be selected by
53d7d69d 217 * hdmi_channel_allocation().
079d88cc
WF		 218 */
219static struct cea_channel_speaker_allocation channel_allocations[] = {
220/* channel: 7 6 5 4 3 2 1 0 */
221{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
222 /* 2.1 */
223{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
224 /* Dolby Surround */
225{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
226 /* surround40 */
227{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
228 /* surround41 */
229{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
230 /* surround50 */
231{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
232 /* surround51 */
233{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
234 /* 6.1 */
235{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
236 /* surround71 */
237{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
238
239{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
240{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
241{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
242{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
243{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
244{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
245{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
246{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
247{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
248{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
249{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
250{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
251{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
252{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
253{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
254{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
255{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
256{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
257{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
258{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
259{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
260{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
261{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
262{ .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
263{ .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
264{ .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
265{ .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
266{ .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
267{ .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
268{ .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
269{ .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
270{ .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
271{ .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
272{ .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
273{ .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
274{ .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
275{ .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
276{ .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
277{ .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
278{ .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
279{ .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
280};
281
282
283/*
284 * HDMI routines
285 */
286
287static int hda_node_index(hda_nid_t *nids, hda_nid_t nid)
288{
289 int i;
290
291 for (i = 0; nids[i]; i++)
292 if (nids[i] == nid)
293 return i;
294
295 snd_printk(KERN_WARNING "HDMI: nid %d not registered\n", nid);
296 return -EINVAL;
297}
298
079d88cc
WF		 299#ifdef BE_PARANOID
300static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
301 int *packet_index, int *byte_index)
302{
303 int val;
304
305 val = snd_hda_codec_read(codec, pin_nid, 0,
306 AC_VERB_GET_HDMI_DIP_INDEX, 0);
307
308 *packet_index = val >> 5;
309 *byte_index = val & 0x1f;
310}
311#endif
312
313static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
314 int packet_index, int byte_index)
315{
316 int val;
317
318 val = (packet_index << 5) | (byte_index & 0x1f);
319
320 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
321}
322
323static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
324 unsigned char val)
325{
326 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
327}
328
329static void hdmi_enable_output(struct hda_codec *codec, hda_nid_t pin_nid)
330{
331 /* Unmute */
332 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
333 snd_hda_codec_write(codec, pin_nid, 0,
334 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
335 /* Enable pin out */
336 snd_hda_codec_write(codec, pin_nid, 0,
337 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
338}
339
340static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t nid)
341{
342 return 1 + snd_hda_codec_read(codec, nid, 0,
343 AC_VERB_GET_CVT_CHAN_COUNT, 0);
344}
345
346static void hdmi_set_channel_count(struct hda_codec *codec,
347 hda_nid_t nid, int chs)
348{
349 if (chs != hdmi_get_channel_count(codec, nid))
350 snd_hda_codec_write(codec, nid, 0,
351 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
352}
353
354
355/*
356 * Channel mapping routines
357 */
358
359/*
360 * Compute derived values in channel_allocations[].
361 */
362static void init_channel_allocations(void)
363{
364 int i, j;
365 struct cea_channel_speaker_allocation *p;
366
367 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
368 p = channel_allocations + i;
369 p->channels = 0;
370 p->spk_mask = 0;
371 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
372 if (p->speakers[j]) {
373 p->channels++;
374 p->spk_mask |= p->speakers[j];
375 }
376 }
377}
378
379/*
380 * The transformation takes two steps:
381 *
382 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
383 * spk_mask => (channel_allocations[]) => ai->CA
384 *
385 * TODO: it could select the wrong CA from multiple candidates.
386*/
53d7d69d
WF		 387static int hdmi_channel_allocation(struct hda_codec *codec, hda_nid_t nid,
388 int channels)
079d88cc
WF		 389{
390 struct hdmi_spec *spec = codec->spec;
391 struct hdmi_eld *eld;
392 int i;
53d7d69d 393 int ca = 0;
079d88cc 394 int spk_mask = 0;
079d88cc
WF		 395 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
396
397 /*
398 * CA defaults to 0 for basic stereo audio
399 */
400 if (channels <= 2)
401 return 0;
402
403 i = hda_node_index(spec->pin_cvt, nid);
404 if (i < 0)
405 return 0;
406 eld = &spec->sink_eld[i];
407
408 /*
409 * HDMI sink's ELD info cannot always be retrieved for now, e.g.
410 * in console or for audio devices. Assume the highest speakers
411 * configuration, to _not_ prohibit multi-channel audio playback.
412 */
413 if (!eld->spk_alloc)
414 eld->spk_alloc = 0xffff;
415
416 /*
417 * expand ELD's speaker allocation mask
418 *
419 * ELD tells the speaker mask in a compact(paired) form,
420 * expand ELD's notions to match the ones used by Audio InfoFrame.
421 */
422 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
423 if (eld->spk_alloc & (1 << i))
424 spk_mask |= eld_speaker_allocation_bits[i];
425 }
426
427 /* search for the first working match in the CA table */
428 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
429 if (channels == channel_allocations[i].channels &&
430 (spk_mask & channel_allocations[i].spk_mask) ==
431 channel_allocations[i].spk_mask) {
53d7d69d 432 ca = channel_allocations[i].ca_index;
079d88cc
WF		 433 break;
434 }
435 }
436
437 snd_print_channel_allocation(eld->spk_alloc, buf, sizeof(buf));
2abbf439 438 snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n",
53d7d69d 439 ca, channels, buf);
079d88cc 440
53d7d69d 441 return ca;
079d88cc
WF		 442}
443
444static void hdmi_debug_channel_mapping(struct hda_codec *codec,
445 hda_nid_t pin_nid)
446{
447#ifdef CONFIG_SND_DEBUG_VERBOSE
448 int i;
449 int slot;
450
451 for (i = 0; i < 8; i++) {
452 slot = snd_hda_codec_read(codec, pin_nid, 0,
453 AC_VERB_GET_HDMI_CHAN_SLOT, i);
454 printk(KERN_DEBUG "HDMI: ASP channel %d => slot %d\n",
455 slot >> 4, slot & 0xf);
456 }
457#endif
458}
459
460
461static void hdmi_setup_channel_mapping(struct hda_codec *codec,
462 hda_nid_t pin_nid,
53d7d69d 463 int ca)
079d88cc
WF		 464{
465 int i;
079d88cc
WF		 466 int err;
467
468 if (hdmi_channel_mapping[ca][1] == 0) {
469 for (i = 0; i < channel_allocations[ca].channels; i++)
470 hdmi_channel_mapping[ca][i] = i | (i << 4);
471 for (; i < 8; i++)
472 hdmi_channel_mapping[ca][i] = 0xf | (i << 4);
473 }
474
475 for (i = 0; i < 8; i++) {
476 err = snd_hda_codec_write(codec, pin_nid, 0,
477 AC_VERB_SET_HDMI_CHAN_SLOT,
478 hdmi_channel_mapping[ca][i]);
479 if (err) {
2abbf439
WF		 480 snd_printdd(KERN_NOTICE
481 "HDMI: channel mapping failed\n");
079d88cc
WF		 482 break;
483 }
484 }
485
486 hdmi_debug_channel_mapping(codec, pin_nid);
487}
488
489
490/*
491 * Audio InfoFrame routines
492 */
493
494/*
495 * Enable Audio InfoFrame Transmission
496 */
497static void hdmi_start_infoframe_trans(struct hda_codec *codec,
498 hda_nid_t pin_nid)
499{
500 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
501 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
502 AC_DIPXMIT_BEST);
503}
504
505/*
506 * Disable Audio InfoFrame Transmission
507 */
508static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
509 hda_nid_t pin_nid)
510{
511 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
512 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
513 AC_DIPXMIT_DISABLE);
514}
515
516static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
517{
518#ifdef CONFIG_SND_DEBUG_VERBOSE
519 int i;
520 int size;
521
522 size = snd_hdmi_get_eld_size(codec, pin_nid);
523 printk(KERN_DEBUG "HDMI: ELD buf size is %d\n", size);
524
525 for (i = 0; i < 8; i++) {
526 size = snd_hda_codec_read(codec, pin_nid, 0,
527 AC_VERB_GET_HDMI_DIP_SIZE, i);
528 printk(KERN_DEBUG "HDMI: DIP GP[%d] buf size is %d\n", i, size);
529 }
530#endif
531}
532
533static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
534{
535#ifdef BE_PARANOID
536 int i, j;
537 int size;
538 int pi, bi;
539 for (i = 0; i < 8; i++) {
540 size = snd_hda_codec_read(codec, pin_nid, 0,
541 AC_VERB_GET_HDMI_DIP_SIZE, i);
542 if (size == 0)
543 continue;
544
545 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
546 for (j = 1; j < 1000; j++) {
547 hdmi_write_dip_byte(codec, pin_nid, 0x0);
548 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
549 if (pi != i)
550 snd_printd(KERN_INFO "dip index %d: %d != %d\n",
551 bi, pi, i);
552 if (bi == 0) /* byte index wrapped around */
553 break;
554 }
555 snd_printd(KERN_INFO
556 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
557 i, size, j);
558 }
559#endif
560}
561
53d7d69d 562static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
079d88cc 563{
53d7d69d 564 u8 *bytes = (u8 *)hdmi_ai;
079d88cc
WF		 565 u8 sum = 0;
566 int i;
567
53d7d69d 568 hdmi_ai->checksum = 0;
079d88cc 569
53d7d69d 570 for (i = 0; i < sizeof(*hdmi_ai); i++)
079d88cc
WF		 571 sum += bytes[i];
572
53d7d69d 573 hdmi_ai->checksum = -sum;
079d88cc
WF		 574}
575
576static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
577 hda_nid_t pin_nid,
53d7d69d 578 u8 *dip, int size)
079d88cc 579{
079d88cc
WF		 580 int i;
581
582 hdmi_debug_dip_size(codec, pin_nid);
583 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
584
079d88cc 585 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d
WF		 586 for (i = 0; i < size; i++)
587 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
079d88cc
WF		 588}
589
590static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
53d7d69d 591 u8 *dip, int size)
079d88cc 592{
079d88cc
WF		 593 u8 val;
594 int i;
595
596 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
597 != AC_DIPXMIT_BEST)
598 return false;
599
600 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d 601 for (i = 0; i < size; i++) {
079d88cc
WF		 602 val = snd_hda_codec_read(codec, pin_nid, 0,
603 AC_VERB_GET_HDMI_DIP_DATA, 0);
53d7d69d 604 if (val != dip[i])
079d88cc
WF		 605 return false;
606 }
607
608 return true;
609}
610
611static void hdmi_setup_audio_infoframe(struct hda_codec *codec, hda_nid_t nid,
612 struct snd_pcm_substream *substream)
613{
614 struct hdmi_spec *spec = codec->spec;
615 hda_nid_t pin_nid;
53d7d69d
WF		 616 int channels = substream->runtime->channels;
617 int ca;
079d88cc 618 int i;
2b203dbb 619 union audio_infoframe ai;
079d88cc 620
53d7d69d 621 ca = hdmi_channel_allocation(codec, nid, channels);
079d88cc
WF		 622
623 for (i = 0; i < spec->num_pins; i++) {
624 if (spec->pin_cvt[i] != nid)
625 continue;
626 if (!spec->sink_eld[i].monitor_present)
627 continue;
628
629 pin_nid = spec->pin[i];
53d7d69d 630
2b203dbb 631 memset(&ai, 0, sizeof(ai));
53d7d69d 632 if (spec->sink_eld[i].conn_type == 0) { /* HDMI */
2b203dbb 633 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
53d7d69d 634
53d7d69d
WF		 635 hdmi_ai->type = 0x84;
636 hdmi_ai->ver = 0x01;
637 hdmi_ai->len = 0x0a;
638 hdmi_ai->CC02_CT47 = channels - 1;
11839aed 639 hdmi_ai->CA = ca;
53d7d69d
WF		 640 hdmi_checksum_audio_infoframe(hdmi_ai);
641 } else if (spec->sink_eld[i].conn_type == 1) { /* DisplayPort */
2b203dbb 642 struct dp_audio_infoframe *dp_ai = &ai.dp;
53d7d69d 643
53d7d69d
WF		 644 dp_ai->type = 0x84;
645 dp_ai->len = 0x1b;
646 dp_ai->ver = 0x11 << 2;
647 dp_ai->CC02_CT47 = channels - 1;
11839aed 648 dp_ai->CA = ca;
53d7d69d
WF		 649 } else {
650 snd_printd("HDMI: unknown connection type at pin %d\n",
651 pin_nid);
652 continue;
653 }
654
655 /*
656 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
657 * sizeof(*dp_ai) to avoid partial match/update problems when
658 * the user switches between HDMI/DP monitors.
659 */
2b203dbb
TI		 660 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
661 sizeof(ai))) {
2abbf439
WF		 662 snd_printdd("hdmi_setup_audio_infoframe: "
663 "cvt=%d pin=%d channels=%d\n",
664 nid, pin_nid,
53d7d69d
WF		 665 channels);
666 hdmi_setup_channel_mapping(codec, pin_nid, ca);
079d88cc 667 hdmi_stop_infoframe_trans(codec, pin_nid);
53d7d69d 668 hdmi_fill_audio_infoframe(codec, pin_nid,
2b203dbb 669 ai.bytes, sizeof(ai));
079d88cc
WF		 670 hdmi_start_infoframe_trans(codec, pin_nid);
671 }
672 }
673}
674
675
676/*
677 * Unsolicited events
678 */
679
38faddb1
TI		 680static void hdmi_present_sense(struct hda_codec *codec, hda_nid_t pin_nid,
681 struct hdmi_eld *eld);
682
079d88cc
WF		 683static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
684{
685 struct hdmi_spec *spec = codec->spec;
5d44f927
SW		 686 int pin_nid = res >> AC_UNSOL_RES_TAG_SHIFT;
687 int pd = !!(res & AC_UNSOL_RES_PD);
079d88cc
WF		 688 int eldv = !!(res & AC_UNSOL_RES_ELDV);
689 int index;
690
691 printk(KERN_INFO
692 "HDMI hot plug event: Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
5d44f927 693 pin_nid, pd, eldv);
079d88cc 694
5d44f927 695 index = hda_node_index(spec->pin, pin_nid);
079d88cc
WF		 696 if (index < 0)
697 return;
698
5d44f927 699 hdmi_present_sense(codec, pin_nid, &spec->sink_eld[index]);
079d88cc
WF		 700}
701
702static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
703{
704 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
705 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
706 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
707 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
708
709 printk(KERN_INFO
710 "HDMI CP event: PIN=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
711 tag,
712 subtag,
713 cp_state,
714 cp_ready);
715
716 /* TODO */
717 if (cp_state)
718 ;
719 if (cp_ready)
720 ;
721}
722
723
724static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
725{
726 struct hdmi_spec *spec = codec->spec;
727 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
728 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
729
730 if (hda_node_index(spec->pin, tag) < 0) {
731 snd_printd(KERN_INFO "Unexpected HDMI event tag 0x%x\n", tag);
732 return;
733 }
734
735 if (subtag == 0)
736 hdmi_intrinsic_event(codec, res);
737 else
738 hdmi_non_intrinsic_event(codec, res);
739}
740
741/*
742 * Callbacks
743 */
744
92f10b3f
TI		 745/* HBR should be Non-PCM, 8 channels */
746#define is_hbr_format(format) \
747 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
748
ea87d1c4 749static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t nid,
079d88cc
WF		 750 u32 stream_tag, int format)
751{
ea87d1c4 752 struct hdmi_spec *spec = codec->spec;
ea87d1c4
AH		 753 int pinctl;
754 int new_pinctl = 0;
755 int i;
756
757 for (i = 0; i < spec->num_pins; i++) {
758 if (spec->pin_cvt[i] != nid)
759 continue;
760 if (!(snd_hda_query_pin_caps(codec, spec->pin[i]) & AC_PINCAP_HBR))
761 continue;
762
763 pinctl = snd_hda_codec_read(codec, spec->pin[i], 0,
764 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
765
766 new_pinctl = pinctl & ~AC_PINCTL_EPT;
92f10b3f 767 if (is_hbr_format(format))
ea87d1c4
AH		 768 new_pinctl |= AC_PINCTL_EPT_HBR;
769 else
770 new_pinctl |= AC_PINCTL_EPT_NATIVE;
771
772 snd_printdd("hdmi_setup_stream: "
773 "NID=0x%x, %spinctl=0x%x\n",
774 spec->pin[i],
775 pinctl == new_pinctl ? "" : "new-",
776 new_pinctl);
777
778 if (pinctl != new_pinctl)
779 snd_hda_codec_write(codec, spec->pin[i], 0,
780 AC_VERB_SET_PIN_WIDGET_CONTROL,
781 new_pinctl);
782 }
783
92f10b3f 784 if (is_hbr_format(format) && !new_pinctl) {
ea87d1c4
AH		 785 snd_printdd("hdmi_setup_stream: HBR is not supported\n");
786 return -EINVAL;
787 }
079d88cc 788
4f347607 789 snd_hda_codec_setup_stream(codec, nid, stream_tag, 0, format);
ea87d1c4 790 return 0;
079d88cc
WF		 791}
792
bbbe3390
TI		 793/*
794 * HDA PCM callbacks
795 */
796static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
797 struct hda_codec *codec,
798 struct snd_pcm_substream *substream)
799{
800 struct hdmi_spec *spec = codec->spec;
801 struct hdmi_eld *eld;
802 struct hda_pcm_stream *codec_pars;
639cef0e 803 struct snd_pcm_runtime *runtime = substream->runtime;
bbbe3390
TI		 804 unsigned int idx;
805
806 for (idx = 0; idx < spec->num_cvts; idx++)
807 if (hinfo->nid == spec->cvt[idx])
808 break;
809 if (snd_BUG_ON(idx >= spec->num_cvts) ||
810 snd_BUG_ON(idx >= spec->num_pins))
811 return -EINVAL;
812
813 /* save the PCM info the codec provides */
814 codec_pars = &spec->codec_pcm_pars[idx];
815 if (!codec_pars->rates)
816 *codec_pars = *hinfo;
817
818 eld = &spec->sink_eld[idx];
c3d52105 819 if (!static_hdmi_pcm && eld->eld_valid) {
bbbe3390
TI		 820 hdmi_eld_update_pcm_info(eld, hinfo, codec_pars);
821 if (hinfo->channels_min > hinfo->channels_max ||
822 !hinfo->rates || !hinfo->formats)
823 return -ENODEV;
824 } else {
825 /* fallback to the codec default */
bbbe3390
TI		 826 hinfo->channels_max = codec_pars->channels_max;
827 hinfo->rates = codec_pars->rates;
828 hinfo->formats = codec_pars->formats;
829 hinfo->maxbps = codec_pars->maxbps;
830 }
639cef0e
TI		 831 /* store the updated parameters */
832 runtime->hw.channels_min = hinfo->channels_min;
833 runtime->hw.channels_max = hinfo->channels_max;
834 runtime->hw.formats = hinfo->formats;
835 runtime->hw.rates = hinfo->rates;
4fe2ca14
TI		 836
837 snd_pcm_hw_constraint_step(substream->runtime, 0,
838 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
bbbe3390
TI		 839 return 0;
840}
841
079d88cc
WF		 842/*
843 * HDA/HDMI auto parsing
844 */
079d88cc
WF		 845static int hdmi_read_pin_conn(struct hda_codec *codec, hda_nid_t pin_nid)
846{
847 struct hdmi_spec *spec = codec->spec;
848 hda_nid_t conn_list[HDA_MAX_CONNECTIONS];
849 int conn_len, curr;
850 int index;
851
852 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
853 snd_printk(KERN_WARNING
854 "HDMI: pin %d wcaps %#x "
855 "does not support connection list\n",
856 pin_nid, get_wcaps(codec, pin_nid));
857 return -EINVAL;
858 }
859
860 conn_len = snd_hda_get_connections(codec, pin_nid, conn_list,
861 HDA_MAX_CONNECTIONS);
862 if (conn_len > 1)
863 curr = snd_hda_codec_read(codec, pin_nid, 0,
864 AC_VERB_GET_CONNECT_SEL, 0);
865 else
866 curr = 0;
867
868 index = hda_node_index(spec->pin, pin_nid);
869 if (index < 0)
870 return -EINVAL;
871
872 spec->pin_cvt[index] = conn_list[curr];
873
874 return 0;
875}
876
877static void hdmi_present_sense(struct hda_codec *codec, hda_nid_t pin_nid,
878 struct hdmi_eld *eld)
879{
5d44f927
SW		 880 /*
881 * Always execute a GetPinSense verb here, even when called from
882 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
883 * response's PD bit is not the real PD value, but indicates that
884 * the real PD value changed. An older version of the HD-audio
885 * specification worked this way. Hence, we just ignore the data in
886 * the unsolicited response to avoid custom WARs.
887 */
079d88cc
WF		 888 int present = snd_hda_pin_sense(codec, pin_nid);
889
5d44f927
SW		 890 memset(eld, 0, sizeof(*eld));
891
079d88cc 892 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
5d44f927
SW		 893 if (eld->monitor_present)
894 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
895 else
896 eld->eld_valid = 0;
079d88cc 897
5d44f927
SW		 898 printk(KERN_INFO
899 "HDMI status: Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
900 pin_nid, eld->monitor_present, eld->eld_valid);
901
902 if (eld->eld_valid)
903 if (!snd_hdmi_get_eld(eld, codec, pin_nid))
904 snd_hdmi_show_eld(eld);
905
906 snd_hda_input_jack_report(codec, pin_nid);
079d88cc
WF		 907}
908
909static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
910{
911 struct hdmi_spec *spec = codec->spec;
07acecc1 912 int err;
079d88cc
WF		 913
914 if (spec->num_pins >= MAX_HDMI_PINS) {
915 snd_printk(KERN_WARNING
916 "HDMI: no space for pin %d\n", pin_nid);
3eaead57 917 return -E2BIG;
079d88cc
WF		 918 }
919
07acecc1
DH		 920 err = snd_hda_input_jack_add(codec, pin_nid,
921 SND_JACK_VIDEOOUT, NULL);
922 if (err < 0)
923 return err;
07acecc1 924
079d88cc
WF		 925 hdmi_present_sense(codec, pin_nid, &spec->sink_eld[spec->num_pins]);
926
927 spec->pin[spec->num_pins] = pin_nid;
928 spec->num_pins++;
929
079d88cc
WF		 930 return hdmi_read_pin_conn(codec, pin_nid);
931}
932
933static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t nid)
934{
116dcde6 935 int i, found_pin = 0;
079d88cc
WF		 936 struct hdmi_spec *spec = codec->spec;
937
116dcde6
DH		 938 for (i = 0; i < spec->num_pins; i++)
939 if (nid == spec->pin_cvt[i]) {
940 found_pin = 1;
941 break;
942 }
943
944 if (!found_pin) {
945 snd_printdd("HDMI: Skipping node %d (no connection)\n", nid);
946 return -EINVAL;
079d88cc
WF		 947 }
948
116dcde6
DH		 949 if (snd_BUG_ON(spec->num_cvts >= MAX_HDMI_CVTS))
950 return -E2BIG;
951
079d88cc
WF		 952 spec->cvt[spec->num_cvts] = nid;
953 spec->num_cvts++;
954
955 return 0;
956}
957
958static int hdmi_parse_codec(struct hda_codec *codec)
959{
960 hda_nid_t nid;
961 int i, nodes;
116dcde6
DH		 962 int num_tmp_cvts = 0;
963 hda_nid_t tmp_cvt[MAX_HDMI_CVTS];
079d88cc
WF		 964
965 nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid);
966 if (!nid || nodes < 0) {
967 snd_printk(KERN_WARNING "HDMI: failed to get afg sub nodes\n");
968 return -EINVAL;
969 }
970
971 for (i = 0; i < nodes; i++, nid++) {
972 unsigned int caps;
973 unsigned int type;
116dcde6 974 unsigned int config;
079d88cc
WF		 975
976 caps = snd_hda_param_read(codec, nid, AC_PAR_AUDIO_WIDGET_CAP);
977 type = get_wcaps_type(caps);
978
979 if (!(caps & AC_WCAP_DIGITAL))
980 continue;
981
982 switch (type) {
983 case AC_WID_AUD_OUT:
116dcde6
DH		 984 if (num_tmp_cvts >= MAX_HDMI_CVTS) {
985 snd_printk(KERN_WARNING
986 "HDMI: no space for converter %d\n", nid);
987 continue;
988 }
989 tmp_cvt[num_tmp_cvts] = nid;
990 num_tmp_cvts++;
079d88cc
WF		 991 break;
992 case AC_WID_PIN:
993 caps = snd_hda_param_read(codec, nid, AC_PAR_PIN_CAP);
994 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
995 continue;
116dcde6
DH		 996
997 config = snd_hda_codec_read(codec, nid, 0,
998 AC_VERB_GET_CONFIG_DEFAULT, 0);
999 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1000 continue;
1001
3eaead57 1002 hdmi_add_pin(codec, nid);
079d88cc
WF		 1003 break;
1004 }
1005 }
1006
116dcde6
DH		 1007 for (i = 0; i < num_tmp_cvts; i++)
1008 hdmi_add_cvt(codec, tmp_cvt[i]);
1009
079d88cc
WF		 1010 /*
1011 * G45/IbexPeak don't support EPSS: the unsolicited pin hot plug event
1012 * can be lost and presence sense verb will become inaccurate if the
1013 * HDA link is powered off at hot plug or hw initialization time.
1014 */
1015#ifdef CONFIG_SND_HDA_POWER_SAVE
1016 if (!(snd_hda_param_read(codec, codec->afg, AC_PAR_POWER_STATE) &
1017 AC_PWRST_EPSS))
1018 codec->bus->power_keep_link_on = 1;
1019#endif
1020
1021 return 0;
1022}
1023
84eb01be
TI		 1024/*
1025 */
1026static char *generic_hdmi_pcm_names[MAX_HDMI_CVTS] = {
1027 "HDMI 0",
1028 "HDMI 1",
1029 "HDMI 2",
73926656 1030 "HDMI 3",
84eb01be
TI		 1031};
1032
1033/*
1034 * HDMI callbacks
1035 */
1036
1037static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1038 struct hda_codec *codec,
1039 unsigned int stream_tag,
1040 unsigned int format,
1041 struct snd_pcm_substream *substream)
1042{
1043 hdmi_set_channel_count(codec, hinfo->nid,
1044 substream->runtime->channels);
1045
1046 hdmi_setup_audio_infoframe(codec, hinfo->nid, substream);
1047
1048 return hdmi_setup_stream(codec, hinfo->nid, stream_tag, format);
1049}
1050
fb79e1e0 1051static const struct hda_pcm_stream generic_hdmi_pcm_playback = {
84eb01be
TI		 1052 .substreams = 1,
1053 .channels_min = 2,
1054 .ops = {
1055 .open = hdmi_pcm_open,
1056 .prepare = generic_hdmi_playback_pcm_prepare,
1057 },
1058};
1059
1060static int generic_hdmi_build_pcms(struct hda_codec *codec)
1061{
1062 struct hdmi_spec *spec = codec->spec;
1063 struct hda_pcm *info = spec->pcm_rec;
1064 int i;
1065
1066 codec->num_pcms = spec->num_cvts;
1067 codec->pcm_info = info;
1068
1069 for (i = 0; i < codec->num_pcms; i++, info++) {
1070 unsigned int chans;
1071 struct hda_pcm_stream *pstr;
1072
1073 chans = get_wcaps(codec, spec->cvt[i]);
1074 chans = get_wcaps_channels(chans);
1075
1076 info->name = generic_hdmi_pcm_names[i];
1077 info->pcm_type = HDA_PCM_TYPE_HDMI;
1078 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
1079 if (spec->pcm_playback)
1080 *pstr = *spec->pcm_playback;
1081 else
1082 *pstr = generic_hdmi_pcm_playback;
1083 pstr->nid = spec->cvt[i];
1084 if (pstr->channels_max <= 2 && chans && chans <= 16)
1085 pstr->channels_max = chans;
1086 }
1087
1088 return 0;
1089}
1090
1091static int generic_hdmi_build_controls(struct hda_codec *codec)
1092{
1093 struct hdmi_spec *spec = codec->spec;
1094 int err;
1095 int i;
1096
1097 for (i = 0; i < codec->num_pcms; i++) {
74b654c9
SW		 1098 err = snd_hda_create_spdif_out_ctls(codec, spec->cvt[i],
1099 spec->cvt[i]);
84eb01be
TI		 1100 if (err < 0)
1101 return err;
1102 }
1103
1104 return 0;
1105}
1106
1107static int generic_hdmi_init(struct hda_codec *codec)
1108{
1109 struct hdmi_spec *spec = codec->spec;
1110 int i;
1111
1112 for (i = 0; spec->pin[i]; i++) {
1113 hdmi_enable_output(codec, spec->pin[i]);
1114 snd_hda_codec_write(codec, spec->pin[i], 0,
1115 AC_VERB_SET_UNSOLICITED_ENABLE,
1116 AC_USRSP_EN | spec->pin[i]);
1117 }
1118 return 0;
1119}
1120
1121static void generic_hdmi_free(struct hda_codec *codec)
1122{
1123 struct hdmi_spec *spec = codec->spec;
1124 int i;
1125
1126 for (i = 0; i < spec->num_pins; i++)
1127 snd_hda_eld_proc_free(codec, &spec->sink_eld[i]);
07acecc1 1128 snd_hda_input_jack_free(codec);
84eb01be
TI		 1129
1130 kfree(spec);
1131}
1132
fb79e1e0 1133static const struct hda_codec_ops generic_hdmi_patch_ops = {
84eb01be
TI		 1134 .init = generic_hdmi_init,
1135 .free = generic_hdmi_free,
1136 .build_pcms = generic_hdmi_build_pcms,
1137 .build_controls = generic_hdmi_build_controls,
1138 .unsol_event = hdmi_unsol_event,
1139};
1140
1141static int patch_generic_hdmi(struct hda_codec *codec)
1142{
1143 struct hdmi_spec *spec;
1144 int i;
1145
1146 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1147 if (spec == NULL)
1148 return -ENOMEM;
1149
1150 codec->spec = spec;
1151 if (hdmi_parse_codec(codec) < 0) {
1152 codec->spec = NULL;
1153 kfree(spec);
1154 return -EINVAL;
1155 }
1156 codec->patch_ops = generic_hdmi_patch_ops;
1157
1158 for (i = 0; i < spec->num_pins; i++)
1159 snd_hda_eld_proc_new(codec, &spec->sink_eld[i], i);
1160
1161 init_channel_allocations();
1162
1163 return 0;
1164}
1165
1166/*
1167 * Nvidia specific implementations
1168 */
1169
1170#define Nv_VERB_SET_Channel_Allocation 0xF79
1171#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
1172#define Nv_VERB_SET_Audio_Protection_On 0xF98
1173#define Nv_VERB_SET_Audio_Protection_Off 0xF99
1174
1175#define nvhdmi_master_con_nid_7x 0x04
1176#define nvhdmi_master_pin_nid_7x 0x05
1177
fb79e1e0 1178static const hda_nid_t nvhdmi_con_nids_7x[4] = {
84eb01be
TI		 1179 /*front, rear, clfe, rear_surr */
1180 0x6, 0x8, 0xa, 0xc,
1181};
1182
fb79e1e0 1183static const struct hda_verb nvhdmi_basic_init_7x[] = {
84eb01be
TI		 1184 /* set audio protect on */
1185 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
1186 /* enable digital output on pin widget */
1187 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1188 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1189 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1190 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1191 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1192 {} /* terminator */
1193};
1194
1195#ifdef LIMITED_RATE_FMT_SUPPORT
1196/* support only the safe format and rate */
1197#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
1198#define SUPPORTED_MAXBPS 16
1199#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
1200#else
1201/* support all rates and formats */
1202#define SUPPORTED_RATES \
1203 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
1204 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
1205 SNDRV_PCM_RATE_192000)
1206#define SUPPORTED_MAXBPS 24
1207#define SUPPORTED_FORMATS \
1208 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
1209#endif
1210
1211static int nvhdmi_7x_init(struct hda_codec *codec)
1212{
1213 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x);
1214 return 0;
1215}
1216
393004b2
ND		 1217static unsigned int channels_2_6_8[] = {
1218 2, 6, 8
1219};
1220
1221static unsigned int channels_2_8[] = {
1222 2, 8
1223};
1224
1225static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
1226 .count = ARRAY_SIZE(channels_2_6_8),
1227 .list = channels_2_6_8,
1228 .mask = 0,
1229};
1230
1231static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
1232 .count = ARRAY_SIZE(channels_2_8),
1233 .list = channels_2_8,
1234 .mask = 0,
1235};
1236
84eb01be
TI		 1237static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
1238 struct hda_codec *codec,
1239 struct snd_pcm_substream *substream)
1240{
1241 struct hdmi_spec *spec = codec->spec;
393004b2
ND		 1242 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
1243
1244 switch (codec->preset->id) {
1245 case 0x10de0002:
1246 case 0x10de0003:
1247 case 0x10de0005:
1248 case 0x10de0006:
1249 hw_constraints_channels = &hw_constraints_2_8_channels;
1250 break;
1251 case 0x10de0007:
1252 hw_constraints_channels = &hw_constraints_2_6_8_channels;
1253 break;
1254 default:
1255 break;
1256 }
1257
1258 if (hw_constraints_channels != NULL) {
1259 snd_pcm_hw_constraint_list(substream->runtime, 0,
1260 SNDRV_PCM_HW_PARAM_CHANNELS,
1261 hw_constraints_channels);
ad09fc9d
TI		 1262 } else {
1263 snd_pcm_hw_constraint_step(substream->runtime, 0,
1264 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
393004b2
ND		 1265 }
1266
84eb01be
TI		 1267 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
1268}
1269
1270static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
1271 struct hda_codec *codec,
1272 struct snd_pcm_substream *substream)
1273{
1274 struct hdmi_spec *spec = codec->spec;
1275 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
1276}
1277
1278static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1279 struct hda_codec *codec,
1280 unsigned int stream_tag,
1281 unsigned int format,
1282 struct snd_pcm_substream *substream)
1283{
1284 struct hdmi_spec *spec = codec->spec;
1285 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
1286 stream_tag, format, substream);
1287}
1288
1f348522
AP		 1289static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
1290 int channels)
1291{
1292 unsigned int chanmask;
1293 int chan = channels ? (channels - 1) : 1;
1294
1295 switch (channels) {
1296 default:
1297 case 0:
1298 case 2:
1299 chanmask = 0x00;
1300 break;
1301 case 4:
1302 chanmask = 0x08;
1303 break;
1304 case 6:
1305 chanmask = 0x0b;
1306 break;
1307 case 8:
1308 chanmask = 0x13;
1309 break;
1310 }
1311
1312 /* Set the audio infoframe channel allocation and checksum fields. The
1313 * channel count is computed implicitly by the hardware. */
1314 snd_hda_codec_write(codec, 0x1, 0,
1315 Nv_VERB_SET_Channel_Allocation, chanmask);
1316
1317 snd_hda_codec_write(codec, 0x1, 0,
1318 Nv_VERB_SET_Info_Frame_Checksum,
1319 (0x71 - chan - chanmask));
1320}
1321
84eb01be
TI		 1322static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
1323 struct hda_codec *codec,
1324 struct snd_pcm_substream *substream)
1325{
1326 struct hdmi_spec *spec = codec->spec;
1327 int i;
1328
1329 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
1330 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
1331 for (i = 0; i < 4; i++) {
1332 /* set the stream id */
1333 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
1334 AC_VERB_SET_CHANNEL_STREAMID, 0);
1335 /* set the stream format */
1336 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
1337 AC_VERB_SET_STREAM_FORMAT, 0);
1338 }
1339
1f348522
AP		 1340 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
1341 * streams are disabled. */
1342 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
1343
84eb01be
TI		 1344 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
1345}
1346
1347static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
1348 struct hda_codec *codec,
1349 unsigned int stream_tag,
1350 unsigned int format,
1351 struct snd_pcm_substream *substream)
1352{
1353 int chs;
1f348522 1354 unsigned int dataDCC1, dataDCC2, channel_id;
84eb01be 1355 int i;
7c935976
SW		 1356 struct hdmi_spec *spec = codec->spec;
1357 struct hda_spdif_out *spdif =
1358 snd_hda_spdif_out_of_nid(codec, spec->cvt[0]);
84eb01be
TI		 1359
1360 mutex_lock(&codec->spdif_mutex);
1361
1362 chs = substream->runtime->channels;
84eb01be 1363
84eb01be
TI		 1364 dataDCC1 = AC_DIG1_ENABLE | AC_DIG1_COPYRIGHT;
1365 dataDCC2 = 0x2;
1366
84eb01be 1367 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
7c935976 1368 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 1369 snd_hda_codec_write(codec,
1370 nvhdmi_master_con_nid_7x,
1371 0,
1372 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 1373 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 1374
1375 /* set the stream id */
1376 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
1377 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
1378
1379 /* set the stream format */
1380 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
1381 AC_VERB_SET_STREAM_FORMAT, format);
1382
1383 /* turn on again (if needed) */
1384 /* enable and set the channel status audio/data flag */
7c935976 1385 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 1386 snd_hda_codec_write(codec,
1387 nvhdmi_master_con_nid_7x,
1388 0,
1389 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 1390 spdif->ctls & 0xff);
84eb01be
TI		 1391 snd_hda_codec_write(codec,
1392 nvhdmi_master_con_nid_7x,
1393 0,
1394 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
1395 }
1396
1397 for (i = 0; i < 4; i++) {
1398 if (chs == 2)
1399 channel_id = 0;
1400 else
1401 channel_id = i * 2;
1402
1403 /* turn off SPDIF once;
1404 *otherwise the IEC958 bits won't be updated
1405 */
1406 if (codec->spdif_status_reset &&
7c935976 1407 (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 1408 snd_hda_codec_write(codec,
1409 nvhdmi_con_nids_7x[i],
1410 0,
1411 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 1412 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 1413 /* set the stream id */
1414 snd_hda_codec_write(codec,
1415 nvhdmi_con_nids_7x[i],
1416 0,
1417 AC_VERB_SET_CHANNEL_STREAMID,
1418 (stream_tag << 4) | channel_id);
1419 /* set the stream format */
1420 snd_hda_codec_write(codec,
1421 nvhdmi_con_nids_7x[i],
1422 0,
1423 AC_VERB_SET_STREAM_FORMAT,
1424 format);
1425 /* turn on again (if needed) */
1426 /* enable and set the channel status audio/data flag */
1427 if (codec->spdif_status_reset &&
7c935976 1428 (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 1429 snd_hda_codec_write(codec,
1430 nvhdmi_con_nids_7x[i],
1431 0,
1432 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 1433 spdif->ctls & 0xff);
84eb01be
TI		 1434 snd_hda_codec_write(codec,
1435 nvhdmi_con_nids_7x[i],
1436 0,
1437 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
1438 }
1439 }
1440
1f348522 1441 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
84eb01be
TI		 1442
1443 mutex_unlock(&codec->spdif_mutex);
1444 return 0;
1445}
1446
fb79e1e0 1447static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
84eb01be
TI		 1448 .substreams = 1,
1449 .channels_min = 2,
1450 .channels_max = 8,
1451 .nid = nvhdmi_master_con_nid_7x,
1452 .rates = SUPPORTED_RATES,
1453 .maxbps = SUPPORTED_MAXBPS,
1454 .formats = SUPPORTED_FORMATS,
1455 .ops = {
1456 .open = simple_playback_pcm_open,
1457 .close = nvhdmi_8ch_7x_pcm_close,
1458 .prepare = nvhdmi_8ch_7x_pcm_prepare
1459 },
1460};
1461
fb79e1e0 1462static const struct hda_pcm_stream nvhdmi_pcm_playback_2ch = {
84eb01be
TI		 1463 .substreams = 1,
1464 .channels_min = 2,
1465 .channels_max = 2,
1466 .nid = nvhdmi_master_con_nid_7x,
1467 .rates = SUPPORTED_RATES,
1468 .maxbps = SUPPORTED_MAXBPS,
1469 .formats = SUPPORTED_FORMATS,
1470 .ops = {
1471 .open = simple_playback_pcm_open,
1472 .close = simple_playback_pcm_close,
1473 .prepare = simple_playback_pcm_prepare
1474 },
1475};
1476
fb79e1e0 1477static const struct hda_codec_ops nvhdmi_patch_ops_8ch_7x = {
84eb01be
TI		 1478 .build_controls = generic_hdmi_build_controls,
1479 .build_pcms = generic_hdmi_build_pcms,
1480 .init = nvhdmi_7x_init,
1481 .free = generic_hdmi_free,
1482};
1483
fb79e1e0 1484static const struct hda_codec_ops nvhdmi_patch_ops_2ch = {
84eb01be
TI		 1485 .build_controls = generic_hdmi_build_controls,
1486 .build_pcms = generic_hdmi_build_pcms,
1487 .init = nvhdmi_7x_init,
1488 .free = generic_hdmi_free,
1489};
1490
84eb01be
TI		 1491static int patch_nvhdmi_2ch(struct hda_codec *codec)
1492{
1493 struct hdmi_spec *spec;
1494
1495 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1496 if (spec == NULL)
1497 return -ENOMEM;
1498
1499 codec->spec = spec;
1500
1501 spec->multiout.num_dacs = 0; /* no analog */
1502 spec->multiout.max_channels = 2;
1503 spec->multiout.dig_out_nid = nvhdmi_master_con_nid_7x;
84eb01be
TI		 1504 spec->num_cvts = 1;
1505 spec->cvt[0] = nvhdmi_master_con_nid_7x;
1506 spec->pcm_playback = &nvhdmi_pcm_playback_2ch;
1507
1508 codec->patch_ops = nvhdmi_patch_ops_2ch;
1509
1510 return 0;
1511}
1512
1513static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
1514{
1515 struct hdmi_spec *spec;
1516 int err = patch_nvhdmi_2ch(codec);
1517
1518 if (err < 0)
1519 return err;
1520 spec = codec->spec;
1521 spec->multiout.max_channels = 8;
1522 spec->pcm_playback = &nvhdmi_pcm_playback_8ch_7x;
1523 codec->patch_ops = nvhdmi_patch_ops_8ch_7x;
1f348522
AP		 1524
1525 /* Initialize the audio infoframe channel mask and checksum to something
1526 * valid */
1527 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
1528
84eb01be
TI		 1529 return 0;
1530}
1531
1532/*
1533 * ATI-specific implementations
1534 *
1535 * FIXME: we may omit the whole this and use the generic code once after
1536 * it's confirmed to work.
1537 */
1538
1539#define ATIHDMI_CVT_NID 0x02 /* audio converter */
1540#define ATIHDMI_PIN_NID 0x03 /* HDMI output pin */
1541
1542static int atihdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1543 struct hda_codec *codec,
1544 unsigned int stream_tag,
1545 unsigned int format,
1546 struct snd_pcm_substream *substream)
1547{
1548 struct hdmi_spec *spec = codec->spec;
1549 int chans = substream->runtime->channels;
1550 int i, err;
1551
1552 err = simple_playback_pcm_prepare(hinfo, codec, stream_tag, format,
1553 substream);
1554 if (err < 0)
1555 return err;
1556 snd_hda_codec_write(codec, spec->cvt[0], 0, AC_VERB_SET_CVT_CHAN_COUNT,
1557 chans - 1);
1558 /* FIXME: XXX */
1559 for (i = 0; i < chans; i++) {
1560 snd_hda_codec_write(codec, spec->cvt[0], 0,
1561 AC_VERB_SET_HDMI_CHAN_SLOT,
1562 (i << 4) | i);
1563 }
1564 return 0;
1565}
1566
fb79e1e0 1567static const struct hda_pcm_stream atihdmi_pcm_digital_playback = {
84eb01be
TI		 1568 .substreams = 1,
1569 .channels_min = 2,
1570 .channels_max = 2,
1571 .nid = ATIHDMI_CVT_NID,
1572 .ops = {
1573 .open = simple_playback_pcm_open,
1574 .close = simple_playback_pcm_close,
1575 .prepare = atihdmi_playback_pcm_prepare
1576 },
1577};
1578
fb79e1e0 1579static const struct hda_verb atihdmi_basic_init[] = {
84eb01be
TI		 1580 /* enable digital output on pin widget */
1581 { 0x03, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT },
1582 {} /* terminator */
1583};
1584
1585static int atihdmi_init(struct hda_codec *codec)
1586{
1587 struct hdmi_spec *spec = codec->spec;
1588
1589 snd_hda_sequence_write(codec, atihdmi_basic_init);
1590 /* SI codec requires to unmute the pin */
1591 if (get_wcaps(codec, spec->pin[0]) & AC_WCAP_OUT_AMP)
1592 snd_hda_codec_write(codec, spec->pin[0], 0,
1593 AC_VERB_SET_AMP_GAIN_MUTE,
1594 AMP_OUT_UNMUTE);
1595 return 0;
1596}
1597
fb79e1e0 1598static const struct hda_codec_ops atihdmi_patch_ops = {
84eb01be
TI		 1599 .build_controls = generic_hdmi_build_controls,
1600 .build_pcms = generic_hdmi_build_pcms,
1601 .init = atihdmi_init,
1602 .free = generic_hdmi_free,
1603};
1604
1605
1606static int patch_atihdmi(struct hda_codec *codec)
1607{
1608 struct hdmi_spec *spec;
1609
1610 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1611 if (spec == NULL)
1612 return -ENOMEM;
1613
1614 codec->spec = spec;
1615
1616 spec->multiout.num_dacs = 0; /* no analog */
1617 spec->multiout.max_channels = 2;
1618 spec->multiout.dig_out_nid = ATIHDMI_CVT_NID;
1619 spec->num_cvts = 1;
1620 spec->cvt[0] = ATIHDMI_CVT_NID;
1621 spec->pin[0] = ATIHDMI_PIN_NID;
1622 spec->pcm_playback = &atihdmi_pcm_digital_playback;
1623
1624 codec->patch_ops = atihdmi_patch_ops;
1625
1626 return 0;
1627}
1628
1629
1630/*
1631 * patch entries
1632 */
fb79e1e0 1633static const struct hda_codec_preset snd_hda_preset_hdmi[] = {
84eb01be
TI		 1634{ .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi },
1635{ .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi },
1636{ .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi },
36e9c135 1637{ .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 1638{ .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi },
1639{ .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi },
1640{ .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi },
1641{ .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
1642{ .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
1643{ .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
1644{ .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
1645{ .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x },
5d44f927
SW		 1646{ .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_generic_hdmi },
1647{ .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_generic_hdmi },
1648{ .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_generic_hdmi },
1649{ .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_generic_hdmi },
1650{ .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_generic_hdmi },
1651{ .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_generic_hdmi },
1652{ .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_generic_hdmi },
1653{ .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_generic_hdmi },
1654{ .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_generic_hdmi },
1655{ .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_generic_hdmi },
1656{ .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_generic_hdmi },
c8900a0f 1657/* 17 is known to be absent */
5d44f927
SW		 1658{ .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_generic_hdmi },
1659{ .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_generic_hdmi },
1660{ .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_generic_hdmi },
1661{ .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_generic_hdmi },
1662{ .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_generic_hdmi },
1663{ .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_generic_hdmi },
1664{ .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_generic_hdmi },
1665{ .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_generic_hdmi },
1666{ .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_generic_hdmi },
1667{ .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_generic_hdmi },
84eb01be
TI		 1668{ .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
1669{ .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
1670{ .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
1671{ .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi },
1672{ .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi },
1673{ .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi },
1674{ .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
1675{ .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
591e610d 1676{ .id = 0x80862806, .name = "PantherPoint HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 1677{ .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
1678{} /* terminator */
1679};
1680
1681MODULE_ALIAS("snd-hda-codec-id:1002793c");
1682MODULE_ALIAS("snd-hda-codec-id:10027919");
1683MODULE_ALIAS("snd-hda-codec-id:1002791a");
1684MODULE_ALIAS("snd-hda-codec-id:1002aa01");
1685MODULE_ALIAS("snd-hda-codec-id:10951390");
1686MODULE_ALIAS("snd-hda-codec-id:10951392");
1687MODULE_ALIAS("snd-hda-codec-id:10de0002");
1688MODULE_ALIAS("snd-hda-codec-id:10de0003");
1689MODULE_ALIAS("snd-hda-codec-id:10de0005");
1690MODULE_ALIAS("snd-hda-codec-id:10de0006");
1691MODULE_ALIAS("snd-hda-codec-id:10de0007");
1692MODULE_ALIAS("snd-hda-codec-id:10de000a");
1693MODULE_ALIAS("snd-hda-codec-id:10de000b");
1694MODULE_ALIAS("snd-hda-codec-id:10de000c");
1695MODULE_ALIAS("snd-hda-codec-id:10de000d");
1696MODULE_ALIAS("snd-hda-codec-id:10de0010");
1697MODULE_ALIAS("snd-hda-codec-id:10de0011");
1698MODULE_ALIAS("snd-hda-codec-id:10de0012");
1699MODULE_ALIAS("snd-hda-codec-id:10de0013");
1700MODULE_ALIAS("snd-hda-codec-id:10de0014");
c8900a0f
RS		 1701MODULE_ALIAS("snd-hda-codec-id:10de0015");
1702MODULE_ALIAS("snd-hda-codec-id:10de0016");
84eb01be
TI		 1703MODULE_ALIAS("snd-hda-codec-id:10de0018");
1704MODULE_ALIAS("snd-hda-codec-id:10de0019");
1705MODULE_ALIAS("snd-hda-codec-id:10de001a");
1706MODULE_ALIAS("snd-hda-codec-id:10de001b");
1707MODULE_ALIAS("snd-hda-codec-id:10de001c");
1708MODULE_ALIAS("snd-hda-codec-id:10de0040");
1709MODULE_ALIAS("snd-hda-codec-id:10de0041");
1710MODULE_ALIAS("snd-hda-codec-id:10de0042");
1711MODULE_ALIAS("snd-hda-codec-id:10de0043");
1712MODULE_ALIAS("snd-hda-codec-id:10de0044");
1713MODULE_ALIAS("snd-hda-codec-id:10de0067");
1714MODULE_ALIAS("snd-hda-codec-id:10de8001");
1715MODULE_ALIAS("snd-hda-codec-id:17e80047");
1716MODULE_ALIAS("snd-hda-codec-id:80860054");
1717MODULE_ALIAS("snd-hda-codec-id:80862801");
1718MODULE_ALIAS("snd-hda-codec-id:80862802");
1719MODULE_ALIAS("snd-hda-codec-id:80862803");
1720MODULE_ALIAS("snd-hda-codec-id:80862804");
1721MODULE_ALIAS("snd-hda-codec-id:80862805");
591e610d 1722MODULE_ALIAS("snd-hda-codec-id:80862806");
84eb01be
TI		 1723MODULE_ALIAS("snd-hda-codec-id:808629fb");
1724
1725MODULE_LICENSE("GPL");
1726MODULE_DESCRIPTION("HDMI HD-audio codec");
1727MODULE_ALIAS("snd-hda-codec-intelhdmi");
1728MODULE_ALIAS("snd-hda-codec-nvhdmi");
1729MODULE_ALIAS("snd-hda-codec-atihdmi");
1730
1731static struct hda_codec_preset_list intel_list = {
1732 .preset = snd_hda_preset_hdmi,
1733 .owner = THIS_MODULE,
1734};
1735
1736static int __init patch_hdmi_init(void)
1737{
1738 return snd_hda_add_codec_preset(&intel_list);
1739}
1740
1741static void __exit patch_hdmi_exit(void)
1742{
1743 snd_hda_delete_codec_preset(&intel_list);
1744}
1745
1746module_init(patch_hdmi_init)
1747module_exit(patch_hdmi_exit)
Linux 6.x block layer and io_uring tree(s)