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Merge tag 'asoc-v3.12-2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie...
[linux-block.git] / sound / pci / hda / patch_hdmi.c
CommitLineData
079d88cc
WF		 1/*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
84eb01be
TI		 6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
079d88cc
WF		 9 *
10 * Authors:
11 * Wu Fengguang <wfg@linux.intel.com>
12 *
13 * Maintained by:
14 * Wu Fengguang <wfg@linux.intel.com>
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the Free
18 * Software Foundation; either version 2 of the License, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful, but
22 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
23 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
24 * for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software Foundation,
28 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
84eb01be
TI		 31#include <linux/init.h>
32#include <linux/delay.h>
33#include <linux/slab.h>
65a77217 34#include <linux/module.h>
84eb01be 35#include <sound/core.h>
07acecc1 36#include <sound/jack.h>
433968da 37#include <sound/asoundef.h>
d45e6889 38#include <sound/tlv.h>
84eb01be
TI		 39#include "hda_codec.h"
40#include "hda_local.h"
1835a0f9 41#include "hda_jack.h"
84eb01be 42
0ebaa24c
TI		 43static bool static_hdmi_pcm;
44module_param(static_hdmi_pcm, bool, 0644);
45MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
46
384a48d7
SW		 47struct hdmi_spec_per_cvt {
48 hda_nid_t cvt_nid;
49 int assigned;
50 unsigned int channels_min;
51 unsigned int channels_max;
52 u32 rates;
53 u64 formats;
54 unsigned int maxbps;
55};
079d88cc 56
4eea3091
TI		 57/* max. connections to a widget */
58#define HDA_MAX_CONNECTIONS 32
59
384a48d7
SW		 60struct hdmi_spec_per_pin {
61 hda_nid_t pin_nid;
62 int num_mux_nids;
63 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
744626da
WF		 64
65 struct hda_codec *codec;
384a48d7 66 struct hdmi_eld sink_eld;
744626da 67 struct delayed_work work;
92c69e79 68 struct snd_kcontrol *eld_ctl;
c6e8453e 69 int repoll_count;
1a6003b5 70 bool non_pcm;
d45e6889
TI		 71 bool chmap_set; /* channel-map override by ALSA API? */
72 unsigned char chmap[8]; /* ALSA API channel-map */
bce0d2a8 73 char pcm_name[8]; /* filled in build_pcm callbacks */
384a48d7 74};
079d88cc 75
384a48d7
SW		 76struct hdmi_spec {
77 int num_cvts;
bce0d2a8
TI		 78 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
79 hda_nid_t cvt_nids[4]; /* only for haswell fix */
079d88cc 80
384a48d7 81 int num_pins;
bce0d2a8
TI		 82 struct snd_array pins; /* struct hdmi_spec_per_pin */
83 struct snd_array pcm_rec; /* struct hda_pcm */
d45e6889 84 unsigned int channels_max; /* max over all cvts */
079d88cc 85
4bd038f9 86 struct hdmi_eld temp_eld;
079d88cc 87 /*
384a48d7 88 * Non-generic ATI/NVIDIA specific
079d88cc
WF		 89 */
90 struct hda_multi_out multiout;
d0b1252d 91 struct hda_pcm_stream pcm_playback;
079d88cc
WF		 92};
93
94
95struct hdmi_audio_infoframe {
96 u8 type; /* 0x84 */
97 u8 ver; /* 0x01 */
98 u8 len; /* 0x0a */
99
53d7d69d
WF		 100 u8 checksum;
101
079d88cc
WF		 102 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
103 u8 SS01_SF24;
104 u8 CXT04;
105 u8 CA;
106 u8 LFEPBL01_LSV36_DM_INH7;
53d7d69d
WF		 107};
108
109struct dp_audio_infoframe {
110 u8 type; /* 0x84 */
111 u8 len; /* 0x1b */
112 u8 ver; /* 0x11 << 2 */
113
114 u8 CC02_CT47; /* match with HDMI infoframe from this on */
115 u8 SS01_SF24;
116 u8 CXT04;
117 u8 CA;
118 u8 LFEPBL01_LSV36_DM_INH7;
079d88cc
WF		 119};
120
2b203dbb
TI		 121union audio_infoframe {
122 struct hdmi_audio_infoframe hdmi;
123 struct dp_audio_infoframe dp;
124 u8 bytes[0];
125};
126
079d88cc
WF		 127/*
128 * CEA speaker placement:
129 *
130 * FLH FCH FRH
131 * FLW FL FLC FC FRC FR FRW
132 *
133 * LFE
134 * TC
135 *
136 * RL RLC RC RRC RR
137 *
138 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
139 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
140 */
141enum cea_speaker_placement {
142 FL = (1 << 0), /* Front Left */
143 FC = (1 << 1), /* Front Center */
144 FR = (1 << 2), /* Front Right */
145 FLC = (1 << 3), /* Front Left Center */
146 FRC = (1 << 4), /* Front Right Center */
147 RL = (1 << 5), /* Rear Left */
148 RC = (1 << 6), /* Rear Center */
149 RR = (1 << 7), /* Rear Right */
150 RLC = (1 << 8), /* Rear Left Center */
151 RRC = (1 << 9), /* Rear Right Center */
152 LFE = (1 << 10), /* Low Frequency Effect */
153 FLW = (1 << 11), /* Front Left Wide */
154 FRW = (1 << 12), /* Front Right Wide */
155 FLH = (1 << 13), /* Front Left High */
156 FCH = (1 << 14), /* Front Center High */
157 FRH = (1 << 15), /* Front Right High */
158 TC = (1 << 16), /* Top Center */
159};
160
161/*
162 * ELD SA bits in the CEA Speaker Allocation data block
163 */
164static int eld_speaker_allocation_bits[] = {
165 [0] = FL | FR,
166 [1] = LFE,
167 [2] = FC,
168 [3] = RL | RR,
169 [4] = RC,
170 [5] = FLC | FRC,
171 [6] = RLC | RRC,
172 /* the following are not defined in ELD yet */
173 [7] = FLW | FRW,
174 [8] = FLH | FRH,
175 [9] = TC,
176 [10] = FCH,
177};
178
179struct cea_channel_speaker_allocation {
180 int ca_index;
181 int speakers[8];
182
183 /* derived values, just for convenience */
184 int channels;
185 int spk_mask;
186};
187
188/*
189 * ALSA sequence is:
190 *
191 * surround40 surround41 surround50 surround51 surround71
192 * ch0 front left = = = =
193 * ch1 front right = = = =
194 * ch2 rear left = = = =
195 * ch3 rear right = = = =
196 * ch4 LFE center center center
197 * ch5 LFE LFE
198 * ch6 side left
199 * ch7 side right
200 *
201 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
202 */
203static int hdmi_channel_mapping[0x32][8] = {
204 /* stereo */
205 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
206 /* 2.1 */
207 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
208 /* Dolby Surround */
209 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
210 /* surround40 */
211 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
212 /* 4ch */
213 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
214 /* surround41 */
9396d317 215 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
079d88cc
WF		 216 /* surround50 */
217 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
218 /* surround51 */
219 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
220 /* 7.1 */
221 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
222};
223
224/*
225 * This is an ordered list!
226 *
227 * The preceding ones have better chances to be selected by
53d7d69d 228 * hdmi_channel_allocation().
079d88cc
WF		 229 */
230static struct cea_channel_speaker_allocation channel_allocations[] = {
231/* channel: 7 6 5 4 3 2 1 0 */
232{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
233 /* 2.1 */
234{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
235 /* Dolby Surround */
236{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
237 /* surround40 */
238{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
239 /* surround41 */
240{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
241 /* surround50 */
242{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
243 /* surround51 */
244{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
245 /* 6.1 */
246{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
247 /* surround71 */
248{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
249
250{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
251{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
252{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
253{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
254{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
255{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
256{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
257{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
258{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
259{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
260{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
261{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
262{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
263{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
264{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
265{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
266{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
267{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
268{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
269{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
270{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
271{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
272{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
273{ .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
274{ .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
275{ .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
276{ .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
277{ .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
278{ .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
279{ .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
280{ .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
281{ .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
282{ .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
283{ .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
284{ .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
285{ .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
286{ .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
287{ .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
288{ .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
289{ .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
290{ .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
291};
292
293
294/*
295 * HDMI routines
296 */
297
bce0d2a8
TI		 298#define get_pin(spec, idx) \
299 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
300#define get_cvt(spec, idx) \
301 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
302#define get_pcm_rec(spec, idx) \
303 ((struct hda_pcm *)snd_array_elem(&spec->pcm_rec, idx))
304
384a48d7 305static int pin_nid_to_pin_index(struct hdmi_spec *spec, hda_nid_t pin_nid)
079d88cc 306{
384a48d7 307 int pin_idx;
079d88cc 308
384a48d7 309 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
bce0d2a8 310 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
384a48d7 311 return pin_idx;
079d88cc 312
384a48d7
SW		 313 snd_printk(KERN_WARNING "HDMI: pin nid %d not registered\n", pin_nid);
314 return -EINVAL;
315}
316
317static int hinfo_to_pin_index(struct hdmi_spec *spec,
318 struct hda_pcm_stream *hinfo)
319{
320 int pin_idx;
321
322 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
bce0d2a8 323 if (get_pcm_rec(spec, pin_idx)->stream == hinfo)
384a48d7
SW		 324 return pin_idx;
325
326 snd_printk(KERN_WARNING "HDMI: hinfo %p not registered\n", hinfo);
327 return -EINVAL;
328}
329
330static int cvt_nid_to_cvt_index(struct hdmi_spec *spec, hda_nid_t cvt_nid)
331{
332 int cvt_idx;
333
334 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
bce0d2a8 335 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
384a48d7
SW		 336 return cvt_idx;
337
338 snd_printk(KERN_WARNING "HDMI: cvt nid %d not registered\n", cvt_nid);
079d88cc
WF		 339 return -EINVAL;
340}
341
14bc52b8
PLB		 342static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
343 struct snd_ctl_elem_info *uinfo)
344{
345 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9
DH		 346 struct hdmi_spec *spec = codec->spec;
347 struct hdmi_eld *eld;
14bc52b8
PLB		 348 int pin_idx;
349
14bc52b8
PLB		 350 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
351
352 pin_idx = kcontrol->private_value;
bce0d2a8 353 eld = &get_pin(spec, pin_idx)->sink_eld;
68e03de9 354
4bd038f9 355 mutex_lock(&eld->lock);
68e03de9 356 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
4bd038f9 357 mutex_unlock(&eld->lock);
14bc52b8
PLB		 358
359 return 0;
360}
361
362static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
363 struct snd_ctl_elem_value *ucontrol)
364{
365 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
68e03de9
DH		 366 struct hdmi_spec *spec = codec->spec;
367 struct hdmi_eld *eld;
14bc52b8
PLB		 368 int pin_idx;
369
14bc52b8 370 pin_idx = kcontrol->private_value;
bce0d2a8 371 eld = &get_pin(spec, pin_idx)->sink_eld;
68e03de9 372
4bd038f9 373 mutex_lock(&eld->lock);
68e03de9 374 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data)) {
4bd038f9 375 mutex_unlock(&eld->lock);
68e03de9
DH		 376 snd_BUG();
377 return -EINVAL;
378 }
379
380 memset(ucontrol->value.bytes.data, 0,
381 ARRAY_SIZE(ucontrol->value.bytes.data));
382 if (eld->eld_valid)
383 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
384 eld->eld_size);
4bd038f9 385 mutex_unlock(&eld->lock);
14bc52b8
PLB		 386
387 return 0;
388}
389
390static struct snd_kcontrol_new eld_bytes_ctl = {
391 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
392 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
393 .name = "ELD",
394 .info = hdmi_eld_ctl_info,
395 .get = hdmi_eld_ctl_get,
396};
397
398static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
399 int device)
400{
401 struct snd_kcontrol *kctl;
402 struct hdmi_spec *spec = codec->spec;
403 int err;
404
405 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
406 if (!kctl)
407 return -ENOMEM;
408 kctl->private_value = pin_idx;
409 kctl->id.device = device;
410
bce0d2a8 411 err = snd_hda_ctl_add(codec, get_pin(spec, pin_idx)->pin_nid, kctl);
14bc52b8
PLB		 412 if (err < 0)
413 return err;
414
bce0d2a8 415 get_pin(spec, pin_idx)->eld_ctl = kctl;
14bc52b8
PLB		 416 return 0;
417}
418
079d88cc
WF		 419#ifdef BE_PARANOID
420static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
421 int *packet_index, int *byte_index)
422{
423 int val;
424
425 val = snd_hda_codec_read(codec, pin_nid, 0,
426 AC_VERB_GET_HDMI_DIP_INDEX, 0);
427
428 *packet_index = val >> 5;
429 *byte_index = val & 0x1f;
430}
431#endif
432
433static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
434 int packet_index, int byte_index)
435{
436 int val;
437
438 val = (packet_index << 5) | (byte_index & 0x1f);
439
440 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
441}
442
443static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
444 unsigned char val)
445{
446 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
447}
448
384a48d7 449static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
079d88cc
WF		 450{
451 /* Unmute */
452 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
453 snd_hda_codec_write(codec, pin_nid, 0,
454 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
6169b673
TI		 455 /* Enable pin out: some machines with GM965 gets broken output when
456 * the pin is disabled or changed while using with HDMI
457 */
079d88cc 458 snd_hda_codec_write(codec, pin_nid, 0,
6169b673 459 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
079d88cc
WF		 460}
461
384a48d7 462static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc 463{
384a48d7 464 return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
079d88cc
WF		 465 AC_VERB_GET_CVT_CHAN_COUNT, 0);
466}
467
468static void hdmi_set_channel_count(struct hda_codec *codec,
384a48d7 469 hda_nid_t cvt_nid, int chs)
079d88cc 470{
384a48d7
SW		 471 if (chs != hdmi_get_channel_count(codec, cvt_nid))
472 snd_hda_codec_write(codec, cvt_nid, 0,
079d88cc
WF		 473 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
474}
475
476
477/*
478 * Channel mapping routines
479 */
480
481/*
482 * Compute derived values in channel_allocations[].
483 */
484static void init_channel_allocations(void)
485{
486 int i, j;
487 struct cea_channel_speaker_allocation *p;
488
489 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
490 p = channel_allocations + i;
491 p->channels = 0;
492 p->spk_mask = 0;
493 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
494 if (p->speakers[j]) {
495 p->channels++;
496 p->spk_mask |= p->speakers[j];
497 }
498 }
499}
500
72357c78
WX		 501static int get_channel_allocation_order(int ca)
502{
503 int i;
504
505 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
506 if (channel_allocations[i].ca_index == ca)
507 break;
508 }
509 return i;
510}
511
079d88cc
WF		 512/*
513 * The transformation takes two steps:
514 *
515 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
516 * spk_mask => (channel_allocations[]) => ai->CA
517 *
518 * TODO: it could select the wrong CA from multiple candidates.
519*/
384a48d7 520static int hdmi_channel_allocation(struct hdmi_eld *eld, int channels)
079d88cc 521{
079d88cc 522 int i;
53d7d69d 523 int ca = 0;
079d88cc 524 int spk_mask = 0;
079d88cc
WF		 525 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
526
527 /*
528 * CA defaults to 0 for basic stereo audio
529 */
530 if (channels <= 2)
531 return 0;
532
079d88cc
WF		 533 /*
534 * expand ELD's speaker allocation mask
535 *
536 * ELD tells the speaker mask in a compact(paired) form,
537 * expand ELD's notions to match the ones used by Audio InfoFrame.
538 */
539 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
1613d6b4 540 if (eld->info.spk_alloc & (1 << i))
079d88cc
WF		 541 spk_mask |= eld_speaker_allocation_bits[i];
542 }
543
544 /* search for the first working match in the CA table */
545 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
546 if (channels == channel_allocations[i].channels &&
547 (spk_mask & channel_allocations[i].spk_mask) ==
548 channel_allocations[i].spk_mask) {
53d7d69d 549 ca = channel_allocations[i].ca_index;
079d88cc
WF		 550 break;
551 }
552 }
553
1613d6b4 554 snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf));
2abbf439 555 snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n",
53d7d69d 556 ca, channels, buf);
079d88cc 557
53d7d69d 558 return ca;
079d88cc
WF		 559}
560
561static void hdmi_debug_channel_mapping(struct hda_codec *codec,
562 hda_nid_t pin_nid)
563{
564#ifdef CONFIG_SND_DEBUG_VERBOSE
565 int i;
566 int slot;
567
568 for (i = 0; i < 8; i++) {
569 slot = snd_hda_codec_read(codec, pin_nid, 0,
570 AC_VERB_GET_HDMI_CHAN_SLOT, i);
571 printk(KERN_DEBUG "HDMI: ASP channel %d => slot %d\n",
572 slot >> 4, slot & 0xf);
573 }
574#endif
575}
576
577
d45e6889 578static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
079d88cc 579 hda_nid_t pin_nid,
433968da 580 bool non_pcm,
53d7d69d 581 int ca)
079d88cc
WF		 582{
583 int i;
079d88cc 584 int err;
72357c78 585 int order;
433968da 586 int non_pcm_mapping[8];
079d88cc 587
72357c78 588 order = get_channel_allocation_order(ca);
433968da 589
079d88cc 590 if (hdmi_channel_mapping[ca][1] == 0) {
72357c78 591 for (i = 0; i < channel_allocations[order].channels; i++)
079d88cc
WF		 592 hdmi_channel_mapping[ca][i] = i | (i << 4);
593 for (; i < 8; i++)
594 hdmi_channel_mapping[ca][i] = 0xf | (i << 4);
595 }
596
433968da
WX		 597 if (non_pcm) {
598 for (i = 0; i < channel_allocations[order].channels; i++)
599 non_pcm_mapping[i] = i | (i << 4);
600 for (; i < 8; i++)
601 non_pcm_mapping[i] = 0xf | (i << 4);
602 }
603
079d88cc
WF		 604 for (i = 0; i < 8; i++) {
605 err = snd_hda_codec_write(codec, pin_nid, 0,
606 AC_VERB_SET_HDMI_CHAN_SLOT,
433968da 607 non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i]);
079d88cc 608 if (err) {
2abbf439
WF		 609 snd_printdd(KERN_NOTICE
610 "HDMI: channel mapping failed\n");
079d88cc
WF		 611 break;
612 }
613 }
614
615 hdmi_debug_channel_mapping(codec, pin_nid);
616}
617
d45e6889
TI		 618struct channel_map_table {
619 unsigned char map; /* ALSA API channel map position */
620 unsigned char cea_slot; /* CEA slot value */
621 int spk_mask; /* speaker position bit mask */
622};
623
624static struct channel_map_table map_tables[] = {
625 { SNDRV_CHMAP_FL, 0x00, FL },
626 { SNDRV_CHMAP_FR, 0x01, FR },
627 { SNDRV_CHMAP_RL, 0x04, RL },
628 { SNDRV_CHMAP_RR, 0x05, RR },
629 { SNDRV_CHMAP_LFE, 0x02, LFE },
630 { SNDRV_CHMAP_FC, 0x03, FC },
631 { SNDRV_CHMAP_RLC, 0x06, RLC },
632 { SNDRV_CHMAP_RRC, 0x07, RRC },
633 {} /* terminator */
634};
635
636/* from ALSA API channel position to speaker bit mask */
637static int to_spk_mask(unsigned char c)
638{
639 struct channel_map_table *t = map_tables;
640 for (; t->map; t++) {
641 if (t->map == c)
642 return t->spk_mask;
643 }
644 return 0;
645}
646
647/* from ALSA API channel position to CEA slot */
648static int to_cea_slot(unsigned char c)
649{
650 struct channel_map_table *t = map_tables;
651 for (; t->map; t++) {
652 if (t->map == c)
653 return t->cea_slot;
654 }
655 return 0x0f;
656}
657
658/* from CEA slot to ALSA API channel position */
659static int from_cea_slot(unsigned char c)
660{
661 struct channel_map_table *t = map_tables;
662 for (; t->map; t++) {
663 if (t->cea_slot == c)
664 return t->map;
665 }
666 return 0;
667}
668
669/* from speaker bit mask to ALSA API channel position */
670static int spk_to_chmap(int spk)
671{
672 struct channel_map_table *t = map_tables;
673 for (; t->map; t++) {
674 if (t->spk_mask == spk)
675 return t->map;
676 }
677 return 0;
678}
679
680/* get the CA index corresponding to the given ALSA API channel map */
681static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
682{
683 int i, spks = 0, spk_mask = 0;
684
685 for (i = 0; i < chs; i++) {
686 int mask = to_spk_mask(map[i]);
687 if (mask) {
688 spk_mask |= mask;
689 spks++;
690 }
691 }
692
693 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
694 if ((chs == channel_allocations[i].channels ||
695 spks == channel_allocations[i].channels) &&
696 (spk_mask & channel_allocations[i].spk_mask) ==
697 channel_allocations[i].spk_mask)
698 return channel_allocations[i].ca_index;
699 }
700 return -1;
701}
702
703/* set up the channel slots for the given ALSA API channel map */
704static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
705 hda_nid_t pin_nid,
706 int chs, unsigned char *map)
707{
708 int i;
709 for (i = 0; i < 8; i++) {
710 int val, err;
711 if (i < chs)
712 val = to_cea_slot(map[i]);
713 else
714 val = 0xf;
715 val |= (i << 4);
716 err = snd_hda_codec_write(codec, pin_nid, 0,
717 AC_VERB_SET_HDMI_CHAN_SLOT, val);
718 if (err)
719 return -EINVAL;
720 }
721 return 0;
722}
723
724/* store ALSA API channel map from the current default map */
725static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
726{
727 int i;
728 for (i = 0; i < 8; i++) {
729 if (i < channel_allocations[ca].channels)
730 map[i] = from_cea_slot((hdmi_channel_mapping[ca][i] >> 4) & 0x0f);
731 else
732 map[i] = 0;
733 }
734}
735
736static void hdmi_setup_channel_mapping(struct hda_codec *codec,
737 hda_nid_t pin_nid, bool non_pcm, int ca,
20608731
AH		 738 int channels, unsigned char *map,
739 bool chmap_set)
d45e6889 740{
20608731 741 if (!non_pcm && chmap_set) {
d45e6889
TI		 742 hdmi_manual_setup_channel_mapping(codec, pin_nid,
743 channels, map);
744 } else {
745 hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
746 hdmi_setup_fake_chmap(map, ca);
747 }
748}
079d88cc
WF		 749
750/*
751 * Audio InfoFrame routines
752 */
753
754/*
755 * Enable Audio InfoFrame Transmission
756 */
757static void hdmi_start_infoframe_trans(struct hda_codec *codec,
758 hda_nid_t pin_nid)
759{
760 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
761 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
762 AC_DIPXMIT_BEST);
763}
764
765/*
766 * Disable Audio InfoFrame Transmission
767 */
768static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
769 hda_nid_t pin_nid)
770{
771 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
772 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
773 AC_DIPXMIT_DISABLE);
774}
775
776static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
777{
778#ifdef CONFIG_SND_DEBUG_VERBOSE
779 int i;
780 int size;
781
782 size = snd_hdmi_get_eld_size(codec, pin_nid);
783 printk(KERN_DEBUG "HDMI: ELD buf size is %d\n", size);
784
785 for (i = 0; i < 8; i++) {
786 size = snd_hda_codec_read(codec, pin_nid, 0,
787 AC_VERB_GET_HDMI_DIP_SIZE, i);
788 printk(KERN_DEBUG "HDMI: DIP GP[%d] buf size is %d\n", i, size);
789 }
790#endif
791}
792
793static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
794{
795#ifdef BE_PARANOID
796 int i, j;
797 int size;
798 int pi, bi;
799 for (i = 0; i < 8; i++) {
800 size = snd_hda_codec_read(codec, pin_nid, 0,
801 AC_VERB_GET_HDMI_DIP_SIZE, i);
802 if (size == 0)
803 continue;
804
805 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
806 for (j = 1; j < 1000; j++) {
807 hdmi_write_dip_byte(codec, pin_nid, 0x0);
808 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
809 if (pi != i)
810 snd_printd(KERN_INFO "dip index %d: %d != %d\n",
811 bi, pi, i);
812 if (bi == 0) /* byte index wrapped around */
813 break;
814 }
815 snd_printd(KERN_INFO
816 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
817 i, size, j);
818 }
819#endif
820}
821
53d7d69d 822static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
079d88cc 823{
53d7d69d 824 u8 *bytes = (u8 *)hdmi_ai;
079d88cc
WF		 825 u8 sum = 0;
826 int i;
827
53d7d69d 828 hdmi_ai->checksum = 0;
079d88cc 829
53d7d69d 830 for (i = 0; i < sizeof(*hdmi_ai); i++)
079d88cc
WF		 831 sum += bytes[i];
832
53d7d69d 833 hdmi_ai->checksum = -sum;
079d88cc
WF		 834}
835
836static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
837 hda_nid_t pin_nid,
53d7d69d 838 u8 *dip, int size)
079d88cc 839{
079d88cc
WF		 840 int i;
841
842 hdmi_debug_dip_size(codec, pin_nid);
843 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
844
079d88cc 845 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d
WF		 846 for (i = 0; i < size; i++)
847 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
079d88cc
WF		 848}
849
850static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
53d7d69d 851 u8 *dip, int size)
079d88cc 852{
079d88cc
WF		 853 u8 val;
854 int i;
855
856 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
857 != AC_DIPXMIT_BEST)
858 return false;
859
860 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
53d7d69d 861 for (i = 0; i < size; i++) {
079d88cc
WF		 862 val = snd_hda_codec_read(codec, pin_nid, 0,
863 AC_VERB_GET_HDMI_DIP_DATA, 0);
53d7d69d 864 if (val != dip[i])
079d88cc
WF		 865 return false;
866 }
867
868 return true;
869}
870
384a48d7 871static void hdmi_setup_audio_infoframe(struct hda_codec *codec, int pin_idx,
1a6003b5
TI		 872 bool non_pcm,
873 struct snd_pcm_substream *substream)
079d88cc
WF		 874{
875 struct hdmi_spec *spec = codec->spec;
bce0d2a8 876 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 877 hda_nid_t pin_nid = per_pin->pin_nid;
53d7d69d 878 int channels = substream->runtime->channels;
384a48d7 879 struct hdmi_eld *eld;
53d7d69d 880 int ca;
2b203dbb 881 union audio_infoframe ai;
079d88cc 882
bce0d2a8 883 eld = &per_pin->sink_eld;
384a48d7
SW		 884 if (!eld->monitor_present)
885 return;
079d88cc 886
d45e6889
TI		 887 if (!non_pcm && per_pin->chmap_set)
888 ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
889 else
890 ca = hdmi_channel_allocation(eld, channels);
891 if (ca < 0)
892 ca = 0;
384a48d7
SW		 893
894 memset(&ai, 0, sizeof(ai));
1613d6b4 895 if (eld->info.conn_type == 0) { /* HDMI */
384a48d7
SW		 896 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
897
898 hdmi_ai->type = 0x84;
899 hdmi_ai->ver = 0x01;
900 hdmi_ai->len = 0x0a;
901 hdmi_ai->CC02_CT47 = channels - 1;
902 hdmi_ai->CA = ca;
903 hdmi_checksum_audio_infoframe(hdmi_ai);
1613d6b4 904 } else if (eld->info.conn_type == 1) { /* DisplayPort */
384a48d7
SW		 905 struct dp_audio_infoframe *dp_ai = &ai.dp;
906
907 dp_ai->type = 0x84;
908 dp_ai->len = 0x1b;
909 dp_ai->ver = 0x11 << 2;
910 dp_ai->CC02_CT47 = channels - 1;
911 dp_ai->CA = ca;
912 } else {
913 snd_printd("HDMI: unknown connection type at pin %d\n",
914 pin_nid);
915 return;
916 }
53d7d69d 917
384a48d7
SW		 918 /*
919 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
920 * sizeof(*dp_ai) to avoid partial match/update problems when
921 * the user switches between HDMI/DP monitors.
922 */
923 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
924 sizeof(ai))) {
925 snd_printdd("hdmi_setup_audio_infoframe: "
926 "pin=%d channels=%d\n",
927 pin_nid,
928 channels);
d45e6889 929 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
20608731
AH		 930 channels, per_pin->chmap,
931 per_pin->chmap_set);
384a48d7
SW		 932 hdmi_stop_infoframe_trans(codec, pin_nid);
933 hdmi_fill_audio_infoframe(codec, pin_nid,
934 ai.bytes, sizeof(ai));
935 hdmi_start_infoframe_trans(codec, pin_nid);
2d7e887c
WX		 936 } else {
937 /* For non-pcm audio switch, setup new channel mapping
938 * accordingly */
1a6003b5 939 if (per_pin->non_pcm != non_pcm)
d45e6889 940 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
20608731
AH		 941 channels, per_pin->chmap,
942 per_pin->chmap_set);
079d88cc 943 }
433968da 944
1a6003b5 945 per_pin->non_pcm = non_pcm;
079d88cc
WF		 946}
947
948
949/*
950 * Unsolicited events
951 */
952
c6e8453e 953static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
38faddb1 954
079d88cc
WF		 955static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
956{
957 struct hdmi_spec *spec = codec->spec;
3a93897e
TI		 958 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
959 int pin_nid;
384a48d7 960 int pin_idx;
3a93897e 961 struct hda_jack_tbl *jack;
2e59e5ab 962 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
3a93897e
TI		 963
964 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
965 if (!jack)
966 return;
967 pin_nid = jack->nid;
968 jack->jack_dirty = 1;
079d88cc 969
fae3d88a 970 _snd_printd(SND_PR_VERBOSE,
2e59e5ab
ML		 971 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
972 codec->addr, pin_nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
fae3d88a 973 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
079d88cc 974
384a48d7
SW		 975 pin_idx = pin_nid_to_pin_index(spec, pin_nid);
976 if (pin_idx < 0)
079d88cc
WF		 977 return;
978
bce0d2a8 979 hdmi_present_sense(get_pin(spec, pin_idx), 1);
01a61e12 980 snd_hda_jack_report_sync(codec);
079d88cc
WF		 981}
982
983static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
984{
985 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
986 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
987 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
988 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
989
990 printk(KERN_INFO
e9ea8e8f 991 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
384a48d7 992 codec->addr,
079d88cc
WF		 993 tag,
994 subtag,
995 cp_state,
996 cp_ready);
997
998 /* TODO */
999 if (cp_state)
1000 ;
1001 if (cp_ready)
1002 ;
1003}
1004
1005
1006static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
1007{
079d88cc
WF		 1008 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1009 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1010
3a93897e 1011 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
079d88cc
WF		 1012 snd_printd(KERN_INFO "Unexpected HDMI event tag 0x%x\n", tag);
1013 return;
1014 }
1015
1016 if (subtag == 0)
1017 hdmi_intrinsic_event(codec, res);
1018 else
1019 hdmi_non_intrinsic_event(codec, res);
1020}
1021
53b434f0
WX		 1022static void haswell_verify_pin_D0(struct hda_codec *codec,
1023 hda_nid_t cvt_nid, hda_nid_t nid)
83f26ad2
DH		 1024{
1025 int pwr, lamp, ramp;
1026
53b434f0
WX		 1027 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
1028 * thus pins could only choose converter 0 for use. Make sure the
1029 * converters are in correct power state */
fd678cac 1030 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
53b434f0
WX		 1031 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
1032
fd678cac 1033 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
83f26ad2
DH		 1034 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
1035 AC_PWRST_D0);
1036 msleep(40);
1037 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
1038 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
1039 snd_printd("Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
1040 }
1041
1042 lamp = snd_hda_codec_read(codec, nid, 0,
1043 AC_VERB_GET_AMP_GAIN_MUTE,
1044 AC_AMP_GET_LEFT | AC_AMP_GET_OUTPUT);
1045 ramp = snd_hda_codec_read(codec, nid, 0,
1046 AC_VERB_GET_AMP_GAIN_MUTE,
1047 AC_AMP_GET_RIGHT | AC_AMP_GET_OUTPUT);
1048 if (lamp != ramp) {
1049 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_AMP_GAIN_MUTE,
1050 AC_AMP_SET_RIGHT | AC_AMP_SET_OUTPUT | lamp);
1051
1052 lamp = snd_hda_codec_read(codec, nid, 0,
1053 AC_VERB_GET_AMP_GAIN_MUTE,
1054 AC_AMP_GET_LEFT | AC_AMP_GET_OUTPUT);
1055 ramp = snd_hda_codec_read(codec, nid, 0,
1056 AC_VERB_GET_AMP_GAIN_MUTE,
1057 AC_AMP_GET_RIGHT | AC_AMP_GET_OUTPUT);
1058 snd_printd("Haswell HDMI audio: Mute after set on pin 0x%x: [0x%x 0x%x]\n", nid, lamp, ramp);
1059 }
1060}
1061
079d88cc
WF		 1062/*
1063 * Callbacks
1064 */
1065
92f10b3f
TI		 1066/* HBR should be Non-PCM, 8 channels */
1067#define is_hbr_format(format) \
1068 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
1069
384a48d7
SW		 1070static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
1071 hda_nid_t pin_nid, u32 stream_tag, int format)
079d88cc 1072{
ea87d1c4
AH		 1073 int pinctl;
1074 int new_pinctl = 0;
ea87d1c4 1075
83f26ad2 1076 if (codec->vendor_id == 0x80862807)
53b434f0 1077 haswell_verify_pin_D0(codec, cvt_nid, pin_nid);
83f26ad2 1078
384a48d7
SW		 1079 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
1080 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
ea87d1c4
AH		 1081 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1082
1083 new_pinctl = pinctl & ~AC_PINCTL_EPT;
92f10b3f 1084 if (is_hbr_format(format))
ea87d1c4
AH		 1085 new_pinctl |= AC_PINCTL_EPT_HBR;
1086 else
1087 new_pinctl |= AC_PINCTL_EPT_NATIVE;
1088
1089 snd_printdd("hdmi_setup_stream: "
1090 "NID=0x%x, %spinctl=0x%x\n",
384a48d7 1091 pin_nid,
ea87d1c4
AH		 1092 pinctl == new_pinctl ? "" : "new-",
1093 new_pinctl);
1094
1095 if (pinctl != new_pinctl)
384a48d7 1096 snd_hda_codec_write(codec, pin_nid, 0,
ea87d1c4
AH		 1097 AC_VERB_SET_PIN_WIDGET_CONTROL,
1098 new_pinctl);
ea87d1c4 1099
384a48d7 1100 }
92f10b3f 1101 if (is_hbr_format(format) && !new_pinctl) {
ea87d1c4
AH		 1102 snd_printdd("hdmi_setup_stream: HBR is not supported\n");
1103 return -EINVAL;
1104 }
079d88cc 1105
384a48d7 1106 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
ea87d1c4 1107 return 0;
079d88cc
WF		 1108}
1109
7ef166b8
WX		 1110static int hdmi_choose_cvt(struct hda_codec *codec,
1111 int pin_idx, int *cvt_id, int *mux_id)
bbbe3390
TI		 1112{
1113 struct hdmi_spec *spec = codec->spec;
384a48d7 1114 struct hdmi_spec_per_pin *per_pin;
384a48d7 1115 struct hdmi_spec_per_cvt *per_cvt = NULL;
7ef166b8 1116 int cvt_idx, mux_idx = 0;
bbbe3390 1117
bce0d2a8 1118 per_pin = get_pin(spec, pin_idx);
384a48d7
SW		 1119
1120 /* Dynamically assign converter to stream */
1121 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
bce0d2a8 1122 per_cvt = get_cvt(spec, cvt_idx);
bbbe3390 1123
384a48d7
SW		 1124 /* Must not already be assigned */
1125 if (per_cvt->assigned)
1126 continue;
1127 /* Must be in pin's mux's list of converters */
1128 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1129 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1130 break;
1131 /* Not in mux list */
1132 if (mux_idx == per_pin->num_mux_nids)
1133 continue;
1134 break;
1135 }
7ef166b8 1136
384a48d7
SW		 1137 /* No free converters */
1138 if (cvt_idx == spec->num_cvts)
1139 return -ENODEV;
1140
7ef166b8
WX		 1141 if (cvt_id)
1142 *cvt_id = cvt_idx;
1143 if (mux_id)
1144 *mux_id = mux_idx;
1145
1146 return 0;
1147}
1148
1149static void haswell_config_cvts(struct hda_codec *codec,
1150 int pin_id, int mux_id)
1151{
1152 struct hdmi_spec *spec = codec->spec;
1153 struct hdmi_spec_per_pin *per_pin;
1154 int pin_idx, mux_idx;
1155 int curr;
1156 int err;
1157
1158 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1159 per_pin = get_pin(spec, pin_idx);
1160
1161 if (pin_idx == pin_id)
1162 continue;
1163
1164 curr = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1165 AC_VERB_GET_CONNECT_SEL, 0);
1166
1167 /* Choose another unused converter */
1168 if (curr == mux_id) {
1169 err = hdmi_choose_cvt(codec, pin_idx, NULL, &mux_idx);
1170 if (err < 0)
1171 return;
1172 snd_printdd("HDMI: choose converter %d for pin %d\n", mux_idx, pin_idx);
1173 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1174 AC_VERB_SET_CONNECT_SEL,
1175 mux_idx);
1176 }
1177 }
1178}
1179
1180/*
1181 * HDA PCM callbacks
1182 */
1183static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1184 struct hda_codec *codec,
1185 struct snd_pcm_substream *substream)
1186{
1187 struct hdmi_spec *spec = codec->spec;
1188 struct snd_pcm_runtime *runtime = substream->runtime;
1189 int pin_idx, cvt_idx, mux_idx = 0;
1190 struct hdmi_spec_per_pin *per_pin;
1191 struct hdmi_eld *eld;
1192 struct hdmi_spec_per_cvt *per_cvt = NULL;
1193 int err;
1194
1195 /* Validate hinfo */
1196 pin_idx = hinfo_to_pin_index(spec, hinfo);
1197 if (snd_BUG_ON(pin_idx < 0))
1198 return -EINVAL;
1199 per_pin = get_pin(spec, pin_idx);
1200 eld = &per_pin->sink_eld;
1201
1202 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx);
1203 if (err < 0)
1204 return err;
1205
1206 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1207 /* Claim converter */
1208 per_cvt->assigned = 1;
1209 hinfo->nid = per_cvt->cvt_nid;
1210
bddee96b 1211 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
384a48d7
SW		 1212 AC_VERB_SET_CONNECT_SEL,
1213 mux_idx);
7ef166b8
WX		 1214
1215 /* configure unused pins to choose other converters */
1216 if (codec->vendor_id == 0x80862807)
1217 haswell_config_cvts(codec, pin_idx, mux_idx);
1218
384a48d7 1219 snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
bbbe3390 1220
2def8172 1221 /* Initially set the converter's capabilities */
384a48d7
SW		 1222 hinfo->channels_min = per_cvt->channels_min;
1223 hinfo->channels_max = per_cvt->channels_max;
1224 hinfo->rates = per_cvt->rates;
1225 hinfo->formats = per_cvt->formats;
1226 hinfo->maxbps = per_cvt->maxbps;
2def8172 1227
384a48d7 1228 /* Restrict capabilities by ELD if this isn't disabled */
c3d52105 1229 if (!static_hdmi_pcm && eld->eld_valid) {
1613d6b4 1230 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
bbbe3390 1231 if (hinfo->channels_min > hinfo->channels_max ||
2ad779b7
TI		 1232 !hinfo->rates || !hinfo->formats) {
1233 per_cvt->assigned = 0;
1234 hinfo->nid = 0;
1235 snd_hda_spdif_ctls_unassign(codec, pin_idx);
bbbe3390 1236 return -ENODEV;
2ad779b7 1237 }
bbbe3390 1238 }
2def8172
SW		 1239
1240 /* Store the updated parameters */
639cef0e
TI		 1241 runtime->hw.channels_min = hinfo->channels_min;
1242 runtime->hw.channels_max = hinfo->channels_max;
1243 runtime->hw.formats = hinfo->formats;
1244 runtime->hw.rates = hinfo->rates;
4fe2ca14
TI		 1245
1246 snd_pcm_hw_constraint_step(substream->runtime, 0,
1247 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
bbbe3390
TI		 1248 return 0;
1249}
1250
079d88cc
WF		 1251/*
1252 * HDA/HDMI auto parsing
1253 */
384a48d7 1254static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
079d88cc
WF		 1255{
1256 struct hdmi_spec *spec = codec->spec;
bce0d2a8 1257 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1258 hda_nid_t pin_nid = per_pin->pin_nid;
079d88cc
WF		 1259
1260 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1261 snd_printk(KERN_WARNING
1262 "HDMI: pin %d wcaps %#x "
1263 "does not support connection list\n",
1264 pin_nid, get_wcaps(codec, pin_nid));
1265 return -EINVAL;
1266 }
1267
384a48d7
SW		 1268 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1269 per_pin->mux_nids,
1270 HDA_MAX_CONNECTIONS);
079d88cc
WF		 1271
1272 return 0;
1273}
1274
c6e8453e 1275static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
079d88cc 1276{
744626da 1277 struct hda_codec *codec = per_pin->codec;
4bd038f9
DH		 1278 struct hdmi_spec *spec = codec->spec;
1279 struct hdmi_eld *eld = &spec->temp_eld;
1280 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
744626da 1281 hda_nid_t pin_nid = per_pin->pin_nid;
5d44f927
SW		 1282 /*
1283 * Always execute a GetPinSense verb here, even when called from
1284 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1285 * response's PD bit is not the real PD value, but indicates that
1286 * the real PD value changed. An older version of the HD-audio
1287 * specification worked this way. Hence, we just ignore the data in
1288 * the unsolicited response to avoid custom WARs.
1289 */
079d88cc 1290 int present = snd_hda_pin_sense(codec, pin_nid);
4bd038f9
DH		 1291 bool update_eld = false;
1292 bool eld_changed = false;
079d88cc 1293
4bd038f9
DH		 1294 pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1295 if (pin_eld->monitor_present)
1296 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1297 else
1298 eld->eld_valid = false;
079d88cc 1299
fae3d88a 1300 _snd_printd(SND_PR_VERBOSE,
384a48d7 1301 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
10250911 1302 codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
5d44f927 1303
4bd038f9 1304 if (eld->eld_valid) {
1613d6b4
DH		 1305 if (snd_hdmi_get_eld(codec, pin_nid, eld->eld_buffer,
1306 &eld->eld_size) < 0)
4bd038f9 1307 eld->eld_valid = false;
1613d6b4
DH		 1308 else {
1309 memset(&eld->info, 0, sizeof(struct parsed_hdmi_eld));
1310 if (snd_hdmi_parse_eld(&eld->info, eld->eld_buffer,
1311 eld->eld_size) < 0)
4bd038f9 1312 eld->eld_valid = false;
1613d6b4
DH		 1313 }
1314
4bd038f9 1315 if (eld->eld_valid) {
1613d6b4 1316 snd_hdmi_show_eld(&eld->info);
4bd038f9 1317 update_eld = true;
1613d6b4 1318 }
c6e8453e 1319 else if (repoll) {
744626da
WF		 1320 queue_delayed_work(codec->bus->workq,
1321 &per_pin->work,
1322 msecs_to_jiffies(300));
4bd038f9 1323 return;
744626da
WF		 1324 }
1325 }
4bd038f9
DH		 1326
1327 mutex_lock(&pin_eld->lock);
92c69e79 1328 if (pin_eld->eld_valid && !eld->eld_valid) {
4bd038f9 1329 update_eld = true;
92c69e79
DH		 1330 eld_changed = true;
1331 }
4bd038f9
DH		 1332 if (update_eld) {
1333 pin_eld->eld_valid = eld->eld_valid;
92c69e79
DH		 1334 eld_changed = pin_eld->eld_size != eld->eld_size ||
1335 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
4bd038f9
DH		 1336 eld->eld_size) != 0;
1337 if (eld_changed)
1338 memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1339 eld->eld_size);
1340 pin_eld->eld_size = eld->eld_size;
1341 pin_eld->info = eld->info;
1342 }
1343 mutex_unlock(&pin_eld->lock);
92c69e79
DH		 1344
1345 if (eld_changed)
1346 snd_ctl_notify(codec->bus->card,
1347 SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO,
1348 &per_pin->eld_ctl->id);
079d88cc
WF		 1349}
1350
744626da
WF		 1351static void hdmi_repoll_eld(struct work_struct *work)
1352{
1353 struct hdmi_spec_per_pin *per_pin =
1354 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1355
c6e8453e
WF		 1356 if (per_pin->repoll_count++ > 6)
1357 per_pin->repoll_count = 0;
1358
1359 hdmi_present_sense(per_pin, per_pin->repoll_count);
744626da
WF		 1360}
1361
c88d4e84
TI		 1362static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1363 hda_nid_t nid);
1364
079d88cc
WF		 1365static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1366{
1367 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1368 unsigned int caps, config;
1369 int pin_idx;
1370 struct hdmi_spec_per_pin *per_pin;
07acecc1 1371 int err;
079d88cc 1372
efc2f8de 1373 caps = snd_hda_query_pin_caps(codec, pin_nid);
384a48d7
SW		 1374 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1375 return 0;
1376
efc2f8de 1377 config = snd_hda_codec_get_pincfg(codec, pin_nid);
384a48d7
SW		 1378 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1379 return 0;
1380
c88d4e84
TI		 1381 if (codec->vendor_id == 0x80862807)
1382 intel_haswell_fixup_connect_list(codec, pin_nid);
1383
384a48d7 1384 pin_idx = spec->num_pins;
bce0d2a8
TI		 1385 per_pin = snd_array_new(&spec->pins);
1386 if (!per_pin)
1387 return -ENOMEM;
384a48d7
SW		 1388
1389 per_pin->pin_nid = pin_nid;
1a6003b5 1390 per_pin->non_pcm = false;
079d88cc 1391
384a48d7
SW		 1392 err = hdmi_read_pin_conn(codec, pin_idx);
1393 if (err < 0)
1394 return err;
079d88cc 1395
079d88cc
WF		 1396 spec->num_pins++;
1397
384a48d7 1398 return 0;
079d88cc
WF		 1399}
1400
384a48d7 1401static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
079d88cc
WF		 1402{
1403 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1404 struct hdmi_spec_per_cvt *per_cvt;
1405 unsigned int chans;
1406 int err;
079d88cc 1407
384a48d7
SW		 1408 chans = get_wcaps(codec, cvt_nid);
1409 chans = get_wcaps_channels(chans);
1410
bce0d2a8
TI		 1411 per_cvt = snd_array_new(&spec->cvts);
1412 if (!per_cvt)
1413 return -ENOMEM;
384a48d7
SW		 1414
1415 per_cvt->cvt_nid = cvt_nid;
1416 per_cvt->channels_min = 2;
d45e6889 1417 if (chans <= 16) {
384a48d7 1418 per_cvt->channels_max = chans;
d45e6889
TI		 1419 if (chans > spec->channels_max)
1420 spec->channels_max = chans;
1421 }
384a48d7
SW		 1422
1423 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1424 &per_cvt->rates,
1425 &per_cvt->formats,
1426 &per_cvt->maxbps);
1427 if (err < 0)
1428 return err;
1429
bce0d2a8
TI		 1430 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1431 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1432 spec->num_cvts++;
079d88cc
WF		 1433
1434 return 0;
1435}
1436
1437static int hdmi_parse_codec(struct hda_codec *codec)
1438{
1439 hda_nid_t nid;
1440 int i, nodes;
1441
1442 nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid);
1443 if (!nid || nodes < 0) {
1444 snd_printk(KERN_WARNING "HDMI: failed to get afg sub nodes\n");
1445 return -EINVAL;
1446 }
1447
1448 for (i = 0; i < nodes; i++, nid++) {
1449 unsigned int caps;
1450 unsigned int type;
1451
efc2f8de 1452 caps = get_wcaps(codec, nid);
079d88cc
WF		 1453 type = get_wcaps_type(caps);
1454
1455 if (!(caps & AC_WCAP_DIGITAL))
1456 continue;
1457
1458 switch (type) {
1459 case AC_WID_AUD_OUT:
384a48d7 1460 hdmi_add_cvt(codec, nid);
079d88cc
WF		 1461 break;
1462 case AC_WID_PIN:
3eaead57 1463 hdmi_add_pin(codec, nid);
079d88cc
WF		 1464 break;
1465 }
1466 }
1467
c9adeefd
DH		 1468#ifdef CONFIG_PM
1469 /* We're seeing some problems with unsolicited hot plug events on
1470 * PantherPoint after S3, if this is not enabled */
1471 if (codec->vendor_id == 0x80862806)
1472 codec->bus->power_keep_link_on = 1;
079d88cc
WF		 1473 /*
1474 * G45/IbexPeak don't support EPSS: the unsolicited pin hot plug event
1475 * can be lost and presence sense verb will become inaccurate if the
1476 * HDA link is powered off at hot plug or hw initialization time.
1477 */
c9adeefd 1478 else if (!(snd_hda_param_read(codec, codec->afg, AC_PAR_POWER_STATE) &
079d88cc
WF		 1479 AC_PWRST_EPSS))
1480 codec->bus->power_keep_link_on = 1;
1481#endif
1482
1483 return 0;
1484}
1485
84eb01be
TI		 1486/*
1487 */
1a6003b5
TI		 1488static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1489{
1490 struct hda_spdif_out *spdif;
1491 bool non_pcm;
1492
1493 mutex_lock(&codec->spdif_mutex);
1494 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1495 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1496 mutex_unlock(&codec->spdif_mutex);
1497 return non_pcm;
1498}
1499
1500
84eb01be
TI		 1501/*
1502 * HDMI callbacks
1503 */
1504
1505static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1506 struct hda_codec *codec,
1507 unsigned int stream_tag,
1508 unsigned int format,
1509 struct snd_pcm_substream *substream)
1510{
384a48d7
SW		 1511 hda_nid_t cvt_nid = hinfo->nid;
1512 struct hdmi_spec *spec = codec->spec;
1513 int pin_idx = hinfo_to_pin_index(spec, hinfo);
bce0d2a8 1514 hda_nid_t pin_nid = get_pin(spec, pin_idx)->pin_nid;
1a6003b5
TI		 1515 bool non_pcm;
1516
1517 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
384a48d7
SW		 1518
1519 hdmi_set_channel_count(codec, cvt_nid, substream->runtime->channels);
84eb01be 1520
1a6003b5 1521 hdmi_setup_audio_infoframe(codec, pin_idx, non_pcm, substream);
84eb01be 1522
384a48d7 1523 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
84eb01be
TI		 1524}
1525
8dfaa573
TI		 1526static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1527 struct hda_codec *codec,
1528 struct snd_pcm_substream *substream)
1529{
1530 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1531 return 0;
1532}
1533
f2ad24fa
TI		 1534static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1535 struct hda_codec *codec,
1536 struct snd_pcm_substream *substream)
384a48d7
SW		 1537{
1538 struct hdmi_spec *spec = codec->spec;
1539 int cvt_idx, pin_idx;
1540 struct hdmi_spec_per_cvt *per_cvt;
1541 struct hdmi_spec_per_pin *per_pin;
384a48d7 1542
384a48d7
SW		 1543 if (hinfo->nid) {
1544 cvt_idx = cvt_nid_to_cvt_index(spec, hinfo->nid);
1545 if (snd_BUG_ON(cvt_idx < 0))
1546 return -EINVAL;
bce0d2a8 1547 per_cvt = get_cvt(spec, cvt_idx);
384a48d7
SW		 1548
1549 snd_BUG_ON(!per_cvt->assigned);
1550 per_cvt->assigned = 0;
1551 hinfo->nid = 0;
1552
1553 pin_idx = hinfo_to_pin_index(spec, hinfo);
1554 if (snd_BUG_ON(pin_idx < 0))
1555 return -EINVAL;
bce0d2a8 1556 per_pin = get_pin(spec, pin_idx);
384a48d7 1557
384a48d7 1558 snd_hda_spdif_ctls_unassign(codec, pin_idx);
d45e6889
TI		 1559 per_pin->chmap_set = false;
1560 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
384a48d7 1561 }
d45e6889 1562
384a48d7
SW		 1563 return 0;
1564}
1565
1566static const struct hda_pcm_ops generic_ops = {
1567 .open = hdmi_pcm_open,
f2ad24fa 1568 .close = hdmi_pcm_close,
384a48d7 1569 .prepare = generic_hdmi_playback_pcm_prepare,
8dfaa573 1570 .cleanup = generic_hdmi_playback_pcm_cleanup,
84eb01be
TI		 1571};
1572
d45e6889
TI		 1573/*
1574 * ALSA API channel-map control callbacks
1575 */
1576static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
1577 struct snd_ctl_elem_info *uinfo)
1578{
1579 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1580 struct hda_codec *codec = info->private_data;
1581 struct hdmi_spec *spec = codec->spec;
1582 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1583 uinfo->count = spec->channels_max;
1584 uinfo->value.integer.min = 0;
1585 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
1586 return 0;
1587}
1588
1589static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
1590 unsigned int size, unsigned int __user *tlv)
1591{
1592 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1593 struct hda_codec *codec = info->private_data;
1594 struct hdmi_spec *spec = codec->spec;
1595 const unsigned int valid_mask =
1596 FL | FR | RL | RR | LFE | FC | RLC | RRC;
1597 unsigned int __user *dst;
1598 int chs, count = 0;
1599
1600 if (size < 8)
1601 return -ENOMEM;
1602 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
1603 return -EFAULT;
1604 size -= 8;
1605 dst = tlv + 2;
498dab3a 1606 for (chs = 2; chs <= spec->channels_max; chs++) {
d45e6889
TI		 1607 int i, c;
1608 struct cea_channel_speaker_allocation *cap;
1609 cap = channel_allocations;
1610 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
1611 int chs_bytes = chs * 4;
1612 if (cap->channels != chs)
1613 continue;
1614 if (cap->spk_mask & ~valid_mask)
1615 continue;
1616 if (size < 8)
1617 return -ENOMEM;
1618 if (put_user(SNDRV_CTL_TLVT_CHMAP_VAR, dst) ||
1619 put_user(chs_bytes, dst + 1))
1620 return -EFAULT;
1621 dst += 2;
1622 size -= 8;
1623 count += 8;
1624 if (size < chs_bytes)
1625 return -ENOMEM;
1626 size -= chs_bytes;
1627 count += chs_bytes;
1628 for (c = 7; c >= 0; c--) {
1629 int spk = cap->speakers[c];
1630 if (!spk)
1631 continue;
1632 if (put_user(spk_to_chmap(spk), dst))
1633 return -EFAULT;
1634 dst++;
1635 }
1636 }
1637 }
1638 if (put_user(count, tlv + 1))
1639 return -EFAULT;
1640 return 0;
1641}
1642
1643static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
1644 struct snd_ctl_elem_value *ucontrol)
1645{
1646 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1647 struct hda_codec *codec = info->private_data;
1648 struct hdmi_spec *spec = codec->spec;
1649 int pin_idx = kcontrol->private_value;
bce0d2a8 1650 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
d45e6889
TI		 1651 int i;
1652
1653 for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
1654 ucontrol->value.integer.value[i] = per_pin->chmap[i];
1655 return 0;
1656}
1657
1658static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
1659 struct snd_ctl_elem_value *ucontrol)
1660{
1661 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1662 struct hda_codec *codec = info->private_data;
1663 struct hdmi_spec *spec = codec->spec;
1664 int pin_idx = kcontrol->private_value;
bce0d2a8 1665 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
d45e6889
TI		 1666 unsigned int ctl_idx;
1667 struct snd_pcm_substream *substream;
1668 unsigned char chmap[8];
1669 int i, ca, prepared = 0;
1670
1671 ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
1672 substream = snd_pcm_chmap_substream(info, ctl_idx);
1673 if (!substream || !substream->runtime)
6f54c361 1674 return 0; /* just for avoiding error from alsactl restore */
d45e6889
TI		 1675 switch (substream->runtime->status->state) {
1676 case SNDRV_PCM_STATE_OPEN:
1677 case SNDRV_PCM_STATE_SETUP:
1678 break;
1679 case SNDRV_PCM_STATE_PREPARED:
1680 prepared = 1;
1681 break;
1682 default:
1683 return -EBUSY;
1684 }
1685 memset(chmap, 0, sizeof(chmap));
1686 for (i = 0; i < ARRAY_SIZE(chmap); i++)
1687 chmap[i] = ucontrol->value.integer.value[i];
1688 if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
1689 return 0;
1690 ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
1691 if (ca < 0)
1692 return -EINVAL;
1693 per_pin->chmap_set = true;
1694 memcpy(per_pin->chmap, chmap, sizeof(chmap));
1695 if (prepared)
1696 hdmi_setup_audio_infoframe(codec, pin_idx, per_pin->non_pcm,
1697 substream);
1698
1699 return 0;
1700}
1701
84eb01be
TI		 1702static int generic_hdmi_build_pcms(struct hda_codec *codec)
1703{
1704 struct hdmi_spec *spec = codec->spec;
384a48d7 1705 int pin_idx;
84eb01be 1706
384a48d7
SW		 1707 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1708 struct hda_pcm *info;
84eb01be 1709 struct hda_pcm_stream *pstr;
bce0d2a8
TI		 1710 struct hdmi_spec_per_pin *per_pin;
1711
1712 per_pin = get_pin(spec, pin_idx);
1713 sprintf(per_pin->pcm_name, "HDMI %d", pin_idx);
1714 info = snd_array_new(&spec->pcm_rec);
1715 if (!info)
1716 return -ENOMEM;
1717 info->name = per_pin->pcm_name;
84eb01be 1718 info->pcm_type = HDA_PCM_TYPE_HDMI;
d45e6889 1719 info->own_chmap = true;
384a48d7 1720
84eb01be 1721 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
384a48d7
SW		 1722 pstr->substreams = 1;
1723 pstr->ops = generic_ops;
1724 /* other pstr fields are set in open */
84eb01be
TI		 1725 }
1726
384a48d7 1727 codec->num_pcms = spec->num_pins;
bce0d2a8 1728 codec->pcm_info = spec->pcm_rec.list;
384a48d7 1729
84eb01be
TI		 1730 return 0;
1731}
1732
0b6c49b5
DH		 1733static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
1734{
31ef2257 1735 char hdmi_str[32] = "HDMI/DP";
0b6c49b5 1736 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 1737 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1738 int pcmdev = get_pcm_rec(spec, pin_idx)->device;
0b6c49b5 1739
31ef2257
TI		 1740 if (pcmdev > 0)
1741 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
30efd8de
DH		 1742 if (!is_jack_detectable(codec, per_pin->pin_nid))
1743 strncat(hdmi_str, " Phantom",
1744 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
0b6c49b5 1745
31ef2257 1746 return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, 0);
0b6c49b5
DH		 1747}
1748
84eb01be
TI		 1749static int generic_hdmi_build_controls(struct hda_codec *codec)
1750{
1751 struct hdmi_spec *spec = codec->spec;
1752 int err;
384a48d7 1753 int pin_idx;
84eb01be 1754
384a48d7 1755 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 1756 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
0b6c49b5
DH		 1757
1758 err = generic_hdmi_build_jack(codec, pin_idx);
1759 if (err < 0)
1760 return err;
1761
dcda5806
TI		 1762 err = snd_hda_create_dig_out_ctls(codec,
1763 per_pin->pin_nid,
1764 per_pin->mux_nids[0],
1765 HDA_PCM_TYPE_HDMI);
84eb01be
TI		 1766 if (err < 0)
1767 return err;
384a48d7 1768 snd_hda_spdif_ctls_unassign(codec, pin_idx);
14bc52b8
PLB		 1769
1770 /* add control for ELD Bytes */
bce0d2a8
TI		 1771 err = hdmi_create_eld_ctl(codec, pin_idx,
1772 get_pcm_rec(spec, pin_idx)->device);
14bc52b8
PLB		 1773
1774 if (err < 0)
1775 return err;
31ef2257 1776
82b1d73f 1777 hdmi_present_sense(per_pin, 0);
84eb01be
TI		 1778 }
1779
d45e6889
TI		 1780 /* add channel maps */
1781 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1782 struct snd_pcm_chmap *chmap;
1783 struct snd_kcontrol *kctl;
1784 int i;
1785 err = snd_pcm_add_chmap_ctls(codec->pcm_info[pin_idx].pcm,
1786 SNDRV_PCM_STREAM_PLAYBACK,
1787 NULL, 0, pin_idx, &chmap);
1788 if (err < 0)
1789 return err;
1790 /* override handlers */
1791 chmap->private_data = codec;
1792 kctl = chmap->kctl;
1793 for (i = 0; i < kctl->count; i++)
1794 kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
1795 kctl->info = hdmi_chmap_ctl_info;
1796 kctl->get = hdmi_chmap_ctl_get;
1797 kctl->put = hdmi_chmap_ctl_put;
1798 kctl->tlv.c = hdmi_chmap_ctl_tlv;
1799 }
1800
84eb01be
TI		 1801 return 0;
1802}
1803
8b8d654b 1804static int generic_hdmi_init_per_pins(struct hda_codec *codec)
84eb01be
TI		 1805{
1806 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1807 int pin_idx;
1808
1809 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 1810 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1811 struct hdmi_eld *eld = &per_pin->sink_eld;
84eb01be 1812
744626da 1813 per_pin->codec = codec;
4bd038f9 1814 mutex_init(&eld->lock);
744626da 1815 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
384a48d7 1816 snd_hda_eld_proc_new(codec, eld, pin_idx);
84eb01be 1817 }
8b8d654b
TI		 1818 return 0;
1819}
1820
1821static int generic_hdmi_init(struct hda_codec *codec)
1822{
1823 struct hdmi_spec *spec = codec->spec;
1824 int pin_idx;
1825
1826 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 1827 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
8b8d654b
TI		 1828 hda_nid_t pin_nid = per_pin->pin_nid;
1829
1830 hdmi_init_pin(codec, pin_nid);
1831 snd_hda_jack_detect_enable(codec, pin_nid, pin_nid);
1832 }
84eb01be
TI		 1833 return 0;
1834}
1835
bce0d2a8
TI		 1836static void hdmi_array_init(struct hdmi_spec *spec, int nums)
1837{
1838 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
1839 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
1840 snd_array_init(&spec->pcm_rec, sizeof(struct hda_pcm), nums);
1841}
1842
1843static void hdmi_array_free(struct hdmi_spec *spec)
1844{
1845 snd_array_free(&spec->pins);
1846 snd_array_free(&spec->cvts);
1847 snd_array_free(&spec->pcm_rec);
1848}
1849
84eb01be
TI		 1850static void generic_hdmi_free(struct hda_codec *codec)
1851{
1852 struct hdmi_spec *spec = codec->spec;
384a48d7
SW		 1853 int pin_idx;
1854
1855 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
bce0d2a8 1856 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
384a48d7 1857 struct hdmi_eld *eld = &per_pin->sink_eld;
84eb01be 1858
744626da 1859 cancel_delayed_work(&per_pin->work);
384a48d7
SW		 1860 snd_hda_eld_proc_free(codec, eld);
1861 }
84eb01be 1862
744626da 1863 flush_workqueue(codec->bus->workq);
bce0d2a8 1864 hdmi_array_free(spec);
84eb01be
TI		 1865 kfree(spec);
1866}
1867
28cb72e5
WX		 1868#ifdef CONFIG_PM
1869static int generic_hdmi_resume(struct hda_codec *codec)
1870{
1871 struct hdmi_spec *spec = codec->spec;
1872 int pin_idx;
1873
1874 generic_hdmi_init(codec);
1875 snd_hda_codec_resume_amp(codec);
1876 snd_hda_codec_resume_cache(codec);
1877
1878 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1879 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1880 hdmi_present_sense(per_pin, 1);
1881 }
1882 return 0;
1883}
1884#endif
1885
fb79e1e0 1886static const struct hda_codec_ops generic_hdmi_patch_ops = {
84eb01be
TI		 1887 .init = generic_hdmi_init,
1888 .free = generic_hdmi_free,
1889 .build_pcms = generic_hdmi_build_pcms,
1890 .build_controls = generic_hdmi_build_controls,
1891 .unsol_event = hdmi_unsol_event,
28cb72e5
WX		 1892#ifdef CONFIG_PM
1893 .resume = generic_hdmi_resume,
1894#endif
84eb01be
TI		 1895};
1896
6ffe168f 1897
c88d4e84
TI		 1898static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1899 hda_nid_t nid)
1900{
1901 struct hdmi_spec *spec = codec->spec;
1902 hda_nid_t conns[4];
1903 int nconns;
6ffe168f 1904
c88d4e84
TI		 1905 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
1906 if (nconns == spec->num_cvts &&
1907 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
6ffe168f
ML		 1908 return;
1909
c88d4e84
TI		 1910 /* override pins connection list */
1911 snd_printdd("hdmi: haswell: override pin connection 0x%x\n", nid);
1912 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
6ffe168f
ML		 1913}
1914
1611a9c9
ML		 1915#define INTEL_VENDOR_NID 0x08
1916#define INTEL_GET_VENDOR_VERB 0xf81
1917#define INTEL_SET_VENDOR_VERB 0x781
1918#define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
1919#define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
1920
1921static void intel_haswell_enable_all_pins(struct hda_codec *codec,
17df3f55 1922 bool update_tree)
1611a9c9
ML		 1923{
1924 unsigned int vendor_param;
1925
1611a9c9
ML		 1926 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
1927 INTEL_GET_VENDOR_VERB, 0);
1928 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
1929 return;
1930
1931 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
1932 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
1933 INTEL_SET_VENDOR_VERB, vendor_param);
1934 if (vendor_param == -1)
1935 return;
1936
17df3f55
TI		 1937 if (update_tree)
1938 snd_hda_codec_update_widgets(codec);
1611a9c9
ML		 1939}
1940
c88d4e84
TI		 1941static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
1942{
1943 unsigned int vendor_param;
1944
1945 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
1946 INTEL_GET_VENDOR_VERB, 0);
1947 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
1948 return;
1949
1950 /* enable DP1.2 mode */
1951 vendor_param |= INTEL_EN_DP12;
1952 snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
1953 INTEL_SET_VENDOR_VERB, vendor_param);
1954}
1955
17df3f55
TI		 1956/* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
1957 * Otherwise you may get severe h/w communication errors.
1958 */
1959static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
1960 unsigned int power_state)
1961{
1962 if (power_state == AC_PWRST_D0) {
1963 intel_haswell_enable_all_pins(codec, false);
1964 intel_haswell_fixup_enable_dp12(codec);
1965 }
c88d4e84 1966
17df3f55
TI		 1967 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
1968 snd_hda_codec_set_power_to_all(codec, fg, power_state);
1969}
6ffe168f 1970
84eb01be
TI		 1971static int patch_generic_hdmi(struct hda_codec *codec)
1972{
1973 struct hdmi_spec *spec;
84eb01be
TI		 1974
1975 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1976 if (spec == NULL)
1977 return -ENOMEM;
1978
1979 codec->spec = spec;
bce0d2a8 1980 hdmi_array_init(spec, 4);
6ffe168f 1981
17df3f55
TI		 1982 if (codec->vendor_id == 0x80862807) {
1983 intel_haswell_enable_all_pins(codec, true);
c88d4e84 1984 intel_haswell_fixup_enable_dp12(codec);
17df3f55 1985 }
6ffe168f 1986
84eb01be
TI		 1987 if (hdmi_parse_codec(codec) < 0) {
1988 codec->spec = NULL;
1989 kfree(spec);
1990 return -EINVAL;
1991 }
1992 codec->patch_ops = generic_hdmi_patch_ops;
5dc989bd 1993 if (codec->vendor_id == 0x80862807) {
17df3f55 1994 codec->patch_ops.set_power_state = haswell_set_power_state;
5dc989bd
ML		 1995 codec->dp_mst = true;
1996 }
17df3f55 1997
8b8d654b 1998 generic_hdmi_init_per_pins(codec);
84eb01be 1999
84eb01be
TI		 2000 init_channel_allocations();
2001
2002 return 0;
2003}
2004
3aaf8980
SW		 2005/*
2006 * Shared non-generic implementations
2007 */
2008
2009static int simple_playback_build_pcms(struct hda_codec *codec)
2010{
2011 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2012 struct hda_pcm *info;
8ceb332d
TI		 2013 unsigned int chans;
2014 struct hda_pcm_stream *pstr;
bce0d2a8 2015 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2016
bce0d2a8
TI		 2017 per_cvt = get_cvt(spec, 0);
2018 chans = get_wcaps(codec, per_cvt->cvt_nid);
8ceb332d 2019 chans = get_wcaps_channels(chans);
3aaf8980 2020
bce0d2a8
TI		 2021 info = snd_array_new(&spec->pcm_rec);
2022 if (!info)
2023 return -ENOMEM;
2024 info->name = get_pin(spec, 0)->pcm_name;
2025 sprintf(info->name, "HDMI 0");
8ceb332d
TI		 2026 info->pcm_type = HDA_PCM_TYPE_HDMI;
2027 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2028 *pstr = spec->pcm_playback;
bce0d2a8 2029 pstr->nid = per_cvt->cvt_nid;
8ceb332d
TI		 2030 if (pstr->channels_max <= 2 && chans && chans <= 16)
2031 pstr->channels_max = chans;
3aaf8980 2032
bce0d2a8
TI		 2033 codec->num_pcms = 1;
2034 codec->pcm_info = info;
2035
3aaf8980
SW		 2036 return 0;
2037}
2038
4b6ace9e
TI		 2039/* unsolicited event for jack sensing */
2040static void simple_hdmi_unsol_event(struct hda_codec *codec,
2041 unsigned int res)
2042{
9dd8cf12 2043 snd_hda_jack_set_dirty_all(codec);
4b6ace9e
TI		 2044 snd_hda_jack_report_sync(codec);
2045}
2046
2047/* generic_hdmi_build_jack can be used for simple_hdmi, too,
2048 * as long as spec->pins[] is set correctly
2049 */
2050#define simple_hdmi_build_jack generic_hdmi_build_jack
2051
3aaf8980
SW		 2052static int simple_playback_build_controls(struct hda_codec *codec)
2053{
2054 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2055 struct hdmi_spec_per_cvt *per_cvt;
3aaf8980 2056 int err;
3aaf8980 2057
bce0d2a8
TI		 2058 per_cvt = get_cvt(spec, 0);
2059 err = snd_hda_create_spdif_out_ctls(codec, per_cvt->cvt_nid,
2060 per_cvt->cvt_nid);
8ceb332d
TI		 2061 if (err < 0)
2062 return err;
2063 return simple_hdmi_build_jack(codec, 0);
3aaf8980
SW		 2064}
2065
4f0110ce
TI		 2066static int simple_playback_init(struct hda_codec *codec)
2067{
2068 struct hdmi_spec *spec = codec->spec;
bce0d2a8
TI		 2069 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2070 hda_nid_t pin = per_pin->pin_nid;
8ceb332d
TI		 2071
2072 snd_hda_codec_write(codec, pin, 0,
2073 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2074 /* some codecs require to unmute the pin */
2075 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2076 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2077 AMP_OUT_UNMUTE);
2078 snd_hda_jack_detect_enable(codec, pin, pin);
4f0110ce
TI		 2079 return 0;
2080}
2081
3aaf8980
SW		 2082static void simple_playback_free(struct hda_codec *codec)
2083{
2084 struct hdmi_spec *spec = codec->spec;
2085
bce0d2a8 2086 hdmi_array_free(spec);
3aaf8980
SW		 2087 kfree(spec);
2088}
2089
84eb01be
TI		 2090/*
2091 * Nvidia specific implementations
2092 */
2093
2094#define Nv_VERB_SET_Channel_Allocation 0xF79
2095#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2096#define Nv_VERB_SET_Audio_Protection_On 0xF98
2097#define Nv_VERB_SET_Audio_Protection_Off 0xF99
2098
2099#define nvhdmi_master_con_nid_7x 0x04
2100#define nvhdmi_master_pin_nid_7x 0x05
2101
fb79e1e0 2102static const hda_nid_t nvhdmi_con_nids_7x[4] = {
84eb01be
TI		 2103 /*front, rear, clfe, rear_surr */
2104 0x6, 0x8, 0xa, 0xc,
2105};
2106
ceaa86ba
TI		 2107static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2108 /* set audio protect on */
2109 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2110 /* enable digital output on pin widget */
2111 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2112 {} /* terminator */
2113};
2114
2115static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
84eb01be
TI		 2116 /* set audio protect on */
2117 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2118 /* enable digital output on pin widget */
2119 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2120 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2121 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2122 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2123 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2124 {} /* terminator */
2125};
2126
2127#ifdef LIMITED_RATE_FMT_SUPPORT
2128/* support only the safe format and rate */
2129#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2130#define SUPPORTED_MAXBPS 16
2131#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2132#else
2133/* support all rates and formats */
2134#define SUPPORTED_RATES \
2135 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2136 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2137 SNDRV_PCM_RATE_192000)
2138#define SUPPORTED_MAXBPS 24
2139#define SUPPORTED_FORMATS \
2140 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2141#endif
2142
ceaa86ba
TI		 2143static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2144{
2145 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2146 return 0;
2147}
2148
2149static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
84eb01be 2150{
ceaa86ba 2151 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
84eb01be
TI		 2152 return 0;
2153}
2154
393004b2
ND		 2155static unsigned int channels_2_6_8[] = {
2156 2, 6, 8
2157};
2158
2159static unsigned int channels_2_8[] = {
2160 2, 8
2161};
2162
2163static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2164 .count = ARRAY_SIZE(channels_2_6_8),
2165 .list = channels_2_6_8,
2166 .mask = 0,
2167};
2168
2169static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2170 .count = ARRAY_SIZE(channels_2_8),
2171 .list = channels_2_8,
2172 .mask = 0,
2173};
2174
84eb01be
TI		 2175static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2176 struct hda_codec *codec,
2177 struct snd_pcm_substream *substream)
2178{
2179 struct hdmi_spec *spec = codec->spec;
393004b2
ND		 2180 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2181
2182 switch (codec->preset->id) {
2183 case 0x10de0002:
2184 case 0x10de0003:
2185 case 0x10de0005:
2186 case 0x10de0006:
2187 hw_constraints_channels = &hw_constraints_2_8_channels;
2188 break;
2189 case 0x10de0007:
2190 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2191 break;
2192 default:
2193 break;
2194 }
2195
2196 if (hw_constraints_channels != NULL) {
2197 snd_pcm_hw_constraint_list(substream->runtime, 0,
2198 SNDRV_PCM_HW_PARAM_CHANNELS,
2199 hw_constraints_channels);
ad09fc9d
TI		 2200 } else {
2201 snd_pcm_hw_constraint_step(substream->runtime, 0,
2202 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
393004b2
ND		 2203 }
2204
84eb01be
TI		 2205 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2206}
2207
2208static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2209 struct hda_codec *codec,
2210 struct snd_pcm_substream *substream)
2211{
2212 struct hdmi_spec *spec = codec->spec;
2213 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2214}
2215
2216static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2217 struct hda_codec *codec,
2218 unsigned int stream_tag,
2219 unsigned int format,
2220 struct snd_pcm_substream *substream)
2221{
2222 struct hdmi_spec *spec = codec->spec;
2223 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2224 stream_tag, format, substream);
2225}
2226
d0b1252d
TI		 2227static const struct hda_pcm_stream simple_pcm_playback = {
2228 .substreams = 1,
2229 .channels_min = 2,
2230 .channels_max = 2,
2231 .ops = {
2232 .open = simple_playback_pcm_open,
2233 .close = simple_playback_pcm_close,
2234 .prepare = simple_playback_pcm_prepare
2235 },
2236};
2237
2238static const struct hda_codec_ops simple_hdmi_patch_ops = {
2239 .build_controls = simple_playback_build_controls,
2240 .build_pcms = simple_playback_build_pcms,
2241 .init = simple_playback_init,
2242 .free = simple_playback_free,
250e41ac 2243 .unsol_event = simple_hdmi_unsol_event,
d0b1252d
TI		 2244};
2245
2246static int patch_simple_hdmi(struct hda_codec *codec,
2247 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2248{
2249 struct hdmi_spec *spec;
bce0d2a8
TI		 2250 struct hdmi_spec_per_cvt *per_cvt;
2251 struct hdmi_spec_per_pin *per_pin;
d0b1252d
TI		 2252
2253 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2254 if (!spec)
2255 return -ENOMEM;
2256
2257 codec->spec = spec;
bce0d2a8 2258 hdmi_array_init(spec, 1);
d0b1252d
TI		 2259
2260 spec->multiout.num_dacs = 0; /* no analog */
2261 spec->multiout.max_channels = 2;
2262 spec->multiout.dig_out_nid = cvt_nid;
2263 spec->num_cvts = 1;
2264 spec->num_pins = 1;
bce0d2a8
TI		 2265 per_pin = snd_array_new(&spec->pins);
2266 per_cvt = snd_array_new(&spec->cvts);
2267 if (!per_pin || !per_cvt) {
2268 simple_playback_free(codec);
2269 return -ENOMEM;
2270 }
2271 per_cvt->cvt_nid = cvt_nid;
2272 per_pin->pin_nid = pin_nid;
d0b1252d
TI		 2273 spec->pcm_playback = simple_pcm_playback;
2274
2275 codec->patch_ops = simple_hdmi_patch_ops;
2276
2277 return 0;
2278}
2279
1f348522
AP		 2280static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2281 int channels)
2282{
2283 unsigned int chanmask;
2284 int chan = channels ? (channels - 1) : 1;
2285
2286 switch (channels) {
2287 default:
2288 case 0:
2289 case 2:
2290 chanmask = 0x00;
2291 break;
2292 case 4:
2293 chanmask = 0x08;
2294 break;
2295 case 6:
2296 chanmask = 0x0b;
2297 break;
2298 case 8:
2299 chanmask = 0x13;
2300 break;
2301 }
2302
2303 /* Set the audio infoframe channel allocation and checksum fields. The
2304 * channel count is computed implicitly by the hardware. */
2305 snd_hda_codec_write(codec, 0x1, 0,
2306 Nv_VERB_SET_Channel_Allocation, chanmask);
2307
2308 snd_hda_codec_write(codec, 0x1, 0,
2309 Nv_VERB_SET_Info_Frame_Checksum,
2310 (0x71 - chan - chanmask));
2311}
2312
84eb01be
TI		 2313static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2314 struct hda_codec *codec,
2315 struct snd_pcm_substream *substream)
2316{
2317 struct hdmi_spec *spec = codec->spec;
2318 int i;
2319
2320 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2321 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2322 for (i = 0; i < 4; i++) {
2323 /* set the stream id */
2324 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2325 AC_VERB_SET_CHANNEL_STREAMID, 0);
2326 /* set the stream format */
2327 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2328 AC_VERB_SET_STREAM_FORMAT, 0);
2329 }
2330
1f348522
AP		 2331 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2332 * streams are disabled. */
2333 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2334
84eb01be
TI		 2335 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2336}
2337
2338static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2339 struct hda_codec *codec,
2340 unsigned int stream_tag,
2341 unsigned int format,
2342 struct snd_pcm_substream *substream)
2343{
2344 int chs;
112daa7a 2345 unsigned int dataDCC2, channel_id;
84eb01be 2346 int i;
7c935976 2347 struct hdmi_spec *spec = codec->spec;
e3245cdd 2348 struct hda_spdif_out *spdif;
bce0d2a8 2349 struct hdmi_spec_per_cvt *per_cvt;
84eb01be
TI		 2350
2351 mutex_lock(&codec->spdif_mutex);
bce0d2a8
TI		 2352 per_cvt = get_cvt(spec, 0);
2353 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
84eb01be
TI		 2354
2355 chs = substream->runtime->channels;
84eb01be 2356
84eb01be
TI		 2357 dataDCC2 = 0x2;
2358
84eb01be 2359 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
7c935976 2360 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2361 snd_hda_codec_write(codec,
2362 nvhdmi_master_con_nid_7x,
2363 0,
2364 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2365 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2366
2367 /* set the stream id */
2368 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2369 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2370
2371 /* set the stream format */
2372 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2373 AC_VERB_SET_STREAM_FORMAT, format);
2374
2375 /* turn on again (if needed) */
2376 /* enable and set the channel status audio/data flag */
7c935976 2377 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2378 snd_hda_codec_write(codec,
2379 nvhdmi_master_con_nid_7x,
2380 0,
2381 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2382 spdif->ctls & 0xff);
84eb01be
TI		 2383 snd_hda_codec_write(codec,
2384 nvhdmi_master_con_nid_7x,
2385 0,
2386 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2387 }
2388
2389 for (i = 0; i < 4; i++) {
2390 if (chs == 2)
2391 channel_id = 0;
2392 else
2393 channel_id = i * 2;
2394
2395 /* turn off SPDIF once;
2396 *otherwise the IEC958 bits won't be updated
2397 */
2398 if (codec->spdif_status_reset &&
7c935976 2399 (spdif->ctls & AC_DIG1_ENABLE))
84eb01be
TI		 2400 snd_hda_codec_write(codec,
2401 nvhdmi_con_nids_7x[i],
2402 0,
2403 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2404 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
84eb01be
TI		 2405 /* set the stream id */
2406 snd_hda_codec_write(codec,
2407 nvhdmi_con_nids_7x[i],
2408 0,
2409 AC_VERB_SET_CHANNEL_STREAMID,
2410 (stream_tag << 4) | channel_id);
2411 /* set the stream format */
2412 snd_hda_codec_write(codec,
2413 nvhdmi_con_nids_7x[i],
2414 0,
2415 AC_VERB_SET_STREAM_FORMAT,
2416 format);
2417 /* turn on again (if needed) */
2418 /* enable and set the channel status audio/data flag */
2419 if (codec->spdif_status_reset &&
7c935976 2420 (spdif->ctls & AC_DIG1_ENABLE)) {
84eb01be
TI		 2421 snd_hda_codec_write(codec,
2422 nvhdmi_con_nids_7x[i],
2423 0,
2424 AC_VERB_SET_DIGI_CONVERT_1,
7c935976 2425 spdif->ctls & 0xff);
84eb01be
TI		 2426 snd_hda_codec_write(codec,
2427 nvhdmi_con_nids_7x[i],
2428 0,
2429 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2430 }
2431 }
2432
1f348522 2433 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
84eb01be
TI		 2434
2435 mutex_unlock(&codec->spdif_mutex);
2436 return 0;
2437}
2438
fb79e1e0 2439static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
84eb01be
TI		 2440 .substreams = 1,
2441 .channels_min = 2,
2442 .channels_max = 8,
2443 .nid = nvhdmi_master_con_nid_7x,
2444 .rates = SUPPORTED_RATES,
2445 .maxbps = SUPPORTED_MAXBPS,
2446 .formats = SUPPORTED_FORMATS,
2447 .ops = {
2448 .open = simple_playback_pcm_open,
2449 .close = nvhdmi_8ch_7x_pcm_close,
2450 .prepare = nvhdmi_8ch_7x_pcm_prepare
2451 },
2452};
2453
84eb01be
TI		 2454static int patch_nvhdmi_2ch(struct hda_codec *codec)
2455{
2456 struct hdmi_spec *spec;
d0b1252d
TI		 2457 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2458 nvhdmi_master_pin_nid_7x);
2459 if (err < 0)
2460 return err;
84eb01be 2461
ceaa86ba 2462 codec->patch_ops.init = nvhdmi_7x_init_2ch;
d0b1252d
TI		 2463 /* override the PCM rates, etc, as the codec doesn't give full list */
2464 spec = codec->spec;
2465 spec->pcm_playback.rates = SUPPORTED_RATES;
2466 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2467 spec->pcm_playback.formats = SUPPORTED_FORMATS;
84eb01be
TI		 2468 return 0;
2469}
2470
53775b0d
TI		 2471static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2472{
2473 struct hdmi_spec *spec = codec->spec;
2474 int err = simple_playback_build_pcms(codec);
bce0d2a8
TI		 2475 if (!err) {
2476 struct hda_pcm *info = get_pcm_rec(spec, 0);
2477 info->own_chmap = true;
2478 }
53775b0d
TI		 2479 return err;
2480}
2481
2482static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2483{
2484 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2485 struct hda_pcm *info;
53775b0d
TI		 2486 struct snd_pcm_chmap *chmap;
2487 int err;
2488
2489 err = simple_playback_build_controls(codec);
2490 if (err < 0)
2491 return err;
2492
2493 /* add channel maps */
bce0d2a8
TI		 2494 info = get_pcm_rec(spec, 0);
2495 err = snd_pcm_add_chmap_ctls(info->pcm,
53775b0d
TI		 2496 SNDRV_PCM_STREAM_PLAYBACK,
2497 snd_pcm_alt_chmaps, 8, 0, &chmap);
2498 if (err < 0)
2499 return err;
2500 switch (codec->preset->id) {
2501 case 0x10de0002:
2502 case 0x10de0003:
2503 case 0x10de0005:
2504 case 0x10de0006:
2505 chmap->channel_mask = (1U << 2) | (1U << 8);
2506 break;
2507 case 0x10de0007:
2508 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
2509 }
2510 return 0;
2511}
2512
84eb01be
TI		 2513static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
2514{
2515 struct hdmi_spec *spec;
2516 int err = patch_nvhdmi_2ch(codec);
84eb01be
TI		 2517 if (err < 0)
2518 return err;
2519 spec = codec->spec;
2520 spec->multiout.max_channels = 8;
d0b1252d 2521 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
ceaa86ba 2522 codec->patch_ops.init = nvhdmi_7x_init_8ch;
53775b0d
TI		 2523 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
2524 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
1f348522
AP		 2525
2526 /* Initialize the audio infoframe channel mask and checksum to something
2527 * valid */
2528 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2529
84eb01be
TI		 2530 return 0;
2531}
2532
2533/*
2534 * ATI-specific implementations
2535 *
2536 * FIXME: we may omit the whole this and use the generic code once after
2537 * it's confirmed to work.
2538 */
2539
2540#define ATIHDMI_CVT_NID 0x02 /* audio converter */
2541#define ATIHDMI_PIN_NID 0x03 /* HDMI output pin */
2542
2543static int atihdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2544 struct hda_codec *codec,
2545 unsigned int stream_tag,
2546 unsigned int format,
2547 struct snd_pcm_substream *substream)
2548{
2549 struct hdmi_spec *spec = codec->spec;
bce0d2a8 2550 struct hdmi_spec_per_cvt *per_cvt = get_cvt(spec, 0);
84eb01be
TI		 2551 int chans = substream->runtime->channels;
2552 int i, err;
2553
2554 err = simple_playback_pcm_prepare(hinfo, codec, stream_tag, format,
2555 substream);
2556 if (err < 0)
2557 return err;
bce0d2a8 2558 snd_hda_codec_write(codec, per_cvt->cvt_nid, 0,
384a48d7 2559 AC_VERB_SET_CVT_CHAN_COUNT, chans - 1);
84eb01be
TI		 2560 /* FIXME: XXX */
2561 for (i = 0; i < chans; i++) {
bce0d2a8 2562 snd_hda_codec_write(codec, per_cvt->cvt_nid, 0,
84eb01be
TI		 2563 AC_VERB_SET_HDMI_CHAN_SLOT,
2564 (i << 4) | i);
2565 }
2566 return 0;
2567}
2568
84eb01be
TI		 2569static int patch_atihdmi(struct hda_codec *codec)
2570{
2571 struct hdmi_spec *spec;
d0b1252d
TI		 2572 int err = patch_simple_hdmi(codec, ATIHDMI_CVT_NID, ATIHDMI_PIN_NID);
2573 if (err < 0)
2574 return err;
2575 spec = codec->spec;
2576 spec->pcm_playback.ops.prepare = atihdmi_playback_pcm_prepare;
84eb01be
TI		 2577 return 0;
2578}
2579
3de5ff88
AL		 2580/* VIA HDMI Implementation */
2581#define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
2582#define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
2583
3de5ff88
AL		 2584static int patch_via_hdmi(struct hda_codec *codec)
2585{
250e41ac 2586 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3de5ff88 2587}
84eb01be
TI		 2588
2589/*
2590 * patch entries
2591 */
fb79e1e0 2592static const struct hda_codec_preset snd_hda_preset_hdmi[] = {
84eb01be
TI		 2593{ .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi },
2594{ .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi },
2595{ .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi },
36e9c135 2596{ .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 2597{ .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi },
2598{ .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi },
2599{ .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi },
2600{ .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2601{ .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2602{ .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2603{ .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
2604{ .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x },
5d44f927
SW		 2605{ .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_generic_hdmi },
2606{ .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_generic_hdmi },
2607{ .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_generic_hdmi },
2608{ .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_generic_hdmi },
2609{ .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_generic_hdmi },
2610{ .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_generic_hdmi },
2611{ .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_generic_hdmi },
2612{ .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_generic_hdmi },
2613{ .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_generic_hdmi },
2614{ .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_generic_hdmi },
2615{ .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_generic_hdmi },
c8900a0f 2616/* 17 is known to be absent */
5d44f927
SW		 2617{ .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_generic_hdmi },
2618{ .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_generic_hdmi },
2619{ .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_generic_hdmi },
2620{ .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_generic_hdmi },
2621{ .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_generic_hdmi },
2622{ .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_generic_hdmi },
2623{ .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_generic_hdmi },
2624{ .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_generic_hdmi },
2625{ .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_generic_hdmi },
2626{ .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_generic_hdmi },
7ae48b56 2627{ .id = 0x10de0051, .name = "GPU 51 HDMI/DP", .patch = patch_generic_hdmi },
d52392b1 2628{ .id = 0x10de0060, .name = "GPU 60 HDMI/DP", .patch = patch_generic_hdmi },
84eb01be
TI		 2629{ .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
2630{ .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
3de5ff88
AL		 2631{ .id = 0x11069f80, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
2632{ .id = 0x11069f81, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
2633{ .id = 0x11069f84, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
2634{ .id = 0x11069f85, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
84eb01be
TI		 2635{ .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
2636{ .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi },
2637{ .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi },
2638{ .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi },
2639{ .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
2640{ .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
591e610d 2641{ .id = 0x80862806, .name = "PantherPoint HDMI", .patch = patch_generic_hdmi },
1c76684d 2642{ .id = 0x80862807, .name = "Haswell HDMI", .patch = patch_generic_hdmi },
6edc59e6 2643{ .id = 0x80862880, .name = "CedarTrail HDMI", .patch = patch_generic_hdmi },
84eb01be
TI		 2644{ .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
2645{} /* terminator */
2646};
2647
2648MODULE_ALIAS("snd-hda-codec-id:1002793c");
2649MODULE_ALIAS("snd-hda-codec-id:10027919");
2650MODULE_ALIAS("snd-hda-codec-id:1002791a");
2651MODULE_ALIAS("snd-hda-codec-id:1002aa01");
2652MODULE_ALIAS("snd-hda-codec-id:10951390");
2653MODULE_ALIAS("snd-hda-codec-id:10951392");
2654MODULE_ALIAS("snd-hda-codec-id:10de0002");
2655MODULE_ALIAS("snd-hda-codec-id:10de0003");
2656MODULE_ALIAS("snd-hda-codec-id:10de0005");
2657MODULE_ALIAS("snd-hda-codec-id:10de0006");
2658MODULE_ALIAS("snd-hda-codec-id:10de0007");
2659MODULE_ALIAS("snd-hda-codec-id:10de000a");
2660MODULE_ALIAS("snd-hda-codec-id:10de000b");
2661MODULE_ALIAS("snd-hda-codec-id:10de000c");
2662MODULE_ALIAS("snd-hda-codec-id:10de000d");
2663MODULE_ALIAS("snd-hda-codec-id:10de0010");
2664MODULE_ALIAS("snd-hda-codec-id:10de0011");
2665MODULE_ALIAS("snd-hda-codec-id:10de0012");
2666MODULE_ALIAS("snd-hda-codec-id:10de0013");
2667MODULE_ALIAS("snd-hda-codec-id:10de0014");
c8900a0f
RS		 2668MODULE_ALIAS("snd-hda-codec-id:10de0015");
2669MODULE_ALIAS("snd-hda-codec-id:10de0016");
84eb01be
TI		 2670MODULE_ALIAS("snd-hda-codec-id:10de0018");
2671MODULE_ALIAS("snd-hda-codec-id:10de0019");
2672MODULE_ALIAS("snd-hda-codec-id:10de001a");
2673MODULE_ALIAS("snd-hda-codec-id:10de001b");
2674MODULE_ALIAS("snd-hda-codec-id:10de001c");
2675MODULE_ALIAS("snd-hda-codec-id:10de0040");
2676MODULE_ALIAS("snd-hda-codec-id:10de0041");
2677MODULE_ALIAS("snd-hda-codec-id:10de0042");
2678MODULE_ALIAS("snd-hda-codec-id:10de0043");
2679MODULE_ALIAS("snd-hda-codec-id:10de0044");
7ae48b56 2680MODULE_ALIAS("snd-hda-codec-id:10de0051");
d52392b1 2681MODULE_ALIAS("snd-hda-codec-id:10de0060");
84eb01be
TI		 2682MODULE_ALIAS("snd-hda-codec-id:10de0067");
2683MODULE_ALIAS("snd-hda-codec-id:10de8001");
3de5ff88
AL		 2684MODULE_ALIAS("snd-hda-codec-id:11069f80");
2685MODULE_ALIAS("snd-hda-codec-id:11069f81");
2686MODULE_ALIAS("snd-hda-codec-id:11069f84");
2687MODULE_ALIAS("snd-hda-codec-id:11069f85");
84eb01be
TI		 2688MODULE_ALIAS("snd-hda-codec-id:17e80047");
2689MODULE_ALIAS("snd-hda-codec-id:80860054");
2690MODULE_ALIAS("snd-hda-codec-id:80862801");
2691MODULE_ALIAS("snd-hda-codec-id:80862802");
2692MODULE_ALIAS("snd-hda-codec-id:80862803");
2693MODULE_ALIAS("snd-hda-codec-id:80862804");
2694MODULE_ALIAS("snd-hda-codec-id:80862805");
591e610d 2695MODULE_ALIAS("snd-hda-codec-id:80862806");
1c76684d 2696MODULE_ALIAS("snd-hda-codec-id:80862807");
6edc59e6 2697MODULE_ALIAS("snd-hda-codec-id:80862880");
84eb01be
TI		 2698MODULE_ALIAS("snd-hda-codec-id:808629fb");
2699
2700MODULE_LICENSE("GPL");
2701MODULE_DESCRIPTION("HDMI HD-audio codec");
2702MODULE_ALIAS("snd-hda-codec-intelhdmi");
2703MODULE_ALIAS("snd-hda-codec-nvhdmi");
2704MODULE_ALIAS("snd-hda-codec-atihdmi");
2705
2706static struct hda_codec_preset_list intel_list = {
2707 .preset = snd_hda_preset_hdmi,
2708 .owner = THIS_MODULE,
2709};
2710
2711static int __init patch_hdmi_init(void)
2712{
2713 return snd_hda_add_codec_preset(&intel_list);
2714}
2715
2716static void __exit patch_hdmi_exit(void)
2717{
2718 snd_hda_delete_codec_preset(&intel_list);
2719}
2720
2721module_init(patch_hdmi_init)
2722module_exit(patch_hdmi_exit)
Linux 6.x block layer and io_uring tree(s)